Skip to content
Snippets Groups Projects
Commit 55314038 authored by Reinier van der Walle's avatar Reinier van der Walle
Browse files

updated mmap gold files

parent 50f0a50d
Branches
No related tags found
1 merge request!251Resolve L2SDP-721
Pipeline #29895 passed
Stage: simulation
Stage: synthesis
Show whitespace changes
Inline Side-by-side
Showing
with 584 additions and 584 deletions
applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
+ 3
− 3
View file @ 55314038
...@@ -34,7 +34,7 @@ number_of_columns = 13 ...@@ -34,7 +34,7 @@ number_of_columns = 13
- - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - - - - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - -
- - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - - - - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - -
- - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - - - - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - -
- - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0] - - - - - - design_note 0x00008014 48 RO char8 b[31:0] b[7:0] - -
REG_WDI 1 1 REG wdi_override 0x00010000 1 WO uint32 b[31:0] - - - REG_WDI 1 1 REG wdi_override 0x00010000 1 WO uint32 b[31:0] - - -
REG_FPGA_TEMP_SENS 1 1 REG temp 0x00018000 1 RO uint32 b[31:0] - - - REG_FPGA_TEMP_SENS 1 1 REG temp 0x00018000 1 RO uint32 b[31:0] - - -
REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00018000 6 RO uint32 b[31:0] - - - REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00018000 6 RO uint32 b[31:0] - - -
...@@ -542,7 +542,7 @@ number_of_columns = 13 ...@@ -542,7 +542,7 @@ number_of_columns = 13
- - - - latency 0x001a8008 1 RO uint32 b[31:0] - - - - - - - latency 0x001a8008 1 RO uint32 b[31:0] - - -
REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x001b0000 1 RO uint32 b[0:0] - 1 2 REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x001b0000 1 RO uint32 b[0:0] - 1 2
- - - - transport_nof_hops 0x001b0001 1 RW uint32 b[31:0] - - - - - - - transport_nof_hops 0x001b0001 1 RW uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_RX_BF 2 16 REG xon_stable 0x001b8000 1 RO uint32 b[0:0] - 1 8 REG_BSN_MONITOR_V2_RING_RX_BF 2 1 REG xon_stable 0x001b8000 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x001b8000 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x001b8000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x001b8000 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x001b8000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x001b8001 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x001b8001 1 RO uint64 b[31:0] b[31:0] - -
...@@ -551,7 +551,7 @@ number_of_columns = 13 ...@@ -551,7 +551,7 @@ number_of_columns = 13
- - - - nof_valid 0x001b8004 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x001b8004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x001b8005 1 RO uint32 b[31:0] - - - - - - - nof_err 0x001b8005 1 RO uint32 b[31:0] - - -
- - - - latency 0x001b8008 1 RO uint32 b[31:0] - - - - - - - latency 0x001b8008 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_TX_BF 2 16 REG xon_stable 0x001c0000 1 RO uint32 b[0:0] - 1 8 REG_BSN_MONITOR_V2_RING_TX_BF 2 1 REG xon_stable 0x001c0000 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x001c0000 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x001c0000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x001c0000 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x001c0000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x001c0001 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x001c0001 1 RO uint64 b[31:0] b[31:0] - -
......
applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
+ 289
− 289
View file @ 55314038
...@@ -34,53 +34,53 @@ number_of_columns = 13 ...@@ -34,53 +34,53 @@ number_of_columns = 13
- - - - stamp_date 0x0000000f 1 RO uint32 b[31:0] - - - - - - - stamp_date 0x0000000f 1 RO uint32 b[31:0] - - -
- - - - stamp_time 0x00000010 1 RO uint32 b[31:0] - - - - - - - stamp_time 0x00000010 1 RO uint32 b[31:0] - - -
- - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - - - - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - -
- - - - design_note 0x00000014 52 RO char8 b[31:0] b[7:0] - - - - - - design_note 0x00000014 48 RO char8 b[31:0] b[7:0] - -
REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - - REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - -
REG_FPGA_TEMP_SENS 1 1 REG temp 0x00043498 1 RO uint32 b[31:0] - - - REG_FPGA_TEMP_SENS 1 1 REG temp 0x000432b8 1 RO uint32 b[31:0] - - -
REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00043450 6 RO uint32 b[31:0] - - - REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00043270 6 RO uint32 b[31:0] - - -
RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - - RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - -
AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - - AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - -
AVS_ETH_0_REG 1 1 REG status 0x000433e0 12 RO uint32 b[31:0] - - - AVS_ETH_0_REG 1 1 REG status 0x00000c10 12 RO uint32 b[31:0] - - -
AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - - AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - -
PIO_PPS 1 1 REG capture_cnt 0x000434c8 1 RO uint32 b[29:0] - - - PIO_PPS 1 1 REG capture_cnt 0x000432e8 1 RO uint32 b[29:0] - - -
- - - - stable 0x000434c8 1 RO uint32 b[30:30] - - - - - - - stable 0x000432e8 1 RO uint32 b[30:30] - - -
- - - - toggle 0x000434c8 1 RO uint32 b[31:31] - - - - - - - toggle 0x000432e8 1 RO uint32 b[31:31] - - -
- - - - expected_cnt 0x000434c9 1 RW uint32 b[27:0] - - - - - - - expected_cnt 0x000432e9 1 RW uint32 b[27:0] - - -
- - - - edge 0x000434c9 1 RW uint32 b[31:31] - - - - - - - edge 0x000432e9 1 RW uint32 b[31:31] - - -
- - - - offset_cnt 0x000434ca 1 RO uint32 b[27:0] - - - - - - - offset_cnt 0x000432ea 1 RO uint32 b[27:0] - - -
REG_EPCS 1 1 REG addr 0x000434a0 1 WO uint32 b[31:0] - - - REG_EPCS 1 1 REG addr 0x000432c0 1 WO uint32 b[31:0] - - -
- - - - rden 0x000434a1 1 WO uint32 b[0:0] - - - - - - - rden 0x000432c1 1 WO uint32 b[0:0] - - -
- - - - read_bit 0x000434a2 1 WO uint32 b[0:0] - - - - - - - read_bit 0x000432c2 1 WO uint32 b[0:0] - - -
- - - - write_bit 0x000434a3 1 WO uint32 b[0:0] - - - - - - - write_bit 0x000432c3 1 WO uint32 b[0:0] - - -
- - - - sector_erase 0x000434a4 1 WO uint32 b[0:0] - - - - - - - sector_erase 0x000432c4 1 WO uint32 b[0:0] - - -
- - - - busy 0x000434a5 1 RO uint32 b[0:0] - - - - - - - busy 0x000432c5 1 RO uint32 b[0:0] - - -
- - - - unprotect 0x000434a6 1 WO uint32 b[31:0] - - - - - - - unprotect 0x000432c6 1 WO uint32 b[31:0] - - -
REG_DPMM_CTRL 1 1 REG rd_usedw 0x000434e2 1 RO uint32 b[31:0] - - - REG_DPMM_CTRL 1 1 REG rd_usedw 0x00043302 1 RO uint32 b[31:0] - - -
REG_DPMM_DATA 1 1 FIFO data 0x000434e0 1 RO uint32 b[31:0] - - - REG_DPMM_DATA 1 1 FIFO data 0x00043300 1 RO uint32 b[31:0] - - -
REG_MMDP_CTRL 1 1 REG wr_usedw 0x000434de 1 RO uint32 b[31:0] - - - REG_MMDP_CTRL 1 1 REG wr_usedw 0x000432fe 1 RO uint32 b[31:0] - - -
- - - - wr_availw 0x000434df 1 RO uint32 b[31:0] - - - - - - - wr_availw 0x000432ff 1 RO uint32 b[31:0] - - -
REG_MMDP_DATA 1 1 FIFO data 0x000434dc 1 WO uint32 b[31:0] - - - REG_MMDP_DATA 1 1 FIFO data 0x000432fc 1 WO uint32 b[31:0] - - -
REG_REMU 1 1 REG reconfigure 0x000434a8 1 WO uint32 b[31:0] - - - REG_REMU 1 1 REG reconfigure 0x000432c8 1 WO uint32 b[31:0] - - -
- - - - param 0x000434a9 1 WO uint32 b[2:0] - - - - - - - param 0x000432c9 1 WO uint32 b[2:0] - - -
- - - - read_param 0x000434aa 1 WO uint32 b[0:0] - - - - - - - read_param 0x000432ca 1 WO uint32 b[0:0] - - -
- - - - write_param 0x000434ab 1 WO uint32 b[0:0] - - - - - - - write_param 0x000432cb 1 WO uint32 b[0:0] - - -
- - - - data_out 0x000434ac 1 RO uint32 b[31:0] - - - - - - - data_out 0x000432cc 1 RO uint32 b[31:0] - - -
- - - - data_in 0x000434ad 1 WO uint32 b[31:0] - - - - - - - data_in 0x000432cd 1 WO uint32 b[31:0] - - -
- - - - busy 0x000434ae 1 RO uint32 b[0:0] - - - - - - - busy 0x000432ce 1 RO uint32 b[0:0] - - -
REG_SDP_INFO 1 1 REG block_period 0x00043440 1 RO uint32 b[15:0] - - - REG_SDP_INFO 1 1 REG block_period 0x00043260 1 RO uint32 b[15:0] - - -
- - - - beam_repositioning_flag 0x00043441 1 RW uint32 b[0:0] - - - - - - - beam_repositioning_flag 0x00043261 1 RW uint32 b[0:0] - - -
- - - - fsub_type 0x00043442 1 RO uint32 b[0:0] - - - - - - - fsub_type 0x00043262 1 RO uint32 b[0:0] - - -
- - - - f_adc 0x00043443 1 RO uint32 b[0:0] - - - - - - - f_adc 0x00043263 1 RO uint32 b[0:0] - - -
- - - - nyquist_zone_index 0x00043444 1 RW uint32 b[1:0] - - - - - - - nyquist_zone_index 0x00043264 1 RW uint32 b[1:0] - - -
- - - - observation_id 0x00043445 1 RW uint32 b[31:0] - - - - - - - observation_id 0x00043265 1 RW uint32 b[31:0] - - -
- - - - antenna_band_index 0x00043446 1 RW uint32 b[0:0] - - - - - - - antenna_band_index 0x00043266 1 RW uint32 b[0:0] - - -
- - - - station_id 0x00043447 1 RW uint32 b[15:0] - - - - - - - station_id 0x00043267 1 RW uint32 b[15:0] - - -
REG_RING_INFO 1 1 REG use_cable_to_previous_rn 0x000434b4 1 RW uint32 b[0:0] - - - REG_RING_INFO 1 1 REG use_cable_to_previous_rn 0x000432d4 1 RW uint32 b[0:0] - - -
- - - - use_cable_to_next_rn 0x000434b5 1 RW uint32 b[0:0] - - - - - - - use_cable_to_next_rn 0x000432d5 1 RW uint32 b[0:0] - - -
- - - - n_rn 0x000434b6 1 RW uint32 b[7:0] - - - - - - - n_rn 0x000432d6 1 RW uint32 b[7:0] - - -
- - - - o_rn 0x000434b7 1 RW uint32 b[7:0] - - - - - - - o_rn 0x000432d7 1 RW uint32 b[7:0] - - -
PIO_JESD_CTRL 1 1 REG enable 0x000434d2 1 RW uint32 b[30:0] - - - PIO_JESD_CTRL 1 1 REG enable 0x000432f2 1 RW uint32 b[30:0] - - -
- - - - reset 0x000434d2 1 RW uint32 b[31:31] - - - - - - - reset 0x000432f2 1 RW uint32 b[31:31] - - -
JESD204B 1 12 REG rx_lane_ctrl_common 0x00042000 1 RW uint32 b[2:0] - - 256 JESD204B 1 12 REG rx_lane_ctrl_common 0x00042000 1 RW uint32 b[2:0] - - 256
- - - - rx_lane_ctrl_0 0x00042001 1 RW uint32 b[2:0] - - - - - - - rx_lane_ctrl_0 0x00042001 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_1 0x00042002 1 RW uint32 b[2:0] - - - - - - - rx_lane_ctrl_1 0x00042002 1 RW uint32 b[2:0] - - -
...@@ -118,47 +118,47 @@ number_of_columns = 13 ...@@ -118,47 +118,47 @@ number_of_columns = 13
- - - - rx_status5 0x0004203d 1 RW uint32 b[15:0] - - - - - - - rx_status5 0x0004203d 1 RW uint32 b[15:0] - - -
- - - - rx_status6 0x0004203e 1 RW uint32 b[23:0] - - - - - - - rx_status6 0x0004203e 1 RW uint32 b[23:0] - - -
- - - - rx_status7 0x0004203f 1 RO uint32 b[31:0] - - - - - - - rx_status7 0x0004203f 1 RO uint32 b[31:0] - - -
REG_DP_SHIFTRAM 1 12 REG shift 0x000433c0 1 RW uint32 b[11:0] - - 2 REG_DP_SHIFTRAM 1 12 REG shift 0x000431c0 1 RW uint32 b[11:0] - - 2
REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00043490 1 RW uint32 b[0:0] - - - REG_BSN_SOURCE_V2 1 1 REG dp_on 0x000432b0 1 RW uint32 b[0:0] - - -
- - - - dp_on_pps 0x00043490 1 RW uint32 b[1:1] - - - - - - - dp_on_pps 0x000432b0 1 RW uint32 b[1:1] - - -
- - - - nof_clk_per_sync 0x00043491 1 RW uint32 b[31:0] - - - - - - - nof_clk_per_sync 0x000432b1 1 RW uint32 b[31:0] - - -
- - - - bsn_init 0x00043492 1 RW uint64 b[31:0] b[31:0] - - - - - - bsn_init 0x000432b2 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00043493 - - - b[31:0] b[63:32] - - - - - - - 0x000432b3 - - - b[31:0] b[63:32] - -
- - - - bsn_time_offset 0x00043494 1 RW uint32 b[9:0] - - - - - - - bsn_time_offset 0x000432b4 1 RW uint32 b[9:0] - - -
REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x000434d8 1 RW uint64 b[31:0] b[31:0] - - REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x000432f8 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x000434d9 - - - b[31:0] b[63:32] - - - - - - - 0x000432f9 - - - b[31:0] b[63:32] - -
REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00043000 1 RO uint32 b[0:0] - - - REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x00043000 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00043000 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00043001 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00043002 - - - b[31:0] b[63:32] - - - - - - - 0x00000102 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00043003 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00043004 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00043005 1 RO uint32 b[31:0] - - - - - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - -
- - - - bsn_first 0x00043006 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_first 0x00000106 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00043007 - - - b[31:0] b[63:32] - - - - - - - 0x00000107 - - - b[31:0] b[63:32] - -
- - - - bsn_first_cycle_cnt 0x00043008 1 RO uint32 b[31:0] - - - - - - - bsn_first_cycle_cnt 0x00000108 1 RO uint32 b[31:0] - - -
REG_WG 1 12 REG mode 0x00043280 1 RW uint32 b[7:0] - - 4 REG_WG 1 12 REG mode 0x00043080 1 RW uint32 b[7:0] - - 4
- - - - nof_samples 0x00043280 1 RW uint32 b[31:16] - - - - - - - nof_samples 0x00043080 1 RW uint32 b[31:16] - - -
- - - - phase 0x00043281 1 RW uint32 b[15:0] - - - - - - - phase 0x00043081 1 RW uint32 b[15:0] - - -
- - - - freq 0x00043282 1 RW uint32 b[30:0] - - - - - - - freq 0x00043082 1 RW uint32 b[30:0] - - -
- - - - ampl 0x00043283 1 RW uint32 b[16:0] - - - - - - - ampl 0x00043083 1 RW uint32 b[16:0] - - -
RAM_WG 1 12 RAM data 0x00034000 1024 RW uint32 b[17:0] - - 1024 RAM_WG 1 12 RAM data 0x00034000 1024 RW uint32 b[17:0] - - 1024
RAM_ST_HISTOGRAM 1 12 RAM data 0x00002000 512 RW uint32 b[31:0] b[27:0] - 512 RAM_ST_HISTOGRAM 1 12 RAM data 0x00002000 512 RW uint32 b[31:0] b[27:0] - 512
REG_ADUH_MONITOR 1 12 REG mean_sum 0x000432c0 1 RO int64 b[31:0] b[31:0] - 4 REG_ADUH_MONITOR 1 12 REG mean_sum 0x000430c0 1 RO int64 b[31:0] b[31:0] - 4
- - - - - 0x000432c1 - - - b[31:0] b[63:32] - - - - - - - 0x000430c1 - - - b[31:0] b[63:32] - -
- - - - power_sum 0x000432c2 1 RO int64 b[31:0] b[31:0] - - - - - - power_sum 0x000430c2 1 RO int64 b[31:0] b[31:0] - -
- - - - - 0x000432c3 - - - b[31:0] b[63:32] - - - - - - - 0x000430c3 - - - b[31:0] b[63:32] - -
REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x000433a0 1 RO uint32 b[31:0] - - 2 REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x000431a0 1 RO uint32 b[31:0] - - 2
- - - - word_cnt 0x000433a1 1 RO uint32 b[31:0] - - - - - - - word_cnt 0x000431a1 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[31:0] b[15:0] - 1024 RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[31:0] b[15:0] - 1024
REG_SI 1 1 REG enable 0x000434da 1 RW uint32 b[0:0] - - - REG_SI 1 1 REG enable 0x000432fa 1 RW uint32 b[0:0] - - -
RAM_FIL_COEFS 1 16 RAM data 0x00038000 1024 RW uint32 b[15:0] - - 1024 RAM_FIL_COEFS 1 16 RAM data 0x00038000 1024 RW uint32 b[15:0] - - 1024
RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - - 1024 RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - - 1024
REG_DP_SELECTOR 1 1 REG input_select 0x000434d6 1 RW uint32 b[0:0] - - - REG_DP_SELECTOR 1 1 REG input_select 0x000432f6 1 RW uint32 b[0:0] - - -
RAM_ST_SST 1 6 RAM data 0x0003c000 1024 RW uint64 b[31:0] b[31:0] - 2048 RAM_ST_SST 1 6 RAM data 0x0003c000 1024 RW uint64 b[31:0] b[31:0] - 2048
- - - - - 0x0003c001 - - - b[21:0] b[53:32] - - - - - - - 0x0003c001 - - - b[21:0] b[53:32] - -
REG_STAT_ENABLE_SST 1 1 REG enable 0x000434d0 1 RW uint32 b[0:0] - - - REG_STAT_ENABLE_SST 1 1 REG enable 0x000432f0 1 RW uint32 b[0:0] - - -
REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c40 1 RW uint64 b[31:0] b[31:0] - - REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c40 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c41 - - - b[31:0] b[63:32] - - - - - - - 0x00000c41 - - - b[31:0] b[63:32] - -
- - - - sdp_block_period 0x00000c42 1 RW uint32 b[15:0] - - - - - - - sdp_block_period 0x00000c42 1 RW uint32 b[15:0] - - -
...@@ -205,36 +205,36 @@ number_of_columns = 13 ...@@ -205,36 +205,36 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00000c69 1 RW uint64 b[31:0] b[31:0] - - - - - - eth_destination_mac 0x00000c69 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c6a - - - b[15:0] b[47:32] - - - - - - - 0x00000c6a - - - b[15:0] b[47:32] - -
- - - - word_align 0x00000c6b 1 RW uint32 b[15:0] - - - - - - - word_align 0x00000c6b 1 RW uint32 b[15:0] - - -
REG_BSN_MONITOR_V2_SST_OFFLOAD 1 1 REG xon_stable 0x00043470 1 RO uint32 b[0:0] - - - REG_BSN_MONITOR_V2_SST_OFFLOAD 1 1 REG xon_stable 0x00043290 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x00043470 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x00043290 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00043470 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x00043290 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00043471 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x00043291 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00043472 - - - b[31:0] b[63:32] - - - - - - - 0x00043292 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00043473 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x00043293 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00043474 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x00043294 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00043475 1 RO uint32 b[31:0] - - - - - - - nof_err 0x00043295 1 RO uint32 b[31:0] - - -
- - - - latency 0x00043478 1 RO uint32 b[31:0] - - - - - - - latency 0x00043298 1 RO uint32 b[31:0] - - -
REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x00043420 1 RW uint32 b[0:0] - - - REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x00043240 1 RW uint32 b[0:0] - - -
- - - - ctrl_interval_size 0x00043421 1 RW uint32 b[30:0] - - - - - - - ctrl_interval_size 0x00043241 1 RW uint32 b[30:0] - - -
- - - - ctrl_start_bsn 0x00043422 1 RW uint64 b[31:0] b[31:0] - - - - - - ctrl_start_bsn 0x00043242 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00043423 - - - b[31:0] b[63:32] - - - - - - - 0x00043243 - - - b[31:0] b[63:32] - -
- - - - mon_current_input_bsn 0x00043424 1 RO uint64 b[31:0] b[31:0] - - - - - - mon_current_input_bsn 0x00043244 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00043425 - - - b[31:0] b[63:32] - - - - - - - 0x00043245 - - - b[31:0] b[63:32] - -
- - - - mon_input_bsn_at_sync 0x00043426 1 RO uint64 b[31:0] b[31:0] - - - - - - mon_input_bsn_at_sync 0x00043246 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00043427 - - - b[31:0] b[63:32] - - - - - - - 0x00043247 - - - b[31:0] b[63:32] - -
- - - - mon_output_enable 0x00043428 1 RO uint32 b[0:0] - - - - - - - mon_output_enable 0x00043248 1 RO uint32 b[0:0] - - -
- - - - mon_output_sync_bsn 0x00043429 1 RO uint64 b[31:0] b[31:0] - - - - - - mon_output_sync_bsn 0x00043249 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x0004342a - - - b[31:0] b[63:32] - - - - - - - 0x0004324a - - - b[31:0] b[63:32] - -
- - - - block_size 0x0004342b 1 RO uint32 b[31:0] - - - - - - - block_size 0x0004324b 1 RO uint32 b[31:0] - - -
RAM_ST_XSQ 1 9 RAM data 0x00010000 1008 RW cint64_ir b[31:0] b[31:0] - 4096 RAM_ST_XSQ 1 9 RAM data 0x00010000 1008 RW cint64_ir b[31:0] b[31:0] - 4096
- - - - - 0x00010001 - - - b[31:0] b[63:32] - - - - - - - 0x00010001 - - - b[31:0] b[63:32] - -
- - - - - 0x00010002 - - - b[31:0] b[95:64] - - - - - - - 0x00010002 - - - b[31:0] b[95:64] - -
- - - - - 0x00010003 - - - b[31:0] b[127:96] - - - - - - - 0x00010003 - - - b[31:0] b[127:96] - -
REG_CROSSLETS_INFO 1 1 REG offset 0x00043430 15 RW uint32 b[31:0] - - - REG_CROSSLETS_INFO 1 1 REG offset 0x00043250 15 RW uint32 b[31:0] - - -
- - - - step 0x0004343f 1 RW uint32 b[31:0] - - - - - - - step 0x0004325f 1 RW uint32 b[31:0] - - -
REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x000434cc 1 RW uint32 b[31:0] - - - REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x000432ec 1 RW uint32 b[31:0] - - -
- - - - unused 0x000434cd 1 RW uint32 b[31:0] - - - - - - - unused 0x000432ed 1 RW uint32 b[31:0] - - -
REG_STAT_ENABLE_XST 1 1 REG enable 0x000434ce 1 RW uint32 b[0:0] - - - REG_STAT_ENABLE_XST 1 1 REG enable 0x000432ee 1 RW uint32 b[0:0] - - -
REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00000040 1 RW uint64 b[31:0] b[31:0] - - REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00000040 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000041 - - - b[31:0] b[63:32] - - - - - - - 0x00000041 - - - b[31:0] b[63:32] - -
- - - - block_period 0x00000042 1 RW uint32 b[15:0] - - - - - - - block_period 0x00000042 1 RW uint32 b[15:0] - - -
...@@ -283,35 +283,35 @@ number_of_columns = 13 ...@@ -283,35 +283,35 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00000069 1 RW uint64 b[31:0] b[31:0] - - - - - - eth_destination_mac 0x00000069 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x0000006a - - - b[15:0] b[47:32] - - - - - - - 0x0000006a - - - b[15:0] b[47:32] - -
- - - - word_align 0x0000006b 1 RW uint32 b[15:0] - - - - - - - word_align 0x0000006b 1 RW uint32 b[15:0] - - -
REG_BSN_ALIGN_V2_XSUB 1 9 REG enable 0x00043380 1 RW uint32 b[0:0] - - 2 REG_BSN_ALIGN_V2_XSUB 1 9 REG enable 0x00043180 1 RW uint32 b[0:0] - - 2
- - - - replaced_pkt_cnt 0x00043381 1 RO uint32 b[31:0] - - - - - - - replaced_pkt_cnt 0x00043181 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RX_ALIGN_XSUB 1 9 REG xon_stable 0x00043100 1 RO uint32 b[0:0] - - 8 REG_BSN_MONITOR_V2_RX_ALIGN_XSUB 1 9 REG xon_stable 0x00000d00 1 RO uint32 b[0:0] - - 8
- - - - ready_stable 0x00043100 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x00000d00 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00043100 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x00000d00 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00043101 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x00000d01 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00043102 - - - b[31:0] b[63:32] - - - - - - - 0x00000d02 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00043103 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x00000d03 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00043104 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x00000d04 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00043105 1 RO uint32 b[31:0] - - - - - - - nof_err 0x00000d05 1 RO uint32 b[31:0] - - -
- - - - latency 0x00043108 1 RO uint32 b[31:0] - - - - - - - latency 0x00000d08 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_ALIGNED_XSUB 1 1 REG xon_stable 0x00043488 1 RO uint32 b[0:0] - - - REG_BSN_MONITOR_V2_ALIGNED_XSUB 1 1 REG xon_stable 0x000432a8 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x00043488 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x000432a8 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00043488 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x000432a8 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00043489 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x000432a9 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x0004348a - - - b[31:0] b[63:32] - - - - - - - 0x000432aa - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x0004348b 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x000432ab 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x0004348c 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x000432ac 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x0004348d 1 RO uint32 b[31:0] - - - - - - - nof_err 0x000432ad 1 RO uint32 b[31:0] - - -
- - - - latency 0x00043490 1 RO uint32 b[31:0] - - - - - - - latency 0x000432b0 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_XST_OFFLOAD 1 1 REG xon_stable 0x00043480 1 RO uint32 b[0:0] - - - REG_BSN_MONITOR_V2_XST_OFFLOAD 1 1 REG xon_stable 0x000432a0 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x00043480 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x000432a0 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00043480 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x000432a0 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00043481 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x000432a1 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00043482 - - - b[31:0] b[63:32] - - - - - - - 0x000432a2 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00043483 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x000432a3 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00043484 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x000432a4 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00043485 1 RO uint32 b[31:0] - - - - - - - nof_err 0x000432a5 1 RO uint32 b[31:0] - - -
- - - - latency 0x00043488 1 RO uint32 b[31:0] - - - - - - - latency 0x000432a8 1 RO uint32 b[31:0] - - -
REG_RING_LANE_INFO_XST 1 1 REG lane_direction 0x00000c02 1 RO uint32 b[0:0] - - - REG_RING_LANE_INFO_XST 1 1 REG lane_direction 0x00000c02 1 RO uint32 b[0:0] - - -
- - - - transport_nof_hops 0x00000c03 1 RW uint32 b[31:0] - - - - - - - transport_nof_hops 0x00000c03 1 RW uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_RX_XST 1 16 REG xon_stable 0x00000c80 1 RO uint32 b[0:0] - - 8 REG_BSN_MONITOR_V2_RING_RX_XST 1 16 REG xon_stable 0x00000c80 1 RO uint32 b[0:0] - - 8
...@@ -332,13 +332,13 @@ number_of_columns = 13 ...@@ -332,13 +332,13 @@ number_of_columns = 13
- - - - nof_valid 0x00000084 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x00000084 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000085 1 RO uint32 b[31:0] - - - - - - - nof_err 0x00000085 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000088 1 RO uint32 b[31:0] - - - - - - - latency 0x00000088 1 RO uint32 b[31:0] - - -
REG_DP_BLOCK_VALIDATE_ERR_XST 1 1 REG err_count_index 0x00043410 8 RO uint32 b[31:0] - - - REG_DP_BLOCK_VALIDATE_ERR_XST 1 1 REG err_count_index 0x00043230 8 RO uint32 b[31:0] - - -
- - - - total_discarded_blocks 0x00043418 1 RO uint32 b[31:0] - - - - - - - total_discarded_blocks 0x00043238 1 RO uint32 b[31:0] - - -
- - - - total_block_count 0x00043419 1 RO uint32 b[31:0] - - - - - - - total_block_count 0x00043239 1 RO uint32 b[31:0] - - -
- - - - clear 0x0004341a 1 RW uint32 b[31:0] - - - - - - - clear 0x0004323a 1 RW uint32 b[31:0] - - -
REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST 1 1 REG nof_sync_discarded 0x000434b8 1 RO uint32 b[31:0] - - - REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST 1 1 REG nof_sync_discarded 0x000432d8 1 RO uint32 b[31:0] - - -
- - - - nof_sync 0x000434b9 1 RO uint32 b[31:0] - - - - - - - nof_sync 0x000432d9 1 RO uint32 b[31:0] - - -
- - - - clear 0x000434ba 1 RW uint32 b[31:0] - - - - - - - clear 0x000432da 1 RW uint32 b[31:0] - - -
REG_TR_10GBE_MAC 1 3 REG rx_transfer_control 0x00020000 1 RW uint32 b[0:0] - - 1 REG_TR_10GBE_MAC 1 3 REG rx_transfer_control 0x00020000 1 RW uint32 b[0:0] - - 1
- - - - rx_transfer_status 0x00020001 1 RO uint32 b[0:0] - - - - - - - rx_transfer_status 0x00020001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00020002 1 RW uint32 b[0:0] - - - - - - - tx_transfer_control 0x00020002 1 RW uint32 b[0:0] - - -
...@@ -515,13 +515,13 @@ number_of_columns = 13 ...@@ -515,13 +515,13 @@ number_of_columns = 13
- - - - - 0x00021c3b - - - b[31:0] b[31:0] - - - - - - - 0x00021c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00021c3c 1 RO uint64 b[3:0] b[35:32] - - - - - - tx_stats_pfcmacctrlframes 0x00021c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00021c3d - - - b[31:0] b[31:0] - - - - - - - 0x00021c3d - - - b[31:0] b[31:0] - -
REG_TR_10GBE_ETH10G 1 3 REG tx_snk_out_xon 0x00043478 1 RO uint32 b[0:0] - - 1 REG_TR_10GBE_ETH10G 1 3 REG tx_snk_out_xon 0x00043298 1 RO uint32 b[0:0] - - 1
- - - - xgmii_tx_ready 0x00043478 1 RO uint32 b[1:1] - - - - - - - xgmii_tx_ready 0x00043298 1 RO uint32 b[1:1] - - -
- - - - xgmii_link_status 0x00043478 1 RO uint32 b[3:2] - - - - - - - xgmii_link_status 0x00043298 1 RO uint32 b[3:2] - - -
RAM_SS_SS_WIDE 2 6 RAM data 0x00030000 976 RW uint32 b[9:0] - 8192 1024 RAM_SS_SS_WIDE 2 6 RAM data 0x00030000 976 RW uint32 b[9:0] - 8192 1024
RAM_BF_WEIGHTS 2 12 RAM data 0x00028000 976 RW cint16_ir b[31:0] - 16384 1024 RAM_BF_WEIGHTS 2 12 RAM data 0x00028000 976 RW cint16_ir b[31:0] - 16384 1024
REG_BSN_ALIGN_V2_BF 2 2 REG enable 0x00043460 1 RW uint32 b[0:0] - 1 2 REG_BSN_ALIGN_V2_BF 2 2 REG enable 0x00043288 1 RW uint32 b[0:0] - 1 2
- - - - replaced_pkt_cnt 0x00043461 1 RO uint32 b[31:0] - - - - - - - replaced_pkt_cnt 0x00043289 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RX_ALIGN_BF 2 2 REG xon_stable 0x00000c20 1 RO uint32 b[0:0] - 1 8 REG_BSN_MONITOR_V2_RX_ALIGN_BF 2 2 REG xon_stable 0x00000c20 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x00000c20 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x00000c20 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000c20 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x00000c20 1 RO uint32 b[2:2] - - -
...@@ -531,154 +531,154 @@ number_of_columns = 13 ...@@ -531,154 +531,154 @@ number_of_columns = 13
- - - - nof_valid 0x00000c24 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x00000c24 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000c25 1 RO uint32 b[31:0] - - - - - - - nof_err 0x00000c25 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000c28 1 RO uint32 b[31:0] - - - - - - - latency 0x00000c28 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_ALIGNED_BF 2 1 REG xon_stable 0x00000c10 1 RO uint32 b[0:0] - 1 8 REG_BSN_MONITOR_V2_ALIGNED_BF 2 1 REG xon_stable 0x00043200 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x00000c10 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x00043200 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000c10 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x00043200 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00000c11 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x00043201 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c12 - - - b[31:0] b[63:32] - - - - - - - 0x00043202 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00000c13 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x00043203 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00000c14 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x00043204 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000c15 1 RO uint32 b[31:0] - - - - - - - nof_err 0x00043205 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000c18 1 RO uint32 b[31:0] - - - - - - - latency 0x00043208 1 RO uint32 b[31:0] - - -
REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x00000c04 1 RO uint32 b[0:0] - 1 2 REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x000432d0 1 RO uint32 b[0:0] - 1 2
- - - - transport_nof_hops 0x00000c05 1 RW uint32 b[31:0] - - - - - - - transport_nof_hops 0x000432d1 1 RW uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_RX_BF 2 16 REG xon_stable 0x00000d00 1 RO uint32 b[0:0] - 1 8 REG_BSN_MONITOR_V2_RING_RX_BF 2 1 REG xon_stable 0x000431f0 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x00000d00 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x000431f0 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000d00 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x000431f0 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00000d01 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x000431f1 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00000d02 - - - b[31:0] b[63:32] - - - - - - - 0x000431f2 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00000d03 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x000431f3 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00000d04 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x000431f4 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000d05 1 RO uint32 b[31:0] - - - - - - - nof_err 0x000431f5 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000d08 1 RO uint32 b[31:0] - - - - - - - latency 0x000431f8 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_TX_BF 2 16 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - 1 8 REG_BSN_MONITOR_V2_RING_TX_BF 2 1 REG xon_stable 0x000431e0 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x000431e0 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x000431e0 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x000431e1 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00000102 - - - b[31:0] b[63:32] - - - - - - - 0x000431e2 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x000431e3 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x000431e4 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - - - - - - nof_err 0x000431e5 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000108 1 RO uint32 b[31:0] - - - - - - - latency 0x000431e8 1 RO uint32 b[31:0] - - -
REG_DP_BLOCK_VALIDATE_ERR_BF 2 1 REG err_count_index 0x00000020 8 RO uint32 b[31:0] - 1 16 REG_DP_BLOCK_VALIDATE_ERR_BF 2 1 REG err_count_index 0x00000020 8 RO uint32 b[31:0] - 1 16
- - - - total_discarded_blocks 0x00000028 1 RO uint32 b[31:0] - - - - - - - total_discarded_blocks 0x00000028 1 RO uint32 b[31:0] - - -
- - - - total_block_count 0x00000029 1 RO uint32 b[31:0] - - - - - - - total_block_count 0x00000029 1 RO uint32 b[31:0] - - -
- - - - clear 0x0000002a 1 RW uint32 b[31:0] - - - - - - - clear 0x0000002a 1 RW uint32 b[31:0] - - -
REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF 2 1 REG nof_sync_discarded 0x00000c08 1 RO uint32 b[31:0] - 1 4 REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF 2 1 REG nof_sync_discarded 0x00043280 1 RO uint32 b[31:0] - 1 4
- - - - nof_sync 0x00000c09 1 RO uint32 b[31:0] - - - - - - - nof_sync 0x00043281 1 RO uint32 b[31:0] - - -
- - - - clear 0x00000c0a 1 RW uint32 b[31:0] - - - - - - - clear 0x00043282 1 RW uint32 b[31:0] - - -
REG_BF_SCALE 2 1 REG scale 0x000434c4 1 RW uint32 b[15:0] - 2 2 REG_BF_SCALE 2 1 REG scale 0x000432e4 1 RW uint32 b[15:0] - 2 2
- - - - unused 0x000434c5 1 RW uint32 b[31:0] - - - - - - - unused 0x000432e5 1 RW uint32 b[31:0] - - -
REG_HDR_DAT 2 1 REG bsn 0x00043200 1 RW uint64 b[31:0] b[31:0] 64 64 REG_HDR_DAT 2 1 REG bsn 0x00043000 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - 0x00043201 - - - b[31:0] b[63:32] - - - - - - - 0x00043001 - - - b[31:0] b[63:32] - -
- - - - sdp_block_period 0x00043202 1 RW uint32 b[15:0] - - - - - - - sdp_block_period 0x00043002 1 RW uint32 b[15:0] - - -
- - - - sdp_nof_beamlets_per_block 0x00043203 1 RW uint32 b[15:0] - - - - - - - sdp_nof_beamlets_per_block 0x00043003 1 RW uint32 b[15:0] - - -
- - - - sdp_nof_blocks_per_packet 0x00043204 1 RW uint32 b[7:0] - - - - - - - sdp_nof_blocks_per_packet 0x00043004 1 RW uint32 b[7:0] - - -
- - - - sdp_beamlet_index 0x00043205 1 RW uint32 b[15:0] - - - - - - - sdp_beamlet_index 0x00043005 1 RW uint32 b[15:0] - - -
- - - - sdp_beamlet_scale 0x00043206 1 RW uint32 b[15:0] - - - - - - - sdp_beamlet_scale 0x00043006 1 RW uint32 b[15:0] - - -
- - - - sdp_reserved 0x00043207 1 RW uint64 b[31:0] b[31:0] - - - - - - sdp_reserved 0x00043007 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00043208 - - - b[7:0] b[39:32] - - - - - - - 0x00043008 - - - b[7:0] b[39:32] - -
- - - - sdp_source_info_gn_index 0x00043209 1 RW uint32 b[4:0] - - - - - - - sdp_source_info_gn_index 0x00043009 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_beamlet_width 0x0004320a 1 RW uint32 b[7:5] - - - - - - - sdp_source_info_beamlet_width 0x0004300a 1 RW uint32 b[7:5] - - -
- - - - sdp_source_info_repositioning_flag 0x0004320b 1 RW uint32 b[9:9] - - - - - - - sdp_source_info_repositioning_flag 0x0004300b 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x0004320c 1 RW uint32 b[10:10] - - - - - - - sdp_source_info_payload_error 0x0004300c 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x0004320d 1 RW uint32 b[11:11] - - - - - - - sdp_source_info_fsub_type 0x0004300d 1 RW uint32 b[11:11] - - -
- - - - sdp_source_info_f_adc 0x0004320e 1 RW uint32 b[12:12] - - - - - - - sdp_source_info_f_adc 0x0004300e 1 RW uint32 b[12:12] - - -
- - - - sdp_source_info_nyquist_zone_index 0x0004320f 1 RW uint32 b[14:13] - - - - - - - sdp_source_info_nyquist_zone_index 0x0004300f 1 RW uint32 b[14:13] - - -
- - - - sdp_source_info_antenna_band_index 0x00043210 1 RW uint32 b[15:15] - - - - - - - sdp_source_info_antenna_band_index 0x00043010 1 RW uint32 b[15:15] - - -
- - - - sdp_station_id 0x00043211 1 RW uint32 b[15:0] - - - - - - - sdp_station_id 0x00043011 1 RW uint32 b[15:0] - - -
- - - - sdp_observation_id 0x00043212 1 RW uint32 b[31:0] - - - - - - - sdp_observation_id 0x00043012 1 RW uint32 b[31:0] - - -
- - - - sdp_version_id 0x00043213 1 RO uint32 b[7:0] - - - - - - - sdp_version_id 0x00043013 1 RO uint32 b[7:0] - - -
- - - - sdp_marker 0x00043214 1 RO uint32 b[7:0] - - - - - - - sdp_marker 0x00043014 1 RO uint32 b[7:0] - - -
- - - - udp_checksum 0x00043215 1 RW uint32 b[15:0] - - - - - - - udp_checksum 0x00043015 1 RW uint32 b[15:0] - - -
- - - - udp_length 0x00043216 1 RW uint32 b[15:0] - - - - - - - udp_length 0x00043016 1 RW uint32 b[15:0] - - -
- - - - udp_destination_port 0x00043217 1 RW uint32 b[15:0] - - - - - - - udp_destination_port 0x00043017 1 RW uint32 b[15:0] - - -
- - - - udp_source_port 0x00043218 1 RW uint32 b[15:0] - - - - - - - udp_source_port 0x00043018 1 RW uint32 b[15:0] - - -
- - - - ip_destination_address 0x00043219 1 RW uint32 b[31:0] - - - - - - - ip_destination_address 0x00043019 1 RW uint32 b[31:0] - - -
- - - - ip_source_address 0x0004321a 1 RW uint32 b[31:0] - - - - - - - ip_source_address 0x0004301a 1 RW uint32 b[31:0] - - -
- - - - ip_header_checksum 0x0004321b 1 RW uint32 b[15:0] - - - - - - - ip_header_checksum 0x0004301b 1 RW uint32 b[15:0] - - -
- - - - ip_protocol 0x0004321c 1 RW uint32 b[7:0] - - - - - - - ip_protocol 0x0004301c 1 RW uint32 b[7:0] - - -
- - - - ip_time_to_live 0x0004321d 1 RW uint32 b[7:0] - - - - - - - ip_time_to_live 0x0004301d 1 RW uint32 b[7:0] - - -
- - - - ip_fragment_offset 0x0004321e 1 RW uint32 b[12:0] - - - - - - - ip_fragment_offset 0x0004301e 1 RW uint32 b[12:0] - - -
- - - - ip_flags 0x0004321f 1 RW uint32 b[2:0] - - - - - - - ip_flags 0x0004301f 1 RW uint32 b[2:0] - - -
- - - - ip_identification 0x00043220 1 RW uint32 b[15:0] - - - - - - - ip_identification 0x00043020 1 RW uint32 b[15:0] - - -
- - - - ip_total_length 0x00043221 1 RW uint32 b[15:0] - - - - - - - ip_total_length 0x00043021 1 RW uint32 b[15:0] - - -
- - - - ip_services 0x00043222 1 RW uint32 b[7:0] - - - - - - - ip_services 0x00043022 1 RW uint32 b[7:0] - - -
- - - - ip_header_length 0x00043223 1 RW uint32 b[3:0] - - - - - - - ip_header_length 0x00043023 1 RW uint32 b[3:0] - - -
- - - - ip_version 0x00043224 1 RW uint32 b[3:0] - - - - - - - ip_version 0x00043024 1 RW uint32 b[3:0] - - -
- - - - eth_type 0x00043225 1 RO uint32 b[15:0] - - - - - - - eth_type 0x00043025 1 RO uint32 b[15:0] - - -
- - - - eth_source_mac 0x00043226 1 RO uint64 b[31:0] b[31:0] - - - - - - eth_source_mac 0x00043026 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00043227 - - - b[15:0] b[47:32] - - - - - - - 0x00043027 - - - b[15:0] b[47:32] - -
- - - - eth_destination_mac 0x00043228 1 RW uint64 b[31:0] b[31:0] - - - - - - eth_destination_mac 0x00043028 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00043229 - - - b[15:0] b[47:32] - - - - - - - 0x00043029 - - - b[15:0] b[47:32] - -
REG_DP_XONOFF 2 1 REG enable_stream 0x000434c0 1 RW uint32 b[0:0] - 2 2 REG_DP_XONOFF 2 1 REG enable_stream 0x000432e0 1 RW uint32 b[0:0] - 2 2
RAM_ST_BST 2 1 RAM data 0x00001000 976 RW uint64 b[31:0] b[31:0] 2048 2048 RAM_ST_BST 2 1 RAM data 0x00001000 976 RW uint64 b[31:0] b[31:0] 2048 2048
- - - - - 0x00001001 - - - b[21:0] b[53:32] - - - - - - - 0x00001001 - - - b[21:0] b[53:32] - -
REG_STAT_ENABLE_BST 2 1 REG enable 0x000434bc 1 RW uint32 b[0:0] - 2 2 REG_STAT_ENABLE_BST 2 1 REG enable 0x000432dc 1 RW uint32 b[0:0] - 2 2
REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00043180 1 RW uint64 b[31:0] b[31:0] 64 64 REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00000d80 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - 0x00043181 - - - b[31:0] b[63:32] - - - - - - - 0x00000d81 - - - b[31:0] b[63:32] - -
- - - - block_period 0x00043182 1 RW uint32 b[15:0] - - - - - - - block_period 0x00000d82 1 RW uint32 b[15:0] - - -
- - - - nof_statistics_per_packet 0x00043183 1 RW uint32 b[15:0] - - - - - - - nof_statistics_per_packet 0x00000d83 1 RW uint32 b[15:0] - - -
- - - - nof_bytes_per_statistic 0x00043184 1 RW uint32 b[7:0] - - - - - - - nof_bytes_per_statistic 0x00000d84 1 RW uint32 b[7:0] - - -
- - - - nof_signal_inputs 0x00043185 1 RW uint32 b[7:0] - - - - - - - nof_signal_inputs 0x00000d85 1 RW uint32 b[7:0] - - -
- - - - sdp_data_id 0x00043186 1 RW uint32 b[31:0] - - - - - - - sdp_data_id 0x00000d86 1 RW uint32 b[31:0] - - -
- - - - sdp_data_id_bst_beamlet_index 0x00043186 1 RW uint32 b[15:0] - - - - - - - sdp_data_id_bst_beamlet_index 0x00000d86 1 RW uint32 b[15:0] - - -
- - - - sdp_data_id_bst_reserved 0x00043186 1 RW uint32 b[31:16] - - - - - - - sdp_data_id_bst_reserved 0x00000d86 1 RW uint32 b[31:16] - - -
- - - - sdp_integration_interval 0x00043187 1 RW uint32 b[23:0] - - - - - - - sdp_integration_interval 0x00000d87 1 RW uint32 b[23:0] - - -
- - - - sdp_reserved 0x00043188 1 RW uint32 b[7:0] - - - - - - - sdp_reserved 0x00000d88 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x00043189 1 RW uint32 b[4:0] - - - - - - - sdp_source_info_gn_index 0x00000d89 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x0004318a 1 RW uint32 b[7:5] - - - - - - - sdp_source_info_reserved 0x00000d8a 1 RW uint32 b[7:5] - - -
- - - - sdp_source_info_weighted_subbands_flag 0x0004318b 1 RW uint32 b[8:8] - - - - - - - sdp_source_info_weighted_subbands_flag 0x00000d8b 1 RW uint32 b[8:8] - - -
- - - - sdp_source_info_beam_repositioning_flag 0x0004318c 1 RW uint32 b[9:9] - - - - - - - sdp_source_info_beam_repositioning_flag 0x00000d8c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x0004318d 1 RW uint32 b[10:10] - - - - - - - sdp_source_info_payload_error 0x00000d8d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x0004318e 1 RW uint32 b[11:11] - - - - - - - sdp_source_info_fsub_type 0x00000d8e 1 RW uint32 b[11:11] - - -
- - - - sdp_source_info_f_adc 0x0004318f 1 RW uint32 b[12:12] - - - - - - - sdp_source_info_f_adc 0x00000d8f 1 RW uint32 b[12:12] - - -
- - - - sdp_source_info_nyquist_zone_index 0x00043190 1 RW uint32 b[14:13] - - - - - - - sdp_source_info_nyquist_zone_index 0x00000d90 1 RW uint32 b[14:13] - - -
- - - - sdp_source_info_antenna_band_index 0x00043191 1 RW uint32 b[15:15] - - - - - - - sdp_source_info_antenna_band_index 0x00000d91 1 RW uint32 b[15:15] - - -
- - - - sdp_station_id 0x00043192 1 RW uint32 b[15:0] - - - - - - - sdp_station_id 0x00000d92 1 RW uint32 b[15:0] - - -
- - - - sdp_observation_id 0x00043193 1 RW uint32 b[31:0] - - - - - - - sdp_observation_id 0x00000d93 1 RW uint32 b[31:0] - - -
- - - - sdp_version_id 0x00043194 1 RO uint32 b[7:0] - - - - - - - sdp_version_id 0x00000d94 1 RO uint32 b[7:0] - - -
- - - - sdp_marker 0x00043195 1 RO uint32 b[7:0] - - - - - - - sdp_marker 0x00000d95 1 RO uint32 b[7:0] - - -
- - - - udp_checksum 0x00043196 1 RW uint32 b[15:0] - - - - - - - udp_checksum 0x00000d96 1 RW uint32 b[15:0] - - -
- - - - udp_length 0x00043197 1 RW uint32 b[15:0] - - - - - - - udp_length 0x00000d97 1 RW uint32 b[15:0] - - -
- - - - udp_destination_port 0x00043198 1 RW uint32 b[15:0] - - - - - - - udp_destination_port 0x00000d98 1 RW uint32 b[15:0] - - -
- - - - udp_source_port 0x00043199 1 RW uint32 b[15:0] - - - - - - - udp_source_port 0x00000d99 1 RW uint32 b[15:0] - - -
- - - - ip_destination_address 0x0004319a 1 RW uint32 b[31:0] - - - - - - - ip_destination_address 0x00000d9a 1 RW uint32 b[31:0] - - -
- - - - ip_source_address 0x0004319b 1 RW uint32 b[31:0] - - - - - - - ip_source_address 0x00000d9b 1 RW uint32 b[31:0] - - -
- - - - ip_header_checksum 0x0004319c 1 RW uint32 b[15:0] - - - - - - - ip_header_checksum 0x00000d9c 1 RW uint32 b[15:0] - - -
- - - - ip_protocol 0x0004319d 1 RW uint32 b[7:0] - - - - - - - ip_protocol 0x00000d9d 1 RW uint32 b[7:0] - - -
- - - - ip_time_to_live 0x0004319e 1 RW uint32 b[7:0] - - - - - - - ip_time_to_live 0x00000d9e 1 RW uint32 b[7:0] - - -
- - - - ip_fragment_offset 0x0004319f 1 RW uint32 b[12:0] - - - - - - - ip_fragment_offset 0x00000d9f 1 RW uint32 b[12:0] - - -
- - - - ip_flags 0x000431a0 1 RW uint32 b[2:0] - - - - - - - ip_flags 0x00000da0 1 RW uint32 b[2:0] - - -
- - - - ip_identification 0x000431a1 1 RW uint32 b[15:0] - - - - - - - ip_identification 0x00000da1 1 RW uint32 b[15:0] - - -
- - - - ip_total_length 0x000431a2 1 RW uint32 b[15:0] - - - - - - - ip_total_length 0x00000da2 1 RW uint32 b[15:0] - - -
- - - - ip_services 0x000431a3 1 RW uint32 b[7:0] - - - - - - - ip_services 0x00000da3 1 RW uint32 b[7:0] - - -
- - - - ip_header_length 0x000431a4 1 RW uint32 b[3:0] - - - - - - - ip_header_length 0x00000da4 1 RW uint32 b[3:0] - - -
- - - - ip_version 0x000431a5 1 RW uint32 b[3:0] - - - - - - - ip_version 0x00000da5 1 RW uint32 b[3:0] - - -
- - - - eth_type 0x000431a6 1 RO uint32 b[15:0] - - - - - - - eth_type 0x00000da6 1 RO uint32 b[15:0] - - -
- - - - eth_source_mac 0x000431a7 1 RO uint64 b[31:0] b[31:0] - - - - - - eth_source_mac 0x00000da7 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x000431a8 - - - b[15:0] b[47:32] - - - - - - - 0x00000da8 - - - b[15:0] b[47:32] - -
- - - - eth_destination_mac 0x000431a9 1 RW uint64 b[31:0] b[31:0] - - - - - - eth_destination_mac 0x00000da9 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x000431aa - - - b[15:0] b[47:32] - - - - - - - 0x00000daa - - - b[15:0] b[47:32] - -
- - - - word_align 0x000431ab 1 RW uint32 b[15:0] - - - - - - - word_align 0x00000dab 1 RW uint32 b[15:0] - - -
REG_BSN_MONITOR_V2_BST_OFFLOAD 2 1 REG xon_stable 0x00043400 1 RO uint32 b[0:0] - 1 8 REG_BSN_MONITOR_V2_BST_OFFLOAD 2 1 REG xon_stable 0x00043220 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x00043400 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x00043220 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00043400 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x00043220 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00043401 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x00043221 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00043402 - - - b[31:0] b[63:32] - - - - - - - 0x00043222 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00043403 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x00043223 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00043404 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x00043224 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00043405 1 RO uint32 b[31:0] - - - - - - - nof_err 0x00043225 1 RO uint32 b[31:0] - - -
- - - - latency 0x00043408 1 RO uint32 b[31:0] - - - - - - - latency 0x00043228 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_BEAMLET_OUTPUT 2 1 REG xon_stable 0x000433f0 1 RO uint32 b[0:0] - 1 8 REG_BSN_MONITOR_V2_BEAMLET_OUTPUT 2 1 REG xon_stable 0x00043210 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x000433f0 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x00043210 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x000433f0 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x00043210 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x000433f1 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x00043211 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x000433f2 - - - b[31:0] b[63:32] - - - - - - - 0x00043212 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x000433f3 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x00043213 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x000433f4 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x00043214 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x000433f5 1 RO uint32 b[31:0] - - - - - - - nof_err 0x00043215 1 RO uint32 b[31:0] - - -
- - - - latency 0x000433f8 1 RO uint32 b[31:0] - - - - - - - latency 0x00043218 1 RO uint32 b[31:0] - - -
REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00006000 1 RW uint32 b[0:0] - - - REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00006000 1 RW uint32 b[0:0] - - -
- - - - rx_transfer_status 0x00006001 1 RO uint32 b[0:0] - - - - - - - rx_transfer_status 0x00006001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00006002 1 RW uint32 b[0:0] - - - - - - - tx_transfer_control 0x00006002 1 RW uint32 b[0:0] - - -
...@@ -855,6 +855,6 @@ number_of_columns = 13 ...@@ -855,6 +855,6 @@ number_of_columns = 13
- - - - - 0x00007c3b - - - b[31:0] b[31:0] - - - - - - - 0x00007c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00007c3c 1 RO uint64 b[3:0] b[35:32] - - - - - - tx_stats_pfcmacctrlframes 0x00007c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00007c3d - - - b[31:0] b[31:0] - - - - - - - 0x00007c3d - - - b[31:0] b[31:0] - -
REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x000434d4 1 RO uint32 b[0:0] - - - REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x000432f4 1 RO uint32 b[0:0] - - -
- - - - xgmii_tx_ready 0x000434d4 1 RO uint32 b[1:1] - - - - - - - xgmii_tx_ready 0x000432f4 1 RO uint32 b[1:1] - - -
- - - - xgmii_link_status 0x000434d4 1 RO uint32 b[3:2] - - - - - - - xgmii_link_status 0x000432f4 1 RO uint32 b[3:2] - - -
\ No newline at end of file \ No newline at end of file
applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.gold
+ 3
− 3
View file @ 55314038
...@@ -34,7 +34,7 @@ number_of_columns = 13 ...@@ -34,7 +34,7 @@ number_of_columns = 13
- - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - - - - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - -
- - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - - - - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - -
- - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - - - - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - -
- - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0] - - - - - - design_note 0x00008014 48 RO char8 b[31:0] b[7:0] - -
REG_WDI 1 1 REG wdi_override 0x00010000 1 WO uint32 b[31:0] - - - REG_WDI 1 1 REG wdi_override 0x00010000 1 WO uint32 b[31:0] - - -
REG_FPGA_TEMP_SENS 1 1 REG temp 0x00018000 1 RO uint32 b[31:0] - - - REG_FPGA_TEMP_SENS 1 1 REG temp 0x00018000 1 RO uint32 b[31:0] - - -
REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00018000 6 RO uint32 b[31:0] - - - REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00018000 6 RO uint32 b[31:0] - - -
...@@ -542,7 +542,7 @@ number_of_columns = 13 ...@@ -542,7 +542,7 @@ number_of_columns = 13
- - - - latency 0x001a8008 1 RO uint32 b[31:0] - - - - - - - latency 0x001a8008 1 RO uint32 b[31:0] - - -
REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x001b0000 1 RO uint32 b[0:0] - 1 2 REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x001b0000 1 RO uint32 b[0:0] - 1 2
- - - - transport_nof_hops 0x001b0001 1 RW uint32 b[31:0] - - - - - - - transport_nof_hops 0x001b0001 1 RW uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_RX_BF 2 16 REG xon_stable 0x001b8000 1 RO uint32 b[0:0] - 1 8 REG_BSN_MONITOR_V2_RING_RX_BF 2 1 REG xon_stable 0x001b8000 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x001b8000 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x001b8000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x001b8000 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x001b8000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x001b8001 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x001b8001 1 RO uint64 b[31:0] b[31:0] - -
...@@ -551,7 +551,7 @@ number_of_columns = 13 ...@@ -551,7 +551,7 @@ number_of_columns = 13
- - - - nof_valid 0x001b8004 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x001b8004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x001b8005 1 RO uint32 b[31:0] - - - - - - - nof_err 0x001b8005 1 RO uint32 b[31:0] - - -
- - - - latency 0x001b8008 1 RO uint32 b[31:0] - - - - - - - latency 0x001b8008 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_TX_BF 2 16 REG xon_stable 0x001c0000 1 RO uint32 b[0:0] - 1 8 REG_BSN_MONITOR_V2_RING_TX_BF 2 1 REG xon_stable 0x001c0000 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x001c0000 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x001c0000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x001c0000 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x001c0000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x001c0001 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x001c0001 1 RO uint64 b[31:0] b[31:0] - -
......
applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.qsys.gold
+ 289
− 289
View file @ 55314038
...@@ -34,53 +34,53 @@ number_of_columns = 13 ...@@ -34,53 +34,53 @@ number_of_columns = 13
- - - - stamp_date 0x0000000f 1 RO uint32 b[31:0] - - - - - - - stamp_date 0x0000000f 1 RO uint32 b[31:0] - - -
- - - - stamp_time 0x00000010 1 RO uint32 b[31:0] - - - - - - - stamp_time 0x00000010 1 RO uint32 b[31:0] - - -
- - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - - - - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - -
- - - - design_note 0x00000014 52 RO char8 b[31:0] b[7:0] - - - - - - design_note 0x00000014 48 RO char8 b[31:0] b[7:0] - -
REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - - REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - -
REG_FPGA_TEMP_SENS 1 1 REG temp 0x00043418 1 RO uint32 b[31:0] - - - REG_FPGA_TEMP_SENS 1 1 REG temp 0x00043238 1 RO uint32 b[31:0] - - -
REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x000433d0 6 RO uint32 b[31:0] - - - REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x000431f0 6 RO uint32 b[31:0] - - -
RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - - RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - -
AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - - AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - -
AVS_ETH_0_REG 1 1 REG status 0x00043360 12 RO uint32 b[31:0] - - - AVS_ETH_0_REG 1 1 REG status 0x00000c10 12 RO uint32 b[31:0] - - -
AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - - AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - -
PIO_PPS 1 1 REG capture_cnt 0x00043448 1 RO uint32 b[29:0] - - - PIO_PPS 1 1 REG capture_cnt 0x00043268 1 RO uint32 b[29:0] - - -
- - - - stable 0x00043448 1 RO uint32 b[30:30] - - - - - - - stable 0x00043268 1 RO uint32 b[30:30] - - -
- - - - toggle 0x00043448 1 RO uint32 b[31:31] - - - - - - - toggle 0x00043268 1 RO uint32 b[31:31] - - -
- - - - expected_cnt 0x00043449 1 RW uint32 b[27:0] - - - - - - - expected_cnt 0x00043269 1 RW uint32 b[27:0] - - -
- - - - edge 0x00043449 1 RW uint32 b[31:31] - - - - - - - edge 0x00043269 1 RW uint32 b[31:31] - - -
- - - - offset_cnt 0x0004344a 1 RO uint32 b[27:0] - - - - - - - offset_cnt 0x0004326a 1 RO uint32 b[27:0] - - -
REG_EPCS 1 1 REG addr 0x00043420 1 WO uint32 b[31:0] - - - REG_EPCS 1 1 REG addr 0x00043240 1 WO uint32 b[31:0] - - -
- - - - rden 0x00043421 1 WO uint32 b[0:0] - - - - - - - rden 0x00043241 1 WO uint32 b[0:0] - - -
- - - - read_bit 0x00043422 1 WO uint32 b[0:0] - - - - - - - read_bit 0x00043242 1 WO uint32 b[0:0] - - -
- - - - write_bit 0x00043423 1 WO uint32 b[0:0] - - - - - - - write_bit 0x00043243 1 WO uint32 b[0:0] - - -
- - - - sector_erase 0x00043424 1 WO uint32 b[0:0] - - - - - - - sector_erase 0x00043244 1 WO uint32 b[0:0] - - -
- - - - busy 0x00043425 1 RO uint32 b[0:0] - - - - - - - busy 0x00043245 1 RO uint32 b[0:0] - - -
- - - - unprotect 0x00043426 1 WO uint32 b[31:0] - - - - - - - unprotect 0x00043246 1 WO uint32 b[31:0] - - -
REG_DPMM_CTRL 1 1 REG rd_usedw 0x00043462 1 RO uint32 b[31:0] - - - REG_DPMM_CTRL 1 1 REG rd_usedw 0x00043282 1 RO uint32 b[31:0] - - -
REG_DPMM_DATA 1 1 FIFO data 0x00043460 1 RO uint32 b[31:0] - - - REG_DPMM_DATA 1 1 FIFO data 0x00043280 1 RO uint32 b[31:0] - - -
REG_MMDP_CTRL 1 1 REG wr_usedw 0x0004345e 1 RO uint32 b[31:0] - - - REG_MMDP_CTRL 1 1 REG wr_usedw 0x0004327e 1 RO uint32 b[31:0] - - -
- - - - wr_availw 0x0004345f 1 RO uint32 b[31:0] - - - - - - - wr_availw 0x0004327f 1 RO uint32 b[31:0] - - -
REG_MMDP_DATA 1 1 FIFO data 0x0004345c 1 WO uint32 b[31:0] - - - REG_MMDP_DATA 1 1 FIFO data 0x0004327c 1 WO uint32 b[31:0] - - -
REG_REMU 1 1 REG reconfigure 0x00043428 1 WO uint32 b[31:0] - - - REG_REMU 1 1 REG reconfigure 0x00043248 1 WO uint32 b[31:0] - - -
- - - - param 0x00043429 1 WO uint32 b[2:0] - - - - - - - param 0x00043249 1 WO uint32 b[2:0] - - -
- - - - read_param 0x0004342a 1 WO uint32 b[0:0] - - - - - - - read_param 0x0004324a 1 WO uint32 b[0:0] - - -
- - - - write_param 0x0004342b 1 WO uint32 b[0:0] - - - - - - - write_param 0x0004324b 1 WO uint32 b[0:0] - - -
- - - - data_out 0x0004342c 1 RO uint32 b[31:0] - - - - - - - data_out 0x0004324c 1 RO uint32 b[31:0] - - -
- - - - data_in 0x0004342d 1 WO uint32 b[31:0] - - - - - - - data_in 0x0004324d 1 WO uint32 b[31:0] - - -
- - - - busy 0x0004342e 1 RO uint32 b[0:0] - - - - - - - busy 0x0004324e 1 RO uint32 b[0:0] - - -
REG_SDP_INFO 1 1 REG block_period 0x000433c0 1 RO uint32 b[15:0] - - - REG_SDP_INFO 1 1 REG block_period 0x000431e0 1 RO uint32 b[15:0] - - -
- - - - beam_repositioning_flag 0x000433c1 1 RW uint32 b[0:0] - - - - - - - beam_repositioning_flag 0x000431e1 1 RW uint32 b[0:0] - - -
- - - - fsub_type 0x000433c2 1 RO uint32 b[0:0] - - - - - - - fsub_type 0x000431e2 1 RO uint32 b[0:0] - - -
- - - - f_adc 0x000433c3 1 RO uint32 b[0:0] - - - - - - - f_adc 0x000431e3 1 RO uint32 b[0:0] - - -
- - - - nyquist_zone_index 0x000433c4 1 RW uint32 b[1:0] - - - - - - - nyquist_zone_index 0x000431e4 1 RW uint32 b[1:0] - - -
- - - - observation_id 0x000433c5 1 RW uint32 b[31:0] - - - - - - - observation_id 0x000431e5 1 RW uint32 b[31:0] - - -
- - - - antenna_band_index 0x000433c6 1 RW uint32 b[0:0] - - - - - - - antenna_band_index 0x000431e6 1 RW uint32 b[0:0] - - -
- - - - station_id 0x000433c7 1 RW uint32 b[15:0] - - - - - - - station_id 0x000431e7 1 RW uint32 b[15:0] - - -
REG_RING_INFO 1 1 REG use_cable_to_previous_rn 0x00043434 1 RW uint32 b[0:0] - - - REG_RING_INFO 1 1 REG use_cable_to_previous_rn 0x00043254 1 RW uint32 b[0:0] - - -
- - - - use_cable_to_next_rn 0x00043435 1 RW uint32 b[0:0] - - - - - - - use_cable_to_next_rn 0x00043255 1 RW uint32 b[0:0] - - -
- - - - n_rn 0x00043436 1 RW uint32 b[7:0] - - - - - - - n_rn 0x00043256 1 RW uint32 b[7:0] - - -
- - - - o_rn 0x00043437 1 RW uint32 b[7:0] - - - - - - - o_rn 0x00043257 1 RW uint32 b[7:0] - - -
PIO_JESD_CTRL 1 1 REG enable 0x00043452 1 RW uint32 b[30:0] - - - PIO_JESD_CTRL 1 1 REG enable 0x00043272 1 RW uint32 b[30:0] - - -
- - - - reset 0x00043452 1 RW uint32 b[31:31] - - - - - - - reset 0x00043272 1 RW uint32 b[31:31] - - -
JESD204B 1 12 REG rx_lane_ctrl_common 0x00042000 1 RW uint32 b[2:0] - - 256 JESD204B 1 12 REG rx_lane_ctrl_common 0x00042000 1 RW uint32 b[2:0] - - 256
- - - - rx_lane_ctrl_0 0x00042001 1 RW uint32 b[2:0] - - - - - - - rx_lane_ctrl_0 0x00042001 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_1 0x00042002 1 RW uint32 b[2:0] - - - - - - - rx_lane_ctrl_1 0x00042002 1 RW uint32 b[2:0] - - -
...@@ -118,47 +118,47 @@ number_of_columns = 13 ...@@ -118,47 +118,47 @@ number_of_columns = 13
- - - - rx_status5 0x0004203d 1 RW uint32 b[15:0] - - - - - - - rx_status5 0x0004203d 1 RW uint32 b[15:0] - - -
- - - - rx_status6 0x0004203e 1 RW uint32 b[23:0] - - - - - - - rx_status6 0x0004203e 1 RW uint32 b[23:0] - - -
- - - - rx_status7 0x0004203f 1 RO uint32 b[31:0] - - - - - - - rx_status7 0x0004203f 1 RO uint32 b[31:0] - - -
REG_DP_SHIFTRAM 1 12 REG shift 0x00043340 1 RW uint32 b[11:0] - - 2 REG_DP_SHIFTRAM 1 12 REG shift 0x00043140 1 RW uint32 b[11:0] - - 2
REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00043410 1 RW uint32 b[0:0] - - - REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00043230 1 RW uint32 b[0:0] - - -
- - - - dp_on_pps 0x00043410 1 RW uint32 b[1:1] - - - - - - - dp_on_pps 0x00043230 1 RW uint32 b[1:1] - - -
- - - - nof_clk_per_sync 0x00043411 1 RW uint32 b[31:0] - - - - - - - nof_clk_per_sync 0x00043231 1 RW uint32 b[31:0] - - -
- - - - bsn_init 0x00043412 1 RW uint64 b[31:0] b[31:0] - - - - - - bsn_init 0x00043232 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00043413 - - - b[31:0] b[63:32] - - - - - - - 0x00043233 - - - b[31:0] b[63:32] - -
- - - - bsn_time_offset 0x00043414 1 RW uint32 b[9:0] - - - - - - - bsn_time_offset 0x00043234 1 RW uint32 b[9:0] - - -
REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00043458 1 RW uint64 b[31:0] b[31:0] - - REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00043278 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00043459 - - - b[31:0] b[63:32] - - - - - - - 0x00043279 - - - b[31:0] b[63:32] - -
REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00043000 1 RO uint32 b[0:0] - - - REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x00043000 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00043000 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00043001 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00043002 - - - b[31:0] b[63:32] - - - - - - - 0x00000102 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00043003 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00043004 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00043005 1 RO uint32 b[31:0] - - - - - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - -
- - - - bsn_first 0x00043006 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_first 0x00000106 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00043007 - - - b[31:0] b[63:32] - - - - - - - 0x00000107 - - - b[31:0] b[63:32] - -
- - - - bsn_first_cycle_cnt 0x00043008 1 RO uint32 b[31:0] - - - - - - - bsn_first_cycle_cnt 0x00000108 1 RO uint32 b[31:0] - - -
REG_WG 1 12 REG mode 0x00043280 1 RW uint32 b[7:0] - - 4 REG_WG 1 12 REG mode 0x00043080 1 RW uint32 b[7:0] - - 4
- - - - nof_samples 0x00043280 1 RW uint32 b[31:16] - - - - - - - nof_samples 0x00043080 1 RW uint32 b[31:16] - - -
- - - - phase 0x00043281 1 RW uint32 b[15:0] - - - - - - - phase 0x00043081 1 RW uint32 b[15:0] - - -
- - - - freq 0x00043282 1 RW uint32 b[30:0] - - - - - - - freq 0x00043082 1 RW uint32 b[30:0] - - -
- - - - ampl 0x00043283 1 RW uint32 b[16:0] - - - - - - - ampl 0x00043083 1 RW uint32 b[16:0] - - -
RAM_WG 1 12 RAM data 0x00034000 1024 RW uint32 b[17:0] - - 1024 RAM_WG 1 12 RAM data 0x00034000 1024 RW uint32 b[17:0] - - 1024
RAM_ST_HISTOGRAM 1 12 RAM data 0x00002000 512 RW uint32 b[31:0] b[27:0] - 512 RAM_ST_HISTOGRAM 1 12 RAM data 0x00002000 512 RW uint32 b[31:0] b[27:0] - 512
REG_ADUH_MONITOR 1 12 REG mean_sum 0x000432c0 1 RO int64 b[31:0] b[31:0] - 4 REG_ADUH_MONITOR 1 12 REG mean_sum 0x000430c0 1 RO int64 b[31:0] b[31:0] - 4
- - - - - 0x000432c1 - - - b[31:0] b[63:32] - - - - - - - 0x000430c1 - - - b[31:0] b[63:32] - -
- - - - power_sum 0x000432c2 1 RO int64 b[31:0] b[31:0] - - - - - - power_sum 0x000430c2 1 RO int64 b[31:0] b[31:0] - -
- - - - - 0x000432c3 - - - b[31:0] b[63:32] - - - - - - - 0x000430c3 - - - b[31:0] b[63:32] - -
REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00043320 1 RO uint32 b[31:0] - - 2 REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00043120 1 RO uint32 b[31:0] - - 2
- - - - word_cnt 0x00043321 1 RO uint32 b[31:0] - - - - - - - word_cnt 0x00043121 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[31:0] b[15:0] - 1024 RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[31:0] b[15:0] - 1024
REG_SI 1 1 REG enable 0x0004345a 1 RW uint32 b[0:0] - - - REG_SI 1 1 REG enable 0x0004327a 1 RW uint32 b[0:0] - - -
RAM_FIL_COEFS 1 16 RAM data 0x00038000 1024 RW uint32 b[15:0] - - 1024 RAM_FIL_COEFS 1 16 RAM data 0x00038000 1024 RW uint32 b[15:0] - - 1024
RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - - 1024 RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - - 1024
REG_DP_SELECTOR 1 1 REG input_select 0x00043456 1 RW uint32 b[0:0] - - - REG_DP_SELECTOR 1 1 REG input_select 0x00043276 1 RW uint32 b[0:0] - - -
RAM_ST_SST 1 6 RAM data 0x0003c000 1024 RW uint64 b[31:0] b[31:0] - 2048 RAM_ST_SST 1 6 RAM data 0x0003c000 1024 RW uint64 b[31:0] b[31:0] - 2048
- - - - - 0x0003c001 - - - b[21:0] b[53:32] - - - - - - - 0x0003c001 - - - b[21:0] b[53:32] - -
REG_STAT_ENABLE_SST 1 1 REG enable 0x00043450 1 RW uint32 b[0:0] - - - REG_STAT_ENABLE_SST 1 1 REG enable 0x00043270 1 RW uint32 b[0:0] - - -
REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c40 1 RW uint64 b[31:0] b[31:0] - - REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c40 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c41 - - - b[31:0] b[63:32] - - - - - - - 0x00000c41 - - - b[31:0] b[63:32] - -
- - - - sdp_block_period 0x00000c42 1 RW uint32 b[15:0] - - - - - - - sdp_block_period 0x00000c42 1 RW uint32 b[15:0] - - -
...@@ -205,36 +205,36 @@ number_of_columns = 13 ...@@ -205,36 +205,36 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00000c69 1 RW uint64 b[31:0] b[31:0] - - - - - - eth_destination_mac 0x00000c69 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c6a - - - b[15:0] b[47:32] - - - - - - - 0x00000c6a - - - b[15:0] b[47:32] - -
- - - - word_align 0x00000c6b 1 RW uint32 b[15:0] - - - - - - - word_align 0x00000c6b 1 RW uint32 b[15:0] - - -
REG_BSN_MONITOR_V2_SST_OFFLOAD 1 1 REG xon_stable 0x000433f0 1 RO uint32 b[0:0] - - - REG_BSN_MONITOR_V2_SST_OFFLOAD 1 1 REG xon_stable 0x00043210 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x000433f0 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x00043210 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x000433f0 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x00043210 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x000433f1 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x00043211 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x000433f2 - - - b[31:0] b[63:32] - - - - - - - 0x00043212 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x000433f3 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x00043213 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x000433f4 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x00043214 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x000433f5 1 RO uint32 b[31:0] - - - - - - - nof_err 0x00043215 1 RO uint32 b[31:0] - - -
- - - - latency 0x000433f8 1 RO uint32 b[31:0] - - - - - - - latency 0x00043218 1 RO uint32 b[31:0] - - -
REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x000433a0 1 RW uint32 b[0:0] - - - REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x000431c0 1 RW uint32 b[0:0] - - -
- - - - ctrl_interval_size 0x000433a1 1 RW uint32 b[30:0] - - - - - - - ctrl_interval_size 0x000431c1 1 RW uint32 b[30:0] - - -
- - - - ctrl_start_bsn 0x000433a2 1 RW uint64 b[31:0] b[31:0] - - - - - - ctrl_start_bsn 0x000431c2 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x000433a3 - - - b[31:0] b[63:32] - - - - - - - 0x000431c3 - - - b[31:0] b[63:32] - -
- - - - mon_current_input_bsn 0x000433a4 1 RO uint64 b[31:0] b[31:0] - - - - - - mon_current_input_bsn 0x000431c4 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x000433a5 - - - b[31:0] b[63:32] - - - - - - - 0x000431c5 - - - b[31:0] b[63:32] - -
- - - - mon_input_bsn_at_sync 0x000433a6 1 RO uint64 b[31:0] b[31:0] - - - - - - mon_input_bsn_at_sync 0x000431c6 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x000433a7 - - - b[31:0] b[63:32] - - - - - - - 0x000431c7 - - - b[31:0] b[63:32] - -
- - - - mon_output_enable 0x000433a8 1 RO uint32 b[0:0] - - - - - - - mon_output_enable 0x000431c8 1 RO uint32 b[0:0] - - -
- - - - mon_output_sync_bsn 0x000433a9 1 RO uint64 b[31:0] b[31:0] - - - - - - mon_output_sync_bsn 0x000431c9 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x000433aa - - - b[31:0] b[63:32] - - - - - - - 0x000431ca - - - b[31:0] b[63:32] - -
- - - - block_size 0x000433ab 1 RO uint32 b[31:0] - - - - - - - block_size 0x000431cb 1 RO uint32 b[31:0] - - -
RAM_ST_XSQ 1 9 RAM data 0x00010000 1008 RW cint64_ir b[31:0] b[31:0] - 4096 RAM_ST_XSQ 1 9 RAM data 0x00010000 1008 RW cint64_ir b[31:0] b[31:0] - 4096
- - - - - 0x00010001 - - - b[31:0] b[63:32] - - - - - - - 0x00010001 - - - b[31:0] b[63:32] - -
- - - - - 0x00010002 - - - b[31:0] b[95:64] - - - - - - - 0x00010002 - - - b[31:0] b[95:64] - -
- - - - - 0x00010003 - - - b[31:0] b[127:96] - - - - - - - 0x00010003 - - - b[31:0] b[127:96] - -
REG_CROSSLETS_INFO 1 1 REG offset 0x000433b0 15 RW uint32 b[31:0] - - - REG_CROSSLETS_INFO 1 1 REG offset 0x000431d0 15 RW uint32 b[31:0] - - -
- - - - step 0x000433bf 1 RW uint32 b[31:0] - - - - - - - step 0x000431df 1 RW uint32 b[31:0] - - -
REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x0004344c 1 RW uint32 b[31:0] - - - REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x0004326c 1 RW uint32 b[31:0] - - -
- - - - unused 0x0004344d 1 RW uint32 b[31:0] - - - - - - - unused 0x0004326d 1 RW uint32 b[31:0] - - -
REG_STAT_ENABLE_XST 1 1 REG enable 0x0004344e 1 RW uint32 b[0:0] - - - REG_STAT_ENABLE_XST 1 1 REG enable 0x0004326e 1 RW uint32 b[0:0] - - -
REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00000040 1 RW uint64 b[31:0] b[31:0] - - REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00000040 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000041 - - - b[31:0] b[63:32] - - - - - - - 0x00000041 - - - b[31:0] b[63:32] - -
- - - - block_period 0x00000042 1 RW uint32 b[15:0] - - - - - - - block_period 0x00000042 1 RW uint32 b[15:0] - - -
...@@ -283,8 +283,8 @@ number_of_columns = 13 ...@@ -283,8 +283,8 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00000069 1 RW uint64 b[31:0] b[31:0] - - - - - - eth_destination_mac 0x00000069 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x0000006a - - - b[15:0] b[47:32] - - - - - - - 0x0000006a - - - b[15:0] b[47:32] - -
- - - - word_align 0x0000006b 1 RW uint32 b[15:0] - - - - - - - word_align 0x0000006b 1 RW uint32 b[15:0] - - -
REG_BSN_ALIGN_V2_XSUB 1 9 REG enable 0x00043300 1 RW uint32 b[0:0] - - 2 REG_BSN_ALIGN_V2_XSUB 1 9 REG enable 0x00043100 1 RW uint32 b[0:0] - - 2
- - - - replaced_pkt_cnt 0x00043301 1 RO uint32 b[31:0] - - - - - - - replaced_pkt_cnt 0x00043101 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RX_ALIGN_XSUB 1 9 REG xon_stable 0x00000080 1 RO uint32 b[0:0] - - 8 REG_BSN_MONITOR_V2_RX_ALIGN_XSUB 1 9 REG xon_stable 0x00000080 1 RO uint32 b[0:0] - - 8
- - - - ready_stable 0x00000080 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x00000080 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000080 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x00000080 1 RO uint32 b[2:2] - - -
...@@ -294,35 +294,35 @@ number_of_columns = 13 ...@@ -294,35 +294,35 @@ number_of_columns = 13
- - - - nof_valid 0x00000084 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x00000084 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000085 1 RO uint32 b[31:0] - - - - - - - nof_err 0x00000085 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000088 1 RO uint32 b[31:0] - - - - - - - latency 0x00000088 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_ALIGNED_XSUB 1 1 REG xon_stable 0x00043408 1 RO uint32 b[0:0] - - - REG_BSN_MONITOR_V2_ALIGNED_XSUB 1 1 REG xon_stable 0x00043228 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x00043408 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x00043228 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00043408 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x00043228 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00043409 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x00043229 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x0004340a - - - b[31:0] b[63:32] - - - - - - - 0x0004322a - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x0004340b 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x0004322b 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x0004340c 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x0004322c 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x0004340d 1 RO uint32 b[31:0] - - - - - - - nof_err 0x0004322d 1 RO uint32 b[31:0] - - -
- - - - latency 0x00043410 1 RO uint32 b[31:0] - - - - - - - latency 0x00043230 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_XST_OFFLOAD 1 1 REG xon_stable 0x00043400 1 RO uint32 b[0:0] - - - REG_BSN_MONITOR_V2_XST_OFFLOAD 1 1 REG xon_stable 0x00043220 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x00043400 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x00043220 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00043400 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x00043220 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00043401 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x00043221 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00043402 - - - b[31:0] b[63:32] - - - - - - - 0x00043222 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00043403 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x00043223 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00043404 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x00043224 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00043405 1 RO uint32 b[31:0] - - - - - - - nof_err 0x00043225 1 RO uint32 b[31:0] - - -
- - - - latency 0x00043408 1 RO uint32 b[31:0] - - - - - - - latency 0x00043228 1 RO uint32 b[31:0] - - -
REG_RING_LANE_INFO_XST 1 1 REG lane_direction 0x00000c02 1 RO uint32 b[0:0] - - - REG_RING_LANE_INFO_XST 1 1 REG lane_direction 0x00000c02 1 RO uint32 b[0:0] - - -
- - - - transport_nof_hops 0x00000c03 1 RW uint32 b[31:0] - - - - - - - transport_nof_hops 0x00000c03 1 RW uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_RX_XST 1 16 REG xon_stable 0x00043100 1 RO uint32 b[0:0] - - 8 REG_BSN_MONITOR_V2_RING_RX_XST 1 16 REG xon_stable 0x00000d00 1 RO uint32 b[0:0] - - 8
- - - - ready_stable 0x00043100 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x00000d00 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00043100 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x00000d00 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00043101 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x00000d01 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00043102 - - - b[31:0] b[63:32] - - - - - - - 0x00000d02 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00043103 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x00000d03 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00043104 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x00000d04 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00043105 1 RO uint32 b[31:0] - - - - - - - nof_err 0x00000d05 1 RO uint32 b[31:0] - - -
- - - - latency 0x00043108 1 RO uint32 b[31:0] - - - - - - - latency 0x00000d08 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_TX_XST 1 16 REG xon_stable 0x00000c80 1 RO uint32 b[0:0] - - 8 REG_BSN_MONITOR_V2_RING_TX_XST 1 16 REG xon_stable 0x00000c80 1 RO uint32 b[0:0] - - 8
- - - - ready_stable 0x00000c80 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x00000c80 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000c80 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x00000c80 1 RO uint32 b[2:2] - - -
...@@ -332,13 +332,13 @@ number_of_columns = 13 ...@@ -332,13 +332,13 @@ number_of_columns = 13
- - - - nof_valid 0x00000c84 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x00000c84 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000c85 1 RO uint32 b[31:0] - - - - - - - nof_err 0x00000c85 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000c88 1 RO uint32 b[31:0] - - - - - - - latency 0x00000c88 1 RO uint32 b[31:0] - - -
REG_DP_BLOCK_VALIDATE_ERR_XST 1 1 REG err_count_index 0x00043390 8 RO uint32 b[31:0] - - - REG_DP_BLOCK_VALIDATE_ERR_XST 1 1 REG err_count_index 0x000431b0 8 RO uint32 b[31:0] - - -
- - - - total_discarded_blocks 0x00043398 1 RO uint32 b[31:0] - - - - - - - total_discarded_blocks 0x000431b8 1 RO uint32 b[31:0] - - -
- - - - total_block_count 0x00043399 1 RO uint32 b[31:0] - - - - - - - total_block_count 0x000431b9 1 RO uint32 b[31:0] - - -
- - - - clear 0x0004339a 1 RW uint32 b[31:0] - - - - - - - clear 0x000431ba 1 RW uint32 b[31:0] - - -
REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST 1 1 REG nof_sync_discarded 0x00043438 1 RO uint32 b[31:0] - - - REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST 1 1 REG nof_sync_discarded 0x00043258 1 RO uint32 b[31:0] - - -
- - - - nof_sync 0x00043439 1 RO uint32 b[31:0] - - - - - - - nof_sync 0x00043259 1 RO uint32 b[31:0] - - -
- - - - clear 0x0004343a 1 RW uint32 b[31:0] - - - - - - - clear 0x0004325a 1 RW uint32 b[31:0] - - -
REG_TR_10GBE_MAC 1 3 REG rx_transfer_control 0x00020000 1 RW uint32 b[0:0] - - 1 REG_TR_10GBE_MAC 1 3 REG rx_transfer_control 0x00020000 1 RW uint32 b[0:0] - - 1
- - - - rx_transfer_status 0x00020001 1 RO uint32 b[0:0] - - - - - - - rx_transfer_status 0x00020001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00020002 1 RW uint32 b[0:0] - - - - - - - tx_transfer_control 0x00020002 1 RW uint32 b[0:0] - - -
...@@ -515,13 +515,13 @@ number_of_columns = 13 ...@@ -515,13 +515,13 @@ number_of_columns = 13
- - - - - 0x00021c3b - - - b[31:0] b[31:0] - - - - - - - 0x00021c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00021c3c 1 RO uint64 b[3:0] b[35:32] - - - - - - tx_stats_pfcmacctrlframes 0x00021c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00021c3d - - - b[31:0] b[31:0] - - - - - - - 0x00021c3d - - - b[31:0] b[31:0] - -
REG_TR_10GBE_ETH10G 1 3 REG tx_snk_out_xon 0x000433f8 1 RO uint32 b[0:0] - - 1 REG_TR_10GBE_ETH10G 1 3 REG tx_snk_out_xon 0x00043218 1 RO uint32 b[0:0] - - 1
- - - - xgmii_tx_ready 0x000433f8 1 RO uint32 b[1:1] - - - - - - - xgmii_tx_ready 0x00043218 1 RO uint32 b[1:1] - - -
- - - - xgmii_link_status 0x000433f8 1 RO uint32 b[3:2] - - - - - - - xgmii_link_status 0x00043218 1 RO uint32 b[3:2] - - -
RAM_SS_SS_WIDE 2 6 RAM data 0x00030000 976 RW uint32 b[9:0] - 8192 1024 RAM_SS_SS_WIDE 2 6 RAM data 0x00030000 976 RW uint32 b[9:0] - 8192 1024
RAM_BF_WEIGHTS 2 12 RAM data 0x00028000 976 RW cint16_ir b[31:0] - 16384 1024 RAM_BF_WEIGHTS 2 12 RAM data 0x00028000 976 RW cint16_ir b[31:0] - 16384 1024
REG_BSN_ALIGN_V2_BF 2 2 REG enable 0x000433e0 1 RW uint32 b[0:0] - 1 2 REG_BSN_ALIGN_V2_BF 2 2 REG enable 0x00043208 1 RW uint32 b[0:0] - 1 2
- - - - replaced_pkt_cnt 0x000433e1 1 RO uint32 b[31:0] - - - - - - - replaced_pkt_cnt 0x00043209 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RX_ALIGN_BF 2 2 REG xon_stable 0x00000c20 1 RO uint32 b[0:0] - 1 8 REG_BSN_MONITOR_V2_RX_ALIGN_BF 2 2 REG xon_stable 0x00000c20 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x00000c20 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x00000c20 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000c20 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x00000c20 1 RO uint32 b[2:2] - - -
...@@ -531,154 +531,154 @@ number_of_columns = 13 ...@@ -531,154 +531,154 @@ number_of_columns = 13
- - - - nof_valid 0x00000c24 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x00000c24 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000c25 1 RO uint32 b[31:0] - - - - - - - nof_err 0x00000c25 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000c28 1 RO uint32 b[31:0] - - - - - - - latency 0x00000c28 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_ALIGNED_BF 2 1 REG xon_stable 0x00000c10 1 RO uint32 b[0:0] - 1 8 REG_BSN_MONITOR_V2_ALIGNED_BF 2 1 REG xon_stable 0x00043180 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x00000c10 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x00043180 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000c10 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x00043180 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00000c11 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x00043181 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c12 - - - b[31:0] b[63:32] - - - - - - - 0x00043182 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00000c13 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x00043183 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00000c14 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x00043184 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000c15 1 RO uint32 b[31:0] - - - - - - - nof_err 0x00043185 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000c18 1 RO uint32 b[31:0] - - - - - - - latency 0x00043188 1 RO uint32 b[31:0] - - -
REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x00000c04 1 RO uint32 b[0:0] - 1 2 REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x00043250 1 RO uint32 b[0:0] - 1 2
- - - - transport_nof_hops 0x00000c05 1 RW uint32 b[31:0] - - - - - - - transport_nof_hops 0x00043251 1 RW uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_RX_BF 2 16 REG xon_stable 0x00000d00 1 RO uint32 b[0:0] - 1 8 REG_BSN_MONITOR_V2_RING_RX_BF 2 1 REG xon_stable 0x00043170 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x00000d00 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x00043170 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000d00 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x00043170 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00000d01 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x00043171 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00000d02 - - - b[31:0] b[63:32] - - - - - - - 0x00043172 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00000d03 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x00043173 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00000d04 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x00043174 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000d05 1 RO uint32 b[31:0] - - - - - - - nof_err 0x00043175 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000d08 1 RO uint32 b[31:0] - - - - - - - latency 0x00043178 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_TX_BF 2 16 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - 1 8 REG_BSN_MONITOR_V2_RING_TX_BF 2 1 REG xon_stable 0x00043160 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x00043160 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x00043160 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x00043161 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00000102 - - - b[31:0] b[63:32] - - - - - - - 0x00043162 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x00043163 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x00043164 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - - - - - - nof_err 0x00043165 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000108 1 RO uint32 b[31:0] - - - - - - - latency 0x00043168 1 RO uint32 b[31:0] - - -
REG_DP_BLOCK_VALIDATE_ERR_BF 2 1 REG err_count_index 0x00000020 8 RO uint32 b[31:0] - 1 16 REG_DP_BLOCK_VALIDATE_ERR_BF 2 1 REG err_count_index 0x00000020 8 RO uint32 b[31:0] - 1 16
- - - - total_discarded_blocks 0x00000028 1 RO uint32 b[31:0] - - - - - - - total_discarded_blocks 0x00000028 1 RO uint32 b[31:0] - - -
- - - - total_block_count 0x00000029 1 RO uint32 b[31:0] - - - - - - - total_block_count 0x00000029 1 RO uint32 b[31:0] - - -
- - - - clear 0x0000002a 1 RW uint32 b[31:0] - - - - - - - clear 0x0000002a 1 RW uint32 b[31:0] - - -
REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF 2 1 REG nof_sync_discarded 0x00000c08 1 RO uint32 b[31:0] - 1 4 REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF 2 1 REG nof_sync_discarded 0x00043200 1 RO uint32 b[31:0] - 1 4
- - - - nof_sync 0x00000c09 1 RO uint32 b[31:0] - - - - - - - nof_sync 0x00043201 1 RO uint32 b[31:0] - - -
- - - - clear 0x00000c0a 1 RW uint32 b[31:0] - - - - - - - clear 0x00043202 1 RW uint32 b[31:0] - - -
REG_BF_SCALE 2 1 REG scale 0x00043444 1 RW uint32 b[15:0] - 2 2 REG_BF_SCALE 2 1 REG scale 0x00043264 1 RW uint32 b[15:0] - 2 2
- - - - unused 0x00043445 1 RW uint32 b[31:0] - - - - - - - unused 0x00043265 1 RW uint32 b[31:0] - - -
REG_HDR_DAT 2 1 REG bsn 0x00043200 1 RW uint64 b[31:0] b[31:0] 64 64 REG_HDR_DAT 2 1 REG bsn 0x00043000 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - 0x00043201 - - - b[31:0] b[63:32] - - - - - - - 0x00043001 - - - b[31:0] b[63:32] - -
- - - - sdp_block_period 0x00043202 1 RW uint32 b[15:0] - - - - - - - sdp_block_period 0x00043002 1 RW uint32 b[15:0] - - -
- - - - sdp_nof_beamlets_per_block 0x00043203 1 RW uint32 b[15:0] - - - - - - - sdp_nof_beamlets_per_block 0x00043003 1 RW uint32 b[15:0] - - -
- - - - sdp_nof_blocks_per_packet 0x00043204 1 RW uint32 b[7:0] - - - - - - - sdp_nof_blocks_per_packet 0x00043004 1 RW uint32 b[7:0] - - -
- - - - sdp_beamlet_index 0x00043205 1 RW uint32 b[15:0] - - - - - - - sdp_beamlet_index 0x00043005 1 RW uint32 b[15:0] - - -
- - - - sdp_beamlet_scale 0x00043206 1 RW uint32 b[15:0] - - - - - - - sdp_beamlet_scale 0x00043006 1 RW uint32 b[15:0] - - -
- - - - sdp_reserved 0x00043207 1 RW uint64 b[31:0] b[31:0] - - - - - - sdp_reserved 0x00043007 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00043208 - - - b[7:0] b[39:32] - - - - - - - 0x00043008 - - - b[7:0] b[39:32] - -
- - - - sdp_source_info_gn_index 0x00043209 1 RW uint32 b[4:0] - - - - - - - sdp_source_info_gn_index 0x00043009 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_beamlet_width 0x0004320a 1 RW uint32 b[7:5] - - - - - - - sdp_source_info_beamlet_width 0x0004300a 1 RW uint32 b[7:5] - - -
- - - - sdp_source_info_repositioning_flag 0x0004320b 1 RW uint32 b[9:9] - - - - - - - sdp_source_info_repositioning_flag 0x0004300b 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x0004320c 1 RW uint32 b[10:10] - - - - - - - sdp_source_info_payload_error 0x0004300c 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x0004320d 1 RW uint32 b[11:11] - - - - - - - sdp_source_info_fsub_type 0x0004300d 1 RW uint32 b[11:11] - - -
- - - - sdp_source_info_f_adc 0x0004320e 1 RW uint32 b[12:12] - - - - - - - sdp_source_info_f_adc 0x0004300e 1 RW uint32 b[12:12] - - -
- - - - sdp_source_info_nyquist_zone_index 0x0004320f 1 RW uint32 b[14:13] - - - - - - - sdp_source_info_nyquist_zone_index 0x0004300f 1 RW uint32 b[14:13] - - -
- - - - sdp_source_info_antenna_band_index 0x00043210 1 RW uint32 b[15:15] - - - - - - - sdp_source_info_antenna_band_index 0x00043010 1 RW uint32 b[15:15] - - -
- - - - sdp_station_id 0x00043211 1 RW uint32 b[15:0] - - - - - - - sdp_station_id 0x00043011 1 RW uint32 b[15:0] - - -
- - - - sdp_observation_id 0x00043212 1 RW uint32 b[31:0] - - - - - - - sdp_observation_id 0x00043012 1 RW uint32 b[31:0] - - -
- - - - sdp_version_id 0x00043213 1 RO uint32 b[7:0] - - - - - - - sdp_version_id 0x00043013 1 RO uint32 b[7:0] - - -
- - - - sdp_marker 0x00043214 1 RO uint32 b[7:0] - - - - - - - sdp_marker 0x00043014 1 RO uint32 b[7:0] - - -
- - - - udp_checksum 0x00043215 1 RW uint32 b[15:0] - - - - - - - udp_checksum 0x00043015 1 RW uint32 b[15:0] - - -
- - - - udp_length 0x00043216 1 RW uint32 b[15:0] - - - - - - - udp_length 0x00043016 1 RW uint32 b[15:0] - - -
- - - - udp_destination_port 0x00043217 1 RW uint32 b[15:0] - - - - - - - udp_destination_port 0x00043017 1 RW uint32 b[15:0] - - -
- - - - udp_source_port 0x00043218 1 RW uint32 b[15:0] - - - - - - - udp_source_port 0x00043018 1 RW uint32 b[15:0] - - -
- - - - ip_destination_address 0x00043219 1 RW uint32 b[31:0] - - - - - - - ip_destination_address 0x00043019 1 RW uint32 b[31:0] - - -
- - - - ip_source_address 0x0004321a 1 RW uint32 b[31:0] - - - - - - - ip_source_address 0x0004301a 1 RW uint32 b[31:0] - - -
- - - - ip_header_checksum 0x0004321b 1 RW uint32 b[15:0] - - - - - - - ip_header_checksum 0x0004301b 1 RW uint32 b[15:0] - - -
- - - - ip_protocol 0x0004321c 1 RW uint32 b[7:0] - - - - - - - ip_protocol 0x0004301c 1 RW uint32 b[7:0] - - -
- - - - ip_time_to_live 0x0004321d 1 RW uint32 b[7:0] - - - - - - - ip_time_to_live 0x0004301d 1 RW uint32 b[7:0] - - -
- - - - ip_fragment_offset 0x0004321e 1 RW uint32 b[12:0] - - - - - - - ip_fragment_offset 0x0004301e 1 RW uint32 b[12:0] - - -
- - - - ip_flags 0x0004321f 1 RW uint32 b[2:0] - - - - - - - ip_flags 0x0004301f 1 RW uint32 b[2:0] - - -
- - - - ip_identification 0x00043220 1 RW uint32 b[15:0] - - - - - - - ip_identification 0x00043020 1 RW uint32 b[15:0] - - -
- - - - ip_total_length 0x00043221 1 RW uint32 b[15:0] - - - - - - - ip_total_length 0x00043021 1 RW uint32 b[15:0] - - -
- - - - ip_services 0x00043222 1 RW uint32 b[7:0] - - - - - - - ip_services 0x00043022 1 RW uint32 b[7:0] - - -
- - - - ip_header_length 0x00043223 1 RW uint32 b[3:0] - - - - - - - ip_header_length 0x00043023 1 RW uint32 b[3:0] - - -
- - - - ip_version 0x00043224 1 RW uint32 b[3:0] - - - - - - - ip_version 0x00043024 1 RW uint32 b[3:0] - - -
- - - - eth_type 0x00043225 1 RO uint32 b[15:0] - - - - - - - eth_type 0x00043025 1 RO uint32 b[15:0] - - -
- - - - eth_source_mac 0x00043226 1 RO uint64 b[31:0] b[31:0] - - - - - - eth_source_mac 0x00043026 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00043227 - - - b[15:0] b[47:32] - - - - - - - 0x00043027 - - - b[15:0] b[47:32] - -
- - - - eth_destination_mac 0x00043228 1 RW uint64 b[31:0] b[31:0] - - - - - - eth_destination_mac 0x00043028 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00043229 - - - b[15:0] b[47:32] - - - - - - - 0x00043029 - - - b[15:0] b[47:32] - -
REG_DP_XONOFF 2 1 REG enable_stream 0x00043440 1 RW uint32 b[0:0] - 2 2 REG_DP_XONOFF 2 1 REG enable_stream 0x00043260 1 RW uint32 b[0:0] - 2 2
RAM_ST_BST 2 1 RAM data 0x00001000 976 RW uint64 b[31:0] b[31:0] 2048 2048 RAM_ST_BST 2 1 RAM data 0x00001000 976 RW uint64 b[31:0] b[31:0] 2048 2048
- - - - - 0x00001001 - - - b[21:0] b[53:32] - - - - - - - 0x00001001 - - - b[21:0] b[53:32] - -
REG_STAT_ENABLE_BST 2 1 REG enable 0x0004343c 1 RW uint32 b[0:0] - 2 2 REG_STAT_ENABLE_BST 2 1 REG enable 0x0004325c 1 RW uint32 b[0:0] - 2 2
REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00043180 1 RW uint64 b[31:0] b[31:0] 64 64 REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00000d80 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - 0x00043181 - - - b[31:0] b[63:32] - - - - - - - 0x00000d81 - - - b[31:0] b[63:32] - -
- - - - block_period 0x00043182 1 RW uint32 b[15:0] - - - - - - - block_period 0x00000d82 1 RW uint32 b[15:0] - - -
- - - - nof_statistics_per_packet 0x00043183 1 RW uint32 b[15:0] - - - - - - - nof_statistics_per_packet 0x00000d83 1 RW uint32 b[15:0] - - -
- - - - nof_bytes_per_statistic 0x00043184 1 RW uint32 b[7:0] - - - - - - - nof_bytes_per_statistic 0x00000d84 1 RW uint32 b[7:0] - - -
- - - - nof_signal_inputs 0x00043185 1 RW uint32 b[7:0] - - - - - - - nof_signal_inputs 0x00000d85 1 RW uint32 b[7:0] - - -
- - - - sdp_data_id 0x00043186 1 RW uint32 b[31:0] - - - - - - - sdp_data_id 0x00000d86 1 RW uint32 b[31:0] - - -
- - - - sdp_data_id_bst_beamlet_index 0x00043186 1 RW uint32 b[15:0] - - - - - - - sdp_data_id_bst_beamlet_index 0x00000d86 1 RW uint32 b[15:0] - - -
- - - - sdp_data_id_bst_reserved 0x00043186 1 RW uint32 b[31:16] - - - - - - - sdp_data_id_bst_reserved 0x00000d86 1 RW uint32 b[31:16] - - -
- - - - sdp_integration_interval 0x00043187 1 RW uint32 b[23:0] - - - - - - - sdp_integration_interval 0x00000d87 1 RW uint32 b[23:0] - - -
- - - - sdp_reserved 0x00043188 1 RW uint32 b[7:0] - - - - - - - sdp_reserved 0x00000d88 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x00043189 1 RW uint32 b[4:0] - - - - - - - sdp_source_info_gn_index 0x00000d89 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x0004318a 1 RW uint32 b[7:5] - - - - - - - sdp_source_info_reserved 0x00000d8a 1 RW uint32 b[7:5] - - -
- - - - sdp_source_info_weighted_subbands_flag 0x0004318b 1 RW uint32 b[8:8] - - - - - - - sdp_source_info_weighted_subbands_flag 0x00000d8b 1 RW uint32 b[8:8] - - -
- - - - sdp_source_info_beam_repositioning_flag 0x0004318c 1 RW uint32 b[9:9] - - - - - - - sdp_source_info_beam_repositioning_flag 0x00000d8c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x0004318d 1 RW uint32 b[10:10] - - - - - - - sdp_source_info_payload_error 0x00000d8d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x0004318e 1 RW uint32 b[11:11] - - - - - - - sdp_source_info_fsub_type 0x00000d8e 1 RW uint32 b[11:11] - - -
- - - - sdp_source_info_f_adc 0x0004318f 1 RW uint32 b[12:12] - - - - - - - sdp_source_info_f_adc 0x00000d8f 1 RW uint32 b[12:12] - - -
- - - - sdp_source_info_nyquist_zone_index 0x00043190 1 RW uint32 b[14:13] - - - - - - - sdp_source_info_nyquist_zone_index 0x00000d90 1 RW uint32 b[14:13] - - -
- - - - sdp_source_info_antenna_band_index 0x00043191 1 RW uint32 b[15:15] - - - - - - - sdp_source_info_antenna_band_index 0x00000d91 1 RW uint32 b[15:15] - - -
- - - - sdp_station_id 0x00043192 1 RW uint32 b[15:0] - - - - - - - sdp_station_id 0x00000d92 1 RW uint32 b[15:0] - - -
- - - - sdp_observation_id 0x00043193 1 RW uint32 b[31:0] - - - - - - - sdp_observation_id 0x00000d93 1 RW uint32 b[31:0] - - -
- - - - sdp_version_id 0x00043194 1 RO uint32 b[7:0] - - - - - - - sdp_version_id 0x00000d94 1 RO uint32 b[7:0] - - -
- - - - sdp_marker 0x00043195 1 RO uint32 b[7:0] - - - - - - - sdp_marker 0x00000d95 1 RO uint32 b[7:0] - - -
- - - - udp_checksum 0x00043196 1 RW uint32 b[15:0] - - - - - - - udp_checksum 0x00000d96 1 RW uint32 b[15:0] - - -
- - - - udp_length 0x00043197 1 RW uint32 b[15:0] - - - - - - - udp_length 0x00000d97 1 RW uint32 b[15:0] - - -
- - - - udp_destination_port 0x00043198 1 RW uint32 b[15:0] - - - - - - - udp_destination_port 0x00000d98 1 RW uint32 b[15:0] - - -
- - - - udp_source_port 0x00043199 1 RW uint32 b[15:0] - - - - - - - udp_source_port 0x00000d99 1 RW uint32 b[15:0] - - -
- - - - ip_destination_address 0x0004319a 1 RW uint32 b[31:0] - - - - - - - ip_destination_address 0x00000d9a 1 RW uint32 b[31:0] - - -
- - - - ip_source_address 0x0004319b 1 RW uint32 b[31:0] - - - - - - - ip_source_address 0x00000d9b 1 RW uint32 b[31:0] - - -
- - - - ip_header_checksum 0x0004319c 1 RW uint32 b[15:0] - - - - - - - ip_header_checksum 0x00000d9c 1 RW uint32 b[15:0] - - -
- - - - ip_protocol 0x0004319d 1 RW uint32 b[7:0] - - - - - - - ip_protocol 0x00000d9d 1 RW uint32 b[7:0] - - -
- - - - ip_time_to_live 0x0004319e 1 RW uint32 b[7:0] - - - - - - - ip_time_to_live 0x00000d9e 1 RW uint32 b[7:0] - - -
- - - - ip_fragment_offset 0x0004319f 1 RW uint32 b[12:0] - - - - - - - ip_fragment_offset 0x00000d9f 1 RW uint32 b[12:0] - - -
- - - - ip_flags 0x000431a0 1 RW uint32 b[2:0] - - - - - - - ip_flags 0x00000da0 1 RW uint32 b[2:0] - - -
- - - - ip_identification 0x000431a1 1 RW uint32 b[15:0] - - - - - - - ip_identification 0x00000da1 1 RW uint32 b[15:0] - - -
- - - - ip_total_length 0x000431a2 1 RW uint32 b[15:0] - - - - - - - ip_total_length 0x00000da2 1 RW uint32 b[15:0] - - -
- - - - ip_services 0x000431a3 1 RW uint32 b[7:0] - - - - - - - ip_services 0x00000da3 1 RW uint32 b[7:0] - - -
- - - - ip_header_length 0x000431a4 1 RW uint32 b[3:0] - - - - - - - ip_header_length 0x00000da4 1 RW uint32 b[3:0] - - -
- - - - ip_version 0x000431a5 1 RW uint32 b[3:0] - - - - - - - ip_version 0x00000da5 1 RW uint32 b[3:0] - - -
- - - - eth_type 0x000431a6 1 RO uint32 b[15:0] - - - - - - - eth_type 0x00000da6 1 RO uint32 b[15:0] - - -
- - - - eth_source_mac 0x000431a7 1 RO uint64 b[31:0] b[31:0] - - - - - - eth_source_mac 0x00000da7 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x000431a8 - - - b[15:0] b[47:32] - - - - - - - 0x00000da8 - - - b[15:0] b[47:32] - -
- - - - eth_destination_mac 0x000431a9 1 RW uint64 b[31:0] b[31:0] - - - - - - eth_destination_mac 0x00000da9 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x000431aa - - - b[15:0] b[47:32] - - - - - - - 0x00000daa - - - b[15:0] b[47:32] - -
- - - - word_align 0x000431ab 1 RW uint32 b[15:0] - - - - - - - word_align 0x00000dab 1 RW uint32 b[15:0] - - -
REG_BSN_MONITOR_V2_BST_OFFLOAD 2 1 REG xon_stable 0x00043380 1 RO uint32 b[0:0] - 1 8 REG_BSN_MONITOR_V2_BST_OFFLOAD 2 1 REG xon_stable 0x000431a0 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x00043380 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x000431a0 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00043380 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x000431a0 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00043381 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x000431a1 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00043382 - - - b[31:0] b[63:32] - - - - - - - 0x000431a2 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00043383 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x000431a3 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00043384 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x000431a4 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00043385 1 RO uint32 b[31:0] - - - - - - - nof_err 0x000431a5 1 RO uint32 b[31:0] - - -
- - - - latency 0x00043388 1 RO uint32 b[31:0] - - - - - - - latency 0x000431a8 1 RO uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_BEAMLET_OUTPUT 2 1 REG xon_stable 0x00043370 1 RO uint32 b[0:0] - 1 8 REG_BSN_MONITOR_V2_BEAMLET_OUTPUT 2 1 REG xon_stable 0x00043190 1 RO uint32 b[0:0] - 1 8
- - - - ready_stable 0x00043370 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x00043190 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00043370 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x00043190 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00043371 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x00043191 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00043372 - - - b[31:0] b[63:32] - - - - - - - 0x00043192 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00043373 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x00043193 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00043374 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x00043194 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00043375 1 RO uint32 b[31:0] - - - - - - - nof_err 0x00043195 1 RO uint32 b[31:0] - - -
- - - - latency 0x00043378 1 RO uint32 b[31:0] - - - - - - - latency 0x00043198 1 RO uint32 b[31:0] - - -
REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00006000 1 RW uint32 b[0:0] - - - REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00006000 1 RW uint32 b[0:0] - - -
- - - - rx_transfer_status 0x00006001 1 RO uint32 b[0:0] - - - - - - - rx_transfer_status 0x00006001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00006002 1 RW uint32 b[0:0] - - - - - - - tx_transfer_control 0x00006002 1 RW uint32 b[0:0] - - -
...@@ -855,6 +855,6 @@ number_of_columns = 13 ...@@ -855,6 +855,6 @@ number_of_columns = 13
- - - - - 0x00007c3b - - - b[31:0] b[31:0] - - - - - - - 0x00007c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00007c3c 1 RO uint64 b[3:0] b[35:32] - - - - - - tx_stats_pfcmacctrlframes 0x00007c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00007c3d - - - b[31:0] b[31:0] - - - - - - - 0x00007c3d - - - b[31:0] b[31:0] - -
REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x00043454 1 RO uint32 b[0:0] - - - REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x00043274 1 RO uint32 b[0:0] - - -
- - - - xgmii_tx_ready 0x00043454 1 RO uint32 b[1:1] - - - - - - - xgmii_tx_ready 0x00043274 1 RO uint32 b[1:1] - - -
- - - - xgmii_link_status 0x00043454 1 RO uint32 b[3:2] - - - - - - - xgmii_link_status 0x00043274 1 RO uint32 b[3:2] - - -
\ No newline at end of file \ No newline at end of file
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment