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Commit 3b9d2701 authored by Eric Kooistra's avatar Eric Kooistra
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Ported tse_sgmii_gx v9.1 from $UNB to ip_stratix_tse_sgmii_gx in $RADIOHDL.

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hdl_lib_name = ip_stratixiv_tse_sgmii_gx
hdl_library_clause_name = ip_stratixiv_tse_sgmii_gx_lib
hdl_lib_uses = technology
build_sim_dir = $HDL_BUILD_DIR
build_synth_dir =
synth_files =
ip_stratixiv_tse_sgmii_gx.vho
test_bench_files =
set_global_assignment -name IP_TOOL_NAME "Triple Speed Ethernet"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ip_stratixiv_tse_sgmii_gx.vhd"]
set_global_assignment -name SEARCH_PATH [file join $::quartus(qip_path) "." ]
set_global_assignment -name SEARCH_PATH [file join $::quartus(qip_path) triple_speed_ethernet-library ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rgmii_in4.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_mdio.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_ff_cntrl.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_sgmii.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_alt2gxb_basic.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_multi_mac_pcs_pma.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mdio.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_multi_mac_pcs.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_a_fifo_opt_1246.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_dpram_8x32.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_pcs_pma_gige.v ]
set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_1000_base_x.ocp ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_pma_lvds_rx.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_altgx_civgx_gige.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_a_fifo_opt_14_44.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_control.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_dc_fifo.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mii_tx_if.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_crc32ctl8.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_pcs_pma.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_sync.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_sgmii_clk_cntl.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_min_ff.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_register_map.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_pcs_pma_strx_gx_ena.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_alt4gxb_gige.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_bin_cnt.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_pcs.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_a_fifo_34.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_dec_func.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_crc32galois8.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_pcs_control.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_tx_converter.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mdio_cntl.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_encapsulation.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mdio_clk_gen.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_gmii_io.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_counter_cntl.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_lfsr_10.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_fifoless_mac_rx.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_ff_cntrl_32.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_fifoless_mac_tx.v ]
set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_1000_base_x_strx_gx.ocp ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_a_fifo_24.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_clk_gen.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_rx_converter.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_crc328checker.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_gxb_gige_inst.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_carrier_sense.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_pcs_pma_gige.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_multi_mac_pcs_pma_gige.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_loopback_ff.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rgmii_module.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mii_rx_if_pcs.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_crc328generator.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_altshifttaps.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_counter_cntl.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_geth_pcs_wo_ratematch.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_rx.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_encapsulation_strx_gx.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_1000_base_x_strx_gx.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_altsyncram_dpm_fifo.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_ff.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_tx.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_ff_length.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_quad_8x32.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_alt2gxb_arriagx.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_multi_mac_pcs_gige.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_ff.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_gxb_aligned_rxsync.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_fifoless_1geth.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_encapsulation.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_fifo_rd.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_dpram_16x32.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_hashing.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_ff_cntrl_32_shift16.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rgmii_in1.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_retransmit_cntl.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_multi_mac.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mii_tx_if_pcs.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_ff_cntrl.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_shared_mac_control.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_wo_fifo.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_multi_mac_pcs.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_pma_lvds_tx.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_a_fifo_13.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_converter.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_host_control.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_gray_cnt.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_ff_cntrl_32.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_fifoless_retransmit_cntl.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_sgmii_clk_enable.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_timing_adapter_fifo8.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_pcs.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_pcs_host_control.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_enc8b10b.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_pcs_pma_ena.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_gen_host.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_1000_base_x.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_multi_channel_arbiter.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rgmii_out1.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_pcs_pma.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_align_sync.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_stat_extract.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_sdpm_gen.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_dec10b8b.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_lb_read_cntl.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_alt2gxb_gige.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_colision_detect.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_min_ff.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_1geth.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rx_ff_length.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_converter.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_gige_reset_ctrl.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_sgmii_clk_scheduler.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_timing_adapter_fifo32.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_timing_adapter32.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_rgmii_out4.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_ff_cntrl_32_shift16.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_tx.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_pcs_gige_woff.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_pcs.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_host_control_small.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_quad_16x32.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_autoneg.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_a_fifo_opt_36_10.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mdio_reg.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_w_fifo.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_multi_mac.v ]
set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_woff.ocp ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_timing_adapter8.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_w_fifo_10_100_1000.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_register_map_small.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_pcs_strx_gx.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mii_rx_if.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_magic_detection.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_shared_register_map.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_rx.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_sgmii_strx_gx.v ]
set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_gen_host.ocp ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_pcs_woff.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_top_wo_fifo_10_100_1000.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_clk_cntl.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_sdpm_altsyncram.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_mac_woff.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_ff_read_cntl.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_sgmii_clk_div.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_lb_wrt_cntl.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) triple_speed_ethernet-library/altera_tse_tx_stat_extract.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_stratixiv_tse_sgmii_gx.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_stratixiv_tse_sgmii_gx.vho ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_stratixiv_tse_sgmii_gx.qip ]
-- megafunction wizard: %Triple Speed Ethernet v9.1%
-- GENERATION: XML
-- ============================================================
-- Megafunction Name(s):
-- altera_tse_mac_pcs_pma_gige
-- ============================================================
-- Generated by Triple Speed Ethernet 9.1 [Altera, IP Toolbench 1.3.0 Build 350]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2014 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY ip_stratixiv_tse_sgmii_gx IS
PORT (
ff_tx_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ff_tx_eop : IN STD_LOGIC;
ff_tx_err : IN STD_LOGIC;
ff_tx_mod : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ff_tx_sop : IN STD_LOGIC;
ff_tx_wren : IN STD_LOGIC;
ff_tx_clk : IN STD_LOGIC;
ff_rx_rdy : IN STD_LOGIC;
ff_rx_clk : IN STD_LOGIC;
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
read : IN STD_LOGIC;
writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
write : IN STD_LOGIC;
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
rxp : IN STD_LOGIC;
ref_clk : IN STD_LOGIC;
reconfig_clk : IN STD_LOGIC;
reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
ff_tx_crc_fwd : IN STD_LOGIC;
gxb_cal_blk_clk : IN STD_LOGIC;
ff_tx_rdy : OUT STD_LOGIC;
ff_rx_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ff_rx_dval : OUT STD_LOGIC;
ff_rx_eop : OUT STD_LOGIC;
ff_rx_mod : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
ff_rx_sop : OUT STD_LOGIC;
rx_err : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
waitrequest : OUT STD_LOGIC;
led_an : OUT STD_LOGIC;
led_char_err : OUT STD_LOGIC;
led_link : OUT STD_LOGIC;
led_disp_err : OUT STD_LOGIC;
txp : OUT STD_LOGIC;
reconfig_fromgxb : OUT STD_LOGIC_VECTOR (16 DOWNTO 0);
ff_tx_septy : OUT STD_LOGIC;
tx_ff_uflow : OUT STD_LOGIC;
ff_tx_a_full : OUT STD_LOGIC;
ff_tx_a_empty : OUT STD_LOGIC;
rx_err_stat : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
rx_frm_type : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
ff_rx_dsav : OUT STD_LOGIC;
ff_rx_a_full : OUT STD_LOGIC;
ff_rx_a_empty : OUT STD_LOGIC
);
END ip_stratixiv_tse_sgmii_gx;
ARCHITECTURE SYN OF ip_stratixiv_tse_sgmii_gx IS
COMPONENT altera_tse_mac_pcs_pma_gige
GENERIC (
ENABLE_MAGIC_DETECT : NATURAL;
ENABLE_MDIO : NATURAL;
ENABLE_SHIFT16 : NATURAL;
ENABLE_SUP_ADDR : NATURAL;
CORE_VERSION : STD_LOGIC_VECTOR := X"0901";
CRC32GENDELAY : NATURAL;
MDIO_CLK_DIV : NATURAL;
ENA_HASH : NATURAL;
USE_SYNC_RESET : NATURAL;
STAT_CNT_ENA : NATURAL;
ENABLE_EXTENDED_STAT_REG : NATURAL;
ENABLE_HD_LOGIC : NATURAL;
REDUCED_INTERFACE_ENA : NATURAL;
CRC32S1L2_EXTERN : NATURAL;
ENABLE_GMII_LOOPBACK : NATURAL;
CRC32DWIDTH : NATURAL;
CUST_VERSION : NATURAL;
RESET_LEVEL : STD_LOGIC_VECTOR := X"01";
CRC32CHECK16BIT : STD_LOGIC_VECTOR := X"00";
ENABLE_MAC_FLOW_CTRL : NATURAL;
ENABLE_MAC_TXADDR_SET : NATURAL;
ENABLE_MAC_RX_VLAN : NATURAL;
ENABLE_MAC_TX_VLAN : NATURAL;
SYNCHRONIZER_DEPTH : NATURAL;
EG_FIFO : NATURAL;
EG_ADDR : NATURAL;
ING_FIFO : NATURAL;
ENABLE_ENA : NATURAL;
ING_ADDR : NATURAL;
RAM_TYPE : STRING;
INSERT_TA : NATURAL;
ENABLE_MACLITE : NATURAL;
MACLITE_GIGE : NATURAL;
PHY_IDENTIFIER : STD_LOGIC_VECTOR := X"00000000";
DEV_VERSION : STD_LOGIC_VECTOR := X"0901";
ENABLE_SGMII : NATURAL;
DEVICE_FAMILY : STRING;
EXPORT_PWRDN : NATURAL;
TRANSCEIVER_OPTION : NATURAL;
ENABLE_ALT_RECONFIG : NATURAL
);
PORT (
ff_tx_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ff_tx_eop : IN STD_LOGIC;
ff_tx_err : IN STD_LOGIC;
ff_tx_mod : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ff_tx_sop : IN STD_LOGIC;
ff_tx_wren : IN STD_LOGIC;
ff_tx_clk : IN STD_LOGIC;
ff_rx_rdy : IN STD_LOGIC;
ff_rx_clk : IN STD_LOGIC;
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
read : IN STD_LOGIC;
writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
write : IN STD_LOGIC;
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
rxp : IN STD_LOGIC;
ref_clk : IN STD_LOGIC;
reconfig_clk : IN STD_LOGIC;
reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
ff_tx_crc_fwd : IN STD_LOGIC;
gxb_cal_blk_clk : IN STD_LOGIC;
ff_tx_rdy : OUT STD_LOGIC;
ff_rx_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ff_rx_dval : OUT STD_LOGIC;
ff_rx_eop : OUT STD_LOGIC;
ff_rx_mod : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
ff_rx_sop : OUT STD_LOGIC;
rx_err : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
waitrequest : OUT STD_LOGIC;
led_an : OUT STD_LOGIC;
led_char_err : OUT STD_LOGIC;
led_link : OUT STD_LOGIC;
led_disp_err : OUT STD_LOGIC;
txp : OUT STD_LOGIC;
reconfig_fromgxb : OUT STD_LOGIC_VECTOR (16 DOWNTO 0);
ff_tx_septy : OUT STD_LOGIC;
tx_ff_uflow : OUT STD_LOGIC;
ff_tx_a_full : OUT STD_LOGIC;
ff_tx_a_empty : OUT STD_LOGIC;
rx_err_stat : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
rx_frm_type : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
ff_rx_dsav : OUT STD_LOGIC;
ff_rx_a_full : OUT STD_LOGIC;
ff_rx_a_empty : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
altera_tse_mac_pcs_pma_gige_inst : altera_tse_mac_pcs_pma_gige
GENERIC MAP (
ENABLE_MAGIC_DETECT => 0,
ENABLE_MDIO => 0,
ENABLE_SHIFT16 => 1,
ENABLE_SUP_ADDR => 0,
CORE_VERSION => X"0901",
CRC32GENDELAY => 6,
MDIO_CLK_DIV => 40,
ENA_HASH => 0,
USE_SYNC_RESET => 0,
STAT_CNT_ENA => 0,
ENABLE_EXTENDED_STAT_REG => 0,
ENABLE_HD_LOGIC => 0,
REDUCED_INTERFACE_ENA => 0,
CRC32S1L2_EXTERN => 0,
ENABLE_GMII_LOOPBACK => 1,
CRC32DWIDTH => 8,
CUST_VERSION => 0,
RESET_LEVEL => X"01",
CRC32CHECK16BIT => X"00",
ENABLE_MAC_FLOW_CTRL => 0,
ENABLE_MAC_TXADDR_SET => 1,
ENABLE_MAC_RX_VLAN => 0,
ENABLE_MAC_TX_VLAN => 0,
SYNCHRONIZER_DEPTH => 4,
EG_FIFO => 256,
EG_ADDR => 8,
ING_FIFO => 256,
ENABLE_ENA => 32,
ING_ADDR => 8,
RAM_TYPE => "M9K",
INSERT_TA => 0,
ENABLE_MACLITE => 0,
MACLITE_GIGE => 0,
PHY_IDENTIFIER => X"00000000",
DEV_VERSION => X"0901",
ENABLE_SGMII => 0,
DEVICE_FAMILY => "STRATIXIV",
EXPORT_PWRDN => 0,
TRANSCEIVER_OPTION => 0,
ENABLE_ALT_RECONFIG => 1
)
PORT MAP (
ff_tx_data => ff_tx_data,
ff_tx_eop => ff_tx_eop,
ff_tx_err => ff_tx_err,
ff_tx_mod => ff_tx_mod,
ff_tx_rdy => ff_tx_rdy,
ff_tx_sop => ff_tx_sop,
ff_tx_wren => ff_tx_wren,
ff_tx_clk => ff_tx_clk,
ff_rx_data => ff_rx_data,
ff_rx_dval => ff_rx_dval,
ff_rx_eop => ff_rx_eop,
ff_rx_mod => ff_rx_mod,
ff_rx_rdy => ff_rx_rdy,
ff_rx_sop => ff_rx_sop,
rx_err => rx_err,
ff_rx_clk => ff_rx_clk,
address => address,
readdata => readdata,
read => read,
writedata => writedata,
write => write,
waitrequest => waitrequest,
clk => clk,
reset => reset,
led_an => led_an,
led_char_err => led_char_err,
led_link => led_link,
led_disp_err => led_disp_err,
txp => txp,
rxp => rxp,
ref_clk => ref_clk,
reconfig_clk => reconfig_clk,
reconfig_togxb => reconfig_togxb,
reconfig_fromgxb => reconfig_fromgxb,
ff_tx_crc_fwd => ff_tx_crc_fwd,
ff_tx_septy => ff_tx_septy,
tx_ff_uflow => tx_ff_uflow,
ff_tx_a_full => ff_tx_a_full,
ff_tx_a_empty => ff_tx_a_empty,
rx_err_stat => rx_err_stat,
rx_frm_type => rx_frm_type,
ff_rx_dsav => ff_rx_dsav,
ff_rx_a_full => ff_rx_a_full,
ff_rx_a_empty => ff_rx_a_empty,
gxb_cal_blk_clk => gxb_cal_blk_clk
);
END SYN;
-- =========================================================
-- Triple Speed Ethernet Wizard Data
-- ===============================
-- DO NOT EDIT FOLLOWING DATA
-- @Altera, IP Toolbench@
-- Warning: If you modify this section, Triple Speed Ethernet Wizard may not be able to reproduce your chosen configuration.
--
-- Retrieval info: <?xml version="1.0"?>
-- Retrieval info: <MEGACORE title="Triple Speed Ethernet MegaCore Function" version="9.1" build="350" iptb_version="1.3.0 Build 350" format_version="120" >
-- Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.TSEMVCModel" active_core="altera_tse_mac_pcs_pma_gige" >
-- Retrieval info: <STATIC_SECTION>
-- Retrieval info: <PRIVATES>
-- Retrieval info: <NAMESPACE name = "parameterization">
-- Retrieval info: <PRIVATE name = "atlanticSinkClockRate" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "atlanticSinkClockSource" value="unassigned" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "atlanticSourceClockRate" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "atlanticSourceClockSource" value="unassigned" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "avalonSlaveClockRate" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "avalonSlaveClockSource" value="unassigned" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "avalonStNeighbours" value="{}" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "channel_count" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "core_variation" value="MAC_PCS" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "core_version" value="2305" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "crc32dwidth" value="8" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "crc32gendelay" value="6" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "crc32s1l2_extern" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "cust_version" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "dataBitsPerSymbol" value="8" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "dev_version" value="2305" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "deviceFamily" value="STRATIXIV" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "eg_addr" value="8" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "eg_fifo" value="256" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "ena_hash" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_alt_reconfig" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_clk_sharing" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_ena" value="32" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_fifoless" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_gmii_loopback" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_hd_logic" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_mac_flow_ctrl" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_mac_txaddr_set" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_mac_vlan" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_maclite" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_magic_detect" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_multi_channel" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_pkt_class" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_pma" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_reg_sharing" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_sgmii" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_shift16" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_sup_addr" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "enable_use_internal_fifo" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "export_calblkclk" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "export_pwrdn" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "ext_stat_cnt_ena" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "gigeAdvanceMode" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "ifGMII" value="MII_GMII" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ifPCSuseEmbeddedSerdes" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "ing_addr" value="8" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "ing_fifo" value="256" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "insert_ta" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "maclite_gige" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "max_channels" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "mdio_clk_div" value="40" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "phy_identifier" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ramType" value="M9K" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "sopcSystemTopLevelName" value="system" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "stat_cnt_ena" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "timingAdapterName" value="timingAdapter" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "toolContext" value="STANDALONE" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "transceiver_type" value="GXB" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiEgFIFOSize" value="256 x 32 Bits" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiHostClockFrequency" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "uiIngFIFOSize" value="256 x 32 Bits" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiMACFIFO" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "uiMACOptions" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "uiMDIOFreq" value="0.0 MHz" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiMIIInterfaceOptions" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCSInterface" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCSInterfaceOptions" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "useLvds" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "useMAC" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "useMDIO" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "usePCS" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "use_sync_reset" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "simgen_enable">
-- Retrieval info: <PRIVATE name = "language" value="VHDL" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "enabled" value="1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "gb_enabled" value="0" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "testbench">
-- Retrieval info: <PRIVATE name = "variation_name" value="ip_stratixiv_tse_sgmii_gx" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "project_name" value="system" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "output_name" value="ip_stratixiv_tse_sgmii_gx" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "tool_context" value="STANDALONE" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "constraint_file_generator">
-- Retrieval info: <PRIVATE name = "variation_name" value="ip_stratixiv_tse_sgmii_gx" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "instance_name" value="ip_stratixiv_tse_sgmii_gx" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "output_name" value="ip_stratixiv_tse_sgmii_gx" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "modelsim_script_generator">
-- Retrieval info: <PRIVATE name = "variation_name" value="ip_stratixiv_tse_sgmii_gx" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "instance_name" value="ip_stratixiv_tse_sgmii_gx" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "plugin_worker" value="1" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "europa_executor">
-- Retrieval info: <PRIVATE name = "plugin_worker" value="0" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "simgen">
-- Retrieval info: <PRIVATE name = "use_alt_top" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "filename" value="ip_stratixiv_tse_sgmii_gx.vho" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "modelsim_wave_script_plugin">
-- Retrieval info: <PRIVATE name = "plugin_worker" value="1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "output_name" value="ip_stratixiv_tse_sgmii_gx" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "nativelink">
-- Retrieval info: <PRIVATE name = "plugin_worker" value="1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "language" value="VHDL" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "output_name" value="ip_stratixiv_tse_sgmii_gx" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "variation_name" value="ip_stratixiv_tse_sgmii_gx" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "top_level_name" value="ip_stratixiv_tse_sgmii_gx" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "greybox">
-- Retrieval info: <PRIVATE name = "filename" value="ip_stratixiv_tse_sgmii_gx_syn.v" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "serializer"/>
-- Retrieval info: <NAMESPACE name = "settings">
-- Retrieval info: <PRIVATE name = "WEB_BROWSER" value="/usr/bin/firefox" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "quartus_settings">
-- Retrieval info: <PRIVATE name = "WEB_BROWSER" value="/usr/bin/firefox" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: </PRIVATES>
-- Retrieval info: <FILES/>
-- Retrieval info: <PORTS/>
-- Retrieval info: <LIBRARIES/>
-- Retrieval info: </STATIC_SECTION>
-- Retrieval info: </NETLIST_SECTION>
-- Retrieval info: </MEGACORE>
-- =========================================================
-- RELATED_FILES: ip_stratixiv_tse_sgmii_gx.vhd, altera_tse_mac_pcs_pma_gige.v;
-- IPFS_FILES: ip_stratixiv_tse_sgmii_gx.vho;
-- =========================================================
Source diff could not be displayed: it is too large. Options to address this: view the blob.
#####################################################################################
# Copyright (C) 1991-2009 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any other
# associated documentation or information provided by Altera or a partner
# under Altera's Megafunction Partnership Program may be used only
# to program PLD devices (but not masked PLD devices) from Altera. Any
# other use of such megafunction design, netlist, support information,
# device programming or simulation file, or any other related documentation
# or information is prohibited for any other purpose, including, but not
# limited to modification, reverse engineering, de-compiling, or use with
# any other silicon devices, unless such use is explicitly licensed under
# a separate agreement with Altera or a megafunction partner. Title to the
# intellectual property, including patents, copyrights, trademarks, trade
# secrets, or maskworks, embodied in any such megafunction design, netlist,
# support information, device programming or simulation file, or any other
# related documentation or information provided by Altera or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.
#####################################################################################
#####################################################################################
# Altera Triple-Speed Ethernet Megacore SDC file for use with the Quartus II
# TimeQuest Timing Analyzer
#
# To add this SDC file to your Quartus II project execute the following TCL
# command in the Quartus II TCL console:
# set_global_assignment -name SDC_FILE "ip_stratixiv_tse_sgmii_gx"_constraints.sdc
#
# Generated on Fri Mar 07 15:43:49 CET 2014
#
#####################################################################################
# *************************************************************
# Customer modifiable constraints, value is set default by constraints
# *************************************************************
set SYSTEM_PATH_PREFIX ""
set TSE_CLOCK_FREQUENCY "125 MHz"
set FIFO_CLOCK_FREQUENCY "100 MHz"
set DEFAULT_SYSTEM_CLOCK_SPEED "66 MHz"
# name the clocks that will be coming into the tse core named changed from top level
set TX_CLK "tx_clk"
set RX_CLK "rx_clk"
set CLK "clk"
set FF_TX_CLK "ff_tx_clk"
set FF_RX_CLK "ff_rx_clk"
set TBI_TX_CLK "tbi_tx_clk"
set TBI_RX_CLK "tbi_rx_clk"
set REF_CLK "ref_clk"
# General Option
set IS_SOPC 0
set VARIATION_NAME "ip_stratixiv_tse_sgmii_gx"
set DEVICE_FAMILY "STRATIXIV"
# MAC Option
set IS_MAC 1
set NUMBER_OF_CHANNEL 1
set IS_SMALLMAC 0
set IS_SMALLMAC_GIGE 0
set IS_FIFOLESS 0
set IS_HALFDUPLEX 0
set MII_INTERFACE "MII_GMII"
# PCS Option
set IS_PCS 1
set IS_SGMII 0
# PMA Option
set IS_PMA 1
set TRANSCEIVER_TYPE 0
# GXB Option
set IS_POWERDOWN 0
# ********************** Please do not modify anything beyond this line ****************************
# *********** The script might not work correctly if the following lines are modified **************
if { [ expr ($TRANSCEIVER_TYPE == 0)]} {
set CLOCK_1 "U_RXCLK"
set CLOCK_2 "U_TXCLK"
} else {
set CLOCK_1 "U_RXCLK"
set CLOCK_2 "U_TXCLK"
}
if { [ expr ($IS_SOPC == 1) ]} {
set FROM_THE_VARIATION_NAME "_from_the_$VARIATION_NAME"
set TO_THE_VARIATION_NAME "_to_the_$VARIATION_NAME"
} else {
set FROM_THE_VARIATION_NAME ""
set TO_THE_VARIATION_NAME ""
}
#**************************************************************
# Time Information
#**************************************************************
# Uncommenting one of the following derive_pll_clocks lines
# will instruct the TimeQuest Timing Analyzer to automatically
# create derived clocks for all PLL outputs for all PLLs in a
# Quartus design.
# If the PLL inputs are constrained elsewhere, uncomment the
# next line to automatically constrain all PLL output clocks.
# derive_pll_clocks
# If the PLL inputs are not constrained elsewhere, uncomment
# the next line to automatically constrain all PLL input and
# output clocks.
# derive_pll_clocks -create_base_clocks
#**************************************************************
#**************************************************************
# Create Clock
#**************************************************************
#Constrain timing for half duplex logic
# - Direct path as we are confirmed of this path
if { [ expr ( $IS_FIFOLESS == 0 )] } {
# mac
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 0) && ($IS_PMA == 0)] } {
#Constrain MAC control interface clock
create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_${CLK}_$TO_THE_VARIATION_NAME [ get_ports $CLK]
#Constrain MAC FIFO data interface clocks
create_clock -period "$FIFO_CLOCK_FREQUENCY" -name altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $FF_TX_CLK]
create_clock -period "$FIFO_CLOCK_FREQUENCY" -name altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $FF_RX_CLK]
#Constrain MAC network-side interface clocks
create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TX_CLK]
create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $RX_CLK]
}
# macPcs
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 0) ] } {
#Constrain MAC PCS control interface clock
create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_${CLK}_$TO_THE_VARIATION_NAME [ get_ports $CLK]
#Constrain MAC PCS FIFO data interface clocks
create_clock -period "$FIFO_CLOCK_FREQUENCY" -name altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $FF_TX_CLK]
create_clock -period "$FIFO_CLOCK_FREQUENCY" -name altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $FF_RX_CLK]
#Constrain MAC PCS network-side interface clocks
create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TBI_RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TBI_RX_CLK]
create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TBI_TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TBI_TX_CLK]
}
# macPcsPma
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) ] } {
#Constrain transceiver reference clock
create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME [ get_ports $REF_CLK]
#Constrain MAC PCS control interface clock
create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_${CLK}_$TO_THE_VARIATION_NAME [ get_ports $CLK]
#Constrain MAC PCS FIFO data interface clocks
create_clock -period "$FIFO_CLOCK_FREQUENCY" -name altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $FF_TX_CLK]
create_clock -period "$FIFO_CLOCK_FREQUENCY" -name altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $FF_RX_CLK]
}
# pcs
if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 0) ] } {
#Cut the timing path betweeen unrelated clock domains
}
# pcsPma
if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) ] } {
#Constrain PCS control interface clock
create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_${CLK}_$TO_THE_VARIATION_NAME [ get_ports clk]
#Constrain transceiver reference clock
create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME [ get_ports $REF_CLK]
}
# macPcsSgmii
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 0) && ($IS_SGMII == 1)] } {
}
# macPcsNoSgmii
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 0) && ($IS_SGMII == 0)] } {
}
# macPcsPmaSgmii
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1)] } {
}
# macPcsPmaNoSgmii
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0)] } {
}
# pmaAlt4Gxb
if { [expr ($TRANSCEIVER_TYPE == 0) && ($IS_PMA == 1) && (([string match $DEVICE_FAMILY "STRATIXIV"]) || ([string match $DEVICE_FAMILY "ARRIAIIGX"]) || ([string match $DEVICE_FAMILY "HARDCOPYIV"]) ) ] } {
}
# pcsSgmii
if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 0) && ($IS_SGMII == 1)] } {
#Constrain PCS GMII/MII interface clocks
create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_REG_CLK_$TO_THE_VARIATION_NAME [ get_ports reg_clk]
create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TBI_RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TBI_RX_CLK]
create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TBI_TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TBI_TX_CLK]
}
# pcsNoSgmii
if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 0) && ($IS_SGMII == 0)] } {
#Constrain PCS control interface clock
create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_REG_CLK_$TO_THE_VARIATION_NAME [ get_ports reg_clk]
#Constrain PCS network-side interface clocks
create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TBI_RX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TBI_RX_CLK]
create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_${TBI_TX_CLK}_$TO_THE_VARIATION_NAME [ get_ports $TBI_TX_CLK]
}
# pcsPmaSgmii
if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1)] } {
#Constrain PCS GMII/MII interface clocks
}
derive_pll_clocks
# pcsPmaNoSgmii
if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1)] } {
}
# macPcsPmaLvdsSgmii
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1) && ($TRANSCEIVER_TYPE == 1)] } {
#Cut the timing path betweeen unrelated clock domains
}
# macPcsPmaLvdsNoSgmii
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0) && ($TRANSCEIVER_TYPE == 1)] } {
}
# macPcsPmaTransceiverSgmii=
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1) && ($TRANSCEIVER_TYPE == 0) && (([string match $DEVICE_FAMILY "STRATIXIIGX"]) || ([string match $DEVICE_FAMILY "ARRIAGX"]))] } {
#Cut the timing path betweeen unrelated clock domains
set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|refclkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${TX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|clkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${TX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_quad[0].pll0|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${TX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_tx[0].transmit|clkout }]
}
# macPcsPmaTransceiverNoSgmii=
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0) && ($TRANSCEIVER_TYPE == 0) && (([string match $DEVICE_FAMILY "STRATIXIIGX"]) || ([string match $DEVICE_FAMILY "ARRIAGX"]))] } {
#Cut the timing path betweeen unrelated clock domains
set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|refclkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|clkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_quad[0].pll0|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_TX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${FF_RX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_tx[0].transmit|clkout }]
}
# pcsPmaLvdsSgmii=
if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1) && ($TRANSCEIVER_TYPE == 1)] } {
#Cut the timing path betweeen unrelated clock domains
}
# pcsPmaLvdsNoSgmii
if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0) && ($TRANSCEIVER_TYPE == 1)] } {
}
# pcsPmaTransceiverSgmii
if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1) && ($TRANSCEIVER_TYPE == 0) && (([string match $DEVICE_FAMILY "STRATIXIIGX"]) || ([string match $DEVICE_FAMILY "ARRIAGX"])) ] } {
#Cut the timing path betweeen unrelated clock domains
set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|refclkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${TSE_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|clkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${TX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_quad[0].pll0|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME altera_tse_${RX_CLK}_$TO_THE_VARIATION_NAME altera_tse_${TX_CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_tx[0].transmit|clkout }]
}
# pcsPmaTransceiverNoSgmii
if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0) && ($TRANSCEIVER_TYPE == 0) && (([string match $DEVICE_FAMILY "STRATIXIIGX"]) || ([string match $DEVICE_FAMILY "ARRIAGX"]))] } {
#Cut the timing path betweeen unrelated clock domains
set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|refclkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|clkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_tx[0].transmit|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_quad[0].pll0|clkout }]
set_clock_groups -exclusive -group [get_clocks {*|alt2gxb_component|channel_quad[0].pll0|clkout }] -group [get_clocks {altera_tse_${REF_CLK}_$TO_THE_VARIATION_NAME altera_tse_${CLK}_$TO_THE_VARIATION_NAME *|alt2gxb_component|channel_tx[0].transmit|refclkout *|alt2gxb_component|channel_tx[0].transmit|clkout }]
}
# Universal Clock Group setter
set clocks_list [get_clocks *]
foreach_in_collection clock $clocks_list {
set name [get_clock_info -name $clock]
if {[ expr [regexp "altera_tse" $name] == 1]} {
set_clock_groups -exclusive -group [get_clocks $name]
}
}
} else {
# multiChannelFifoless
#**************************************************************
# Set Parameter
#**************************************************************
#**************************************************************
#**************************************************************
# Time Information
#**************************************************************
# Uncommenting one of the following derive_pll_clocks lines
# will instruct the TimeQuest Timing Analyzer to automatically
# create derived clocks for all PLL outputs for all PLLs in a
# Quartus design.
# If the PLL inputs are constrained elsewhere, uncomment the
# next line to automatically constrain all PLL output clocks.
# derive_pll_clocks
# If the PLL inputs are not constrained elsewhere, uncomment
# the next line to automatically constrain all PLL input and
# output clocks.
# derive_pll_clocks -create_base_clocks
#**************************************************************
#**************************************************************
# Create Clock
#**************************************************************
#**************************************************************
#All clocks used by TSE is named with prefix "altera_tse"
#Constrain MAC PCS control interface clock
if { [ expr $IS_SOPC == 0 ] } {
create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_sys_clk [ get_ports "$CLK"]
}
if { [ expr ($IS_FIFOLESS == 1) ] } {
for {set x 0} {$x < $NUMBER_OF_CHANNEL} {incr x} {
if { [ expr ($IS_SOPC == 0) ] } {
create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_mac_tx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}mac_tx_clk_${x}${FROM_THE_VARIATION_NAME}" ]
create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_mac_rx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}mac_rx_clk_${x}${FROM_THE_VARIATION_NAME}" ]
} else {
create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_mac_tx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}${VARIATION_NAME}_mac_rx_clk_${x}_out" ]
create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_mac_rx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}${VARIATION_NAME}_mac_tx_clk_${x}_out" ]
}
}
}
# Mac
if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 0) && ($IS_PMA == 0) ] } {
for {set x 0} {$x < $NUMBER_OF_CHANNEL} {incr x} {
create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_tx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}tx_clk_${x}$TO_THE_VARIATION_NAME" ]
create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_rx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}rx_clk_${x}$TO_THE_VARIATION_NAME" ]
}}
# MacPcs
if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 0) ] } {
for {set x 0} {$x < $NUMBER_OF_CHANNEL} {incr x} {
create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_tbi_tx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}tbi_tx_clk_${x}$TO_THE_VARIATION_NAME" ]
create_clock -period "$TSE_CLOCK_FREQUENCY" -name "altera_tse_tbi_rx_clk_${x}" [ get_ports "${SYSTEM_PATH_PREFIX}tbi_rx_clk_${x}$TO_THE_VARIATION_NAME" ]
}}
# MacPcsPma
if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) ] } {
#Constrain transceiver reference clock
create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_ref_clk [ get_ports "${SYSTEM_PATH_PREFIX}ref_clk$TO_THE_VARIATION_NAME" ]
}
# MacPcs+SGMII
if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 0) && ($IS_SGMII == 1)] } {
#Constrain transceiver reference clock
create_clock -period "$TSE_CLOCK_FREQUENCY" -name altera_tse_ref_clk [ get_ports "${SYSTEM_PATH_PREFIX}ref_clk$TO_THE_VARIATION_NAME" ]
}
# MacPcs+SGMII ( with or without PMA )
if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_SGMII == 1)] } {
}
# pmaAlt4Gxb
if { [expr ($TRANSCEIVER_TYPE == 0) && ($IS_PMA == 1) && (([string match $DEVICE_FAMILY "STRATIXIV"]) || ([string match $DEVICE_FAMILY "ARRIAIIGX"]) || ([string match $DEVICE_FAMILY "HARDCOPYIV"]) ) ] } {
}
# macPcsPmaLvdsSgmii
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1) && ($TRANSCEIVER_TYPE == 1)] } {
#Cut the timing path betweeen unrelated clock domains
}
# macPcsPmaLvdsNoSgmii
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0) && ($TRANSCEIVER_TYPE == 1)] } {
}
# macPcsPmaTransceiverSgmii=
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 1) && ($TRANSCEIVER_TYPE == 0) && (([string match $DEVICE_FAMILY "STRATIXIIGX"]) || ([string match $DEVICE_FAMILY "ARRIAGX"]))] } {
#Cut the timing path betweeen unrelated clock domains
}
# macPcsPmaTransceiverNoSgmii=
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($IS_SGMII == 0) && ($TRANSCEIVER_TYPE == 0) && (([string match $DEVICE_FAMILY "STRATIXIIGX"]) || ([string match $DEVICE_FAMILY "ARRIAGX"]))] } {
#Cut the timing path betweeen unrelated clock domains
}
if { [ expr ($IS_SOPC == 0) ] } {
if { [ expr ($IS_FIFOLESS == 1) ] } {
create_clock -period "$DEFAULT_SYSTEM_CLOCK_SPEED" -name altera_tse_rx_afull_clk [get_ports "${SYSTEM_PATH_PREFIX}rx_afull_clk$TO_THE_VARIATION_NAME" ]
}
}
derive_pll_clocks
set clocks_list [get_clocks *]
foreach_in_collection clock $clocks_list {
set name [get_clock_info -name $clock]
if {[ expr [regexp "altera_tse" $name] == 1]} {
set_clock_groups -exclusive -group [get_clocks $name]
}
}
#**************************************************************
# Set False Path
#**************************************************************
if { [ expr ($IS_SGMII == 1)] } {
set_false_path -from [get_registers {*|altera_tse_a_fifo_24:U_DSW|altera_tse_gray_cnt:U_RD|g_out[*]}] -to [get_registers {*|altera_tse_a_fifo_24:U_DSW|rd_g_wptr[*]}]
set_false_path -from [get_registers {*|altera_tse_a_fifo_24:U_DSW|altera_tse_gray_cnt:U_RD|b_out[*]}] -to [get_registers {*|altera_tse_a_fifo_24:U_DSW|rd_g_wptr[*]}]
set_false_path -from [get_registers {*|altera_tse_a_fifo_24:U_DSW|altera_tse_gray_cnt:U_WRT|g_out[*]}] -to [get_registers {*|altera_tse_a_fifo_24:U_DSW|wr_g_rptr[*]}]
set_false_path -from [get_registers {*|altera_tse_top_sgmii*:U_SGMII|altera_tse_colision_detect:U_COL|state*}] -to [get_registers {*|altera_tse_fifoless_mac_tx:U_TX|gm_rx_col_reg*}]
}
}
if { [ expr ($IS_HALFDUPLEX == 8) ] } {
#Constrain timing for half duplex logic
if { [ expr ($IS_FIFOLESS == 0) ] } {
set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
set_multicycle_path -setup 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [ get_registers *]
set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
set_multicycle_path -hold 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [ get_registers *]
set_max_delay 7.5 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [get_registers *|altera_tse_mac_tx:U_TX|eop[1]]
set_max_delay 7.5 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [get_registers *|altera_tse_mac_tx:U_TX|sop[1]]
set_max_delay 7.5 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [get_registers *|altera_tse_mac_tx:U_TX|rd_1[*]]
set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|*col*] -to [ get_registers *]
set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|*col*] -to [ get_registers *]
}
}
if { [ expr ($IS_HALFDUPLEX == 32) ] } {
#Constrain timing for half duplex logic
if { [ expr ($IS_FIFOLESS == 0) ] } {
set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
set_multicycle_path -setup 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
set_multicycle_path -hold 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|dout_reg_sft*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*]
set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|eop_sft*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*]
set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|sop_reg*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*]
}
}
if { [ expr ($IS_HALFDUPLEX == 8) ] } {
#Constrain timing for half duplex logic
if { [ expr ($IS_FIFOLESS == 1) ] } {
set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_fifoless_mac_tx:U_TX|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_fifoless_mac_tx:U_TX|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
set_multicycle_path -setup 5 -from [ get_registers *] -to [ get_registers *|altera_tse_fifoless_mac_tx:U_TX|altera_tse_retransmit_cntl:U_RETR|*]
set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_fifoless_mac_tx:U_TX|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_fifoless_mac_tx:U_TX|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
set_multicycle_path -hold 5 -from [ get_registers *] -to [ get_registers *|altera_tse_fifoless_mac_tx:U_TX|altera_tse_retransmit_cntl:U_RETR|*]
}
}
#####################################################################################
# Copyright (C) 1991-2009 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any other
# associated documentation or information provided by Altera or a partner
# under Altera's Megafunction Partnership Program may be used only
# to program PLD devices (but not masked PLD devices) from Altera. Any
# other use of such megafunction design, netlist, support information,
# device programming or simulation file, or any other related documentation
# or information is prohibited for any other purpose, including, but not
# limited to modification, reverse engineering, de-compiling, or use with
# any other silicon devices, unless such use is explicitly licensed under
# a separate agreement with Altera or a megafunction partner. Title to the
# intellectual property, including patents, copyrights, trademarks, trade
# secrets, or maskworks, embodied in any such megafunction design, netlist,
# support information, device programming or simulation file, or any other
# related documentation or information provided by Altera or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.
#####################################################################################
#####################################################################################
# Altera Triple-Speed Ethernet Megacore TCL constraint file
#
# Generated on Fri Mar 07 15:43:49 CET 2014
#
#####################################################################################
# General Option
set IS_SOPC 0
set VARIATION_NAME "ip_stratixiv_tse_sgmii_gx"
set DEVICE_FAMILY "STRATIXIV"
set FROM_THE_VARIATION_NAME ""
set TO_THE_VARIATION_NAME ""
# MAC Option
set IS_MAC 1
set NUMBER_OF_CHANNEL 1
set IS_SMALLMAC 0
set IS_SMALLMAC_GIGE 0
set IS_FIFOLESS 0
set IS_HALFDUPLEX 0
set MII_INTERFACE "MII_GMII"
# PCS Option
set IS_PCS 1
set IS_SGMII 0
# PMA Option
set IS_PMA 1
set TRANSCEIVER_TYPE 0
# GXB Option
set IS_POWERDOWN 0
if { [ expr ( $IS_SOPC == 1 )] } {
set FROM_THE_VARIATION_NAME "_from_the_$VARIATION_NAME"
set TO_THE_VARIATION_NAME "_to_the_$VARIATION_NAME"
} else {
set FROM_THE_VARIATION_NAME ""
set TO_THE_VARIATION_NAME ""
}
if { [ expr ( $IS_FIFOLESS == 0 )] } {
# macPcs=
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 0)] } {
#Optimize I/O timing for TBI interface
set_instance_assignment -name FAST_INPUT_REGISTER ON -to tbi_rx_d${TO_THE_VARIATION_NAME}
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to tbi_tx_d${FROM_THE_VARIATION_NAME}
}
# pcs=
if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 0)] } {
#Optimize I/O timing for MII interface
set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_tx_d
set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_tx_en
set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_tx_err
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_rx_col
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_rx_crs
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_rx_d
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_rx_en
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_rx_err
#Optimize I/O timing for GMII interface
set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_tx_d
set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_tx_en
set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_tx_err
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_rx_d
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_rx_dv
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_rx_err
#Optimize I/O timing for TBI interface
set_instance_assignment -name FAST_INPUT_REGISTER ON -to tbi_rx_d
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to tbi_tx_d
set_instance_assignment -name FAST_INPUT_REGISTER ON -to tbi_rx_d
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to tbi_tx_d
}
# pcsPma=
if { [ expr ($IS_MAC == 0) && ($IS_PCS == 1) && ($IS_PMA == 1)] } {
#Optimize I/O timing for MII interface
set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_tx_d
set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_tx_en
set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_tx_err
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_rx_col
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_rx_crs
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_rx_d
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_rx_en
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_rx_err
#Optimize I/O timing for GMII interface
set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_tx_d
set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_tx_en
set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_tx_err
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_rx_d
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_rx_dv
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_rx_err
}
# pmaTransceiver=
if { [ expr ($IS_PCS == 1) && ($IS_PMA == 1)] } {
if { [ expr ($TRANSCEIVER_TYPE == 0)] } {
if { [string match $DEVICE_FAMILY "STRATIXIV"]} {
#Optimize I/O timing for serdes interface
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to txp
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to rxp
} else {
# pmaTransceiverStratixIV=
#Optimize I/O timing for serdes interface
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to txp
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rxp
}
}
if { [ expr ($TRANSCEIVER_TYPE == 1)] } {
# pmaLvds=
#Constrain MAC PCS reference clock
set_instance_assignment -name GLOBAL_SIGNAL ON -to ref_clk
#Optimize I/O timing for serdes interface
set_instance_assignment -name IO_STANDARD LVDS -to ref_clk
set_instance_assignment -name IO_STANDARD LVDS -to txp
set_instance_assignment -name IO_STANDARD LVDS -to rxp
}
}
# gmii=
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 0) && ($IS_PMA == 0) && ([string match $MII_INTERFACE "MII_GMII"]) ] } {
#Optimize I/O timing for GMII network-side interface
set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_rx_d
set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_rx_dv
set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_rx_err
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_tx_d
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_tx_en
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_tx_err
#Optimize I/O timing for MII network-side interface
set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_col
set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_crs
set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_d
set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_en
set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_err
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_tx_d
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_tx_en
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_tx_err
}
# rgmii=
if { [ expr ($IS_MAC == 1) && ($IS_PCS == 0) && ($IS_PMA == 0) && ([string match $MII_INTERFACE "RGMII"])] } {
#Optimize I/O timing for RGMII network-side interface
set_instance_assignment -name FAST_INPUT_REGISTER ON -to rx_control
set_instance_assignment -name FAST_INPUT_REGISTER ON -to rgmii_in
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to tx_control
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to rgmii_out
}
} else {
if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 0) && ($IS_PMA == 0) ] } {
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk${TO_THE_VARIATION_NAME}
set_instance_assignment -name GLOBAL_SIGNAL ON -to reset${TO_THE_VARIATION_NAME}
for {set x 0} {$x < $NUMBER_OF_CHANNEL} {incr x} {
if { [ expr [string match $MII_INTERFACE "MII_GMII"] ] } {
#Optimize I/O timing for MII network-side interface
if { [ expr $IS_HALFDUPLEX == 1 ] } {
set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_col_${x}${TO_THE_VARIATION_NAME}
set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_crs_${x}${TO_THE_VARIATION_NAME}
}
set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_d_${x}${TO_THE_VARIATION_NAME}
set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_en_${x}${TO_THE_VARIATION_NAME}
set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_err_${x}${TO_THE_VARIATION_NAME}
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_tx_d_${x}${FROM_THE_VARIATION_NAME}
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_tx_en_${x}${FROM_THE_VARIATION_NAME}
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to m_tx_err_${x}${FROM_THE_VARIATION_NAME}
#Optimize I/O timing for GMII network-side interface
set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_rx_d_${x}${TO_THE_VARIATION_NAME}
set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_rx_dv_${x}${TO_THE_VARIATION_NAME}
set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_rx_err_${x}${TO_THE_VARIATION_NAME}
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_tx_d_${x}${FROM_THE_VARIATION_NAME}
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_tx_en_${x}${FROM_THE_VARIATION_NAME}
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to gm_tx_err_${x}${FROM_THE_VARIATION_NAME}
set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to rx_clk_${x}${TO_THE_VARIATION_NAME}
set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to tx_clk_${x}${TO_THE_VARIATION_NAME}
}
if { [ expr [string match $MII_INTERFACE "RGMII"] ] } {
#Optimize I/O timing for RGMII network-side interface
set_instance_assignment -name FAST_INPUT_REGISTER ON -to rx_control_${x}${TO_THE_VARIATION_NAME}
set_instance_assignment -name FAST_INPUT_REGISTER ON -to rgmii_in_${x}${TO_THE_VARIATION_NAME}
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to tx_control_${x}${FROM_THE_VARIATION_NAME}
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to rgmii_out_${x}${FROM_THE_VARIATION_NAME}
set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to rx_clk_${x}${TO_THE_VARIATION_NAME}
#set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to tx_clk_${x}${TO_THE_VARIATION_NAME}
}
}
}
if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 0) ] } {
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk${TO_THE_VARIATION_NAME}
set_instance_assignment -name GLOBAL_SIGNAL ON -to reset${TO_THE_VARIATION_NAME}
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to ref_clk${TO_THE_VARIATION_NAME}
for {set x 0} {$x < $NUMBER_OF_CHANNEL} {incr x} {
#Optimize I/O timing for TBI interface
set_instance_assignment -name FAST_INPUT_REGISTER ON -to tbi_rx_d_${x}${TO_THE_VARIATION_NAME}
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to tbi_tx_d_${x}${FROM_THE_VARIATION_NAME}
set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to tbi_rx_clk_${x}${FROM_THE_VARIATION_NAME}
}
}
if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) ] } {
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk${TO_THE_VARIATION_NAME}
set_instance_assignment -name GLOBAL_SIGNAL ON -to reset${TO_THE_VARIATION_NAME}
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to ref_clk${TO_THE_VARIATION_NAME}
}
if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($TRANSCEIVER_TYPE == 0) ] } {
for {set x 0} {$x < $NUMBER_OF_CHANNEL} {incr x} {
if { [string match $DEVICE_FAMILY "STRATIXIV"]} {
#Optimize I/O timing for serdes interface
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to txp_${x}${FROM_THE_VARIATION_NAME}
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to rxp_${x}${TO_THE_VARIATION_NAME}
} else {
#Optimize I/O timing for serdes interface
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to txp_${x}${FROM_THE_VARIATION_NAME}
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rxp_${x}${TO_THE_VARIATION_NAME}
}
}
}
if { [ expr ($IS_FIFOLESS == 1) && ($IS_MAC == 1) && ($IS_PCS == 1) && ($IS_PMA == 1) && ($TRANSCEIVER_TYPE == 1) ] } {
set_instance_assignment -name IO_STANDARD LVDS -to ref_clk${TO_THE_VARIATION_NAME}
for {set x 0} {$x < $NUMBER_OF_CHANNEL} {incr x} {
set_instance_assignment -name IO_STANDARD LVDS -to txp_${x}${FROM_THE_VARIATION_NAME}
set_instance_assignment -name IO_STANDARD LVDS -to rxp_${x}${TO_THE_VARIATION_NAME}
}
}
}
export_assignments
#####################################################################################
# Copyright (C) 1991-2007 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any other
# associated documentation or information provided by Altera or a partner
# under Altera's Megafunction Partnership Program may be used only
# to program PLD devices (but not masked PLD devices) from Altera. Any
# other use of such megafunction design, netlist, support information,
# device programming or simulation file, or any other related documentation
# or information is prohibited for any other purpose, including, but not
# limited to modification, reverse engineering, de-compiling, or use with
# any other silicon devices, unless such use is explicitly licensed under
# a separate agreement with Altera or a megafunction partner. Title to the
# intellectual property, including patents, copyrights, trademarks, trade
# secrets, or maskworks, embodied in any such megafunction design, netlist,
# support information, device programming or simulation file, or any other
# related documentation or information provided by Altera or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.
#####################################################################################
#####################################################################################
# Altera Triple-Speed Ethernet Megacore NativeLink TCL script
#
# This script should be sourced from the Quartus II TCL console prior to
# simulating using NativeLink
#
# Generated on Fri Mar 07 15:44:07 CET 2014
#
#####################################################################################
#Set time scale
set_global_assignment -name EDA_TIME_SCALE "1 ns" -section_id eda_simulation
#Set eda netlist writer options
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VHDL" -section_id eda_simulation
#Set to work in test bench mode
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
#Set testbench top level name and module name
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH ip_stratixiv_tse_sgmii_gx_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME ip_stratixiv_tse_sgmii_gx_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb -section_id ip_stratixiv_tse_sgmii_gx_tb
#Set design instance
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME ip_stratixiv_tse_sgmii_gx -section_id ip_stratixiv_tse_sgmii_gx_tb
#Set simulation time
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "50 us" -section_id ip_stratixiv_tse_sgmii_gx_tb
#Set testbench component files
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/ethgen.vhd -section_id ip_stratixiv_tse_sgmii_gx_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/ethgen2.vhd -section_id ip_stratixiv_tse_sgmii_gx_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/ethgen32.vhd -section_id ip_stratixiv_tse_sgmii_gx_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/ethmon.vhd -section_id ip_stratixiv_tse_sgmii_gx_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/ethmon2.vhd -section_id ip_stratixiv_tse_sgmii_gx_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/ethmon_32.vhd -section_id ip_stratixiv_tse_sgmii_gx_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/top_ethmon32.vhd -section_id ip_stratixiv_tse_sgmii_gx_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/mdio_reg.vhd -section_id ip_stratixiv_tse_sgmii_gx_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/mdio_slave.vhd -section_id ip_stratixiv_tse_sgmii_gx_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/top_mdio_slave.vhd -section_id ip_stratixiv_tse_sgmii_gx_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/loopback_adapter.vhd -section_id ip_stratixiv_tse_sgmii_gx_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/loopback_adapter_fifo.vhd -section_id ip_stratixiv_tse_sgmii_gx_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/timing_adapter_8.vhd -section_id ip_stratixiv_tse_sgmii_gx_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/timing_adapter_fifo_8.vhd -section_id ip_stratixiv_tse_sgmii_gx_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/timing_adapter_32.vhd -section_id ip_stratixiv_tse_sgmii_gx_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/top_ethgen8.vhd -section_id ip_stratixiv_tse_sgmii_gx_tb
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/model/altera_ethmodels_pack.vhd -section_id ip_stratixiv_tse_sgmii_gx_tb
#Set memory initialization files
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/ip_stratixiv_tse_sgmii_gx/sdpm_altsyncram.hex -section_id ip_stratixiv_tse_sgmii_gx_tb
#Set top level testbench files
set_global_assignment -name EDA_TEST_BENCH_FILE testbench/ip_stratixiv_tse_sgmii_gx/ip_stratixiv_tse_sgmii_gx_tb.vhd -section_id ip_stratixiv_tse_sgmii_gx_tb
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