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Commit 16ff9a6d authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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added gluelogic for the 4x chan 10G IPs

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libraries/technology/10gbase_r/hdllib.cfg
+ 4
− 0
View file @ 16ff9a6d
...@@ -3,10 +3,14 @@ hdl_library_clause_name = tech_10gbase_r_lib ...@@ -3,10 +3,14 @@ hdl_library_clause_name = tech_10gbase_r_lib
hdl_lib_uses_synth = technology hdl_lib_uses_synth = technology
tech_pll tech_pll
ip_arria10_phy_10gbase_r ip_arria10_phy_10gbase_r
ip_arria10_phy_10gbase_r_4
ip_arria10_phy_10gbase_r_12 ip_arria10_phy_10gbase_r_12
ip_arria10_phy_10gbase_r_24
ip_arria10_transceiver_pll_10g ip_arria10_transceiver_pll_10g
ip_arria10_transceiver_reset_controller_1 ip_arria10_transceiver_reset_controller_1
ip_arria10_transceiver_reset_controller_4
ip_arria10_transceiver_reset_controller_12 ip_arria10_transceiver_reset_controller_12
ip_arria10_transceiver_reset_controller_24
tech_transceiver tech_transceiver
common common
hdl_lib_uses_sim = hdl_lib_uses_sim =
......
libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
+ 172
− 1
View file @ 16ff9a6d
...@@ -22,10 +22,14 @@ ...@@ -22,10 +22,14 @@
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis. -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_150; LIBRARY ip_arria10_phy_10gbase_r_altera_xcvr_native_a10_150;
LIBRARY ip_arria10_phy_10gbase_r_4_altera_xcvr_native_a10_150;
LIBRARY ip_arria10_phy_10gbase_r_12_altera_xcvr_native_a10_150; LIBRARY ip_arria10_phy_10gbase_r_12_altera_xcvr_native_a10_150;
LIBRARY ip_arria10_phy_10gbase_r_24_altera_xcvr_native_a10_150;
LIBRARY ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_150; LIBRARY ip_arria10_transceiver_pll_10g_altera_xcvr_atx_pll_a10_150;
LIBRARY ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_150; LIBRARY ip_arria10_transceiver_reset_controller_1_altera_xcvr_reset_control_150;
LIBRARY ip_arria10_transceiver_reset_controller_4_altera_xcvr_reset_control_150;
LIBRARY ip_arria10_transceiver_reset_controller_12_altera_xcvr_reset_control_150; LIBRARY ip_arria10_transceiver_reset_controller_12_altera_xcvr_reset_control_150;
LIBRARY ip_arria10_transceiver_reset_controller_24_altera_xcvr_reset_control_150;
LIBRARY IEEE, tech_pll_lib, common_lib; LIBRARY IEEE, tech_pll_lib, common_lib;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
...@@ -62,7 +66,11 @@ END tech_10gbase_r_arria10; ...@@ -62,7 +66,11 @@ END tech_10gbase_r_arria10;
ARCHITECTURE str OF tech_10gbase_r_arria10 IS ARCHITECTURE str OF tech_10gbase_r_arria10 IS
CONSTANT c_nof_channels_per_ip : NATURAL := sel_a_b(g_nof_channels=12, 12, 1); -- only support single 1 or block of 12 --CONSTANT c_nof_channels_per_ip : NATURAL := sel_a_b(g_nof_channels=24, 24, 1); -- only support single 1 or block of 12
--CONSTANT c_nof_channels_per_ip : NATURAL := 24 WHEN g_nof_channels=24 ELSE 12 WHEN g_nof_channels=12 ELSE 1;
CONSTANT c_nof_channels_per_ip : NATURAL := g_nof_channels;
CONSTANT IP_SIZE : NATURAL := c_nof_channels_per_ip; -- short constant name alias to improve index readability CONSTANT IP_SIZE : NATURAL := c_nof_channels_per_ip; -- short constant name alias to improve index readability
CONSTANT IP_SIZE_DATA : NATURAL := IP_SIZE * c_xgmii_data_w; CONSTANT IP_SIZE_DATA : NATURAL := IP_SIZE * c_xgmii_data_w;
...@@ -193,7 +201,89 @@ BEGIN ...@@ -193,7 +201,89 @@ BEGIN
); );
END GENERATE; END GENERATE;
END GENERATE; END GENERATE;
gen_phy_4 : IF c_nof_channels_per_ip=4 GENERATE
tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0));
tr_coreclkin_slv <= (OTHERS=>tr_coreclkin(0));
gen_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
tx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w) <= tx_parallel_data_arr(I);
tx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes) <= tx_control_arr(I);
rx_parallel_data_arr(I) <= rx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w);
rx_control_arr(I) <= rx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes);
END GENERATE;
u_ip_arria10_phy_10gbase_r_4 : ip_arria10_phy_10gbase_r_4
PORT MAP (
tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
tx_serial_data => tx_serial_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
rx_serial_data => rx_serial_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
tx_control => tx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
rx_control => rx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
--tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
--tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
--tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
--tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
--tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
--tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
--tx_pma_div_clkout : out std_logic_vector(11 downto 0); -- tx_pma_div_clkout.clk
--rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
--rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
--rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
--rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
--rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
--rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
--rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
--unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
--unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
--unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
--unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
);
u_ip_arria10_transceiver_reset_controller_4 : ip_arria10_transceiver_reset_controller_4
PORT MAP (
clock => clk_156, -- : in std_logic := '0'; -- clock.clk
pll_locked => atx_pll_locked_arr(0 DOWNTO 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
pll_powerdown => atx_pll_powerdown_arr(0 DOWNTO 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
reset => rst_156, -- : in std_logic := '0'; -- reset.reset
rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
tx_cal_busy => cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 DOWNTO 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
);
END GENERATE;
gen_phy_12 : IF c_nof_channels_per_ip=12 GENERATE gen_phy_12 : IF c_nof_channels_per_ip=12 GENERATE
tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0)); tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0));
tr_coreclkin_slv <= (OTHERS=>tr_coreclkin(0)); tr_coreclkin_slv <= (OTHERS=>tr_coreclkin(0));
...@@ -275,6 +365,87 @@ BEGIN ...@@ -275,6 +365,87 @@ BEGIN
); );
END GENERATE; END GENERATE;
gen_phy_24 : IF c_nof_channels_per_ip=24 GENERATE
tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0));
tr_coreclkin_slv <= (OTHERS=>tr_coreclkin(0));
gen_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
tx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w) <= tx_parallel_data_arr(I);
tx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes) <= tx_control_arr(I);
rx_parallel_data_arr(I) <= rx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w);
rx_control_arr(I) <= rx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes);
END GENERATE;
u_ip_arria10_phy_10gbase_r_24 : ip_arria10_phy_10gbase_r_24
PORT MAP (
tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
tx_serial_data => tx_serial_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
rx_serial_data => rx_serial_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
tx_control => tx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
rx_control => rx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
--tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
--tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
--tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
--tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
--tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
--tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
--tx_pma_div_clkout : out std_logic_vector(11 downto 0); -- tx_pma_div_clkout.clk
--rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
--rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
--rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
--rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
--rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
--rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
--rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
--unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
--unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
--unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
--unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
);
u_ip_arria10_transceiver_reset_controller_24 : ip_arria10_transceiver_reset_controller_24
PORT MAP (
clock => clk_156, -- : in std_logic := '0'; -- clock.clk
pll_locked => atx_pll_locked_arr(0 DOWNTO 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
pll_powerdown => atx_pll_powerdown_arr(0 DOWNTO 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
reset => rst_156, -- : in std_logic := '0'; -- reset.reset
rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
tx_cal_busy => cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 DOWNTO 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
);
END GENERATE;
-- ATX PLL -- ATX PLL
u_ip_arria10_transceiver_pll_10g : ip_arria10_transceiver_pll_10g u_ip_arria10_transceiver_pll_10g : ip_arria10_transceiver_pll_10g
......
libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
+ 174
− 84
View file @ 16ff9a6d
...@@ -73,9 +73,63 @@ PACKAGE tech_10gbase_r_component_pkg IS ...@@ -73,9 +73,63 @@ PACKAGE tech_10gbase_r_component_pkg IS
); );
END COMPONENT; END COMPONENT;
COMPONENT ip_arria10_phy_10gbase_r_4
port (
reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
reconfig_address : in std_logic_vector(11 downto 0) := (others => '0'); -- .address
reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
rx_analogreset : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
rx_cal_busy : out std_logic_vector(3 downto 0); -- rx_cal_busy.rx_cal_busy
rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
rx_clkout : out std_logic_vector(3 downto 0); -- rx_clkout.clk
rx_control : out std_logic_vector(31 downto 0); -- rx_control.rx_control
rx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_coreclkin.clk
rx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
rx_enh_blk_lock : out std_logic_vector(3 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
rx_enh_data_valid : out std_logic_vector(3 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
rx_enh_fifo_del : out std_logic_vector(3 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
rx_enh_fifo_empty : out std_logic_vector(3 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
rx_enh_fifo_full : out std_logic_vector(3 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
rx_enh_fifo_insert : out std_logic_vector(3 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
rx_enh_highber : out std_logic_vector(3 downto 0); -- rx_enh_highber.rx_enh_highber
rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
rx_parallel_data : out std_logic_vector(255 downto 0); -- rx_parallel_data.rx_parallel_data
rx_prbs_done : out std_logic_vector(3 downto 0); -- rx_prbs_done.rx_prbs_done
rx_prbs_err : out std_logic_vector(3 downto 0); -- rx_prbs_err.rx_prbs_err
rx_prbs_err_clr : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
tx_analogreset : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
tx_cal_busy : out std_logic_vector(3 downto 0); -- tx_cal_busy.tx_cal_busy
tx_clkout : out std_logic_vector(3 downto 0); -- tx_clkout.clk
tx_control : in std_logic_vector(31 downto 0) := (others => '0'); -- tx_control.tx_control
tx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_coreclkin.clk
tx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
tx_enh_data_valid : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
tx_enh_fifo_empty : out std_logic_vector(3 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
tx_enh_fifo_full : out std_logic_vector(3 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
tx_enh_fifo_pempty : out std_logic_vector(3 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
tx_enh_fifo_pfull : out std_logic_vector(3 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
tx_err_ins : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
tx_serial_clk0 : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_serial_clk0.clk
tx_serial_data : out std_logic_vector(3 downto 0); -- tx_serial_data.tx_serial_data
unused_rx_control : out std_logic_vector(47 downto 0); -- unused_rx_control.unused_rx_control
unused_rx_parallel_data : out std_logic_vector(255 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
unused_tx_control : in std_logic_vector(35 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
unused_tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
);
END COMPONENT;
COMPONENT ip_arria10_phy_10gbase_r_12 COMPONENT ip_arria10_phy_10gbase_r_12
PORT ( PORT (
reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
reconfig_address : in std_logic_vector(13 downto 0) := (others => '0'); -- .address reconfig_address : in std_logic_vector(13 downto 0) := (others => '0'); -- .address
reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
...@@ -124,67 +178,80 @@ PACKAGE tech_10gbase_r_component_pkg IS ...@@ -124,67 +178,80 @@ PACKAGE tech_10gbase_r_component_pkg IS
unused_rx_parallel_data : out std_logic_vector(767 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data unused_rx_parallel_data : out std_logic_vector(767 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
unused_tx_control : in std_logic_vector(107 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control unused_tx_control : in std_logic_vector(107 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
unused_tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data unused_tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
-- rx_analogreset : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
-- rx_cal_busy : out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
-- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
-- rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
-- rx_control : out std_logic_vector(95 downto 0); -- rx_control.rx_control
-- rx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
-- rx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
-- rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
-- rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
-- rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
-- rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
-- rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
-- rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
-- rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
-- rx_is_lockedtodata : out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
-- rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
-- rx_parallel_data : out std_logic_vector(767 downto 0); -- rx_parallel_data.rx_parallel_data
-- rx_serial_data : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
-- tx_analogreset : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
-- tx_cal_busy : out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
-- tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
-- tx_control : in std_logic_vector(95 downto 0) := (others => '0'); -- tx_control.tx_control
-- tx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
-- tx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
-- tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
-- tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
-- tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
-- tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
-- tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
-- tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
-- tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
-- tx_pma_div_clkout : out std_logic_vector(11 downto 0); -- tx_pma_div_clkout.clk
-- tx_serial_clk0 : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
-- tx_serial_data : out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
-- unused_rx_control : out std_logic_vector(143 downto 0); -- unused_rx_control.unused_rx_control
-- unused_rx_parallel_data : out std_logic_vector(767 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
-- unused_tx_control : in std_logic_vector(107 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
-- unused_tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
); );
END COMPONENT; END COMPONENT;
COMPONENT ip_arria10_phy_10gbase_r_24
PORT (
reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
reconfig_address : in std_logic_vector(14 downto 0) := (others => '0'); -- .address
reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
rx_analogreset : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
rx_cal_busy : out std_logic_vector(23 downto 0); -- rx_cal_busy.rx_cal_busy
rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
rx_clkout : out std_logic_vector(23 downto 0); -- rx_clkout.clk
rx_control : out std_logic_vector(191 downto 0); -- rx_control.rx_control
rx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_coreclkin.clk
rx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
rx_enh_blk_lock : out std_logic_vector(23 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
rx_enh_data_valid : out std_logic_vector(23 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
rx_enh_fifo_del : out std_logic_vector(23 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
rx_enh_fifo_empty : out std_logic_vector(23 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
rx_enh_fifo_full : out std_logic_vector(23 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
rx_enh_fifo_insert : out std_logic_vector(23 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
rx_enh_highber : out std_logic_vector(23 downto 0); -- rx_enh_highber.rx_enh_highber
rx_is_lockedtodata : out std_logic_vector(23 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
rx_is_lockedtoref : out std_logic_vector(23 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
rx_parallel_data : out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
rx_prbs_done : out std_logic_vector(23 downto 0); -- rx_prbs_done.rx_prbs_done
rx_prbs_err : out std_logic_vector(23 downto 0); -- rx_prbs_err.rx_prbs_err
rx_prbs_err_clr : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
rx_serial_data : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
rx_seriallpbken : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
tx_analogreset : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
tx_cal_busy : out std_logic_vector(23 downto 0); -- tx_cal_busy.tx_cal_busy
tx_clkout : out std_logic_vector(23 downto 0); -- tx_clkout.clk
tx_control : in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
tx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_coreclkin.clk
tx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
tx_enh_fifo_empty : out std_logic_vector(23 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
tx_enh_fifo_full : out std_logic_vector(23 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
tx_enh_fifo_pempty : out std_logic_vector(23 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
tx_enh_fifo_pfull : out std_logic_vector(23 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
tx_err_ins : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
tx_serial_clk0 : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_serial_clk0.clk
tx_serial_data : out std_logic_vector(23 downto 0); -- tx_serial_data.tx_serial_data
unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
);
END COMPONENT;
COMPONENT ip_arria10_transceiver_pll_10g IS COMPONENT ip_arria10_transceiver_pll_10g IS
PORT ( PORT (
mcgb_rst : in std_logic := '0'; -- mcgb_rst.mcgb_rst mcgb_rst : in std_logic := '0'; -- mcgb_rst.mcgb_rst
mcgb_serial_clk : out std_logic; -- mcgb_serial_clk.clk mcgb_serial_clk : out std_logic; -- mcgb_serial_clk.clk
pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
pll_locked : out std_logic; -- pll_locked.pll_locked pll_locked : out std_logic; -- pll_locked.pll_locked
pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
reconfig_write0 : in std_logic := '0'; -- reconfig_avmm0.write reconfig_write0 : in std_logic := '0'; -- reconfig_avmm0.write
reconfig_read0 : in std_logic := '0'; -- .read reconfig_read0 : in std_logic := '0'; -- .read
reconfig_address0 : in std_logic_vector(9 downto 0) := (others => '0'); -- .address reconfig_address0 : in std_logic_vector(9 downto 0) := (others => '0'); -- .address
reconfig_writedata0 : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata reconfig_writedata0 : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
reconfig_readdata0 : out std_logic_vector(31 downto 0); -- .readdata reconfig_readdata0 : out std_logic_vector(31 downto 0); -- .readdata
reconfig_waitrequest0 : out std_logic; -- .waitrequest reconfig_waitrequest0 : out std_logic; -- .waitrequest
reconfig_clk0 : in std_logic := '0'; -- reconfig_clk0.clk reconfig_clk0 : in std_logic := '0'; -- reconfig_clk0.clk
reconfig_reset0 : in std_logic := '0'; -- reconfig_reset0.reset reconfig_reset0 : in std_logic := '0'; -- reconfig_reset0.reset
tx_serial_clk : out std_logic -- tx_serial_clk.clk tx_serial_clk : out std_logic -- tx_serial_clk.clk
-- pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown -- pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
-- pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk -- pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
-- pll_locked : out std_logic; -- pll_locked.pll_locked -- pll_locked : out std_logic; -- pll_locked.pll_locked
...@@ -213,37 +280,60 @@ PACKAGE tech_10gbase_r_component_pkg IS ...@@ -213,37 +280,60 @@ PACKAGE tech_10gbase_r_component_pkg IS
); );
END COMPONENT; END COMPONENT;
COMPONENT ip_arria10_transceiver_reset_controller_4
port (
clock : in std_logic := '0'; -- clock.clk
pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
reset : in std_logic := '0'; -- reset.reset
rx_analogreset : out std_logic_vector(3 downto 0); -- rx_analogreset.rx_analogreset
rx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
rx_digitalreset : out std_logic_vector(3 downto 0); -- rx_digitalreset.rx_digitalreset
rx_is_lockedtodata : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
rx_ready : out std_logic_vector(3 downto 0); -- rx_ready.rx_ready
tx_analogreset : out std_logic_vector(3 downto 0); -- tx_analogreset.tx_analogreset
tx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
tx_digitalreset : out std_logic_vector(3 downto 0); -- tx_digitalreset.tx_digitalreset
tx_ready : out std_logic_vector(3 downto 0) -- tx_ready.tx_ready
);
END COMPONENT;
COMPONENT ip_arria10_transceiver_reset_controller_12 COMPONENT ip_arria10_transceiver_reset_controller_12
PORT ( PORT (
clock : in std_logic := '0'; -- clock.clk clock : in std_logic := '0'; -- clock.clk
pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
reset : in std_logic := '0'; -- reset.reset reset : in std_logic := '0'; -- reset.reset
rx_analogreset : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset rx_analogreset : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
rx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy rx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
rx_digitalreset : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset rx_digitalreset : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
rx_is_lockedtodata : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata rx_is_lockedtodata : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
rx_ready : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready rx_ready : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
tx_analogreset : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset tx_analogreset : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
tx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy tx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
tx_digitalreset : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset tx_digitalreset : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
tx_ready : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready tx_ready : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
);
END COMPONENT;
-- clock : in std_logic := '0'; -- clock.clk COMPONENT ip_arria10_transceiver_reset_controller_24
-- pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked PORT (
-- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown clock : in std_logic := '0'; -- clock.clk
-- pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
-- reset : in std_logic := '0'; -- reset.reset pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
-- rx_analogreset : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
-- rx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy reset : in std_logic := '0'; -- reset.reset
-- rx_digitalreset : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset rx_analogreset : out std_logic_vector(23 downto 0); -- rx_analogreset.rx_analogreset
-- rx_is_lockedtodata : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata rx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
-- rx_ready : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready rx_digitalreset : out std_logic_vector(23 downto 0); -- rx_digitalreset.rx_digitalreset
-- tx_analogreset : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset rx_is_lockedtodata : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
-- tx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy rx_ready : out std_logic_vector(23 downto 0); -- rx_ready.rx_ready
-- tx_digitalreset : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset tx_analogreset : out std_logic_vector(23 downto 0); -- tx_analogreset.tx_analogreset
-- tx_ready : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready tx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
tx_digitalreset : out std_logic_vector(23 downto 0); -- tx_digitalreset.tx_digitalreset
tx_ready : out std_logic_vector(23 downto 0) -- tx_ready.tx_ready
); );
END COMPONENT; END COMPONENT;
......
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