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Commit 111781f6 authored by Dumez's avatar Dumez
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Add beam0 Eth and Beam0 offload_rx

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applications/rfidb/designs/rfidb/hdllib.cfg
+ 9
− 6
View file @ 111781f6
hdl_lib_name = unb1_rfidb
hdl_library_clause_name = unb1_rfidb_lib
hdl_lib_uses_synth = unb1_board detector
hdl_lib_uses_synth = common dp unb1_board eth detector tech_tse
hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_top_level_entity =
quartus_copy_files =
quartus/qsys_unb1_rfidb.qsys .
quartus/stp32.stp
synth_files =
src/vhdl/stp32.vhd
src/vhdl/qsys_unb1_rfidb_pkg.vhd
src/vhdl/mmm_unb1_rfidb.vhd
src/vhdl/unb1_rfidb.vhd
......@@ -13,11 +20,6 @@ synth_files =
test_bench_files =
tb/vhdl/tb_unb1_rfidb.vhd
synth_top_level_entity =
quartus_copy_files =
quartus/qsys_unb1_rfidb.qsys .
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
......@@ -30,4 +32,5 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
src/vhdl/stp32.qip
$HDL_BUILD_DIR/unb1/quartus/unb1_rfidb/qsys_unb1_rfidb/synthesis/qsys_unb1_rfidb.qip
applications/rfidb/designs/rfidb/quartus/qsys_unb1_rfidb.qsys
+ 396
− 72
View file @ 111781f6
......@@ -12,6 +12,22 @@
element $${FILENAME}
{
}
element Beam0_dp_offload_rx_reg_hdr_dat
{
datum _sortIndex
{
value = "22";
type = "int";
}
}
element Beam0_eth
{
datum _sortIndex
{
value = "21";
type = "int";
}
}
element altpll_0
{
datum _sortIndex
......@@ -24,7 +40,7 @@
{
datum baseAddress
{
value = "352";
value = "800";
type = "long";
}
}
......@@ -36,6 +52,14 @@
type = "int";
}
}
element altpll_0.c0
{
datum _clockDomain
{
value = "mm_clk";
type = "String";
}
}
element c0
{
datum _sortIndex
......@@ -44,27 +68,27 @@
type = "int";
}
}
element altpll_0.c0
element altpll_0.c1
{
datum _clockDomain
{
value = "mm_clk";
value = "epcs_clk";
type = "String";
}
}
element altpll_0.c1
element altpll_0.c2
{
datum _clockDomain
{
value = "epcs_clk";
value = "tse_clk";
type = "String";
}
}
element altpll_0.c2
element altpll_0.c3
{
datum _clockDomain
{
value = "tse_clk";
value = "cal_rec_clk";
type = "String";
}
}
......@@ -84,6 +108,14 @@
type = "int";
}
}
element cpu_0.data_master
{
datum _tags
{
value = "";
type = "String";
}
}
element cpu_0.jtag_debug_module
{
datum baseAddress
......@@ -105,35 +137,37 @@
type = "String";
}
}
element reg_remu.mem
element pio_pps.mem
{
datum baseAddress
{
value = "256";
value = "808";
type = "long";
}
}
element reg_mmdp_data.mem
element pio_system_info.mem
{
datum baseAddress
datum _lockedAddress
{
value = "392";
type = "long";
}
value = "1";
type = "boolean";
}
element reg_dpmm_data.mem
{
datum baseAddress
{
value = "376";
value = "0";
type = "long";
}
}
element reg_dpmm_ctrl.mem
element rom_system_info.mem
{
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "368";
value = "4096";
type = "long";
}
}
......@@ -141,23 +175,23 @@
{
datum baseAddress
{
value = "288";
value = "736";
type = "long";
}
}
element pio_pps.mem
element Beam0_dp_offload_rx_reg_hdr_dat.mem
{
datum baseAddress
{
value = "360";
value = "256";
type = "long";
}
}
element reg_mmdp_ctrl.mem
element reg_mmdp_data.mem
{
datum baseAddress
{
value = "384";
value = "840";
type = "long";
}
}
......@@ -174,16 +208,19 @@
type = "long";
}
}
element rom_system_info.mem
element reg_remu.mem
{
datum _lockedAddress
datum baseAddress
{
value = "1";
type = "boolean";
value = "704";
type = "long";
}
}
element reg_dpmm_ctrl.mem
{
datum baseAddress
{
value = "4096";
value = "816";
type = "long";
}
}
......@@ -191,20 +228,31 @@
{
datum baseAddress
{
value = "224";
value = "672";
type = "long";
}
}
element pio_system_info.mem
element reg_common.mem
{
datum _lockedAddress
datum baseAddress
{
value = "1";
type = "boolean";
value = "128";
type = "long";
}
}
element reg_mmdp_ctrl.mem
{
datum baseAddress
{
value = "0";
value = "832";
type = "long";
}
}
element reg_dpmm_data.mem
{
datum baseAddress
{
value = "824";
type = "long";
}
}
......@@ -216,11 +264,27 @@
type = "long";
}
}
element Beam0_eth.mms_ram
{
datum baseAddress
{
value = "24576";
type = "long";
}
}
element Beam0_eth.mms_reg
{
datum baseAddress
{
value = "576";
type = "long";
}
}
element avs_eth_0.mms_reg
{
datum baseAddress
{
value = "128";
value = "512";
type = "long";
}
}
......@@ -232,6 +296,14 @@
type = "long";
}
}
element Beam0_eth.mms_tse
{
datum baseAddress
{
value = "20480";
type = "long";
}
}
element onchip_memory2_0
{
datum _sortIndex
......@@ -283,10 +355,18 @@
}
datum baseAddress
{
value = "320";
value = "768";
type = "long";
}
}
element reg_common
{
datum _sortIndex
{
value = "20";
type = "int";
}
}
element reg_dpmm_ctrl
{
datum _sortIndex
......@@ -363,15 +443,7 @@
{
datum baseAddress
{
value = "192";
type = "long";
}
}
element pio_wdi.s1
{
datum baseAddress
{
value = "336";
value = "640";
type = "long";
}
}
......@@ -388,6 +460,14 @@
type = "long";
}
}
element pio_wdi.s1
{
datum baseAddress
{
value = "784";
type = "long";
}
}
element timer_0
{
datum _sortIndex
......@@ -408,10 +488,10 @@
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VHDL" />
<parameter name="maxAdditionalLatency" value="0" />
<parameter name="projectName" value="" />
<parameter name="projectName" value="unb1_rfidb.qpf" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="1" />
<parameter name="timeStamp" value="1441611640370" />
<parameter name="timeStamp" value="1444585069452" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
......@@ -1256,13 +1336,6 @@
name="coe_ram_writedata_export_from_the_avs_eth_0"
internal="coe_ram_writedata_export" />
</interface>
<interface
name="altpll_0_c3_conduit"
internal="altpll_0.c3_conduit"
type="conduit"
dir="end">
<port name="c3_from_the_altpll_0" internal="c3" />
</interface>
<interface
name="reg_remu_read"
internal="reg_remu.read"
......@@ -1270,6 +1343,174 @@
dir="end">
<port name="coe_read_export_from_the_reg_remu" internal="coe_read_export" />
</interface>
<interface
name="reg_common_reset"
internal="reg_common.reset"
type="conduit"
dir="end" />
<interface
name="reg_common_clk"
internal="reg_common.clk"
type="conduit"
dir="end" />
<interface
name="reg_common_address"
internal="reg_common.address"
type="conduit"
dir="end" />
<interface
name="reg_common_write"
internal="reg_common.write"
type="conduit"
dir="end" />
<interface
name="reg_common_writedata"
internal="reg_common.writedata"
type="conduit"
dir="end" />
<interface
name="reg_common_read"
internal="reg_common.read"
type="conduit"
dir="end" />
<interface
name="reg_common_readdata"
internal="reg_common.readdata"
type="conduit"
dir="end" />
<interface
name="beam0_dp_offload_rx_reg_hdr_dat_reset"
internal="Beam0_dp_offload_rx_reg_hdr_dat.reset"
type="conduit"
dir="end" />
<interface
name="beam0_dp_offload_rx_reg_hdr_dat_clk"
internal="Beam0_dp_offload_rx_reg_hdr_dat.clk"
type="conduit"
dir="end" />
<interface
name="beam0_dp_offload_rx_reg_hdr_dat_address"
internal="Beam0_dp_offload_rx_reg_hdr_dat.address"
type="conduit"
dir="end" />
<interface
name="beam0_dp_offload_rx_reg_hdr_dat_write"
internal="Beam0_dp_offload_rx_reg_hdr_dat.write"
type="conduit"
dir="end" />
<interface
name="beam0_dp_offload_rx_reg_hdr_dat_writedata"
internal="Beam0_dp_offload_rx_reg_hdr_dat.writedata"
type="conduit"
dir="end" />
<interface
name="beam0_dp_offload_rx_reg_hdr_dat_read"
internal="Beam0_dp_offload_rx_reg_hdr_dat.read"
type="conduit"
dir="end" />
<interface
name="beam0_dp_offload_rx_reg_hdr_dat_readdata"
internal="Beam0_dp_offload_rx_reg_hdr_dat.readdata"
type="conduit"
dir="end" />
<interface
name="beam0_eth_tse_address"
internal="Beam0_eth.tse_address"
type="conduit"
dir="end" />
<interface
name="beam0_eth_tse_write"
internal="Beam0_eth.tse_write"
type="conduit"
dir="end" />
<interface
name="beam0_eth_tse_read"
internal="Beam0_eth.tse_read"
type="conduit"
dir="end" />
<interface
name="beam0_eth_tse_writedata"
internal="Beam0_eth.tse_writedata"
type="conduit"
dir="end" />
<interface
name="beam0_eth_tse_readdata"
internal="Beam0_eth.tse_readdata"
type="conduit"
dir="end" />
<interface
name="beam0_eth_tse_waitrequest"
internal="Beam0_eth.tse_waitrequest"
type="conduit"
dir="end" />
<interface
name="beam0_eth_reg_address"
internal="Beam0_eth.reg_address"
type="conduit"
dir="end" />
<interface
name="beam0_eth_reg_write"
internal="Beam0_eth.reg_write"
type="conduit"
dir="end" />
<interface
name="beam0_eth_reg_read"
internal="Beam0_eth.reg_read"
type="conduit"
dir="end" />
<interface
name="beam0_eth_reg_readdata"
internal="Beam0_eth.reg_readdata"
type="conduit"
dir="end" />
<interface
name="beam0_eth_ram_address"
internal="Beam0_eth.ram_address"
type="conduit"
dir="end" />
<interface
name="beam0_eth_ram_write"
internal="Beam0_eth.ram_write"
type="conduit"
dir="end" />
<interface
name="beam0_eth_ram_read"
internal="Beam0_eth.ram_read"
type="conduit"
dir="end" />
<interface
name="beam0_eth_ram_writedata"
internal="Beam0_eth.ram_writedata"
type="conduit"
dir="end" />
<interface
name="beam0_eth_ram_readdata"
internal="Beam0_eth.ram_readdata"
type="conduit"
dir="end" />
<interface
name="beam0_eth_irq"
internal="Beam0_eth.irq"
type="conduit"
dir="end" />
<interface
name="beam0_eth_reg_writedata"
internal="Beam0_eth.reg_writedata"
type="conduit"
dir="end" />
<interface
name="beam0_eth_reset"
internal="Beam0_eth.reset"
type="conduit"
dir="end" />
<interface
name="beam0_eth_clk"
internal="Beam0_eth.clk"
type="conduit"
dir="end" />
<interface name="altpll_0_c3" internal="altpll_0.c3" type="clock" dir="start">
<port name="cal_rec_clk" internal="c3" />
</interface>
<module kind="clock_source" version="11.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="25000000" />
<parameter name="clockFrequencyKnown" value="true" />
......@@ -1282,7 +1523,7 @@
enabled="1"
name="onchip_memory2_0">
<parameter name="allowInSystemMemoryContentEditor" value="false" />
<parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_0</parameter>
<parameter name="autoInitializationFileName">qsys_unb1_rfidb_onchip_memory2_0</parameter>
<parameter name="blockType" value="M144K" />
<parameter name="dataWidth" value="32" />
<parameter name="deviceFamily" value="Stratix IV" />
......@@ -1427,7 +1668,7 @@ q]]></parameter>
<parameter name="PORT_clk0" value="PORT_USED" />
<parameter name="PORT_clk1" value="PORT_USED" />
<parameter name="PORT_clk2" value="PORT_USED" />
<parameter name="PORT_clk3" value="PORT_UNUSED" />
<parameter name="PORT_clk3" value="PORT_USED" />
<parameter name="PORT_clk4" value="PORT_UNUSED" />
<parameter name="PORT_clk5" value="PORT_UNUSED" />
<parameter name="PORT_clk6" value="PORT_UNUSED" />
......@@ -1476,7 +1717,7 @@ q]]></parameter>
<parameter name="USING_FBMIMICBIDIR_PORT" value="OFF" />
<parameter name="SCAN_CHAIN_MIF_FILE" value="" />
<parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
<parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 1 CT#PORT_clk9 PORT_UNUSED CT#PORT_clk8 PORT_UNUSED CT#PORT_clk7 PORT_UNUSED CT#PORT_clk6 PORT_UNUSED CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 5 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT 0 CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 10 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 4 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 40000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_FBOUT PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 5 CT#INTENDED_DEVICE_FAMILY {Stratix IV} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 5 CT#CLK3_MULTIPLY_BY 8 CT#USING_FBMIMICBIDIR_PORT OFF CT#PORT_LOCKED PORT_USED</parameter>
<parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 1 CT#PORT_clk9 PORT_UNUSED CT#PORT_clk8 PORT_UNUSED CT#PORT_clk7 PORT_UNUSED CT#PORT_clk6 PORT_UNUSED CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 5 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT 0 CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 10 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 4 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 40000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_FBOUT PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 5 CT#INTENDED_DEVICE_FAMILY {Stratix IV} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 5 CT#CLK3_MULTIPLY_BY 8 CT#USING_FBMIMICBIDIR_PORT OFF CT#PORT_LOCKED PORT_USED</parameter>
<parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 25.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ3 40.00000000 PT#OUTPUT_FREQ2 125.00000000 PT#OUTPUT_FREQ1 20.00000000 PT#OUTPUT_FREQ0 50.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 0.00000000 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE3 40.000000 PT#EFF_OUTPUT_FREQ_VALUE2 125.000000 PT#EFF_OUTPUT_FREQ_VALUE1 20.000000 PT#EFF_OUTPUT_FREQ_VALUE0 50.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR3 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Stratix IV} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1256297171721465.mif PT#ACTIVECLK_CHECK 0</parameter>
<parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
<parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
......@@ -1659,7 +1900,7 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='reg_remu.mem' start='0x100' end='0x120' /><slave name='reg_epcs.mem' start='0x120' end='0x140' /><slave name='altpll_0.pll_slave' start='0x140' end='0x150' /><slave name='pio_wdi.s1' start='0x150' end='0x160' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x160' end='0x168' /><slave name='pio_pps.mem' start='0x168' end='0x170' /><slave name='reg_dpmm_ctrl.mem' start='0x170' end='0x178' /><slave name='reg_dpmm_data.mem' start='0x178' end='0x180' /><slave name='reg_mmdp_ctrl.mem' start='0x180' end='0x188' /><slave name='reg_mmdp_data.mem' start='0x188' end='0x190' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_common.mem' start='0x80' end='0x100' /><slave name='Beam0_dp_offload_rx_reg_hdr_dat.mem' start='0x100' end='0x200' /><slave name='avs_eth_0.mms_reg' start='0x200' end='0x240' /><slave name='Beam0_eth.mms_reg' start='0x240' end='0x280' /><slave name='timer_0.s1' start='0x280' end='0x2A0' /><slave name='reg_unb_sens.mem' start='0x2A0' end='0x2C0' /><slave name='reg_remu.mem' start='0x2C0' end='0x2E0' /><slave name='reg_epcs.mem' start='0x2E0' end='0x300' /><slave name='altpll_0.pll_slave' start='0x300' end='0x310' /><slave name='pio_wdi.s1' start='0x310' end='0x320' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x320' end='0x328' /><slave name='pio_pps.mem' start='0x328' end='0x330' /><slave name='reg_dpmm_ctrl.mem' start='0x330' end='0x338' /><slave name='reg_dpmm_data.mem' start='0x338' end='0x340' /><slave name='reg_mmdp_ctrl.mem' start='0x340' end='0x348' /><slave name='reg_mmdp_data.mem' start='0x348' end='0x350' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='Beam0_eth.mms_tse' start='0x5000' end='0x6000' /><slave name='Beam0_eth.mms_ram' start='0x6000' end='0x7000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
<parameter name="clockFrequency" value="50000000" />
<parameter name="deviceFamilyName" value="Stratix IV" />
<parameter name="internalIrqMaskSystemInfo" value="7" />
......@@ -1679,6 +1920,23 @@ q]]></parameter>
<parameter name="EXPLICIT_CLOCK_RATE" value="0" />
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
</module>
<module kind="avs_common_mm" version="1.0" enabled="1" name="reg_common">
<parameter name="g_adr_w" value="5" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
</module>
<module kind="avs2_eth_coe" version="1.0" enabled="1" name="Beam0_eth">
<parameter name="AUTO_MM_CLOCK_RATE" value="50000000" />
</module>
<module
kind="avs_common_mm"
version="1.0"
enabled="1"
name="Beam0_dp_offload_rx_reg_hdr_dat">
<parameter name="g_adr_w" value="6" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
</module>
<connection
kind="avalon"
version="11.1"
......@@ -1717,7 +1975,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0160" />
<parameter name="baseAddress" value="0x0320" />
</connection>
<connection
kind="interrupt"
......@@ -1732,7 +1990,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="altpll_0.pll_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0140" />
<parameter name="baseAddress" value="0x0300" />
</connection>
<connection kind="clock" version="11.1" start="altpll_0.c0" end="cpu_0.clk" />
<connection
......@@ -1753,7 +2011,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="pio_wdi.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0150" />
<parameter name="baseAddress" value="0x0310" />
</connection>
<connection kind="clock" version="11.1" start="altpll_0.c0" end="timer_0.clk" />
<connection
......@@ -1762,7 +2020,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="timer_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00c0" />
<parameter name="baseAddress" value="0x0280" />
</connection>
<connection kind="interrupt" version="11.1" start="cpu_0.d_irq" end="timer_0.irq">
<parameter name="irqNumber" value="1" />
......@@ -1778,7 +2036,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_unb_sens.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00e0" />
<parameter name="baseAddress" value="0x02a0" />
</connection>
<connection
kind="clock"
......@@ -1813,7 +2071,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0168" />
<parameter name="baseAddress" value="0x0328" />
</connection>
<connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_wdi.system" />
<connection
......@@ -1839,7 +2097,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="avs_eth_0.mms_reg">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0080" />
<parameter name="baseAddress" value="0x0200" />
</connection>
<connection
kind="avalon"
......@@ -1863,7 +2121,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_remu.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0100" />
<parameter name="baseAddress" value="0x02c0" />
</connection>
<connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_epcs.system" />
<connection
......@@ -1872,7 +2130,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_epcs.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0120" />
<parameter name="baseAddress" value="0x02e0" />
</connection>
<connection
kind="clock"
......@@ -1885,7 +2143,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0170" />
<parameter name="baseAddress" value="0x0330" />
</connection>
<connection
kind="clock"
......@@ -1898,7 +2156,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0178" />
<parameter name="baseAddress" value="0x0338" />
</connection>
<connection
kind="clock"
......@@ -1911,7 +2169,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0180" />
<parameter name="baseAddress" value="0x0340" />
</connection>
<connection
kind="clock"
......@@ -1924,7 +2182,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0188" />
<parameter name="baseAddress" value="0x0348" />
</connection>
<connection
kind="reset"
......@@ -2107,4 +2365,70 @@ q]]></parameter>
start="cpu_0.jtag_debug_module_reset"
end="cpu_0.reset_n" />
<connection kind="clock" version="11.1" start="altpll_0.c0" end="c0.in_clk" />
<connection
kind="clock"
version="11.1"
start="altpll_0.c0"
end="reg_common.system" />
<connection
kind="reset"
version="11.1"
start="clk_0.clk_reset"
end="reg_common.system_reset" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
end="reg_common.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0080" />
</connection>
<connection kind="clock" version="11.1" start="altpll_0.c0" end="Beam0_eth.mm" />
<connection
kind="reset"
version="11.1"
start="clk_0.clk_reset"
end="Beam0_eth.mm_reset" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
end="Beam0_eth.mms_tse">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x5000" />
</connection>
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
end="Beam0_eth.mms_reg">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0240" />
</connection>
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
end="Beam0_eth.mms_ram">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x6000" />
</connection>
<connection
kind="reset"
version="11.1"
start="clk_0.clk_reset"
end="Beam0_dp_offload_rx_reg_hdr_dat.system_reset" />
<connection
kind="clock"
version="11.1"
start="altpll_0.c0"
end="Beam0_dp_offload_rx_reg_hdr_dat.system" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
end="Beam0_dp_offload_rx_reg_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0100" />
</connection>
</system>
applications/rfidb/designs/rfidb/src/vhdl/mmm_unb1_rfidb.vhd
+ 87
− 11
View file @ 111781f6
......@@ -24,6 +24,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
......@@ -36,7 +37,8 @@ ENTITY mmm_unb1_rfidb IS
g_sim : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
g_use_qsys : BOOLEAN := FALSE
g_use_qsys : BOOLEAN := FALSE;
g_hdr_field_arr : t_common_field_arr
);
PORT (
xo_clk : IN STD_LOGIC;
......@@ -48,6 +50,7 @@ ENTITY mmm_unb1_rfidb IS
mm_locked : OUT STD_LOGIC;
epcs_clk : OUT STD_LOGIC;
cal_rec_clk : OUT STD_LOGIC;
pout_wdi : OUT STD_LOGIC;
......@@ -97,21 +100,60 @@ ENTITY mmm_unb1_rfidb IS
-- Remote Update
reg_remu_mosi : OUT t_mem_mosi;
reg_remu_miso : IN t_mem_miso
reg_remu_miso : IN t_mem_miso;
-- BEAM0_eth
Beam0_eth_tse_mosi : OUT t_mem_mosi;
Beam0_eth_tse_miso : IN t_mem_miso;
Beam0_eth_reg_mosi : OUT t_mem_mosi;
Beam0_eth_reg_miso : IN t_mem_miso;
Beam0_eth_reg_interrupt : IN STD_LOGIC;
Beam0_eth_ram_mosi : OUT t_mem_mosi;
Beam0_eth_ram_miso : IN t_mem_miso;
-- BEAM0_offload
Beam0_dp_offload_rx_reg_hdr_dat_mosi : OUT t_mem_mosi;
Beam0_dp_offload_rx_reg_hdr_dat_miso : IN t_mem_miso
);
END mmm_unb1_rfidb;
ARCHITECTURE str OF mmm_unb1_rfidb IS
CONSTANT c_mm_clk_period : TIME := 8 ns; -- 125 MHz
CONSTANT c_eth_clk_period : TIME := 8 ns;
CONSTANT c_cal_rec_clk_period : TIME := 25 ns;
CONSTANT c_epcs_clk_period : TIME := 50 ns; -- 20 MHz
CONSTANT c_sim_node_type : STRING(1 TO 2):= sel_a_b(g_sim_node_nr<4, "FN", "BN");
CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type="BN", g_sim_node_nr-4, g_sim_node_nr);
SIGNAL i_mm_clk : STD_LOGIC := '1';
SIGNAL i_eth1g_tse_clk : STD_LOGIC := '1';
SIGNAL i_cal_rec_clk : STD_LOGIC := '1';
SIGNAL i_epcs_clk : STD_LOGIC := '1';
-- dp_offload
CONSTANT c_beam_nof_streams : NATURAL := 1;
CONSTANT c_RFI_DB_nof_streams : NATURAL := 1;
CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb1_board_peripherals_mm_reg_default
CONSTANT c_reg_dp_offload_tx_multi_adr_w : NATURAL := ceil_log2(c_RFI_DB_nof_streams* pow2(c_reg_dp_offload_tx_adr_w));
CONSTANT c_reg_dp_offload_tx_hdr_dat_nof_words : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w);
CONSTANT c_reg_dp_offload_tx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_dat_nof_words);
CONSTANT c_reg_dp_offload_tx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(c_RFI_DB_nof_streams* pow2(c_reg_dp_offload_tx_hdr_dat_adr_w));
CONSTANT c_reg_dp_offload_tx_hdr_ovr_nof_words : NATURAL := g_hdr_field_arr'LENGTH;
CONSTANT c_reg_dp_offload_tx_hdr_ovr_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_ovr_nof_words);
CONSTANT c_reg_dp_offload_tx_hdr_ovr_multi_adr_w : NATURAL := ceil_log2(c_RFI_DB_nof_streams* pow2(c_reg_dp_offload_tx_hdr_ovr_adr_w));
CONSTANT c_reg_dp_offload_rx_hdr_dat_nof_words : NATURAL := field_nof_words(g_hdr_field_arr, c_word_w);
CONSTANT c_reg_dp_offload_rx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_hdr_dat_nof_words);
CONSTANT c_reg_dp_offload_rx_hdr_dat_multi_adr_w : NATURAL := ceil_log2(c_beam_nof_streams* pow2(c_reg_dp_offload_rx_hdr_dat_adr_w));
----------------------------------------------------------------------------
-- mm_file component
----------------------------------------------------------------------------
......@@ -134,6 +176,8 @@ BEGIN
mm_clk <= i_mm_clk;
epcs_clk <= i_epcs_clk;
eth1g_tse_clk <= i_eth1g_tse_clk;
cal_rec_clk <= i_cal_rec_clk;
----------------------------------------------------------------------------
......@@ -141,6 +185,8 @@ BEGIN
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
i_cal_rec_clk <= NOT i_cal_rec_clk AFTER c_cal_rec_clk_period/2;
i_eth1g_tse_clk <= NOT i_eth1g_tse_clk AFTER c_eth_clk_period/2;
i_mm_clk <= NOT i_mm_clk AFTER c_mm_clk_period/2;
mm_locked <= '0', '1' AFTER c_mm_clk_period*5;
i_epcs_clk <= NOT i_epcs_clk AFTER c_epcs_clk_period/2;
......@@ -181,8 +227,9 @@ BEGIN
clk_0 => xo_clk,
reset_n => xo_rst_n,
mm_clk => i_mm_clk,
tse_clk => eth1g_tse_clk,
tse_clk => i_eth1g_tse_clk,
epcs_clk => i_epcs_clk,
cal_rec_clk => i_cal_rec_clk,
-- the_altpll_0
locked_from_the_altpll_0 => mm_locked,
......@@ -311,7 +358,36 @@ BEGIN
coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0)
coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- BEAM0_eth
beam0_eth_tse_address_export => BEAM0_eth_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
beam0_eth_tse_write_export => BEAM0_eth_tse_mosi.wr,
beam0_eth_tse_writedata_export => BEAM0_eth_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
beam0_eth_tse_read_export => BEAM0_eth_tse_mosi.rd,
beam0_eth_tse_readdata_export => BEAM0_eth_tse_miso.rddata(c_word_w-1 DOWNTO 0),
beam0_eth_tse_waitrequest_export => BEAM0_eth_tse_miso.waitrequest,
beam0_eth_reg_address_export => BEAM0_eth_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
beam0_eth_reg_write_export => BEAM0_eth_reg_mosi.wr,
beam0_eth_reg_writedata_export => BEAM0_eth_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
beam0_eth_reg_read_export => BEAM0_eth_reg_mosi.rd,
beam0_eth_reg_readdata_export => BEAM0_eth_reg_miso.rddata(c_word_w-1 DOWNTO 0),
beam0_eth_ram_address_export => BEAM0_eth_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
beam0_eth_ram_write_export => BEAM0_eth_ram_mosi.wr,
beam0_eth_ram_writedata_export => BEAM0_eth_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
beam0_eth_ram_read_export => BEAM0_eth_ram_mosi.rd,
beam0_eth_ram_readdata_export => BEAM0_eth_ram_miso.rddata(c_word_w-1 DOWNTO 0),
beam0_eth_irq_export => open,
Beam0_dp_offload_rx_reg_hdr_dat_reset_export => open,
Beam0_dp_offload_rx_reg_hdr_dat_clk_export => open,
Beam0_dp_offload_rx_reg_hdr_dat_address_export => Beam0_dp_offload_rx_reg_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w-1 DOWNTO 0),
Beam0_dp_offload_rx_reg_hdr_dat_write_export => Beam0_dp_offload_rx_reg_hdr_dat_mosi.wr,
Beam0_dp_offload_rx_reg_hdr_dat_writedata_export => Beam0_dp_offload_rx_reg_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
Beam0_dp_offload_rx_reg_hdr_dat_read_export => Beam0_dp_offload_rx_reg_hdr_dat_mosi.rd,
Beam0_dp_offload_rx_reg_hdr_dat_readdata_export => Beam0_dp_offload_rx_reg_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
......
applications/rfidb/designs/rfidb/src/vhdl/qsys_unb1_rfidb_pkg.vhd
+ 140
− 113
View file @ 111781f6
......@@ -27,10 +27,7 @@ PACKAGE qsys_unb1_rfidb_pkg IS
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
-----------------------------------------------------------------------------
COMPONENT qsys_unb1_rfidb is
component qsys_unb1_rfidb is
port (
coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
......@@ -136,11 +133,41 @@ PACKAGE qsys_unb1_rfidb_pkg IS
locked_from_the_altpll_0 : out std_logic; -- export
coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
c3_from_the_altpll_0 : out std_logic; -- export
coe_read_export_from_the_reg_remu : out std_logic -- export
coe_read_export_from_the_reg_remu : out std_logic; -- export
reg_common_reset_export : out std_logic; -- export
reg_common_clk_export : out std_logic; -- export
reg_common_address_export : out std_logic_vector(4 downto 0); -- export
reg_common_write_export : out std_logic; -- export
reg_common_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_common_read_export : out std_logic; -- export
reg_common_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
beam0_dp_offload_rx_reg_hdr_dat_reset_export : out std_logic; -- export
beam0_dp_offload_rx_reg_hdr_dat_clk_export : out std_logic; -- export
beam0_dp_offload_rx_reg_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
beam0_dp_offload_rx_reg_hdr_dat_write_export : out std_logic; -- export
beam0_dp_offload_rx_reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
beam0_dp_offload_rx_reg_hdr_dat_read_export : out std_logic; -- export
beam0_dp_offload_rx_reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
beam0_eth_tse_address_export : out std_logic_vector(9 downto 0); -- export
beam0_eth_tse_write_export : out std_logic; -- export
beam0_eth_tse_read_export : out std_logic; -- export
beam0_eth_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
beam0_eth_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
beam0_eth_tse_waitrequest_export : in std_logic := 'X'; -- export
beam0_eth_reg_address_export : out std_logic_vector(3 downto 0); -- export
beam0_eth_reg_write_export : out std_logic; -- export
beam0_eth_reg_read_export : out std_logic; -- export
beam0_eth_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
beam0_eth_ram_address_export : out std_logic_vector(9 downto 0); -- export
beam0_eth_ram_write_export : out std_logic; -- export
beam0_eth_ram_read_export : out std_logic; -- export
beam0_eth_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
beam0_eth_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
beam0_eth_irq_export : in std_logic := 'X'; -- export
beam0_eth_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
cal_rec_clk : out std_logic -- clk
);
END COMPONENT qsys_unb1_rfidb;
end component qsys_unb1_rfidb;
END qsys_unb1_rfidb_pkg;
applications/rfidb/designs/rfidb/src/vhdl/unb1_rfidb.vhd
+ 275
− 11
View file @ 111781f6
......@@ -20,12 +20,17 @@
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb1_board_lib;
LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE tech_tse_lib.tech_tse_pkg.ALL;
USE eth_lib.eth_pkg.ALL;
ENTITY unb1_rfidb IS
GENERIC (
......@@ -36,7 +41,8 @@ ENTITY unb1_rfidb IS
g_sim_node_nr : NATURAL := 0;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
g_SFP_number : natural := 1
);
PORT (
-- GENERAL
......@@ -58,7 +64,18 @@ ENTITY unb1_rfidb IS
-- 1GbE Control Interface
ETH_clk : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC;
ETH_SGOUT : OUT STD_LOGIC
ETH_SGOUT : OUT STD_LOGIC;
-- OCB Interface
BN_SFP_RX : in STD_LOGIC_VECTOR(g_SFP_number-1 DOWNTO 0);
BN_SFP_TX : out STD_LOGIC_VECTOR(g_SFP_number-1 DOWNTO 0);
BN_SFP_RXLOS : in STD_LOGIC_VECTOR(g_SFP_number-1 DOWNTO 0);
BN_SFP_TXFAULT : in STD_LOGIC_VECTOR(g_SFP_number-1 DOWNTO 0);
BN_SFP_TXDISABL : out STD_LOGIC_VECTOR(g_SFP_number-1 DOWNTO 0);
BN_SFP_PRS : in STD_LOGIC_VECTOR(g_SFP_number-1 DOWNTO 0);
BN_SFP_SCL : out STD_LOGIC_VECTOR(g_SFP_number-1 DOWNTO 0);
BN_SFP_SDA : inout STD_LOGIC_VECTOR(g_SFP_number-1 DOWNTO 0)
);
END unb1_rfidb;
......@@ -84,10 +101,11 @@ ARCHITECTURE str OF unb1_rfidb IS
SIGNAL mm_locked : STD_LOGIC;
SIGNAL mm_rst : STD_LOGIC;
SIGNAL st_rst : STD_LOGIC;
SIGNAL st_clk : STD_LOGIC;
SIGNAL dp_rst : STD_LOGIC;
SIGNAL dp_clk : STD_LOGIC;
SIGNAL epcs_clk : STD_LOGIC;
SIGNAL cal_rec_clk : STD_LOGIC;
-- PIOs
SIGNAL pout_wdi : STD_LOGIC;
......@@ -141,6 +159,83 @@ ARCHITECTURE str OF unb1_rfidb IS
SIGNAL reg_remu_mosi : t_mem_mosi;
SIGNAL reg_remu_miso : t_mem_miso;
-- REG_COMMON
SIGNAL reg_common_mosi : t_mem_mosi;
SIGNAL reg_common_miso : t_mem_miso;
SIGNAL cnt_valid_udp_frm : STD_LOGIC_VECTOR(c_mem_reg.dat_w*c_mem_reg.nof_dat-1 DOWNTO 0);
SIGNAL ctrl_udp_loopback : STD_LOGIC_VECTOR(c_mem_reg.dat_w*c_mem_reg.nof_dat-1 DOWNTO 0);
-- dp_offload
CONSTANT c_nof_hdr_fields : NATURAL := 4+12+4+9; -- Total header bits = 512
CONSTANT c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
( field_name_pad("eth_dst_mac" ), " ", 48, field_default(x"002286080000") ),
( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
( field_name_pad("ip_total_length" ), " ", 16, field_default(128) ),
( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
( field_name_pad("udp_src_port" ), " ", 16, field_default(4000) ),
( field_name_pad("udp_dst_port" ), " ", 16, field_default(4000) ),
( field_name_pad("udp_total_length" ), " ", 16, field_default(108) ),
( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1101"&"111111111100"&"1111"&"001111111";
-- BEAM_0 eth
CONSTANT c_beam_nof_streams : NATURAL := 1;
CONSTANT c_data_w : NATURAL := c_tech_tse_data_w;
SIGNAL Beam0_udp_rx_siso_arr : t_dp_sosi_arr(c_eth_nof_udp_ports-1 DOWNTO 0);
SIGNAL Beam0_udp_rx_sosi_arr : t_dp_siso_arr(c_eth_nof_udp_ports-1 DOWNTO 0);
SIGNAL Beam0_eth_mm_rst : STD_LOGIC;
SIGNAL Beam0_eth_tse_mosi : t_mem_mosi;
SIGNAL Beam0_eth_tse_miso : t_mem_miso;
SIGNAL Beam0_eth_reg_mosi : t_mem_mosi;
SIGNAL Beam0_eth_reg_miso : t_mem_miso;
SIGNAL Beam0_eth_reg_interrupt : STD_LOGIC;
SIGNAL Beam0_eth_ram_mosi : t_mem_mosi;
SIGNAL Beam0_eth_ram_miso : t_mem_miso;
-- BEAM_0 udp_offload
CONSTANT c_st_eth : BOOLEAN := TRUE; -- TRUE forwards the UDP stream to the 1GbE module, FALSE loops back the node function
-- source to its sink to bypass the 1GbE, but still performs packetizing and deframing.
SIGNAL Beam0_dp_offload_rx_reg_hdr_dat_mosi : t_mem_mosi;
SIGNAL Beam0_dp_offload_rx_reg_hdr_dat_miso : t_mem_miso;
SIGNAL Beam0_buf_rx_siso_arr : t_dp_siso_arr(c_beam_nof_streams-1 DOWNTO 0);
SIGNAL Beam0_buf_rx_sosi_arr : t_dp_sosi_arr(c_beam_nof_streams-1 DOWNTO 0);
SIGNAL Beam0_hdr_fields_out_arr : t_slv_1024_arr(c_beam_nof_streams-1 DOWNTO 0);
SIGNAL Beam0_rx_siso : t_dp_siso;
SIGNAL Beam0_rx_sosi : t_dp_sosi;
-- Signal Tap
SIGNAL acq_data_in : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL acq_trigger_in : STD_LOGIC_VECTOR( 3 DOWNTO 0);
BEGIN
-----------------------------------------------------------------------------
......@@ -173,11 +268,11 @@ BEGIN
epcs_clk => epcs_clk,
dp_rst => st_rst,
dp_clk => st_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
dp_pps => OPEN,
dp_rst_in => st_rst,
dp_clk_in => st_clk,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
-- Toggle WDI
pout_wdi => pout_wdi,
......@@ -260,7 +355,8 @@ BEGIN
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_use_qsys => c_use_qsys
g_use_qsys => c_use_qsys,
g_hdr_field_arr => c_hdr_field_arr
)
PORT MAP(
xo_clk => xo_clk,
......@@ -272,6 +368,7 @@ BEGIN
mm_locked => mm_locked,
epcs_clk => epcs_clk,
cal_rec_clk => cal_rec_clk,
-- PIOs
pout_wdi => pout_wdi,
......@@ -323,7 +420,21 @@ BEGIN
-- Remote Update
reg_remu_mosi => reg_remu_mosi,
reg_remu_miso => reg_remu_miso
reg_remu_miso => reg_remu_miso,
-- Beam0 1GbE interface
Beam0_eth_tse_mosi => Beam0_eth_tse_mosi ,
Beam0_eth_tse_miso => Beam0_eth_tse_miso ,
Beam0_eth_reg_mosi => Beam0_eth_reg_mosi ,
Beam0_eth_reg_miso => Beam0_eth_reg_miso ,
Beam0_eth_reg_interrupt => Beam0_eth_reg_interrupt,
Beam0_eth_ram_mosi => Beam0_eth_ram_mosi ,
Beam0_eth_ram_miso => Beam0_eth_ram_miso ,
Beam0_dp_offload_rx_reg_hdr_dat_mosi => Beam0_dp_offload_rx_reg_hdr_dat_mosi,
Beam0_dp_offload_rx_reg_hdr_dat_miso => Beam0_dp_offload_rx_reg_hdr_dat_miso
);
-----------------------------------------------------------------------------
......@@ -331,5 +442,158 @@ BEGIN
-----------------------------------------------------------------------------
-- Insert node_[design_name] here
u_mms_common_reg : ENTITY common_lib.mms_common_reg
GENERIC MAP (
-- TYPE t_c_mem IS RECORD
-- latency : NATURAL; -- read latency
-- adr_w : NATURAL;
-- dat_w : NATURAL;
-- nof_dat : NATURAL; -- optional, nof dat words <= 2**adr_w
-- init_sl : STD_LOGIC; -- optional, init all dat words to std_logic '0', '1' or 'X'
g_mm_reg => c_mem_reg --(1, 1, 32, 1, 'X')
)
PORT MAP(
-- Clocks and reset
mm_rst => mm_rst,
mm_clk => mm_clk,
st_rst => dp_rst,
st_clk => dp_clk,
-- MM bus access in memory-mapped clock domain
reg_mosi => reg_common_mosi,
reg_miso => reg_common_miso,
-- MM register IO in ST clock domain
-- 1) Connect out_reg to in_reg for write and readback register.
-- 2) Do not connect out_reg to in_reg for seperate write only register and read only register at the same address.
-- 3) Leave out_reg OPEN for read only register.
in_reg => cnt_valid_udp_frm,
out_reg => ctrl_udp_loopback
);
cnt_valid: PROCESS(dp_rst,dp_clk)
BEGIN
IF dp_rst = '1' THEN
cnt_valid_udp_frm <= (others => '0');
ELSIF rising_edge(dp_clk) THEN
FOR i in Beam0_udp_rx_siso_arr'RANGE LOOP
IF Beam0_udp_rx_siso_arr(i).valid = '1' THEN
cnt_valid_udp_frm <= std_logic_vector(unsigned(cnt_valid_udp_frm) + 1);
END IF;
END LOOP;
END IF;
END PROCESS;
u_Beam0_eth : ENTITY eth_lib.eth
GENERIC MAP(
g_init_ip_address => X"0a0a010a",
g_cross_clock_domain => TRUE, -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
g_ETH_PHY => "XCVR", -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
g_ihl20 => TRUE
)
PORT MAP(
mm_rst => mm_rst,
mm_clk => mm_clk,
eth_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
st_rst => dp_rst,
st_clk => dp_clk,
cal_rec_clk => cal_rec_clk,
-- UDP interface
udp_tx_snk_in_arr => (others => c_dp_sosi_rst),
udp_tx_snk_out_arr => OPEN,
udp_rx_src_in_arr => Beam0_udp_rx_sosi_arr,
udp_rx_src_out_arr => Beam0_udp_rx_siso_arr,
-- Memory Mapped Slaves
tse_sla_in => Beam0_eth_tse_mosi, -- ETH TSE MAC registers
tse_sla_out => Beam0_eth_tse_miso,
reg_sla_in => Beam0_eth_reg_mosi, -- ETH control and status registers
reg_sla_out => Beam0_eth_reg_miso,
reg_sla_interrupt => OPEN,
ram_sla_in => Beam0_eth_ram_mosi,
ram_sla_out => Beam0_eth_ram_miso,
-- PHY interface
eth_txp => BN_SFP_TX(0),
eth_rxp => BN_SFP_RX(0),
-- LED interface
tse_led => OPEN
);
Beam0_eth_reg_interrupt <= '0';
u_Beam0_dp_offload_rx : ENTITY dp_lib.dp_offload_rx
GENERIC MAP (
g_nof_streams => c_beam_nof_streams,
g_data_w => c_data_w,
g_hdr_field_arr => c_hdr_field_arr,
g_remove_crc => TRUE,
g_crc_nof_words => 1
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
reg_hdr_dat_mosi => Beam0_dp_offload_rx_reg_hdr_dat_mosi,
reg_hdr_dat_miso => Beam0_dp_offload_rx_reg_hdr_dat_miso,
snk_in_arr => Beam0_udp_rx_siso_arr(0 downto 0),
snk_out_arr => Beam0_udp_rx_sosi_arr(0 downto 0),
src_out_arr => Beam0_buf_rx_sosi_arr,
src_in_arr => Beam0_buf_rx_siso_arr,
hdr_fields_out_arr => Beam0_hdr_fields_out_arr
);
Beam0_buf_rx_siso_arr(0) <= Beam0_rx_siso;
Beam0_rx_sosi.sync <= sl(Beam0_hdr_fields_out_arr(0)(field_hi(c_hdr_field_arr, "usr_sync") DOWNTO field_lo(c_hdr_field_arr, "usr_sync" )));
Beam0_rx_sosi.bsn <= RESIZE_UVEC(Beam0_hdr_fields_out_arr(0)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn" )), c_dp_stream_bsn_w);
Beam0_rx_sosi.data <= Beam0_buf_rx_sosi_arr(0).data;
Beam0_rx_sosi.valid <= Beam0_buf_rx_sosi_arr(0).valid;
Beam0_rx_sosi.sop <= Beam0_buf_rx_sosi_arr(0).sop;
Beam0_rx_sosi.eop <= Beam0_buf_rx_sosi_arr(0).eop;
Beam0_rx_sosi.err <= Beam0_buf_rx_sosi_arr(0).err;
u_stp_Beam0 : ENTITY work.stp32
PORT MAP (
acq_clk => dp_clk,
acq_data_in => acq_data_in,
acq_trigger_in => acq_trigger_in
);
acq_data_in <= Beam0_rx_sosi.valid &
Beam0_rx_sosi.sop &
Beam0_rx_sosi.eop &
Beam0_rx_sosi.err(0) &
Beam0_rx_sosi.data(31 downto 0) ;
acq_trigger_in <= Beam0_rx_sosi.valid &
Beam0_rx_sosi.sop &
Beam0_rx_sosi.eop &
Beam0_rx_sosi.err(0) ;
BN_SFP_TXDISABL <= (others => '0');
BN_SFP_SCL <= (others => 'Z');
BN_SFP_SDA <= (others => 'Z');
END str;
applications/rfidb/designs/rfidb/tb/python/tc_unb1_rfidb.py
+ 101
− 2
View file @ 111781f6
......@@ -51,11 +51,14 @@ import pi_wdi
import pi_epcs
import pi_remu
import pi_eth
import pi_eth_OCB
import pi_common_reg
import pi_debug_wave
from tools import *
from common import *
from pi_common import *
from eth import *
def test_info(tc,io,cmd):
......@@ -121,6 +124,8 @@ def test_sensors(tc,io,cmd):
def test_ppsh(tc,io,cmd):
tc.set_section_id('Read PPSH capture count - ')
tc.append_log(1, '>>> NO PPS CONNECTED ON UNB1_RFIDB')
sys.exit(tc.get_result())
tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
......@@ -147,6 +152,9 @@ def test_wdi(tc,io,cmd):
def test_remu(tc,io,cmd):
tc.set_section_id('REMU start image in bank 1 - ')
tc.append_log(1, '>>> NOT TESTED IN UNB1_RFIDB')
sys.exit(tc.get_result())
tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
......@@ -170,20 +178,103 @@ def test_remu(tc,io,cmd):
def test_eth(tc,io,cmd):
tc.set_section_id('ETH status - ')
tc.set_section_id('ETH RAM buffer - ')
tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
eth = pi_eth.PiEth(tc, io)
# eth = pi_eth_OCB.PiEthOCB(tc, io, basename='AVS_ETH_0')
# eth.ETH_read_setup()
# eth.PCS_read_setup()
# eth.MAC_read_setup()
hdr = eth.read_hdr(0)
eth.disassemble_hdr(hdr)
tc.append_log(3, '')
def conf_eth_BeamA(tc,io,cmd):
tc.set_section_id('BeamA configuration - ')
tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
eth = pi_eth_OCB.PiEthOCB(tc, io, basename='BEAM0_ETH')
eth.ETH_config(IP_ADDR=0x0A0B0050, MAC_ADDR=CommonBytes(0x01230A0B0150, c_eth_mac_addr_len), Demux=(4346,))
# eth.ETH_config(IP_ADDR=0x0A0A0050, MAC_ADDR=CommonBytes(0x01230A0A0150, c_eth_mac_addr_len), Demux=(4346,))
eth.PCS_config()
eth.MAC_config(MAC_ADDR=CommonBytes(0x01230A0B0150, c_eth_mac_addr_len), promisc=True)
tc.append_log(3, '')
def test_eth_BeamA(tc,io,cmd):
tc.set_section_id('BeamB ETH status - ')
tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
eth = pi_eth_OCB.PiEthOCB(tc, io, basename='BEAM0_ETH')
eth.ETH_read_setup()
eth.PCS_read_setup()
eth.MAC_read_setup()
tc.append_log(3, '')
tc.set_section_id('BeamB RAM buffer - ')
hdr = eth.read_hdr(0)
eth.disassemble_hdr(hdr)
tc.append_log(3, '')
def conf_eth_BeamB(tc,io,cmd):
tc.set_section_id('BeamB configuration - ')
tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
eth = pi_eth_OCB.PiEthOCB(tc, io, basename='BEAM1_ETH')
eth.ETH_config(IP_ADDR=0x0A0B0050, MAC_ADDR=CommonBytes(0x01230A0B0150, c_eth_mac_addr_len), Demux=(4346,))
eth.PCS_config()
eth.MAC_config(MAC_ADDR=CommonBytes(0x01230A0B0150, c_eth_mac_addr_len), promisc=True)
tc.append_log(3, '')
def test_eth_BeamB(tc,io,cmd):
tc.set_section_id('BeamB status - ')
tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
eth = pi_eth_OCB.PiEthOCB(tc, io, basename='BEAM1_ETH')
hdr = eth.read_hdr(0)
eth.disassemble_hdr(hdr)
tc.append_log(3, '')
eth.ETH_read_setup()
eth.PCS_read_setup()
eth.MAC_read_setup()
tc.append_log(3, '')
def read_reg(tc,io,cmd):
tc.set_section_id('COMMON_REG cnt_valid_udp_frm - ')
tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
reg = pi_common_reg.PiCommonReg(tc, io, regSize=1)
reg.read_reg(radix='dec')
def test_flash(tc,io,cmd):
tc.set_section_id('Flash write to bank 1 - ')
tc.append_log(1, '>>> NOT TESTED IN UNB1_RFIDB')
sys.exit(tc.get_result())
tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
......@@ -210,6 +301,9 @@ def set_led(tc,dw,led,text):
def test_leds(tc,io,cmd):
tc.set_section_id('LED test - ')
tc.append_log(1, '>>> NOT TESTED IN UNB1_RFIDB')
sys.exit(tc.get_result())
tc.append_log(3, '>>>')
tc.append_log(1, '>>> %s' % help_text(tc,io,cmd))
tc.append_log(3, '>>>')
......@@ -246,6 +340,11 @@ Cmd['SENSORS'] = (test_sensors, 'using pi_unb_sens to readout sensors (access RE
Cmd['LED'] = (test_leds, 'using pi_debug_wave to set LEDs (access PIO_DEBUG_WAVE)','')
Cmd['PPSH'] = (test_ppsh, 'using pi_ppsh to read PPSH capture count (access PIO_PPS)','')
Cmd['ETH'] = (test_eth, 'using pi_eth to read eth status','')
Cmd['CFG_BA'] = (conf_eth_BeamA, 'using pi_eth_OCB to configure BeamA','')
Cmd['CFG_BB'] = (conf_eth_BeamB, 'using pi_eth_OCB to configure BeamB','')
Cmd['TST_BA'] = (test_eth_BeamA, 'using pi_eth_OCB to read BeamA status','')
Cmd['TST_BB'] = (test_eth_BeamB, 'using pi_eth_OCB to read BeamB status','')
Cmd['RD_REG'] = (read_reg, 'using pi_common_reg to read cnt_valid_udp_frm','')
Cmd['REMU'] = (test_remu, 'using pi_remu to load user image (access REG_REMU)','')
Cmd['WDI'] = (test_wdi, 'using pi_wdi to reset to image in bank 0 (access REG_WDI)','')
Cmd['sleep1'] = (sleep, 'Sleep 1 second','')
......
applications/rfidb/designs/rfidb/tb/vhdl/tb_unb1_rfidb.vhd
+ 23
− 2
View file @ 111781f6
......@@ -105,6 +105,16 @@ ARCHITECTURE tb OF tb_unb1_rfidb IS
CONSTANT c_uniboard_supply : REAL := 48.0; -- = assume 48.0 V on UniBoard
CONSTANT c_uniboard_adin : REAL := -1.0; -- = NC on UniBoard
CONSTANT c_SFP_number : natural := 1;
SIGNAL BN_SFP_RX : STD_LOGIC_VECTOR(c_SFP_number-1 DOWNTO 0) := (others => '0');
SIGNAL BN_SFP_TX : STD_LOGIC_VECTOR(c_SFP_number-1 DOWNTO 0);
SIGNAL BN_SFP_RXLOS : STD_LOGIC_VECTOR(c_SFP_number-1 DOWNTO 0) := (others => '0');
SIGNAL BN_SFP_TXFAULT : STD_LOGIC_VECTOR(c_SFP_number-1 DOWNTO 0) := (others => '0');
SIGNAL BN_SFP_TXDISABL : STD_LOGIC_VECTOR(c_SFP_number-1 DOWNTO 0);
SIGNAL BN_SFP_PRS : STD_LOGIC_VECTOR(c_SFP_number-1 DOWNTO 0) := (others => '0');
SIGNAL BN_SFP_SCL : STD_LOGIC_VECTOR(c_SFP_number-1 DOWNTO 0);
SIGNAL BN_SFP_SDA : STD_LOGIC_VECTOR(c_SFP_number-1 DOWNTO 0) := (others => '0');
BEGIN
----------------------------------------------------------------------------
......@@ -137,7 +147,8 @@ BEGIN
g_sim => c_sim,
g_sim_unb_nr => c_unb_nr,
g_sim_node_nr => c_node_nr,
g_design_name => g_design_name
g_design_name => g_design_name,
g_SFP_number => c_SFP_number
)
PORT MAP (
-- GENERAL
......@@ -158,7 +169,17 @@ BEGIN
-- 1GbE Control Interface
ETH_clk => eth_clk,
ETH_SGIN => eth_rxp,
ETH_SGOUT => eth_txp
ETH_SGOUT => eth_txp,
-- OCB Interface
BN_SFP_RX => BN_SFP_RX ,
BN_SFP_TX => BN_SFP_TX ,
BN_SFP_RXLOS => BN_SFP_RXLOS ,
BN_SFP_TXFAULT => BN_SFP_TXFAULT ,
BN_SFP_TXDISABL => BN_SFP_TXDISABL ,
BN_SFP_PRS => BN_SFP_PRS ,
BN_SFP_SCL => BN_SFP_SCL ,
BN_SFP_SDA => BN_SFP_SDA
);
------------------------------------------------------------------------------
......
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