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Commit 0b9ea0ba authored by Reinier van der Walle's avatar Reinier van der Walle
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Some quartus error fixes

parent 379b4ad2
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2 merge requests!100Removed text for XSub that is now written in Confluence Subband correlator...,!65Resolve L2SDP-190
...@@ -55,8 +55,8 @@ ...@@ -55,8 +55,8 @@
<interface name="board" port="kernel_stream_snk_10GbE_ring_7" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_7"/> <interface name="board" port="kernel_stream_snk_10GbE_ring_7" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_7"/>
<!-- IO channel from/to design --> <!-- IO channel from/to design -->
<interface name="board" port="kernel_stream_src_lane" type="streamsource" width="72" chan_id="kernel_input_to_lane"/> <interface name="board" port="kernel_stream_src_lane" type="streamsource" width="72" chan_id="kernel_input_lane"/>
<interface name="board" port="kernel_stream_snk_lane" type="streamsink" width="72" chan_id="kernel_output_from_lane"/> <interface name="board" port="kernel_stream_snk_lane" type="streamsink" width="72" chan_id="kernel_output_lane"/>
<interface name="board" port="kernel_stream_src_mm_io" type="streamsource" width="72" chan_id="kernel_input_mm"/> <interface name="board" port="kernel_stream_src_mm_io" type="streamsource" width="72" chan_id="kernel_input_mm"/>
<interface name="board" port="kernel_stream_snk_mm_io" type="streamsink" width="32" chan_id="kernel_output_mm"/> <interface name="board" port="kernel_stream_snk_mm_io" type="streamsink" width="32" chan_id="kernel_output_mm"/>
......
...@@ -287,8 +287,8 @@ set_instance_assignment -name IO_STANDARD LVDS -to BCK_REF_CLK ...@@ -287,8 +287,8 @@ set_instance_assignment -name IO_STANDARD LVDS -to BCK_REF_CLK
set_instance_assignment -name IO_STANDARD LVDS -to "BCK_REF_CLK(n)" set_instance_assignment -name IO_STANDARD LVDS -to "BCK_REF_CLK(n)"
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
### COMMENT OUT UNUSED LANES
### QSFP_0 ### LANE 0, 1
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[0] set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[0]
set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[0] set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[0]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[0] set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[0]
...@@ -311,103 +311,6 @@ set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to ...@@ -311,103 +311,6 @@ set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[0] set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[0]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[0] set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[0]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[1]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[1]
set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[1]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[1]
set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[1]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[1]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[1]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[2]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[2]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[2]
set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[2]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[2]
set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[2]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[2]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[2]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[3]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[3]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[3]
set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[3]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[3]
set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[3]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[3]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[3]
## QSFP_0_RX
set_location_assignment PIN_AN38 -to QSFP_0_RX[0]
set_location_assignment PIN_AM40 -to QSFP_0_RX[1]
set_location_assignment PIN_AK40 -to QSFP_0_RX[2]
set_location_assignment PIN_AJ38 -to QSFP_0_RX[3]
#
## QSFP_0_TX
set_location_assignment PIN_AN42 -to QSFP_0_TX[0]
set_location_assignment PIN_AM44 -to QSFP_0_TX[1]
set_location_assignment PIN_AK44 -to QSFP_0_TX[2]
set_location_assignment PIN_AJ42 -to QSFP_0_TX[3]
## RING
set_location_assignment PIN_AP40 -to RING_0_RX[0]
set_location_assignment PIN_AR38 -to RING_0_RX[1]
set_location_assignment PIN_AT40 -to RING_0_RX[2]
set_location_assignment PIN_AU38 -to RING_0_RX[3]
set_location_assignment PIN_AP44 -to RING_0_TX[0]
set_location_assignment PIN_AR42 -to RING_0_TX[1]
set_location_assignment PIN_AT44 -to RING_0_TX[2]
set_location_assignment PIN_AU42 -to RING_0_TX[3]
set_location_assignment PIN_H40 -to RING_1_RX[0]
set_location_assignment PIN_J38 -to RING_1_RX[1]
set_location_assignment PIN_F40 -to RING_1_RX[2]
set_location_assignment PIN_G38 -to RING_1_RX[3]
set_location_assignment PIN_H44 -to RING_1_TX[0]
set_location_assignment PIN_J42 -to RING_1_TX[1]
set_location_assignment PIN_G42 -to RING_1_TX[2]
set_location_assignment PIN_F44 -to RING_1_TX[3]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[0] set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[0]
set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[0] set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[0]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[0] set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[0]
...@@ -423,51 +326,12 @@ set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to ...@@ -423,51 +326,12 @@ set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[0] set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[0]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[0] set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[0]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[1] set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[0]
set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[1] set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[0]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[1] set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[0]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[1] set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[0]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[1] set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[0]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[1] set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[0]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[1]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[1]
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[1]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[1]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[2]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[2]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[3]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[3]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[0] set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[0]
...@@ -485,52 +349,6 @@ set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to ...@@ -485,52 +349,6 @@ set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[0] set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[0]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[0] set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[0]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[1]
set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[1]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[1]
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[1]
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[1]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[1]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[2]
set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[2]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[2]
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[2]
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[2]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[2]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[3]
set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[3]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[3]
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[3]
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[3]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[3]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[0] set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[0]
set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[0] set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[0]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[0] set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[0]
...@@ -538,57 +356,242 @@ set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to ...@@ -538,57 +356,242 @@ set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[0] set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[0]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[0] set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[0]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[1]
set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[1]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[1]
set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[1]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[1]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[1]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[2]
set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[2]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[2]
set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[2]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[2]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[2]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[3] #### LANE 2, 3
set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[3] #set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[3] #set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[3] #set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[3] #set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[3] #set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[1]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[0] #set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[0] #set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[0] #set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[0] #set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[0] #set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[1]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[0] #set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[1]
#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[1]
#
#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[1]
#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[1]
#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[1]
#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[1]
#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[1]
#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[1]
#
#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[1]
#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[1]
#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[1]
#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[1]
#
#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[1]
#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[1]
#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[1]
#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[1]
#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[1]
#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[1]
#
#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[1]
#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[1]
#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[1]
#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[1]
#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[1]
#
#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[1]
#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[1]
#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[1]
#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[1]
#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[1]
#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[1]
#
#
#### LANE 4, 5
#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[2]
#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[2]
#
#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[2]
#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[2]
#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[2]
#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[2]
#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[2]
#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[2]
#
#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[2]
#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[2]
#
#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[2]
#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[2]
#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[2]
#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[2]
#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[2]
#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[2]
#
#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[2]
#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[2]
#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[2]
#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[2]
#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[2]
#
#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[2]
#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[2]
#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[2]
#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[2]
#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[2]
#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[2]
#
#
#### LANE 6,7
#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[3]
#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[3]
#
#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[3]
#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[3]
#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[3]
#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[3]
#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[3]
#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[3]
#
#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[3]
#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[3]
#
#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[3]
#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[3]
#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[3]
#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[3]
#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[3]
#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[3]
#
#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[3]
#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[3]
#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[3]
#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[3]
#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[3]
#
#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[3]
#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[3]
#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[3]
#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[3]
#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[3]
#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[3]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[1]
set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[1]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[1]
set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[1]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[1]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[1]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[2]
set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[2]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[2]
set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[2]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[2]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[2]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[3]
set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[3]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[3]
set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[3]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[3]
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[3]
## QSFP_0_RX
set_location_assignment PIN_AN38 -to QSFP_0_RX[0]
set_location_assignment PIN_AM40 -to QSFP_0_RX[1]
set_location_assignment PIN_AK40 -to QSFP_0_RX[2]
set_location_assignment PIN_AJ38 -to QSFP_0_RX[3]
#
## QSFP_0_TX
set_location_assignment PIN_AN42 -to QSFP_0_TX[0]
set_location_assignment PIN_AM44 -to QSFP_0_TX[1]
set_location_assignment PIN_AK44 -to QSFP_0_TX[2]
set_location_assignment PIN_AJ42 -to QSFP_0_TX[3]
## RING
set_location_assignment PIN_AP40 -to RING_0_RX[0]
set_location_assignment PIN_AR38 -to RING_0_RX[1]
set_location_assignment PIN_AT40 -to RING_0_RX[2]
set_location_assignment PIN_AU38 -to RING_0_RX[3]
set_location_assignment PIN_AP44 -to RING_0_TX[0]
set_location_assignment PIN_AR42 -to RING_0_TX[1]
set_location_assignment PIN_AT44 -to RING_0_TX[2]
set_location_assignment PIN_AU42 -to RING_0_TX[3]
set_location_assignment PIN_H40 -to RING_1_RX[0]
set_location_assignment PIN_J38 -to RING_1_RX[1]
set_location_assignment PIN_F40 -to RING_1_RX[2]
set_location_assignment PIN_G38 -to RING_1_RX[3]
set_location_assignment PIN_H44 -to RING_1_TX[0]
set_location_assignment PIN_J42 -to RING_1_TX[1]
set_location_assignment PIN_G42 -to RING_1_TX[2]
set_location_assignment PIN_F44 -to RING_1_TX[3]
...@@ -115,13 +115,9 @@ ARCHITECTURE str OF top IS ...@@ -115,13 +115,9 @@ ARCHITECTURE str OF top IS
CONSTANT c_ring_bus_w : NATURAL := c_unb2b_board_tr_ring.bus_w; CONSTANT c_ring_bus_w : NATURAL := c_unb2b_board_tr_ring.bus_w;
CONSTANT c_nof_streams_ring : NATURAL := c_unb2b_board_tr_ring.bus_w*c_nof_ring_bus; CONSTANT c_nof_streams_ring : NATURAL := c_unb2b_board_tr_ring.bus_w*c_nof_ring_bus;
CONSTANT c_nof_even_ring_lanes : NATURAL := ceil_div(g_nof_lanes, 2);
CONSTANT c_nof_odd_ring_lanes : NATURAL := g_nof_lanes/2;
CONSTANT c_nof_qsfp_lanes : NATURAL := c_nof_even_ring_lanes;
-- 10GbE -- 10GbE
CONSTANT c_nof_10GbE_ring_IP : NATURAL := c_nof_even_ring_lanes+c_nof_odd_ring_lanes; CONSTANT c_nof_10GbE_ring_IP : NATURAL := 2*ceil_div(g_nof_lanes, 2);
CONSTANT c_nof_10GbE_qsfp_IP : NATURAL := c_nof_qsfp_lanes; CONSTANT c_nof_10GbE_qsfp_IP : NATURAL := ceil_div(g_nof_lanes, 2);
-- Firmware version x.y -- Firmware version x.y
CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1); CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
...@@ -268,6 +264,10 @@ ARCHITECTURE str OF top IS ...@@ -268,6 +264,10 @@ ARCHITECTURE str OF top IS
SIGNAL board_kernel_register_mem_writedata : std_logic_vector(255 downto 0) := (others => '0'); -- writedata SIGNAL board_kernel_register_mem_writedata : std_logic_vector(255 downto 0) := (others => '0'); -- writedata
SIGNAL board_kernel_register_mem_byteenable : std_logic_vector(31 downto 0) := (others => '0'); -- byteenable SIGNAL board_kernel_register_mem_byteenable : std_logic_vector(31 downto 0) := (others => '0'); -- byteenable
SIGNAL ta2_unb2b_10GbE_ring_ch_src_out_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL ta2_unb2b_10GbE_ring_ch_src_in_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
SIGNAL ta2_unb2b_10GbE_ring_ch_snk_out_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
SIGNAL ta2_unb2b_10GbE_ring_ch_snk_in_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL ta2_unb2b_10GbE_ring_src_out_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); SIGNAL ta2_unb2b_10GbE_ring_src_out_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL ta2_unb2b_10GbE_ring_src_in_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst); SIGNAL ta2_unb2b_10GbE_ring_src_in_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
SIGNAL ta2_unb2b_10GbE_ring_snk_out_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst); SIGNAL ta2_unb2b_10GbE_ring_snk_out_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
...@@ -279,8 +279,6 @@ ARCHITECTURE str OF top IS ...@@ -279,8 +279,6 @@ ARCHITECTURE str OF top IS
SIGNAL ta2_unb2b_10GbE_qsfp_src_in_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst); SIGNAL ta2_unb2b_10GbE_qsfp_src_in_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
SIGNAL ta2_unb2b_10GbE_qsfp_snk_out_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst); SIGNAL ta2_unb2b_10GbE_qsfp_snk_out_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
SIGNAL ta2_unb2b_10GbE_qsfp_snk_in_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); SIGNAL ta2_unb2b_10GbE_qsfp_snk_in_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL ta2_unb2b_10GbE_qsfp_tx_serial_r : STD_LOGIC_VECTOR(c_nof_streams_qsfp -1 DOWNTO 0);
SIGNAL ta2_unb2b_10GbE_qsfp_rx_serial_r : STD_LOGIC_VECTOR(c_nof_streams_qsfp -1 DOWNTO 0);
SIGNAL ta2_unb2b_mm_io_snk_in : t_dp_sosi; SIGNAL ta2_unb2b_mm_io_snk_in : t_dp_sosi;
SIGNAL ta2_unb2b_mm_io_snk_out : t_dp_siso; SIGNAL ta2_unb2b_mm_io_snk_out : t_dp_siso;
...@@ -377,17 +375,14 @@ BEGIN ...@@ -377,17 +375,14 @@ BEGIN
---------- ----------
-- 10GbE -- 10GbE
---------- ----------
-- ring lanes in positive direction (to the right) -- Map [0,0; 0,1; 0,2; 0,3; 1,0; 1,1; 1,2; 1,3] -> [0,0; 1,0; 0,1; 1,1; 0,2; 1,2; 0,3; 1,3]
gen_even_lanes : FOR I IN 0 TO c_nof_even_ring_lanes-1 GENERATE gen_ring_lanes : FOR I IN 0 TO c_nof_streams_ring/2 -1 GENERATE
unb2b_board_ring_io_serial_tx_arr(I+c_ring_bus_w) <= ta2_unb2b_10GbE_ring_tx_serial_r(I*2); -- TX[0,2,4,6] -> RING_TX1[0,1,2,3] ta2_unb2b_10GbE_ring_rx_serial_r(I*2) <= unb2b_board_ring_io_serial_rx_arr(I);
ta2_unb2b_10GbE_ring_rx_serial_r(I*2) <= unb2b_board_ring_io_serial_rx_arr(I); -- RING_RX0[0,1,2,3] -> RX[0,2,4,6] ta2_unb2b_10GbE_ring_rx_serial_r(I*2 +1) <= unb2b_board_ring_io_serial_rx_arr(I+c_ring_bus_w);
unb2b_board_ring_io_serial_tx_arr(I) <= ta2_unb2b_10GbE_ring_tx_serial_r(I*2);
unb2b_board_ring_io_serial_tx_arr(I+c_ring_bus_w) <= ta2_unb2b_10GbE_ring_tx_serial_r(I*2 +1);
END GENERATE; END GENERATE;
-- ring lanes in negative direction (to the left)
gen_odd_lanes : FOR I IN 0 TO c_nof_odd_ring_lanes-1 GENERATE
unb2b_board_ring_io_serial_tx_arr(I) <= ta2_unb2b_10GbE_ring_tx_serial_r(1+I*2); -- TX[1,3,5,7] -> RING_TX0[0,1,2,3]
ta2_unb2b_10GbE_ring_rx_serial_r(1+I*2) <= unb2b_board_ring_io_serial_rx_arr(I); -- RINGRX1[0,1,2,3] -> RX[1,3,5,7]
END GENERATE;
-- tr_10GbE for RING -- tr_10GbE for RING
u_ta2_unb2b_10GbE_ring : ENTITY ta2_unb2b_10GbE_lib.ta2_unb2b_10GbE u_ta2_unb2b_10GbE_ring : ENTITY ta2_unb2b_10GbE_lib.ta2_unb2b_10GbE
...@@ -412,12 +407,17 @@ BEGIN ...@@ -412,12 +407,17 @@ BEGIN
snk_in_arr => ta2_unb2b_10GbE_ring_snk_in_arr(c_nof_10GbE_ring_IP-1 DOWNTO 0) snk_in_arr => ta2_unb2b_10GbE_ring_snk_in_arr(c_nof_10GbE_ring_IP-1 DOWNTO 0)
); );
-- Map to kernel channel, swapping every two elements of the sink.
ta2_unb2b_10GbE_ring_ch_src_out_arr <= ta2_unb2b_10GbE_ring_src_out_arr;
ta2_unb2b_10GbE_ring_src_in_arr <= ta2_unb2b_10GbE_ring_ch_src_in_arr
gen_ring_ch : FOR I IN 0 TO c_nof_streams/2 -1 GENERATE
ta2_unb2b_10GbE_ring_snk_in_arr(2*I) <= ta2_unb2b_10GbE_ring_ch_snk_in_arr(2*I+1);
ta2_unb2b_10GbE_ring_snk_in_arr(2*I+1) <= ta2_unb2b_10GbE_ring_ch_snk_in_arr(2*I);
ta2_unb2b_10GbE_ring_ch_snk_out_arr(2*I+1) <= ta2_unb2b_10GbE_ring_snk_in_arr(2*I);
ta2_unb2b_10GbE_ring_ch_snk_out_arr(2*I) <= ta2_unb2b_10GbE_ring_snk_in_arr(2*I+1);
END GENERATE;
-- Front QSFP 0 RX/TX 10GbE Interface -- Front QSFP 0 RX/TX 10GbE Interface
gen_qsfp_lanes : FOR I IN 0 TO c_nof_qsfp_lanes-1 GENERATE
unb2b_board_front_io_serial_tx_arr(I) <= ta2_unb2b_10GbE_qsfp_tx_serial_r(I);
ta2_unb2b_10GbE_qsfp_rx_serial_r(I) <= unb2b_board_front_io_serial_rx_arr(I);
END GENERATE;
-- tr_10GbE for QSFP -- tr_10GbE for QSFP
u_ta2_unb2b_10GbE_qsfp : ENTITY ta2_unb2b_10GbE_lib.ta2_unb2b_10GbE u_ta2_unb2b_10GbE_qsfp : ENTITY ta2_unb2b_10GbE_lib.ta2_unb2b_10GbE
...@@ -430,8 +430,8 @@ BEGIN ...@@ -430,8 +430,8 @@ BEGIN
clk_ref_r => SA_CLK, clk_ref_r => SA_CLK,
tx_serial_r => ta2_unb2b_10GbE_qsfp_tx_serial_r(c_nof_10GbE_qsfp_IP-1 DOWNTO 0), tx_serial_r => unb2b_board_front_io_serial_tx_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0),
rx_serial_r => ta2_unb2b_10GbE_qsfp_rx_serial_r(c_nof_10GbE_qsfp_IP-1 DOWNTO 0), rx_serial_r => unb2b_board_front_io_serial_rx_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0),
kernel_clk => board_kernel_clk_clk, kernel_clk => board_kernel_clk_clk,
kernel_reset => i_kernel_rst, kernel_reset => i_kernel_rst,
...@@ -555,61 +555,61 @@ BEGIN ...@@ -555,61 +555,61 @@ BEGIN
board_kernel_register_mem_writedata => board_kernel_register_mem_writedata, board_kernel_register_mem_writedata => board_kernel_register_mem_writedata,
board_kernel_register_mem_byteenable => board_kernel_register_mem_byteenable, board_kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
board_kernel_stream_src_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_src_out_arr(0).data(71 DOWNTO 0), board_kernel_stream_src_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).data(71 DOWNTO 0),
board_kernel_stream_src_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_src_out_arr(0).valid, board_kernel_stream_src_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).valid,
board_kernel_stream_src_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_src_in_arr(0).ready, board_kernel_stream_src_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(0).ready,
board_kernel_stream_snk_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_snk_in_arr(0).data(71 DOWNTO 0), board_kernel_stream_snk_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).data(71 DOWNTO 0),
board_kernel_stream_snk_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_snk_in_arr(0).valid, board_kernel_stream_snk_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).valid,
board_kernel_stream_snk_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_snk_out_arr(0).ready, board_kernel_stream_snk_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(0).ready,
board_kernel_stream_src_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_src_out_arr(1).data(71 DOWNTO 0), board_kernel_stream_src_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).data(71 DOWNTO 0),
board_kernel_stream_src_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_src_out_arr(1).valid, board_kernel_stream_src_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).valid,
board_kernel_stream_src_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_src_in_arr(1).ready, board_kernel_stream_src_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(1).ready,
board_kernel_stream_snk_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_snk_in_arr(1).data(71 DOWNTO 0), board_kernel_stream_snk_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).data(71 DOWNTO 0),
board_kernel_stream_snk_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_snk_in_arr(1).valid, board_kernel_stream_snk_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).valid,
board_kernel_stream_snk_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_snk_out_arr(1).ready, board_kernel_stream_snk_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(1).ready,
board_kernel_stream_src_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_src_out_arr(2).data(71 DOWNTO 0), board_kernel_stream_src_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).data(71 DOWNTO 0),
board_kernel_stream_src_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_src_out_arr(2).valid, board_kernel_stream_src_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).valid,
board_kernel_stream_src_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_src_in_arr(2).ready, board_kernel_stream_src_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(2).ready,
board_kernel_stream_snk_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_snk_in_arr(2).data(71 DOWNTO 0), board_kernel_stream_snk_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).data(71 DOWNTO 0),
board_kernel_stream_snk_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_snk_in_arr(2).valid, board_kernel_stream_snk_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).valid,
board_kernel_stream_snk_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_snk_out_arr(2).ready, board_kernel_stream_snk_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(2).ready,
board_kernel_stream_src_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_src_out_arr(3).data(71 DOWNTO 0), board_kernel_stream_src_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).data(71 DOWNTO 0),
board_kernel_stream_src_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_src_out_arr(3).valid, board_kernel_stream_src_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).valid,
board_kernel_stream_src_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_src_in_arr(3).ready, board_kernel_stream_src_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(3).ready,
board_kernel_stream_snk_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_snk_in_arr(3).data(71 DOWNTO 0), board_kernel_stream_snk_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).data(71 DOWNTO 0),
board_kernel_stream_snk_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_snk_in_arr(3).valid, board_kernel_stream_snk_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).valid,
board_kernel_stream_snk_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_snk_out_arr(3).ready, board_kernel_stream_snk_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(3).ready,
board_kernel_stream_src_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_src_out_arr(4).data(71 DOWNTO 0), board_kernel_stream_src_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).data(71 DOWNTO 0),
board_kernel_stream_src_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_src_out_arr(4).valid, board_kernel_stream_src_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).valid,
board_kernel_stream_src_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_src_in_arr(4).ready, board_kernel_stream_src_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(4).ready,
board_kernel_stream_snk_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_snk_in_arr(4).data(71 DOWNTO 0), board_kernel_stream_snk_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).data(71 DOWNTO 0),
board_kernel_stream_snk_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_snk_in_arr(4).valid, board_kernel_stream_snk_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).valid,
board_kernel_stream_snk_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_snk_out_arr(4).ready, board_kernel_stream_snk_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(4).ready,
board_kernel_stream_src_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_src_out_arr(5).data(71 DOWNTO 0), board_kernel_stream_src_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).data(71 DOWNTO 0),
board_kernel_stream_src_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_src_out_arr(5).valid, board_kernel_stream_src_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).valid,
board_kernel_stream_src_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_src_in_arr(5).ready, board_kernel_stream_src_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(5).ready,
board_kernel_stream_snk_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_snk_in_arr(5).data(71 DOWNTO 0), board_kernel_stream_snk_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).data(71 DOWNTO 0),
board_kernel_stream_snk_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_snk_in_arr(5).valid, board_kernel_stream_snk_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).valid,
board_kernel_stream_snk_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_snk_out_arr(5).ready, board_kernel_stream_snk_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(5).ready,
board_kernel_stream_src_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_src_out_arr(6).data(71 DOWNTO 0), board_kernel_stream_src_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).data(71 DOWNTO 0),
board_kernel_stream_src_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_src_out_arr(6).valid, board_kernel_stream_src_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).valid,
board_kernel_stream_src_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_src_in_arr(6).ready, board_kernel_stream_src_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(6).ready,
board_kernel_stream_snk_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_snk_in_arr(6).data(71 DOWNTO 0), board_kernel_stream_snk_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).data(71 DOWNTO 0),
board_kernel_stream_snk_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_snk_in_arr(6).valid, board_kernel_stream_snk_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).valid,
board_kernel_stream_snk_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_snk_out_arr(6).ready, board_kernel_stream_snk_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(6).ready,
board_kernel_stream_src_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_src_out_arr(7).data(71 DOWNTO 0), board_kernel_stream_src_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).data(71 DOWNTO 0),
board_kernel_stream_src_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_src_out_arr(7).valid, board_kernel_stream_src_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).valid,
board_kernel_stream_src_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_src_in_arr(7).ready, board_kernel_stream_src_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(7).ready,
board_kernel_stream_snk_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_snk_in_arr(7).data(71 DOWNTO 0), board_kernel_stream_snk_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).data(71 DOWNTO 0),
board_kernel_stream_snk_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_snk_in_arr(7).valid, board_kernel_stream_snk_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).valid,
board_kernel_stream_snk_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_snk_out_arr(7).ready, board_kernel_stream_snk_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(7).ready,
board_kernel_stream_src_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_src_out_arr(0).data(71 DOWNTO 0), board_kernel_stream_src_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_src_out_arr(0).data(71 DOWNTO 0),
board_kernel_stream_src_10GbE_qsfp_0_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(0).valid, board_kernel_stream_src_10GbE_qsfp_0_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(0).valid,
......
...@@ -216,7 +216,7 @@ BEGIN ...@@ -216,7 +216,7 @@ BEGIN
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Reverse byte order -- Reverse byte order
gen_reverse_rx_bytes : IF g_reverse_bytes GENERATE gen_reverse_rx_bytes : IF g_reverse_bytes GENERATE
gen_rx_bytes: FOR I IN 0 TO g_nof_bytes GENERATE gen_rx_bytes: FOR I IN 0 TO g_nof_bytes-1 GENERATE
dp_src_out_arr(stream).data(c_byte_w*(g_nof_bytes-I) -1 DOWNTO c_byte_w*(g_nof_bytes-1-I)) <= dp_fifo_dc_rx_src_out_arr(stream).data(c_byte_w*(I+1)-1 DOWNTO c_byte_w*I); dp_src_out_arr(stream).data(c_byte_w*(g_nof_bytes-I) -1 DOWNTO c_byte_w*(g_nof_bytes-1-I)) <= dp_fifo_dc_rx_src_out_arr(stream).data(c_byte_w*(I+1)-1 DOWNTO c_byte_w*I);
END GENERATE; END GENERATE;
END GENERATE; END GENERATE;
...@@ -229,8 +229,8 @@ BEGIN ...@@ -229,8 +229,8 @@ BEGIN
dp_src_out_arr(stream).data(g_nof_bytes*c_byte_w+1) <= dp_fifo_dc_rx_src_out_arr(stream).eop; dp_src_out_arr(stream).data(g_nof_bytes*c_byte_w+1) <= dp_fifo_dc_rx_src_out_arr(stream).eop;
dp_src_out_arr(stream).data(c_byte_w*(g_nof_bytes+1)-1 DOWNTO c_byte_w*(g_nof_bytes+1)-c_empty_w) <= dp_fifo_dc_rx_src_out_arr(stream).empty(c_empty_w-1 DOWNTO 0); dp_src_out_arr(stream).data(c_byte_w*(g_nof_bytes+1)-1 DOWNTO c_byte_w*(g_nof_bytes+1)-c_empty_w) <= dp_fifo_dc_rx_src_out_arr(stream).empty(c_empty_w-1 DOWNTO 0);
dp_src_out_arr(stream).valid <= dp_fifo_dc_rx_src_out_arr(stream).valid; dp_src_out_arr(stream).valid <= dp_fifo_dc_rx_src_out_arr(stream).valid;
dp_latency_adapter_rx_src_in_arr(stream).ready <= dp_src_in_arr(stream).ready; dp_fifo_dc_rx_src_in_arr(stream).ready <= dp_src_in_arr(stream).ready;
dp_latency_adapter_rx_src_in_arr(stream).xon <= '1'; dp_fifo_dc_rx_src_in_arr(stream).xon <= '1';
END GENERATE; END GENERATE;
END str; END str;
......
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