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Commit 07e454c2 authored by Reinier van der Walle's avatar Reinier van der Walle
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1 merge request!351added icrc checksum implementation from SKA and added testbench for rdma
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-------------------------------------------------------------------------------
-- Title : Wrapper for a simple dual port RAM
-- Project : CSP
-------------------------------------------------------------------------------
-- File : sdp_ram_ent.vhd
-- Author : William Kamp <william.kamp@aut.ac.nz>
-- Company :
-- Created : 2015-10-01
-- Last update: 2015-10-08
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Entity declaration for a Simple Dual Port RAM.
-- Needs to be attached to an appropriate architecture that implements it for a
-- particular family of chips.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-10-06 1.0 wkamp Created
--
-- Copyright 2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-------------------------------------------------------------------------------
-- Author: R. van der Walle
-- Purpose: Wrapper for a simple dual port RAM
library ieee;
use ieee.std_logic_1164.all;
......
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