Skip to content
GitLab
Explore
Sign in
Register
Open
0
Merged
426
Closed
31
All
457
Recent searches
{{formattedKey}}
{{ title }}
{{ help }}
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
{{name}}
@{{username}}
None
Any
Upcoming
Started
{{title}}
None
Any
{{title}}
None
Any
{{title}}
None
Any
{{name}}
Yes
No
Yes
No
{{title}}
{{title}}
{{title}}
Created date
Use default 0 for nxt_info to avoid X to decimal conversion error in sim_io.py...
hdl!292
· created
Nov 17, 2022
by
Eric Kooistra
Merged
updated
Nov 17, 2022
Resolve L2SDP-861
hdl!291
· created
Nov 14, 2022
by
Reinier van der Walle
Merged
updated
Nov 14, 2022
added 16G ddr4 IP and created example design.
hdl!290
· created
Nov 07, 2022
by
Reinier van der Walle
Merged
updated
Nov 09, 2022
Rename c_sdp_W_fsub_wg into c_sdp_W_local_oscillator. Use...
hdl!289
· created
Nov 03, 2022
by
Eric Kooistra
Merged
updated
Nov 09, 2022
Resolve L2SDP-836
hdl!288
· created
Nov 01, 2022
by
Eric Kooistra
Merged
2
updated
Nov 01, 2022
added valid_arp signal
hdl!287
· created
Oct 19, 2022
by
Reinier van der Walle
Merged
2
updated
Oct 20, 2022
Clarified flipped order of FIR coefficients in PFB.
apertif_matlab!1
· created
Oct 19, 2022
by
Eric Kooistra
Merged
2
updated
Oct 20, 2022
Added tb_verify_pfb_response.vhd to read FIR coefficients from PFB.
hdl!286
· created
Oct 19, 2022
by
Eric Kooistra
Merged
updated
Oct 19, 2022
Resolve L2SDP-840
hdl!285
· created
Oct 13, 2022
by
Eric Kooistra
Merged
updated
Oct 17, 2022
Resolve L2SDP-832
hdl!284
· created
Oct 12, 2022
by
Eric Kooistra
Merged
updated
Oct 12, 2022
Resolve L2SDP-696
hdl!283
· created
Oct 05, 2022
by
Eric Kooistra
Merged
updated
Oct 05, 2022
Increase total_block_count in dp_block_validate_err from 32b to 64b MM field.
hdl!282
· created
Sep 28, 2022
by
Eric Kooistra
Merged
2
updated
Sep 29, 2022
Use block counts at sync for MM read..
hdl!281
· created
Sep 28, 2022
by
Eric Kooistra
Merged
updated
Sep 28, 2022
Use g_try_xst_restart = FALSE to verify nof_cycles_dly +1 to ensure proper...
hdl!280
· created
Sep 23, 2022
by
Eric Kooistra
Merged
updated
Sep 23, 2022
Improve debugging common_reg_r_w.vhd.
hdl!279
· created
Sep 15, 2022
by
Eric Kooistra
Merged
updated
Sep 15, 2022
Resolve L2SDP-811
hdl!278
· created
Sep 06, 2022
by
Eric Kooistra
Merged
updated
Sep 06, 2022
Resolve L2SDP-794
radiohdl!11
· created
Sep 01, 2022
by
Reinier van der Walle
Merged
3
updated
Sep 02, 2022
added synthesis script
radiohdl!10
· created
Aug 30, 2022
by
Reinier van der Walle
Merged
2
updated
Aug 30, 2022
Resolve DIST2-2
hdl!277
· created
Aug 29, 2022
by
Reinier van der Walle
Merged
27
updated
Aug 30, 2022
Resolve DISTURB-2
hdl!276
· created
Aug 29, 2022
by
Reinier van der Walle
Closed
updated
Aug 29, 2022
Prev
1
…
4
5
6
7
8
9
10
11
12
…
23
Next