------------------------------------------------------------------------------- -- -- Copyright (C) 2014 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> -- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/> -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- ------------------------------------------------------------------------------- -- Purpose: IP components declarations for various devices that get wrapped by the tech components LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; PACKAGE tech_ddr_mem_model_component_pkg IS ------------------------------------------------------------------------------ -- ip_stratixiv ------------------------------------------------------------------------------ -- Manually derived VHDL entity from Verilog module alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv in: -- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation/vhdl/submodules/ COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en IS GENERIC ( MEM_IF_CLK_EN_WIDTH : INTEGER := 1; MEM_IF_CK_WIDTH : INTEGER := 1; MEM_IF_BANKADDR_WIDTH : INTEGER := 3; MEM_IF_ADDR_WIDTH : INTEGER := 15; MEM_IF_ROW_ADDR_WIDTH : INTEGER := 15; MEM_IF_COL_ADDR_WIDTH : INTEGER := 10; MEM_IF_CS_WIDTH : INTEGER := 1; MEM_IF_CONTROL_WIDTH : INTEGER := 1; MEM_IF_ODT_WIDTH : INTEGER := 1; DEVICE_DEPTH : INTEGER := 1; DEVICE_WIDTH : INTEGER := 1; MEM_IF_CS_PER_RANK : INTEGER := 1; MEM_IF_DQS_WIDTH : INTEGER := 1; MEM_IF_DQ_WIDTH : INTEGER := 8; MEM_MIRROR_ADDRESSING_DEC : INTEGER := 0; MEM_TRTP : INTEGER := 8; MEM_TRCD : INTEGER := 8; MEM_DQS_TO_CLK_CAPTURE_DELAY : INTEGER := 100; MEM_CLK_TO_DQS_CAPTURE_DELAY : INTEGER := 100000; MEM_REGDIMM_ENABLED : INTEGER := 0; MEM_INIT_EN : INTEGER := 0; MEM_INIT_FILE : STRING := ""; MEM_GUARANTEED_WRITE_INIT : INTEGER := 0; DAT_DATA_WIDTH : INTEGER := 32; MEM_VERBOSE : INTEGER := 1 ); PORT ( mem_a : IN STD_LOGIC_VECTOR(MEM_IF_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); mem_ba : IN STD_LOGIC_VECTOR(MEM_IF_BANKADDR_WIDTH-1 DOWNTO 0):= (OTHERS=>'X'); mem_ck : IN STD_LOGIC_VECTOR(MEM_IF_CK_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); mem_ck_n : IN STD_LOGIC_VECTOR(MEM_IF_CK_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); mem_cke : IN STD_LOGIC_VECTOR(MEM_IF_CLK_EN_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); mem_cs_n : IN STD_LOGIC_VECTOR(MEM_IF_CS_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); mem_ras_n : IN STD_LOGIC_VECTOR(MEM_IF_CONTROL_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); mem_cas_n : IN STD_LOGIC_VECTOR(MEM_IF_CONTROL_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); mem_we_n : IN STD_LOGIC_VECTOR(MEM_IF_CONTROL_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); mem_reset_n: IN STD_LOGIC := 'X'; mem_dm : IN STD_LOGIC_VECTOR(MEM_IF_DQS_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); mem_dq : INOUT STD_LOGIC_VECTOR(MEM_IF_DQ_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); mem_dqs : INOUT STD_LOGIC_VECTOR(MEM_IF_DQS_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); mem_dqs_n : INOUT STD_LOGIC_VECTOR(MEM_IF_DQS_WIDTH-1 DOWNTO 0) := (OTHERS=>'X'); mem_odt : IN STD_LOGIC_VECTOR(MEM_IF_ODT_WIDTH-1 DOWNTO 0) := (OTHERS=>'X') ); END COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en; ------------------------------------------------------------------------------ -- ip_arria10 ------------------------------------------------------------------------------ -- Manually derived VHDL entity from ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd in: -- $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/sim COMPONENT ed_sim_altera_emif_mem_model_141_z3tvrmq IS PORT ( mem_ck : in std_logic_vector(0 downto 0) := (others => '0'); -- mem_conduit_end.mem_ck mem_ck_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_ck_n mem_a : in std_logic_vector(16 downto 0) := (others => '0'); -- .mem_a mem_act_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_act_n mem_ba : in std_logic_vector(1 downto 0) := (others => '0'); -- .mem_ba mem_bg : in std_logic_vector(1 downto 0) := (others => '0'); -- .mem_bg mem_cke : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_cke mem_cs_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_cs_n mem_odt : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_odt mem_reset_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_reset_n mem_par : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_par mem_alert_n : out std_logic_vector(0 downto 0); -- .mem_alert_n mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0') -- .mem_dbi_n ); END COMPONENT ed_sim_altera_emif_mem_model_141_z3tvrmq; END tech_ddr_mem_model_component_pkg; PACKAGE BODY tech_ddr_mem_model_component_pkg IS END tech_ddr_mem_model_component_pkg;