-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: IP components declarations for various devices that get wrapped by the tech components
LIBRARY IEEE, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE technology_lib.technology_pkg.ALL;
PACKAGE tech_transceiver_component_pkg IS
------------------------------------------------------------------------------
-- ip_stratixiv
------------------------------------------------------------------------------
COMPONENT ip_stratixiv_hssi_gx_32b_generic IS
GENERIC (
g_mbps : NATURAL;
starting_channel_number : NATURAL := 0
);
PORT (
cal_blk_clk : IN STD_LOGIC ;
gxb_powerdown : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
pll_inclk : IN STD_LOGIC ;
pll_powerdown : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
reconfig_clk : IN STD_LOGIC ;
reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rx_analogreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_enapatternalign : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_seriallpbken : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_ctrlenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
tx_datain : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
tx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
pll_locked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
reconfig_fromgxb : OUT STD_LOGIC_VECTOR (16 DOWNTO 0);
rx_byteorderalignstatus : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_ctrldetect : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
rx_dataout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
rx_disperr : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
rx_errdetect : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
rx_freqlocked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_patterndetect : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
COMPONENT ip_stratixiv_hssi_tx_32b_generic IS
GENERIC(
g_mbps : NATURAL
);
PORT (
cal_blk_clk : IN STD_LOGIC ;
gxb_powerdown : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
pll_inclk : IN STD_LOGIC ;
pll_powerdown : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_ctrlenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
tx_datain : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
tx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
pll_locked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
COMPONENT ip_stratixiv_hssi_rx_32b_generic IS
GENERIC (
g_mbps : NATURAL;
starting_channel_number : NATURAL := 0
);
PORT (
cal_blk_clk : IN STD_LOGIC ;
gxb_powerdown : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
reconfig_clk : IN STD_LOGIC ;
reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rx_analogreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_cruclk : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
rx_datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_enapatternalign : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
reconfig_fromgxb : OUT STD_LOGIC_VECTOR (16 DOWNTO 0);
rx_byteorderalignstatus : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_ctrldetect : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
rx_dataout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
rx_disperr : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
rx_errdetect : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
rx_freqlocked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_patterndetect : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
COMPONENT ip_stratixiv_hssi_gx_16b IS
GENERIC
(
starting_channel_number : NATURAL := 0
);
PORT
(
cal_blk_clk : IN STD_LOGIC ;
pll_inclk : IN STD_LOGIC ;
pll_powerdown : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
reconfig_clk : IN STD_LOGIC ;
reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rx_analogreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_ctrlenable : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
tx_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
tx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
pll_locked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
reconfig_fromgxb : OUT STD_LOGIC_VECTOR (16 DOWNTO 0);
rx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_ctrldetect : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
rx_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rx_freqlocked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
COMPONENT ip_stratixiv_hssi_tx_16b IS
PORT
(
cal_blk_clk : IN STD_LOGIC ;
pll_inclk : IN STD_LOGIC ;
pll_powerdown : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_ctrlenable : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
tx_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
tx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
pll_locked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
COMPONENT ip_stratixiv_hssi_rx_16b IS
GENERIC
(
starting_channel_number : NATURAL := 0
);
PORT
(
cal_blk_clk : IN STD_LOGIC ;
reconfig_clk : IN STD_LOGIC ;
reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rx_analogreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_cruclk : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
rx_datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
reconfig_fromgxb : OUT STD_LOGIC_VECTOR (16 DOWNTO 0);
rx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_ctrldetect : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
rx_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rx_freqlocked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
COMPONENT ip_stratixiv_gxb_reconfig_v91 IS
GENERIC (
g_nof_gx : NATURAL;
g_fromgxb_bus_w : NATURAL := 17;
g_togxb_bus_w : NATURAL := 4
);
PORT (
reconfig_clk : IN STD_LOGIC;
reconfig_fromgxb : IN STD_LOGIC_VECTOR(g_nof_gx*g_fromgxb_bus_w-1 DOWNTO 0);
busy : OUT STD_LOGIC;
reconfig_togxb : OUT STD_LOGIC_VECTOR(g_togxb_bus_w-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT ip_stratixiv_gxb_reconfig_v111 IS
GENERIC (
g_soft : BOOLEAN := FALSE;
g_nof_gx : NATURAL;
g_fromgxb_bus_w : NATURAL := 17;
g_togxb_bus_w : NATURAL := 4
);
PORT (
reconfig_clk : IN STD_LOGIC;
reconfig_fromgxb : IN STD_LOGIC_VECTOR(tech_ceil_div(g_nof_gx, 4)*g_fromgxb_bus_w-1 DOWNTO 0);
busy : OUT STD_LOGIC;
reconfig_togxb : OUT STD_LOGIC_VECTOR(g_togxb_bus_w-1 DOWNTO 0)
);
END COMPONENT;
------------------------------------------------------------------------------
-- ip_arria10
------------------------------------------------------------------------------
END tech_transceiver_component_pkg;