-------------------------------------------------------------------------------
--
-- Copyright 2022
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-------------------------------------------------------------------------------
-- Author: Job van Wee
-- Purpose: Resize the input data vector so that the output data vector can be
-- stored into the ddr memory.
--
-- Description:
-- The input data gets resized and put into the output data vector.
--
-- Remark:
-- Use VHDL coding template from:
-- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
-- The output vector must be larger than the input vector.
LIBRARY IEEE, dp_lib, tech_ddr_lib;
USE IEEE.std_logic_1164.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY ddrctrl_input_repack IS
GENERIC (
g_tech_ddr : t_c_tech_ddr; -- type of memory
g_in_data_w : NATURAL := 168; -- the input data with
g_bim : NATURAL;
g_of_pb : NATURAL;
g_block_size : NATURAL
);
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
in_sosi : IN t_dp_sosi; -- input data
in_stop : IN STD_LOGIC := '0';
out_sosi : OUT t_dp_sosi := c_dp_sosi_init; -- output data
out_bsn_ds : OUT NATURAL := 0;
out_bsn_wr : OUT STD_LOGIC := '0';
out_data_stopped : OUT STD_LOGIC := '0'
);
END ddrctrl_input_repack;
ARCHITECTURE rtl OF ddrctrl_input_repack IS
-- constant for readability
CONSTANT c_out_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- the output data with, 576
CONSTANT k_c_v_w : NATURAL := c_out_data_w*2; -- the c_v data with, 2*576=1152
-- type for statemachine
TYPE t_state IS (OVERFLOW_OUTPUT, FILL_VECTOR, FIRST_OUTPUT, RESET, STOP, BSN);
-- record for readability
TYPE t_reg IS RECORD
state : t_state; -- the state the process is currently in;
c_v : STD_LOGIC_VECTOR(k_c_v_w-1 DOWNTO 0); -- the vector that stores the input data until the data is put into the output data vector
c_v_count : NATURAL; -- the amount of times the c_v vector received data from the input since the last time it was filled completely
a_of : NATURAL; -- this is the amount of bits that the first data word(168) is shifted from the first bit in the data word(576)
q_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
q_sop : STD_LOGIC;
q_out_bsn_ds : NATURAL;
s_input_cnt : NATURAL;
out_of : NATURAL;
out_data_count : STD_LOGIC; -- the amount of times the output data vector has been filled since the last time c_v was filled completely
out_sosi : t_dp_sosi; -- this is the sosi stream that contains the data
out_bsn_ds : NATURAL; -- this is the amount of bits that the data corresponding to out_bsn is shifted from the first bit in that data word
out_data_stopped : STD_LOGIC; -- this signal is '1' when there is no more data comming form ddrctrl_input_pack
END RECORD;
CONSTANT c_t_reg_init : t_reg := (RESET, (OTHERS => '0'), 0, 0, (OTHERS => '0'), '0', 0, 0, 0, '0', c_dp_sosi_init, 0, '0');
-- signals for readability
SIGNAL d_reg : t_reg := c_t_reg_init;
SIGNAL q_reg : t_reg := c_t_reg_init;
BEGIN
q_reg <= d_reg WHEN rising_edge(clk);
-- put the input data into c_v and fill the output vector from c_v
p_state : PROCESS(q_reg, rst, in_sosi, in_stop)
VARIABLE v : t_reg;
BEGIN
v := q_reg;
CASE q_reg.state IS
WHEN FILL_VECTOR => -- if the input data doesn't exceeds the output data vector width
v.c_v(g_in_data_w*(q_reg.c_v_count+1)+q_reg.out_of-1 DOWNTO g_in_data_w*q_reg.c_v_count+q_reg.out_of) := in_sosi.data(g_in_data_w-1 DOWNTO 0); -- fill c_v
v.c_v_count := q_reg.c_v_count+1; -- increase the counter of c_v with 1
v.out_sosi.valid := '0'; -- out_sosi.valid 0
v.s_input_cnt := q_reg.s_input_cnt+1;
v.out_sosi.sop := '0';
v.out_sosi.eop := '0';
v.out_data_stopped := '0';
IF rst = '1' THEN
v.state := RESET;
ELSIF in_stop = '1' OR in_sosi.valid = '0' THEN
v.state := STOP;
ELSIF ((g_in_data_w*(v.c_v_count+1))+v.out_of >= c_out_data_w*1) AND (v.out_data_count = '0') THEN
v.state := FIRST_OUTPUT;
ELSIF ((g_in_data_w*(v.c_v_count+1))+v.out_of >= c_out_data_w*2) AND (v.out_data_count = '1') THEN
v.state := OVERFLOW_OUTPUT;
ELSE
v.state := FILL_VECTOR;
END IF;
IF NOT (q_reg.q_bsn(c_dp_stream_bsn_w-1 DOWNTO 0) = in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0)) THEN
v.s_input_cnt := 0;
v.state := BSN;
END IF;
WHEN FIRST_OUTPUT => -- if the input data exceeds output data vector width but not the c_v width
v.c_v(g_in_data_w*(q_reg.c_v_count+1)+q_reg.out_of-1 DOWNTO g_in_data_w*q_reg.c_v_count+q_reg.out_of) := in_sosi.data(g_in_data_w-1 DOWNTO 0); -- fill c_v
v.c_v_count := q_reg.c_v_count+1; -- increase the counter of c_v with 1
v.out_sosi.data(c_out_data_w-1 DOWNTO 0) := v.c_v(c_out_data_w-1 DOWNTO 0); -- fill out_sosi.data with 1st part of c_v
v.out_sosi.valid := '1'; -- out_sosi.valid 1
v.out_data_count := '1'; -- increase the counter of out_sosi.data with 1
v.s_input_cnt := q_reg.s_input_cnt+1;
v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := q_reg.q_bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
v.out_bsn_ds := q_reg.q_out_bsn_ds;
v.out_sosi.sop := q_reg.q_sop;
v.out_sosi.eop := '0';
v.out_data_stopped := '0';
IF rst = '1' THEN
v.state := RESET;
ELSIF in_stop = '1' OR in_sosi.valid = '0' THEN
v.state := STOP;
ELSIF ((g_in_data_w*(v.c_v_count+1))+v.out_of >= c_out_data_w*2) THEN
v.state := OVERFLOW_OUTPUT;
ELSE
v.state := FILL_VECTOR;
END IF;
IF NOT (q_reg.q_bsn(c_dp_stream_bsn_w-1 DOWNTO 0) = in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0)) THEN
v.s_input_cnt := 0;
v.state := BSN;
END IF;
WHEN OVERFLOW_OUTPUT => -- if the input data exceeds the output data vector width and the c_v width
v.out_of := q_reg.out_of+(g_in_data_w*(q_reg.c_v_count+1))-(c_out_data_w*2); -- check how much overflow there is and safe it in out_of
v.c_v(k_c_v_w-1 DOWNTO k_c_v_w-(g_in_data_w-v.out_of)) := in_sosi.data(g_in_data_w-v.out_of-1 DOWNTO 0); -- fill the rest of c_v untill the end
v.c_v(v.out_of-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO g_in_data_w-v.out_of); -- fill the start of c_v untill the out_of
v.out_sosi.data(c_out_data_w-1 DOWNTO 0) := v.c_v(k_c_v_w-1 DOWNTO c_out_data_w); -- fill out_sosi.data with 2nd part of c_v
v.out_sosi.valid := '1'; -- out_sosi.valid 1
v.c_v_count := 0; -- reset counter
v.out_data_count := '0'; -- reset counter
v.s_input_cnt := q_reg.s_input_cnt+1;
v.q_sop := '0';
v.out_sosi.sop := '0';
v.out_sosi.eop := '0';
v.out_data_stopped := '0';
IF rst = '1' THEN
v.state := RESET;
ELSIF in_stop = '1' OR in_sosi.valid = '0' THEN
v.state := STOP;
ELSIF ((g_in_data_w*(v.c_v_count+1))+v.out_of >= c_out_data_w*1) THEN
v.state := FIRST_OUTPUT;
ELSE
v.state := FILL_VECTOR;
END IF;
IF NOT (q_reg.q_bsn(c_dp_stream_bsn_w-1 DOWNTO 0) = in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0)) THEN
v.s_input_cnt := 0;
v.state := BSN;
END IF;
WHEN BSN =>
v.c_v(k_c_v_w-1 DOWNTO ((g_in_data_w*q_reg.c_v_count)+q_reg.out_of)) := (OTHERS =>'0');
IF ((g_in_data_w*q_reg.c_v_count)+q_reg.out_of < c_out_data_w*1) THEN
v.out_sosi.data(c_out_data_w-1 DOWNTO 0) := v.c_v(c_out_data_w-1 DOWNTO 0); -- fill out_sosi.data with 1st part of c_v
v.out_sosi.valid := '1'; -- out_sosi.valid 1
ELSE
v.out_sosi.data(c_out_data_w-1 DOWNTO 0) := v.c_v(k_c_v_w-1 DOWNTO c_out_data_w); -- fill out_sosi.data with 2nd part of c_v
v.out_sosi.valid := '1'; -- out_sosi.valid 1
END IF;
-- BSN_INPUT
v.q_bsn := in_sosi.bsn; -- a bsn number is saved when the bsn changes
IF g_in_data_w*q_reg.c_v_count+q_reg.out_of >= c_out_data_w THEN
v.q_out_bsn_ds := g_in_data_w*q_reg.c_v_count+q_reg.out_of-c_out_data_w; -- the amount of bits between word[0] and data[0] where data is the data with the bsn
ELSE
v.q_out_bsn_ds := g_in_data_w*q_reg.c_v_count+q_reg.out_of; -- the amount of bits between word[0] and data[0] where data is the data with the bsn
END IF;
v.q_sop := '1'; -- a signal which indicates that a bsn is written in this word(576) so the address counter can save the corresponinding address. (there are delay in address counter so in_adr is not the same as the address of the word the data from the bsn is written to)
v.a_of := 0;
v.c_v(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0); -- fill c_v
v.c_v_count := 1; -- increase the counter of c_v with 1
v.out_data_count := '0';
v.out_sosi.eop := '1';
IF rst = '1' THEN
v.state := RESET;
ELSIF in_stop = '1' OR in_sosi.valid = '0' THEN
v.state := STOP;
ELSIF ((g_in_data_w*(v.c_v_count+1))+v.out_of >= c_out_data_w*1) AND (v.out_data_count = '0') THEN
v.state := FIRST_OUTPUT;
ELSIF ((g_in_data_w*(v.c_v_count+1))+v.out_of >= c_out_data_w*2) AND (v.out_data_count = '1') THEN
v.state := OVERFLOW_OUTPUT;
ELSE
v.state := FILL_VECTOR;
END IF;
WHEN RESET =>
v := c_t_reg_init;
v.out_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0) := in_sosi.bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
IF rst = '1' THEN
v.state := RESET;
ELSIF in_stop = '1' OR in_sosi.valid = '0' THEN
v.state := STOP;
ELSE
v.state := FILL_VECTOR;
END IF;
WHEN STOP =>
v.out_sosi.valid := '0';
v.q_sop := '0';
v.out_data_stopped := '1';
IF rst = '1' THEN
v.state := RESET;
ELSIF in_stop = '1' OR in_sosi.valid = '0' THEN
v.state := STOP;
ELSIF ((g_in_data_w*(v.c_v_count+1))+v.out_of >= c_out_data_w*1) AND (v.out_data_count = '0') THEN
v.state := FIRST_OUTPUT;
ELSIF ((g_in_data_w*(v.c_v_count+1))+v.out_of >= c_out_data_w*2) AND (v.out_data_count = '1') THEN
v.state := OVERFLOW_OUTPUT;
ELSE
v.state := FILL_VECTOR;
END IF;
END CASE;
d_reg <= v;
END PROCESS;
-- fill outputs
out_sosi <= q_reg.out_sosi;
out_bsn_ds <= q_reg.out_bsn_ds;
out_data_stopped <= q_reg.out_data_stopped;
END rtl;