schema_name: args
schema_version: 1.0
schema_type: peripheral

hdl_library_name: unb2b_board  # ctrl_unb2b_board.vhd
hdl_library_description: "Peripherals in unb2b_board."

peripherals:
  - peripheral_name: ram_scrap  # pi_ram_scrap.py
    peripheral_description: ""
    mm_ports:
      # MM port for common_ram_r_w.vhd
      - mm_port_name: RAM_SCRAP
        mm_port_type: RAM
        mm_port_description: "One memory mapped block RAM for MM access test purposes."
        fields:
          - - field_name: rw_data 
              field_description: "Void data"
              number_of_fields: 512
              address_offset: 0x0
              access_mode: RW
              
  - peripheral_name: system_info  # pi_system_info.py
    peripheral_description: ""
    mm_ports:
      # MM port for mms_unb2b_board_system_info.vhd / common_rom.vhd
      - mm_port_name: ROM_SYSTEM_INFO     # for c_rom_version = 1 in ctrl_unb2b_board.vhd
      #- mm_port_name: ROM_SYSTEM_INFO_V2  # for c_rom_version = 2 in ctrl_unb2b_board.vhd
        mm_port_type: RAM
        mm_port_description: "Memory that stores the MM map system info of the mmap file."
        fields:
          - - field_name: ro_data
              field_description: "FPGA info memory map data"
              number_of_fields: 32768   # c_rom_addr_w in mms_unb2b_board_system_info
              address_offset: 0x0
              mm_width: 32
              user_width: 8
              radix: char8
              access_mode: RO

      # MM port for mms_unb2b_board_system_info.vhd / unb2b_board_system_info_reg.vhd
      - mm_port_name: PIO_SYSTEM_INFO
        mm_port_type: REG
        mm_port_description: "FPGA design name, design note, version and location index info."
        fields:
          # All registers in one array
          #- - field_name: info
          #    field_description: "FPGA info register, see pi_system_info.py for field details."
          #    access_mode: RO
          #    address_offset: 0x0
          #    number_of_fields: 32

          # Each field specified
          - - field_name: info
              field_description: "Info"
              address_offset: 0x0
              bit_offset: 0
              mm_width: 32
              access_mode: RO
          - "info": # field_group
            - field_name: gn_index
              field_description: "Global node index, unb2 FPGA id = gn_index % 4, unb2 backplane id = gn_index // 4"
              address_offset: 0x0
              bit_offset: 0
              mm_width: 8
              access_mode: RO
            - field_name: hw_version
              field_description: "UniBoard2 hardware (HW) version."
              address_offset: 0x0
              bit_offset: 8
              mm_width: 2
              access_mode: RO
            - field_name: cs_sim
              field_description: "0 when running on HW, 1 when running in simulation."
              address_offset: 0x0
              bit_offset: 10
              mm_width: 1
              access_mode: RO
            - field_name: fw_version_major
              field_description: "FPGA Firmware (FW) version major number, not used use version stamp instead."
              address_offset: 0x0
              bit_offset: 16
              mm_width: 4
              access_mode: RO
            - field_name: fw_version_minor
              field_description: "FPGA Firmware (FW) version minor number, not used use version stamp instead."
              address_offset: 0x0
              bit_offset: 20
              mm_width: 4
              access_mode: RO
            - field_name: rom_version
              field_description: "Version of the mmap schema in ROM_SYSTEM_INFO."
              address_offset: 0x0
              bit_offset: 24
              mm_width: 3
              access_mode: RO
            - field_name: technology
              field_description: "FPGA technology"
              address_offset: 0x0
              bit_offset: 27
              mm_width: 5
              access_mode: RO
          - - field_name: use_phy
              field_description: "PHY interfaces that are active in the FPGA, not used."
              address_offset: 0x4
              mm_width: 8
              access_mode: RO
          - - field_name: design_name
              field_description: "FPGA FW design name string."
              number_of_fields: 52
              address_offset: 0x8
              mm_width: 32
              user_width: 8
              radix: char8
              access_mode: RO
          - - field_name: stamp_date
              field_description: "FPGA FW compile date string."
              access_mode: RO
              address_offset: 0x3C
              number_of_fields: 1
          - - field_name: stamp_time
              field_description: "FPGA FW compile time string."
              number_of_fields: 1
              address_offset: 0x40
              access_mode: RO
          - - field_name: stamp_commit
              field_description: "FPGA FW commit hash string."
              number_of_fields: 3
              address_offset: 0x44
              access_mode: RO
          - - field_name: design_note
              field_description: "FPGA FW design note string."
              number_of_fields: 48
              address_offset: 0x50
              mm_width: 32
              user_width: 8
              radix: char8
              access_mode: RO
              
  - peripheral_name: wdi  # pi_wdi.py
    peripheral_description: ""
    mm_ports:
      # MM port for unb2b_board_wdi_reg.vhd
      - mm_port_name: REG_WDI
        mm_port_type: REG
        mm_port_description: "Reset register, if the right value is provided the factory image will be reloaded in the FPGA."
        fields:
          - - field_name: wdi_override
              field_description: "Write value 0xB007FAC7 = 'Boot factory' to disable the watchdog interrupt (WDI), to cause an FPGA image reload."
              address_offset: 0x0
              access_mode: WO

  - peripheral_name: unb2_fpga_sens
    peripheral_description: ""
    mm_ports:
      # MM ports for mms_unb2b_fpga_sens.vhd / unb2b_fpga_sens_reg.vhd
      - mm_port_name: REG_FPGA_TEMP_SENS   # pi_unb_fpga_sens.py
        mm_port_type: REG
        mm_port_description: |
             "FPGA temperature = (AxC)/1024 - B (where A=708; B=273; C=adc value), see page 10 in
              https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_alttemp_sense.pdf"
        fields:
          - - field_name: temp
              field_description: "Raw data"
              number_of_fields: 1
              address_offset: 0x0
              access_mode: RO
              
      - mm_port_name: REG_FPGA_VOLTAGE_SENS  # pi_unb_fpga_voltagesens.py
        mm_port_type: REG
        mm_port_description: "Not used, FPGA voltages are monitored via DC-DC converter power supply volages"
        fields:
          - - field_name: voltages
              field_description: "Not used"
              number_of_fields: 6
              address_offset: 0x0
              access_mode: RO

