-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------

-- Purpose: Testbench for tech_10gbase_r.
-- Description:
--   The tb is not self checking.
--   The tb is used to investigate what clocks the 10gbase_r phy uses.
-- Usage:
--   > as 10
--   > run 100 us

LIBRARY IEEE, technology_lib, common_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_interface_layers_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;


ENTITY tb_tech_10gbase_r IS
  -- Test bench control parameters
  GENERIC (
    g_technology : NATURAL := c_tech_select_default;
    g_nof_phy    : NATURAL := 1
  );
END tb_tech_10gbase_r;


ARCHITECTURE tb OF tb_tech_10gbase_r IS

  CONSTANT sys_clk_period       : TIME :=  5 ns;     -- 200 MHz
  CONSTANT tr_ref_clk_period    : TIME :=  1551515 fs;  -- ~ 644.53125 MHz
  CONSTANT tx_core_clk_period   : TIME :=  5 ns; --6.4 ns;   -- 156.25 MHz
  CONSTANT rx_core_clk_period   : TIME :=  5 ns; --6.4 ns;   -- 156.25 MHz
  CONSTANT phy_delay            : TIME :=  1 ns;
  
  SIGNAL sys_clk                : STD_LOGIC := '0';
  SIGNAL sys_rst                : STD_LOGIC;

  SIGNAL tr_ref_clk             : STD_LOGIC := '0';

  SIGNAL tx_core_clk_in         : STD_LOGIC := '0';
  SIGNAL rx_core_clk_in         : STD_LOGIC := '0';
    
  SIGNAL tx_pma_div_clk_out     : STD_LOGIC;
  SIGNAL tx_pma_clk_out         : STD_LOGIC;
  SIGNAL tx_clk_out             : STD_LOGIC;    -- 156.25 MHz
  SIGNAL rx_clk_out             : STD_LOGIC;    -- 156.25 MHz
    
  -- XGMII interface
  SIGNAL xgmii_tx_dc_arr   : t_xgmii_dc_arr(g_nof_phy-1 DOWNTO 0);
  SIGNAL xgmii_rx_dc_arr   : t_xgmii_dc_arr(g_nof_phy-1 DOWNTO 0);

  -- PHY serial interface
  SIGNAL tx_serial_arr     : STD_LOGIC_VECTOR(g_nof_phy-1 DOWNTO 0);
  SIGNAL rx_serial_arr     : STD_LOGIC_VECTOR(g_nof_phy-1 DOWNTO 0);
  
BEGIN

  -- run 50 us
  sys_clk        <= NOT sys_clk        AFTER sys_clk_period/2;
  tr_ref_clk     <= NOT tr_ref_clk     AFTER tr_ref_clk_period/2;
  tx_core_clk_in <= NOT tx_core_clk_in AFTER tx_core_clk_period/2;
  rx_core_clk_in <= NOT rx_core_clk_in AFTER rx_core_clk_period/2;
  
  sys_rst <= '1', '0' AFTER sys_clk_period*10;

  dut : ENTITY work.tech_10gbase_r
  GENERIC MAP (
    g_technology          => g_technology,
    g_nof_phy             => g_nof_phy
  )
  PORT MAP (
    sys_clk                 => sys_clk,
    sys_rst                 => sys_rst,

    -- Transceiver PLL reference clock
    tr_ref_clk              => tr_ref_clk,

    tx_core_clk_in          => tx_core_clk_in,
    rx_core_clk_in          => rx_core_clk_in,
    
    tx_pma_div_clk_out      => tx_pma_div_clk_out,
    tx_pma_clk_out          => tx_pma_clk_out,
    tx_clk_out              => tx_clk_out,            -- 156.25 MHz
    rx_clk_out              => rx_clk_out,            -- 156.25 MHz
    
    xgmii_tx_dc_arr         => xgmii_tx_dc_arr,
    xgmii_rx_dc_arr         => xgmii_rx_dc_arr,

    tx_serial_arr           => tx_serial_arr,
    rx_serial_arr           => rx_serial_arr
  );
  
  -- PHY loopback
  rx_serial_arr <= TRANSPORT tx_serial_arr AFTER phy_delay;
  
END tb;