diff --git a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
index 4e85d15d7a7d259ac7d503c098b6579849845b9f..8489330cb1cca3a6af9e7161fbc28cadbc05bedb 100644
--- a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
@@ -75,6 +75,7 @@ ARCHITECTURE tb OF tb_unb1_test IS
   CONSTANT c_sa_clk_period   : TIME := 6.4 ns; 
   CONSTANT c_pps_period      : NATURAL := 1000; 
 
+  CONSTANT c_use_ddr         : BOOLEAN := g_design_name="unb1_test_ddr" OR g_design_name="unb1_test_all";
   CONSTANT c_ddr             : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
 
   -- DUT
@@ -209,15 +210,17 @@ BEGIN
   ------------------------------------------------------------------------------
   -- DDR3 memory model
   ------------------------------------------------------------------------------
-  u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
-  GENERIC MAP (
-    g_tech_ddr => c_ddr
-  )
-  PORT MAP (
-    mem3_in => phy_ou,
-    mem3_io => phy_io,
-    mem3_ou => phy_in
-  );
+  gen_tech_ddr_memory_model : IF c_use_ddr = TRUE GENERATE
+    u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
+    GENERIC MAP (
+      g_tech_ddr => c_ddr
+    )
+    PORT MAP (
+      mem3_in => phy_ou,
+      mem3_io => phy_io,
+      mem3_ou => phy_in
+    );
+  END GENERATE;
 
   ------------------------------------------------------------------------------
   -- UniBoard sensors