diff --git a/boards/uniboard1/designs/unb1_test/hdllib.cfg b/boards/uniboard1/designs/unb1_test/hdllib.cfg
index cf4a8b596957479fb517e7c48a221bc39ac2201c..de1d6e71be66dec8dec1a3e1af33b01bf60ffea7 100644
--- a/boards/uniboard1/designs/unb1_test/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/hdllib.cfg
@@ -10,6 +10,7 @@ synth_files =
src/vhdl/unb1_test_pkg.vhd
src/vhdl/mmm_unb1_test.vhd
src/vhdl/udp_stream_test.vhd
+ src/vhdl/ddr_stream_test.vhd
src/vhdl/unb1_test.vhd
test_bench_files =
diff --git a/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys b/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
index 164e1fba6255f5af1f082ecda753a29a91fe748c..0b0118a03eb0d4f5fe886c21928da165141dda9a 100644
--- a/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
+++ b/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
@@ -69,7 +69,15 @@
{
datum baseAddress
{
- value = "12768";
+ value = "12960";
+ type = "long";
+ }
+ }
+ element reg_bsn_monitor_ddr.mem
+ {
+ datum baseAddress
+ {
+ value = "12736";
type = "long";
}
}
@@ -93,7 +101,7 @@
{
datum baseAddress
{
- value = "12816";
+ value = "13040";
type = "long";
}
}
@@ -101,7 +109,7 @@
{
datum baseAddress
{
- value = "12824";
+ value = "13048";
type = "long";
}
}
@@ -109,7 +117,7 @@
{
datum baseAddress
{
- value = "12856";
+ value = "13080";
type = "long";
}
}
@@ -125,7 +133,15 @@
{
datum baseAddress
{
- value = "12832";
+ value = "13056";
+ type = "long";
+ }
+ }
+ element ram_diag_data_buffer_ddr.mem
+ {
+ datum baseAddress
+ {
+ value = "524288";
type = "long";
}
}
@@ -146,7 +162,15 @@
{
datum baseAddress
{
- value = "12736";
+ value = "12928";
+ type = "long";
+ }
+ }
+ element reg_diag_data_buffer_ddr.mem
+ {
+ datum baseAddress
+ {
+ value = "12544";
type = "long";
}
}
@@ -191,7 +215,7 @@
{
datum baseAddress
{
- value = "12840";
+ value = "13064";
type = "long";
}
}
@@ -207,7 +231,7 @@
{
datum baseAddress
{
- value = "12544";
+ value = "12672";
type = "long";
}
}
@@ -215,7 +239,15 @@
{
datum baseAddress
{
- value = "12608";
+ value = "12800";
+ type = "long";
+ }
+ }
+ element reg_diag_bg_ddr.mem
+ {
+ datum baseAddress
+ {
+ value = "12992";
type = "long";
}
}
@@ -223,7 +255,7 @@
{
datum baseAddress
{
- value = "12848";
+ value = "13072";
type = "long";
}
}
@@ -239,7 +271,15 @@
{
datum baseAddress
{
- value = "12640";
+ value = "12832";
+ type = "long";
+ }
+ }
+ element ram_diag_bg_ddr.mem
+ {
+ datum baseAddress
+ {
+ value = "49152";
type = "long";
}
}
@@ -268,7 +308,7 @@
{
datum baseAddress
{
- value = "12672";
+ value = "12864";
type = "long";
}
}
@@ -316,7 +356,7 @@
{
datum baseAddress
{
- value = "12800";
+ value = "13024";
type = "long";
}
}
@@ -324,7 +364,7 @@
{
datum baseAddress
{
- value = "12704";
+ value = "12896";
type = "long";
}
}
@@ -398,7 +438,7 @@
{
datum _sortIndex
{
- value = "31";
+ value = "33";
type = "int";
}
}
@@ -406,7 +446,15 @@
{
datum _sortIndex
{
- value = "30";
+ value = "32";
+ type = "int";
+ }
+ }
+ element ram_diag_bg_ddr
+ {
+ datum _sortIndex
+ {
+ value = "34";
type = "int";
}
}
@@ -414,7 +462,7 @@
{
datum _sortIndex
{
- value = "35";
+ value = "39";
type = "int";
}
}
@@ -422,7 +470,15 @@
{
datum _sortIndex
{
- value = "34";
+ value = "38";
+ type = "int";
+ }
+ }
+ element ram_diag_data_buffer_ddr
+ {
+ datum _sortIndex
+ {
+ value = "40";
type = "int";
}
}
@@ -430,7 +486,7 @@
{
datum _sortIndex
{
- value = "36";
+ value = "41";
type = "int";
}
}
@@ -450,11 +506,19 @@
type = "int";
}
}
+ element reg_bsn_monitor_ddr
+ {
+ datum _sortIndex
+ {
+ value = "22";
+ type = "int";
+ }
+ }
element reg_diag_bg_10GbE
{
datum _sortIndex
{
- value = "29";
+ value = "30";
type = "int";
}
}
@@ -462,7 +526,15 @@
{
datum _sortIndex
{
- value = "28";
+ value = "29";
+ type = "int";
+ }
+ }
+ element reg_diag_bg_ddr
+ {
+ datum _sortIndex
+ {
+ value = "31";
type = "int";
}
}
@@ -470,7 +542,7 @@
{
datum _sortIndex
{
- value = "33";
+ value = "36";
type = "int";
}
}
@@ -478,7 +550,15 @@
{
datum _sortIndex
{
- value = "32";
+ value = "35";
+ type = "int";
+ }
+ }
+ element reg_diag_data_buffer_ddr
+ {
+ datum _sortIndex
+ {
+ value = "37";
type = "int";
}
}
@@ -486,7 +566,7 @@
{
datum _sortIndex
{
- value = "27";
+ value = "28";
type = "int";
}
}
@@ -494,7 +574,7 @@
{
datum _sortIndex
{
- value = "26";
+ value = "27";
type = "int";
}
}
@@ -502,7 +582,7 @@
{
datum _sortIndex
{
- value = "23";
+ value = "24";
type = "int";
}
}
@@ -510,7 +590,7 @@
{
datum _sortIndex
{
- value = "25";
+ value = "26";
type = "int";
}
}
@@ -518,7 +598,7 @@
{
datum _sortIndex
{
- value = "22";
+ value = "23";
type = "int";
}
}
@@ -526,7 +606,7 @@
{
datum _sortIndex
{
- value = "24";
+ value = "25";
type = "int";
}
}
@@ -558,7 +638,7 @@
{
datum _sortIndex
{
- value = "37";
+ value = "42";
type = "int";
}
}
@@ -2266,6 +2346,181 @@
internal="ram_diag_data_buffer_10GbE.readdata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_bsn_monitor_ddr_readdata"
+ internal="reg_bsn_monitor_ddr.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_ddr_read"
+ internal="reg_bsn_monitor_ddr.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_ddr_writedata"
+ internal="reg_bsn_monitor_ddr.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_ddr_write"
+ internal="reg_bsn_monitor_ddr.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_ddr_address"
+ internal="reg_bsn_monitor_ddr.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_ddr_clk"
+ internal="reg_bsn_monitor_ddr.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_ddr_reset"
+ internal="reg_bsn_monitor_ddr.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_ddr_readdata"
+ internal="reg_diag_bg_ddr.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_ddr_read"
+ internal="reg_diag_bg_ddr.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_ddr_writedata"
+ internal="reg_diag_bg_ddr.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_ddr_write"
+ internal="reg_diag_bg_ddr.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_ddr_address"
+ internal="reg_diag_bg_ddr.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_ddr_clk"
+ internal="reg_diag_bg_ddr.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_bg_ddr_reset"
+ internal="reg_diag_bg_ddr.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_ddr_readdata"
+ internal="ram_diag_bg_ddr.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_ddr_read"
+ internal="ram_diag_bg_ddr.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_ddr_writedata"
+ internal="ram_diag_bg_ddr.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_ddr_write"
+ internal="ram_diag_bg_ddr.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_ddr_address"
+ internal="ram_diag_bg_ddr.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_ddr_clk"
+ internal="ram_diag_bg_ddr.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_bg_ddr_reset"
+ internal="ram_diag_bg_ddr.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_ddr_readdata"
+ internal="reg_diag_data_buffer_ddr.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_ddr_read"
+ internal="reg_diag_data_buffer_ddr.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_ddr_writedata"
+ internal="reg_diag_data_buffer_ddr.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_ddr_write"
+ internal="reg_diag_data_buffer_ddr.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_ddr_address"
+ internal="reg_diag_data_buffer_ddr.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_ddr_clk"
+ internal="reg_diag_data_buffer_ddr.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diag_data_buffer_ddr_reset"
+ internal="reg_diag_data_buffer_ddr.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_ddr_readdata"
+ internal="ram_diag_data_buffer_ddr.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_ddr_read"
+ internal="ram_diag_data_buffer_ddr.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_ddr_writedata"
+ internal="ram_diag_data_buffer_ddr.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_ddr_write"
+ internal="ram_diag_data_buffer_ddr.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_ddr_address"
+ internal="ram_diag_data_buffer_ddr.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_ddr_clk"
+ internal="ram_diag_data_buffer_ddr.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_diag_data_buffer_ddr_reset"
+ internal="ram_diag_data_buffer_ddr.reset"
+ type="conduit"
+ dir="end" />
<module kind="clock_source" version="11.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="125000000" />
<parameter name="clockFrequencyKnown" value="true" />
@@ -2496,7 +2751,7 @@ q]]></parameter>
<parameter name="dcache_numTCDM" value="0" />
<parameter name="dcache_lineSize" value="32" />
<parameter name="instAddrWidth" value="18" />
- <parameter name="dataAddrWidth" value="19" />
+ <parameter name="dataAddrWidth" value="20" />
<parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
@@ -2506,7 +2761,7 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_1GbE.mem' start='0x80' end='0x100' /><slave name='reg_dp_offload_rx_1GbE_hdr_dat.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_1GbE_hdr_dat.mem' start='0x200' end='0x300' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x300' end='0x400' /><slave name='reg_dp_offload_tx_10GbE_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' /><slave name='reg_diag_data_buffer_10GbE.mem' start='0x3080' end='0x3100' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x3100' end='0x3140' /><slave name='reg_unb_sens.mem' start='0x3140' end='0x3160' /><slave name='reg_remu.mem' start='0x3160' end='0x3180' /><slave name='reg_epcs.mem' start='0x3180' end='0x31A0' /><slave name='reg_diag_bg_1GbE.mem' start='0x31A0' end='0x31C0' /><slave name='reg_dp_offload_tx_10GbE.mem' start='0x31C0' end='0x31E0' /><slave name='reg_diag_bg_10GbE.mem' start='0x31E0' end='0x3200' /><slave name='reg_io_ddr.mem' start='0x3200' end='0x3210' /><slave name='reg_dpmm_ctrl.mem' start='0x3210' end='0x3218' /><slave name='reg_dpmm_data.mem' start='0x3218' end='0x3220' /><slave name='reg_mmdp_ctrl.mem' start='0x3220' end='0x3228' /><slave name='reg_mmdp_data.mem' start='0x3228' end='0x3230' /><slave name='pio_pps.mem' start='0x3230' end='0x3238' /><slave name='reg_dp_offload_tx_1GbE.mem' start='0x3238' end='0x3240' /><slave name='reg_dp_offload_rx_10GbE_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='ram_diag_bg_10GbE.mem' start='0x4000' end='0x8000' /><slave name='reg_tr_xaui.mem' start='0x8000' end='0xA000' /><slave name='avs_eth_0.mms_ram' start='0xA000' end='0xB000' /><slave name='ram_diag_bg_1GbE.mem' start='0xB000' end='0xC000' /><slave name='ram_diag_data_buffer_1GbE.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /><slave name='ram_ss_ss_wide.mem' start='0x60000' end='0x70000' /><slave name='ram_diag_data_buffer_10GbE.mem' start='0x70000' end='0x80000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_1GbE.mem' start='0x80' end='0x100' /><slave name='reg_dp_offload_rx_1GbE_hdr_dat.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_1GbE_hdr_dat.mem' start='0x200' end='0x300' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x300' end='0x400' /><slave name='reg_dp_offload_tx_10GbE_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' /><slave name='reg_diag_data_buffer_10GbE.mem' start='0x3080' end='0x3100' /><slave name='reg_diag_data_buffer_ddr.mem' start='0x3100' end='0x3180' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x3180' end='0x31C0' /><slave name='reg_bsn_monitor_ddr.mem' start='0x31C0' end='0x3200' /><slave name='reg_unb_sens.mem' start='0x3200' end='0x3220' /><slave name='reg_remu.mem' start='0x3220' end='0x3240' /><slave name='reg_epcs.mem' start='0x3240' end='0x3260' /><slave name='reg_diag_bg_1GbE.mem' start='0x3260' end='0x3280' /><slave name='reg_dp_offload_tx_10GbE.mem' start='0x3280' end='0x32A0' /><slave name='reg_diag_bg_10GbE.mem' start='0x32A0' end='0x32C0' /><slave name='reg_diag_bg_ddr.mem' start='0x32C0' end='0x32E0' /><slave name='reg_io_ddr.mem' start='0x32E0' end='0x32F0' /><slave name='reg_dpmm_ctrl.mem' start='0x32F0' end='0x32F8' /><slave name='reg_dpmm_data.mem' start='0x32F8' end='0x3300' /><slave name='reg_mmdp_ctrl.mem' start='0x3300' end='0x3308' /><slave name='reg_mmdp_data.mem' start='0x3308' end='0x3310' /><slave name='pio_pps.mem' start='0x3310' end='0x3318' /><slave name='reg_dp_offload_tx_1GbE.mem' start='0x3318' end='0x3320' /><slave name='reg_dp_offload_rx_10GbE_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='ram_diag_bg_10GbE.mem' start='0x4000' end='0x8000' /><slave name='reg_tr_xaui.mem' start='0x8000' end='0xA000' /><slave name='avs_eth_0.mms_ram' start='0xA000' end='0xB000' /><slave name='ram_diag_bg_1GbE.mem' start='0xB000' end='0xC000' /><slave name='ram_diag_bg_ddr.mem' start='0xC000' end='0xD000' /><slave name='ram_diag_data_buffer_1GbE.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /><slave name='ram_ss_ss_wide.mem' start='0x60000' end='0x70000' /><slave name='ram_diag_data_buffer_10GbE.mem' start='0x70000' end='0x80000' /><slave name='ram_diag_data_buffer_ddr.mem' start='0x80000' end='0x90000' /></address-map>]]></parameter>
<parameter name="clockFrequency" value="125000000" />
<parameter name="deviceFamilyName" value="Stratix IV" />
<parameter name="internalIrqMaskSystemInfo" value="7" />
@@ -2675,6 +2930,43 @@ q]]></parameter>
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_bsn_monitor_ddr">
+ <parameter name="g_adr_w" value="4" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_diag_bg_ddr">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="ram_diag_bg_ddr">
+ <parameter name="g_adr_w" value="10" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_diag_data_buffer_ddr">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="ram_diag_data_buffer_ddr">
+ <parameter name="g_adr_w" value="14" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
<connection
kind="avalon"
version="11.1"
@@ -2747,7 +3039,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_unb_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3140" />
+ <parameter name="baseAddress" value="0x3200" />
</connection>
<connection
kind="avalon"
@@ -2779,7 +3071,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_remu.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3160" />
+ <parameter name="baseAddress" value="0x3220" />
</connection>
<connection
kind="avalon"
@@ -2787,7 +3079,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3210" />
+ <parameter name="baseAddress" value="0x32f0" />
</connection>
<connection
kind="avalon"
@@ -2795,7 +3087,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3218" />
+ <parameter name="baseAddress" value="0x32f8" />
</connection>
<connection
kind="avalon"
@@ -2803,7 +3095,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3220" />
+ <parameter name="baseAddress" value="0x3300" />
</connection>
<connection
kind="avalon"
@@ -2811,7 +3103,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3228" />
+ <parameter name="baseAddress" value="0x3308" />
</connection>
<connection
kind="avalon"
@@ -2819,7 +3111,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_epcs.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3180" />
+ <parameter name="baseAddress" value="0x3240" />
</connection>
<connection
kind="avalon"
@@ -2827,7 +3119,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3230" />
+ <parameter name="baseAddress" value="0x3310" />
</connection>
<connection
kind="avalon"
@@ -3077,7 +3369,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_bsn_monitor_1GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3100" />
+ <parameter name="baseAddress" value="0x3180" />
</connection>
<connection
kind="reset"
@@ -3128,7 +3420,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dp_offload_tx_1GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3238" />
+ <parameter name="baseAddress" value="0x3318" />
</connection>
<connection
kind="avalon"
@@ -3180,7 +3472,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_diag_bg_1GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x31a0" />
+ <parameter name="baseAddress" value="0x3260" />
</connection>
<connection
kind="avalon"
@@ -3349,7 +3641,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_io_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3200" />
+ <parameter name="baseAddress" value="0x32e0" />
</connection>
<connection
kind="reset"
@@ -3455,7 +3747,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dp_offload_tx_10GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x31c0" />
+ <parameter name="baseAddress" value="0x3280" />
</connection>
<connection
kind="clock"
@@ -3494,7 +3786,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_diag_bg_10GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x31e0" />
+ <parameter name="baseAddress" value="0x32a0" />
</connection>
<connection
kind="clock"
@@ -3535,4 +3827,119 @@ q]]></parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00070000" />
</connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_bsn_monitor_ddr.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_bsn_monitor_ddr.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_diag_bg_ddr.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_diag_bg_ddr.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="ram_diag_bg_ddr.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="ram_diag_bg_ddr.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_diag_data_buffer_ddr.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_diag_data_buffer_ddr.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="ram_diag_data_buffer_ddr.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="ram_diag_data_buffer_ddr.system_reset" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_bsn_monitor_ddr.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor_ddr.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x31c0" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_diag_bg_ddr.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diag_bg_ddr.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x32c0" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="ram_diag_bg_ddr.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="ram_diag_bg_ddr.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0xc000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_diag_data_buffer_ddr.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diag_data_buffer_ddr.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3100" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="ram_diag_data_buffer_ddr.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="ram_diag_data_buffer_ddr.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00080000" />
+ </connection>
</system>
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/ddr_stream_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/ddr_stream_test.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..45e61614e8c5fe629612f95c6fbfaed6573dba07
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/ddr_stream_test.vhd
@@ -0,0 +1,328 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, technology_lib, tech_ddr_lib, diag_lib, io_ddr_lib, reorder_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE reorder_lib.reorder_pkg.ALL;
+USE work.unb1_test_pkg.ALL;
+
+ENTITY ddr_stream_test IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_technology : NATURAL := c_tech_stratixiv;
+ g_nof_streams : NATURAL;
+ g_data_w : NATURAL;
+
+ g_bg_block_size : NATURAL := 900;
+ g_bg_gapsize : NATURAL := 100;
+ g_bg_blocks_per_sync : NATURAL := 200000;
+
+ g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
+ g_ena_pre_transp : BOOLEAN := TRUE;
+ g_reorder_seq : t_reorder_seq := c_reorder_seq
+ );
+ PORT (
+ -- System
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+
+ -- blockgen mm
+ reg_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- BG control register (one for all streams)
+ reg_diag_bg_miso : OUT t_mem_miso;
+ ram_diag_bg_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- BG buffer RAM (one per stream)
+ ram_diag_bg_miso : OUT t_mem_miso;
+
+ -- bsn
+ reg_bsn_monitor_mosi : IN t_mem_mosi;
+ reg_bsn_monitor_miso : OUT t_mem_miso;
+
+ -- databuffer
+ reg_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_diag_data_buf_miso : OUT t_mem_miso;
+ ram_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_diag_data_buf_miso : OUT t_mem_miso;
+
+ -- IO DDR register map
+ reg_io_ddr_mosi : IN t_mem_mosi;
+ reg_io_ddr_miso : OUT t_mem_miso;
+
+ -- Reorder transpose
+ ram_ss_ss_transp_mosi : IN t_mem_mosi;
+ ram_ss_ss_transp_miso : OUT t_mem_miso;
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN : IN t_tech_ddr3_phy_in;
+ MB_I_IO : INOUT t_tech_ddr3_phy_io;
+ MB_I_OU : OUT t_tech_ddr3_phy_ou
+ );
+END ddr_stream_test;
+
+
+
+ARCHITECTURE str OF ddr_stream_test IS
+
+ -- Block generator
+ CONSTANT c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
+ '0', -- enable_sync
+ TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
+
+ CONSTANT c_max_nof_words_per_block : NATURAL := g_bg_block_size;
+ CONSTANT c_min_nof_words_per_block : NATURAL := 1;
+ CONSTANT c_def_nof_blocks_per_packet : NATURAL := 1;
+
+
+ -- ddr
+ CONSTANT c_wr_fifo_depth : NATURAL := 128; -- >=16 , defined at DDR side of the FIFO.
+ CONSTANT c_rd_fifo_depth : NATURAL := 256; -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
+
+
+ SIGNAL block_gen_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL block_gen_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+ SIGNAL fifo_block_gen_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL fifo_block_gen_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+
+ SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL diag_data_buf_snk_out_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+
+ -- Signals to interface with the DDR conroller and memory model.
+ SIGNAL ctlr_dvr_miso : t_mem_ctlr_miso;
+ SIGNAL ctlr_dvr_mosi : t_mem_ctlr_mosi;
+
+ SIGNAL to_mem_siso : t_dp_siso := c_dp_siso_rdy;
+ SIGNAL to_mem_sosi : t_dp_sosi;
+
+ SIGNAL from_mem_siso : t_dp_siso := c_dp_siso_rdy;
+ SIGNAL from_mem_sosi : t_dp_sosi;
+
+ SIGNAL ddr_out_clk_i : STD_LOGIC;
+ SIGNAL ddr_out_rst_i : STD_LOGIC;
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- TX: Block generator and DP fifo
+ -----------------------------------------------------------------------------
+ u_mms_diag_block_gen: ENTITY diag_lib.mms_diag_block_gen
+ GENERIC MAP (
+ g_nof_streams => g_nof_streams,
+ g_buf_dat_w => g_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_name_prefix => "../../counter_data_" & NATURAL'IMAGE(g_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => '1',
+
+ out_sosi_arr => block_gen_src_out_arr,--block_gen_src_1GbE_out_arr,
+ out_siso_arr => block_gen_src_in_arr,--block_gen_src_1GbE_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,--reg_diag_bg_1GbE_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,--reg_diag_bg_1GbE_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,--ram_diag_bg_1GbE_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso --ram_diag_bg_1GbE_miso
+ );
+
+
+
+ u_dp_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
+ GENERIC MAP (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => TRUE,
+ --g_sync_timeout => g_bg_blocks_per_sync*(g_bg_block_size+g_bg_gapsize),
+ g_cnt_sop_w => c_word_w,--ceil_log2(g_bg_blocks_per_sync+1),
+ g_cnt_valid_w => c_word_w,--ceil_log2(g_bg_blocks_per_sync*g_bg_block_size+1),
+ g_log_first_bsn => TRUE
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => diag_data_buf_snk_out_arr,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
+
+ diag_data_buf_snk_out_arr <= (OTHERS=>c_dp_siso_rdy);
+
+ u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
+ GENERIC MAP (
+ g_nof_streams => g_nof_streams,
+ g_data_w => 32, --g_data_w, --FIXME
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => FALSE -- sync by reading last address of data buffer
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+
+ --in_sync => diag_data_buf_snk_in_arr(0).sop,
+ in_sync => diag_data_buf_snk_in_arr(0).sync,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
+
+
+ u_transpose: ENTITY reorder_lib.reorder_transpose
+ GENERIC MAP(
+ g_nof_streams => g_nof_streams,
+ g_in_dat_w => g_data_w,
+ g_frame_size_in => g_reorder_seq.wr_chunksize,
+ g_frame_size_out => g_reorder_seq.wr_chunksize,
+ g_use_complex => FALSE,
+ g_ena_pre_transp => g_ena_pre_transp,
+ g_reorder_seq => g_reorder_seq
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => ddr_out_rst_i,
+ dp_clk => ddr_out_clk_i,
+
+ -- ST sink
+ snk_out_arr => block_gen_src_in_arr,
+ snk_in_arr => block_gen_src_out_arr,
+
+ -- ST source
+ src_in_arr => (OTHERS => c_dp_siso_rdy),
+ src_out_arr => diag_data_buf_snk_in_arr,
+
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ -- Control interface to the external memory
+ dvr_miso => ctlr_dvr_miso,
+ dvr_mosi => ctlr_dvr_mosi,
+
+ -- Data interface to the external memory
+ to_mem_src_out => to_mem_sosi,
+ to_mem_src_in => to_mem_siso,
+
+ from_mem_snk_in => from_mem_sosi,
+ from_mem_snk_out => from_mem_siso
+
+ );
+
+ ------------------------------------------------------------------------------
+ -- DDR3 MODULE 0, MB_I
+ ------------------------------------------------------------------------------
+ u_ddr_mem_ctrl : ENTITY io_ddr_lib.io_ddr
+ GENERIC MAP(
+ g_technology => g_technology,
+ g_tech_ddr => g_tech_ddr,
+ g_cross_domain_dvr_ctlr => FALSE,
+ g_wr_data_w => g_data_w,
+ g_wr_fifo_depth => c_wr_fifo_depth,
+ g_rd_fifo_depth => c_rd_fifo_depth,
+ g_rd_data_w => g_data_w,
+ g_wr_flush_mode => "SYN",
+ g_wr_flush_use_channel => FALSE,
+ g_wr_flush_start_channel => 0,
+ g_wr_flush_nof_channels => 1
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- MM register map for DDR controller status info
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- DDR reference clock
+ ctlr_ref_clk => dp_clk,
+ ctlr_ref_rst => dp_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_out_clk_i,
+ ctlr_rst_out => ddr_out_rst_i,
+
+ ctlr_clk_in => ddr_out_clk_i,
+ ctlr_rst_in => ddr_out_rst_i,
+
+
+ -- Driver clock domain
+ dvr_clk => ddr_out_clk_i,
+ dvr_rst => ddr_out_rst_i,
+
+ dvr_miso => ctlr_dvr_miso,
+ dvr_mosi => ctlr_dvr_mosi,
+
+ -- Write FIFO clock domain
+ wr_clk => ddr_out_clk_i,
+ wr_rst => ddr_out_rst_i,
+
+ wr_fifo_usedw => OPEN,
+ wr_sosi => to_mem_sosi,
+ wr_siso => to_mem_siso,
+
+ -- Read FIFO clock domain
+ rd_clk => ddr_out_clk_i,
+ rd_rst => ddr_out_rst_i,
+
+ rd_fifo_usedw => OPEN,
+ rd_sosi => from_mem_sosi,
+ rd_siso => from_mem_siso,
+
+ term_ctrl_out => OPEN,
+ term_ctrl_in => OPEN,
+
+ phy3_in => MB_I_IN,
+ phy3_io => MB_I_IO,
+ phy3_ou => MB_I_OU
+ );
+END str;
+
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index 8af77608bfc83973da24637f95217e7431f84c87..03bcfe0454bbd03468b8faa19084095db7e898b4 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -47,7 +47,7 @@ ENTITY mmm_unb1_test IS
g_sim : BOOLEAN := FALSE; --FALSE: use QSYS; TRUE: use mm_file I/O
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
- g_nof_streams_1GbE : NATURAL;
+ g_nof_streams_1GbE : NATURAL;
g_nof_streams_10GbE : NATURAL;
g_nof_streams_ddr : NATURAL;
g_bg_block_size : NATURAL
@@ -117,6 +117,11 @@ ENTITY mmm_unb1_test IS
reg_diag_bg_10GbE_mosi : OUT t_mem_mosi;
reg_diag_bg_10GbE_miso : IN t_mem_miso;
+ ram_diag_bg_ddr_mosi : OUT t_mem_mosi;
+ ram_diag_bg_ddr_miso : IN t_mem_miso;
+ reg_diag_bg_ddr_mosi : OUT t_mem_mosi;
+ reg_diag_bg_ddr_miso : IN t_mem_miso;
+
-- dp_offload_tx
reg_dp_offload_tx_1GbE_mosi : OUT t_mem_mosi;
reg_dp_offload_tx_1GbE_miso : IN t_mem_miso;
@@ -139,6 +144,8 @@ ENTITY mmm_unb1_test IS
reg_bsn_monitor_1GbE_miso : IN t_mem_miso;
reg_bsn_monitor_10GbE_mosi : OUT t_mem_mosi;
reg_bsn_monitor_10GbE_miso : IN t_mem_miso;
+ reg_bsn_monitor_ddr_mosi : OUT t_mem_mosi;
+ reg_bsn_monitor_ddr_miso : IN t_mem_miso;
-- databuffer
ram_diag_data_buf_1GbE_mosi : OUT t_mem_mosi;
@@ -151,6 +158,11 @@ ENTITY mmm_unb1_test IS
reg_diag_data_buf_10GbE_mosi : OUT t_mem_mosi;
reg_diag_data_buf_10GbE_miso : IN t_mem_miso;
+ ram_diag_data_buf_ddr_mosi : OUT t_mem_mosi;
+ ram_diag_data_buf_ddr_miso : IN t_mem_miso;
+ reg_diag_data_buf_ddr_mosi : OUT t_mem_mosi;
+ reg_diag_data_buf_ddr_miso : IN t_mem_miso;
+
-- tr_10GbE
reg_tr_10GbE_mosi : OUT t_mem_mosi;
reg_tr_10GbE_miso : IN t_mem_miso;
@@ -170,6 +182,7 @@ ARCHITECTURE str OF mmm_unb1_test IS
-- Block generator
CONSTANT c_ram_diag_bg_1GbE_addr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(ceil_log2(g_bg_block_size)));
CONSTANT c_ram_diag_bg_10GbE_addr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(ceil_log2(g_bg_block_size)));
+ CONSTANT c_ram_diag_bg_ddr_addr_w : NATURAL := ceil_log2(g_nof_streams_ddr * pow2(ceil_log2(g_bg_block_size)));
-- dp_offload
CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb1_board_peripherals_mm_reg_default
@@ -207,6 +220,7 @@ ARCHITECTURE str OF mmm_unb1_test IS
-- BSN monitors
CONSTANT c_reg_rsp_bsn_monitor_1GbE_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
CONSTANT c_reg_rsp_bsn_monitor_10GbE_adr_w : NATURAL := ceil_log2(g_nof_streams_10GbE * pow2(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
+ CONSTANT c_reg_rsp_bsn_monitor_ddr_adr_w : NATURAL := ceil_log2(g_nof_streams_ddr * pow2(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w));
CONSTANT c_dp_reg_mm_nof_words : NATURAL := 1;
@@ -223,10 +237,8 @@ ARCHITECTURE str OF mmm_unb1_test IS
SIGNAL sim_eth_mm_bus_switch : STD_LOGIC;
SIGNAL sim_eth_psc_access : STD_LOGIC;
-
SIGNAL i_eth1g_reg_mosi : t_mem_mosi;
SIGNAL i_eth1g_reg_miso : t_mem_miso;
-
SIGNAL sim_eth1g_reg_mosi : t_mem_mosi;
SIGNAL i_reset_n : STD_LOGIC;
@@ -276,52 +288,51 @@ BEGIN
u_mm_file_reg_diag_bg_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
PORT MAP(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
-
u_mm_file_ram_diag_bg_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
PORT MAP(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
-
u_mm_file_reg_diag_bg_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
PORT MAP(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
-
u_mm_file_ram_diag_bg_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
PORT MAP(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
-
+ u_mm_file_reg_diag_bg_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_DDR")
+ PORT MAP(mm_rst, mm_clk, reg_diag_bg_ddr_mosi, reg_diag_bg_ddr_miso);
+ u_mm_file_ram_diag_bg_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_DDR")
+ PORT MAP(mm_rst, mm_clk, ram_diag_bg_ddr_mosi, ram_diag_bg_ddr_miso);
u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
-
u_mm_file_reg_dp_offload_tx_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_10GBE")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_10GbE_mosi, reg_dp_offload_tx_10GbE_miso);
-
u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
-
u_mm_file_reg_dp_offload_tx_10GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_10GBE_HDR_DAT")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_10GbE_hdr_dat_mosi, reg_dp_offload_tx_10GbE_hdr_dat_miso);
-
u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
-
u_mm_file_reg_dp_offload_rx_10GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_10GBE_HDR_DAT")
PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_10GbE_hdr_dat_mosi, reg_dp_offload_rx_10GbE_hdr_dat_miso);
u_mm_file_reg_bsn_monitor_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
-
u_mm_file_reg_bsn_monitor_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
-
- u_mm_file_ram_diag_data_buffer_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
- PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
- u_mm_file_ram_diag_data_buffer_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
- PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
+ u_mm_file_reg_bsn_monitor_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_DDR")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_ddr_mosi, reg_bsn_monitor_ddr_miso);
u_mm_file_reg_diag_data_buffer_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
+ u_mm_file_ram_diag_data_buffer_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
u_mm_file_reg_diag_data_buffer_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
+ u_mm_file_ram_diag_data_buffer_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
+ u_mm_file_reg_diag_data_buffer_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR")
+ PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_ddr_mosi, reg_diag_data_buf_ddr_miso);
+ u_mm_file_ram_diag_data_buffer_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR")
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_ddr_mosi, ram_diag_data_buf_ddr_miso);
u_mm_file_ram_ss_ss_transp : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
PORT MAP(mm_rst, mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
@@ -567,6 +578,22 @@ BEGIN
ram_diag_bg_10GbE_reset_export => OPEN,
ram_diag_bg_10GbE_write_export => ram_diag_bg_10GbE_mosi.wr,
ram_diag_bg_10GbE_writedata_export => ram_diag_bg_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- the_reg_diag_bg_ddr
+ reg_diag_bg_ddr_address_export => reg_diag_bg_ddr_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
+ reg_diag_bg_ddr_clk_export => OPEN,
+ reg_diag_bg_ddr_read_export => reg_diag_bg_ddr_mosi.rd,
+ reg_diag_bg_ddr_readdata_export => reg_diag_bg_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_bg_ddr_reset_export => OPEN,
+ reg_diag_bg_ddr_write_export => reg_diag_bg_ddr_mosi.wr,
+ reg_diag_bg_ddr_writedata_export => reg_diag_bg_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- the_ram_diag_bg_ddr
+ ram_diag_bg_ddr_address_export => ram_diag_bg_ddr_mosi.address(c_ram_diag_bg_ddr_addr_w-1 DOWNTO 0),
+ ram_diag_bg_ddr_clk_export => OPEN,
+ ram_diag_bg_ddr_read_export => ram_diag_bg_ddr_mosi.rd,
+ ram_diag_bg_ddr_readdata_export => ram_diag_bg_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_diag_bg_ddr_reset_export => OPEN,
+ ram_diag_bg_ddr_write_export => ram_diag_bg_ddr_mosi.wr,
+ ram_diag_bg_ddr_writedata_export => ram_diag_bg_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_dp_offload_tx_1GbE
@@ -640,6 +667,14 @@ BEGIN
reg_bsn_monitor_10GbE_reset_export => OPEN,
reg_bsn_monitor_10GbE_write_export => reg_bsn_monitor_10GbE_mosi.wr,
reg_bsn_monitor_10GbE_writedata_export => reg_bsn_monitor_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- the_reg_bsn_monitor_ddr
+ reg_bsn_monitor_ddr_address_export => reg_bsn_monitor_ddr_mosi.address(c_reg_rsp_bsn_monitor_ddr_adr_w-1 DOWNTO 0),
+ reg_bsn_monitor_ddr_clk_export => OPEN,
+ reg_bsn_monitor_ddr_read_export => reg_bsn_monitor_ddr_mosi.rd,
+ reg_bsn_monitor_ddr_readdata_export => reg_bsn_monitor_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_ddr_reset_export => OPEN,
+ reg_bsn_monitor_ddr_write_export => reg_bsn_monitor_ddr_mosi.wr,
+ reg_bsn_monitor_ddr_writedata_export => reg_bsn_monitor_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_diag_data_buffer_1GbE
@@ -658,6 +693,14 @@ BEGIN
ram_diag_data_buffer_10GbE_reset_export => OPEN,
ram_diag_data_buffer_10GbE_write_export => ram_diag_data_buf_10GbE_mosi.wr,
ram_diag_data_buffer_10GbE_writedata_export => ram_diag_data_buf_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- the_ram_diag_data_buffer_ddr
+ ram_diag_data_buffer_ddr_address_export => ram_diag_data_buf_ddr_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w-1 DOWNTO 0),
+ ram_diag_data_buffer_ddr_clk_export => OPEN,
+ ram_diag_data_buffer_ddr_read_export => ram_diag_data_buf_ddr_mosi.rd,
+ ram_diag_data_buffer_ddr_readdata_export => ram_diag_data_buf_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buffer_ddr_reset_export => OPEN,
+ ram_diag_data_buffer_ddr_write_export => ram_diag_data_buf_ddr_mosi.wr,
+ ram_diag_data_buffer_ddr_writedata_export => ram_diag_data_buf_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_diag_data_buffer_1GbE
@@ -676,6 +719,14 @@ BEGIN
reg_diag_data_buffer_10GbE_reset_export => OPEN,
reg_diag_data_buffer_10GbE_write_export => reg_diag_data_buf_10GbE_mosi.wr,
reg_diag_data_buffer_10GbE_writedata_export => reg_diag_data_buf_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- the_reg_diag_data_buffer_ddr
+ reg_diag_data_buffer_ddr_address_export => reg_diag_data_buf_ddr_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
+ reg_diag_data_buffer_ddr_clk_export => OPEN,
+ reg_diag_data_buffer_ddr_read_export => reg_diag_data_buf_ddr_mosi.rd,
+ reg_diag_data_buffer_ddr_readdata_export => reg_diag_data_buf_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buffer_ddr_reset_export => OPEN,
+ reg_diag_data_buffer_ddr_write_export => reg_diag_data_buf_ddr_mosi.wr,
+ reg_diag_data_buffer_ddr_writedata_export => reg_diag_data_buf_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- ram_ss_ss_wide
ram_ss_ss_wide_address_export => ram_ss_ss_transp_mosi.address(c_ram_ss_ss_transp_adr_w-1 DOWNTO 0),
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
index 1d4b5f70765ccd29bbcd80102d6b651d45e91c5b..f78c1f804acb2116daa9ecc22d5357da1200c105 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2013
+-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
@@ -28,6 +28,7 @@ PACKAGE qsys_unb1_test_pkg IS
-- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
-----------------------------------------------------------------------------
component qsys_unb1_test is
+
port (
coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
@@ -269,8 +270,44 @@ PACKAGE qsys_unb1_test_pkg IS
ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_ddr_read_export : out std_logic; -- export
+ reg_bsn_monitor_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_ddr_write_export : out std_logic; -- export
+ reg_bsn_monitor_ddr_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_ddr_clk_export : out std_logic; -- export
+ reg_bsn_monitor_ddr_reset_export : out std_logic; -- export
+ reg_diag_bg_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_ddr_read_export : out std_logic; -- export
+ reg_diag_bg_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_ddr_write_export : out std_logic; -- export
+ reg_diag_bg_ddr_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_ddr_clk_export : out std_logic; -- export
+ reg_diag_bg_ddr_reset_export : out std_logic; -- export
+ ram_diag_bg_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_ddr_read_export : out std_logic; -- export
+ ram_diag_bg_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_ddr_write_export : out std_logic; -- export
+ ram_diag_bg_ddr_address_export : out std_logic_vector(9 downto 0); -- export
+ ram_diag_bg_ddr_clk_export : out std_logic; -- export
+ ram_diag_bg_ddr_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buffer_ddr_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_reset_export : out std_logic -- export
);
+
end component qsys_unb1_test;
END qsys_unb1_test_pkg;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index 11eb46779437efc36f20e09544889d39a1453113..919dd5e424b1dbd4b531dcd391d08740f1138da6 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -50,7 +50,7 @@ ENTITY unb1_test IS
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
g_nof_MB : NATURAL := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
- g_use_MB_I : NATURAL := 0; -- 1: use MB_I 0: do not use
+ g_use_MB_I : NATURAL := 1; -- 1: use MB_I 0: do not use
g_use_MB_II : NATURAL := 0
);
PORT (
@@ -148,7 +148,6 @@ ARCHITECTURE str OF unb1_test IS
-- ddr
CONSTANT c_ddr_master : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
CONSTANT c_ddr_slave : t_c_tech_ddr := c_tech_ddr3_4g_800m_slave;
- CONSTANT c_st_dat_w : NATURAL := 64; -- Any power of two 8..256
-- Block generator constants
CONSTANT c_bg_block_size : NATURAL := 900;
@@ -264,6 +263,11 @@ ARCHITECTURE str OF unb1_test IS
SIGNAL ram_diag_bg_10GbE_mosi : t_mem_mosi;
SIGNAL ram_diag_bg_10GbE_miso : t_mem_miso;
+ SIGNAL reg_diag_bg_ddr_mosi : t_mem_mosi;
+ SIGNAL reg_diag_bg_ddr_miso : t_mem_miso;
+ SIGNAL ram_diag_bg_ddr_mosi : t_mem_mosi;
+ SIGNAL ram_diag_bg_ddr_miso : t_mem_miso;
+
SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
@@ -283,6 +287,8 @@ ARCHITECTURE str OF unb1_test IS
SIGNAL reg_bsn_monitor_1GbE_miso : t_mem_miso;
SIGNAL reg_bsn_monitor_10GbE_mosi : t_mem_mosi;
SIGNAL reg_bsn_monitor_10GbE_miso : t_mem_miso;
+ SIGNAL reg_bsn_monitor_ddr_mosi : t_mem_mosi;
+ SIGNAL reg_bsn_monitor_ddr_miso : t_mem_miso;
SIGNAL ram_diag_data_buf_1GbE_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_1GbE_miso : t_mem_miso;
@@ -294,6 +300,11 @@ ARCHITECTURE str OF unb1_test IS
SIGNAL reg_diag_data_buf_10GbE_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_10GbE_miso : t_mem_miso;
+ SIGNAL ram_diag_data_buf_ddr_mosi : t_mem_mosi;
+ SIGNAL ram_diag_data_buf_ddr_miso : t_mem_miso;
+ SIGNAL reg_diag_data_buf_ddr_mosi : t_mem_mosi;
+ SIGNAL reg_diag_data_buf_ddr_miso : t_mem_miso;
+
SIGNAL block_gen_1GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
SIGNAL block_gen_10GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
@@ -307,36 +318,18 @@ ARCHITECTURE str OF unb1_test IS
SIGNAL dp_offload_rx_10GbE_snk_in_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
SIGNAL dp_offload_rx_10GbE_snk_out_arr : t_dp_siso_arr(c_nof_streams_10GbE-1 DOWNTO 0);
+ SIGNAL ram_ss_ss_transp_mosi : t_mem_mosi;
+ SIGNAL ram_ss_ss_transp_miso : t_mem_miso;
+
+ SIGNAL reg_io_ddr_mosi : t_mem_mosi;
+ SIGNAL reg_io_ddr_miso : t_mem_miso;
+
-- Interface: 1GbE UDP streaming ports
SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(c_nof_streams_1GbE-1 DOWNTO 0);
- -- DDR
- SIGNAL ddr_ctlr_mosi_arr : t_mem_ctlr_mosi_arr(0 TO g_nof_MB-1);
- SIGNAL ddr_ctlr_miso_arr : t_mem_ctlr_miso_arr(0 TO g_nof_MB-1);
-
- SIGNAL ddr_ctlr_clk : STD_LOGIC_VECTOR(0 TO g_nof_MB-1);
- SIGNAL ddr_ctlr_rst : STD_LOGIC_VECTOR(0 TO g_nof_MB-1);
-
- SIGNAL ram_ss_ss_transp_mosi : t_mem_mosi;
- SIGNAL ram_ss_ss_transp_miso : t_mem_miso;
- SIGNAL ram_ss_ss_transp_mosi2 : t_mem_mosi;
- SIGNAL ram_ss_ss_transp_miso2 : t_mem_miso := c_mem_miso_rst;
-
- SIGNAL to_mem_siso : t_dp_siso := c_dp_siso_rdy;
- SIGNAL to_mem_sosi : t_dp_sosi;
- SIGNAL from_mem_siso : t_dp_siso := c_dp_siso_rdy;
- SIGNAL from_mem_sosi : t_dp_sosi;
-
- SIGNAL to_mem_siso2 : t_dp_siso := c_dp_siso_rdy;
- SIGNAL to_mem_sosi2 : t_dp_sosi;
- SIGNAL from_mem_siso2 : t_dp_siso := c_dp_siso_rdy;
- SIGNAL from_mem_sosi2 : t_dp_sosi;
-
- SIGNAL reg_io_ddr_mosi : t_mem_mosi;
- SIGNAL reg_io_ddr_miso : t_mem_miso;
BEGIN
-----------------------------------------------------------------------------
@@ -544,6 +537,11 @@ BEGIN
reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
+ ram_diag_bg_ddr_mosi => ram_diag_bg_ddr_mosi,
+ ram_diag_bg_ddr_miso => ram_diag_bg_ddr_miso,
+ reg_diag_bg_ddr_mosi => reg_diag_bg_ddr_mosi,
+ reg_diag_bg_ddr_miso => reg_diag_bg_ddr_miso,
+
-- dp_offload_tx
reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
@@ -567,6 +565,8 @@ BEGIN
reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
+ reg_bsn_monitor_ddr_mosi => reg_bsn_monitor_ddr_mosi,
+ reg_bsn_monitor_ddr_miso => reg_bsn_monitor_ddr_miso,
-- databuffer
ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
@@ -579,6 +579,11 @@ BEGIN
reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
+ ram_diag_data_buf_ddr_mosi => ram_diag_data_buf_ddr_mosi,
+ ram_diag_data_buf_ddr_miso => ram_diag_data_buf_ddr_miso,
+ reg_diag_data_buf_ddr_mosi => reg_diag_data_buf_ddr_mosi,
+ reg_diag_data_buf_ddr_miso => reg_diag_data_buf_ddr_miso,
+
-- tr_10GbE
reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
reg_tr_10GbE_miso => reg_tr_10GbE_miso,
@@ -809,101 +814,55 @@ BEGIN
END GENERATE;
--- u_reorder: ENTITY reorder_lib.reorder_transpose
--- GENERIC MAP (
--- g_nof_streams => c_nof_streams_ddr,
--- g_in_dat_w => c_data_w_32,
--- g_ena_pre_transp => FALSE,
--- g_use_complex => FALSE,
--- g_reorder_seq => c_reorder_seq_same
--- )
--- PORT MAP (
--- mm_rst => mm_rst,
--- mm_clk => mm_clk,
--- dp_clk => dp_clk,
--- dp_rst => dp_rst,
--- -- ST sinks from BG
--- snk_out_arr => block_gen_src_in_arr(c_nof_streams-1 downto c_nof_streams_eth), -- -2
--- snk_in_arr => block_gen_src_out_arr(c_nof_streams-1 downto c_nof_streams_eth), -- -2
--- -- ST source to DB
--- src_in_arr => (OTHERS=> c_dp_siso_rdy),
--- src_out_arr => diag_data_buf_snk_in_arr(c_nof_streams-1 downto c_nof_streams_eth), -- -2
--- -- Memory Mapped
--- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
--- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
--- -- Control interface to the external memory
--- dvr_mosi => ddr_ctlr_mosi_arr(0),
--- dvr_miso => ddr_ctlr_miso_arr(0),
--- -- Data interface to the external memory
--- to_mem_src_out => to_mem_sosi,
--- to_mem_src_in => to_mem_siso,
--- from_mem_snk_in => from_mem_sosi,
--- from_mem_snk_out => from_mem_siso
--- );
---
--- ------------------------------------------------------------------------------
--- -- DDR3 MODULE 0,1
--- ------------------------------------------------------------------------------
--- no_MB_I : IF g_use_MB_I = 0 GENERATE
--- --reg_ddr3_miso_arr(0) <= c_mem_miso_rst;
--- --reg_diagnostics_miso_arr(0) <= c_mem_miso_rst;
--- END GENERATE;
---
--- gen_MB_I : IF g_use_MB_I = 1 GENERATE
--- u_mms_ddr3_i: ENTITY io_ddr_lib.io_ddr
--- GENERIC MAP (
--- g_technology => g_technology,
--- g_tech_ddr => c_ddr_master,
--- g_wr_data_w => c_st_dat_w,
--- g_rd_data_w => c_st_dat_w
--- )
--- PORT MAP (
--- mm_clk => mm_clk,
--- mm_rst => mm_rst,
---
--- reg_io_ddr_mosi => reg_io_ddr_mosi,
--- reg_io_ddr_miso => reg_io_ddr_miso,
---
--- ctlr_ref_clk => dp_clk,
--- ctlr_ref_rst => dp_rst,
---
--- ctlr_clk_out => ddr_ctlr_clk(0),
--- ctlr_clk_in => ddr_ctlr_clk(0),
---
--- ctlr_rst_out => ddr_ctlr_rst(0),
--- ctlr_rst_in => ddr_ctlr_rst(0),
---
--- dvr_clk => dp_clk,
--- dvr_rst => dp_rst,
---
--- dvr_mosi => ddr_ctlr_mosi_arr(0),
--- dvr_miso => ddr_ctlr_miso_arr(0),
---
--- wr_clk => dp_clk,
--- wr_rst => dp_rst,
---
--- wr_sosi => to_mem_sosi,
--- wr_siso => to_mem_siso,
---
--- rd_clk => dp_clk,
--- rd_rst => dp_rst,
---
--- rd_sosi => from_mem_sosi,
--- rd_siso => from_mem_siso,
---
--- term_ctrl_out => OPEN,
--- term_ctrl_in => OPEN,
---
--- phy3_in => MB_I_IN,
--- phy3_io => MB_I_IO,
--- phy3_ou => MB_I_OU
--- );
--- END GENERATE;
---
- -----------------------------------------------------------------------------
- -- Node function
- -----------------------------------------------------------------------------
- -- Insert node_[design_name] here
+ u_ddr_stream_test : ENTITY work.ddr_stream_test
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_ddr,
+ g_data_w => c_data_w_32,
+ g_bg_block_size => c_bg_block_size,
+ g_bg_gapsize => c_bg_gapsize,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_tech_ddr => c_ddr_master,
+ g_reorder_seq => c_reorder_seq_same,
+ g_ena_pre_transp => FALSE
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- blockgen mm
+ reg_diag_bg_mosi => reg_diag_bg_ddr_mosi,
+ reg_diag_bg_miso => reg_diag_bg_ddr_miso,
+ ram_diag_bg_mosi => ram_diag_bg_ddr_mosi,
+ ram_diag_bg_miso => ram_diag_bg_ddr_miso,
+
+ -- bsn
+ reg_bsn_monitor_mosi => reg_bsn_monitor_ddr_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_ddr_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_ddr_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_ddr_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_ddr_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_ddr_miso,
+
+ -- IO DDR register map
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- Reorder transpose
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU
+ );
END str;
diff --git a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
index 84766e57e37893502bfb7e655c4ff21dd39d2c47..4e85d15d7a7d259ac7d503c098b6579849845b9f 100644
--- a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2012
+-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
@@ -42,13 +42,16 @@
-- > python $UPE/peripherals/util_ppsh.py --unb 0 --bn 3 -n 1 -v 5 --sim
--
-LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib, technology_lib, tech_ddr_lib;
+LIBRARY ip_stratixiv_ddr3_mem_model_lib;
+
+LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib, io_ddr_lib, technology_lib, tech_ddr_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_mem_model_component_pkg.ALL;
ENTITY tb_unb1_test IS
GENERIC (
@@ -72,6 +75,8 @@ ARCHITECTURE tb OF tb_unb1_test IS
CONSTANT c_sa_clk_period : TIME := 6.4 ns;
CONSTANT c_pps_period : NATURAL := 1000;
+ CONSTANT c_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
+
-- DUT
SIGNAL clk : STD_LOGIC := '0';
SIGNAL pps : STD_LOGIC := '0';
@@ -101,6 +106,11 @@ ARCHITECTURE tb OF tb_unb1_test IS
SIGNAL si_fn_lpbk_2 : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL si_fn_lpbk_3 : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ -- Signals to interface with the DDR3 memory model.
+ SIGNAL phy_in : t_tech_ddr3_phy_in;
+ SIGNAL phy_io : t_tech_ddr3_phy_io;
+ SIGNAL phy_ou : t_tech_ddr3_phy_ou;
+
-- Model I2C sensor slaves as on the UniBoard
CONSTANT c_fpga_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000"; -- MAX1618 address LOW LOW
CONSTANT c_fpga_temp : INTEGER := 60;
@@ -189,13 +199,26 @@ BEGIN
BN_BI_2_TX => OPEN,
BN_BI_2_RX => (OTHERS=>'0'),
BN_BI_3_TX => OPEN,
- BN_BI_3_RX => (OTHERS=>'0')
+ BN_BI_3_RX => (OTHERS=>'0'),
- --MB_I_IN(0) => c_tech_ddr_phy_in_rst,
- --MB_I_IO(0) => c_tech_ddr_phy_io_rst
- --MB_I_OU(0) => OPEN --c_tech_ddr_phy_ou_rst
+ MB_I_IN => phy_in,
+ MB_I_IO => phy_io,
+ MB_I_OU => phy_ou
);
+ ------------------------------------------------------------------------------
+ -- DDR3 memory model
+ ------------------------------------------------------------------------------
+ u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
+ GENERIC MAP (
+ g_tech_ddr => c_ddr
+ )
+ PORT MAP (
+ mem3_in => phy_ou,
+ mem3_io => phy_io,
+ mem3_ou => phy_in
+ );
+
------------------------------------------------------------------------------
-- UniBoard sensors
------------------------------------------------------------------------------