From ff779c76edbc45687f8099a7ea944d107be76943 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Wed, 2 Nov 2022 14:27:57 +0100
Subject: [PATCH] Accept raw or quantized input subbands. Use pipelining for
 requantize to W_crosslet width.

---
 .../sdp/src/vhdl/node_sdp_correlator.vhd      | 30 +++++++++++--------
 1 file changed, 18 insertions(+), 12 deletions(-)

diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
index f62137fba3..fcab7aaaea 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -42,9 +42,11 @@ USE work.sdp_pkg.ALL;
 
 ENTITY node_sdp_correlator IS
   GENERIC (
-    g_sim            : BOOLEAN := FALSE;
-    g_sim_sdp        : t_sdp_sim := c_sdp_sim;
-    g_P_sq           : NATURAL := c_sdp_P_sq
+    g_sim                    : BOOLEAN := FALSE;
+    g_sim_sdp                : t_sdp_sim := c_sdp_sim;
+    g_P_sq                   : NATURAL := c_sdp_P_sq;
+    g_subband_raw_dat_w      : NATURAL := c_sdp_W_subband;
+    g_subband_raw_fraction_w : NATURAL := 0
   );
   PORT (
     dp_clk        : IN  STD_LOGIC;
@@ -138,22 +140,26 @@ ARCHITECTURE str OF node_sdp_correlator IS
   SIGNAL prev_crosslets_info_rec       : t_sdp_crosslets_info;
   SIGNAL nof_crosslets_reg             : STD_LOGIC_VECTOR(c_sdp_nof_crosslets_reg_w-1 DOWNTO 0);
   SIGNAL nof_crosslets                 : STD_LOGIC_VECTOR(c_sdp_nof_crosslets_reg_w-1 DOWNTO 0);
+
 BEGIN
+
   ---------------------------------------------------------------
   -- Requantize 18b to 16b 
   ---------------------------------------------------------------
   gen_requantize : FOR I IN 0 TO c_sdp_P_pfb-1 GENERATE
     u_dp_requantize : ENTITY dp_lib.dp_requantize
     GENERIC MAP (
-      g_complex            => TRUE,
-      g_representation     => "SIGNED",
-      g_lsb_w              => 0,
-      g_lsb_round          => TRUE,
-      g_lsb_round_clip     => FALSE,
-      g_msb_clip           => TRUE,
-      g_msb_clip_symmetric => FALSE,
-      g_in_dat_w           => c_sdp_W_subband,
-      g_out_dat_w          => c_sdp_W_crosslet
+      g_complex             => TRUE,
+      g_representation      => "SIGNED",
+      g_lsb_w               => g_subband_raw_fraction_w,
+      g_lsb_round           => TRUE,  -- round subband fraction
+      g_lsb_round_clip      => FALSE,
+      g_msb_clip            => TRUE,  -- clip subband overflow
+      g_msb_clip_symmetric  => FALSE,
+      g_pipeline_remove_lsb => 1,
+      g_pipeline_remove_msb => 1,
+      g_in_dat_w            => g_subband_raw_dat_w,
+      g_out_dat_w           => c_sdp_W_crosslet
     )
     PORT MAP(
       rst => dp_rst,
-- 
GitLab