From ff37fc544c2cbdcb44809e6f6859d254289cda1d Mon Sep 17 00:00:00 2001
From: Jonathan Hargreaves <hargreaves@jive.eu>
Date: Fri, 21 Feb 2020 10:36:46 +0100
Subject: [PATCH] Remove incorrectly named file. Use lofar2_unb2b_adc_lib in
revisions
---
.../lofar2_unb2b_adc_full/hdllib.cfg | 8 +-
.../lofar2_unb2b_adc_full.vhd | 4 +-
.../tb_lofar2_adc_unb2b_full.vhd | 167 ------------------
.../lofar2_unb2b_adc_one_node/hdllib.cfg | 8 +-
.../lofar2_unb2b_adc_one_node.vhd | 4 +-
5 files changed, 12 insertions(+), 179 deletions(-)
delete mode 100644 applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_adc_unb2b_full.vhd
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
index d38ba1fec4..768c2d6fb3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
@@ -5,10 +5,10 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
- ../../src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
- ../../src/vhdl/lofar2_unb2b_adc_pkg.vhd
- ../../src/vhdl/mmm_lofar2_unb2b_adc.vhd
- ../../src/vhdl/lofar2_unb2b_adc.vhd
+ # ../../src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
+ # ../../src/vhdl/lofar2_unb2b_adc_pkg.vhd
+ # ../../src/vhdl/mmm_lofar2_unb2b_adc.vhd
+ # ../../src/vhdl/lofar2_unb2b_adc.vhd
lofar2_unb2b_adc_full.vhd
test_bench_files =
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
index 90ae0d564a..e810bce975 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -85,7 +85,7 @@ ARCHITECTURE str OF lofar2_unb2b_adc_full IS
BEGIN
- u_revision : ENTITY work.lofar2_unb2b_adc
+ u_revision : ENTITY lofar2_unb2b_adc_lib.lofar2_unb2b_adc
GENERIC MAP (
g_design_name => g_design_name,
g_design_note => g_design_note,
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_adc_unb2b_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_adc_unb2b_full.vhd
deleted file mode 100644
index 0d7d95d171..0000000000
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_adc_unb2b_full.vhd
+++ /dev/null
@@ -1,167 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2018
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Author: Jonathan Hargreaves
--- Purpose: Tb to show that lofar2_unb2b_adc_full can simulate
--- Description:
--- Must use c_sim = TRUE to speed up simulation
--- This is a compile-only test bench
--- Usage:
--- Load sim # check that design can load in vsim
--- > as 10 # check that the hierarchy for g_design_name is complete
--- > run -a # check that design can simulate some us without error
-
-LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE common_lib.common_pkg.ALL;
-USE unb2b_board_lib.unb2b_board_pkg.ALL;
-USE common_lib.tb_common_pkg.ALL;
-
-ENTITY tb_lofar2_unb2b_adc_full IS
-END tb_lofar2_unb2b_adc_full;
-
-ARCHITECTURE tb OF tb_lofar2_unb2b_adc_full IS
-
- CONSTANT c_sim : BOOLEAN := TRUE;
- CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
- CONSTANT c_node_nr : NATURAL := 0; -- Back node 3
- CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
- CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
- CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
-
- CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
- CONSTANT c_ext_clk_period : TIME := 5 ns;
- CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
- CONSTANT c_pps_period : NATURAL := 1000;
-
- -- Tb
- SIGNAL tb_end : STD_LOGIC := '0';
- SIGNAL sim_done : STD_LOGIC := '0';
-
- -- DUT
- SIGNAL ext_clk : STD_LOGIC := '0';
- SIGNAL pps : STD_LOGIC := '0';
- SIGNAL pps_rst : STD_LOGIC := '0';
-
- SIGNAL WDI : STD_LOGIC;
- SIGNAL INTA : STD_LOGIC;
- SIGNAL INTB : STD_LOGIC;
-
- SIGNAL eth_clk : STD_LOGIC := '0';
- SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
- SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
-
- SIGNAL sens_scl : STD_LOGIC;
- SIGNAL sens_sda : STD_LOGIC;
- SIGNAL pmbus_scl : STD_LOGIC;
- SIGNAL pmbus_sda : STD_LOGIC;
-
- -- back transceivers
- SIGNAL bck_rx : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
- SIGNAL bck_ref_clk : STD_LOGIC := '1';
-
- -- jesd204b syncronization signals
- SIGNAL jesd204b_sysref : STD_LOGIC;
- SIGNAL jesd204b_sync : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
-
-
-BEGIN
-
-
- ----------------------------------------------------------------------------
- -- System setup
- ----------------------------------------------------------------------------
- ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
- eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
- bck_ref_clk <= NOT bck_ref_clk AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
-
- INTA <= 'H'; -- pull up
- INTB <= 'H'; -- pull up
-
- sens_scl <= 'H'; -- pull up
- sens_sda <= 'H'; -- pull up
- pmbus_scl <= 'H'; -- pull up
- pmbus_sda <= 'H'; -- pull up
-
- ------------------------------------------------------------------------------
- -- External PPS
- ------------------------------------------------------------------------------
- proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
- jesd204b_sysref <= pps;
-
- ------------------------------------------------------------------------------
- -- DUT
- ------------------------------------------------------------------------------
- u_lofar_unb2b_adc_full : ENTITY work.lofar2_unb2b_adc_full
- GENERIC MAP (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- PORT MAP (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- BCK_RX => bck_rx,
- BCK_REF_CLK => bck_ref_clk,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC => jesd204b_sync
- );
-
-
- ------------------------------------------------------------------------------
- -- Simulation end
- ------------------------------------------------------------------------------
- sim_done <= '0', '1' AFTER 1 us;
-
- proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
-
-END tb;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg
index 707fde2968..a26f0fb9ee 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg
@@ -5,10 +5,10 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
- ../../src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
- ../../src/vhdl/lofar2_unb2b_adc_pkg.vhd
- ../../src/vhdl/mmm_lofar2_unb2b_adc.vhd
- ../../src/vhdl/lofar2_unb2b_adc.vhd
+ # ../../src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
+ # ../../src/vhdl/lofar2_unb2b_adc_pkg.vhd
+ # ../../src/vhdl/mmm_lofar2_unb2b_adc.vhd
+ # ../../src/vhdl/lofar2_unb2b_adc.vhd
lofar2_unb2b_adc_one_node.vhd
test_bench_files =
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
index f3f27d30c2..fb8620a8e5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -85,7 +85,7 @@ ARCHITECTURE str OF lofar2_unb2b_adc_one_node IS
BEGIN
- u_revision : ENTITY work.lofar2_unb2b_adc
+ u_revision : ENTITY lofar2_unb2b_adc_lib.lofar2_unb2b_adc
GENERIC MAP (
g_design_name => g_design_name,
g_design_note => g_design_note,
--
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