diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_tp_bg/tb_apertif_unb1_fn_beamformer_tp_bg.vhd b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_tp_bg/tb_apertif_unb1_fn_beamformer_tp_bg.vhd
index df21cd03c3dec547a6e2dda79093dd64d4628f82..8318f8f8513c21975b14b5b7c1a00d686b23bc1e 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_tp_bg/tb_apertif_unb1_fn_beamformer_tp_bg.vhd
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_tp_bg/tb_apertif_unb1_fn_beamformer_tp_bg.vhd
@@ -78,6 +78,9 @@ ARCHITECTURE tb OF tb_apertif_unb1_fn_beamformer_tp_bg IS
   SIGNAL sens_scl            : STD_LOGIC;
   SIGNAL sens_sda            : STD_LOGIC;
   SIGNAL si_fn_0_tx          : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS => '0');  
+  SIGNAL si_fn_1_tx          : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS => '0');  
+  SIGNAL si_fn_2_tx          : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS => '0');  
+  SIGNAL si_fn_3_tx          : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS => '0');  
   SIGNAL fn_bn_0_tx          : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS => '0');  
   
   -- Signals to interface with the DDR3 memory model.
@@ -149,9 +152,15 @@ BEGIN
   
       -- Serial I/O
       SI_FN_0_RX  => si_fn_0_tx, --  : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-      SI_FN_1_RX  => si_fn_0_tx, --  : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-      SI_FN_2_RX  => si_fn_0_tx, --  : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-      SI_FN_3_RX  => si_fn_0_tx, --  : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+      SI_FN_1_RX  => si_fn_1_tx, --  : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+      SI_FN_2_RX  => si_fn_2_tx, --  : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+      SI_FN_3_RX  => si_fn_3_tx, --  : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+
+      SI_FN_0_TX  => si_fn_0_tx, --  : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+      SI_FN_1_TX  => si_fn_1_tx, --  : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+      SI_FN_2_TX  => si_fn_2_tx, --  : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+      SI_FN_3_TX  => si_fn_3_tx, --  : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+
       
       MB_I_in     => phy_in, 
       MB_I_io     => phy_io,