diff --git a/libraries/io/eth/hdllib.cfg b/libraries/io/eth/hdllib.cfg
index b363c0a31a2bf780c579cec2081824db01c2cd9b..1a3baef26f878fdac3ff1e0ffbcdbafd9d499889 100644
--- a/libraries/io/eth/hdllib.cfg
+++ b/libraries/io/eth/hdllib.cfg
@@ -32,6 +32,14 @@ test_bench_files =
tb/vhdl/tb_eth_ihl_to_20.vhd
tb/vhdl/tb_tb_tb_eth_regression.vhd
+regression_test_vhdl =
+ tb/vhdl/tb_eth_checksum.vhd
+ tb/vhdl/tb_eth_crc_ctrl.vhd
+ tb/vhdl/tb_eth_hdr.vhd
+ tb/vhdl/tb_eth_udp_offload.vhd
+ tb/vhdl/tb_eth_ihl_to_20.vhd
+ tb/vhdl/tb_tb_eth.vhd
+
[modelsim_project_file]
diff --git a/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd b/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd
index 5892b924a1527f2472aa5e7ea5c49d36f0172a39..86527014f8420484d39d6edf38b0fb6007c0b2d8 100644
--- a/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd
@@ -47,6 +47,7 @@ ARCHITECTURE tb OF tb_tb_eth IS
CONSTANT c_tb_end_vec : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS=>'1');
SIGNAL tb_end_vec : STD_LOGIC_VECTOR(15 DOWNTO 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
+ SIGNAL tb_end : STD_LOGIC := '0';
BEGIN
@@ -69,9 +70,12 @@ BEGIN
u_use_udp : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, FALSE, FALSE, c_tb_tech_tse_data_type_udp ) PORT MAP (tb_end_vec(4));
u_use_udp_flush : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, TRUE, FALSE, c_tb_tech_tse_data_type_udp ) PORT MAP (tb_end_vec(5));
+ tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec ELSE '0';
+
p_tb_end : PROCESS
BEGIN
- WAIT UNTIL tb_end_vec=c_tb_end_vec;
+ WAIT UNTIL tb_end='1';
+ WAIT FOR 1 ns;
REPORT "Multi tb simulation finished." SEVERITY FAILURE;
WAIT;
END PROCESS;
diff --git a/libraries/io/i2c/hdllib.cfg b/libraries/io/i2c/hdllib.cfg
index b48f36ef81747a103b9276e4e5671c55e9e3853d..7bf5a7a11e84e40bd795725c62cd25114394e3ca 100644
--- a/libraries/io/i2c/hdllib.cfg
+++ b/libraries/io/i2c/hdllib.cfg
@@ -42,8 +42,13 @@ test_bench_files =
tb/vhdl/tb_i2c_master.vhd
tb/vhdl/tb_avs_i2c_master.vhd
tb/vhdl/tb_i2c_commander.vhd
+ #tb/vhdl/tb_i2c_commander_unb2_pmbus.vhd
+ #tb/vhdl/tb_i2c_commander_unb2_sens.vhd
tb/vhdl/tb_tb_i2c_commander.vhd
+regression_test_vhdl =
+ tb/vhdl/tb_i2c_master.vhd
+ tb/vhdl/tb_tb_i2c_commander.vhd
[modelsim_project_file]
modelsim_copy_files =
diff --git a/libraries/io/i2c/tb/vhdl/tb_tb_i2c_commander.vhd b/libraries/io/i2c/tb/vhdl/tb_tb_i2c_commander.vhd
index eb6eae507d44f30154d4fefb05985e87fbf9f440..e286a1599fb8bf5309ec1d061e325f5aa290f95b 100644
--- a/libraries/io/i2c/tb/vhdl/tb_tb_i2c_commander.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_tb_i2c_commander.vhd
@@ -35,7 +35,7 @@ END tb_tb_i2c_commander;
ARCHITECTURE tb OF tb_tb_i2c_commander IS
-
+ SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
BEGIN
-- g_board : STRING := "adu" -- else default to "unb"
diff --git a/libraries/io/mdio/hdllib.cfg b/libraries/io/mdio/hdllib.cfg
index 378f3569b4467b4ebec8da18f955e31b8e9cc164..726b074d3ae2d27094ac05f072b63a707a37133f 100644
--- a/libraries/io/mdio/hdllib.cfg
+++ b/libraries/io/mdio/hdllib.cfg
@@ -21,6 +21,12 @@ test_bench_files =
tb/vhdl/tb_mdio_phy_reg.vhd
tb/vhdl/tb_mdio_phy_ctlr.vhd
+regression_test_vhdl =
+ tb/vhdl/tb_mdio.vhd
+ tb/vhdl/tb_mdio_phy.vhd
+ tb/vhdl/tb_mdio_phy_reg.vhd
+ tb/vhdl/tb_mdio_phy_ctlr.vhd
+
[modelsim_project_file]
diff --git a/libraries/io/mdio/tb/vhdl/tb_mdio.vhd b/libraries/io/mdio/tb/vhdl/tb_mdio.vhd
index ec271b22793b6211bcfabf05f3e01ae9f9956ad8..207b8a8a305ef781101d72818b0f8ec78c0ab7cd 100644
--- a/libraries/io/mdio/tb/vhdl/tb_mdio.vhd
+++ b/libraries/io/mdio/tb/vhdl/tb_mdio.vhd
@@ -52,6 +52,7 @@ ARCHITECTURE tb OF tb_mdio IS
CONSTANT c_phy_addr : STD_LOGIC_VECTOR(c_halfword_w-1 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(16#A001#, c_halfword_w));
CONSTANT c_phy_data : STD_LOGIC_VECTOR(c_halfword_w-1 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(16#D001#, c_halfword_w));
+ SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL clk : STD_LOGIC := '1';
SIGNAL rst : STD_LOGIC;
@@ -88,7 +89,7 @@ BEGIN
-- run 50 us
- clk <= NOT clk AFTER clk_period/2;
+ clk <= NOT clk OR tb_end AFTER clk_period/2;
rst <= '1', '0' AFTER clk_period*3;
mdio <= 'H'; -- pull up
@@ -176,9 +177,9 @@ BEGIN
IF phy_readdata=c_phy_data THEN
REPORT "Write MDIO slave reg and readback went OK" SEVERITY NOTE;
ELSE
- REPORT "Write MDIO slave reg and readback went wrong" SEVERITY NOTE;
+ REPORT "Write MDIO slave reg and readback went wrong" SEVERITY ERROR;
END IF;
-
+ tb_end <= '1';
WAIT;
END PROCESS;
diff --git a/libraries/io/mdio/tb/vhdl/tb_mdio_phy.vhd b/libraries/io/mdio/tb/vhdl/tb_mdio_phy.vhd
index 79396f8c05c4107ae1002e9d84238bb8098d6e62..f0490997f7a32e220150340210436ae52cbc19d3 100644
--- a/libraries/io/mdio/tb/vhdl/tb_mdio_phy.vhd
+++ b/libraries/io/mdio/tb/vhdl/tb_mdio_phy.vhd
@@ -52,6 +52,7 @@ ARCHITECTURE tb OF tb_mdio_phy IS
CONSTANT c_phy_addr : STD_LOGIC_VECTOR(c_halfword_w-1 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(16#A001#, c_halfword_w));
CONSTANT c_phy_data : STD_LOGIC_VECTOR(c_halfword_w-1 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(16#D001#, c_halfword_w));
+ SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL clk : STD_LOGIC := '1';
SIGNAL rst : STD_LOGIC;
@@ -78,7 +79,7 @@ BEGIN
-- run 50 us
- clk <= NOT clk AFTER clk_period/2;
+ clk <= NOT clk OR tb_end AFTER clk_period/2;
rst <= '1', '0' AFTER clk_period*3;
mdio <= 'H'; -- pull up
@@ -135,7 +136,7 @@ BEGIN
IF rx_dat=c_phy_data THEN
REPORT "Write MDIO slave reg and readback went OK" SEVERITY NOTE;
ELSE
- REPORT "Write MDIO slave reg and readback went wrong" SEVERITY NOTE;
+ REPORT "Write MDIO slave reg and readback went wrong" SEVERITY ERROR;
END IF;
----------------------------------------------------------------------------
@@ -171,9 +172,10 @@ BEGIN
IF rx_dat=c_phy_data THEN
REPORT "Write MDIO slave reg and readback went OK" SEVERITY NOTE;
ELSE
- REPORT "Write MDIO slave reg and readback went wrong" SEVERITY NOTE;
+ REPORT "Write MDIO slave reg and readback went wrong" SEVERITY ERROR;
END IF;
+ tb_end <= '1';
WAIT;
END PROCESS;
diff --git a/libraries/io/mdio/tb/vhdl/tb_mdio_phy_ctlr.vhd b/libraries/io/mdio/tb/vhdl/tb_mdio_phy_ctlr.vhd
index 6ccc53ed1fb26f967899fece05d49da36cdfdb1e..43f0d7ebd56c0d0b275fab098affd98d57dd0679 100644
--- a/libraries/io/mdio/tb/vhdl/tb_mdio_phy_ctlr.vhd
+++ b/libraries/io/mdio/tb/vhdl/tb_mdio_phy_ctlr.vhd
@@ -102,7 +102,7 @@ BEGIN
IF rx_dat=c_phy_data THEN
REPORT "Write MDIO slave reg and readback went OK" SEVERITY NOTE;
ELSE
- REPORT "Write MDIO slave reg and readback went wrong" SEVERITY NOTE;
+ REPORT "Write MDIO slave reg and readback went wrong" SEVERITY ERROR;
END IF;
tb_end <= '1';
diff --git a/libraries/io/mdio/tb/vhdl/tb_mdio_phy_reg.vhd b/libraries/io/mdio/tb/vhdl/tb_mdio_phy_reg.vhd
index c706f7eac9bb40e92b2f064cbed468713f2b3fe7..d1331e6e32dfeda6cf667a869e608ade4c1ebafa 100644
--- a/libraries/io/mdio/tb/vhdl/tb_mdio_phy_reg.vhd
+++ b/libraries/io/mdio/tb/vhdl/tb_mdio_phy_reg.vhd
@@ -63,6 +63,7 @@ ARCHITECTURE tb OF tb_mdio_phy_reg IS
CONSTANT c_ofs_done : NATURAL := 3;
CONSTANT c_ofs_done_ack_evt : NATURAL := 4;
+ SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL clk : STD_LOGIC := '1';
SIGNAL rst : STD_LOGIC;
@@ -96,7 +97,7 @@ BEGIN
-- Run 25us
- clk <= NOT clk AFTER clk_period/2;
+ clk <= NOT clk OR tb_end AFTER clk_period/2;
rst <= '1', '0' AFTER clk_period*3;
mdio <= 'H'; -- pull up
@@ -172,9 +173,10 @@ BEGIN
IF phy_readdata=c_phy_data THEN
REPORT "Write MDIO slave reg and readback went OK" SEVERITY NOTE;
ELSE
- REPORT "Write MDIO slave reg and readback went wrong" SEVERITY FAILURE;
+ REPORT "Write MDIO slave reg and readback went wrong" SEVERITY ERROR;
END IF;
-
+
+ tb_end <= '1';
WAIT;
END PROCESS;
diff --git a/libraries/io/tr_10GbE/hdllib.cfg b/libraries/io/tr_10GbE/hdllib.cfg
index 7ec28c31fd53e7de737459c82cbac598e256b3c6..3638df5136d0ccf6545f030337884e9b6d8d3d52 100644
--- a/libraries/io/tr_10GbE/hdllib.cfg
+++ b/libraries/io/tr_10GbE/hdllib.cfg
@@ -11,6 +11,9 @@ test_bench_files =
tb/vhdl/tb_tr_10GbE.vhd
tb/vhdl/tb_tb_tr_10GbE.vhd
+regression_test_vhdl =
+ tb/vhdl/tb_tb_tr_10GbE.vhd
+
[modelsim_project_file]
diff --git a/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd b/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
index 04ad76a309d24ac814410eb5b6e8aa723572ba97..1c4b56a1601f8bda4a6e91393fee7cd21ac91418 100644
--- a/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
@@ -45,6 +45,7 @@ ARCHITECTURE tb OF tb_tb_tr_10GbE IS
CONSTANT c_tb_end_vec : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS=>'1');
SIGNAL tb_end_vec : STD_LOGIC_VECTOR(7 DOWNTO 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
+ SIGNAL tb_end : STD_LOGIC := '0';
BEGIN
-- g_technology : NATURAL := c_tech_select_default;
@@ -67,9 +68,12 @@ BEGIN
u_tr_10GbE_nof_channels_is_2 : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5 ns, 0, 2, "TX_RX", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(5));
u_tr_10GbE_sim_level_is_1 : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 5 ns, 1, 1, "TX_RX", c_644, c_156, c_data_type, TRUE) PORT MAP (tb_end_vec(6));
+ tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec ELSE '0';
+
p_tb_end : PROCESS
BEGIN
- WAIT UNTIL tb_end_vec=c_tb_end_vec;
+ WAIT UNTIL tb_end='1';
+ WAIT FOR 1 ns;
REPORT "Multi tb simulation finished." SEVERITY FAILURE;
WAIT;
END PROCESS;