diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station.sdc b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station.sdc
index 82c0df011c95f6503ba618f2fbe419b37c5765ab..ce015b6d6219689533c9506e2b06f5c25c83e9ef 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station.sdc
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station.sdc
@@ -86,8 +86,8 @@ set_clock_groups -asynchronous -group [get_clocks pll_clk400]
#set_clock_groups -asynchronous -group [get_clocks {*mac_clock*xcvr_fpll_a10_0|outclk0}]
#set_clock_groups -asynchronous -group [get_clocks {*dp_clk*xcvr_fpll_a10_0|outclk0}]
#set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk1}]
-set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk3}]
-
+set_clock_groups -asynchronous -group [get_clocks {*_board_clk125_pll|*xcvr_fpll_a10_0|outclk2}]
+set_clock_groups -asynchronous -group [get_clocks {*_board_clk125_pll|*xcvr_fpll_a10_0|outclk3}]
set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_native_insts[*]|rx_pma_clk}]
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station.sdc b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station.sdc
index b6e28ef53d3607eac35683c106700762c43cb6a1..6f0327b42261592e1a10b79da8d73447d305b59e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station.sdc
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station.sdc
@@ -86,8 +86,8 @@ set_clock_groups -asynchronous -group [get_clocks pll_clk400]
#set_clock_groups -asynchronous -group [get_clocks {*mac_clock*xcvr_fpll_a10_0|outclk0}]
#set_clock_groups -asynchronous -group [get_clocks {*dp_clk*xcvr_fpll_a10_0|outclk0}]
#set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk1}]
-set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk3}]
-
+set_clock_groups -asynchronous -group [get_clocks {*_board_clk125_pll|*xcvr_fpll_a10_0|outclk2}]
+set_clock_groups -asynchronous -group [get_clocks {*_board_clk125_pll|*xcvr_fpll_a10_0|outclk3}]
set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_native_insts[*]|rx_pma_clk}]
diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index 3931d107704f9417e9ce3156c27593ebe36fb8a3..30edfe8dc9e4010bca8fa7c5190940b7266eaaac 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -98,7 +98,8 @@ PACKAGE common_pkg IS
CONSTANT c_fifo_afull_margin : NATURAL := 4; -- default or minimal FIFO almost full margin
-- DSP
- CONSTANT c_dsp_mult_w : NATURAL := 18; -- Width of the embedded multipliers in Stratix IV
+ CONSTANT c_dsp_mult_w : NATURAL := 18; -- Width of the embedded multipliers in Stratix IV (and Arria 10 for 2 multipliers per DSP block)
+ CONSTANT c_dsp_mult_arria10_w : NATURAL := 27; -- Width of the embedded multipliers in Arria 10
-- TYPE DECLARATIONS --------------------------------------------------------
TYPE t_boolean_arr IS ARRAY (INTEGER RANGE <>) OF BOOLEAN; -- INTEGER left index starts default at -2**31
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd
index 31822aabfeeb6eb12b843f991cdf229112c99e50..ab08dfeb93f79b36b15f944a828ccdf4555224a9 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd
@@ -22,6 +22,7 @@
library ieee, common_lib, common_mult_lib, technology_lib;
use IEEE.std_logic_1164.all;
USE technology_lib.technology_select_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
use common_lib.common_pkg.all;
entity rTwoWMul is
@@ -69,7 +70,8 @@ architecture str of rTwoWMul is
constant c_mult_extra_lat : natural := sel_a_b(c_lat>3, c_lat-3, 0); -- remaining extra pipelining in logic
constant c_mult_output_lat : natural := sel_a_b(c_lat>0, 1, 0) + c_mult_extra_lat; -- first priority use DSP pipeline output
constant c_mult_lat : natural := c_mult_input_lat + c_mult_product_lat + c_mult_adder_lat + c_mult_output_lat;
-
+ constant c_max_dsp_mult_w : natural := sel_a_b(g_technology = c_tech_stratixiv, c_dsp_mult_w, c_dsp_mult_arria10_w);
+
-- Total input to output latency
constant c_total_lat : natural := c_mult_lat + c_round_lat;
@@ -107,7 +109,7 @@ begin
-- . for c_lat >= 3 default best use the FPGA multiplier IP block.
------------------------------------------------------------------------------
- gen_rtl : if g_stage=1 or c_in_dat_w>c_dsp_mult_w or c_weight_w>c_dsp_mult_w or c_lat<c_dsp_mult_lat generate
+ gen_rtl : if g_stage=1 or c_in_dat_w>c_max_dsp_mult_w or c_weight_w>c_max_dsp_mult_w or c_lat<c_dsp_mult_lat generate
u_CmplxMul : entity common_mult_lib.common_complex_mult
generic map (
g_technology => g_technology,
@@ -135,7 +137,7 @@ begin
);
end generate;
- gen_ip : if g_stage>1 and c_in_dat_w<=c_dsp_mult_w and c_weight_w<=c_dsp_mult_w and c_lat>=c_dsp_mult_lat generate
+ gen_ip : if g_stage>1 and c_in_dat_w<=c_max_dsp_mult_w and c_weight_w<=c_max_dsp_mult_w and c_lat>=c_dsp_mult_lat generate
u_cmplx_mul : entity common_mult_lib.common_complex_mult
generic map (
g_technology => g_technology,