diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_remote_ring.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_remote_ring.vhd
index ea76ef8113e5701ef3133c9b28b61ab386cf2631..1ec7de0db3d269388ee83389ea985b8da6ebf426 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_remote_ring.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_remote_ring.vhd
@@ -78,6 +78,24 @@
-- node 78: -1 -1 -1 -1 -1 -1 1800 1599 1351 1137 938 693 472 253 -1 -1
-- node 79: -1 -1 -1 -1 -1 -1 -1 1809 1566 1344 1143 899 681 460 259 -1
--
+-- # FPGA_xst_ring_rx_latency_R (sim: c_nof_delay = 0 with sdp_crosslets_remote_v2.vhd):
+-- # 0: -1 -1 -1 -1 -1 -1 -1 -1 1604 1409 1211 1016 818 623 427 230
+-- # 1: 230 -1 -1 -1 -1 -1 -1 -1 -1 1604 1409 1211 1016 818 623 427
+-- # 2: 427 230 -1 -1 -1 -1 -1 -1 -1 -1 1604 1409 1211 1016 818 623
+-- # 3: 623 427 230 -1 -1 -1 -1 -1 -1 -1 -1 1604 1409 1211 1016 818
+-- # 4: 818 623 427 230 -1 -1 -1 -1 -1 -1 -1 -1 1604 1409 1211 1016
+-- # 5: 1016 818 623 427 230 -1 -1 -1 -1 -1 -1 -1 -1 1604 1409 1211
+-- # 6: 1211 1016 818 623 427 230 -1 -1 -1 -1 -1 -1 -1 -1 1604 1409
+-- # 7: 1409 1211 1016 818 623 427 230 -1 -1 -1 -1 -1 -1 -1 -1 1604
+-- # 8: 1604 1409 1211 1016 818 623 427 230 -1 -1 -1 -1 -1 -1 -1 -1
+-- # 9: -1 1604 1409 1211 1016 818 623 427 230 -1 -1 -1 -1 -1 -1 -1
+-- # 10: -1 -1 1604 1409 1211 1016 818 623 427 230 -1 -1 -1 -1 -1 -1
+-- # 11: -1 -1 -1 1604 1409 1211 1016 818 623 427 230 -1 -1 -1 -1 -1
+-- # 12: -1 -1 -1 -1 1604 1409 1211 1016 818 623 427 230 -1 -1 -1 -1
+-- # 13: -1 -1 -1 -1 -1 1604 1409 1211 1016 818 623 427 230 -1 -1 -1
+-- # 14: -1 -1 -1 -1 -1 -1 1604 1409 1211 1016 818 623 427 230 -1 -1
+-- # 15: -1 -1 -1 -1 -1 -1 -1 1604 1409 1211 1016 818 623 427 230 -1
+--
-- # FPGA_xst_ring_rx_latency_R (sim: c_nof_delay = 12):
-- # 0: -1 -1 -1 -1 -1 -1 -1 -1 1729 1533 1332 1053 856 638 442 245
-- # 1: 245 -1 -1 -1 -1 -1 -1 -1 -1 1729 1533 1332 1053 856 638 442
@@ -132,6 +150,24 @@
-- node 78: -1 -1 -1 -1 -1 -1 -1 1593 1371 1171 928 732 488 268 12 -1
-- node 79: -1 -1 -1 -1 -1 -1 -1 -1 1587 1387 1143 948 702 480 262 12
--
+-- # FPGA_xst_ring_tx_latency_R (sim: c_nof_delay = 0 with sdp_crosslets_remote_v2.vhd):
+-- # 0: 13 -1 -1 -1 -1 -1 -1 -1 -1 1415 1217 1023 824 629 434 237
+-- # 1: 237 13 -1 -1 -1 -1 -1 -1 -1 -1 1415 1217 1023 824 629 434
+-- # 2: 434 237 13 -1 -1 -1 -1 -1 -1 -1 -1 1415 1217 1023 824 629
+-- # 3: 629 434 237 13 -1 -1 -1 -1 -1 -1 -1 -1 1415 1217 1023 824
+-- # 4: 824 629 434 237 13 -1 -1 -1 -1 -1 -1 -1 -1 1415 1217 1023
+-- # 5: 1023 824 629 434 237 13 -1 -1 -1 -1 -1 -1 -1 -1 1415 1217
+-- # 6: 1217 1023 824 629 434 237 13 -1 -1 -1 -1 -1 -1 -1 -1 1415
+-- # 7: 1415 1217 1023 824 629 434 237 13 -1 -1 -1 -1 -1 -1 -1 -1
+-- # 8: -1 1415 1217 1023 824 629 434 237 13 -1 -1 -1 -1 -1 -1 -1
+-- # 9: -1 -1 1415 1217 1023 824 629 434 237 13 -1 -1 -1 -1 -1 -1
+-- # 10: -1 -1 -1 1415 1217 1023 824 629 434 237 13 -1 -1 -1 -1 -1
+-- # 11: -1 -1 -1 -1 1415 1217 1023 824 629 434 237 13 -1 -1 -1 -1
+-- # 12: -1 -1 -1 -1 -1 1415 1217 1023 824 629 434 237 13 -1 -1 -1
+-- # 13: -1 -1 -1 -1 -1 -1 1415 1217 1023 824 629 434 237 13 -1 -1
+-- # 14: -1 -1 -1 -1 -1 -1 -1 1415 1217 1023 824 629 434 237 13 -1
+-- # 15: -1 -1 -1 -1 -1 -1 -1 -1 1415 1217 1023 824 629 434 237 13
+--
-- # FPGA_xst_ring_tx_latency_R (sim: c_nof_delay = 12):
-- # 0: 12 -1 -1 -1 -1 -1 -1 -1 -1 1539 1339 1119 862 645 448 251
-- # 1: 251 12 -1 -1 -1 -1 -1 -1 -1 -1 1539 1339 1119 862 645 448
@@ -186,6 +222,24 @@
-- node 78: 1 206 430 648 868 1109 1332 1559 1772
-- node 79: 1 208 430 650 870 1109 1328 1550 1775
--
+-- # FPGA_xst_rx_align_latency_R (sim: c_nof_delay = 0 with sdp_crosslets_remote_v2.vhd):
+-- # 0: 1 235 432 628 823 1021 1216 1414 1609
+-- # 1: 1 235 432 628 823 1021 1216 1414 1609
+-- # 2: 1 235 432 628 823 1021 1216 1414 1609
+-- # 3: 1 235 432 628 823 1021 1216 1414 1609
+-- # 4: 1 235 432 628 823 1021 1216 1414 1609
+-- # 5: 1 235 432 628 823 1021 1216 1414 1609
+-- # 6: 1 235 432 628 823 1021 1216 1414 1609
+-- # 7: 1 235 432 628 823 1021 1216 1414 1609
+-- # 8: 1 235 432 628 823 1021 1216 1414 1609
+-- # 9: 1 235 432 628 823 1021 1216 1414 1609
+-- # 10: 1 235 432 628 823 1021 1216 1414 1609
+-- # 11: 1 235 432 628 823 1021 1216 1414 1609
+-- # 12: 1 235 432 628 823 1021 1216 1414 1609
+-- # 13: 1 235 432 628 823 1021 1216 1414 1609
+-- # 14: 1 235 432 628 823 1021 1216 1414 1609
+-- # 15: 1 235 432 628 823 1021 1216 1414 1609
+--
-- # FPGA_xst_rx_align_latency_R (sim: c_nof_delay = 12):
-- # 0: 1 199 396 593 810 1109 1308 1506 1702
-- # 1: 1 199 396 593 810 1109 1308 1506 1702
@@ -222,7 +276,7 @@
-- # 14: 1 217 436 653 872 1109 1326 1544 1762
-- # 15: 1 217 436 653 872 1109 1326 1544 1762
--
--- - xst_aligned_latency (SDP-ARTS HW): # FPGA_xst_aligned_latency_R (sim: c_nof_delay = 12, 25):
+-- - xst_aligned_latency (SDP-ARTS HW): # FPGA_xst_aligned_latency_R (sim: c_nof_delay = 0, 12, 25):
-- node 64: 2051 # 0: 2051
-- node 65: 2051 # 1: 2051
-- node 66: 2051 # 2: 2051
@@ -274,9 +328,13 @@ architecture tb of tb_sdp_crosslets_remote_ring is
-- Apply cable delay in tech_pll_clk_156_period units, to remain aligned with tr_10GbE sim model
-- . Choose c_cable_delay = 16 * 6.4 ~= 102 ns ~= 20 dp_clk of 5 ns, to match delay seen on HW
-- . Minimum c_cable_delay >= 12 * 6.4 = 77 ns ~= 15 dp_clk of 5 ns, else missed blocks in x_sosi
+ -- This minimum occurs when g_nof_rn > 8 and was found with g_nof_rn = 16. It happens due to
+ -- that the local crosslets are passed through ring_mux and dp_demux. This causes that the
+ -- block period of the local crosslets can vary and the there is not enough time to read all
+ -- aligned croslets. Therefore instead use sdp_crosslets_remote_v2.vhd.
-- . Maximum c_cable_delay <= 29 * 6.4 = 185 ns ~= 37 dp_clk of 5 ns, else missed blocks in x_sosi
constant c_clk_156_period : time := tech_pll_clk_156_period; -- 6.400020 ns ~= 156.25 MHz
- constant c_nof_delay : natural := 20;
+ constant c_nof_delay : natural := 0;
constant c_cable_delay : time := c_clk_156_period * c_nof_delay;
-- XST data
@@ -345,6 +403,8 @@ architecture tb of tb_sdp_crosslets_remote_ring is
signal crosslets_copi_arr : t_mem_copi_arr(c_last_rn downto 0) := (others => c_mem_copi_rst);
signal crosslets_cipo_2arr : t_crosslets_cipo_2arr(c_last_rn downto 0);
signal x_sosi_2arr : t_crosslets_sosi_2arr(c_last_rn downto 0);
+ signal x_sosi_2arr_valids : std_logic_vector(g_nof_rn * c_P_sq - 1 downto 0);
+ signal x_sosi_arr : t_dp_sosi_arr(c_last_rn downto 0);
signal x_sosi : t_dp_sosi;
-- 10GbE ring
@@ -701,7 +761,7 @@ begin
);
-- Intermediate crosslets alignment at each node
- u_sdp_crosslets_remote : entity work.sdp_crosslets_remote
+ u_sdp_crosslets_remote : entity work.sdp_crosslets_remote_v2
generic map (
g_P_sq => c_P_sq
)
@@ -746,13 +806,29 @@ begin
);
end generate; -- gen_dut
- x_sosi <= x_sosi_2arr(0)(0);
+ -- View status of x_sosi_2arr
+ p_x_sosi_2arr : process(x_sosi_2arr)
+ begin
+ for RN in 0 to c_last_rn loop
+ -- Group all x_sosi_2arr valids into one slv
+ for P in 0 to c_P_sq - 1 loop
+ x_sosi_2arr_valids(RN * c_P_sq + P) <= x_sosi_2arr(RN)(P).valid;
+ end loop;
+
+ -- Group aligned first output from all RN
+ x_sosi_arr(RN) <= x_sosi_2arr(RN)(0);
+ end loop;
+
+ -- Get aligned first output from first RN
+ x_sosi <= x_sosi_2arr(0)(0);
+ end process;
------------------------------------------------------------------------------
-- Verify crosslets at every node, to check that no packets were lost
------------------------------------------------------------------------------
p_verify_crosslets : process(dp_clk)
begin
+ -- Verify that data /= 0, so no lost data = 0 insertion
for RN in 0 to c_last_rn Loop
for P in 0 to c_P_sq - 1 loop
if x_sosi_2arr(RN)(P).valid = '1' then
@@ -761,6 +837,13 @@ begin
end if;
end loop;
end loop;
+
+ -- Verify that all aligned outputs on all RN are valid at the same time
+ if x_sosi.valid = '1' then
+ assert vector_and(x_sosi_2arr_valids) = '1' report "Missing aligned output valid" severity error;
+ else
+ assert vector_and(x_sosi_2arr_valids) = '0' report "Unexpected aligned output valid" severity error;
+ end if;
end process;
------------------------------------------------------------------------------