diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd index 48f28d1c1e3e1a741ffb601e842917728806efb1..313f594ff138593c1a1fad09567fea3104952b33 100644 --- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd +++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_address_counter.vhd @@ -83,51 +83,39 @@ BEGIN q_reg <= d_reg WHEN rising_edge(clk); -- Increments the address each time in_sosi.valid = '1', if address = c_max_adr the address is reset to 0. - p_adr : PROCESS(rst, in_sosi.valid) + p_adr : PROCESS(rst, in_sosi, in_of, q_reg) - VARIABLE v : t_reg := c_t_reg_init; + VARIABLE v : t_reg; BEGIN + v := q_reg; v.out_mosi.wrdata(c_data_w-1 DOWNTO 0) := in_sosi.data(c_data_w - 1 DOWNTO 0); v.out_mosi.wr := in_sosi.valid; v.out_of := in_of; - IF rst = '1' THEN - v.state := RESET; - assert false report "setting state to reset" severity note; - ELSIF v.out_mosi.address(c_adr_w-1 DOWNTO 0) = c_max_adr(c_adr_w-1 DOWNTO 0) AND in_sosi.valid = '1' THEN - v.state := MAX; - assert false report "setting state to max" severity note; - ELSIF in_sosi.valid = '1' THEN - v.state := COUNTING; - assert false report "setting state to counting" severity note; - ELSE - v.state := IDLE; - assert false report "setting state to idle" severity note; - END IF; - - - assert false report "starting case" severity note; CASE v.state IS WHEN RESET => - assert false report "starting reset" severity note; v.out_mosi.address(c_adr_w-1 DOWNTO 0) := (OTHERS => '0'); WHEN COUNTING => - assert false report "starting counting" severity note; v.out_mosi.address(c_adr_w-1 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UVEC(TO_UINT(v.out_mosi.address)+1, c_adr_w)); WHEN MAX => - assert false report "starting max" severity note; v.out_mosi.address(c_adr_w-1 DOWNTO 0) := (OTHERS => '0'); WHEN IDLE => - assert false report "starting idle" severity note; - v.out_mosi.address(c_adr_w-1 DOWNTO 0) := q_reg.out_mosi.address(c_adr_w-1 DOWNTO 0); - assert false report "q_reg.out_mosi.address = " & NATURAL'image(TO_UINT(v.out_mosi.address)) severity note; END CASE; - assert false report "ending case" severity note; + + IF rst = '1' THEN + v.state := RESET; + ELSIF v.out_mosi.address(c_adr_w-1 DOWNTO 0) = c_max_adr(c_adr_w-1 DOWNTO 0) AND in_sosi.valid = '1' THEN + v.state := MAX; + ELSIF in_sosi.valid = '1' THEN + v.state := COUNTING; + ELSE + v.state := IDLE; + END IF; d_reg <= v; END PROCESS; diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd index d1cf1ba92186b20b80eb6891558e3a339f472faf..29778c5d5804a8f80e837026c30930676437b743 100644 --- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd +++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_address_counter.vhd @@ -151,15 +151,15 @@ BEGIN p_verify_address : PROCESS BEGIN FOR I IN 0 TO c_adr_size-1 LOOP + WAIT UNTIL out_mosi.wr = '1'; + IF q_rst = '1' THEN + WAIT UNTIL out_mosi.wr = '1'; + END IF; IF I >= q_lag_due_reset THEN ASSERT I-q_lag_due_reset = TO_UINT(out_mosi.address) REPORT "Wrong address, 1, I = " & NATURAL'image(I-q_lag_due_reset) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR; ELSE ASSERT (I-q_lag_due_reset)+c_adr_size = TO_UINT(out_mosi.address) REPORT "Wrong address, 2, I = " & NATURAL'image((I-q_lag_due_reset)+c_adr_size) & ", address = " & NATURAL'image(TO_UINT(out_mosi.address)) SEVERITY ERROR; END IF; - WAIT UNTIL out_mosi.wr = '1'; - IF q_rst = '1' THEN - WAIT UNTIL out_mosi.wr = '1'; - END IF; END LOOP; END PROCESS;