diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd
index cca6da7cdb0f854a6633f6e629478d3c4903fa0a..77204376033fcbdc6d96ffc57de7246e51f1c2c7 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd
@@ -251,5 +251,4 @@ begin
       I := 0;
     end if;
   end process p_tester;
-
 end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd
index 1be6cbca3ac5ec4e20040d52a6aa4e11422a22af..a38cdfba6556c8596a39677d85fe580010c95cf2 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd
@@ -207,5 +207,4 @@ begin
       I := 0;
     end if;
   end process p_tester;
-
 end tb;
diff --git a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_simple_dual_port_ram_single_clock.vhd b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_simple_dual_port_ram_single_clock.vhd
index 568dfc1930fc822648bd5e68f5131e86295843b0..b39f324843e4c35be2e44d61f92ddd729485596f 100644
--- a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_simple_dual_port_ram_single_clock.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_simple_dual_port_ram_single_clock.vhd
@@ -71,5 +71,4 @@ begin
     q <= ram(raddr);
   end if;
   end process;
-
 end rtl;
diff --git a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_true_dual_port_ram_single_clock.vhd b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_true_dual_port_ram_single_clock.vhd
index 3c19ef88b75f83d076c853a6357cd622cef599ad..495fb1624c07ebdbb8d992350a81b8542661e322 100644
--- a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_true_dual_port_ram_single_clock.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_true_dual_port_ram_single_clock.vhd
@@ -81,5 +81,4 @@ begin
     q_b <= ram(addr_b);
   end if;
   end process;
-
 end rtl;
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_single_clock.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_single_clock.vhd
index 54c278c219fe7f2918490b6eb83769091b02d3af..206e76f7b0ee7f1aeed0b974688519c8090c2a21 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_single_clock.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_single_clock.vhd
@@ -65,5 +65,4 @@ begin
     q <= ram(raddr);
   end if;
   end process;
-
 end rtl;
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_single_clock.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_single_clock.vhd
index cd90cf167ecfd05fd7c016cb13e823224a92fbb3..dba8bb6afd3284259464514303daa65516b3dc09 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_single_clock.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_single_clock.vhd
@@ -65,5 +65,4 @@ begin
     q <= ram(raddr);
   end if;
   end process;
-
 end rtl;
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_single_clock.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_single_clock.vhd
index 558506ca8d9496f26bfb98f7afc36b075c439607..6e789dafdc078d91f84cd714ae2a693aa8bd76b2 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_single_clock.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_single_clock.vhd
@@ -65,5 +65,4 @@ begin
     q <= ram(raddr);
   end if;
   end process;
-
 end rtl;
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_simple_dual_port_ram_single_clock.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_simple_dual_port_ram_single_clock.vhd
index d21f7ee0a70ef312b4d13e600b500bce39b1bcf7..237904b7e18740cb2154dd70e6a0b31b58da1598 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_simple_dual_port_ram_single_clock.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_simple_dual_port_ram_single_clock.vhd
@@ -65,5 +65,4 @@ begin
     q <= ram(raddr);
   end if;
   end process;
-
 end rtl;