From fa5535d7f1e931e8b13f93a7aa4f218622f5bf8b Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Mon, 27 Oct 2014 16:07:29 +0000
Subject: [PATCH] Ported FIFO IP for Arria10.
---
libraries/technology/fifo/hdllib.cfg | 2 +-
.../fifo/tech_fifo_component_pkg.vhd | 66 +++++++++++++++++++
libraries/technology/fifo/tech_fifo_dc.vhd | 10 ++-
.../fifo/tech_fifo_dc_mixed_widths.vhd | 11 +++-
libraries/technology/fifo/tech_fifo_sc.vhd | 11 +++-
5 files changed, 94 insertions(+), 6 deletions(-)
diff --git a/libraries/technology/fifo/hdllib.cfg b/libraries/technology/fifo/hdllib.cfg
index 5cd0dc997f..39077bacc0 100644
--- a/libraries/technology/fifo/hdllib.cfg
+++ b/libraries/technology/fifo/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = tech_fifo
hdl_library_clause_name = tech_fifo_lib
-hdl_lib_uses = technology ip_stratixiv
+hdl_lib_uses = technology ip_stratixiv ip_arria10_fifo
hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
diff --git a/libraries/technology/fifo/tech_fifo_component_pkg.vhd b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
index 0f2d30de1f..0cc6e4e078 100644
--- a/libraries/technology/fifo/tech_fifo_component_pkg.vhd
+++ b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
@@ -91,4 +91,70 @@ PACKAGE tech_fifo_component_pkg IS
);
END COMPONENT;
+
+ -----------------------------------------------------------------------------
+ -- ip_stratixiv
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_fifo_sc IS
+ GENERIC (
+ g_use_eab : STRING := "ON";
+ g_dat_w : NATURAL := 20;
+ g_nof_words : NATURAL := 1024
+ );
+ PORT (
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdreq : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ full : OUT STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
+ usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_fifo_dc IS
+ GENERIC (
+ g_use_eab : STRING := "ON";
+ g_dat_w : NATURAL := 20;
+ g_nof_words : NATURAL := 1024
+ );
+ PORT (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
+ wrfull : OUT STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_fifo_dc_mixed_widths IS
+ GENERIC (
+ g_nof_words : NATURAL := 1024; -- FIFO size in nof wr_dat words
+ g_wrdat_w : NATURAL := 20;
+ g_rddat_w : NATURAL := 10
+ );
+ PORT (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
+ wrfull : OUT STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
END tech_fifo_component_pkg;
diff --git a/libraries/technology/fifo/tech_fifo_dc.vhd b/libraries/technology/fifo/tech_fifo_dc.vhd
index 3e056dc535..f0cb496d1f 100644
--- a/libraries/technology/fifo/tech_fifo_dc.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc.vhd
@@ -27,10 +27,12 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_lib;
+LIBRARY ip_arria10_fifo_lib;
ENTITY tech_fifo_dc IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
+ g_use_eab : STRING := "ON";
g_dat_w : NATURAL;
g_nof_words : NATURAL
);
@@ -60,4 +62,10 @@ BEGIN
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
END GENERATE;
-END ARCHITECTURE;
\ No newline at end of file
+ gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ u0 : ip_arria10_fifo_dc
+ GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
+ PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+ END GENERATE;
+
+END ARCHITECTURE;
diff --git a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
index 58ee8fb327..a5f0be0f91 100644
--- a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_lib;
+LIBRARY ip_arria10_fifo_lib;
ENTITY tech_fifo_dc_mixed_widths IS
GENERIC (
@@ -60,5 +61,11 @@ BEGIN
GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
END GENERATE;
-
-END ARCHITECTURE;
\ No newline at end of file
+
+ gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ u0 : ip_arria10_fifo_dc_mixed_widths
+ GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
+ PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+ END GENERATE;
+
+END ARCHITECTURE;
diff --git a/libraries/technology/fifo/tech_fifo_sc.vhd b/libraries/technology/fifo/tech_fifo_sc.vhd
index e08b6ace45..726e959439 100644
--- a/libraries/technology/fifo/tech_fifo_sc.vhd
+++ b/libraries/technology/fifo/tech_fifo_sc.vhd
@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_lib;
+LIBRARY ip_arria10_fifo_lib;
ENTITY tech_fifo_sc IS
GENERIC (
@@ -58,5 +59,11 @@ BEGIN
GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
END GENERATE;
-
-END ARCHITECTURE;
\ No newline at end of file
+
+ gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ u0 : ip_arria10_fifo_sc
+ GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
+ PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
+ END GENERATE;
+
+END ARCHITECTURE;
--
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