From f9e6bc4b7301d3856e8901571c262857b501dd75 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Tue, 31 Jul 2018 11:32:59 +0000
Subject: [PATCH] fixed the FIXME in io_ddr testbench
---
libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd | 6 +++---
libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd | 5 +----
2 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
index 6b1bec8ba6..a807bd6fbd 100644
--- a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
@@ -71,12 +71,12 @@ ARCHITECTURE str of tb_io_ddr IS
CONSTANT c_sim_ddr : t_c_tech_ddr := func_tech_sel_ddr(g_technology, c_tech_ddr3_sim_16k, c_tech_ddr4_sim_16k);
CONSTANT c_tech_ddr : t_c_tech_ddr := func_tech_sel_ddr(g_sim_model, c_sim_ddr, c_mem_ddr);
- CONSTANT c_ctlr_ref_clk_period : TIME := sel_a_b(c_tech_ddr.name="DDR3", 5 ns, 40 ns); -- 200 MHz for DDR3 on UniBoard and 25 MHz for DDR4 on UniBoard2
+ CONSTANT c_dp_clk_period : TIME := 5 ns; -- 200 MHz
+ CONSTANT c_mm_clk_period : TIME := 8 ns; -- 125 MHz
+ CONSTANT c_ctlr_ref_clk_period : TIME := sel_a_b(g_sim_model, c_dp_clk_period, sel_a_b(c_tech_ddr.name="DDR3", 5 ns, 40 ns)); -- 200 MHz for DDR3 on UniBoard and 25 MHz for DDR4 on UniBoard2, use dp clock for sim_model
CONSTANT c_ctlr_clk_freq : NATURAL := c_tech_ddr.mts/c_tech_ddr.rsl; -- 200 MHz
CONSTANT c_ctlr_clk_period : TIME := (1000000 / c_ctlr_clk_freq) * 1 ps; -- 5000 ps
CONSTANT c_cross_domain_dvr_ctlr : BOOLEAN := g_cross_domain_dvr_ctlr OR g_dvr_clk_period/=c_ctlr_clk_period;
- CONSTANT c_dp_clk_period : TIME := 5 ns; -- 200 MHz
- CONSTANT c_mm_clk_period : TIME := 8 ns; -- 125 MHz
CONSTANT c_ctlr_address_w : NATURAL := func_tech_ddr_ctlr_address_w(c_tech_ddr);
CONSTANT c_ctlr_data_w : NATURAL := func_tech_ddr_ctlr_data_w(c_tech_ddr);
diff --git a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
index 3126457be9..cf5de76ced 100644
--- a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
@@ -65,12 +65,9 @@ BEGIN
-- g_nof_repeat : NATURAL := 1; -- number of stimuli repeats with write flush after each repeat
-- g_wr_flush_mode : STRING := "SYN" -- "VAL", "SOP", "SYN"
- -- FIXME: Sim model does not work for UNB2B, it causes the testbench to timeout. Temporarly placed under gen_ddr3.
- -- u_sim_model : ENTITY work.tb_io_ddr GENERIC MAP ( TRUE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(0));
+ u_sim_model : ENTITY work.tb_io_ddr GENERIC MAP ( TRUE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(0));
gen_ddr3 : IF c_tech_ddr.name="DDR3" GENERATE
- u_sim_model : ENTITY work.tb_io_ddr GENERIC MAP ( TRUE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(0));
-
u_default : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(1));
u_fill_wrfifo_on_next_valid : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 1, 1000, 2, 1, 4, 2, "VAL") PORT MAP (tb_end_vec(2));
--
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