diff --git a/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd b/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd index b2a595644f4227a84650c31fb80f51690131f4b9..76c4300dd44c4889ef4d23151136242494ec00c1 100644 --- a/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd +++ b/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd @@ -1,26 +1,39 @@ -------------------------------------------------------------------------------- +-- ----------------------------------------------------------------------------- -- --- Copyright (C) 2014 +-- Copyright 2014-2023 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands -- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at -- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. +-- http://www.apache.org/licenses/LICENSE-2.0 -- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. -- -------------------------------------------------------------------------------- +-- ----------------------------------------------------------------------------- +-- +-- Author : - +-- Changed by : D.F. Brouwer +-- Description: +-- Dual clock domain with different aspect ratio data widhts +-- Use port a only for write in write clock domain +-- Use port b only for read in read clock domain +-- Remark: +-- Because the the Agilex 7 (agi027_xxxx) does not support the crwk_crw IP, +-- and unfortunately, the rwk_rw IP isn't supported either, the crk_cw IP +-- has been created, resulting in modifications to this file.[1] +-- Reference: +-- [1] Based on the stucture of common_crw_crw_ratio.vhd. -library IEEE, technology_lib; +library IEEE, technology_lib, tech_memory_lib; use IEEE.std_logic_1164.all; +use work.common_pkg.all; use work.common_mem_pkg.all; use technology_lib.technology_select_pkg.all; @@ -51,36 +64,81 @@ entity common_ram_cr_cw_ratio is end common_ram_cr_cw_ratio; architecture str of common_ram_cr_cw_ratio is + constant c_ram : t_c_mem := g_ram_wr; -- use shared parameters from port wr (a) parameter + + constant c_rd_latency : natural := sel_a_b(c_ram.latency < 2, c_ram.latency, 2); -- handle read latency 1 or 2 in RAM + constant c_pipeline : natural := sel_a_b(c_ram.latency > c_rd_latency, c_ram.latency - c_rd_latency, 0); -- handle rest of read latency > 2 in pipeline + + -- Intermediate signal for extra pipelining + signal ram_rd_dat : std_logic_vector(rd_dat'range); + + -- Map sl to single bit slv for rd_val pipelining + signal ram_rd_en : std_logic_vector(0 downto 0); + signal ram_rd_val : std_logic_vector(0 downto 0); + begin - -- Dual clock domain - -- Use port a only for write in write clock domain - -- Use port b only for read in read clock domain + assert c_ram.latency >= 1 + report "common_ram_cr_cw_ratio : only support read latency >= 1" + severity FAILURE; + + assert g_ram_wr.latency = g_ram_rd.latency + report "common_ram_cr_cw_ratio : only support same read latency for both ports" + severity FAILURE; + + -- memory access + u_ramk : entity tech_memory_lib.tech_memory_ram_crk_cw + generic map ( + g_technology => g_technology, + g_wr_adr_w => g_ram_wr.adr_w, + g_rd_adr_w => g_ram_rd.adr_w, + g_wr_dat_w => g_ram_wr.dat_w, + g_rd_dat_w => g_ram_rd.dat_w, + g_wr_nof_words => g_ram_wr.nof_dat, + g_rd_nof_words => g_ram_rd.nof_dat, + g_rd_latency => c_rd_latency, + g_init_file => g_init_file + ) + port map ( + wrclock => wr_clk, + rdclock => rd_clk, + wrclocken => wr_clken, + rdclocken => rd_clken, + wren => wr_en, + data => wr_dat, + wraddress => wr_adr, + rdaddress => rd_adr, + q => ram_rd_dat + ); + + -- read output + u_pipe : entity work.common_pipeline + generic map ( + g_pipeline => c_pipeline, + g_in_dat_w => g_ram_rd.dat_w, + g_out_dat_w => g_ram_rd.dat_w + ) + port map ( + clk => rd_clk, + clken => rd_clken, + in_dat => ram_rd_dat, + out_dat => rd_dat + ); + + -- rd_val control + ram_rd_en(0) <= rd_en; + + rd_val <= ram_rd_val(0); - u_cr_cw : entity work.common_ram_crw_crw_ratio + u_rd_val : entity work.common_pipeline generic map ( - g_technology => g_technology, - g_ram_a => g_ram_wr, - g_ram_b => g_ram_rd, - g_init_file => g_init_file + g_pipeline => c_ram.latency, + g_in_dat_w => 1, + g_out_dat_w => 1 ) port map ( - rst_a => wr_rst, - rst_b => rd_rst, - clk_a => wr_clk, - clk_b => rd_clk, - clken_a => wr_clken, - clken_b => rd_clken, - wr_en_a => wr_en, - wr_en_b => '0', - wr_dat_a => wr_dat, - wr_dat_b => (others => '0'), - adr_a => wr_adr, - adr_b => rd_adr, - rd_en_a => '0', - rd_en_b => rd_en, - rd_dat_a => OPEN, - rd_dat_b => rd_dat, - rd_val_a => OPEN, - rd_val_b => rd_val + clk => rd_clk, + clken => rd_clken, + in_dat => ram_rd_en, + out_dat => ram_rd_val ); end str;