diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
index 2efbc722846c6b8cfc9572098b9f8fda004670d8..a36b47ec9bb23dbf5d44b012b471fe43eaa90f4b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">16</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -605,6 +605,10 @@
<spirit:name>avs_mem_address</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>1</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -697,6 +701,10 @@
<spirit:name>coe_address_export</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>1</spirit:right>
+ </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -775,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -838,7 +846,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -902,7 +910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -971,7 +979,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1366,11 +1374,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
index dc294ad5df439e9258503f0955bda54f6310c130..d6f321e7ef38e0d597aceea0693177e2c39b7e8e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "737752";
+ value = "737760";
type = "String";
}
}
@@ -144,7 +144,7 @@
{
datum baseAddress
{
- value = "737672";
+ value = "737688";
type = "String";
}
}
@@ -157,7 +157,7 @@
}
datum sopceditor_expanded
{
- value = "0";
+ value = "1";
type = "boolean";
}
}
@@ -165,7 +165,7 @@
{
datum baseAddress
{
- value = "737744";
+ value = "737648";
type = "String";
}
}
@@ -426,7 +426,7 @@
{
datum baseAddress
{
- value = "737696";
+ value = "737712";
type = "String";
}
}
@@ -442,7 +442,7 @@
{
datum baseAddress
{
- value = "737648";
+ value = "737664";
type = "String";
}
}
@@ -506,7 +506,7 @@
{
datum baseAddress
{
- value = "737688";
+ value = "737704";
type = "String";
}
}
@@ -538,7 +538,7 @@
{
datum baseAddress
{
- value = "737656";
+ value = "737672";
type = "String";
}
}
@@ -575,7 +575,7 @@
{
datum baseAddress
{
- value = "737736";
+ value = "737752";
type = "String";
}
}
@@ -596,7 +596,7 @@
{
datum baseAddress
{
- value = "737728";
+ value = "737744";
type = "String";
}
}
@@ -691,7 +691,7 @@
{
datum baseAddress
{
- value = "737720";
+ value = "737736";
type = "String";
}
}
@@ -712,7 +712,7 @@
{
datum baseAddress
{
- value = "737712";
+ value = "737728";
type = "String";
}
}
@@ -728,7 +728,7 @@
{
datum baseAddress
{
- value = "737680";
+ value = "737696";
type = "String";
}
}
@@ -797,7 +797,7 @@
{
datum baseAddress
{
- value = "737704";
+ value = "737720";
type = "String";
}
}
@@ -829,7 +829,7 @@
{
datum baseAddress
{
- value = "737664";
+ value = "737680";
type = "String";
}
}
@@ -1291,11 +1291,6 @@
internal="pio_wdi.external_connection"
type="conduit"
dir="end" />
- <interface
- name="reg_stat_hdr_dat_xst_readdata"
- internal="reg_stat_hdr_dat_xst.readdata"
- type="conduit"
- dir="end" />
<interface
name="ram_bf_weights_address"
internal="ram_bf_weights.address"
@@ -2671,6 +2666,11 @@
internal="reg_stat_hdr_dat_xst.read"
type="conduit"
dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_xst_readdata"
+ internal="reg_stat_hdr_dat_xst.readdata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_stat_hdr_dat_xst_reset"
internal="reg_stat_hdr_dat_xst.reset"
@@ -5805,7 +5805,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xB4000' end='0xB4040' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xB4040' end='0xB4080' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xB4080' end='0xB40C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xB40C0' end='0xB40E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xB40E0' end='0xB4100' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4100' end='0xB4120' datawidth='32' /><slave name='reg_remu.mem' start='0xB4120' end='0xB4140' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xB4140' end='0xB4150' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4150' end='0xB4160' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB4160' end='0xB4170' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0xB4170' end='0xB4178' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xB4178' end='0xB4180' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB4180' end='0xB4188' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB4188' end='0xB4190' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB4190' end='0xB4198' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB4198' end='0xB41A0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB41A0' end='0xB41A8' datawidth='32' /><slave name='reg_si.mem' start='0xB41A8' end='0xB41B0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB41B0' end='0xB41B8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB41B8' end='0xB41C0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB41C0' end='0xB41C8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB41C8' end='0xB41D0' datawidth='32' /><slave name='pio_pps.mem' start='0xB41D0' end='0xB41D8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB41D8' end='0xB41E0' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xB4000' end='0xB4040' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xB4040' end='0xB4080' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xB4080' end='0xB40C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xB40C0' end='0xB40E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xB40E0' end='0xB4100' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4100' end='0xB4120' datawidth='32' /><slave name='reg_remu.mem' start='0xB4120' end='0xB4140' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xB4140' end='0xB4150' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4150' end='0xB4160' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB4160' end='0xB4170' datawidth='32' /><slave name='pio_pps.mem' start='0xB4170' end='0xB4180' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0xB4180' end='0xB4188' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xB4188' end='0xB4190' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB4190' end='0xB4198' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB4198' end='0xB41A0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB41A0' end='0xB41A8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB41A8' end='0xB41B0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB41B0' end='0xB41B8' datawidth='32' /><slave name='reg_si.mem' start='0xB41B8' end='0xB41C0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB41C0' end='0xB41C8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB41C8' end='0xB41D0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB41D0' end='0xB41D8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB41D8' end='0xB41E0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB41E0' end='0xB41E8' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -8448,7 +8448,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -8512,7 +8512,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -8581,7 +8581,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -8987,11 +8987,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -39356,7 +39356,7 @@
version="18.0"
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
- <parameter name="baseAddress" value="0x000b41d8" />
+ <parameter name="baseAddress" value="0x000b41e0" />
</connection>
<connection
kind="avalon"
@@ -39391,7 +39391,7 @@
version="18.0"
start="cpu_0.data_master"
end="pio_pps.mem">
- <parameter name="baseAddress" value="0x000b41d0" />
+ <parameter name="baseAddress" value="0x000b4170" />
</connection>
<connection
kind="avalon"
@@ -39419,28 +39419,28 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
- <parameter name="baseAddress" value="0x000b41c8" />
+ <parameter name="baseAddress" value="0x000b41d8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
- <parameter name="baseAddress" value="0x000b41c0" />
+ <parameter name="baseAddress" value="0x000b41d0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
- <parameter name="baseAddress" value="0x000b41b8" />
+ <parameter name="baseAddress" value="0x000b41c8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
- <parameter name="baseAddress" value="0x000b41b0" />
+ <parameter name="baseAddress" value="0x000b41c0" />
</connection>
<connection
kind="avalon"
@@ -39475,7 +39475,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_si.mem">
- <parameter name="baseAddress" value="0x000b41a8" />
+ <parameter name="baseAddress" value="0x000b41b8" />
</connection>
<connection
kind="avalon"
@@ -39517,7 +39517,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
- <parameter name="baseAddress" value="0x000b41a0" />
+ <parameter name="baseAddress" value="0x000b41b0" />
</connection>
<connection
kind="avalon"
@@ -39552,7 +39552,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_selector.mem">
- <parameter name="baseAddress" value="0x000b4198" />
+ <parameter name="baseAddress" value="0x000b41a8" />
</connection>
<connection
kind="avalon"
@@ -39615,7 +39615,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
- <parameter name="baseAddress" value="0x000b4190" />
+ <parameter name="baseAddress" value="0x000b41a0" />
</connection>
<connection
kind="avalon"
@@ -39643,14 +39643,14 @@
version="18.0"
start="cpu_0.data_master"
end="pio_jesd_ctrl.mem">
- <parameter name="baseAddress" value="0x000b4188" />
+ <parameter name="baseAddress" value="0x000b4198" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_sst.mem">
- <parameter name="baseAddress" value="0x000b4180" />
+ <parameter name="baseAddress" value="0x000b4190" />
</connection>
<connection
kind="avalon"
@@ -39678,7 +39678,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_sync_insert_v2.mem">
- <parameter name="baseAddress" value="0x000b4178" />
+ <parameter name="baseAddress" value="0x000b4188" />
</connection>
<connection
kind="avalon"
@@ -39692,7 +39692,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_scheduler_xsub.mem">
- <parameter name="baseAddress" value="0x000b4170" />
+ <parameter name="baseAddress" value="0x000b4180" />
</connection>
<connection
kind="avalon"
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..55e0af625cc4394681a6002faa68592fc2d60209
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
@@ -0,0 +1,107 @@
+hdl_lib_name = lofar2_unb2b_sdp_station_full
+hdl_library_clause_name = lofar2_unb2b_sdp_station_full_lib
+hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_sdp_station
+hdl_lib_uses_sim = eth
+hdl_lib_technology = ip_arria10_e1sg
+
+ synth_files =
+ lofar2_unb2b_sdp_station_full.vhd
+
+test_bench_files =
+
+regression_test_vhdl =
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ # Overwrite bf weights with sim data
+ ../../tb/data data
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ ../../quartus .
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+# use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
+quartus_sdc_files =
+ ../../quartus/lofar2_unb2b_sdp_station.sdc
+ #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+ ../../quartus/lofar2_unb2b_sdp_station_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_full/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_sync_insert_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9c68eacf0efe37d9d6c49d1945b839a57d940487
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
@@ -0,0 +1,177 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author : R. van der Walle
+-- Purpose:
+-- Wrapper for Lofar2 SDP Station full design
+-- Description:
+-- Unb2b version for lab testing
+-- Contains complete SDP station design with AIT input stage with 12 ADC streams, FSUB, XSUB and BF
+
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY lofar2_unb2b_sdp_station_full IS
+ GENERIC (
+ g_design_name : STRING := "lofar2_unb2b_sdp_station_full";
+ g_design_note : STRING := "Lofar2 SDP station full design";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC := '0';
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+
+ -- Transceiver clocks
+ SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
+
+ -- front transceivers
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+
+ -- LEDs
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+
+ -- back transceivers (note only 6 are used in unb2b)
+ BCK_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b-1 downto c_unb2b_board_nof_tr_jesd204b);
+ BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
+
+ -- jesd204b syncronization signals (2 syncs)
+ JESD204B_SYSREF : IN STD_LOGIC;
+ JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0)
+ );
+END lofar2_unb2b_sdp_station_full;
+
+ARCHITECTURE str OF lofar2_unb2b_sdp_station_full IS
+
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC;
+
+
+BEGIN
+
+ -- Mapping between JESD signal names and UNB2B pin/schematic names
+ JESD204B_REFCLK <= BCK_REF_CLK;
+ JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
+ JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
+ JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
+ JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
+ JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
+ JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
+ JESD204B_SERIAL_DATA(6) <= '0';
+ JESD204B_SERIAL_DATA(7) <= '0';
+ JESD204B_SERIAL_DATA(8) <= '0';
+ JESD204B_SERIAL_DATA(9) <= '0';
+ JESD204B_SERIAL_DATA(10) <= '0';
+ JESD204B_SERIAL_DATA(11) <= '0';
+ JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+
+
+ u_revision : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
+END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index 9f8ecfbddf90215cb723d7c0cb500d708250ddba..36bda1b4a0f7ccb59831c8fee5b23f0573f6d8d4 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright 2020
+-- Copyright 2021
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
@@ -23,7 +23,7 @@
-- Purpose:
-- Core design for Lofar2 SDP station
-- Description:
--- Unb2b version for lab testing
+-- Unb2b version for lab testing, using generic sdp_station.vhd for LOFAR2 SDP application.
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib, eth_lib;
@@ -118,32 +118,9 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
CONSTANT c_lofar2_sample_clk_freq : NATURAL := c_sdp_f_adc_MHz * 10**6; -- fixed 200 MHz for LOFAR2.0 stage 1
-- 10 GbE Interface
- CONSTANT c_nof_streams_qsfp : NATURAL := c_unb2b_board_tr_qsfp.nof_bus * c_quad;
- CONSTANT c_nof_qsfp_bus : NATURAL := 1;
- CONSTANT c_nof_10GbE_offload_streams : NATURAL := 1;
- CONSTANT c_nof_blocks_per_packet : NATURAL := 4;
- CONSTANT c_nof_beamlets_per_block : NATURAL := c_sdp_N_pol * c_sdp_S_sub_bf;
- CONSTANT c_10GbE_block_size : NATURAL := c_nof_blocks_per_packet * c_nof_beamlets_per_block / 4; -- 4 beamlets fit in 1 64bit longword
- CONSTANT c_fifo_tx_fill : NATURAL := c_10GbE_block_size;
- CONSTANT c_fifo_tx_size : NATURAL := c_fifo_tx_fill + 11; -- Make fifo size large enough for adding header.
+ CONSTANT c_nof_streams_qsfp : NATURAL := c_unb2b_board_tr_qsfp.nof_bus * c_quad;
- -- Address widths of a single MM instance
- CONSTANT c_addr_w_ram_ss_ss_wide : NATURAL := ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- CONSTANT c_addr_w_ram_bf_weights : NATURAL := ceil_log2(c_sdp_N_pol * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- CONSTANT c_addr_w_reg_bf_scale : NATURAL := 1;
- CONSTANT c_addr_w_reg_hdr_dat : NATURAL := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
- CONSTANT c_addr_w_reg_dp_xonoff : NATURAL := 1;
- CONSTANT c_addr_w_ram_st_bst : NATURAL := ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol*(c_longword_sz/c_word_sz));
-
- --
- CONSTANT c_udp_offload_nof_streams : NATURAL := c_eth_nof_udp_ports;
-
- -- Read only sdp_info values
- CONSTANT c_f_adc : STD_LOGIC := '1'; -- '0' => 160M, '1' => 200M
- CONSTANT c_fsub_type : STD_LOGIC := '0'; -- '0' => critical sampled PFB, '1' => oversampled PFB
-
SIGNAL gn_id : STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
- SIGNAL gn_index : NATURAL := 0;
-- System
SIGNAL cs_sim : STD_LOGIC;
@@ -319,38 +296,26 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
-- Beamlet Subband Select
SIGNAL ram_ss_ss_wide_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL ram_ss_ss_wide_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL ram_ss_ss_wide_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL ram_ss_ss_wide_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
-- Local BF bf weights
SIGNAL ram_bf_weights_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL ram_bf_weights_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL ram_bf_weights_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL ram_bf_weights_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
-- mms_dp_scale Scale Beamlets
SIGNAL reg_bf_scale_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_bf_scale_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_bf_scale_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reg_bf_scale_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
-- Beamlet Data Output header fields
SIGNAL reg_hdr_dat_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_hdr_dat_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_hdr_dat_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reg_hdr_dat_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
-- Beamlet Data Output xonoff
SIGNAL reg_dp_xonoff_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_dp_xonoff_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_dp_xonoff_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reg_dp_xonoff_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
-- Beamlet Statistics (BST)
SIGNAL ram_st_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL ram_st_bst_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL ram_st_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL ram_st_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
----------------------------------------------
-- SST
@@ -380,20 +345,16 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
-- Statistics Enable
SIGNAL reg_stat_enable_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_stat_enable_bst_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_stat_enable_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reg_stat_enable_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
-- Statistics header info
SIGNAL reg_stat_hdr_dat_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_stat_hdr_dat_bst_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_stat_hdr_dat_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reg_stat_hdr_dat_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
----------------------------------------------
-- UDP Offload
----------------------------------------------
- SIGNAL udp_tx_sosi_arr : t_dp_sosi_arr(c_udp_offload_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL udp_tx_siso_arr : t_dp_siso_arr(c_udp_offload_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ SIGNAL udp_tx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL udp_tx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
----------------------------------------------
-- 10 GbE
@@ -404,57 +365,23 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL reg_nw_10GbE_eth10g_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_nw_10GbE_eth10g_miso : t_mem_miso := c_mem_miso_rst;
- ----------------------------------------------
-
- SIGNAL ait_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
- SIGNAL pfb_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
- SIGNAL fsub_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
-
- SIGNAL dp_bsn_source_restart : STD_LOGIC;
-
- SIGNAL bf_udp_sosi_arr : t_dp_sosi_arr(c_sdp_N_beamsets-1 DOWNTO 0);
- SIGNAL bf_udp_siso_arr : t_dp_siso_arr(c_sdp_N_beamsets-1 DOWNTO 0);
- SIGNAL bf_10GbE_hdr_fields_out_arr : t_slv_1024_arr(c_sdp_N_beamsets-1 DOWNTO 0);
-
-- 10GbE
- SIGNAL tr_ref_clk_312 : STD_LOGIC;
- SIGNAL tr_ref_clk_156 : STD_LOGIC;
- SIGNAL tr_ref_rst_156 : STD_LOGIC;
-
SIGNAL i_QSFP_TX : t_unb2b_board_qsfp_bus_2arr(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
SIGNAL i_QSFP_RX : t_unb2b_board_qsfp_bus_2arr(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
SIGNAL unb2_board_front_io_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL unb2_board_front_io_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => '0');
- SIGNAL nw_10gbe_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL nw_10gbe_snk_out_arr : t_dp_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
- SIGNAL nw_10gbe_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL nw_10gbe_src_in_arr : t_dp_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
-
- SIGNAL nw_10GbE_hdr_fields_in_arr : t_slv_1024_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
-
SIGNAL this_bck_id : STD_LOGIC_VECTOR(c_unb2b_board_nof_uniboard_w-1 DOWNTO 0);
SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb2b_board_nof_chip_w-1 DOWNTO 0);
- SIGNAL cep_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
- SIGNAL cep_ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
- SIGNAL cep_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
- SIGNAL stat_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
- SIGNAL stat_ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
- SIGNAL sst_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
- SIGNAL bst_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
- SIGNAL xst_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
-
- SIGNAL sdp_info : t_sdp_info := c_sdp_info_rst;
-
-- QSFP LEDS
SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
- SIGNAL unb2b_board_qsfp_leds_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL unb2b_board_qsfp_leds_tx_siso_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
- SIGNAL unb2b_board_qsfp_leds_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL unb2_board_qsfp_leds_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL unb2_board_qsfp_leds_tx_siso_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL unb2_board_qsfp_leds_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
BEGIN
@@ -723,65 +650,59 @@ BEGIN
ram_st_xsq_miso => ram_st_xsq_miso
);
- -----------------------------------------------------------------------------
- -- SDP Info register
- -----------------------------------------------------------------------------
- gn_id <= ID(c_sdp_W_gn_id-1 DOWNTO 0);
- gn_index <= TO_UINT(gn_id);
- -- derive MAC, IP and UDP Port
- cep_eth_src_mac <= c_sdp_cep_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
- cep_ip_src_addr <= c_sdp_cep_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
- cep_udp_src_port <= c_sdp_cep_udp_src_port_15_8 & ID;
-
- stat_eth_src_mac <= c_sdp_stat_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
- stat_ip_src_addr <= c_sdp_stat_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
- sst_udp_src_port <= c_sdp_sst_udp_src_port_15_8 & ID;
- bst_udp_src_port <= c_sdp_bst_udp_src_port_15_8 & ID;
- xst_udp_src_port <= c_sdp_xst_udp_src_port_15_8 & ID;
-
- u_sdp_info : ENTITY lofar2_sdp_lib.sdp_info
- PORT MAP(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
-
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- reg_mosi => reg_sdp_info_mosi,
- reg_miso => reg_sdp_info_miso,
-
- -- inputs from other blocks
- gn_index => gn_index,
- f_adc => c_f_adc,
- fsub_type => c_fsub_type,
-
- -- sdp info
- sdp_info => sdp_info
- );
+ gn_id <= ID(c_sdp_W_gn_id-1 DOWNTO 0);
-----------------------------------------------------------------------------
- -- node_adc_input_and_timing (AIT)
- -- .Contains JESD receiver, bsn source and associated data buffers, diagnostics and statistics
+ -- sdp nodes
-----------------------------------------------------------------------------
- u_ait: ENTITY lofar2_sdp_lib.node_sdp_adc_input_and_timing
- GENERIC MAP(
- g_technology => g_technology,
- g_sim => g_sim,
- g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync
+ u_sdp_station : ENTITY lofar2_sdp_lib.sdp_station
+ GENERIC MAP (
+ g_technology => c_tech_arria10_e1sg,
+ g_sim => g_sim,
+ g_wpfb => g_wpfb,
+ g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
+ g_scope_selected_subband => g_scope_selected_subband,
+ g_use_fsub => c_revision_select.use_fsub,
+ g_use_xsub => c_revision_select.use_xsub,
+ g_use_bf => c_revision_select.use_bf,
+ g_P_sq => c_revision_select.P_sq
)
- PORT MAP(
- -- clocks and resets
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- mm control buses
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
+ PORT MAP (
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_pps => dp_pps,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ gn_id => gn_id,
+ this_bck_id => this_bck_id,
+ this_chip_id => this_chip_id,
+
+ SA_CLK => SA_CLK,
+
+ -- jesd204b
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => JESD204B_SYNC_N,
+
+ -- UDP Offload
+ udp_tx_sosi_arr => udp_tx_sosi_arr,
+ udp_tx_siso_arr => udp_tx_siso_arr,
+
+ -- 10 GbE
+ reg_nw_10GbE_mac_mosi => reg_nw_10GbE_mac_mosi,
+ reg_nw_10GbE_mac_miso => reg_nw_10GbE_mac_miso,
+ reg_nw_10GbE_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
+ reg_nw_10GbE_eth10g_miso => reg_nw_10GbE_eth10g_miso,
+
+ -- AIT
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
reg_dp_shiftram_miso => reg_dp_shiftram_miso,
reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
@@ -800,341 +721,75 @@ BEGIN
reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
reg_aduh_monitor_miso => reg_aduh_monitor_miso,
-
- -- Jesd external IOs
- jesd204b_serial_data => JESD204B_SERIAL_DATA,
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n => JESD204B_SYNC_N,
-
- -- Streaming data output
- out_sosi_arr => ait_sosi_arr,
- dp_bsn_source_restart => dp_bsn_source_restart
+
+ -- FSUB
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
+ ram_equalizer_gains_miso => ram_equalizer_gains_miso,
+ reg_dp_selector_mosi => reg_dp_selector_mosi,
+ reg_dp_selector_miso => reg_dp_selector_miso,
+
+ -- SDP Info
+ reg_sdp_info_mosi => reg_sdp_info_mosi,
+ reg_sdp_info_miso => reg_sdp_info_miso,
+
+ -- XSUB
+ reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
+ reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
+ reg_crosslets_info_mosi => reg_crosslets_info_mosi,
+ reg_crosslets_info_miso => reg_crosslets_info_miso,
+ reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
+ reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
+ ram_st_xsq_mosi => ram_st_xsq_mosi,
+ ram_st_xsq_miso => ram_st_xsq_miso,
+
+ -- BF
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
+ ram_bf_weights_mosi => ram_bf_weights_mosi,
+ ram_bf_weights_miso => ram_bf_weights_miso,
+ reg_bf_scale_mosi => reg_bf_scale_mosi,
+ reg_bf_scale_miso => reg_bf_scale_miso,
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
+ reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
+ reg_dp_xonoff_miso => reg_dp_xonoff_miso,
+ ram_st_bst_mosi => ram_st_bst_mosi,
+ ram_st_bst_miso => ram_st_bst_miso,
+
+ -- SST
+ reg_stat_enable_sst_mosi => reg_stat_enable_sst_mosi,
+ reg_stat_enable_sst_miso => reg_stat_enable_sst_miso,
+ reg_stat_hdr_dat_sst_mosi => reg_stat_hdr_dat_sst_mosi,
+ reg_stat_hdr_dat_sst_miso => reg_stat_hdr_dat_sst_miso,
+
+ -- XST
+ reg_stat_enable_xst_mosi => reg_stat_enable_xst_mosi,
+ reg_stat_enable_xst_miso => reg_stat_enable_xst_miso,
+ reg_stat_hdr_dat_xst_mosi => reg_stat_hdr_dat_xst_mosi,
+ reg_stat_hdr_dat_xst_miso => reg_stat_hdr_dat_xst_miso,
+
+ -- BST
+ reg_stat_enable_bst_mosi => reg_stat_enable_bst_mosi,
+ reg_stat_enable_bst_miso => reg_stat_enable_bst_miso,
+ reg_stat_hdr_dat_bst_mosi => reg_stat_hdr_dat_bst_mosi,
+ reg_stat_hdr_dat_bst_miso => reg_stat_hdr_dat_bst_miso,
+
+ -- QSFP serial
+ unb2_board_front_io_serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ unb2_board_front_io_serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+
+ -- QSFP LEDS
+ unb2_board_qsfp_leds_tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
+ unb2_board_qsfp_leds_tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
+ unb2_board_qsfp_leds_rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
);
- -----------------------------------------------------------------------------
- -- node_sdp_filterbank (FSUB)
- -----------------------------------------------------------------------------
- gen_use_fsub : IF c_revision_select.use_fsub GENERATE
- u_fsub : ENTITY lofar2_sdp_lib.node_sdp_filterbank
- GENERIC MAP(
- g_sim => g_sim,
- g_wpfb => g_wpfb,
- g_scope_selected_subband => g_scope_selected_subband
- )
- PORT MAP(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- pfb_sosi_arr => pfb_sosi_arr,
- fsub_sosi_arr => fsub_sosi_arr,
- dp_bsn_source_restart => dp_bsn_source_restart,
-
- sst_udp_sosi => udp_tx_sosi_arr(0),
- sst_udp_siso => udp_tx_siso_arr(0),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_gains_mosi => ram_equalizer_gains_mosi,
- ram_gains_miso => ram_equalizer_gains_miso,
- reg_selector_mosi => reg_dp_selector_mosi,
- reg_selector_miso => reg_dp_selector_miso,
-
- reg_enable_mosi => reg_stat_enable_sst_mosi,
- reg_enable_miso => reg_stat_enable_sst_miso,
- reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_mosi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_sst_miso,
-
- sdp_info => sdp_info,
- gn_id => gn_id,
- eth_src_mac => stat_eth_src_mac,
- ip_src_addr => stat_ip_src_addr,
- udp_src_port => sst_udp_src_port
- );
- END GENERATE;
-
-
- -----------------------------------------------------------------------------
- -- node_sdp_correlator (XSUB)
- -----------------------------------------------------------------------------
- gen_use_xsub : IF c_revision_select.use_xsub GENERATE
- u_xsub : ENTITY lofar2_sdp_lib.node_sdp_correlator
- GENERIC MAP(
- g_sim => g_sim,
- g_P_sq => c_revision_select.P_sq
- )
- PORT MAP(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => fsub_sosi_arr,
-
- xst_udp_sosi => udp_tx_sosi_arr(1),
- xst_udp_siso => udp_tx_siso_arr(1),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
- reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
- reg_crosslets_info_mosi => reg_crosslets_info_mosi,
- reg_crosslets_info_miso => reg_crosslets_info_miso,
- reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
- reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
- ram_st_xsq_mosi => ram_st_xsq_mosi,
- ram_st_xsq_miso => ram_st_xsq_miso,
-
- reg_stat_enable_mosi => reg_stat_enable_xst_mosi,
- reg_stat_enable_miso => reg_stat_enable_xst_miso,
- reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_xst_mosi,
- reg_stat_hdr_dat_miso => reg_stat_hdr_dat_xst_miso,
-
- sdp_info => sdp_info,
- gn_id => gn_id,
- stat_eth_src_mac => stat_eth_src_mac,
- stat_ip_src_addr => stat_ip_src_addr,
- stat_udp_src_port => xst_udp_src_port
- );
- END GENERATE;
-
- -----------------------------------------------------------------------------
- -- nof beamsets node_sdp_beamformers (BF)
- -----------------------------------------------------------------------------
- gen_use_bf : IF c_revision_select.use_bf GENERATE
- -- Beamformers
- gen_bf : FOR beamset_id IN 0 TO c_sdp_N_beamsets-1 GENERATE
- u_bf : ENTITY lofar2_sdp_lib.node_sdp_beamformer
- GENERIC MAP(
- g_sim => g_sim,
- g_beamset_id => beamset_id,
- g_scope_selected_beamlet => g_scope_selected_subband
- )
- PORT MAP(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => fsub_sosi_arr,
- bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
- bf_udp_siso => bf_udp_siso_arr(beamset_id),
- bst_udp_sosi => udp_tx_sosi_arr(2+ beamset_id),
- bst_udp_siso => udp_tx_siso_arr(2+ beamset_id),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(beamset_id),
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(beamset_id),
- ram_bf_weights_mosi => ram_bf_weights_mosi_arr(beamset_id),
- ram_bf_weights_miso => ram_bf_weights_miso_arr(beamset_id),
- reg_bf_scale_mosi => reg_bf_scale_mosi_arr(beamset_id),
- reg_bf_scale_miso => reg_bf_scale_miso_arr(beamset_id),
- reg_hdr_dat_mosi => reg_hdr_dat_mosi_arr(beamset_id),
- reg_hdr_dat_miso => reg_hdr_dat_miso_arr(beamset_id),
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi_arr(beamset_id),
- reg_dp_xonoff_miso => reg_dp_xonoff_miso_arr(beamset_id),
- ram_st_bst_mosi => ram_st_bst_mosi_arr(beamset_id),
- ram_st_bst_miso => ram_st_bst_miso_arr(beamset_id),
- reg_stat_enable_mosi => reg_stat_enable_bst_mosi_arr(beamset_id),
- reg_stat_enable_miso => reg_stat_enable_bst_miso_arr(beamset_id),
- reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_bst_mosi_arr(beamset_id),
- reg_stat_hdr_dat_miso => reg_stat_hdr_dat_bst_miso_arr(beamset_id),
-
- sdp_info => sdp_info,
- gn_id => gn_id,
- eth_src_mac => cep_eth_src_mac,
- ip_src_addr => cep_ip_src_addr,
- udp_src_port => cep_udp_src_port,
- stat_eth_src_mac => stat_eth_src_mac,
- stat_ip_src_addr => stat_ip_src_addr,
- stat_udp_src_port => bst_udp_src_port,
-
- hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id)
- );
-
- END GENERATE;
-
- -- MM multiplexing
- u_mem_mux_ram_ss_ss_wide : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_ss_ss_wide
- )
- PORT MAP (
- mosi => ram_ss_ss_wide_mosi,
- miso => ram_ss_ss_wide_miso,
- mosi_arr => ram_ss_ss_wide_mosi_arr,
- miso_arr => ram_ss_ss_wide_miso_arr
- );
-
- u_mem_mux_ram_bf_weights : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_bf_weights
- )
- PORT MAP (
- mosi => ram_bf_weights_mosi,
- miso => ram_bf_weights_miso,
- mosi_arr => ram_bf_weights_mosi_arr,
- miso_arr => ram_bf_weights_miso_arr
- );
-
- u_mem_mux_reg_bf_scale : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_bf_scale
- )
- PORT MAP (
- mosi => reg_bf_scale_mosi,
- miso => reg_bf_scale_miso,
- mosi_arr => reg_bf_scale_mosi_arr,
- miso_arr => reg_bf_scale_miso_arr
- );
-
- u_mem_mux_reg_hdr_dat : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_hdr_dat
- )
- PORT MAP (
- mosi => reg_hdr_dat_mosi,
- miso => reg_hdr_dat_miso,
- mosi_arr => reg_hdr_dat_mosi_arr,
- miso_arr => reg_hdr_dat_miso_arr
- );
-
- u_mem_mux_reg_dp_xonoff : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_dp_xonoff
- )
- PORT MAP (
- mosi => reg_dp_xonoff_mosi,
- miso => reg_dp_xonoff_miso,
- mosi_arr => reg_dp_xonoff_mosi_arr,
- miso_arr => reg_dp_xonoff_miso_arr
- );
-
- u_mem_mux_ram_st_bst : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_st_bst
- )
- PORT MAP (
- mosi => ram_st_bst_mosi,
- miso => ram_st_bst_miso,
- mosi_arr => ram_st_bst_mosi_arr,
- miso_arr => ram_st_bst_miso_arr
- );
-
- u_mem_mux_reg_stat_enable_bst : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_stat_enable_addr_w
- )
- PORT MAP (
- mosi => reg_stat_enable_bst_mosi,
- miso => reg_stat_enable_bst_miso,
- mosi_arr => reg_stat_enable_bst_mosi_arr,
- miso_arr => reg_stat_enable_bst_miso_arr
- );
-
- u_mem_mux_reg_stat_hdr_dat_bst : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_stat_hdr_dat_addr_w
- )
- PORT MAP (
- mosi => reg_stat_hdr_dat_bst_mosi,
- miso => reg_stat_hdr_dat_bst_miso,
- mosi_arr => reg_stat_hdr_dat_bst_mosi_arr,
- miso_arr => reg_stat_hdr_dat_bst_miso_arr
- );
-
- -----------------------------------------------------------------------------
- -- DP MUX
- -----------------------------------------------------------------------------
- -- Assign hdr_fields to nw_10GbE for ARP/PING functionality. Only the fields:
- -- eth_src_mac, ip_src_addr and ip_dst_addr are used. Which are identical for
- -- both beamsets.
- nw_10GbE_hdr_fields_in_arr(0) <= bf_10GbE_hdr_fields_out_arr(0);
-
- u_dp_mux : ENTITY dp_lib.dp_mux
- GENERIC MAP (
- g_nof_input => c_sdp_N_beamsets,
- g_sel_ctrl_invert => TRUE,
- g_fifo_size => array_init(0,c_sdp_N_beamsets), --no FIFO used but must match g_nof_input
- g_fifo_fill => array_init(0,c_sdp_N_beamsets) --no FIFO used but must match g_nof_input
- )
- PORT MAP (
- clk => dp_clk,
- rst => dp_rst,
-
- snk_in_arr => bf_udp_sosi_arr,
- snk_out_arr => bf_udp_siso_arr,
-
- src_out => nw_10gbe_snk_in_arr(0),
- src_in => nw_10gbe_snk_out_arr(0)
- );
-
- ---------------
- -- nw_10GbE
- ---------------
- u_nw_10GbE: ENTITY nw_10GbE_lib.nw_10GbE
- GENERIC MAP (
- g_technology => g_technology,
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_10GbE_offload_streams,
- g_direction => "TX_RX",
- g_tx_fifo_fill => c_fifo_tx_fill,
- g_tx_fifo_size => c_fifo_tx_size,
- g_ip_hdr_field_arr => c_sdp_cep_hdr_field_arr
-
- )
- PORT MAP (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312,
- tr_ref_clk_156 => tr_ref_clk_156,
- tr_ref_rst_156 => tr_ref_rst_156,
-
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mac_mosi => reg_nw_10GbE_mac_mosi,
- reg_mac_miso => reg_nw_10GbE_mac_miso,
-
- reg_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
- reg_eth10g_miso => reg_nw_10GbE_eth10g_miso,
-
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
-
- src_out_arr => nw_10gbe_src_out_arr,
- src_in_arr => nw_10gbe_src_in_arr,
-
- snk_out_arr => nw_10gbe_snk_out_arr,
- snk_in_arr => nw_10gbe_snk_in_arr,
-
- -- Serial IO
- serial_tx_arr => unb2_board_front_io_serial_tx_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0),
- serial_rx_arr => unb2_board_front_io_serial_rx_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0),
-
- hdr_fields_in_arr => nw_10GbE_hdr_fields_in_arr
- );
- END GENERATE;
-
-----------------------------------------------------------------------------
-- Interface : 10GbE
-----------------------------------------------------------------------------
@@ -1161,29 +816,9 @@ BEGIN
QSFP_LED => QSFP_LED
);
- ---------
- -- PLL
- ---------
- u_tech_pll_xgmii_mac_clocks : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
- GENERIC MAP (
- g_technology => g_technology
- )
- PORT MAP (
- refclk_644 => SA_CLK,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => OPEN
- );
-
------------
-- LEDs
------------
- unb2b_board_qsfp_leds_tx_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) <= nw_10gbe_snk_out_arr;
- unb2b_board_qsfp_leds_tx_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) <= nw_10gbe_snk_in_arr;
- unb2b_board_qsfp_leds_rx_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) <= nw_10gbe_src_out_arr;
-
u_front_led : ENTITY unb2b_board_lib.unb2b_board_qsfp_leds
GENERIC MAP (
g_sim => g_sim,
@@ -1197,11 +832,9 @@ BEGIN
green_led_arr => qsfp_green_led_arr,
red_led_arr => qsfp_red_led_arr,
- tx_siso_arr => unb2b_board_qsfp_leds_tx_siso_arr,
- tx_sosi_arr => unb2b_board_qsfp_leds_tx_sosi_arr,
- rx_sosi_arr => unb2b_board_qsfp_leds_rx_sosi_arr
+ tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
+ tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
+ rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
);
-
-
END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index 01eded088e51e68dc9d9440f268f0ca389260c00..e0ec6e62de04ecc0ccf238b673762acbd6f07454 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -479,9 +479,7 @@ BEGIN
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
- pio_pps_address_export => reg_ppsh_mosi.address(0 DOWNTO 0),
--- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
pio_pps_read_export => reg_ppsh_mosi.rd,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index 461075358e25bed8e93cef89b6783e17d3a64ca5..181b0649ce2ec4ba52ea38891fdbb873192a6a20 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -62,7 +62,7 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
pio_jesd_ctrl_reset_export : out std_logic; -- export
pio_jesd_ctrl_write_export : out std_logic; -- export
pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
pio_pps_clk_export : out std_logic; -- export
pio_pps_read_export : out std_logic; -- export
pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_hdl_components.txt b/applications/lofar2/doc/prestudy/station2_sdp_hdl_components.txt
index 86d425c6093b5ff9422589b1dcfc389045216be6..3499fd5fbbb8aab21490ef20541163e2c888c6fe 100755
--- a/applications/lofar2/doc/prestudy/station2_sdp_hdl_components.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_hdl_components.txt
@@ -142,260 +142,270 @@ inputs have the same 64 bit sync and BSN.
*******************************************************************************
Assumptions:
-- Per input the Rx packets arrive in order
+- Done: Per input the Rx packets arrive in order
. a packet contains one or more blocks, on the ring every packet contains one block
-- Only allow correct blocks to enter the FPGA processing
+- Done: Only allow correct blocks to enter the FPGA processing
. the block validation is based on Rx packet CRC and BSN at sync
-- Usage schemes:
- . N = 2 inputs aligner with 1 local data and 1 remote data
- . N > 2 inputs aligner with 1 local data and N-1 remote data
- . N >=2 inputs aligner with 0 local data and N remote data (not used on ring, but was used in
+- Done: Usage schemes:
+ . Ignore: N = 2 inputs aligner with 1 local data and 1 remote data
+ . Ignore: N > 2 inputs aligner with 1 local data and N-1 remote data
+ . Ignore: N >=2 inputs aligner with 0 local data and N remote data (not used on ring, but was used in
APERTIF)
- . Treat all inputs equal, so no special role for a local input to suit more general usage
-- The local sync and BSN sources on all FPGAs are synchronous, to avoid additional BSN latency
+ . Do not: Treat all inputs equal, so no special role for a local input to suit more general usage.
+ . Done: Allow using input 0 as reference ouput. This can be a functional local input or an
+ artificial local input.
+- Done: The local sync and BSN sources on all FPGAs are synchronous, to avoid additional BSN latency
between inputs.
-- Static input enable or disable via M&C
- - it is possible to enable or disable any combination of inputs
- - if all inputs are disabled then the output stops.
- - if the input enable or disable setting is changed, then the BSN aligner restarts trying to
+- Done: Static input enable or disable via M&C
+ - Done: it is possible to enable or disable any combination of inputs
+ - Done: if all inputs are disabled then the output stops.
+ - Ignore: if the input enable or disable setting is changed, then the BSN aligner restarts trying to
achieve alignment.
- - disabled inputs are output with zero or flagged data
- - for the ring with 1 local and 1 remote input the static input enable/disable supports the
+ - Done: disabled inputs are output with zero or flagged data
+ - Ignore: for the ring with 1 local and 1 remote input the static input enable/disable supports the
align modes:
. disabled,
. local only,
. remote only,
. local and remote
-- Input latency:
- . the input latencies are fixed by design, so inputs have a maximum BSN latency g_bsn_latency
+- Done: Input latency:
+ . Done: the input latencies are fixed by design, so inputs have a maximum BSN latency g_bsn_latency
that is fixed and that does not have to be programmable via M&C.
- . If all hops on the ring are active then the total latency will be (N-1)*t_hop, where t_hop is
+ . Ignore: If all hops on the ring are active then the total latency will be (N-1)*t_hop, where t_hop is
the transport latency of each hop. The total transport latency on the ring is (N-1)*t_hop.
The total ring latency is covered by g_bsn_latency > (N-1)*t_hop.
-- Lost input blocks:
- . accept that the corresponding output is lost too, or output filler block to replace lost block
- . should not cause subsequent blocks to get lost too
- . must not induce a burst of output blocks due output catch up after late lost block detection
- . If often blocks on one input get lost, then it is not acceptable that the output is lost.
- - insert filler block to replace the lost input blocks, or
- - support dynamic input enable/disable control
-- Only output correct blocks, either with the received input block or with flagged filler block
-- The output passes on the sync and therefore it does not have to pass on the BSN
-- The output should support flow control to:
- . smoothen bursts (only an issue with remote drive output)
- . provide output throttling (requires output FIFOs or data blocks that have sufficient gaps)
-- Stopped input:
- . If after some block periods (e.g. g_bsn_latency) there is no more block pending at any input,
+- Done: Lost input blocks:
+ . Ignore: accept that the corresponding output is lost too, or output filler block to replace lost block
+ . Done: should not cause subsequent blocks to get lost too
+ . Done: must not induce a burst of output blocks due output catch up after late lost block detection
+ . Done: If often blocks on one input get lost, then it is not acceptable that the output is lost.
+ - Done: insert filler block to replace the lost input blocks, or
+ - Do not: support dynamic input enable/disable control
+- Done: Only output correct blocks, either with the received input block or with flagged filler block
+- Done: The output passes on the sync and should also pass on BSN to be able to identify lost blocks
+- Done: The output should support flow control to:
+ . Done: smoothen bursts (only an issue with remote drive output)
+ . Ignore: provide output throttling (requires output FIFOs or data blocks that have sufficient gaps)
+- Done: Stopped input:
+ . Ignore: If after some block periods (e.g. g_bsn_latency) there is no more block pending at any input,
then the output stops and the BSN aligner should restart trying to achieve alignment.
-Notes:
-- In LOFAR and APERTIF the BSN aligner does loose more blocks due to input flush and realign
-- a BSN aligner can align at any BSN, using a sync aligner that can only align at the sync, would
+Done: Notes:
+- Done: In LOFAR and APERTIF the BSN aligner does loose more blocks due to input flush and realign
+- Done: a BSN aligner can align at any BSN, using a sync aligner that can only align at the sync, would
cause loosing an entire sync interval to realign, which is not acceptable
-- in APERTIF the sync_checker looses entire sync intervals to ensure filled sync intervals
-- In LOFAR and APERTIF the output is driven by the remote input to add minimal latency, however
+- Ignore: in APERTIF the sync_checker looses entire sync intervals to ensure filled sync intervals
+- Done: In LOFAR and APERTIF the output is driven by the remote input to add minimal latency, however
this results in loosing more packets and having to realign if input packets get lost.
-- In dp_bsn_align the artifical local data stream was used to ensure that the output block size
+- Ignore: In dp_bsn_align the artifical local data stream was used to ensure that the output block size
was correct, by using extra CRC checking (ETH CRC and DP CRC) and store and forward in Rx it is
already certain that only correct input packets arrive at the BSN aligner input. Therefore an
artifical local data stream is not needed.
Design options:
-- Lost packet detection
- . Rely on next received packet:
+- Done: Lost packet detection
+ . Do not: Rely on next received packet:
- check per input that the BSN increments +1
- requires a timeout or overflow detection on other inputs to detect a burst of lost packets
- after a burst of lost packets, typically the output cannot catch up anymore, so then the BSN
aligner needs to flush its input buffer and restart.
- . Per packet using a local block reference.
+ . Done: Per packet using a local block reference.
The local block reference is offset by at least g_bsn_latency relative to the local BSN
source, to ensure that all inputs should have a new block pending for output. This is
possible, because the input latencies are static and within a fixed range:
- in circular buffer the Wr flag for the lost block remains unset
- in FIFO by no pending input or pending input with higher BSN then current output BSN
- ==> Design decision:
- - Use local block reference to define when to detect lost packets, because one lost block
+ ==> Done: Design decision:
+ - Done: Use local block reference to define when to detect lost packets, because one lost block
should not cause subsequent blocks to get lost too.
-- Output driven by remote input block arrival or by local block reference
- . in case of 1 remote input, the remote input does not need a FIFO if it drives the output
- . in case of > 1 remote input, then the remote inputs also requires FIFOs
- . using local input increases the latency from remote input to output, because fixed to the
+- Done: Output driven by remote input block arrival or by local block reference
+ . Ignore: in case of 1 remote input, the remote input does not need a FIFO if it drives the output
+ . Ignore: in case of > 1 remote input, then the remote inputs also requires FIFOs
+ . Ignore: using local input increases the latency from remote input to output, because fixed to the
T_sub grid
- . using local input at T_sub grid avoids bursts, this can also be handled using flow control
+ . Done: using local input at T_sub grid avoids bursts, this can also be handled using flow control
. with local input driving the output the assumption is that if the local input has M packets,
then all remote inputs will have delivered at least one frame, so there should be a sop
pending from all.
- . if there is no local input, then an artifical local input can be derived when BSN is equal on
+ . Done: if there is no local input, then an artifical local input can be derived when BSN is equal on
all enabled remote inputs.
- . if remote input is lost, then entire output is lost if remote drives output, because there is
+ . Ingore: if remote input is lost, then entire output is lost if remote drives output, because there is
not enough spare time to still output the other input packets
- . For remote driven output a slot can be output when for all active inputs there is a block.
+ . Done: For remote driven output a slot can be output when for all active inputs there is a block.
However if one or a series of packets got lost, then the other inputs will overflow. Hence
remote driven output needs a timeout to keep the output running, so a form of local driven
output. Hence to avoid additional packet loss on other inputs or of subsequent packets in time
it is necessary to have a local driven output. Therefore using a remote driven output is not
feasible.
- ==> Design decision:
+ ==> Done: Design decision:
- Use local block reference to define when aligned blocks should be output, because one lost
block should not cause subsequent blocks to get lost too, which is more important then
adding minimal latency and potentially saving BSN aligner input buffer memory.
-- Generation of local block reference to define the output pace:
- . During initial input alignment it is important that all active inputs are indeed active, because together they
+- Done: Generation of local block reference to define the output pace:
+ . Ignore: During initial input alignment it is important that all active inputs are indeed active, because together they
determine the latency difference between inputs. After initial alignment the data output can continue at at a
fixed rate, driven by a local block reference:
- - The local input or the remote input with the least latency could be used as local output block reference,
+ - Do not: The local input or the remote input with the least latency could be used as local output block reference,
because (N-1)*d << 1. This requires having a local input or detecting the closest remote input.
- - Alternatively a dedicated local block reference can be started with a certain time offset can be started
+ - Ignore: Alternatively a dedicated local block reference can be started with a certain time offset can be started
after achieving input alignment. The time offset sets a margin that ensures that at subsequent block
refererence pulses all inputs will have a new block pending if the block is not lost.
- ==> Design decision:
- - Generate local block reference when initial BSN alignment has been achieved and start it with a certain
+ ==> Done: Design decision:
+ - Do not: Generate local block reference when initial BSN alignment has been achieved and start it with a certain
fixed offset.
+ Done: Alternatively start local block reference input with a certain fixed offset that is
+ fixed to the local sync, assuming that the inputs have started at that sync too.
+ This avoids the complication of having to wait for initial BSN alignment, but may
+ introduce some more latency.
-- Filler data insertion
- . Whether to drop a block or to replace it by a filler block depends on the application
+- Done: Filler data insertion
+ . Ignore: Whether to drop a block or to replace it by a filler block depends on the application
- for BF drop all inputs, because beam is affected
- for XC insert filler data, because visibilities of active inputs are still correct.
- for the output via the Network insert filler data to keep the output at the nominal rate, such that
the destination can distinguish between data blocks that got lost inside Station and packet loss on
the Network.
- . Filler blocks can be flagged using a sosi.channel bit as flag
- . Filler data can be:
+ . Done: Filler blocks can be flagged using a sosi.channel bit as flag
+ . Done: Filler data can be:
- undefined
- forced to zero
- random with similar noise level,
- flagged data using most negative integer in real data
- flagged data most negative integer in complex real part and imag part (or use imag part as cause identifier).
- ==> Design decision:
- - Replace lost blocks by filler blocks, to preserve the nominal output rate
- - Flag the filler block via a sosi.channel bit, to distinguish the block
- - Forced the filler data to some constant dependent on a generic, to support transparant operation
- in e.g. an adder where x + 0 = x or a multiplier where x * 1 = x, or to support flagging per data
- value using most negative integer value.
+ ==> Done: Design decision:
+ - Done: Replace lost blocks by filler blocks, to preserve the nominal output rate
+ - Done: Flag the filler block via a sosi.channel bit, to distinguish the block
+ - Done: Forced the filler data to some constant dependent on a generic, to support transparant operation
+ in e.g. an adder where x + 0 = x or a multiplier where x * 0 = 0 or x * 1 = x, or to support flagging
+ per data value using most negative integer value.
-. dynamic input enable/disable in case of lost packets
- - Scheme:
- . Fine per packet scheme:
+. Done: dynamic input enable/disable in case of lost packets
+ - Ignore: Scheme:
+ . Ignore: Fine per packet scheme:
- Input packets arrive every block period, remote packets can arrive anywhere within a block period,
- If one input stops, then g_sop_timeout occurs in s_align and then that input could be dynamically disabled in s_xoff.
Inputs can dynamically be enabled if they arrive within two block periods, in s_align.
- too nervous, too difficult to debug and monitor
- . Coarse per sync interval scheme:
+ . Ignore: Coarse per sync interval scheme:
- if an input has no lost packets during one (or more) sync interval then it can be dynamically enabled for the next sync interval
- if an input has lost packets during one (or more) sync interval then it can be dynamically disabled for the next sync interval
- This is a suitable scheme because it does not react too fast and it can be monitored via M&C.
- Define number of sync intervals for dynamic input control as a generic
- preferred because it is less active and easier to monitor
- - Is dynamic input enable/disable necessary if a lost packet does not affect next packets?
- . If lost data is replaced by filler data, then only static input enable/disable is necessary, because if an input
+ - Ignore: Is dynamic input enable/disable necessary if a lost packet does not affect next packets?
+ . Ignore: If lost data is replaced by filler data, then only static input enable/disable is necessary, because if an input
becomes inactive it will be flagged and the output can still continue.
- . If lost data causes all inputs to be discarded, then dynamic input enable/disable may be useful to avoid that a
+ . Ignore: If lost data causes all inputs to be discarded, then dynamic input enable/disable may be useful to avoid that a
single input causes all output to stop.
- ==> Design decision:
- - It is not necessary to support dynamic input enable/disable, because lost blocks are replaced by filler blocks.
+ ==> Done: Design decision:
+ - Done:It is not necessary to support dynamic input enable/disable, because lost blocks are replaced by filler blocks.
-. Treat all inputs equal or use local input stream as reference to achieve input alignment:
- - using the local data stream as reference stream can benefit from the fact that the local data stream has no
+. Done: Treat all inputs equal or use local input stream as reference to achieve input alignment:
+ - Done: using the local data stream as reference stream can benefit from the fact that the local data stream has no
packet loss, because internally in the FPGA logic is error free.
- - treating all streams equal is more general and also works when static input enable/disable disables the local
+ - Done: treating all streams equal is more general and also works when static input enable/disable disables the local
input.
- ==> Design decision:
- - Treat all inputs equal. Do not make use of the fact that the ring has a local input. In this way the BSN
+ ==> Done: Design decision:
+ - Done: Treat all inputs equal. Do not make use of the fact that the ring has a local input. In this way the BSN
aligner can also work when there are only remote inputs.
-. sync aligner instead of BSN aligner
- - Using the sosi.sync one packet lost causes whole interval lost, this is too much impact.
+. Done: sync aligner instead of BSN aligner
+ - Done: Using the sosi.sync one packet lost causes whole interval lost, this is too much impact.
- ==> Design decision:
- Do not make or use a dp_sync_aligner, because loosing an entire sync interval is not acceptable.
+ ==> Done:Design decision:
+ Done: Do not make or use a dp_sync_aligner, because loosing an entire sync interval is not acceptable.
-. Assume circular buffer:
- - advantage:
+. Done: Assume circular buffer:
+ - Done: advantage:
. direct access to each word in block
. no need to flush blocks, status bit per block tells whether it is filled
- - buffer is filled and read after certain latency, because then all remote packets should have arrived
+ - Done: buffer is filled and read after certain latency, because then all remote packets should have arrived
. provide CP for active input streams, is this needed ?
- - use MM interface to read from head column (with block for all parallel streams)
- - provide mm to dp component with bsn aligner (= dp_block_from_mm ?)
- - provide MP for nof lost = nof filler blocks / stream ?
- . err at eop indicates lost = filler data, sosi_info could have eop at sop like with crosslets_info
+ - Done: use MM interface to read from head column (with block for all parallel streams)
+ - Done: provide mm to dp component with bsn aligner (= dp_block_from_mm ?)
+ - - Done: provide MP for nof lost = nof filler blocks / stream ?
+ . Done: use channel field MSbit to indicate filler data at sop, sosi_info could have eop at sop like
+ with crosslets_info
+
. Initial alignment:
- - Assume the received packets on the inputs contain one block per packet.
- The maximum input latency between blocks from two inputs is g_bsn_latency number of block periods. If the
+ - Ignore: Assume the received packets on the inputs contain one block per packet.
+ Ignore: The maximum input latency between blocks from two inputs is g_bsn_latency number of block periods. If the
maximum input latency is less than one block period, then use g_bsn_latency = 1.
- Assume that all inputs are active and that all inputs start with empty input buffers. At each input packets
+ Do not: Assume that all inputs are active and that all inputs start with empty input buffers. At each input packets
arrive and fill the input buffers.
- The minimum size of the total input buffer memory is g_nof_inputs * g_bsn_latency blocks, because then
- initial alignment can be declared as soon as there is a block pending in the input buffers with the same
- BSN at all inputs.
- After initial alignment the alignment can be maintained by using a local block reference to time the
- subsequent output of aligned input blocks.
- As long as at least one input buffer still has blocks then output can continue using filler blocks. The
- local block reference ensures that the buffers will read empty if they do not get new input, this ensures
- that any input in the buffers can still be output at the correct instant. If all buffers are empty then
- input realignment is needed.
-
- - The initial alignment becomes easier if:
+ . Done: The minimum size of the total input buffer memory is g_nof_inputs * g_bsn_latency blocks, because then
+ initial alignment can be declared as soon as there is a block pending in the input buffers with the same
+ BSN at all inputs.
+ . Do not: After initial alignment the alignment can be maintained by using a local block reference to time the
+ subsequent output of aligned input blocks.
+ . Done: As long as at least one input buffer still has blocks then output can continue using filler blocks. The
+ local block reference ensures that the buffers will read empty if they do not get new input, this ensures
+ that any input in the buffers can still be output at the correct instant. If all buffers are empty then
+ input realignment is needed.
+
+ - Done: The alignment becomes easier if:
- . it is not done on the entire 64 bit BSN, but only on a periodic fraction r of the BSN,
- . the periodic BSN has a period that is a power of 2, so r = BSN[R-1:0].
- . it is not done on any BSN, but only on a certain periodic BSN marked by an align_sync pulse at r = 0.
+ . Done: it is not done on the entire 64 bit BSN, but only on a periodic fraction r of the BSN,
+ . Done: the periodic BSN has a period that is a power of 2, so r = BSN[R-1:0].
+ . Ignore: it is not done on any BSN, but only on a certain periodic BSN marked by an align_sync pulse at r = 0.
- The advantage of using a BSN fraction is that it smaller to handle and that it can be used
+ Done: The advantage of using a BSN fraction is that it smaller to handle and that it can be used
as index to a block in the input buffer. The fraction r of the BSN must be unique over the maximum input
latency, so r >= g_bsn_latency. The calculation of the BSN fraction r becomes easier, by choosing a fraction
that is a power of 2, so r = 2**ceil_log2(g_bsn_latency), to avoid integer division. The BSN fraction then
- follows directly from the R = log2(r) LSbits of the BSN, so r = BSN[R-1:0]. The advantange of detecting the
- alignment only at a certain periodic BSN is that the initial block index is then fixed at a certain r,
- choose r = 0. it is convenient to mark the periodic BSN fraction at r = 0 by a sync pulse that is called the
- align_sync.
- The align_sync is only used within the BSN aligner. If alignment fails on an align_sync, due to a lost
- packet, then the intial alignment retries on the next align_sync. The minimal period of the align_sync
- must be large enough to ensure that the input buffers will only contain corresponding align_sync and no
- align_sync from different intervals. Hence the align_sync period must be > BSN latency + buffer size.
- Without align_sync the buffer would need to be twice as large to ensure unambigous detection of alignment.
+ follows directly from the R = log2(r) LSbits of the BSN, so r = BSN[R-1:0].
+ Ignore: The advantange of detecting the alignment only at a certain periodic BSN is that the initial block
+ index is then fixed at a certain r, choose r = 0. it is convenient to mark the periodic BSN fraction at
+ r = 0 by a sync pulse that is called the align_sync.
+ Ignore: The align_sync is only used within the BSN aligner. If alignment fails on an align_sync, due to a lost
+ packet, then the intial alignment retries on the next align_sync.
+ Not true: The minimal period of the align_sync must be large enough to ensure that the input buffers will only contain
+ corresponding align_sync and no align_sync from different intervals. Hence the align_sync period must be
+ > BSN latency + buffer size.
+ Not true: Without align_sync the buffer would need to be twice as large to ensure unambigous detection of alignment.
The align_sync period must be short enough to have a fast initial alignment. The 1 s sync interval could
be used as align_sync, but in LOFAR2.0 the 1 s sync BSN period is not a power of two and differs by 1 per
sync interval, so the sync appears at different block indices. Furthermore a 1 s period is relatively long,
using a dedicated and much shorter align_sync period allows fast initial alignment.
- - For the ring the latency depends on the number of hops. Therefore require that initial BSN alignment is achieved
+ - Ignore: For the ring the latency depends on the number of hops. Therefore require that initial BSN alignment is achieved
with all active input as defined by M&C, to ensure that the total input latency at each node on the ring is
determined by the nominal operation.
- ==> Design decision:
- - Use input buffer size > g_bsn_latency to compensate for the maximum BSN latency difference between inputs
- - Use an align_sync period > g_bsn_latency + buffer size to start initial alignment and to ensure,
+ ==> Done: Design decision:
+ - Done: Use input buffer size > g_bsn_latency to compensate for the maximum BSN latency difference between inputs
+ - Do not: Use an align_sync period > g_bsn_latency + buffer size to start initial alignment and to ensure,
together with the validation of the BSN at sync, the unambigous detection of input alignment on the same BSN
-. Input buffer type
+. Done: Input buffer type
The input buffer can be structured as:
- - a circular buffer that can be accessed at any address, or
- - a FIFO buffer that is used first in first out.
+ - Done: a circular buffer that can be accessed at any address, or
+ - Do not: a FIFO buffer that is used first in first out.
+ Done/ignore:
In a circular buffer each input block will occupy a slot that is identified by the block index r. For each slot
there is a write (Wr) flag that is set when the block is written and cleared when the block is read for output
or discarded. The slots in the circular buffer have the fixed block size, so therefore the sop and eop of the
@@ -414,7 +424,7 @@ Design options:
3 4 5 6 7 A 1 2 . . . W W . . 3 4 W . 3 4 5 W 3 4 5 6 W W 5 6 7 A W 6 7 0 1 W 7
2 3 4 5 6 7 A 1 . . W . . . 2 W W . 2 3 4 W 2 3 4 5 W 3 4 5 6 W W 5 6 7 0 W 6 7
R R
-
+ Do not:
In a FIFO buffer each input block is written at the first free location, so in order of arrival. A lost packet
does not show in the FIFO, so therefore the block index r needs to be passed along with the block through the
FIFO and checked at the output. It is convenient to pass on the sop and eop information with the block through
@@ -433,43 +443,43 @@ Design options:
2 3 4 5 6 7 A 1 . . . . . . . . . . . . . . . . . . . . . . . . W . . . W . . .
R R
- Both the buffers need to pass on the sync information per block, to allow timestamp recovery from Station BSN
+ Ignore:Both the buffers need to pass on the sync information per block, to allow timestamp recovery from Station BSN
for the BSN aligner output.
- The aspects of a circular buffer are:
- - can handle out-of-order data, because it uses the BSN fraction as slot index. However on the ring in SDP all
+ Done: The aspects of a circular buffer are:
+ - Done: can handle out-of-order data, because it uses the BSN fraction as slot index. However on the ring in SDP all
data will be in order.
- - if initial alignment fails it automatically retries on the next align_sync.
- - the BSN must be continuous and incrementing, because then the remainder of the BSN / buffer size can
+ - Ignore: if initial alignment fails it automatically retries on the next align_sync.
+ - Done: the BSN must be continuous and incrementing, because then the remainder of the BSN / buffer size can
be used as Wr pointer.
- - to avoid integer division of the Station BSN the buffer size needs to be a power of 2
+ - Done: to avoid integer division of the Station BSN the buffer size needs to be a power of 2
- The aspects of a FIFO buffer are:
- - during initital alignment lost packets on one input will cause other inputs to overflow.
- - FIFO overflow can occur due to lost packets on an other input or when the initial alignment started while
+ Not used: The aspects of a FIFO buffer are:
+ - Ignore: during initital alignment lost packets on one input will cause other inputs to overflow.
+ - Ignore: FIFO overflow can occur due to lost packets on an other input or when the initial alignment started while
align_sync from the different inputs are arriving. The align_sync period needs to be large enough to
ensure that at a next attempt all align_sync will be for the corresponding BSN. The overflow requires a
restart of the initial alignment by flushing the FIFOs.
- - easy to use a buffer size that is not a power of 2, because the block index is not used as Wr pointer index.
+ - Ignore: easy to use a buffer size that is not a power of 2, because the block index is not used as Wr pointer index.
Using a buffer size that is not a power of 2 can be significant to save RAM.
- - Passing on the BSN fraction r via the FIFO may increase the number RAM, dependent on whether the combination
+ - Ignore: Passing on the BSN fraction r via the FIFO may increase the number RAM, dependent on whether the combination
of data, sop, eop, sync, align_sync and r just fits in a multiple of the maximum data with of a block RAM
- - The BSN index does not have to be incrementing, but is must be unique per BSN latency interval
+ - Ignore: The BSN index does not have to be incrementing, but is must be unique per BSN latency interval
-- Input / output control
- . The BSN aligner can operate independently per input / output. The only interaction between inputs is needed
+- Ignore: Input / output control
+ . Ignore: The BSN aligner can operate independently per input / output. The only interaction between inputs is needed
to detect that all inputs have a pending align_sync. The local block reference for block output can be
shared for all outputs, or replicated per output.
- . The 1 s sync does not have to be checked at the outputs, because if the sync is present on one output, then
+ . Ignore: The 1 s sync does not have to be checked at the outputs, because if the sync is present on one output, then
it will be present on all outputs.
- Flushing:
- . Circular buffer:
+ . Done: Circular buffer:
- Clearing a Wr flag or all Wr flags is much faster than flush reading a FIFO.
- . FIFO buffer:
+ . Ignore: FIFO buffer:
- flush per packet or flush until empty?
- flush per input per input or flush all inputs?
- flush by reading, or by reset or by moving a Rd pointer
@@ -487,22 +497,22 @@ Design options:
corresponded to the lost packet will need to be discarded anyway, because there is no time to output them still.
- also useful to know BSNs at FIFO inputs? --> No, because FIFO packet count can be used to detect pending FIFO overflow.
-. Keep input buffers outside or inside BSN aligner component.
- - for inputs with more latency the buffer can be smaller, this is easier to control with external buffers,
+. Ignore: Keep input buffers outside or inside BSN aligner component.
+ - Ignore: for inputs with more latency the buffer can be smaller, this is easier to control with external buffers,
each input may have different g_bsn_latency, so then each input also has different align timeout, align_sync
interval and input FIFO size.
- - if the BSN aligner relies on FIFO input information, then it is better to have the FIFOs inside.
+ - Ignore: if the BSN aligner relies on FIFO input information, then it is better to have the FIFOs inside.
-- Fast integer division
+- Ignore: Fast integer division
. Modulo 2**n - 1 can be calculated efficiently for binary numbers, by adding the n-bit digit parts. Similar as
mpdulo 3 (= (10-1)/3) can be calculated by adding the decimal digits.
- . Modulo n for constant n can be calculated efficiently suing multiplication by 1/n. The 1/n fraction must be
+ . Modulo n for constant n can be calculated efficiently using multiplication by 1/n. The 1/n fraction must be
represented with sufficient accuracy to determine the remainder. This implies using a 50 bit multiplier,
because the Station BSN is 50 bit.
-. Circular buffers on CEP
+. Done: Circular buffers on CEP
On CEP the beamlet data is written into a circular buffer based on the time stamp. A flag indicates whether data in the
circular buffer is valid. The size of the circular buffer is in the order of hundreds of ms to cover the distance latency
of the international stations. An array of tupples lists the lenght of continuous blocks in the circular buffer, and
@@ -511,7 +521,7 @@ Design options:
also flags the initial channel data that is disturbed after a gap.
-. State machine for circular buffer
+. Ignore: State machine for circular buffer
all:
Receive and monitor input
Derive align_sync from input BSN
@@ -536,7 +546,7 @@ Design options:
output one block, use filler data for lost blocks, clear Wr flag of slot and increment Rd pointer --> s_sop
-. State machine for FIFO buffer
+. Do not: State machine for FIFO buffer
all:
Receive and monitor input
Derive align_sync from input BSN
@@ -559,7 +569,7 @@ Design options:
else
output one block, use filler data for lost blocks --> s_sop
- ==> Design decision:
+ ==> Done: Design decision:
The circular buffer and FIFO are similar. The slight preference is to use a circular buffer, because it
handles overflow automatically and if the maximum input BSN latency is close to a power of 2, then the
RAM usage of the circular buffer is near optimal, because it does not need to pass on the sop, eop and
@@ -567,7 +577,7 @@ Design options:
-Obsolete investigations:
+Ignore: Obsolete investigations:
. APERTIF BSN max/min scheme of dp_bsn_align.vhd core:
- State machine
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_m_and_c.txt b/applications/lofar2/doc/prestudy/station2_sdp_m_and_c.txt
index 65b134f8b4b61b6fea6866d814b58da3bf2f4f14..c3caa48420577f11a63bae87f23026680f7acb19 100755
--- a/applications/lofar2/doc/prestudy/station2_sdp_m_and_c.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_m_and_c.txt
@@ -17,11 +17,17 @@ may provide a monitoring point that allows the master to monitor the progress. O
events that originate in the device it may be necessary to use the publish-subscribe pattern, whereby
the slave self-generates an event message.
-The Station Control (SC) distinguishes between Control and Monitoring and Control (M&C). The Control in SC determines the behaviour of the Station in time. Via M&C the SC can control the Station Digital Processor (SDP) and monitor whether SDP behaves as expected. The SC uses OPC-UA over TCP/IP as standard Station M&C access interface. From SDP point of view all data access points are considered part of SDP M&C, however from SC point of view only a subset of these SDP M&C data points are part of Station M&C, and these are defined in the ICD SC-SDP.
-The SC M&C of SDP concerns two seperate parts:
+The Station Control (SC) distinguishes between Control and Monitoring and Control (M&C). The Control
+in SC determines the behaviour of the Station in time. Via M&C the SC can control the Station Digital
+Processor (SDP) and monitor whether SDP behaves as expected. The SC uses OPC-UA over TCP/IP as standard
+Station M&C access interface. From SDP point of view all data access points are considered part of
+SDP M&C, however from SC point of view only a subset of these SDP M&C data points are part of Station
+M&C, and these are defined in the ICD SC-SDP. The SC M&C of SDP concerns two seperate parts:
* The SDP Hardware is controlled via OPC-UA in the Control subrack in the STCA (STCACO).
-* The SDP Firmware is controlled via OPC-UA in the SDP Translator (SDPT). The complete memory map of all data access points in the SDP Firmware is defined by a configuration file that can be read from the SDP Firmware.
+* The SDP Firmware is controlled via OPC-UA in the SDP Translator (SDPT). The complete memory map of
+ all data access points in the SDP Firmware is defined by a configuration file that can be read from
+ the SDP Firmware.
*******************************************************************************
* M&C of SDP firmware
@@ -41,7 +47,14 @@ Relevant L2 requirements for SDP monitoring points (BH):
* Update scheme for the beamlet weigths
*******************************************************************************
-For the beamformer weights an update period of about once every 4.5 s is fast enough for all astronomical observations [AD-2f] --> BH partioniong rationale for LOFAR2-4392. In LOFAR1 the beamlet weights were applied at every pulse per second (PPS), so every 1 s [RD-8]. The required update rate of the beamlet weigths depends on the beamlet pointing, however all beamlet weigths are controlled as a set, and the beamlets may point in any direction, so therefore the update rate needs to be at least once every 4.5 s. Using a faster update rate makes the beamformer more robust to occasionally loosing an update, because then the previous weigths will still apply well. Table 3.1 lists beamlet weight update schemes that are all suitable for a LOFAR2.0 Station.
+For the beamformer weights an update period of about once every 4.5 s is fast enough for all
+astronomical observations [AD-2f] --> BH partioniong rationale for LOFAR2-4392. In LOFAR1 the beamlet
+weights were applied at every pulse per second (PPS), so every 1 s [RD-8]. The required update rate
+of the beamlet weigths depends on the beamlet pointing, however all beamlet weigths are controlled
+as a set, and the beamlets may point in any direction, so therefore the update rate needs to be at
+least once every 4.5 s. Using a faster update rate makes the beamformer more robust to occasionally
+loosing an update, because then the previous weigths will still apply well. Table 3.1 lists beamlet
+weight update schemes that are all suitable for a LOFAR2.0 Station.
Table Possible beamlet weigths update scheme options for the SC-SDP ICD
@@ -52,13 +65,20 @@ Option Beamlet weights update scheme SDP weigths memory
Comparison of the beamlet weigths update schemes in Table:
-* The advantage of scheme A and C compared to scheme B of LOFAR is that they are less time critica, because they are not tight to thefixed 1 s grid of the PPS.
-* The advantage of scheme A compared to scheme B and C is that it takes less weights memory in SDP, but the weights memory is not a critical resource for SDP
-* The advantage of scheme C compared to scheme A is that the weights can be send in advance, which relaxes the real time constraints on the SC to about 4.5 s.
+* The advantage of scheme A and C compared to scheme B of LOFAR is that they are less time critica,
+ because they are not tight to the fixed 1 s grid of the PPS.
+* The advantage of scheme A compared to scheme B and C is that it takes less weights memory in SDP,
+ but the weights memory is not a critical resource for SDP
+* The advantage of scheme C compared to scheme A is that the weights can be send in advance, which
+ relaxes the real time constraints on the SC to about 4.5 s.
-All schemes in Table can be applied via the SDP Translator as well as via the bypass control path. Scheme C is the most relaxed regarding the real time constrains on the SC and scheme C is quite feasible to realize in the SDP Firmware. Therefore assume that the SC-SDP ICD will specify using scheme C to update the beamlet weights (note that in [AD-2f] a mix of scheme A and scheme B was proposed, so SC sends control every 1 s and SDP applies immediately when received).
+All schemes in Table can be applied via the SDP Translator as well as via the bypass control path.
+Scheme C is the most relaxed regarding the real time constrains on the SC and scheme C is quite
+feasible to realize in the SDP Firmware. Therefore assume that the SC-SDP ICD will specify using
+scheme C to update the beamlet weights (note that in [AD-2f] a mix of scheme A and scheme B was
+proposed, so SC sends control every 1 s and SDP applies immediately when received).
-Design decision: Use option C.
+Design decision: Use option C. --> No, we use schema A because it is simplest and sufficient.
*******************************************************************************
@@ -97,8 +117,8 @@ FPGAs in parallel. The synchronous M&C can be for a single PPS instant or for ev
PPS and then read the monitoring to ensure that it relates to the same interval on all FPGAs.
- Use single event BSN timestamp scheduler
- . Gemini M&C protocol does not have timestamp activated control yet, therefore use separate BSN scheduler
- control point.
+ . Gemini M&C protocol does not have timestamp activated control yet, therefore use separate BSN
+ scheduler control point.
. SCU can read the statistics after the scheduled BSN
. The next integration lasts until the next scheduled BSN
. The programmable interval allows arbitrary intergration intervals, which avoid the need for the
@@ -197,7 +217,8 @@ Behaviour of the data points:
. Sync, dual page monitor, periodic event latch sum values and restart integration at every sosi.sync
- ST_SST
- . SYnc, dual page control, periodic event page swap at sync when last value was written (so only then swap)
+ . Sync, dual page control, periodic event page swap at sync when last value was written (so only
+ then swap)
- DP_FRINGE_STOP_OFFSET
*******************************************************************************
@@ -208,7 +229,8 @@ Behaviour of the data points:
[2] TCP = Transmission Control Protocol (RFC 793)
[3] UDP = User Datagram Protocol (RFC 768)
-TCP is a connection oriented protocol and is used when the data transfer needs to be intact and complete (e.g. files).
+TCP is a connection oriented protocol and is used when the data transfer needs to be intact and
+complete (e.g. files).
- retransmit corrupt or lost datagrams
- remove duplicate datagrams
@@ -216,7 +238,9 @@ TCP is a connection oriented protocol and is used when the data transfer needs t
- rate adaption dependent on the throughput capacity of the network and the receiver
- fragmentation of application data into datagrams [1]
-UDP is a transaction oriented and connectionless protocol and is used when the data transfer needs low latency and lost data may remain lost (e.g. video). The data interface to the application is discrete packets.
+UDP is a transaction oriented and connectionless protocol and is used when the data transfer needs
+low latency and lost data may remain lost (e.g. video). The data interface to the application is
+discrete packets.
IP takes care of:
@@ -231,7 +255,11 @@ Ethernet
- medium access control
-A socket pair identifies both ends of a connection, i.e. the virtual circuit [3]. For UDP the end-to-end connection identified by the source MAC, IP and UDP port tuple and destination MAC, IP and UDP port is sufficient, because UDP operates per datagram [3]. For TCP in addition a connection needs to be setup, because TCP needs to maintain the state of multiple datagrams that are communicated [2].
+A socket pair identifies both ends of a connection, i.e. the virtual circuit [3]. For UDP the
+end-to-end connection identified by the source MAC, IP and UDP port tuple and destination MAC,
+IP and UDP port is sufficient, because UDP operates per datagram [3]. For TCP in addition a
+connection needs to be setup, because TCP needs to maintain the state of multiple datagrams
+that are communicated [2].
To make a reliable transport protocol involves:
@@ -248,7 +276,8 @@ MM transaction
Verify flash
- using readback is necessary with UCP due to that it uses a MM-DP fifo.
-- the transaction from FPGA to flash on UniBoard should preferrably have been readback already for each write request.
+- the transaction from FPGA to flash on UniBoard should preferrably have been readback already
+ for each write request.
*******************************************************************************
* Conclusion:
@@ -257,5 +286,5 @@ Verify flash
- Identify casue of error preferrably via a single monitoring point
- With proper monitoring no test time is needed
- Support writing status fields in a test mode for SW - FW interface testing
-- Use 1 s sync interval of PPS to time period M&C events for all. Optionally support a local BSN scheduler
- for the XST.
+- Use 1 s sync interval of PPS to time period M&C events for all. Optionally support a local
+ BSN scheduler for the XST.
diff --git a/applications/lofar2/doc/prestudy/vhdl_explained.txt b/applications/lofar2/doc/prestudy/vhdl_explained.txt
index d8175f7f62c5d9ccca751e0fd32cc5e760649c3d..9140f745e434b49e9a814b4830dc5f8eb27e751f 100644
--- a/applications/lofar2/doc/prestudy/vhdl_explained.txt
+++ b/applications/lofar2/doc/prestudy/vhdl_explained.txt
@@ -10,7 +10,25 @@ IF x = 3 THEN
y <= x;
END IF;
-Maakt dat y een latch wordt. Je moet een ELSE y <= 0 END IF; toevoegen, of beginnen met een default assignment y <= 0; en dan de IF - END IF;
+Maakt dat y een latch wordt. Je moet een ELSE y <= 0 END IF; toevoegen, of beginnen met een default assignment y <= 0; en dan de IF - END IF; Dus:
+
+a <= 0
+IF b THEN
+ a<= 1
+END IF
+
+is hetzelfde als:
+
+IF b THEN
+ a<= 1
+ELSE
+ a <= 0
+END IF
+
+Mijn voorkeur is meestal om de eerste manier te gebruiken, omdat je dan daar al de default assignments doet.
+
+In process met IF of ELSIF rising_edge() moet juist geen ELSE, omdat je daar juist wel wilt dat er een flipflop gegenereerd zal worden. De synthesis compiler snapt dat.
+Een latch en een flipflop zin beide single bit geheugens, maar we moeten alleen flipflops maken.
3) Complete sensitivity list
diff --git a/applications/lofar2/images/images.txt b/applications/lofar2/images/images.txt
index 29135b8ae552db29d9b56d622121a6c8b0bbe813..2ee374ed6d6bc4b67bc5cc73e2479310637d6635 100644
--- a/applications/lofar2/images/images.txt
+++ b/applications/lofar2/images/images.txt
@@ -8,4 +8,4 @@ lofar2_unb2b_sdp_station_fsub-rbc8dc7f66 | 2021-06-23 | R vd Walle
lofar2_unb2b_sdp_station_bf-rc125dfd6d | 2021-04-21 | R vd Walle | See $UPE_GEAR/peripherals/tc_lofar2_unb2b_beamformer.py
lofar2_unb2b_sdp_station_bf-r087d98be6 | 2021-06-14 | R vd Walle | See $UPE_GEAR/peripherals/tc_lofar2_unb2b_beamformer.py
lofar2_unb2b_sdp_station_xsub_one-r087d98be6 | 2021-06-14 | R vd Walle |
-
+unb2b_minimal-rce6b96eed | 2021-08-26 | P. Donker | unb2b_minimal with new mmap, rbf maid with option --unb2_factory
diff --git a/applications/lofar2/images/unb2b_minimal-rce6b96eed.tar.gz b/applications/lofar2/images/unb2b_minimal-rce6b96eed.tar.gz
new file mode 100644
index 0000000000000000000000000000000000000000..1ffeaade50d0a5729d27c1e134430bcb84a93b9c
Binary files /dev/null and b/applications/lofar2/images/unb2b_minimal-rce6b96eed.tar.gz differ
diff --git a/applications/lofar2/libraries/sdp/hdllib.cfg b/applications/lofar2/libraries/sdp/hdllib.cfg
index c4922d48959a7f833f7a037362781c0d9727b380..3ffb4a50f6bc0119df4d202cf2ebfe4c5fd688b4 100644
--- a/applications/lofar2/libraries/sdp/hdllib.cfg
+++ b/applications/lofar2/libraries/sdp/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = lofar2_sdp
hdl_library_clause_name = lofar2_sdp_lib
-hdl_lib_uses_synth = common dp wpfb rTwoSDF filter si st reorder technology mm dp diag aduh tech_jesd204b tr_10GbE
+hdl_lib_uses_synth = common dp wpfb rTwoSDF filter si st reorder technology tech_pll mm dp diag aduh tech_jesd204b nw_10GbE eth
hdl_lib_uses_sim =
hdl_lib_technology =
@@ -19,6 +19,7 @@ synth_files =
src/vhdl/node_sdp_filterbank.vhd
src/vhdl/node_sdp_beamformer.vhd
src/vhdl/node_sdp_correlator.vhd
+ src/vhdl/sdp_station.vhd
test_bench_files =
tb/vhdl/tb_sdp_info.vhd
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
index ff65bd028369c3506fe83e4e120ddacb57fe6b12..2f74ef1528571469ec7352232ea0016c810e57a8 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
@@ -110,9 +110,9 @@ ARCHITECTURE str OF node_sdp_beamformer IS
SIGNAL local_bf_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL bf_sum_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL bf_out_sosi : t_dp_sosi := c_dp_sosi_rst;
- SIGNAL scope_local_bf_sosi_arr : t_dp_sosi_integer_arr(c_sdp_N_pol-1 DOWNTO 0);
- SIGNAL scope_bf_sum_sosi_arr : t_dp_sosi_integer_arr(c_sdp_N_pol-1 DOWNTO 0);
- SIGNAL scope_bf_out_sosi_arr : t_dp_sosi_integer_arr(c_sdp_N_pol-1 DOWNTO 0);
+ SIGNAL scope_local_bf_sosi_arr : t_dp_sosi_integer_arr(c_sdp_N_pol_bf-1 DOWNTO 0);
+ SIGNAL scope_bf_sum_sosi_arr : t_dp_sosi_integer_arr(c_sdp_N_pol_bf-1 DOWNTO 0);
+ SIGNAL scope_bf_out_sosi_arr : t_dp_sosi_integer_arr(c_sdp_N_pol_bf-1 DOWNTO 0);
SIGNAL beamlet_scale : STD_LOGIC_VECTOR(c_sdp_W_beamlet_scale-1 DOWNTO 0);
BEGIN
---------------------------------------------------------------
@@ -237,7 +237,7 @@ BEGIN
---------------------------------------------------------------
u_beamlet_stats : ENTITY st_lib.st_sst
GENERIC MAP(
- g_nof_stat => c_sdp_S_sub_bf*c_sdp_N_pol,
+ g_nof_stat => c_sdp_S_sub_bf*c_sdp_N_pol_bf,
g_in_data_w => c_sdp_W_beamlet_sum,
g_stat_data_w => c_longword_w,
g_stat_data_sz => c_longword_sz/c_word_sz
@@ -320,7 +320,7 @@ BEGIN
g_sim => g_sim,
g_selection => g_scope_selected_beamlet,
g_nof_input => 1,
- g_n_deinterleave => c_sdp_N_pol,
+ g_n_deinterleave => c_sdp_N_pol_bf,
g_dat_w => c_sdp_W_beamlet_sum
)
PORT MAP (
@@ -335,7 +335,7 @@ BEGIN
g_sim => g_sim,
g_selection => g_scope_selected_beamlet,
g_nof_input => 1,
- g_n_deinterleave => c_sdp_N_pol,
+ g_n_deinterleave => c_sdp_N_pol_bf,
g_dat_w => c_sdp_W_beamlet_sum
)
@@ -351,7 +351,7 @@ BEGIN
g_sim => g_sim,
g_selection => g_scope_selected_beamlet,
g_nof_input => 1,
- g_n_deinterleave => c_sdp_N_pol,
+ g_n_deinterleave => c_sdp_N_pol_bf,
g_dat_w => c_sdp_W_beamlet
)
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
index f1cdb3465b719aba7a7802067a0d3eff5d4329e4..2f75f2f098ace38313417f95651dfd84db0232e0 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
@@ -64,8 +64,8 @@ ARCHITECTURE str OF sdp_beamformer_local IS
CONSTANT c_complex_adder_sum_w : NATURAL := c_sdp_W_bf_product + ceil_log2(c_sdp_S_pn);
- SIGNAL sub_sosi_arr : t_dp_sosi_arr(c_sdp_N_pol*c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL bf_weights_out_sosi_arr : t_dp_sosi_arr(c_sdp_N_pol*c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL sub_sosi_arr : t_dp_sosi_arr(c_sdp_N_pol_bf*c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL bf_weights_out_sosi_arr : t_dp_sosi_arr(c_sdp_N_pol_bf*c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL bf_weights_x_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL bf_weights_y_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL deinterleaved_x_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
@@ -79,9 +79,9 @@ BEGIN
---------------------------------------------------------------
-- COPY INPUT STERAMS FOR X AND Y POLARIZATION PATHS
---------------------------------------------------------------
- gen_pol : FOR N_pol IN 0 TO c_sdp_N_pol-1 GENERATE
+ gen_pol : FOR N_pol_bf IN 0 TO c_sdp_N_pol_bf-1 GENERATE
gen_pfb : FOR P_pfb IN 0 TO c_sdp_P_pfb-1 GENERATE
- sub_sosi_arr(N_pol*c_sdp_P_pfb + P_pfb) <= in_sosi_arr(P_pfb);
+ sub_sosi_arr(N_pol_bf * c_sdp_P_pfb + P_pfb) <= in_sosi_arr(P_pfb);
END GENERATE;
END GENERATE;
@@ -169,7 +169,7 @@ BEGIN
gen_interleave : FOR I IN 0 TO c_sdp_S_pn-1 GENERATE
u_dp_interleave : ENTITY dp_lib.dp_interleave_n_to_one
GENERIC MAP(
- g_nof_inputs => c_sdp_N_pol
+ g_nof_inputs => c_sdp_N_pol_bf
)
PORT MAP(
rst => dp_rst,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
index 229ca24f7ea55d1f21704cc8d4138c8fe3339121..0b868af821c25a614814cb356f9f93a6fbadeadf 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
@@ -48,8 +48,8 @@ ENTITY sdp_bf_weights IS
dp_clk : IN STD_LOGIC;
dp_rst : IN STD_LOGIC;
- in_sosi_arr : IN t_dp_sosi_arr(c_sdp_N_pol * c_sdp_P_pfb-1 DOWNTO 0);
- out_sosi_arr : OUT t_dp_sosi_arr(c_sdp_N_pol * c_sdp_P_pfb-1 DOWNTO 0);
+ in_sosi_arr : IN t_dp_sosi_arr(c_sdp_N_pol_bf * c_sdp_P_pfb-1 DOWNTO 0);
+ out_sosi_arr : OUT t_dp_sosi_arr(c_sdp_N_pol_bf * c_sdp_P_pfb-1 DOWNTO 0);
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
@@ -72,9 +72,9 @@ BEGIN
-- Counter
---------------------------------------------------------------
-- The BF weigths per PN are stored as
- -- (cint16)subband_weights[N_pol][S_pn/Q_fft]_[Q_fft][S_sub_bf], but have
+ -- (cint16)bf_weights[N_pol_bf][S_pn/Q_fft]_[Q_fft][S_sub_bf], but have
-- to be applied according the subband data order
- -- [N_pol][S_pn/Q_fft]_[S_sub_bf][Q_fft]. Therefore this counter
+ -- [N_pol_bf][S_pn/Q_fft]_[S_sub_bf][Q_fft]. Therefore this counter
-- has to account for this difference in order.
p_cnt : PROCESS(dp_clk, dp_rst)
VARIABLE v_Q_fft, v_S_sub_bf : NATURAL;
@@ -111,7 +111,7 @@ BEGIN
---------------------------------------------------------------
u_mms_dp_gain_serial_arr : ENTITY dp_lib.mms_dp_gain_serial_arr
GENERIC MAP (
- g_nof_streams => c_sdp_N_pol * c_sdp_P_pfb,
+ g_nof_streams => c_sdp_N_pol_bf * c_sdp_P_pfb,
g_nof_gains => c_sdp_Q_fft * c_sdp_S_sub_bf,
g_complex_data => TRUE,
g_complex_gain => TRUE,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 235e5a8cc89744f128a594c683b8ac824aa1ab5a..7296acce10bc4df20ebdd7aad5e7f35d4c3f5913 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -73,6 +73,7 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_N_fft : NATURAL := 1024;
CONSTANT c_sdp_N_pn_lb : NATURAL := 16;
CONSTANT c_sdp_N_pol : NATURAL := 2;
+ CONSTANT c_sdp_N_pol_bf : NATURAL := 2;
CONSTANT c_sdp_N_sub : NATURAL := 512;
CONSTANT c_sdp_N_taps : NATURAL := 16;
CONSTANT c_sdp_P_sq : NATURAL := 9;
@@ -113,7 +114,8 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_marker_bst : NATURAL := 66; -- = 0x42 = 'B'
CONSTANT c_sdp_marker_xst : NATURAL := 88; -- = 0x58 = 'X'
- CONSTANT c_sdp_offload_time : NATURAL := 13000; -- from wave window 62855nS / 5nS = 12571 cycles.
+ --CONSTANT c_sdp_offload_time : NATURAL := 13000; -- from wave window 62855nS / 5nS = 12571 cycles.
+ CONSTANT c_sdp_offload_time : NATURAL := 600000;
-- In SDP c_nof_channels = 2**nof_chan = 1 and wb_factor = 1,
@@ -213,7 +215,7 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_cep_udp_src_port_15_8 : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"D0"; -- 15:8, 7:0 = gn_id (= ID[7:0] = backplane[5:0] & node[1:0])
CONSTANT c_sdp_cep_nof_blocks_per_packet : NATURAL := 4;
- CONSTANT c_sdp_cep_nof_beamlets_per_block : NATURAL := c_sdp_N_pol * c_sdp_S_sub_bf;
+ CONSTANT c_sdp_cep_nof_beamlets_per_block : NATURAL := c_sdp_N_pol_bf * c_sdp_S_sub_bf; -- FIXME in L2SDP-471
CONSTANT c_sdp_cep_nof_hdr_fields : NATURAL := 3+12+4+18+1; -- 592b; 9.25 64b words
CONSTANT c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := "101"&"111111111001"&"0111"&"1100"&"00000010"&"000110"&"0"; -- 0=data path, 1=MM controlled TODO
--CONSTANT c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := "100"&"000000010001"&"0100"&"0100"&"00000000"&"101000"&"0"; -- 0=data path, 1=MM controlled TODO
@@ -304,10 +306,10 @@ PACKAGE sdp_pkg is
-- BF MM address widths
CONSTANT c_sdp_reg_sdp_info_addr_w : NATURAL := 4;
CONSTANT c_sdp_ram_ss_ss_wide_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- CONSTANT c_sdp_ram_bf_weights_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_N_pol * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_sdp_ram_bf_weights_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_N_pol_bf * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
CONSTANT c_sdp_reg_bf_scale_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
CONSTANT c_sdp_reg_dp_xonoff_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
- CONSTANT c_sdp_ram_st_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol*(c_longword_sz/c_word_sz));
+ CONSTANT c_sdp_ram_st_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol_bf*(c_longword_sz/c_word_sz));
CONSTANT c_sdp_reg_stat_enable_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_stat_enable_addr_w;
CONSTANT c_sdp_reg_stat_hdr_dat_bst_addr_w: NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_stat_hdr_dat_addr_w;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..15b936c1d5495941c4748df81b6ab6e6d649c810
--- /dev/null
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -0,0 +1,796 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Purpose:
+-- Core design for Lofar2 SDP station
+-- Description:
+-- Combines sdp nodes. Contains the UniBoard2 HW version independent LOFAR2 SDP application code.
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, tech_pll_lib, nw_10gbe_lib, eth_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE work.sdp_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+
+
+ENTITY sdp_station IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_arria10_e1sg;
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_wpfb : t_wpfb := c_sdp_wpfb_subbands;
+ g_bsn_nof_clk_per_sync : NATURAL := c_sdp_f_adc_MHz*10**6; -- Default 200M, overide for short simulation
+ g_scope_selected_subband : NATURAL := 0;
+ g_use_fsub : BOOLEAN := TRUE;
+ g_use_xsub : BOOLEAN := TRUE;
+ g_use_bf : BOOLEAN := TRUE;
+ g_P_sq : NATURAL := 1
+ );
+ PORT (
+ -- System
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC := '0';
+
+ dp_pps : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+
+ -- ID
+ gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
+ this_bck_id : IN STD_LOGIC_VECTOR(6-1 DOWNTO 0);
+ this_chip_id : IN STD_LOGIC_VECTOR(2-1 DOWNTO 0);
+
+ -- Transceiver clocks
+ SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
+
+ -- back transceivers (Note: numbered from 0)
+ JESD204B_SERIAL_DATA : IN STD_LOGIC_VECTOR(c_sdp_S_pn-1 downto 0);
+ -- Connect to the BCK_RX pins in the top wrapper
+ JESD204B_REFCLK : IN STD_LOGIC; -- Connect to BCK_REF_CLK pin in the top level wrapper
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF : IN STD_LOGIC;
+ JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0);
+
+
+ ----------------------------------------------
+ -- UDP Offload
+ ----------------------------------------------
+ udp_tx_sosi_arr : OUT t_dp_sosi_arr(c_eth_nof_udp_ports-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ udp_tx_siso_arr : IN t_dp_siso_arr(c_eth_nof_udp_ports-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+
+ ----------------------------------------------
+ -- 10 GbE
+ ----------------------------------------------
+ reg_nw_10GbE_mac_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_nw_10GbE_mac_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ reg_nw_10GbE_eth10g_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_nw_10GbE_eth10g_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ ----------------------------------------------
+ -- AIT
+ ----------------------------------------------
+ -- JESD
+ jesd204b_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ jesd204b_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- JESD control
+ jesd_ctrl_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ jesd_ctrl_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Shiftram (applies per-antenna delay)
+ reg_dp_shiftram_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_shiftram_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- bsn source
+ reg_bsn_source_v2_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bsn_source_v2_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- bsn scheduler
+ reg_bsn_scheduler_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bsn_scheduler_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- WG
+ reg_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- BSN MONITOR
+ reg_bsn_monitor_input_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bsn_monitor_input_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Data buffer bsn
+ ram_diag_data_buf_bsn_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_diag_data_buf_bsn_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_diag_data_buf_bsn_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_diag_data_buf_bsn_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Aduh statistics monitor
+ reg_aduh_monitor_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_aduh_monitor_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ ----------------------------------------------
+ -- FSUB
+ ----------------------------------------------
+ -- Subband statistics
+ ram_st_sst_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_st_sst_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Spectral Inversion
+ reg_si_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_si_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Filter coefficients
+ ram_fil_coefs_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_fil_coefs_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Equalizer gains
+ ram_equalizer_gains_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_equalizer_gains_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- DP Selector
+ reg_dp_selector_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_selector_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ ----------------------------------------------
+ -- SDP Info
+ ----------------------------------------------
+ reg_sdp_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_sdp_info_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ ----------------------------------------------
+ -- XSUB
+ ----------------------------------------------
+ -- dp_sync_insert_v2
+ reg_dp_sync_insert_v2_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_sync_insert_v2_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- crosslets_info
+ reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_crosslets_info_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- bsn_scheduler_xsub
+ reg_bsn_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bsn_scheduler_xsub_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- st_xsq
+ ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_st_xsq_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ ----------------------------------------------
+ -- BF
+ ----------------------------------------------
+ -- Beamlet Subband Select
+ ram_ss_ss_wide_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_ss_ss_wide_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Local BF bf weights
+ ram_bf_weights_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_bf_weights_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- mms_dp_scale Scale Beamlets
+ reg_bf_scale_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bf_scale_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Beamlet Data Output header fields
+ reg_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_hdr_dat_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Beamlet Data Output xonoff
+ reg_dp_xonoff_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_xonoff_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Beamlet Statistics (BST)
+ ram_st_bst_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_st_bst_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ ----------------------------------------------
+ -- SST
+ ----------------------------------------------
+ -- Statistics Enable
+ reg_stat_enable_sst_mosi : IN t_mem_mosi;
+ reg_stat_enable_sst_miso : OUT t_mem_miso;
+
+ -- Statistics header info
+ reg_stat_hdr_dat_sst_mosi : IN t_mem_mosi;
+ reg_stat_hdr_dat_sst_miso : OUT t_mem_miso;
+
+ ----------------------------------------------
+ -- XST
+ ----------------------------------------------
+ -- Statistics Enable
+ reg_stat_enable_xst_mosi : IN t_mem_mosi;
+ reg_stat_enable_xst_miso : OUT t_mem_miso;
+
+ -- Statistics header info
+ reg_stat_hdr_dat_xst_mosi : IN t_mem_mosi;
+ reg_stat_hdr_dat_xst_miso : OUT t_mem_miso;
+
+ ----------------------------------------------
+ -- BST
+ ----------------------------------------------
+ -- Statistics Enable
+ reg_stat_enable_bst_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_stat_enable_bst_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- Statistics header info
+ reg_stat_hdr_dat_bst_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_stat_hdr_dat_bst_miso : OUT t_mem_miso := c_mem_miso_rst;
+
+ -- QSFP serial
+ unb2_board_front_io_serial_tx_arr : OUT STD_LOGIC_VECTOR(6 * c_quad-1 DOWNTO 0) := (OTHERS => '0');
+ unb2_board_front_io_serial_rx_arr : IN STD_LOGIC_VECTOR(6 * c_quad-1 DOWNTO 0) := (OTHERS => '0');
+
+ -- QSFP LEDS
+ unb2_board_qsfp_leds_tx_sosi_arr : OUT t_dp_sosi_arr(6 * c_quad-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ unb2_board_qsfp_leds_tx_siso_arr : OUT t_dp_siso_arr(6 * c_quad-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ unb2_board_qsfp_leds_rx_sosi_arr : OUT t_dp_sosi_arr(6 * c_quad-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst)
+ );
+END sdp_station;
+
+
+ARCHITECTURE str OF sdp_station IS
+
+ -- 10 GbE Interface
+ CONSTANT c_nof_10GbE_offload_streams : NATURAL := 1;
+ CONSTANT c_nof_blocks_per_packet : NATURAL := 4;
+ CONSTANT c_nof_beamlets_per_block : NATURAL := c_sdp_N_pol * c_sdp_S_sub_bf;
+ CONSTANT c_10GbE_block_size : NATURAL := c_nof_blocks_per_packet * c_nof_beamlets_per_block / 4; -- 4 beamlets fit in 1 64bit longword
+ CONSTANT c_fifo_tx_fill : NATURAL := c_10GbE_block_size;
+ CONSTANT c_fifo_tx_size : NATURAL := c_fifo_tx_fill + 11; -- Make fifo size large enough for adding header.
+
+ -- Address widths of a single MM instance
+ CONSTANT c_addr_w_ram_ss_ss_wide : NATURAL := ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_addr_w_ram_bf_weights : NATURAL := ceil_log2(c_sdp_N_pol * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_addr_w_reg_bf_scale : NATURAL := 1;
+ CONSTANT c_addr_w_reg_hdr_dat : NATURAL := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
+ CONSTANT c_addr_w_reg_dp_xonoff : NATURAL := 1;
+ CONSTANT c_addr_w_ram_st_bst : NATURAL := ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol*(c_longword_sz/c_word_sz));
+
+ -- Read only sdp_info values
+ CONSTANT c_f_adc : STD_LOGIC := '1'; -- '0' => 160M, '1' => 200M
+ CONSTANT c_fsub_type : STD_LOGIC := '0'; -- '0' => critical sampled PFB, '1' => oversampled PFB
+
+ SIGNAL gn_index : NATURAL := 0;
+
+ ----------------------------------------------
+ -- BF
+ ----------------------------------------------
+ -- Beamlet Subband Select
+ SIGNAL ram_ss_ss_wide_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL ram_ss_ss_wide_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+
+ -- Local BF bf weights
+ SIGNAL ram_bf_weights_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL ram_bf_weights_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+
+ -- mms_dp_scale Scale Beamlets
+ SIGNAL reg_bf_scale_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL reg_bf_scale_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+
+ -- Beamlet Data Output header fields
+ SIGNAL reg_hdr_dat_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL reg_hdr_dat_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+
+ -- Beamlet Data Output xonoff
+ SIGNAL reg_dp_xonoff_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL reg_dp_xonoff_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+
+ -- Beamlet Statistics (BST)
+ SIGNAL ram_st_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL ram_st_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+
+ ----------------------------------------------
+ -- BST
+ ----------------------------------------------
+ -- Statistics Enable
+ SIGNAL reg_stat_enable_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL reg_stat_enable_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+
+ -- Statistics header info
+ SIGNAL reg_stat_hdr_dat_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL reg_stat_hdr_dat_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ ----------------------------------------------
+
+ SIGNAL ait_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
+ SIGNAL pfb_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
+ SIGNAL fsub_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
+
+ SIGNAL dp_bsn_source_restart : STD_LOGIC;
+
+ SIGNAL bf_udp_sosi_arr : t_dp_sosi_arr(c_sdp_N_beamsets-1 DOWNTO 0);
+ SIGNAL bf_udp_siso_arr : t_dp_siso_arr(c_sdp_N_beamsets-1 DOWNTO 0);
+ SIGNAL bf_10GbE_hdr_fields_out_arr : t_slv_1024_arr(c_sdp_N_beamsets-1 DOWNTO 0);
+
+ -- 10GbE
+ SIGNAL tr_ref_clk_312 : STD_LOGIC;
+ SIGNAL tr_ref_clk_156 : STD_LOGIC;
+ SIGNAL tr_ref_rst_156 : STD_LOGIC;
+
+
+ SIGNAL nw_10gbe_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL nw_10gbe_snk_out_arr : t_dp_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ SIGNAL nw_10gbe_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL nw_10gbe_src_in_arr : t_dp_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+
+ SIGNAL nw_10GbE_hdr_fields_in_arr : t_slv_1024_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
+
+
+ SIGNAL cep_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
+ SIGNAL cep_ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
+ SIGNAL cep_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+ SIGNAL stat_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
+ SIGNAL stat_ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
+ SIGNAL sst_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+ SIGNAL bst_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+ SIGNAL xst_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
+
+ SIGNAL sdp_info : t_sdp_info := c_sdp_info_rst;
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- SDP Info register
+ -----------------------------------------------------------------------------
+ gn_index <= TO_UINT(gn_id);
+ -- derive MAC, IP and UDP Port
+ cep_eth_src_mac <= c_sdp_cep_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
+ cep_ip_src_addr <= c_sdp_cep_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
+ cep_udp_src_port <= c_sdp_cep_udp_src_port_15_8 & RESIZE_UVEC(gn_id, c_byte_w);
+
+ stat_eth_src_mac <= c_sdp_stat_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
+ stat_ip_src_addr <= c_sdp_stat_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
+ sst_udp_src_port <= c_sdp_sst_udp_src_port_15_8 & RESIZE_UVEC(gn_id, c_byte_w);
+ bst_udp_src_port <= c_sdp_bst_udp_src_port_15_8 & RESIZE_UVEC(gn_id, c_byte_w);
+ xst_udp_src_port <= c_sdp_xst_udp_src_port_15_8 & RESIZE_UVEC(gn_id, c_byte_w);
+
+ u_sdp_info : ENTITY work.sdp_info
+ PORT MAP(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
+
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ reg_mosi => reg_sdp_info_mosi,
+ reg_miso => reg_sdp_info_miso,
+
+ -- inputs from other blocks
+ gn_index => gn_index,
+ f_adc => c_f_adc,
+ fsub_type => c_fsub_type,
+
+ -- sdp info
+ sdp_info => sdp_info
+ );
+
+ -----------------------------------------------------------------------------
+ -- node_adc_input_and_timing (AIT)
+ -- .Contains JESD receiver, bsn source and associated data buffers, diagnostics and statistics
+ -----------------------------------------------------------------------------
+ u_ait: ENTITY work.node_sdp_adc_input_and_timing
+ GENERIC MAP(
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync
+ )
+ PORT MAP(
+ -- clocks and resets
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- mm control buses
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
+ reg_bsn_source_v2_miso => reg_bsn_source_v2_miso,
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+
+ -- Jesd external IOs
+ jesd204b_serial_data => JESD204B_SERIAL_DATA,
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n => JESD204B_SYNC_N,
+
+ -- Streaming data output
+ out_sosi_arr => ait_sosi_arr,
+ dp_bsn_source_restart => dp_bsn_source_restart
+ );
+
+ -----------------------------------------------------------------------------
+ -- node_sdp_filterbank (FSUB)
+ -----------------------------------------------------------------------------
+ gen_use_fsub : IF g_use_fsub GENERATE
+ u_fsub : ENTITY work.node_sdp_filterbank
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_wpfb => g_wpfb,
+ g_scope_selected_subband => g_scope_selected_subband
+ )
+ PORT MAP(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ pfb_sosi_arr => pfb_sosi_arr,
+ fsub_sosi_arr => fsub_sosi_arr,
+ dp_bsn_source_restart => dp_bsn_source_restart,
+
+ sst_udp_sosi => udp_tx_sosi_arr(0),
+ sst_udp_siso => udp_tx_siso_arr(0),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ ram_gains_mosi => ram_equalizer_gains_mosi,
+ ram_gains_miso => ram_equalizer_gains_miso,
+ reg_selector_mosi => reg_dp_selector_mosi,
+ reg_selector_miso => reg_dp_selector_miso,
+
+ reg_enable_mosi => reg_stat_enable_sst_mosi,
+ reg_enable_miso => reg_stat_enable_sst_miso,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_mosi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_sst_miso,
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
+ );
+ END GENERATE;
+
+
+ -----------------------------------------------------------------------------
+ -- node_sdp_correlator (XSUB)
+ -----------------------------------------------------------------------------
+ gen_use_xsub : IF g_use_xsub GENERATE
+ u_xsub : ENTITY work.node_sdp_correlator
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_P_sq => g_P_sq
+ )
+ PORT MAP(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => fsub_sosi_arr,
+
+ xst_udp_sosi => udp_tx_sosi_arr(1),
+ xst_udp_siso => udp_tx_siso_arr(1),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
+ reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
+ reg_crosslets_info_mosi => reg_crosslets_info_mosi,
+ reg_crosslets_info_miso => reg_crosslets_info_miso,
+ reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
+ reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
+ ram_st_xsq_mosi => ram_st_xsq_mosi,
+ ram_st_xsq_miso => ram_st_xsq_miso,
+
+ reg_stat_enable_mosi => reg_stat_enable_xst_mosi,
+ reg_stat_enable_miso => reg_stat_enable_xst_miso,
+ reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_xst_mosi,
+ reg_stat_hdr_dat_miso => reg_stat_hdr_dat_xst_miso,
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ stat_eth_src_mac => stat_eth_src_mac,
+ stat_ip_src_addr => stat_ip_src_addr,
+ stat_udp_src_port => xst_udp_src_port
+ );
+ END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- nof beamsets node_sdp_beamformers (BF)
+ -----------------------------------------------------------------------------
+ gen_use_bf : IF g_use_bf GENERATE
+ -- Beamformers
+ gen_bf : FOR beamset_id IN 0 TO c_sdp_N_beamsets-1 GENERATE
+ u_bf : ENTITY work.node_sdp_beamformer
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_beamset_id => beamset_id,
+ g_scope_selected_beamlet => g_scope_selected_subband
+ )
+ PORT MAP(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => fsub_sosi_arr,
+ bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
+ bf_udp_siso => bf_udp_siso_arr(beamset_id),
+ bst_udp_sosi => udp_tx_sosi_arr(2+ beamset_id),
+ bst_udp_siso => udp_tx_siso_arr(2+ beamset_id),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(beamset_id),
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(beamset_id),
+ ram_bf_weights_mosi => ram_bf_weights_mosi_arr(beamset_id),
+ ram_bf_weights_miso => ram_bf_weights_miso_arr(beamset_id),
+ reg_bf_scale_mosi => reg_bf_scale_mosi_arr(beamset_id),
+ reg_bf_scale_miso => reg_bf_scale_miso_arr(beamset_id),
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi_arr(beamset_id),
+ reg_hdr_dat_miso => reg_hdr_dat_miso_arr(beamset_id),
+ reg_dp_xonoff_mosi => reg_dp_xonoff_mosi_arr(beamset_id),
+ reg_dp_xonoff_miso => reg_dp_xonoff_miso_arr(beamset_id),
+ ram_st_bst_mosi => ram_st_bst_mosi_arr(beamset_id),
+ ram_st_bst_miso => ram_st_bst_miso_arr(beamset_id),
+ reg_stat_enable_mosi => reg_stat_enable_bst_mosi_arr(beamset_id),
+ reg_stat_enable_miso => reg_stat_enable_bst_miso_arr(beamset_id),
+ reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_bst_mosi_arr(beamset_id),
+ reg_stat_hdr_dat_miso => reg_stat_hdr_dat_bst_miso_arr(beamset_id),
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ eth_src_mac => cep_eth_src_mac,
+ ip_src_addr => cep_ip_src_addr,
+ udp_src_port => cep_udp_src_port,
+ stat_eth_src_mac => stat_eth_src_mac,
+ stat_ip_src_addr => stat_ip_src_addr,
+ stat_udp_src_port => bst_udp_src_port,
+
+ hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id)
+ );
+
+ END GENERATE;
+
+ -- MM multiplexing
+ u_mem_mux_ram_ss_ss_wide : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_ss_ss_wide
+ )
+ PORT MAP (
+ mosi => ram_ss_ss_wide_mosi,
+ miso => ram_ss_ss_wide_miso,
+ mosi_arr => ram_ss_ss_wide_mosi_arr,
+ miso_arr => ram_ss_ss_wide_miso_arr
+ );
+
+ u_mem_mux_ram_bf_weights : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_bf_weights
+ )
+ PORT MAP (
+ mosi => ram_bf_weights_mosi,
+ miso => ram_bf_weights_miso,
+ mosi_arr => ram_bf_weights_mosi_arr,
+ miso_arr => ram_bf_weights_miso_arr
+ );
+
+ u_mem_mux_reg_bf_scale : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bf_scale
+ )
+ PORT MAP (
+ mosi => reg_bf_scale_mosi,
+ miso => reg_bf_scale_miso,
+ mosi_arr => reg_bf_scale_mosi_arr,
+ miso_arr => reg_bf_scale_miso_arr
+ );
+
+ u_mem_mux_reg_hdr_dat : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_hdr_dat
+ )
+ PORT MAP (
+ mosi => reg_hdr_dat_mosi,
+ miso => reg_hdr_dat_miso,
+ mosi_arr => reg_hdr_dat_mosi_arr,
+ miso_arr => reg_hdr_dat_miso_arr
+ );
+
+ u_mem_mux_reg_dp_xonoff : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_dp_xonoff
+ )
+ PORT MAP (
+ mosi => reg_dp_xonoff_mosi,
+ miso => reg_dp_xonoff_miso,
+ mosi_arr => reg_dp_xonoff_mosi_arr,
+ miso_arr => reg_dp_xonoff_miso_arr
+ );
+
+ u_mem_mux_ram_st_bst : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_st_bst
+ )
+ PORT MAP (
+ mosi => ram_st_bst_mosi,
+ miso => ram_st_bst_miso,
+ mosi_arr => ram_st_bst_mosi_arr,
+ miso_arr => ram_st_bst_miso_arr
+ );
+
+ u_mem_mux_reg_stat_enable_bst : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_stat_enable_addr_w
+ )
+ PORT MAP (
+ mosi => reg_stat_enable_bst_mosi,
+ miso => reg_stat_enable_bst_miso,
+ mosi_arr => reg_stat_enable_bst_mosi_arr,
+ miso_arr => reg_stat_enable_bst_miso_arr
+ );
+
+ u_mem_mux_reg_stat_hdr_dat_bst : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_stat_hdr_dat_addr_w
+ )
+ PORT MAP (
+ mosi => reg_stat_hdr_dat_bst_mosi,
+ miso => reg_stat_hdr_dat_bst_miso,
+ mosi_arr => reg_stat_hdr_dat_bst_mosi_arr,
+ miso_arr => reg_stat_hdr_dat_bst_miso_arr
+ );
+
+ -----------------------------------------------------------------------------
+ -- DP MUX
+ -----------------------------------------------------------------------------
+ -- Assign hdr_fields to nw_10GbE for ARP/PING functionality. Only the fields:
+ -- eth_src_mac, ip_src_addr and ip_dst_addr are used. Which are identical for
+ -- both beamsets.
+ nw_10GbE_hdr_fields_in_arr(0) <= bf_10GbE_hdr_fields_out_arr(0);
+
+ u_dp_mux : ENTITY dp_lib.dp_mux
+ GENERIC MAP (
+ g_nof_input => c_sdp_N_beamsets,
+ g_sel_ctrl_invert => TRUE,
+ g_fifo_size => array_init(0,c_sdp_N_beamsets), --no FIFO used but must match g_nof_input
+ g_fifo_fill => array_init(0,c_sdp_N_beamsets) --no FIFO used but must match g_nof_input
+ )
+ PORT MAP (
+ clk => dp_clk,
+ rst => dp_rst,
+
+ snk_in_arr => bf_udp_sosi_arr,
+ snk_out_arr => bf_udp_siso_arr,
+
+ src_out => nw_10gbe_snk_in_arr(0),
+ src_in => nw_10gbe_snk_out_arr(0)
+ );
+
+ ---------------
+ -- nw_10GbE
+ ---------------
+ u_nw_10GbE: ENTITY nw_10GbE_lib.nw_10GbE
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_10GbE_offload_streams,
+ g_direction => "TX_RX",
+ g_tx_fifo_fill => c_fifo_tx_fill,
+ g_tx_fifo_size => c_fifo_tx_size,
+ g_ip_hdr_field_arr => c_sdp_cep_hdr_field_arr
+
+ )
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312,
+ tr_ref_clk_156 => tr_ref_clk_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_nw_10GbE_mac_mosi,
+ reg_mac_miso => reg_nw_10GbE_mac_miso,
+
+ reg_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
+ reg_eth10g_miso => reg_nw_10GbE_eth10g_miso,
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+
+ src_out_arr => nw_10gbe_src_out_arr,
+ src_in_arr => nw_10gbe_src_in_arr,
+
+ snk_out_arr => nw_10gbe_snk_out_arr,
+ snk_in_arr => nw_10gbe_snk_in_arr,
+
+ -- Serial IO
+ serial_tx_arr => unb2_board_front_io_serial_tx_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0),
+ serial_rx_arr => unb2_board_front_io_serial_rx_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0),
+
+ hdr_fields_in_arr => nw_10GbE_hdr_fields_in_arr
+ );
+ END GENERATE;
+
+ ---------
+ -- PLL
+ ---------
+ u_tech_pll_xgmii_mac_clocks : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
+ GENERIC MAP (
+ g_technology => g_technology
+ )
+ PORT MAP (
+ refclk_644 => SA_CLK,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => OPEN
+ );
+
+ ------------
+ -- LEDs
+ ------------
+ unb2_board_qsfp_leds_tx_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) <= nw_10gbe_snk_out_arr;
+ unb2_board_qsfp_leds_tx_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) <= nw_10gbe_snk_in_arr;
+ unb2_board_qsfp_leds_rx_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) <= nw_10gbe_src_out_arr;
+
+
+END str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
index 287331749627f658af4d5ffdb785c249e7f54fb2..3824502c0b6e1a0bc7634fc3410a3427631f1988 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
@@ -192,7 +192,7 @@ BEGIN
END IF;
END PROCESS;
- p_control_packet_offload : PROCESS(r, gn_index, in_sosi, trigger, done, dp_header_info)
+ p_control_packet_offload : PROCESS(r, gn_index, in_sosi, trigger, done, dp_header_info, selected_crosslet)
VARIABLE v: t_reg;
BEGIN
v := r;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
index 47d0e1390b2e2ce81898ee294cf60bf51078c686..ad0a102909558615f140a4146699c84693ef9bff 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
@@ -61,7 +61,7 @@ PACKAGE unb2b_board_peripherals_pkg IS
reg_common_adr_w : NATURAL; -- = 1 -- fixed, from c_mem_reg in mms_common_reg
-- pi_ppsh
- reg_ppsh_adr_w : NATURAL; -- = 1 -- fixed, from c_mm_reg in ppsh_reg
+ reg_ppsh_adr_w : NATURAL; -- = 2 -- fixed, from c_mm_reg in ppsh_reg
-- pi_unb_sens
reg_unb_sens_adr_w : NATURAL; -- = 6 -- fixed, from c_mm_reg in unb_sens_reg
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd
index e64925db8956a2f0296f91f6b30f4787eb9938e8..f24eba33ead6e1d13f4a6fc6541fb52296e80094 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd
@@ -61,7 +61,7 @@ PACKAGE unb2c_board_peripherals_pkg IS
reg_common_adr_w : NATURAL; -- = 1 -- fixed, from c_mem_reg in mms_common_reg
-- pi_ppsh
- reg_ppsh_adr_w : NATURAL; -- = 1 -- fixed, from c_mm_reg in ppsh_reg
+ reg_ppsh_adr_w : NATURAL; -- = 2 -- fixed, from c_mm_reg in ppsh_reg
-- pi_unb_sens
reg_unb_sens_adr_w : NATURAL; -- = 6 -- fixed, from c_mm_reg in unb_sens_reg
diff --git a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
index e63d1860dc244929c83b99be41d886fefff7c7cf..158f3cb747fb60b86fb13e8ba917f330920df0d1 100644
--- a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
+++ b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
@@ -462,7 +462,7 @@ architecture str of wpfb_unit_dev is
begin
-- The complete input sosi arry is registered.
- comb : process(r, in_sosi_arr)
+ comb : process(r, in_sosi_arr, dp_bsn_source_restart)
variable v : reg_type;
begin
v := r;
diff --git a/libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd b/libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd
index 39e21de98a90bb33568d11fbeed94e304dc52444..d308e06249db71b1111e2183d43cbd900c416d37 100644
--- a/libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd
+++ b/libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd
@@ -32,13 +32,18 @@ END tb_mms_ppsh;
ARCHITECTURE tb OF tb_mms_ppsh IS
- CONSTANT c_clk_freq : NATURAL := 1000; -- clock frequency in Hz
- CONSTANT c_clk_period : TIME := 1000000 us / c_clk_freq;
- CONSTANT c_pps_period : NATURAL := c_clk_freq; -- 1 s takes c_clk_freq clk cycles
+ CONSTANT c_st_clk_freq : NATURAL := 1000; -- clock frequency in Hz
+ CONSTANT c_st_clk_period : TIME := 1000000 us / c_st_clk_freq;
+ CONSTANT c_mm_clk_period : TIME := c_st_clk_period * 3; -- somewhat slower mm_clk
+ CONSTANT c_pps_period : NATURAL := c_st_clk_freq; -- 1 s takes c_clk_freq clk cycles
+
+ CONSTANT c_cnt_w : NATURAL := ceil_log2(c_st_clk_freq);
SIGNAL tb_end : STD_LOGIC := '0';
- SIGNAL rst : STD_LOGIC := '1';
- SIGNAL clk : STD_LOGIC := '1';
+ SIGNAL mm_rst : STD_LOGIC := '1';
+ SIGNAL mm_clk : STD_LOGIC := '1';
+ SIGNAL st_rst : STD_LOGIC := '1';
+ SIGNAL st_clk : STD_LOGIC := '1';
-- DUT
SIGNAL pps_ext : STD_LOGIC;
@@ -48,7 +53,7 @@ ARCHITECTURE tb OF tb_mms_ppsh IS
SIGNAL reg_miso : t_mem_miso;
-- Verify
- SIGNAL bsn : NATURAL;
+ SIGNAL bsn : NATURAL; -- block sequence number counts seconds
SIGNAL pps_toggle : STD_LOGIC;
SIGNAL pps_stable : STD_LOGIC;
SIGNAL capture_cnt : NATURAL;
@@ -65,8 +70,10 @@ BEGIN
-----------------------------------------------------------------------------
-- Stimuli
-----------------------------------------------------------------------------
- rst <= '1', '0' AFTER 7*c_clk_period;
- clk <= NOT clk OR tb_end AFTER c_clk_period/2;
+ st_rst <= '1', '0' AFTER 7*c_st_clk_period;
+ st_clk <= NOT st_clk OR tb_end AFTER c_st_clk_period/2;
+ mm_rst <= '1', '0' AFTER 7*c_mm_clk_period;
+ mm_clk <= NOT mm_clk OR tb_end AFTER c_mm_clk_period/2;
p_pps_ext : PROCESS
VARIABLE v_pps_period : NATURAL := c_pps_period;
@@ -81,10 +88,10 @@ BEGIN
ELSIF bsn = 69 THEN
v_pps_period := c_pps_period+1;
END IF;
- proc_common_wait_some_cycles(clk, v_pps_period-1);
+ proc_common_wait_some_cycles(st_clk, v_pps_period-1);
pps_ext <= '1';
bsn <= bsn + 1;
- proc_common_wait_some_cycles(clk, 1);
+ proc_common_wait_some_cycles(st_clk, 1);
pps_ext <= '0';
END LOOP;
@@ -94,88 +101,89 @@ BEGIN
p_mm_stimuli : PROCESS
VARIABLE v_word : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
BEGIN
- proc_common_wait_until_low(clk, rst); -- Wait until reset has finished
- proc_common_wait_some_cycles(clk, 10); -- Wait an additional amount of cycles
+ proc_common_wait_until_low(st_clk, st_rst); -- Wait until reset has finished
+ proc_common_wait_until_low(mm_clk, mm_rst); -- Wait until reset has finished
+ proc_common_wait_some_cycles(mm_clk, 10); -- Wait an additional amount of cycles
v_word := '0' & TO_UVEC(c_pps_period, 31); -- capture_edge = '0' = at rising edge
-- expected_cnt = c_pps_period = 1000
- proc_mem_mm_bus_wr(1, v_word, clk, reg_mosi);
+ proc_mem_mm_bus_wr(1, v_word, mm_clk, reg_mosi);
-- Simulate reading PPS status every 10 PPS periods
- proc_common_wait_some_cycles(clk, 10);
+ proc_common_wait_some_cycles(st_clk, 10);
FOR I IN 0 TO 9 LOOP
- proc_common_wait_some_cycles(clk, c_pps_period*10);
+ proc_common_wait_some_cycles(st_clk, c_pps_period*10);
- proc_mem_mm_bus_rd(0, clk, reg_mosi);
- proc_common_wait_some_cycles(clk, 1);
+ proc_mem_mm_bus_rd(0, mm_clk, reg_mosi);
+ proc_common_wait_some_cycles(mm_clk, 1);
pps_toggle <= reg_miso.rddata(31);
pps_stable <= reg_miso.rddata(30);
- capture_cnt <= TO_UINT(reg_miso.rddata(ceil_log2(c_clk_freq)-1 DOWNTO 0));
+ capture_cnt <= TO_UINT(reg_miso.rddata(c_cnt_w-1 DOWNTO 0));
END LOOP;
- -- Simulate reading PPS offset counter every 0.1 PPS periods
- proc_common_wait_some_cycles(clk, 10);
- FOR I IN 0 TO 4 LOOP
- proc_common_wait_some_cycles(clk, c_pps_period/10);
+ -- Simulate reading PPS offset counter every 0.25 PPS periods
+ proc_common_wait_some_cycles(st_clk, 10);
+ FOR I IN 0 TO 40 LOOP
+ proc_common_wait_some_cycles(st_clk, c_pps_period/4);
last_offset_cnt <= offset_cnt;
- proc_mem_mm_bus_rd(2, clk, reg_mosi);
- proc_common_wait_some_cycles(clk, 1);
- offset_cnt <= TO_UINT(reg_miso.rddata(ceil_log2(c_clk_freq)-1 DOWNTO 0));
+ proc_mem_mm_bus_rd(2, mm_clk, reg_mosi);
+ proc_common_wait_some_cycles(mm_clk, 1);
+ offset_cnt <= TO_UINT(reg_miso.rddata(c_cnt_w-1 DOWNTO 0));
END LOOP;
- proc_common_wait_some_cycles(clk, 100);
+ proc_common_wait_some_cycles(st_clk, 100);
tb_end <= '1';
WAIT;
END PROCESS;
p_verify : PROCESS
BEGIN
- proc_common_wait_until_low(clk, rst); -- Wait until reset has finished
- proc_common_wait_some_cycles(clk, 10); -- Wait an additional amount of cycles
+ proc_common_wait_until_low(st_clk, st_rst); -- Wait until reset has finished
+ proc_common_wait_some_cycles(st_clk, 10); -- Wait an additional amount of cycles
- proc_common_wait_some_cycles(clk, c_pps_period/2); -- Verification offset
+ proc_common_wait_some_cycles(st_clk, c_pps_period/2); -- Verification offset
-- 1
- proc_common_wait_some_cycles(clk, c_pps_period*10);
+ proc_common_wait_some_cycles(st_clk, c_pps_period*10);
ASSERT pps_stable='0' REPORT "1) Wrong pps_stable" SEVERITY ERROR;
ASSERT capture_cnt=1000 REPORT "1) Wrong capture_cnt" SEVERITY ERROR;
-- 2
- proc_common_wait_some_cycles(clk, c_pps_period*10);
+ proc_common_wait_some_cycles(st_clk, c_pps_period*10);
ASSERT pps_stable='1' REPORT "2) Wrong pps_stable" SEVERITY ERROR;
ASSERT capture_cnt=1000 REPORT "2) Wrong capture_cnt" SEVERITY ERROR;
-- 3
- proc_common_wait_some_cycles(clk, c_pps_period*10);
+ proc_common_wait_some_cycles(st_clk, c_pps_period*10);
ASSERT pps_stable='0' REPORT "3) Wrong pps_stable" SEVERITY ERROR;
ASSERT capture_cnt=999 REPORT "3) Wrong capture_cnt" SEVERITY ERROR;
-- 4
- proc_common_wait_some_cycles(clk, c_pps_period*10);
+ proc_common_wait_some_cycles(st_clk, c_pps_period*10);
ASSERT pps_stable='0' REPORT "4) Wrong pps_stable" SEVERITY ERROR;
ASSERT capture_cnt=1000 REPORT "4) Wrong capture_cnt" SEVERITY ERROR;
-- 5
- proc_common_wait_some_cycles(clk, c_pps_period*10);
+ proc_common_wait_some_cycles(st_clk, c_pps_period*10);
ASSERT pps_stable='1' REPORT "5) Wrong pps_stable" SEVERITY ERROR;
ASSERT capture_cnt=1000 REPORT "5) Wrong capture_cnt" SEVERITY ERROR;
-- 6
- proc_common_wait_some_cycles(clk, c_pps_period*10);
+ proc_common_wait_some_cycles(st_clk, c_pps_period*10);
ASSERT pps_stable='1' REPORT "6) Wrong pps_stable" SEVERITY ERROR;
ASSERT capture_cnt=1000 REPORT "6) Wrong capture_cnt" SEVERITY ERROR;
-- 7
- proc_common_wait_some_cycles(clk, c_pps_period*10);
+ proc_common_wait_some_cycles(st_clk, c_pps_period*10);
ASSERT pps_stable='0' REPORT "7) Wrong pps_stable" SEVERITY ERROR;
ASSERT capture_cnt=1001 REPORT "7) Wrong capture_cnt" SEVERITY ERROR;
-- 8
- proc_common_wait_some_cycles(clk, c_pps_period*10);
+ proc_common_wait_some_cycles(st_clk, c_pps_period*10);
ASSERT pps_stable='0' REPORT "8) Wrong pps_stable" SEVERITY ERROR;
ASSERT capture_cnt=1000 REPORT "8) Wrong capture_cnt" SEVERITY ERROR;
-- 9
- proc_common_wait_some_cycles(clk, c_pps_period*10);
+ proc_common_wait_some_cycles(st_clk, c_pps_period*10);
ASSERT pps_stable='1' REPORT "9) Wrong pps_stable" SEVERITY ERROR;
ASSERT capture_cnt=1000 REPORT "9) Wrong capture_cnt" SEVERITY ERROR;
-- 10
- proc_common_wait_some_cycles(clk, c_pps_period/10);
+ proc_common_wait_some_cycles(st_clk, c_pps_period/10);
ASSERT offset_cnt=last_offset_cnt REPORT "10) Wrong offset_cnt" SEVERITY ERROR;
-- 11
- proc_common_wait_some_cycles(clk, c_pps_period/10);
+ proc_common_wait_some_cycles(st_clk, c_pps_period/10);
ASSERT offset_cnt=last_offset_cnt REPORT "11) Wrong offset_cnt" SEVERITY ERROR;
WAIT;
END PROCESS;
@@ -187,14 +195,14 @@ BEGIN
dut : ENTITY work.mms_ppsh
GENERIC MAP (
- g_st_clk_freq => c_clk_freq
+ g_st_clk_freq => c_st_clk_freq
)
PORT MAP (
-- Clocks and reset
- mm_rst => rst,
- mm_clk => clk,
- st_rst => rst,
- st_clk => clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
pps_ext => pps_ext,
-- Memory-mapped clock domain
diff --git a/libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd b/libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd
index 4887a8489d1df8bb0245cf12ddb2f6c75c31dbca..2c1e4a9e49f9dc1b8120f4fa3cf1eaa0fddb9cba 100644
--- a/libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd
+++ b/libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd
@@ -33,6 +33,7 @@ ARCHITECTURE tb OF tb_ppsh IS
CONSTANT c_clk_period : TIME := 1000000 us / c_clk_freq;
CONSTANT c_pps_default_period : NATURAL := c_clk_freq; -- 1 s takes c_clk_freq clk cycles
CONSTANT c_pps_skew : TIME := 7*c_clk_period/10;
+ CONSTANT c_cnt_w : NATURAL := ceil_log2(c_clk_freq);
-- The state name tells what kind of test is being done
TYPE t_state_enum IS (
@@ -54,11 +55,15 @@ ARCHITECTURE tb OF tb_ppsh IS
SIGNAL pps_ext : STD_LOGIC;
SIGNAL pps_sys : STD_LOGIC;
SIGNAL pps_toggle : STD_LOGIC;
+ SIGNAL pps_stable : STD_LOGIC;
+ SIGNAL pps_stable_ack : STD_LOGIC := '0';
SIGNAL capture_edge : STD_LOGIC;
- SIGNAL capture_cnt : STD_LOGIC_VECTOR(ceil_log2(c_clk_freq)-1 DOWNTO 0);
- SIGNAL offset_cnt : STD_LOGIC_VECTOR(ceil_log2(c_clk_freq)-1 DOWNTO 0);
+ SIGNAL capture_cnt : STD_LOGIC_VECTOR(c_cnt_w-1 DOWNTO 0);
+ SIGNAL offset_cnt : STD_LOGIC_VECTOR(c_cnt_w-1 DOWNTO 0);
+ SIGNAL expected_cnt : STD_LOGIC_VECTOR(c_cnt_w-1 DOWNTO 0);
-- Verify
+ SIGNAL verify_s : REAL := 0.0; -- provides time line marker for p_verify in Wave Window
BEGIN
@@ -73,13 +78,44 @@ BEGIN
-- Verify that using the falling capture edge indeed does change timing by
-- using a c_pps_skew that is > 0.5 c_clk_period and < c_clk_period
- capture_edge <= '0', '1' AFTER 5000 ms, '0' AFTER 7000 ms;
+ p_capture_edge : PROCESS
+ BEGIN
+ capture_edge <= '0';
+ WAIT FOR 5000 ms;
+ capture_edge <= '1'; -- will be verified by p_verify
+ WAIT FOR 2000 ms;
+ capture_edge <= '0';
+ WAIT;
+ END PROCESS;
+
+ p_verify_pps_stable : PROCESS
+ BEGIN
+ pps_stable_ack <= '0';
+ WAIT FOR 9000 ms; -- wait until p_capture_edge is done
+ IF pps_stable /= '0' THEN
+ REPORT "PPSH : Unexpected pps_stable, should be 0." SEVERITY ERROR;
+ END IF;
+ -- ack PPS stable monitor
+ pps_stable_ack <= '1';
+ WAIT FOR 1*c_clk_period;
+ pps_stable_ack <= '0';
+ WAIT FOR 10 ms;
+ IF pps_stable /= '1' THEN
+ REPORT "PPSH : Unexpected pps_stable, should be 1." SEVERITY ERROR;
+ END IF;
+ WAIT FOR 13000 ms; -- wait until first loop in p_pps_default_period is done
+ IF pps_stable /= '0' THEN
+ REPORT "PPSH : Unexpected pps_stable, should have become 0." SEVERITY ERROR;
+ END IF;
+ WAIT;
+ END PROCESS;
-- Verify the capture_cnt
p_pps_default_period : PROCESS
BEGIN
tb_state <= s_idle;
pps <= '0';
+ expected_cnt <= TO_UVEC(c_pps_default_period, c_cnt_w);
WAIT UNTIL rst='0';
WAIT FOR 10*c_clk_period;
WAIT UNTIL rising_edge(clk); -- get synchronous to clk
@@ -130,8 +166,6 @@ BEGIN
pps <= '0';
WAIT FOR (c_pps_default_period-I)*c_clk_period;
END LOOP;
- -- Missing PPS pulses
- tb_state <= s_missing_pps;
-- End
tb_state <= s_end;
@@ -158,11 +192,14 @@ BEGIN
-- PPS
pps_ext => pps_ext,
pps_sys => pps_sys,
- pps_toggle => pps_toggle,
-- MM control
- capture_edge => capture_edge,
- capture_cnt => capture_cnt,
- offset_cnt => offset_cnt
+ pps_toggle => pps_toggle,
+ pps_stable => pps_stable,
+ pps_stable_ack => pps_stable_ack,
+ capture_edge => capture_edge,
+ capture_cnt => capture_cnt,
+ offset_cnt => offset_cnt,
+ expected_cnt => expected_cnt
);
-----------------------------------------------------------------------------
@@ -187,18 +224,21 @@ BEGIN
IF UNSIGNED(capture_cnt)/=c_clk_freq+1 THEN
REPORT "PPSH : Unexpected capture count value at 6 s." SEVERITY ERROR;
END IF;
+ verify_s <= 6.0;
END IF;
IF (NOW > 7000 ms) AND (NOW <= 7000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=c_clk_freq THEN
REPORT "PPSH : Unexpected capture count value at 7 s." SEVERITY ERROR;
END IF;
+ verify_s <= 7.0;
END IF;
IF (NOW > 8000 ms) AND (NOW <= 8000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=c_clk_freq-1 THEN
REPORT "PPSH : Unexpected capture count value at 8 s." SEVERITY ERROR;
END IF;
+ verify_s <= 8.0;
END IF;
-- Verify external PPS period fluctuations at specific stimuli moments
@@ -206,57 +246,65 @@ BEGIN
IF UNSIGNED(capture_cnt)/=c_clk_freq THEN
REPORT "PPSH : Unexpected capture count value at 10 s." SEVERITY ERROR;
END IF;
+ verify_s <= 10.0;
END IF;
IF (NOW > 22000 ms) AND (NOW <= 22000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=c_clk_freq-1 THEN
REPORT "PPSH : Unexpected capture count value at 22 s." SEVERITY ERROR;
END IF;
+ verify_s <= 22.0;
END IF;
IF (NOW > 25000 ms) AND (NOW <= 25000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=c_clk_freq THEN
REPORT "PPSH : Unexpected capture count value at 25 s." SEVERITY ERROR;
END IF;
+ verify_s <= 25.0;
END IF;
IF (NOW > 28000 ms) AND (NOW <= 28000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=c_clk_freq+1 THEN
REPORT "PPSH : Unexpected capture count value at 28 s." SEVERITY ERROR;
END IF;
+ verify_s <= 28.0;
END IF;
IF (NOW > 30000 ms) AND (NOW <= 30000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=c_clk_freq THEN
REPORT "PPSH : Unexpected capture count value at 30 s." SEVERITY ERROR;
END IF;
+ verify_s <= 30.0;
END IF;
IF (NOW > 35000 ms) AND (NOW <= 35000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=2**capture_cnt'LENGTH-1 THEN
REPORT "PPSH : Unexpected capture count value at 35 s." SEVERITY ERROR;
END IF;
+ verify_s <= 35.0;
END IF;
IF (NOW > 49000 ms) AND (NOW <= 49000 ms + c_clk_period) THEN
IF UNSIGNED(capture_cnt)/=2**capture_cnt'LENGTH-1 THEN
REPORT "PPSH : Unexpected capture count value at 49 s." SEVERITY ERROR;
END IF;
+ verify_s <= 49.0;
END IF;
-- check if offset_cnt is counting
IF (NOW > 7500 ms) AND (NOW <= 7500 ms + c_clk_period) THEN
IF UNSIGNED(offset_cnt)/=475 THEN
- REPORT "PPSH : Unexpected offset count value at 5.5 s." SEVERITY ERROR;
+ REPORT "PPSH : Unexpected offset count value at 7.5 s." SEVERITY ERROR;
END IF;
+ verify_s <= 7.5;
END IF;
IF (NOW > 7700 ms) AND (NOW <= 7700 ms + c_clk_period) THEN
IF UNSIGNED(offset_cnt)/=675 THEN
- REPORT "PPSH : Unexpected offset count value at 5.5 s." SEVERITY ERROR;
+ REPORT "PPSH : Unexpected offset count value at 7.7 s." SEVERITY ERROR;
END IF;
+ verify_s <= 7.7;
END IF;
-
END IF;
END PROCESS;