From f94b6d3784764d604a9398ad7255d5b612f9132b Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Mon, 6 Mar 2017 07:18:55 +0000
Subject: [PATCH] Pass on g_sim via aduh_dd to lvdsh_dd_phs4 to be able to
shorten the locked timeout in lvdsh_dd_phs4_align.
---
.../designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd | 1 +
libraries/io/aduh/src/vhdl/aduh_dd.vhd | 3 +++
libraries/io/aduh/src/vhdl/aduh_quad.vhd | 2 ++
libraries/io/aduh/src/vhdl/mms_aduh_quad.vhd | 2 ++
4 files changed, 8 insertions(+)
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
index be2f3249a5..6dcef5f21f 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
@@ -152,6 +152,7 @@ BEGIN
u_aduh_quad : ENTITY aduh_lib.mms_aduh_quad
GENERIC MAP (
-- General
+ g_sim => g_sim,
g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
-- ADC Interface
g_nof_dp_phs_clk => g_nof_dp_phs_clk,
diff --git a/libraries/io/aduh/src/vhdl/aduh_dd.vhd b/libraries/io/aduh/src/vhdl/aduh_dd.vhd
index 13d838a8b1..ec78a8438a 100644
--- a/libraries/io/aduh/src/vhdl/aduh_dd.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_dd.vhd
@@ -55,6 +55,7 @@ USE work.aduh_dd_pkg.ALL;
ENTITY aduh_dd IS
GENERIC (
+ g_sim : BOOLEAN := FALSE;
g_nof_dp_phs_clk : NATURAL := 1; -- nof dp_phs_clk that can be used to detect the word phase
g_ai : t_c_aduh_dd_ai := c_aduh_dd_ai
);
@@ -260,6 +261,7 @@ BEGIN
u_lvdsh_dd_phs4_ab : ENTITY work.lvdsh_dd_phs4
GENERIC MAP (
+ g_sim => g_sim,
g_wb_factor => c_dp_factor, -- fixed wideband factor = 4
g_nof_dp_phs_clk => g_nof_dp_phs_clk, -- nof dp_phs_clk that can be used to detect lock
g_in_dat_w => c_in_dat_w -- nof PHY data bits
@@ -291,6 +293,7 @@ BEGIN
u_lvdsh_dd_phs4_cd : ENTITY work.lvdsh_dd_phs4
GENERIC MAP (
+ g_sim => g_sim,
g_wb_factor => c_dp_factor, -- fixed wideband factor = 4
g_nof_dp_phs_clk => g_nof_dp_phs_clk, -- nof dp_phs_clk that can be used to detect lock
g_in_dat_w => c_in_dat_w -- nof PHY data bits
diff --git a/libraries/io/aduh/src/vhdl/aduh_quad.vhd b/libraries/io/aduh/src/vhdl/aduh_quad.vhd
index c691542201..27d9e634eb 100644
--- a/libraries/io/aduh/src/vhdl/aduh_quad.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_quad.vhd
@@ -32,6 +32,7 @@ USE work.aduh_dd_pkg.ALL;
ENTITY aduh_quad IS
GENERIC (
-- ADC Interface
+ g_sim : BOOLEAN := FALSE;
g_nof_dp_phs_clk : NATURAL := 1; -- nof dp_phs_clk that can be used to detect the word phase
g_ai : t_c_aduh_dd_ai := c_aduh_dd_ai
);
@@ -99,6 +100,7 @@ BEGIN
u_aduh : ENTITY work.aduh_dd
GENERIC MAP (
+ g_sim => g_sim,
g_nof_dp_phs_clk => g_nof_dp_phs_clk,
g_ai => g_ai
)
diff --git a/libraries/io/aduh/src/vhdl/mms_aduh_quad.vhd b/libraries/io/aduh/src/vhdl/mms_aduh_quad.vhd
index d44b109a3c..e2a7514306 100644
--- a/libraries/io/aduh/src/vhdl/mms_aduh_quad.vhd
+++ b/libraries/io/aduh/src/vhdl/mms_aduh_quad.vhd
@@ -33,6 +33,7 @@ USE work.aduh_dd_pkg.ALL;
ENTITY mms_aduh_quad IS
GENERIC (
-- General
+ g_sim : BOOLEAN := FALSE;
g_cross_clock_domain : BOOLEAN := TRUE; -- use FALSE when mm_clk and dp_clk are the same, else use TRUE to cross the clock domain
-- ADC Interface
g_nof_dp_phs_clk : NATURAL := 1; -- nof dp_phs_clk that can be used to detect the word phase
@@ -145,6 +146,7 @@ BEGIN
u_aduh_quad : ENTITY work.aduh_quad
GENERIC MAP (
-- ADC Interface
+ g_sim => g_sim,
g_nof_dp_phs_clk => g_nof_dp_phs_clk,
g_ai => g_ai
)
--
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