diff --git a/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys b/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
index ef18ec2426cefa5fa72053dc342364dce4b2ab9e..201065eb7e30d3bbbb00ef293d79088d5dbe2bb5 100644
--- a/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
+++ b/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
@@ -12,14 +12,6 @@
element $${FILENAME}
{
}
- element altpll_0
- {
- datum _sortIndex
- {
- value = "2";
- type = "int";
- }
- }
element jtag_uart_0.avalon_jtag_slave
{
datum baseAddress
@@ -32,63 +24,15 @@
{
datum _sortIndex
{
- value = "8";
- type = "int";
- }
- }
- element altpll_0.c0
- {
- datum _clockDomain
- {
- value = "mm_clk";
- type = "String";
- }
- }
- element c0
- {
- datum _sortIndex
- {
- value = "1";
+ value = "6";
type = "int";
}
}
- element altpll_0.c1
- {
- datum _clockDomain
- {
- value = "epcs_clk";
- type = "String";
- }
- }
- element altpll_0.c2
- {
- datum _clockDomain
- {
- value = "tse_clk";
- type = "String";
- }
- }
- element altpll_0.c3
- {
- datum _clockDomain
- {
- value = "dp_clk";
- type = "String";
- }
- }
- element altpll_0.c4
- {
- datum _clockDomain
- {
- value = "cal_reconf_clk";
- type = "String";
- }
- }
element clk_0
{
datum _sortIndex
{
- value = "5";
+ value = "0";
type = "int";
}
}
@@ -96,7 +40,7 @@
{
datum _sortIndex
{
- value = "0";
+ value = "1";
type = "int";
}
}
@@ -112,7 +56,7 @@
{
datum _sortIndex
{
- value = "4";
+ value = "3";
type = "int";
}
datum megawizard_uipreferences
@@ -121,109 +65,104 @@
type = "String";
}
}
- element reg_tr_10GbE.mem
+ element reg_diag_data_buffer.mem
{
datum baseAddress
{
- value = "524288";
+ value = "128";
type = "long";
}
}
- element pio_pps.mem
+ element reg_mmdp_ctrl.mem
{
datum baseAddress
{
- value = "12624";
+ value = "12592";
type = "long";
}
}
- element rom_system_info.mem
+ element reg_dp_offload_tx.mem
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "4096";
+ value = "12512";
type = "long";
}
}
- element pio_system_info.mem
+ element reg_dp_offload_tx_hdr_ovr.mem
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "0";
+ value = "512";
type = "long";
}
}
- element reg_dp_offload_tx_hdr_dat.mem
+ element reg_dpmm_data.mem
{
datum baseAddress
{
- value = "13312";
+ value = "12584";
type = "long";
}
}
- element reg_dpmm_data.mem
+ element reg_diag_bg.mem
{
datum baseAddress
{
- value = "12600";
+ value = "12544";
type = "long";
}
}
- element reg_dpmm_ctrl.mem
+ element reg_dp_offload_rx_hdr_dat.mem
{
datum baseAddress
{
- value = "12592";
+ value = "1024";
type = "long";
}
}
- element reg_bsn_monitor.mem
+ element reg_mmdp_data.mem
{
datum baseAddress
{
- value = "256";
+ value = "12600";
type = "long";
}
}
- element reg_dp_offload_tx.mem
+ element rom_system_info.mem
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "12512";
+ value = "4096";
type = "long";
}
}
- element reg_diag_data_buffer.mem
+ element reg_epcs.mem
{
datum baseAddress
{
- value = "128";
+ value = "12480";
type = "long";
}
}
- element reg_mmdp_ctrl.mem
+ element reg_unb_sens.mem
{
datum baseAddress
{
- value = "12608";
+ value = "12416";
type = "long";
}
}
- element reg_mmdp_data.mem
+ element reg_remu.mem
{
datum baseAddress
{
- value = "12616";
+ value = "12448";
type = "long";
}
}
@@ -240,83 +179,88 @@
type = "long";
}
}
- element ram_diag_bg.mem
+ element reg_tr_10GbE.mem
{
datum baseAddress
{
- value = "262144";
+ value = "524288";
type = "long";
}
}
- element reg_dp_offload_tx_hdr_ovr.mem
+ element reg_bsn_monitor.mem
{
datum baseAddress
{
- value = "512";
+ value = "256";
type = "long";
}
}
- element ram_diag_data_buffer.mem
+ element ram_ss_ss_wide.mem
{
datum baseAddress
{
- value = "65536";
+ value = "655360";
type = "long";
}
}
- element reg_diag_bg.mem
+ element reg_dp_offload_tx_hdr_dat.mem
{
datum baseAddress
{
- value = "12544";
+ value = "13312";
type = "long";
}
}
- element reg_remu.mem
+ element ram_diag_data_buffer.mem
{
datum baseAddress
{
- value = "12448";
+ value = "65536";
type = "long";
}
}
- element reg_tr_xaui.mem
+ element reg_dpmm_ctrl.mem
{
datum baseAddress
{
- value = "16384";
+ value = "12576";
type = "long";
}
}
- element reg_unb_sens.mem
+ element pio_system_info.mem
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "12416";
+ value = "0";
type = "long";
}
}
- element reg_epcs.mem
+ element ram_diag_bg.mem
{
datum baseAddress
{
- value = "12480";
+ value = "262144";
type = "long";
}
}
- element reg_dp_offload_rx_hdr_dat.mem
+ element reg_tr_xaui.mem
{
datum baseAddress
{
- value = "1024";
+ value = "16384";
type = "long";
}
}
- element ram_ss_ss_wide.mem
+ element pio_pps.mem
{
datum baseAddress
{
- value = "655360";
+ value = "12608";
type = "long";
}
}
@@ -348,7 +292,7 @@
{
datum _sortIndex
{
- value = "3";
+ value = "2";
type = "int";
}
datum megawizard_uipreferences
@@ -361,7 +305,7 @@
{
datum _sortIndex
{
- value = "19";
+ value = "17";
type = "int";
}
}
@@ -369,7 +313,7 @@
{
datum _sortIndex
{
- value = "17";
+ value = "15";
type = "int";
}
}
@@ -377,7 +321,7 @@
{
datum _sortIndex
{
- value = "6";
+ value = "4";
type = "int";
}
datum megawizard_uipreferences
@@ -386,24 +330,11 @@
type = "String";
}
}
- element altpll_0.pll_slave
- {
- datum _lockedAddress
- {
- value = "0";
- type = "boolean";
- }
- datum baseAddress
- {
- value = "12576";
- type = "long";
- }
- }
element ram_diag_bg
{
datum _sortIndex
{
- value = "30";
+ value = "28";
type = "int";
}
}
@@ -411,7 +342,7 @@
{
datum _sortIndex
{
- value = "28";
+ value = "26";
type = "int";
}
}
@@ -419,7 +350,7 @@
{
datum _sortIndex
{
- value = "31";
+ value = "29";
type = "int";
}
}
@@ -427,7 +358,7 @@
{
datum _sortIndex
{
- value = "22";
+ value = "20";
type = "int";
}
}
@@ -435,7 +366,7 @@
{
datum _sortIndex
{
- value = "29";
+ value = "27";
type = "int";
}
}
@@ -443,7 +374,7 @@
{
datum _sortIndex
{
- value = "27";
+ value = "25";
type = "int";
}
}
@@ -451,7 +382,7 @@
{
datum _sortIndex
{
- value = "25";
+ value = "23";
type = "int";
}
}
@@ -459,7 +390,7 @@
{
datum _sortIndex
{
- value = "23";
+ value = "21";
type = "int";
}
}
@@ -467,7 +398,7 @@
{
datum _sortIndex
{
- value = "24";
+ value = "22";
type = "int";
}
}
@@ -475,7 +406,7 @@
{
datum _sortIndex
{
- value = "26";
+ value = "24";
type = "int";
}
}
@@ -483,7 +414,7 @@
{
datum _sortIndex
{
- value = "10";
+ value = "8";
type = "int";
}
}
@@ -491,7 +422,7 @@
{
datum _sortIndex
{
- value = "11";
+ value = "9";
type = "int";
}
}
@@ -499,7 +430,7 @@
{
datum _sortIndex
{
- value = "14";
+ value = "12";
type = "int";
}
}
@@ -507,7 +438,7 @@
{
datum _sortIndex
{
- value = "12";
+ value = "10";
type = "int";
}
}
@@ -515,7 +446,7 @@
{
datum _sortIndex
{
- value = "13";
+ value = "11";
type = "int";
}
}
@@ -523,7 +454,7 @@
{
datum _sortIndex
{
- value = "9";
+ value = "7";
type = "int";
}
}
@@ -531,7 +462,7 @@
{
datum _sortIndex
{
- value = "20";
+ value = "18";
type = "int";
}
}
@@ -539,7 +470,7 @@
{
datum _sortIndex
{
- value = "21";
+ value = "19";
type = "int";
}
}
@@ -547,7 +478,7 @@
{
datum _sortIndex
{
- value = "15";
+ value = "13";
type = "int";
}
}
@@ -555,7 +486,7 @@
{
datum _sortIndex
{
- value = "18";
+ value = "16";
type = "int";
}
}
@@ -563,7 +494,7 @@
{
datum _sortIndex
{
- value = "16";
+ value = "14";
type = "int";
}
}
@@ -575,6 +506,14 @@
type = "long";
}
}
+ element pio_wdi.s1
+ {
+ datum baseAddress
+ {
+ value = "12304";
+ type = "long";
+ }
+ }
element onchip_memory2_0.s1
{
datum _lockedAddress
@@ -588,19 +527,11 @@
type = "long";
}
}
- element pio_wdi.s1
- {
- datum baseAddress
- {
- value = "12304";
- type = "long";
- }
- }
element timer_0
{
datum _sortIndex
{
- value = "7";
+ value = "5";
type = "int";
}
}
@@ -619,7 +550,7 @@
<parameter name="projectName" value="unb1_test_10GbE.qpf" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="1" />
- <parameter name="timeStamp" value="1425903424589" />
+ <parameter name="timeStamp" value="1426850848673" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
@@ -649,9 +580,6 @@
name="coe_readdata_export_to_the_reg_mmdp_ctrl"
internal="coe_readdata_export" />
</interface>
- <interface name="c0_out_clk" internal="c0.out_clk" type="clock" dir="start">
- <port name="mm_clk" internal="out_clk" />
- </interface>
<interface
name="pio_system_info_address"
internal="pio_system_info.address"
@@ -1058,13 +986,6 @@
dir="end">
<port name="coe_irq_export_to_the_avs_eth_0" internal="coe_irq_export" />
</interface>
- <interface
- name="altpll_0_phasedone_conduit"
- internal="altpll_0.phasedone_conduit"
- type="conduit"
- dir="end">
- <port name="phasedone_from_the_altpll_0" internal="phasedone" />
- </interface>
<interface
name="rom_system_info_read"
internal="rom_system_info.read"
@@ -1081,11 +1002,7 @@
dir="end">
<port name="coe_reset_export_from_the_reg_epcs" internal="coe_reset_export" />
</interface>
- <interface
- name="clk_0_clk_in_reset"
- internal="clk_0.clk_in_reset"
- type="reset"
- dir="end">
+ <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end">
<port name="reset_n" internal="reset_n" />
</interface>
<interface
@@ -1124,7 +1041,7 @@
name="coe_tse_readdata_export_to_the_avs_eth_0"
internal="coe_tse_readdata_export" />
</interface>
- <interface name="clk_0_clk_in" internal="clk_0.clk_in" type="clock" dir="end">
+ <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end">
<port name="clk_0" internal="in_clk" />
</interface>
<interface
@@ -1181,12 +1098,6 @@
name="coe_writedata_export_from_the_reg_tr_10GbE"
internal="coe_writedata_export" />
</interface>
- <interface name="altpll_0_c2" internal="altpll_0.c2" type="clock" dir="start">
- <port name="tse_clk" internal="c2" />
- </interface>
- <interface name="altpll_0_c3" internal="altpll_0.c3" type="clock" dir="start">
- <port name="dp_clk" internal="c3" />
- </interface>
<interface
name="avs_eth_0_reg_readdata"
internal="avs_eth_0.reg_readdata"
@@ -1196,9 +1107,6 @@
name="coe_reg_readdata_export_to_the_avs_eth_0"
internal="coe_reg_readdata_export" />
</interface>
- <interface name="altpll_0_c1" internal="altpll_0.c1" type="clock" dir="start">
- <port name="epcs_clk" internal="c1" />
- </interface>
<interface
name="reg_tr_10GbE_read"
internal="reg_tr_10GbE.read"
@@ -1278,9 +1186,6 @@
name="coe_read_export_from_the_pio_system_info"
internal="coe_read_export" />
</interface>
- <interface name="altpll_0_c4" internal="altpll_0.c4" type="clock" dir="start">
- <port name="cal_reconf_clk" internal="c4" />
- </interface>
<interface
name="reg_mmdp_data_clk"
internal="reg_mmdp_data.clk"
@@ -1560,20 +1465,6 @@
name="coe_address_export_from_the_reg_remu"
internal="coe_address_export" />
</interface>
- <interface
- name="altpll_0_areset_conduit"
- internal="altpll_0.areset_conduit"
- type="conduit"
- dir="end">
- <port name="areset_to_the_altpll_0" internal="areset" />
- </interface>
- <interface
- name="altpll_0_locked_conduit"
- internal="altpll_0.locked_conduit"
- type="conduit"
- dir="end">
- <port name="locked_from_the_altpll_0" internal="locked" />
- </interface>
<interface
name="reg_tr_10GbE_readdata"
internal="reg_tr_10GbE.readdata"
@@ -1968,7 +1859,7 @@
type="conduit"
dir="end" />
<module kind="clock_source" version="11.1" enabled="1" name="clk_0">
- <parameter name="clockFrequency" value="25000000" />
+ <parameter name="clockFrequency" value="125000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
@@ -2062,173 +1953,6 @@ q]]></parameter>
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
- <module kind="altpll" version="11.1" enabled="1" name="altpll_0">
- <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
- <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
- <parameter name="INTENDED_DEVICE_FAMILY" value="Stratix IV" />
- <parameter name="WIDTH_CLOCK" value="10" />
- <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
- <parameter name="PRIMARY_CLOCK" value="" />
- <parameter name="INCLK0_INPUT_FREQUENCY" value="40000" />
- <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
- <parameter name="OPERATION_MODE" value="NORMAL" />
- <parameter name="PLL_TYPE" value="AUTO" />
- <parameter name="QUALIFY_CONF_DONE" value="" />
- <parameter name="COMPENSATE_CLOCK" value="CLK0" />
- <parameter name="SCAN_CHAIN" value="" />
- <parameter name="GATE_LOCK_SIGNAL" value="" />
- <parameter name="GATE_LOCK_COUNTER" value="" />
- <parameter name="LOCK_HIGH" value="" />
- <parameter name="LOCK_LOW" value="" />
- <parameter name="VALID_LOCK_MULTIPLIER" value="" />
- <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
- <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
- <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
- <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
- <parameter name="SKIP_VCO" value="" />
- <parameter name="SWITCH_OVER_COUNTER" value="" />
- <parameter name="SWITCH_OVER_TYPE" value="" />
- <parameter name="FEEDBACK_SOURCE" value="" />
- <parameter name="BANDWIDTH" value="" />
- <parameter name="BANDWIDTH_TYPE" value="AUTO" />
- <parameter name="SPREAD_FREQUENCY" value="" />
- <parameter name="DOWN_SPREAD" value="" />
- <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
- <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
- <parameter name="CLK0_MULTIPLY_BY" value="5" />
- <parameter name="CLK1_MULTIPLY_BY" value="4" />
- <parameter name="CLK2_MULTIPLY_BY" value="5" />
- <parameter name="CLK3_MULTIPLY_BY" value="8" />
- <parameter name="CLK4_MULTIPLY_BY" value="8" />
- <parameter name="CLK5_MULTIPLY_BY" value="" />
- <parameter name="CLK6_MULTIPLY_BY" value="" />
- <parameter name="CLK7_MULTIPLY_BY" value="" />
- <parameter name="CLK8_MULTIPLY_BY" value="" />
- <parameter name="CLK9_MULTIPLY_BY" value="" />
- <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
- <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
- <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
- <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
- <parameter name="CLK0_DIVIDE_BY" value="1" />
- <parameter name="CLK1_DIVIDE_BY" value="5" />
- <parameter name="CLK2_DIVIDE_BY" value="1" />
- <parameter name="CLK3_DIVIDE_BY" value="1" />
- <parameter name="CLK4_DIVIDE_BY" value="5" />
- <parameter name="CLK5_DIVIDE_BY" value="" />
- <parameter name="CLK6_DIVIDE_BY" value="" />
- <parameter name="CLK7_DIVIDE_BY" value="" />
- <parameter name="CLK8_DIVIDE_BY" value="" />
- <parameter name="CLK9_DIVIDE_BY" value="" />
- <parameter name="EXTCLK0_DIVIDE_BY" value="" />
- <parameter name="EXTCLK1_DIVIDE_BY" value="" />
- <parameter name="EXTCLK2_DIVIDE_BY" value="" />
- <parameter name="EXTCLK3_DIVIDE_BY" value="" />
- <parameter name="CLK0_PHASE_SHIFT" value="0" />
- <parameter name="CLK1_PHASE_SHIFT" value="0" />
- <parameter name="CLK2_PHASE_SHIFT" value="0" />
- <parameter name="CLK3_PHASE_SHIFT" value="0" />
- <parameter name="CLK4_PHASE_SHIFT" value="0" />
- <parameter name="CLK5_PHASE_SHIFT" value="" />
- <parameter name="CLK6_PHASE_SHIFT" value="" />
- <parameter name="CLK7_PHASE_SHIFT" value="" />
- <parameter name="CLK8_PHASE_SHIFT" value="" />
- <parameter name="CLK9_PHASE_SHIFT" value="" />
- <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
- <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
- <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
- <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
- <parameter name="CLK0_DUTY_CYCLE" value="50" />
- <parameter name="CLK1_DUTY_CYCLE" value="50" />
- <parameter name="CLK2_DUTY_CYCLE" value="50" />
- <parameter name="CLK3_DUTY_CYCLE" value="50" />
- <parameter name="CLK4_DUTY_CYCLE" value="50" />
- <parameter name="CLK5_DUTY_CYCLE" value="" />
- <parameter name="CLK6_DUTY_CYCLE" value="" />
- <parameter name="CLK7_DUTY_CYCLE" value="" />
- <parameter name="CLK8_DUTY_CYCLE" value="" />
- <parameter name="CLK9_DUTY_CYCLE" value="" />
- <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
- <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
- <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
- <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
- <parameter name="PORT_clkena0" value="PORT_UNUSED" />
- <parameter name="PORT_clkena1" value="PORT_UNUSED" />
- <parameter name="PORT_clkena2" value="PORT_UNUSED" />
- <parameter name="PORT_clkena3" value="PORT_UNUSED" />
- <parameter name="PORT_clkena4" value="PORT_UNUSED" />
- <parameter name="PORT_clkena5" value="PORT_UNUSED" />
- <parameter name="PORT_extclkena0" value="" />
- <parameter name="PORT_extclkena1" value="" />
- <parameter name="PORT_extclkena2" value="" />
- <parameter name="PORT_extclkena3" value="" />
- <parameter name="PORT_extclk0" value="" />
- <parameter name="PORT_extclk1" value="" />
- <parameter name="PORT_extclk2" value="" />
- <parameter name="PORT_extclk3" value="" />
- <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
- <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
- <parameter name="PORT_clk0" value="PORT_USED" />
- <parameter name="PORT_clk1" value="PORT_USED" />
- <parameter name="PORT_clk2" value="PORT_USED" />
- <parameter name="PORT_clk3" value="PORT_USED" />
- <parameter name="PORT_clk4" value="PORT_USED" />
- <parameter name="PORT_clk5" value="PORT_UNUSED" />
- <parameter name="PORT_clk6" value="PORT_UNUSED" />
- <parameter name="PORT_clk7" value="PORT_UNUSED" />
- <parameter name="PORT_clk8" value="PORT_UNUSED" />
- <parameter name="PORT_clk9" value="PORT_UNUSED" />
- <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
- <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
- <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
- <parameter name="PORT_SCLKOUT1" value="" />
- <parameter name="PORT_SCLKOUT0" value="" />
- <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
- <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
- <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
- <parameter name="PORT_INCLK0" value="PORT_USED" />
- <parameter name="PORT_FBIN" value="PORT_UNUSED" />
- <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
- <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
- <parameter name="PORT_ARESET" value="PORT_UNUSED" />
- <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
- <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
- <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
- <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
- <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
- <parameter name="PORT_ENABLE0" value="" />
- <parameter name="PORT_ENABLE1" value="" />
- <parameter name="PORT_LOCKED" value="PORT_USED" />
- <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
- <parameter name="PORT_FBOUT" value="PORT_UNUSED" />
- <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
- <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
- <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
- <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
- <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
- <parameter name="PORT_VCOOVERRANGE" value="" />
- <parameter name="PORT_VCOUNDERRANGE" value="" />
- <parameter name="DPA_MULTIPLY_BY" value="" />
- <parameter name="DPA_DIVIDE_BY" value="" />
- <parameter name="DPA_DIVIDER" value="" />
- <parameter name="VCO_MULTIPLY_BY" value="" />
- <parameter name="VCO_DIVIDE_BY" value="" />
- <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
- <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
- <parameter name="VCO_FREQUENCY_CONTROL" value="" />
- <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
- <parameter name="USING_FBMIMICBIDIR_PORT" value="OFF" />
- <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
- <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
- <parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 1 CT#PORT_clk9 PORT_UNUSED CT#PORT_clk8 PORT_UNUSED CT#PORT_clk7 PORT_UNUSED CT#PORT_clk6 PORT_UNUSED CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 1 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT 0 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 5 CT#WIDTH_CLOCK 10 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 8 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 4 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT 0 CT#INCLK0_INPUT_FREQUENCY 40000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_FBOUT PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 5 CT#INTENDED_DEVICE_FAMILY {Stratix IV} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 5 CT#CLK3_MULTIPLY_BY 8 CT#USING_FBMIMICBIDIR_PORT OFF CT#PORT_LOCKED PORT_USED</parameter>
- <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 25.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 40.00000000 PT#OUTPUT_FREQ3 200.00000000 PT#OUTPUT_FREQ2 125.00000000 PT#OUTPUT_FREQ1 20.00000000 PT#OUTPUT_FREQ0 125.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 1 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 0.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 0.00000000 PT#DIV_FACTOR4 1 PT#DIV_FACTOR3 1 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 40.000000 PT#EFF_OUTPUT_FREQ_VALUE3 200.000000 PT#EFF_OUTPUT_FREQ_VALUE2 125.000000 PT#EFF_OUTPUT_FREQ_VALUE1 20.000000 PT#EFF_OUTPUT_FREQ_VALUE0 125.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Stratix IV} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1256297171721465.mif PT#ACTIVECLK_CHECK 0</parameter>
- <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
- <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
- <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
- <parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</parameter>
- <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
- <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="25000000" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Stratix IV" />
- </module>
<module kind="avs_common_mm" version="1.0" enabled="1" name="reg_remu">
<parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" />
@@ -2374,7 +2098,7 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='reg_bsn_monitor.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_hdr_ovr.mem' start='0x200' end='0x400' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' /><slave name='reg_unb_sens.mem' start='0x3080' end='0x30A0' /><slave name='reg_remu.mem' start='0x30A0' end='0x30C0' /><slave name='reg_epcs.mem' start='0x30C0' end='0x30E0' /><slave name='reg_dp_offload_tx.mem' start='0x30E0' end='0x3100' /><slave name='reg_diag_bg.mem' start='0x3100' end='0x3120' /><slave name='altpll_0.pll_slave' start='0x3120' end='0x3130' /><slave name='reg_dpmm_ctrl.mem' start='0x3130' end='0x3138' /><slave name='reg_dpmm_data.mem' start='0x3138' end='0x3140' /><slave name='reg_mmdp_ctrl.mem' start='0x3140' end='0x3148' /><slave name='reg_mmdp_data.mem' start='0x3148' end='0x3150' /><slave name='pio_pps.mem' start='0x3150' end='0x3158' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_diag_bg.mem' start='0x40000' end='0x80000' /><slave name='reg_tr_10GbE.mem' start='0x80000' end='0xA0000' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='reg_bsn_monitor.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_hdr_ovr.mem' start='0x200' end='0x400' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' /><slave name='reg_unb_sens.mem' start='0x3080' end='0x30A0' /><slave name='reg_remu.mem' start='0x30A0' end='0x30C0' /><slave name='reg_epcs.mem' start='0x30C0' end='0x30E0' /><slave name='reg_dp_offload_tx.mem' start='0x30E0' end='0x3100' /><slave name='reg_diag_bg.mem' start='0x3100' end='0x3120' /><slave name='reg_dpmm_ctrl.mem' start='0x3120' end='0x3128' /><slave name='reg_dpmm_data.mem' start='0x3128' end='0x3130' /><slave name='reg_mmdp_ctrl.mem' start='0x3130' end='0x3138' /><slave name='reg_mmdp_data.mem' start='0x3138' end='0x3140' /><slave name='pio_pps.mem' start='0x3140' end='0x3148' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_diag_bg.mem' start='0x40000' end='0x80000' /><slave name='reg_tr_10GbE.mem' start='0x80000' end='0xA0000' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' /></address-map>]]></parameter>
<parameter name="clockFrequency" value="125000000" />
<parameter name="deviceFamilyName" value="Stratix IV" />
<parameter name="internalIrqMaskSystemInfo" value="7" />
@@ -2389,11 +2113,6 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
</module>
- <module kind="altera_clock_bridge" version="11.1" enabled="1" name="c0">
- <parameter name="DERIVED_CLOCK_RATE" value="125000000" />
- <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
- <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
- </module>
<module kind="avs_common_mm" version="1.0" enabled="1" name="reg_bsn_monitor">
<parameter name="g_adr_w" value="6" />
<parameter name="g_dat_w" value="32" />
@@ -2566,45 +2285,6 @@ q]]></parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3000" />
</connection>
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="altpll_0.pll_slave">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3120" />
- </connection>
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="cpu_0.clk" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="onchip_memory2_0.clk1" />
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="jtag_uart_0.clk" />
- <connection
- kind="clock"
- version="11.1"
- start="clk_0.clk"
- end="altpll_0.inclk_interface" />
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_wdi.clk" />
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="timer_0.clk" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_unb_sens.system" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="rom_system_info.system" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="pio_system_info.system" />
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_wdi.system" />
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_remu.system" />
<connection
kind="avalon"
version="11.1"
@@ -2613,59 +2293,38 @@ q]]></parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x30a0" />
</connection>
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_dpmm_ctrl.system" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3130" />
+ <parameter name="baseAddress" value="0x3120" />
</connection>
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_dpmm_data.system" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3138" />
+ <parameter name="baseAddress" value="0x3128" />
</connection>
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_mmdp_ctrl.system" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3140" />
+ <parameter name="baseAddress" value="0x3130" />
</connection>
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_mmdp_data.system" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3148" />
+ <parameter name="baseAddress" value="0x3138" />
</connection>
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_epcs.system" />
<connection
kind="avalon"
version="11.1"
@@ -2674,20 +2333,14 @@ q]]></parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x30c0" />
</connection>
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_pps.system" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3150" />
+ <parameter name="baseAddress" value="0x3140" />
</connection>
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_tr_10GbE.system" />
<connection
kind="avalon"
version="11.1"
@@ -2696,7 +2349,6 @@ q]]></parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00080000" />
</connection>
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="avs_eth_0.mm" />
<connection
kind="avalon"
version="11.1"
@@ -2728,11 +2380,6 @@ q]]></parameter>
end="avs_eth_0.interrupt">
<parameter name="irqNumber" value="2" />
</connection>
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_tr_xaui.system" />
<connection
kind="avalon"
version="11.1"
@@ -2821,16 +2468,6 @@ q]]></parameter>
version="11.1"
start="cpu_0.jtag_debug_module_reset"
end="reg_wdi.system_reset" />
- <connection
- kind="reset"
- version="11.1"
- start="clk_0.clk_reset"
- end="altpll_0.inclk_interface_reset" />
- <connection
- kind="reset"
- version="11.1"
- start="cpu_0.jtag_debug_module_reset"
- end="altpll_0.inclk_interface_reset" />
<connection
kind="reset"
version="11.1"
@@ -2941,12 +2578,6 @@ q]]></parameter>
version="11.1"
start="cpu_0.jtag_debug_module_reset"
end="cpu_0.reset_n" />
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="c0.in_clk" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_bsn_monitor.system" />
<connection
kind="reset"
version="11.1"
@@ -2983,21 +2614,6 @@ q]]></parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0400" />
</connection>
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_dp_offload_rx_hdr_dat.system" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_dp_offload_tx_hdr_dat.system" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_dp_offload_tx.system" />
<connection
kind="reset"
version="11.1"
@@ -3073,21 +2689,6 @@ q]]></parameter>
version="11.1"
start="cpu_0.jtag_debug_module_reset"
end="ram_diag_data_buffer.system_reset" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_dp_offload_tx_hdr_ovr.system" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_diag_data_buffer.system" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="ram_diag_data_buffer.system" />
<connection
kind="reset"
version="11.1"
@@ -3129,16 +2730,6 @@ q]]></parameter>
version="11.1"
start="cpu_0.jtag_debug_module_reset"
end="reg_diag_bg.system_reset" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="reg_diag_bg.system" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="ram_diag_bg.system" />
<connection
kind="reset"
version="11.1"
@@ -3159,11 +2750,6 @@ q]]></parameter>
version="11.1"
start="cpu_0.jtag_debug_module_reset"
end="ram_ss_ss_wide.system_reset" />
- <connection
- kind="clock"
- version="11.1"
- start="altpll_0.c0"
- end="ram_ss_ss_wide.system" />
<connection
kind="avalon"
version="11.1"
@@ -3172,4 +2758,113 @@ q]]></parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x000a0000" />
</connection>
+ <connection kind="clock" version="11.1" start="clk_0.clk" end="cpu_0.clk" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="onchip_memory2_0.clk1" />
+ <connection kind="clock" version="11.1" start="clk_0.clk" end="jtag_uart_0.clk" />
+ <connection kind="clock" version="11.1" start="clk_0.clk" end="pio_wdi.clk" />
+ <connection kind="clock" version="11.1" start="clk_0.clk" end="timer_0.clk" />
+ <connection kind="clock" version="11.1" start="clk_0.clk" end="avs_eth_0.mm" />
+ <connection kind="clock" version="11.1" start="clk_0.clk" end="reg_remu.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_dpmm_ctrl.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_dpmm_data.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_mmdp_ctrl.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_mmdp_data.system" />
+ <connection kind="clock" version="11.1" start="clk_0.clk" end="reg_epcs.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_unb_sens.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="rom_system_info.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="pio_system_info.system" />
+ <connection kind="clock" version="11.1" start="clk_0.clk" end="reg_wdi.system" />
+ <connection kind="clock" version="11.1" start="clk_0.clk" end="pio_pps.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_tr_10GbE.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_tr_xaui.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_bsn_monitor.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_dp_offload_tx.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_dp_offload_tx_hdr_dat.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_dp_offload_rx_hdr_dat.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_dp_offload_tx_hdr_ovr.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_diag_data_buffer.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="ram_diag_data_buffer.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="reg_diag_bg.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="ram_diag_bg.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="ram_ss_ss_wide.system" />
</system>
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
index 8b8196edba8f364f8e02552b44c1f12da601f14f..910e0fea5240f1fa2c58c6627b53c4c63011653d 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
@@ -43,7 +43,7 @@ ENTITY unb1_test_10GbE IS
);
PORT (
-- GENERAL
- --CLK : IN STD_LOGIC; -- System Clock - not used as the SOPC generates dp_clk.
+ CLK : IN STD_LOGIC; -- System Clock
PPS : IN STD_LOGIC; -- System Sync
WDI : OUT STD_LOGIC; -- Watchdog Clear
INTA : INOUT STD_LOGIC; -- FPGA interconnect line
@@ -55,11 +55,11 @@ ENTITY unb1_test_10GbE IS
TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
- sens_sc : INOUT STD_LOGIC;
- sens_sd : INOUT STD_LOGIC;
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
-- 1GbE Control Interface
- ETH_clk : IN STD_LOGIC;
+ ETH_CLK : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC;
ETH_SGOUT : OUT STD_LOGIC;
@@ -121,7 +121,7 @@ BEGIN
)
PORT MAP (
-- GENERAL
- --CLK => CLK,
+ CLK => CLK,
PPS => PPS,
WDI => WDI,
INTA => INTA,
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index fc420d04ff0e1f4cb903fed5990ed20daf38db68..c38908aa17746ef6d6ea7476850e7d84a6477c4e 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -52,18 +52,8 @@ ENTITY mmm_unb1_test IS
g_hdr_field_arr : t_common_field_arr
);
PORT (
- xo_clk : IN STD_LOGIC;
- xo_rst_n : IN STD_LOGIC;
- xo_rst : IN STD_LOGIC;
-
mm_rst : IN STD_LOGIC;
- mm_clk : OUT STD_LOGIC;
- mm_locked : OUT STD_LOGIC;
-
- epcs_clk : OUT STD_LOGIC;
- cal_rec_clk : OUT STD_LOGIC;
- dp_clk : OUT STD_LOGIC;
-
+ mm_clk : IN STD_LOGIC;
pout_wdi : OUT STD_LOGIC;
@@ -86,7 +76,6 @@ ENTITY mmm_unb1_test IS
reg_ppsh_miso : IN t_mem_miso;
-- eth1g
- eth1g_tse_clk : OUT STD_LOGIC;
eth1g_mm_rst : OUT STD_LOGIC;
eth1g_tse_mosi : OUT t_mem_mosi;
eth1g_tse_miso : IN t_mem_miso;
@@ -153,12 +142,6 @@ END mmm_unb1_test;
ARCHITECTURE str OF mmm_unb1_test IS
- SIGNAL i_mm_clk : STD_LOGIC := '1';
- SIGNAL i_cal_rec_clk : STD_LOGIC := '1';
- SIGNAL i_dp_clk : STD_LOGIC := '1';
- SIGNAL i_eth1g_tse_clk : STD_LOGIC := '1';
- SIGNAL i_epcs_clk : STD_LOGIC := '1';
-
--FIXME
--CONSTANT g_nof_streams : NATURAL := g_nof_streams_10GbE + g_nof_streams_ddr;
CONSTANT g_nof_streams : NATURAL := g_nof_streams_10GbE + 1;
@@ -203,7 +186,6 @@ ARCHITECTURE str OF mmm_unb1_test IS
-- Simulation
CONSTANT c_mm_clk_period : TIME := 8 ns; -- 125 MHz
CONSTANT c_cal_rec_clk_period : TIME := 25 ns; -- 40 MHz
- CONSTANT c_dp_clk_period : TIME := 5 ns; -- 200 MHz
CONSTANT c_tse_clk_period : TIME := 8 ns; -- 125 MHz
CONSTANT c_epcs_clk_period : TIME := 50 ns; -- 20 MHz
@@ -231,7 +213,6 @@ ARCHITECTURE str OF mmm_unb1_test IS
COMPONENT mm_file
GENERIC(
g_file_prefix : STRING;
- g_mm_clk_period : TIME := c_mm_clk_period;
g_update_on_change : BOOLEAN := FALSE;
g_mm_rd_latency : NATURAL := 1
);
@@ -245,81 +226,66 @@ ARCHITECTURE str OF mmm_unb1_test IS
BEGIN
- mm_clk <= i_mm_clk;
- cal_rec_clk <= i_cal_rec_clk;
- dp_clk <= i_dp_clk;
- eth1g_tse_clk <= i_eth1g_tse_clk;
- epcs_clk <= i_epcs_clk;
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
- i_mm_clk <= NOT i_mm_clk AFTER c_mm_clk_period/2;
- i_cal_rec_clk <= NOT i_cal_rec_clk AFTER c_cal_rec_clk_period/2;
- i_dp_clk <= NOT i_dp_clk AFTER c_dp_clk_period/2;
- i_eth1g_tse_clk <= NOT i_eth1g_tse_clk AFTER c_tse_clk_period/2;
- i_epcs_clk <= NOT i_epcs_clk AFTER c_epcs_clk_period/2;
-
- mm_locked <= '0', '1' AFTER c_mm_clk_period*5;
- eth1g_mm_rst <= '1', '0' AFTER c_tse_clk_period*5;
-
u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- PORT MAP(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- PORT MAP(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- PORT MAP(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- PORT MAP(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- PORT MAP(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- PORT MAP(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- PORT MAP(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ PORT MAP(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
u_mm_file_reg_dp_offload_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX")
- PORT MAP(mm_rst, i_mm_clk, reg_dp_offload_tx_mosi, reg_dp_offload_tx_miso );
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_mosi, reg_dp_offload_tx_miso );
u_mm_file_reg_dp_offload_tx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
- PORT MAP(mm_rst, i_mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso );
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso );
u_mm_file_reg_dp_offload_tx_hdr_ovr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_OVR")
- PORT MAP(mm_rst, i_mm_clk, reg_dp_offload_tx_hdr_ovr_mosi, reg_dp_offload_tx_hdr_ovr_miso );
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_ovr_mosi, reg_dp_offload_tx_hdr_ovr_miso );
u_mm_file_reg_dp_offload_rx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_HDR_DAT")
- PORT MAP(mm_rst, i_mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
u_mm_file_reg_bsn_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
- PORT MAP(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
u_mm_file_ram_diag_data_buffer : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
- PORT MAP(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
u_mm_file_reg_diag_data_buffer : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
- PORT MAP(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
+ PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
u_mm_file_ram_ss_ss_transp : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- PORT MAP(mm_rst, i_mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
+ PORT MAP(mm_rst, mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- PORT MAP(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_reg_tr_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE", c_mm_clk_period, FALSE, 0)
- PORT MAP(mm_rst, i_mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso );
+ u_mm_file_reg_tr_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE")--, c_mm_clk_period, FALSE, 0)
+ PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso );
- u_mm_file_reg_tr_xaui : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_XAUI", c_mm_clk_period, FALSE, 0)
- PORT MAP(mm_rst, i_mm_clk, reg_tr_xaui_mosi, reg_tr_xaui_miso );
+ u_mm_file_reg_tr_xaui : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_XAUI")--, c_mm_clk_period, FALSE, 0)
+ PORT MAP(mm_rst, mm_clk, reg_tr_xaui_mosi, reg_tr_xaui_miso );
----------------------------------------------------------------------------
@@ -332,11 +298,11 @@ BEGIN
eth1g_tse_mosi.wr <= '0';
eth1g_tse_mosi.rd <= '0';
WAIT FOR 400 ns;
- WAIT UNTIL rising_edge(i_mm_clk);
- proc_tech_tse_setup(c_tech_stratixiv, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, i_mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
+ WAIT UNTIL rising_edge(mm_clk);
+ proc_tech_tse_setup(c_tech_stratixiv, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
-- Enable RX
- proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, i_mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
sim_eth_mm_bus_switch <= '0';
WAIT;
@@ -367,18 +333,8 @@ BEGIN
gen_qsys : IF g_sim = FALSE GENERATE
u_qsys : qsys_unb1_test
PORT MAP (
- clk_0 => xo_clk,
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk,
- cal_reconf_clk => i_cal_rec_clk,
- tse_clk => i_eth1g_tse_clk,
- epcs_clk => i_epcs_clk,
- dp_clk => i_dp_clk,
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
+ clk_0 => mm_clk,
+ reset_n => mm_rst,
-- the_avs_eth_0
coe_clk_export_from_the_avs_eth_0 => OPEN,
@@ -612,7 +568,6 @@ BEGIN
ram_ss_ss_wide_reset_export => OPEN,
ram_ss_ss_wide_write_export => ram_ss_ss_transp_mosi.wr,
ram_ss_ss_wide_writedata_export => ram_ss_ss_transp_mosi.wrdata(c_word_w-1 DOWNTO 0)
-
);
END GENERATE;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
index de1ed04f649d9a572a4233ba8fa61a36f89f613c..00ee53dcf7b7faf58d48a593b63b886551a24161 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
@@ -34,7 +34,6 @@ PACKAGE qsys_unb1_test_pkg IS
coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- mm_clk : out std_logic; -- clk
coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
coe_address_export_from_the_pio_pps : out std_logic;--_vector(0 downto 0); -- export
coe_waitrequest_export_to_the_reg_tr_10GbE : in std_logic := 'X'; -- export
@@ -83,7 +82,6 @@ PACKAGE qsys_unb1_test_pkg IS
coe_write_export_from_the_pio_pps : out std_logic; -- export
coe_write_export_from_the_rom_system_info : out std_logic; -- export
coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- phasedone_from_the_altpll_0 : out std_logic; -- export
coe_read_export_from_the_rom_system_info : out std_logic; -- export
coe_reset_export_from_the_reg_epcs : out std_logic; -- export
reset_n : in std_logic := 'X'; -- reset_n
@@ -98,10 +96,7 @@ PACKAGE qsys_unb1_test_pkg IS
coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
coe_writedata_export_from_the_reg_tr_10GbE : out std_logic_vector(31 downto 0); -- export
- tse_clk : out std_logic; -- clk
- dp_clk : out std_logic; -- clk
coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- epcs_clk : out std_logic; -- clk
coe_read_export_from_the_reg_tr_10GbE : out std_logic; -- export
coe_clk_export_from_the_reg_tr_10GbE : out std_logic; -- export
coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
@@ -111,7 +106,6 @@ PACKAGE qsys_unb1_test_pkg IS
coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
coe_reset_export_from_the_pio_system_info : out std_logic; -- export
coe_read_export_from_the_pio_system_info : out std_logic; -- export
- cal_reconf_clk : out std_logic; -- clk
coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
coe_clk_export_from_the_reg_wdi : out std_logic; -- export
coe_clk_export_from_the_reg_epcs : out std_logic; -- export
@@ -147,8 +141,6 @@ PACKAGE qsys_unb1_test_pkg IS
coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
- areset_to_the_altpll_0 : in std_logic := 'X'; -- export
- locked_from_the_altpll_0 : out std_logic; -- export
coe_readdata_export_to_the_reg_tr_10GbE : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
coe_reset_export_from_the_reg_tr_10GbE : out std_logic; -- export
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index dc055969e447d0f849dde3019d0983bab2a0fcfc..532a03cf20b0cbcf0d6e5a4571ef16bb8ecc3513 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -54,7 +54,7 @@ ENTITY unb1_test IS
);
PORT (
-- GENERAL
- --CLK : IN STD_LOGIC; -- System Clock - not used as the SOPC generates dp_clk.
+ CLK : IN STD_LOGIC; -- System Clock
PPS : IN STD_LOGIC; -- System Sync
WDI : OUT STD_LOGIC; -- Watchdog Clear
INTA : INOUT STD_LOGIC; -- FPGA interconnect line
@@ -232,10 +232,8 @@ ARCHITECTURE str OF unb1_test IS
SIGNAL xo_rst : STD_LOGIC;
SIGNAL xo_rst_n : STD_LOGIC;
SIGNAL mm_clk : STD_LOGIC;
- SIGNAL mm_locked : STD_LOGIC;
SIGNAL mm_rst : STD_LOGIC;
- SIGNAL epcs_clk : STD_LOGIC;
SIGNAL cal_rec_clk : STD_LOGIC;
SIGNAL sa_rst : STD_LOGIC;
@@ -406,7 +404,8 @@ BEGIN
g_aux => c_unb1_board_aux,
g_udp_offload => c_use_1GbE,
g_udp_offload_nof_streams => c_nof_streams_10GbE,
- g_dp_clk_use_pll => FALSE
+ g_dp_clk_use_pll => TRUE,
+ g_mm_clk_use_pll => TRUE
)
PORT MAP (
-- Clock and reset signals
@@ -415,17 +414,16 @@ BEGIN
xo_rst => xo_rst,
xo_rst_n => xo_rst_n,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
+ mm_clk_out => mm_clk,
mm_rst => mm_rst,
- epcs_clk => epcs_clk,
-
dp_rst => dp_rst,
- dp_clk => OPEN,
+ dp_clk => dp_clk,
dp_pps => OPEN,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
+
+ cal_rec_clk => cal_rec_clk,
-- Toggle WDI
pout_wdi => pout_wdi,
@@ -470,7 +468,6 @@ BEGIN
reg_ppsh_miso => reg_ppsh_miso,
-- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
@@ -488,7 +485,7 @@ BEGIN
-- FPGA pins
-- . General
- CLK => '0', -- SOPC-generated 200MHz dp_clk is used.
+ CLK => CLK,
PPS => PPS,
WDI => WDI,
INTA => INTA,
@@ -498,10 +495,10 @@ BEGIN
ID => ID,
TESTIO => TESTIO,
-- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
-- . 1GbE Control Interface
- ETH_clk => ETH_clk,
+ ETH_CLK => ETH_CLK,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT
);
@@ -520,18 +517,8 @@ BEGIN
g_hdr_field_arr => c_hdr_field_arr
)
PORT MAP(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
mm_rst => mm_rst,
mm_clk => mm_clk,
- mm_locked => mm_locked,
-
- epcs_clk => epcs_clk,
- cal_rec_clk => cal_rec_clk,
- dp_clk => dp_clk,
-
-- PIOs
pout_wdi => pout_wdi,
@@ -555,7 +542,6 @@ BEGIN
reg_ppsh_miso => reg_ppsh_miso,
-- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
diff --git a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
index 78dda37a30431dace5ed56aef2da1f8f113c001e..84766e57e37893502bfb7e655c4ff21dd39d2c47 100644
--- a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
@@ -150,14 +150,14 @@ BEGIN
)
PORT MAP (
-- GENERAL
- --CLK => clk,
+ CLK => clk,
PPS => pps,
WDI => WDI,
INTA => INTA,
INTB => INTB,
- sens_sc => sens_scl,
- sens_sd => sens_sda,
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
-- Others
VERSION => VERSION,
@@ -165,7 +165,7 @@ BEGIN
TESTIO => TESTIO,
-- 1GbE Control Interface
- ETH_clk => eth_clk,
+ ETH_CLK => eth_clk,
ETH_SGIN => eth_rxp,
ETH_SGOUT => eth_txp,