diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd index 627e517a1220f6a26c04d689b3c6267b2a1ca744..12b9a849b4df0ef5bc98fb66108f24f387fe4cda 100644 --- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd +++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd @@ -367,11 +367,11 @@ BEGIN PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso); u_mm_file_eth1g_reg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG") - PORT MAP(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso ); + PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso ); u_mm_file_eth1g_ram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM") - PORT MAP(mm_rst, i_mm_clk, eth1g_ram_mosi, eth1g_ram_miso ); + PORT MAP(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso ); u_mm_file_eth1g_tse : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE") - PORT MAP(mm_rst, i_mm_clk, eth1g_tse_mosi, eth1g_tse_miso ); + PORT MAP(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso ); u_mm_file_reg_tr_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE")--, c_mm_clk_period, FALSE, 0) PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso);