diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index 00d9bc5946efa386af23e9d9afd0e0eb5b027398..01bc245c25b79173f9656b75787421b01bb3748c 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -1,6 +1,6 @@
 -------------------------------------------------------------------------------
 --
--- Copyright 2020
+-- Copyright 2021
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
@@ -18,7 +18,7 @@
 --
 -------------------------------------------------------------------------------
 
--- Author : J Hargreaves
+-- Authors : J Hargreaves, L Hiemstra
 -- Purpose:  
 --   AIT - ADC (Jesd) receiver, input, timing and associated diagnostic blocks
 -- Description:
@@ -26,24 +26,24 @@
 --   Contains all the signal processing blocks to receive and time the ADC input data
 --   See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
 
-LIBRARY IEEE, common_lib, technology_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE technology_lib.technology_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
 USE diag_lib.diag_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
+USE work.lofar2_unb2b_adc_pkg.ALL;
 USE work.sdp_pkg.ALL;
 
-ENTITY node_adc_input_and_timing IS
+ENTITY node_sdp_adc_input_and_timing IS
   GENERIC (
     g_technology              : NATURAL := c_tech_arria10_e1sg;
-    g_buf_nof_data            : NATURAL := 8192; --1024;
-    g_nof_streams             : NATURAL := 12;
-    g_nof_sync_n              : NATURAL := 4;          -- Three ADCs per RCU share a sync
-    g_aduh_buffer_nof_symbols : NATURAL := 512;        -- Default 512
-    g_bsn_sync_timeout        : NATURAL := 200000000;  -- Default 200M, overide for short simulation 
+    g_buf_nof_data            : NATURAL := c_sdp_V_si_db;
+    g_bsn_sync_timeout        : NATURAL := c_sdp_f_adc_MHz*10**6;  -- Default 200M, overide for short simulation 
     g_sim                     : BOOLEAN := FALSE  
   );
   PORT (
@@ -53,6 +53,7 @@ ENTITY node_adc_input_and_timing IS
     dp_clk                         : IN STD_LOGIC;
     dp_rst                         : IN STD_LOGIC;
 
+
     -- mm control buses
     -- JESD 
     jesd204b_mosi                  : IN  t_mem_mosi := c_mem_mosi_rst;
@@ -80,12 +81,6 @@ ENTITY node_adc_input_and_timing IS
     reg_bsn_monitor_input_mosi     : IN  t_mem_mosi;
     reg_bsn_monitor_input_miso     : OUT t_mem_miso;
 
-    -- Data buffer for raw samples
-    ram_diag_data_buf_jesd_mosi    : IN  t_mem_mosi;
-    ram_diag_data_buf_jesd_miso    : OUT t_mem_miso;
-    reg_diag_data_buf_jesd_mosi    : IN  t_mem_mosi;
-    reg_diag_data_buf_jesd_miso    : OUT t_mem_miso;
-
     -- Data buffer for framed samples (variable depth)
     ram_diag_data_buf_bsn_mosi     : IN  t_mem_mosi;
     ram_diag_data_buf_bsn_miso     : OUT t_mem_miso;
@@ -93,78 +88,94 @@ ENTITY node_adc_input_and_timing IS
     reg_diag_data_buf_bsn_miso     : OUT t_mem_miso;
 
     -- Aduh (statistics) monitor
-    ram_aduh_monitor_mosi          : IN  t_mem_mosi;
-    ram_aduh_monitor_miso          : OUT t_mem_miso;
     reg_aduh_monitor_mosi          : IN  t_mem_mosi;
     reg_aduh_monitor_miso          : OUT t_mem_miso;
 
+    -- JESD control
+    jesd_ctrl_mosi                 : IN  t_mem_mosi;
+    jesd_ctrl_miso                 : OUT t_mem_miso;
+
     -- JESD io signals
-    JESD204B_SERIAL_DATA           : IN    STD_LOGIC_VECTOR((c_sdp_jesd204b_bus_w*c_sdp_jesd204b_nof_bus)-1 downto 0); 
-    JESD204B_REFCLK                : IN    STD_LOGIC; 
-    JESD204B_SYSREF                : IN    STD_LOGIC;
-    JESD204B_SYNC_N                : OUT   STD_LOGIC_VECTOR((c_sdp_jesd204b_bus_w*c_sdp_jesd204b_nof_bus)-1 DOWNTO 0);
+    jesd204b_serial_data           : IN    STD_LOGIC_VECTOR(c_sdp_jesd204b_nof_streams-1 downto 0); 
+    jesd204b_refclk                : IN    STD_LOGIC; 
+    jesd204b_sysref                : IN    STD_LOGIC;
+    jesd204b_sync_n                : OUT   STD_LOGIC_VECTOR(c_sdp_jesd204b_nof_streams-1 DOWNTO 0);
 
     -- Streaming data output
-    out_sosi_arr                   : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)        
+    out_sosi_arr                   : OUT t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0)        
 
   );
-END node_adc_input_and_timing;
-
-
-ARCHITECTURE str OF node_adc_input_and_timing IS
+END node_sdp_adc_input_and_timing;
 
 
-  CONSTANT c_nof_streams_jesd204b   : NATURAL := 12;     -- IP is set up for 12 streams
-  CONSTANT c_nof_streams_db         : NATURAL := 2;      -- Streams of raw samples to record in db 
+ARCHITECTURE str OF node_sdp_adc_input_and_timing IS
 
   -- Waveform Generator
   CONSTANT c_wg_buf_directory       : STRING := "data/";
   CONSTANT c_wg_buf_dat_w           : NATURAL := 18; --default value of WG that fits 14 bits of ADC data
   CONSTANT c_wg_buf_addr_w          : NATURAL := 10; --default value of WG for 1024 samples;
-  SIGNAL wg_out_ovr                 : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);    
-  SIGNAL wg_out_val                 : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);    
-  SIGNAL wg_out_data                : STD_LOGIC_VECTOR(g_nof_streams*c_wg_buf_dat_w-1 DOWNTO 0);    
-  SIGNAL wg_out_sync                : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);    
+  SIGNAL wg_out_ovr                 : STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0);    
+  SIGNAL wg_out_val                 : STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0);    
+  SIGNAL wg_out_data                : STD_LOGIC_VECTOR(c_sdp_S_pn*c_wg_buf_dat_w-1 DOWNTO 0);    
+  SIGNAL wg_out_sync                : STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0);    
   SIGNAL trigger_wg                 : STD_LOGIC;
 
   -- Frame parameters TBC
   CONSTANT c_bs_bsn_w               : NATURAL := 64; --51;
   CONSTANT c_bs_block_size          : NATURAL := 1024;
   CONSTANT c_bs_nof_block_per_sync  : NATURAL := 390625;  -- generate a sync every 2s for testing
-  CONSTANT c_dp_shiftram_nof_samples: NATURAL := 4096;
-  CONSTANT c_data_w                 : NATURAL := 16;
   CONSTANT c_dp_fifo_dc_size        : NATURAL := 64;
  
  
+  -- QSFP leds
+  SIGNAL qsfp_green_led_arr         : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+  SIGNAL qsfp_red_led_arr           : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+
   -- JESD signals
   SIGNAL rx_clk                     : STD_LOGIC; -- formerly jesd204b_frame_clk
   SIGNAL rx_rst                     : STD_LOGIC; 
   SIGNAL rx_sysref                  : STD_LOGIC; 
 
   -- Sosis and sosi arrays
-  SIGNAL rx_sosi_arr                : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);         
-  SIGNAL dp_shiftram_snk_in_arr     : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);         
-  SIGNAL ant_sosi_arr               : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
-  SIGNAL diag_data_buf_snk_in_arr   : t_dp_sosi_arr(c_nof_streams_db-1 DOWNTO 0);
+  SIGNAL rx_sosi_arr                : t_dp_sosi_arr(c_sdp_jesd204b_nof_streams-1 DOWNTO 0);         
+  SIGNAL dp_shiftram_snk_in_arr     : t_dp_sosi_arr(c_sdp_jesd204b_nof_streams-1 DOWNTO 0);         
+  SIGNAL ant_sosi_arr               : t_dp_sosi_arr(c_sdp_jesd204b_nof_streams-1 DOWNTO 0);
   SIGNAL bs_sosi                    : t_dp_sosi;    
-  SIGNAL wg_sosi_arr                : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);    
-  SIGNAL mux_sosi_arr               : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);         
-  SIGNAL nxt_mux_sosi_arr           : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
-  SIGNAL st_sosi_arr                : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);    
+  SIGNAL wg_sosi_arr                : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);    
+  SIGNAL mux_sosi_arr               : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);         
+  SIGNAL nxt_mux_sosi_arr           : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
+  SIGNAL st_sosi_arr                : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);    
 
+  SIGNAL mm_rst_internal            : STD_LOGIC; 
+  SIGNAL mm_jesd_ctrl_reg           : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+  SIGNAL jesd204b_disable_arr       : STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0);
+  SIGNAL jesd204b_reset             : STD_LOGIC;
 
 BEGIN
 
+  -- The node AIT is reset at power up by mm_rst and under software control by jesd204b_reset.
+  -- The mm_rst internal will cause a reset on the rx_rst by the reset sequencer in the u_jesd204b.
+  -- The MM jesd204b_reset is intended for node AIT resynchronisation tests of the u_jesd204b.
+  -- The MM jesd204b_reset should not be applied in an SDP application, because this will cause
+  -- a disturbance in the block timing of the out_sosi_arr(i).sync,bsn,sop,eop. The other logic
+  -- in an SDP application assumes that the block timing of the out_sosi_arr(i) only contains
+  -- complete blocks, so from sop to eop.
+
+  mm_rst_internal <= mm_rst OR mm_jesd_ctrl_reg(31);
+  gen_jesd_disable : FOR I IN 0 TO c_sdp_jesd204b_nof_streams-1 GENERATE
+    jesd204b_disable_arr(i) <= mm_jesd_ctrl_reg(i);
+  END GENERATE;
+
   -----------------------------------------------------------------------------
   -- JESD204B IP (ADC Handler)
   -----------------------------------------------------------------------------
   
   u_jesd204b: ENTITY tech_jesd204b_lib.tech_jesd204b 
   GENERIC MAP(
-    g_sim                => g_sim,     
-    g_technology         => g_technology,           
-    g_nof_streams        => c_nof_streams_jesd204b,
-    g_nof_sync_n         => g_nof_sync_n        
+    g_sim                => g_sim,                
+    g_nof_streams        => c_sdp_jesd204b_nof_streams,
+    g_nof_sync_n         => c_sdp_jesd204b_nof_sync_n,
+    g_jesd_freq          => c_sdp_jesd204b_freq
   )
   PORT MAP(
     jesd204b_refclk      => JESD204B_REFCLK,   
@@ -175,57 +186,22 @@ BEGIN
     rx_clk               => rx_clk,          
     rx_rst               => rx_rst,          
     rx_sysref            => rx_sysref,          
+
+    jesd204b_disable_arr  => jesd204b_disable_arr,
   
     -- MM
     mm_clk               => mm_clk,           
-    mm_rst               => mm_rst,           
+    mm_rst               => mm_rst_internal,           
   
     jesd204b_mosi        => jesd204b_mosi,         
     jesd204b_miso        => jesd204b_miso,         
   
      -- Serial
     serial_tx_arr        => open,
-    serial_rx_arr        => JESD204B_SERIAL_DATA(c_nof_streams_jesd204b-1 downto 0)
+    serial_rx_arr        => JESD204B_SERIAL_DATA(c_sdp_jesd204b_nof_streams-1 downto 0)
   );
 
 
-  gen_jesd_mon_in : FOR i IN 0 TO c_nof_streams_db-1 GENERATE
-    diag_data_buf_snk_in_arr(i).data(c_data_w-1 downto 0) <= rx_sosi_arr(i).data(c_data_w-1 downto 0);
-    diag_data_buf_snk_in_arr(i).valid <= rx_sosi_arr(i).valid;
-    diag_data_buf_snk_in_arr(i).sop   <= '0';
-    diag_data_buf_snk_in_arr(i).eop   <= '0';
-    diag_data_buf_snk_in_arr(i).err   <= (OTHERS=>'0');
-  END GENERATE;
-
-
-  -----------------------------------------------------------------------------
-  -- Diagnostic Data Buffer (Records 1024 raw ADC samples after the PPS)
-  --   ToDo: Remove this JESD DB when the second (BSN) data buffer is working correctly
-  -----------------------------------------------------------------------------
-
-  u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
-  GENERIC MAP (
-    g_technology   => g_technology,
-    g_nof_streams  => c_nof_streams_db,
-    g_data_w       => c_data_w,
-    g_buf_nof_data => 1024,
-    g_buf_use_sync => TRUE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
-  )
-  PORT MAP (
-    mm_rst            => mm_rst,
-    mm_clk            => mm_clk,
-    dp_rst            => rx_rst,
-    dp_clk            => rx_clk,
-
-    ram_data_buf_mosi => ram_diag_data_buf_jesd_mosi,
-    ram_data_buf_miso => ram_diag_data_buf_jesd_miso,
-    reg_data_buf_mosi => reg_diag_data_buf_jesd_mosi,
-    reg_data_buf_miso => reg_diag_data_buf_jesd_miso,
-
-    in_sosi_arr       => diag_data_buf_snk_in_arr,
-    in_sync           => rx_sysref
-  );
-
   -----------------------------------------------------------------------------
   -- Time delay: dp_shiftram
   -- . copied from unb1_bn_capture_input (apertif)
@@ -233,7 +209,7 @@ BEGIN
   -- . the input valid is always '1', even when there is no data 
   -----------------------------------------------------------------------------
   
-  gen_force_valid : FOR I IN 0 TO c_nof_streams_jesd204b-1 GENERATE
+  gen_force_valid : FOR I IN 0 TO c_sdp_jesd204b_nof_streams-1 GENERATE
     p_sosi : PROCESS(rx_sosi_arr)
     BEGIN
       dp_shiftram_snk_in_arr(I)       <= rx_sosi_arr(I);
@@ -244,16 +220,16 @@ BEGIN
 
   u_dp_shiftram : ENTITY dp_lib.dp_shiftram
   GENERIC MAP (
-    g_nof_streams => c_nof_streams_jesd204b, 
-    g_nof_words   => c_dp_shiftram_nof_samples,
-    g_data_w      => c_data_w, 
+    g_nof_streams => c_sdp_jesd204b_nof_streams, 
+    g_nof_words   => c_sdp_V_sample_delay,
+    g_data_w      => c_sdp_W_adc_jesd, 
     g_use_sync_in => TRUE
   )
   PORT MAP (
     dp_rst   => rx_rst,
     dp_clk   => rx_clk,
 
-    mm_rst   => mm_rst,
+    mm_rst   => mm_rst_internal,
     mm_clk   => mm_clk,
 
     sync_in  => bs_sosi.sync,
@@ -278,7 +254,7 @@ BEGIN
   )
   PORT MAP (
     -- Clocks and reset
-    mm_rst            => mm_rst,
+    mm_rst            => mm_rst_internal,
     mm_clk            => mm_clk,
     dp_rst            => rx_rst,
     dp_clk            => rx_clk,
@@ -299,7 +275,7 @@ BEGIN
   )
   PORT MAP (
     -- Memory-mapped clock domain
-    mm_rst      => mm_rst,
+    mm_rst      => mm_rst_internal,
     mm_clk      => mm_clk,
 
     reg_mosi    => reg_bsn_scheduler_wg_mosi,
@@ -320,7 +296,7 @@ BEGIN
 
   u_wg_arr : ENTITY diag_lib.mms_diag_wg_wideband_arr
   GENERIC MAP (
-    g_nof_streams        => g_nof_streams, 
+    g_nof_streams        => c_sdp_S_pn, 
     g_cross_clock_domain => TRUE,
     g_buf_dir            => c_wg_buf_directory,
 
@@ -332,11 +308,11 @@ BEGIN
     g_buf_addr_w         => c_wg_buf_addr_w,
     g_calc_support       => TRUE,
     g_calc_gain_w        => 1,
-    g_calc_dat_w         => c_wg_buf_dat_w
+    g_calc_dat_w         => c_sdp_W_adc
   )
   PORT MAP (
     -- Memory-mapped clock domain
-    mm_rst              => mm_rst,
+    mm_rst              => mm_rst_internal,
     mm_clk              => mm_clk,
 
     reg_mosi            => reg_wg_mosi,
@@ -358,7 +334,7 @@ BEGIN
   -- ADC/WG Mux (Input Select)
   -----------------------------------------------------------------------------
   
-  gen_mux : FOR I IN 0 TO g_nof_streams-1 GENERATE
+  gen_mux : FOR I IN 0 TO c_sdp_S_pn-1 GENERATE
     p_sosi : PROCESS(ant_sosi_arr(I), wg_sosi_arr(I))
     BEGIN
       -- Default use the ADC data
@@ -376,7 +352,7 @@ BEGIN
   -- Concatenate muxed data streams with bsn framing
   -----------------------------------------------------------------------------
   
-  gen_concat : FOR I IN 0 TO g_nof_streams-1 GENERATE
+  gen_concat : FOR I IN 0 TO c_sdp_S_pn-1 GENERATE
     p_sosi : PROCESS(mux_sosi_arr(I), bs_sosi)
     BEGIN
       st_sosi_arr(I)       <= bs_sosi;
@@ -405,7 +381,7 @@ BEGIN
   )
   PORT MAP (
     -- Memory-mapped clock domain
-    mm_rst      => mm_rst,
+    mm_rst      => mm_rst_internal,
     mm_clk      => mm_clk,
     reg_mosi    => reg_bsn_monitor_input_mosi,
     reg_miso    => reg_bsn_monitor_input_miso,
@@ -423,22 +399,20 @@ BEGIN
   u_aduh_monitor : ENTITY aduh_lib.mms_aduh_monitor_arr
   GENERIC MAP (
     g_cross_clock_domain   => TRUE,
-    g_nof_streams          => g_nof_streams,
-    g_symbol_w             => c_data_w,   --TBD 16?
+    g_nof_streams          => c_sdp_S_pn,
+    g_symbol_w             => c_sdp_W_adc_jesd,   --TBD 16?
     g_nof_symbols_per_data => 1,          -- Wideband factor is 1          
-    g_nof_accumulations    => 200000512,  -- = 195313 blocks * 1024 samples
-    g_buffer_nof_symbols   => g_aduh_buffer_nof_symbols,  -- default 512, larger for full design
-    g_buffer_use_sync      => TRUE        -- True to capture all streams synchronously
+    g_nof_accumulations    => 200000512   -- = 195313 blocks * 1024 samples
   )
   PORT MAP (
     -- Memory-mapped clock domain
-    mm_rst         => mm_rst,
+    mm_rst         => mm_rst_internal,
     mm_clk         => mm_clk,
 
     reg_mosi       => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
     reg_miso       => reg_aduh_monitor_miso,
-    buf_mosi       => ram_aduh_monitor_mosi, -- read and overwrite access to the signal path data buffers
-    buf_miso       => ram_aduh_monitor_miso,
+    buf_mosi       => c_mm_mosi_rst,         -- Unused
+    buf_miso       => OPEN,
 
     -- Streaming clock domain
     st_rst         => rx_rst,
@@ -448,20 +422,20 @@ BEGIN
   );
 
 
- -----------------------------------------------------------------------------
--- Diagnostic Data Buffer
+  -----------------------------------------------------------------------------
+  -- Diagnostic Data Buffer
   -----------------------------------------------------------------------------
 
   u_diag_data_buffer_bsn : ENTITY diag_lib.mms_diag_data_buffer
   GENERIC MAP (
     g_technology   => g_technology,
-    g_nof_streams  => g_nof_streams,
-    g_data_w       => c_data_w,
+    g_nof_streams  => c_sdp_S_pn,
+    g_data_w       => c_sdp_W_adc_jesd,
     g_buf_nof_data => g_buf_nof_data,
     g_buf_use_sync => TRUE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
   )
   PORT MAP (
-    mm_rst            => mm_rst,
+    mm_rst            => mm_rst_internal,
     mm_clk            => mm_clk,
     dp_rst            => rx_rst,
     dp_clk            => rx_clk,
@@ -481,10 +455,10 @@ BEGIN
   --   . Thin dual clock fifo to cross from jesd frame clock (rx_clk) to dp_clk domain
   -----------------------------------------------------------------------------
  
-  gen_dp_fifo_dc : FOR I IN 0 TO g_nof_streams-1 GENERATE
+  gen_dp_fifo_dc : FOR I IN 0 TO c_sdp_S_pn-1 GENERATE
     u_dp_fifo_dc : ENTITY dp_lib.dp_fifo_dc
       GENERIC MAP (
-        g_data_w         => c_data_w,
+        g_data_w         => c_sdp_W_adc_jesd,
         g_use_empty      => FALSE, --TRUE,
         g_use_ctrl       => TRUE,
         g_use_sync       => TRUE,
@@ -501,4 +475,28 @@ BEGIN
       );
   END GENERATE;
 
+  -----------------------------------------------------------------------------
+  -- JESD Control register
+  -----------------------------------------------------------------------------
+  u_mm_jesd_ctrl_reg : ENTITY common_lib.common_reg_r_w
+  GENERIC MAP (
+    g_reg       => c_sdp_jesd204b_mm_jesd_ctrl_reg,
+    g_init_reg  => (OTHERS => '0')
+  )
+  PORT MAP (
+    rst       => mm_rst,
+    clk       => mm_clk,
+    -- control side
+    wr_en     => jesd_ctrl_mosi.wr,
+    wr_adr    => jesd_ctrl_mosi.address(c_sdp_jesd204b_mm_jesd_ctrl_reg.adr_w-1 DOWNTO 0),
+    wr_dat    => jesd_ctrl_mosi.wrdata(c_sdp_jesd204b_mm_jesd_ctrl_reg.dat_w-1 DOWNTO 0),
+    rd_en     => jesd_ctrl_mosi.rd,
+    rd_adr    => jesd_ctrl_mosi.address(c_sdp_jesd204b_mm_jesd_ctrl_reg.adr_w-1 DOWNTO 0),
+    rd_dat    => jesd_ctrl_miso.rddata(c_sdp_jesd204b_mm_jesd_ctrl_reg.dat_w-1 DOWNTO 0),
+    rd_val    => OPEN,
+    -- data side
+    out_reg   => mm_jesd_ctrl_reg,
+    in_reg    => mm_jesd_ctrl_reg
+  );
+
 END str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 4e6691032fa2714d9e381802cf2cfae89d1640f6..5786f13b90612472c21088cf03794f9318cba41e 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -95,16 +95,17 @@ PACKAGE sdp_pkg is
   CONSTANT c_sdp_W_beamlet_scale : NATURAL := 16; 
   CONSTANT c_sdp_W_gn_id         : NATURAL := 5;
   CONSTANT c_sdp_N_pn_lb         : NATURAL := 16;
+  CONSTANT c_sdp_S_rcu           : NATURAL := 3;
+  CONSTANT c_sdp_V_sample_delay  : NATURAL := 4096;
+  CONSTANT c_sdp_W_adc_jesd      : NATURAL := 16; 
+  CONSTANT c_sdp_V_si_db         : NATURAL := 1024;
+  CONSTANT c_sdp_V_si_db_large   : NATURAL := 131072;
 
   -- 
   CONSTANT c_sdp_marker_sst : NATURAL := 83;  -- = 0x53 = 'S'
   CONSTANT c_sdp_marker_bst : NATURAL := 66;  -- = 0x42 = 'B'
   CONSTANT c_sdp_marker_xst : NATURAL := 88;  -- = 0x58 = 'X'
 
-  -- AIT constants
-  CONSTANT c_sdp_ait_buf_nof_data_jesd : NATURAL := 1024; -- 1024 14 bit samples fit in one M20k BRAM 
-  CONSTANT c_sdp_ait_buf_nof_data_bsn  : NATURAL := 1024; -- 1024 14 bit samples fit in one M20k BRAM
- 
   -- In SDP c_nof_channels = 2**nof_chan = 1 and wb_factor = 1, 
   -- therefore these parameters are not explicitly used in calculation of derived constants
   -- LTS 2020_11_23:
@@ -128,8 +129,17 @@ PACKAGE sdp_pkg is
    c_fil_ppf_pipeline);
 
   -- JESD204
-  CONSTANT c_sdp_jesd204b_bus_w   : NATURAL := 12;
-  CONSTANT c_sdp_jesd204b_nof_bus : NATURAL := 1;
+  CONSTANT c_sdp_jesd204b_freq        : STRING := "200MHz";
+  CONSTANT c_sdp_jesd204b_bus_w       : NATURAL := 12;
+  CONSTANT c_sdp_jesd204b_nof_bus     : NATURAL := 1;
+  CONSTANT c_sdp_jesd204b_nof_streams : NATURAL := c_sdp_jesd204_bus_w*c_sdp_jesd204b_nof_bus;
+  CONSTANT c_sdp_jesd204b_nof_sync_n  : NATURAL := c_sdp_jesd204b_bus_w/c_sdp_S_rcu; -- Three ADCs per RCU share a sync 
+
+  CONSTANT c_sdp_jesd204b_mm_jesd_ctrl_reg : t_c_mem := (latency  => 1,
+                                                         adr_w    => 1,
+                                                         dat_w    => c_word_w,
+                                                         nof_dat  => 1,
+                                                         init_sl  => '0');
 
   -- AIT MM address widths
   CONSTANT c_sdp_jesd204b_addr_w               : NATURAL := 8 + ceil_log2(c_sdp_S_pn);