From f6f75d08e9eb7621a3b1eaa85f57236fa30b6a26 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Mon, 7 Dec 2020 10:28:25 +0100
Subject: [PATCH] Added ta2_unb2b_mm_io to ta2_unb2b_bsp
---
.../ta2/bsp/hardware/ta2_unb2b_bsp/board.qsys | 2070 ++++-------------
.../bsp/hardware/ta2_unb2b_bsp/board_spec.xml | 4 +-
.../ta2/bsp/hardware/ta2_unb2b_bsp/flat.qsf | 10 +-
.../ta2_unb2b_bsp/ip/board/board_cpu_0.ip | 4 +-
...ctrl_1.ip => board_reg_ta2_unb2b_mm_io.ip} | 189 +-
.../ta2_unb2b_bsp/ip/board/reg_mmdp_data_1.ip | 1525 ------------
.../ta2_unb2b_bsp/ip/freeze_wrapper.v | 8 +-
.../bsp/hardware/ta2_unb2b_bsp/ip/pr_region.v | 8 +-
.../hardware/ta2_unb2b_bsp/opencl_bsp_ip.qsf | 1 +
.../ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd | 62 +-
.../ta2_unb2b_bsp/top_components_pkg.vhd | 227 +-
.../ta2/ip/ta2_unb2b_mm_io/hdllib.cfg | 1 +
.../ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd | 275 ++-
.../ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd | 179 ++
14 files changed, 1090 insertions(+), 3473 deletions(-)
rename applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/board/{reg_mmdp_ctrl_1.ip => board_reg_ta2_unb2b_mm_io.ip} (90%)
delete mode 100644 applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/board/reg_mmdp_data_1.ip
create mode 100644 applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/board.qsys b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/board.qsys
index fe8629ef04..fc981d16a0 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/board.qsys
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/board.qsys
@@ -46,7 +46,7 @@
{
datum _sortIndex
{
- value = "25";
+ value = "24";
type = "int";
}
}
@@ -86,7 +86,7 @@
{
datum baseAddress
{
- value = "968";
+ value = "952";
type = "String";
}
}
@@ -102,7 +102,7 @@
{
datum _sortIndex
{
- value = "28";
+ value = "27";
type = "int";
}
}
@@ -110,7 +110,7 @@
{
datum _sortIndex
{
- value = "24";
+ value = "23";
type = "int";
}
}
@@ -118,7 +118,7 @@
{
datum _sortIndex
{
- value = "22";
+ value = "21";
type = "int";
}
}
@@ -134,7 +134,7 @@
{
datum _sortIndex
{
- value = "26";
+ value = "25";
type = "int";
}
}
@@ -142,7 +142,7 @@
{
datum _sortIndex
{
- value = "23";
+ value = "22";
type = "int";
}
}
@@ -158,7 +158,7 @@
{
datum _sortIndex
{
- value = "27";
+ value = "26";
type = "int";
}
}
@@ -208,7 +208,7 @@
{
datum baseAddress
{
- value = "960";
+ value = "944";
type = "String";
}
}
@@ -266,7 +266,7 @@
{
datum baseAddress
{
- value = "952";
+ value = "936";
type = "String";
}
}
@@ -287,7 +287,7 @@
{
datum baseAddress
{
- value = "944";
+ value = "928";
type = "String";
}
}
@@ -366,23 +366,7 @@
{
datum baseAddress
{
- value = "936";
- type = "String";
- }
- }
- element reg_mmdp_ctrl_1
- {
- datum _sortIndex
- {
- value = "29";
- type = "int";
- }
- }
- element reg_mmdp_ctrl_1.mem
- {
- datum baseAddress
- {
- value = "912";
+ value = "920";
type = "String";
}
}
@@ -403,56 +387,56 @@
{
datum baseAddress
{
- value = "928";
+ value = "912";
type = "String";
}
}
- element reg_mmdp_data_1
+ element reg_remu
{
datum _sortIndex
{
- value = "30";
+ value = "14";
type = "int";
}
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
}
- element reg_mmdp_data_1.mem
+ element reg_remu.mem
{
datum baseAddress
{
- value = "920";
+ value = "864";
type = "String";
}
}
- element reg_remu
+ element reg_ta2_unb2b_jesd204b
{
datum _sortIndex
{
- value = "14";
+ value = "28";
type = "int";
}
- datum sopceditor_expanded
- {
- value = "0";
- type = "boolean";
- }
}
- element reg_remu.mem
+ element reg_ta2_unb2b_jesd204b.mem
{
datum baseAddress
{
- value = "864";
+ value = "13312";
type = "String";
}
}
- element reg_ta2_unb2b_jesd204b
+ element reg_ta2_unb2b_mm_io
{
datum _sortIndex
{
- value = "21";
+ value = "29";
type = "int";
}
}
- element reg_ta2_unb2b_jesd204b.mem
+ element reg_ta2_unb2b_mm_io.mem
{
datum baseAddress
{
@@ -1070,41 +1054,6 @@
internal="reg_fpga_voltage_sens.writedata"
type="conduit"
dir="end" />
- <interface
- name="reg_mmdp_ctrl_1_address"
- internal="reg_mmdp_ctrl_1.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_mmdp_ctrl_1_clk"
- internal="reg_mmdp_ctrl_1.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_mmdp_ctrl_1_read"
- internal="reg_mmdp_ctrl_1.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_mmdp_ctrl_1_readdata"
- internal="reg_mmdp_ctrl_1.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_mmdp_ctrl_1_reset"
- internal="reg_mmdp_ctrl_1.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_mmdp_ctrl_1_write"
- internal="reg_mmdp_ctrl_1.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_mmdp_ctrl_1_writedata"
- internal="reg_mmdp_ctrl_1.writedata"
- type="conduit"
- dir="end" />
<interface
name="reg_mmdp_ctrl_address"
internal="reg_mmdp_ctrl.address"
@@ -1140,41 +1089,6 @@
internal="reg_mmdp_ctrl.writedata"
type="conduit"
dir="end" />
- <interface
- name="reg_mmdp_data_1_address"
- internal="reg_mmdp_data_1.address"
- type="conduit"
- dir="end" />
- <interface
- name="reg_mmdp_data_1_clk"
- internal="reg_mmdp_data_1.clk"
- type="conduit"
- dir="end" />
- <interface
- name="reg_mmdp_data_1_read"
- internal="reg_mmdp_data_1.read"
- type="conduit"
- dir="end" />
- <interface
- name="reg_mmdp_data_1_readdata"
- internal="reg_mmdp_data_1.readdata"
- type="conduit"
- dir="end" />
- <interface
- name="reg_mmdp_data_1_reset"
- internal="reg_mmdp_data_1.reset"
- type="conduit"
- dir="end" />
- <interface
- name="reg_mmdp_data_1_write"
- internal="reg_mmdp_data_1.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_mmdp_data_1_writedata"
- internal="reg_mmdp_data_1.writedata"
- type="conduit"
- dir="end" />
<interface
name="reg_mmdp_data_address"
internal="reg_mmdp_data.address"
@@ -1281,6 +1195,46 @@
internal="reg_ta2_unb2b_jesd204b.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_ta2_unb2b_mm_io_address"
+ internal="reg_ta2_unb2b_mm_io.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ta2_unb2b_mm_io_clk"
+ internal="reg_ta2_unb2b_mm_io.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ta2_unb2b_mm_io_read"
+ internal="reg_ta2_unb2b_mm_io.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ta2_unb2b_mm_io_readdata"
+ internal="reg_ta2_unb2b_mm_io.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ta2_unb2b_mm_io_reset"
+ internal="reg_ta2_unb2b_mm_io.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ta2_unb2b_mm_io_waitrequest"
+ internal="reg_ta2_unb2b_mm_io.waitrequest"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ta2_unb2b_mm_io_write"
+ internal="reg_ta2_unb2b_mm_io.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ta2_unb2b_mm_io_writedata"
+ internal="reg_ta2_unb2b_mm_io.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_unb_pmbus_address"
internal="reg_unb_pmbus.address"
@@ -6801,7 +6755,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_ctrl_1.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_data_1.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='pio_pps.mem' start='0x3C0' end='0x3C8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3C8' end='0x3D0' datawidth='32' /><slave name='reg_ta2_unb2b_jesd204b.mem' start='0x400' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /><slave name='kernel_clk_gen.ctrl' start='0x9000' end='0xA000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='reg_ta2_unb2b_mm_io.mem' start='0x400' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ta2_unb2b_jesd204b.mem' start='0x3400' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /><slave name='kernel_clk_gen.ctrl' start='0x9000' end='0xA000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -25536,7 +25490,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_ctrl_1"
+ name="reg_mmdp_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -26124,17 +26078,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -26143,28 +26097,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -26177,11 +26130,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -26234,17 +26189,21 @@
</ports>
<assignments>
<assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>false</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>false</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>false</value>
+ <value>0</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -26284,6 +26243,7 @@
</entry>
<entry>
<key>bridgedAddressOffset</key>
+ <value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
@@ -26416,44 +26376,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -26480,15 +26408,15 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26512,49 +26440,17 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
- <width>32</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -26576,12 +26472,75 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -26608,14 +26567,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -26642,37 +26601,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>reg_mmdp_ctrl_1</hdlLibraryName>
+ <hdlLibraryName>board_reg_mmdp_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>reg_mmdp_ctrl_1</fileSetName>
- <fileSetFixedName>reg_mmdp_ctrl_1</fileSetFixedName>
+ <fileSetName>board_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>reg_mmdp_ctrl_1</fileSetName>
- <fileSetFixedName>reg_mmdp_ctrl_1</fileSetFixedName>
+ <fileSetName>board_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>reg_mmdp_ctrl_1</fileSetName>
- <fileSetFixedName>reg_mmdp_ctrl_1</fileSetFixedName>
+ <fileSetName>board_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/reg_mmdp_ctrl_1.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_mmdp_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_data"
+ name="reg_remu"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -26688,7 +26647,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26752,7 +26711,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26821,7 +26780,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -27227,11 +27186,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -27268,7 +27227,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27332,7 +27291,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27401,7 +27360,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -27783,37 +27742,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_mmdp_data</hdlLibraryName>
+ <hdlLibraryName>board_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_mmdp_data</fileSetName>
- <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>board_reg_remu</fileSetName>
+ <fileSetFixedName>board_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_mmdp_data</fileSetName>
- <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>board_reg_remu</fileSetName>
+ <fileSetFixedName>board_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_mmdp_data</fileSetName>
- <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>board_reg_remu</fileSetName>
+ <fileSetFixedName>board_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_mmdp_data.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_data_1"
+ name="reg_ta2_unb2b_jesd204b"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -27829,7 +27788,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27893,7 +27852,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27929,6 +27888,14 @@
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
+ <port>
+ <name>avs_mem_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
</ports>
<assignments>
<assignmentValueMap>
@@ -27962,7 +27929,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -28065,15 +28032,15 @@
</entry>
<entry>
<key>readLatency</key>
- <value>1</value>
+ <value>0</value>
</entry>
<entry>
<key>readWaitStates</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>readWaitTime</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
@@ -28277,6 +28244,38 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>waitrequest</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_waitrequest_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
<interface>
<name>write</name>
<type>conduit</type>
@@ -28344,9 +28343,9 @@
</interfaces>
</boundary>
<originalModuleInfo>
- <className>avs_common_mm</className>
+ <className>avs_common_mm_readlatency0</className>
<version>1.0</version>
- <displayName>avs_common_mm</displayName>
+ <displayName>avs_common_mm_readlatency0</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
@@ -28368,11 +28367,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>10</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -28401,17 +28400,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -28420,27 +28419,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -28453,13 +28453,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -28473,7 +28471,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28509,24 +28507,28 @@
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
+ <port>
+ <name>avs_mem_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
</ports>
<assignments>
<assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
+ <value>false</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
+ <value>false</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
+ <value>false</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -28542,7 +28544,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -28566,7 +28568,6 @@
</entry>
<entry>
<key>bridgedAddressOffset</key>
- <value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
@@ -28645,15 +28646,15 @@
</entry>
<entry>
<key>readLatency</key>
- <value>1</value>
+ <value>0</value>
</entry>
<entry>
<key>readWaitStates</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>readWaitTime</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
@@ -28699,12 +28700,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -28731,17 +28732,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -28762,785 +28763,6 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition>]]></parameter>
- <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>reg_mmdp_data_1</hdlLibraryName>
- <fileSets>
- <fileSet>
- <fileSetName>reg_mmdp_data_1</fileSetName>
- <fileSetFixedName>reg_mmdp_data_1</fileSetFixedName>
- <fileSetKind>QUARTUS_SYNTH</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>reg_mmdp_data_1</fileSetName>
- <fileSetFixedName>reg_mmdp_data_1</fileSetFixedName>
- <fileSetKind>SIM_VERILOG</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- <fileSet>
- <fileSetName>reg_mmdp_data_1</fileSetName>
- <fileSetFixedName>reg_mmdp_data_1</fileSetFixedName>
- <fileSetKind>SIM_VHDL</fileSetKind>
- <fileSetFiles/>
- </fileSet>
- </fileSets>
-</generationInfoDefinition>]]></parameter>
- <parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/reg_mmdp_data_1.ip</parameter>
- <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
- <assignmentValueMap/>
-</assignmentDefinition>]]></parameter>
- <parameter name="svInterfaceDefinition" value="" />
- </module>
- <module
- name="reg_remu"
- kind="altera_generic_component"
- version="1.0"
- enabled="1">
- <parameter name="componentDefinition"><![CDATA[<componentDefinition>
- <boundary>
- <interfaces>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>3</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>3</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>32</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
- </boundary>
- <originalModuleInfo>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <displayName>avs_common_mm</displayName>
- </originalModuleInfo>
- <systemInfoParameterDescriptors>
- <descriptors>
- <descriptor>
- <parameterDefaultValue>-1</parameterDefaultValue>
- <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
- <parameterType>java.lang.Long</parameterType>
- <systemInfoArgs>system</systemInfoArgs>
- <systemInfotype>CLOCK_RATE</systemInfotype>
- </descriptor>
- </descriptors>
- </systemInfoParameterDescriptors>
- <systemInfos>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>5</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- </connPtSystemInfos>
- </systemInfos>
-</componentDefinition>]]></parameter>
- <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
- <interfaces>
<interface>
<name>address</name>
<type>conduit</type>
@@ -29550,7 +28772,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29574,12 +28796,12 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -29606,45 +28828,13 @@
</parameters>
</interface>
<interface>
- <name>mem</name>
- <type>avalon</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>3</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
+ <name>coe_writedata_export</name>
+ <role>export</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
@@ -29652,190 +28842,20 @@
</port>
</ports>
<assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
+ <assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>32</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
</parameterValueMap>
</parameters>
</interface>
@@ -29904,78 +28924,13 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>waitrequest</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_waitrequest_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -29985,68 +28940,6 @@
<assignments>
<assignmentValueMap/>
</assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
<parameters>
<parameterValueMap>
<entry>
@@ -30065,37 +28958,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_remu</hdlLibraryName>
+ <hdlLibraryName>board_reg_ta2_unb2b_jesd204b</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_remu</fileSetName>
- <fileSetFixedName>board_reg_remu</fileSetFixedName>
+ <fileSetName>board_reg_ta2_unb2b_jesd204b</fileSetName>
+ <fileSetFixedName>board_reg_ta2_unb2b_jesd204b</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_remu</fileSetName>
- <fileSetFixedName>board_reg_remu</fileSetFixedName>
+ <fileSetName>board_reg_ta2_unb2b_jesd204b</fileSetName>
+ <fileSetFixedName>board_reg_ta2_unb2b_jesd204b</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_remu</fileSetName>
- <fileSetFixedName>board_reg_remu</fileSetFixedName>
+ <fileSetName>board_reg_ta2_unb2b_jesd204b</fileSetName>
+ <fileSetFixedName>board_reg_ta2_unb2b_jesd204b</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_remu.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_ta2_unb2b_jesd204b.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_ta2_unb2b_jesd204b"
+ name="reg_ta2_unb2b_mm_io"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -30103,17 +28996,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>8</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -30122,27 +29015,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -30155,13 +29049,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -30409,12 +29301,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -30441,17 +29333,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -30473,17 +29365,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -30505,14 +29397,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -30524,31 +29416,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -30558,24 +29449,26 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>waitrequest</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_waitrequest_export</name>
+ <name>coe_read_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -30600,17 +29493,17 @@
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -30632,17 +29525,17 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>waitrequest</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_waitrequest_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -30723,17 +29616,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>8</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -30742,27 +29635,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -30775,13 +29669,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -31029,12 +29921,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -31061,17 +29953,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -31093,17 +29985,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -31125,14 +30017,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -31144,31 +30036,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -31178,24 +30069,26 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>waitrequest</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_waitrequest_export</name>
+ <name>coe_read_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -31220,17 +30113,17 @@
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -31252,17 +30145,17 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>waitrequest</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_waitrequest_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -31286,30 +30179,30 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_ta2_unb2b_jesd204b</hdlLibraryName>
+ <hdlLibraryName>board_reg_ta2_unb2b_mm_io</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_ta2_unb2b_jesd204b</fileSetName>
- <fileSetFixedName>board_reg_ta2_unb2b_jesd204b</fileSetFixedName>
+ <fileSetName>board_reg_ta2_unb2b_mm_io</fileSetName>
+ <fileSetFixedName>board_reg_ta2_unb2b_mm_io</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_ta2_unb2b_jesd204b</fileSetName>
- <fileSetFixedName>board_reg_ta2_unb2b_jesd204b</fileSetFixedName>
+ <fileSetName>board_reg_ta2_unb2b_mm_io</fileSetName>
+ <fileSetFixedName>board_reg_ta2_unb2b_mm_io</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_ta2_unb2b_jesd204b</fileSetName>
- <fileSetFixedName>board_reg_ta2_unb2b_jesd204b</fileSetFixedName>
+ <fileSetName>board_reg_ta2_unb2b_mm_io</fileSetName>
+ <fileSetFixedName>board_reg_ta2_unb2b_mm_io</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_ta2_unb2b_jesd204b.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_ta2_unb2b_mm_io.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -37189,7 +36082,7 @@
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x03c8" />
+ <parameter name="baseAddress" value="0x03b8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -37329,7 +36222,7 @@
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x03c0" />
+ <parameter name="baseAddress" value="0x03b0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -37409,7 +36302,7 @@
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x03b8" />
+ <parameter name="baseAddress" value="0x03a8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -37429,7 +36322,7 @@
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x03b0" />
+ <parameter name="baseAddress" value="0x03a0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -37449,7 +36342,7 @@
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x03a8" />
+ <parameter name="baseAddress" value="0x0398" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -37469,7 +36362,7 @@
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x03a0" />
+ <parameter name="baseAddress" value="0x0390" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -37549,27 +36442,7 @@
start="cpu_0.data_master"
end="reg_ta2_unb2b_jesd204b.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0400" />
- <parameter name="defaultConnection" value="false" />
- <parameter name="domainAlias" value="" />
- <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
- <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
- <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
- <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
- <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
- <parameter name="qsys_mm.interconnectType" value="STANDARD" />
- <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
- <parameter name="qsys_mm.syncResets" value="FALSE" />
- <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
- </connection>
- <connection
- kind="avalon"
- version="19.2"
- start="cpu_0.data_master"
- end="reg_mmdp_data_1.mem">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0398" />
+ <parameter name="baseAddress" value="0x3400" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -37587,9 +36460,9 @@
kind="avalon"
version="19.2"
start="cpu_0.data_master"
- end="reg_mmdp_ctrl_1.mem">
+ end="reg_ta2_unb2b_mm_io.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0390" />
+ <parameter name="baseAddress" value="0x0400" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -37871,12 +36744,7 @@
kind="clock"
version="19.2"
start="clk_0.clk"
- end="reg_mmdp_data_1.system" />
- <connection
- kind="clock"
- version="19.2"
- start="clk_0.clk"
- end="reg_mmdp_ctrl_1.system" />
+ end="reg_ta2_unb2b_mm_io.system" />
<connection
kind="clock"
version="19.2"
@@ -38044,12 +36912,7 @@
kind="reset"
version="19.2"
start="clk_0.clk_reset"
- end="reg_mmdp_data_1.system_reset" />
- <connection
- kind="reset"
- version="19.2"
- start="clk_0.clk_reset"
- end="reg_mmdp_ctrl_1.system_reset" />
+ end="reg_ta2_unb2b_mm_io.system_reset" />
<connection
kind="reset"
version="19.2"
@@ -38174,12 +37037,7 @@
kind="reset"
version="19.2"
start="cpu_0.debug_reset_request"
- end="reg_mmdp_data_1.system_reset" />
- <connection
- kind="reset"
- version="19.2"
- start="cpu_0.debug_reset_request"
- end="reg_mmdp_ctrl_1.system_reset" />
+ end="reg_ta2_unb2b_mm_io.system_reset" />
<connection
kind="reset"
version="19.2"
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/board_spec.xml b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/board_spec.xml
index 69812e4833..dc120f9fc8 100755
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/board_spec.xml
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/board_spec.xml
@@ -48,7 +48,9 @@
<interface name="board" port="kernel_stream_snk_40GbE_ring_1" type="streamsink" width="264" chan_id="kernel_output_40GbE_ring_1"/>
<interface name="board" port="kernel_stream_src_ADC" type="streamsource" width="16" chan_id="kernel_input_ADC"/>
- <interface name="board" port="kernel_stream_src_mm_io" type="streamsource" width="32" chan_id="kernel_input_mm"/>
+
+ <interface name="board" port="kernel_stream_src_mm_io" type="streamsource" width="72" chan_id="kernel_input_mm"/>
+ <interface name="board" port="kernel_stream_snk_mm_io" type="streamsink" width="32" chan_id="kernel_output_mm"/>
</channels>
<host>
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/flat.qsf b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/flat.qsf
index c3fe092879..16cfdba084 100755
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/flat.qsf
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/flat.qsf
@@ -1279,17 +1279,19 @@ set_location_assignment PIN_T32 -to MB_II_IO.dqs_n[7]
set_global_assignment -name SIGNALTAP_FILE stp1.stp
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
+
+
set_global_assignment -name IP_FILE ip/ddr4/ddr4_ddr4a.ip
set_global_assignment -name IP_FILE ip/board/board_kernel_ddr4a_bridge.ip
set_global_assignment -name IP_FILE ip/mem/mem_pipe_stage_ddr4a_dimm.ip
set_global_assignment -name IP_FILE ip/mem/mem_reset_controller_ddr4a_pipe.ip
+set_global_assignment -name IP_FILE ip/ddr4/ddr4_pipe_stage_ddr4a_dimm_post_4th.ip
set_global_assignment -name IP_FILE ip/mem/mem_kernel_clk_in.ip
set_global_assignment -name IP_FILE ip/ddr4/ddr4_clock_bridge_0.ip
+set_global_assignment -name IP_FILE ip/mem/mem_global_reset_in.ip
set_global_assignment -name IP_FILE ip/board/board_kclk_global.ip
set_global_assignment -name IP_FILE ip/mem/mem_reset_controller_ddr4a.ip
-set_global_assignment -name IP_FILE ip/board/reg_mmdp_ctrl_1.ip
-set_global_assignment -name IP_FILE ip/ddr4/ddr4_pipe_stage_ddr4a_dimm_post_4th.ip
-set_global_assignment -name IP_FILE ip/mem/mem_global_reset_in.ip
set_global_assignment -name IP_FILE ip/ddr4/ddr4_reset_bridge_0.ip
-set_global_assignment -name IP_FILE ip/board/reg_mmdp_data_1.ip
set_global_assignment -name IP_FILE ip/mem/mem_clock_cross_kernel_to_ddr4a.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_ta2_unb2b_mm_io.ip
+set_global_assignment -name QSYS_FILE mem.qsys
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/board/board_cpu_0.ip b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/board/board_cpu_0.ip
index 5497c27568..81565d7d96 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/board/board_cpu_0.ip
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/board/board_cpu_0.ip
@@ -2302,7 +2302,7 @@
<ipxact:parameter parameterId="dataSlaveMapParam" type="string">
<ipxact:name>dataSlaveMapParam</ipxact:name>
<ipxact:displayName>dataSlaveMapParam</ipxact:displayName>
- <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_ctrl_1.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_data_1.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='pio_pps.mem' start='0x3C0' end='0x3C8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3C8' end='0x3D0' datawidth='32' /><slave name='reg_ta2_unb2b_jesd204b.mem' start='0x400' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /><slave name='kernel_clk_gen.ctrl' start='0x9000' end='0xA000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></ipxact:value>
+ <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='reg_ta2_unb2b_mm_io.mem' start='0x400' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ta2_unb2b_jesd204b.mem' start='0x3400' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /><slave name='kernel_clk_gen.ctrl' start='0x9000' end='0xA000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="tightlyCoupledDataMaster0MapParam" type="string">
<ipxact:name>tightlyCoupledDataMaster0MapParam</ipxact:name>
@@ -3589,7 +3589,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl_1.mem' start='0x390' end='0x398' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data_1.mem' start='0x398' end='0x3A0' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x3B0' end='0x3B8' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x3B8' end='0x3C0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x3C0' end='0x3C8' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x3C8' end='0x3D0' datawidth='32' /&gt;&lt;slave name='reg_ta2_unb2b_jesd204b.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /&gt;&lt;slave name='kernel_clk_gen.ctrl' start='0x9000' end='0xA000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /&gt;&lt;slave name='reg_ta2_unb2b_mm_io.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_ta2_unb2b_jesd204b.mem' start='0x3400' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /&gt;&lt;slave name='kernel_clk_gen.ctrl' start='0x9000' end='0xA000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/board/reg_mmdp_ctrl_1.ip b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/board/board_reg_ta2_unb2b_mm_io.ip
similarity index 90%
rename from applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/board/reg_mmdp_ctrl_1.ip
rename to applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/board/board_reg_ta2_unb2b_mm_io.ip
index 1a88dc850a..dd249ee85a 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/board/reg_mmdp_ctrl_1.ip
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/board/board_reg_ta2_unb2b_mm_io.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>reg_mmdp_ctrl_1</ipxact:library>
- <ipxact:name>reg_mmdp_ctrl_1</ipxact:name>
+ <ipxact:library>board_reg_ta2_unb2b_mm_io</ipxact:library>
+ <ipxact:name>board_reg_ta2_unb2b_mm_io</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -121,6 +121,14 @@
<ipxact:name>avs_mem_readdata</ipxact:name>
</ipxact:physicalPort>
</ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>waitrequest</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_waitrequest</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
</ipxact:portMaps>
</ipxact:abstractionType>
</ipxact:abstractionTypes>
@@ -139,7 +147,7 @@
<ipxact:parameter parameterId="addressSpan" type="string">
<ipxact:name>addressSpan</ipxact:name>
<ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>8</ipxact:value>
+ <ipxact:value>1024</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressUnits" type="string">
<ipxact:name>addressUnits</ipxact:name>
@@ -269,17 +277,17 @@
<ipxact:parameter parameterId="readLatency" type="int">
<ipxact:name>readLatency</ipxact:name>
<ipxact:displayName>Read latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
+ <ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="readWaitStates" type="int">
<ipxact:name>readWaitStates</ipxact:name>
<ipxact:displayName>Read wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
+ <ipxact:value>1</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="readWaitTime" type="int">
<ipxact:name>readWaitTime</ipxact:name>
<ipxact:displayName>Read wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
+ <ipxact:value>1</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="registerIncomingSignals" type="bit">
<ipxact:name>registerIncomingSignals</ipxact:name>
@@ -614,6 +622,43 @@
</ipxact:parameter>
</ipxact:parameters>
</ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>waitrequest</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_waitrequest_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
</ipxact:busInterfaces>
<ipxact:model>
<ipxact:views>
@@ -626,7 +671,7 @@
<ipxact:instantiations>
<ipxact:componentInstantiation>
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:moduleName>avs_common_mm_readlatency0</ipxact:moduleName>
<ipxact:fileSetRef>
<ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
</ipxact:fileSetRef>
@@ -664,7 +709,12 @@
<ipxact:name>avs_mem_address</ipxact:name>
<ipxact:wire>
<ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
@@ -735,6 +785,19 @@
</ipxact:wireTypeDefs>
</ipxact:wire>
</ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_waitrequest</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
<ipxact:port>
<ipxact:name>coe_reset_export</ipxact:name>
<ipxact:wire>
@@ -765,7 +828,12 @@
<ipxact:name>coe_address_export</ipxact:name>
<ipxact:wire>
<ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
@@ -836,13 +904,26 @@
</ipxact:wireTypeDefs>
</ipxact:wire>
</ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_waitrequest_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
</ipxact:ports>
</ipxact:model>
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>reg_mmdp_ctrl_1</ipxact:library>
- <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:library>board_reg_ta2_unb2b_mm_io</ipxact:library>
+ <ipxact:name>avs_common_mm_readlatency0</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
<altera:altera_module_parameters>
@@ -850,7 +931,7 @@
<ipxact:parameter parameterId="g_adr_w" type="int">
<ipxact:name>g_adr_w</ipxact:name>
<ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
+ <ipxact:value>8</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="g_dat_w" type="int">
<ipxact:name>g_dat_w</ipxact:name>
@@ -899,7 +980,7 @@
type = "String";
}
}
- element reg_mmdp_ctrl_1
+ element board_reg_ta2_unb2b_mm_io
{
}
}
@@ -908,7 +989,7 @@
<ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
<ipxact:name>hideFromIPCatalog</ipxact:name>
<ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
- <ipxact:value>true</ipxact:value>
+ <ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
<ipxact:name>lockedInterfaceDefinition</ipxact:name>
@@ -987,7 +1068,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1023,6 +1104,14 @@
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
+ <port>
+ <name>avs_mem_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
</ports>
<assignments>
<assignmentValueMap>
@@ -1056,7 +1145,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1159,15 +1248,15 @@
</entry>
<entry>
<key>readLatency</key>
- <value>1</value>
+ <value>0</value>
</entry>
<entry>
<key>readWaitStates</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>readWaitTime</key>
- <value>0</value>
+ <value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
@@ -1285,7 +1374,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1436,6 +1525,38 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>waitrequest</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_waitrequest_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
</interfaces>
</boundaryDefinition></ipxact:value>
</ipxact:parameter>
@@ -1452,11 +1573,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x400' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>10</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -1484,38 +1605,42 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="reg_mmdp_ctrl_1.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="board_reg_ta2_unb2b_mm_io.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="reg_mmdp_ctrl_1.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="board_reg_ta2_unb2b_mm_io.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="reg_mmdp_ctrl_1.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="board_reg_ta2_unb2b_mm_io.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_waitrequest" altera:internal="avs_mem_waitrequest"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="reg_mmdp_ctrl_1.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="board_reg_ta2_unb2b_mm_io.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="reg_mmdp_ctrl_1.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="board_reg_ta2_unb2b_mm_io.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="reg_mmdp_ctrl_1.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="board_reg_ta2_unb2b_mm_io.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="reg_mmdp_ctrl_1.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="board_reg_ta2_unb2b_mm_io.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="reg_mmdp_ctrl_1.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="board_reg_ta2_unb2b_mm_io.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="reg_mmdp_ctrl_1.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="waitrequest" altera:internal="board_reg_ta2_unb2b_mm_io.waitrequest" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_waitrequest_export" altera:internal="coe_waitrequest_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="board_reg_ta2_unb2b_mm_io.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="reg_mmdp_ctrl_1.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="board_reg_ta2_unb2b_mm_io.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/board/reg_mmdp_data_1.ip b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/board/reg_mmdp_data_1.ip
deleted file mode 100644
index e3678f1895..0000000000
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/board/reg_mmdp_data_1.ip
+++ /dev/null
@@ -1,1525 +0,0 @@
-<?xml version="1.0" ?>
-<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
- <ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>reg_mmdp_data_1</ipxact:library>
- <ipxact:name>reg_mmdp_data_1</ipxact:name>
- <ipxact:version>1.0</ipxact:version>
- <ipxact:busInterfaces>
- <ipxact:busInterface>
- <ipxact:name>system</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="clock" version="19.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>clk</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>csi_system_clk</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="clockRate" type="longint">
- <ipxact:name>clockRate</ipxact:name>
- <ipxact:displayName>Clock rate</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="externallyDriven" type="bit">
- <ipxact:name>externallyDriven</ipxact:name>
- <ipxact:displayName>Externally driven</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="ptfSchematicName" type="string">
- <ipxact:name>ptfSchematicName</ipxact:name>
- <ipxact:displayName>PTF schematic name</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>system_reset</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="reset" version="19.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>reset</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>csi_system_reset</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>system</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="synchronousEdges" type="string">
- <ipxact:name>synchronousEdges</ipxact:name>
- <ipxact:displayName>Synchronous edges</ipxact:displayName>
- <ipxact:value>DEASSERT</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>mem</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>address</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_address</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>write</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_write</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>writedata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_writedata</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>read</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_read</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>readdata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_readdata</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="addressAlignment" type="string">
- <ipxact:name>addressAlignment</ipxact:name>
- <ipxact:displayName>Slave addressing</ipxact:displayName>
- <ipxact:value>DYNAMIC</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressGroup" type="int">
- <ipxact:name>addressGroup</ipxact:name>
- <ipxact:displayName>Address group</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressSpan" type="string">
- <ipxact:name>addressSpan</ipxact:name>
- <ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>8</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressUnits" type="string">
- <ipxact:name>addressUnits</ipxact:name>
- <ipxact:displayName>Address units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
- <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
- <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>system</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>Associated reset</ipxact:displayName>
- <ipxact:value>system_reset</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bitsPerSymbol" type="int">
- <ipxact:name>bitsPerSymbol</ipxact:name>
- <ipxact:displayName>Bits per symbol</ipxact:displayName>
- <ipxact:value>8</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
- <ipxact:name>bridgedAddressOffset</ipxact:name>
- <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgesToMaster" type="string">
- <ipxact:name>bridgesToMaster</ipxact:name>
- <ipxact:displayName>Bridges to master</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
- <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
- <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstcountUnits" type="string">
- <ipxact:name>burstcountUnits</ipxact:name>
- <ipxact:displayName>Burstcount units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
- <ipxact:name>constantBurstBehavior</ipxact:name>
- <ipxact:displayName>Constant burst behavior</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="explicitAddressSpan" type="string">
- <ipxact:name>explicitAddressSpan</ipxact:name>
- <ipxact:displayName>Explicit address span</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="holdTime" type="int">
- <ipxact:name>holdTime</ipxact:name>
- <ipxact:displayName>Hold</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="interleaveBursts" type="bit">
- <ipxact:name>interleaveBursts</ipxact:name>
- <ipxact:displayName>Interleave bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isBigEndian" type="bit">
- <ipxact:name>isBigEndian</ipxact:name>
- <ipxact:displayName>Big endian</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isFlash" type="bit">
- <ipxact:name>isFlash</ipxact:name>
- <ipxact:displayName>Flash memory</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isMemoryDevice" type="bit">
- <ipxact:name>isMemoryDevice</ipxact:name>
- <ipxact:displayName>Memory device</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
- <ipxact:name>isNonVolatileStorage</ipxact:name>
- <ipxact:displayName>Non-volatile storage</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="linewrapBursts" type="bit">
- <ipxact:name>linewrapBursts</ipxact:name>
- <ipxact:displayName>Linewrap bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
- <ipxact:name>maximumPendingReadTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
- <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumReadLatency" type="int">
- <ipxact:name>minimumReadLatency</ipxact:name>
- <ipxact:displayName>minimumReadLatency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumResponseLatency" type="int">
- <ipxact:name>minimumResponseLatency</ipxact:name>
- <ipxact:displayName>Minimum response latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
- <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
- <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="printableDevice" type="bit">
- <ipxact:name>printableDevice</ipxact:name>
- <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readLatency" type="int">
- <ipxact:name>readLatency</ipxact:name>
- <ipxact:displayName>Read latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitStates" type="int">
- <ipxact:name>readWaitStates</ipxact:name>
- <ipxact:displayName>Read wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitTime" type="int">
- <ipxact:name>readWaitTime</ipxact:name>
- <ipxact:displayName>Read wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
- <ipxact:name>registerIncomingSignals</ipxact:name>
- <ipxact:displayName>Register incoming signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
- <ipxact:name>registerOutgoingSignals</ipxact:name>
- <ipxact:displayName>Register outgoing signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="setupTime" type="int">
- <ipxact:name>setupTime</ipxact:name>
- <ipxact:displayName>Setup</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="timingUnits" type="string">
- <ipxact:name>timingUnits</ipxact:name>
- <ipxact:displayName>Timing units</ipxact:displayName>
- <ipxact:value>Cycles</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="transparentBridge" type="bit">
- <ipxact:name>transparentBridge</ipxact:name>
- <ipxact:displayName>Transparent bridge</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="waitrequestAllowance" type="int">
- <ipxact:name>waitrequestAllowance</ipxact:name>
- <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
- <ipxact:name>wellBehavedWaitrequest</ipxact:name>
- <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeLatency" type="int">
- <ipxact:name>writeLatency</ipxact:name>
- <ipxact:displayName>Write latency</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitStates" type="int">
- <ipxact:name>writeWaitStates</ipxact:name>
- <ipxact:displayName>Write wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitTime" type="int">
- <ipxact:name>writeWaitTime</ipxact:name>
- <ipxact:displayName>Write wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- <ipxact:vendorExtensions>
- <altera:altera_assignments>
- <ipxact:parameters>
- <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
- <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
- <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_assignments>
- </ipxact:vendorExtensions>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>reset</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_reset_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>clk</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_clk_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>address</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_address_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>write</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_write_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>writedata</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_writedata_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>read</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_read_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>readdata</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_readdata_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- </ipxact:busInterfaces>
- <ipxact:model>
- <ipxact:views>
- <ipxact:view>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
- <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
- </ipxact:view>
- </ipxact:views>
- <ipxact:instantiations>
- <ipxact:componentInstantiation>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
- <ipxact:fileSetRef>
- <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
- </ipxact:fileSetRef>
- <ipxact:parameters></ipxact:parameters>
- </ipxact:componentInstantiation>
- </ipxact:instantiations>
- <ipxact:ports>
- <ipxact:port>
- <ipxact:name>csi_system_clk</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>csi_system_reset</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_address</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_write</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_writedata</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_read</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_readdata</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_reset_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_clk_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_address_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_write_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_writedata_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_read_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_readdata_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- </ipxact:ports>
- </ipxact:model>
- <ipxact:vendorExtensions>
- <altera:entity_info>
- <ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>reg_mmdp_data_1</ipxact:library>
- <ipxact:name>avs_common_mm</ipxact:name>
- <ipxact:version>1.0</ipxact:version>
- </altera:entity_info>
- <altera:altera_module_parameters>
- <ipxact:parameters>
- <ipxact:parameter parameterId="g_adr_w" type="int">
- <ipxact:name>g_adr_w</ipxact:name>
- <ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="g_dat_w" type="int">
- <ipxact:name>g_dat_w</ipxact:name>
- <ipxact:displayName>g_dat_w</ipxact:displayName>
- <ipxact:value>32</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
- <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
- <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
- <ipxact:value>100000000</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_module_parameters>
- <altera:altera_system_parameters>
- <ipxact:parameters>
- <ipxact:parameter parameterId="device" type="string">
- <ipxact:name>device</ipxact:name>
- <ipxact:displayName>Device</ipxact:displayName>
- <ipxact:value>10AX115U2F45E1SG</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceFamily" type="string">
- <ipxact:name>deviceFamily</ipxact:name>
- <ipxact:displayName>Device family</ipxact:displayName>
- <ipxact:value>Arria 10</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
- <ipxact:name>deviceSpeedGrade</ipxact:name>
- <ipxact:displayName>Device Speed Grade</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="generationId" type="int">
- <ipxact:name>generationId</ipxact:name>
- <ipxact:displayName>Generation Id</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bonusData" type="string">
- <ipxact:name>bonusData</ipxact:name>
- <ipxact:displayName>bonusData</ipxact:displayName>
- <ipxact:value>bonusData
-{
- element $system
- {
- datum _originalDeviceFamily
- {
- value = "Arria 10";
- type = "String";
- }
- }
- element reg_mmdp_data_1
- {
- }
-}
-</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
- <ipxact:name>hideFromIPCatalog</ipxact:name>
- <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
- <ipxact:value>true</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
- <ipxact:name>lockedInterfaceDefinition</ipxact:name>
- <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
- <ipxact:value><boundaryDefinition>
- <interfaces>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>8</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="systemInfos" type="string">
- <ipxact:name>systemInfos</ipxact:name>
- <ipxact:displayName>systemInfos</ipxact:displayName>
- <ipxact:value><systemInfosDefinition>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>3</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
-</systemInfosDefinition></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_system_parameters>
- <altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="reg_mmdp_data_1.address" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="reg_mmdp_data_1.clk" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="reg_mmdp_data_1.mem" altera:type="avalon" altera:dir="end">
- <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="reg_mmdp_data_1.read" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="reg_mmdp_data_1.readdata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="reg_mmdp_data_1.reset" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="reg_mmdp_data_1.system" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="reg_mmdp_data_1.system_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="reg_mmdp_data_1.write" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="reg_mmdp_data_1.writedata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
- </altera:interface_mapping>
- </altera:altera_interface_boundary>
- <altera:altera_has_warnings>false</altera:altera_has_warnings>
- <altera:altera_has_errors>false</altera:altera_has_errors>
- </ipxact:vendorExtensions>
-</ipxact:component>
\ No newline at end of file
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/freeze_wrapper.v b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/freeze_wrapper.v
index 23f1c90760..e0f4da2ea1 100755
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/freeze_wrapper.v
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/freeze_wrapper.v
@@ -42,9 +42,12 @@ module freeze_wrapper(
input wire board_kernel_stream_src_ADC_valid,
output wire board_kernel_stream_src_ADC_ready,
- input wire [31:0] board_kernel_stream_src_mm_io_data,
+ input wire [71:0] board_kernel_stream_src_mm_io_data,
input wire board_kernel_stream_src_mm_io_valid,
output wire board_kernel_stream_src_mm_io_ready,
+ output wire [31:0] board_kernel_stream_snk_mm_io_data,
+ output wire board_kernel_stream_snk_mm_io_valid,
+ input wire board_kernel_stream_snk_mm_io_ready,
input wire [39:0] board_kernel_stream_src_1GbE_data,
input wire board_kernel_stream_src_1GbE_valid,
@@ -255,6 +258,9 @@ pr_region pr_region_inst
.kernel_stream_src_ADC_ready(board_kernel_stream_src_ADC_ready),
.kernel_stream_src_ADC_valid(board_kernel_stream_src_ADC_valid),
+ .kernel_stream_snk_mm_io_data(board_kernel_stream_snk_mm_io_data),
+ .kernel_stream_snk_mm_io_ready(board_kernel_stream_snk_mm_io_ready),
+ .kernel_stream_snk_mm_io_valid(board_kernel_stream_snk_mm_io_valid),
.kernel_stream_src_mm_io_data(board_kernel_stream_src_mm_io_data),
.kernel_stream_src_mm_io_ready(board_kernel_stream_src_mm_io_ready),
.kernel_stream_src_mm_io_valid(board_kernel_stream_src_mm_io_valid),
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/pr_region.v b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/pr_region.v
index 9328a1f416..a24b63b57f 100755
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/pr_region.v
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/ip/pr_region.v
@@ -57,9 +57,12 @@ module pr_region (
input wire kernel_stream_src_ADC_valid,
output wire kernel_stream_src_ADC_ready,
- input wire [31:0] kernel_stream_src_mm_io_data,
+ input wire [71:0] kernel_stream_src_mm_io_data,
input wire kernel_stream_src_mm_io_valid,
output wire kernel_stream_src_mm_io_ready,
+ output wire [31:0] kernel_stream_snk_mm_io_data,
+ output wire kernel_stream_snk_mm_io_valid,
+ input wire kernel_stream_snk_mm_io_ready,
input wire [39:0] kernel_stream_src_1GbE_data,
input wire kernel_stream_src_1GbE_valid,
@@ -251,6 +254,9 @@ kernel_system kernel_system_inst
.kernel_input_mm_ready(kernel_stream_src_mm_io_ready),
.kernel_input_mm_valid(kernel_stream_src_mm_io_valid),
+ .kernel_output_mm_data(kernel_stream_snk_mm_io_data),
+ .kernel_output_mm_ready(kernel_stream_snk_mm_io_ready),
+ .kernel_output_mm_valid(kernel_stream_snk_mm_io_valid),
.kernel_mem0_address(pipelined_kernel_mem0_s0_address),
.kernel_mem0_read(pipelined_kernel_mem0_s0_read),
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/opencl_bsp_ip.qsf b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/opencl_bsp_ip.qsf
index 170b847576..1b449e26db 100755
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/opencl_bsp_ip.qsf
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/opencl_bsp_ip.qsf
@@ -68,3 +68,4 @@ set_global_assignment -name IP_FILE ip/board/board_jtag_uart_0.ip
set_global_assignment -name IP_FILE ip/board/board_kernel_clk.ip
set_global_assignment -name IP_FILE ip/board/board_onchip_memory.ip
set_global_assignment -name IP_FILE ip/board/board_reg_ta2_unb2b_jesd204b.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_ta2_unb2b_mm_io.ip
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
index 3c62c1dbe2..e92596380c 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
@@ -26,11 +26,12 @@
-- include:
-- . 40 GbE
-- . 10 GbE
+-- . 1 GbE
-- . ADC
--- . 1 GbE M&C
+-- . M&C
-- --------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, dp_lib, tech_ddr_lib, ta2_unb2b_40GbE_lib, ta2_unb2b_10gbe_lib, ta2_unb2b_1gbe_mc_lib, ta2_unb2b_mm_io_lib, ta2_unb2b_jesd204b_lib ;
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, dp_lib, tech_ddr_lib, ta2_unb2b_40GbE_lib, ta2_unb2b_10gbe_lib, ta2_unb2b_1gbe_lib, ta2_unb2b_mm_io_lib, ta2_unb2b_jesd204b_lib ;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -245,14 +246,10 @@ ARCHITECTURE str OF top IS
SIGNAL reg_ta2_unb2b_jesd204b_mosi : t_mem_mosi;
SIGNAL reg_ta2_unb2b_jesd204b_miso : t_mem_miso;
- -- MM IO Reg
- SIGNAL ta2_unb2b_mm_io_ctrl_mosi : t_mem_mosi;
- SIGNAL ta2_unb2b_mm_io_ctrl_miso : t_mem_miso;
+ -- MM IO
+ SIGNAL reg_ta2_unb2b_mm_io_mosi : t_mem_mosi;
+ SIGNAL reg_ta2_unb2b_mm_io_miso : t_mem_miso;
- -- MM IO Data
- SIGNAL ta2_unb2b_mm_io_data_mosi : t_mem_mosi;
- SIGNAL ta2_unb2b_mm_io_data_miso : t_mem_miso;
-
-- QSFP
SIGNAL i_QSFP_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
@@ -342,11 +339,12 @@ ARCHITECTURE str OF top IS
SIGNAL ta2_unb2b_ADC_src_out_arr : t_dp_sosi_arr(c_nof_ADC-1 DOWNTO 0);
SIGNAL ta2_unb2b_ADC_src_in_arr : t_dp_siso_arr(c_nof_ADC-1 DOWNTO 0);
+ SIGNAL ta2_unb2b_mm_io_snk_in : t_dp_sosi;
+ SIGNAL ta2_unb2b_mm_io_snk_out : t_dp_siso;
SIGNAL ta2_unb2b_mm_io_src_out : t_dp_sosi;
SIGNAL ta2_unb2b_mm_io_src_in : t_dp_siso;
-
CONSTANT c_ones : STD_LOGIC_VECTOR(511 DOWNTO 0) := (OTHERS => '1');
BEGIN
@@ -501,7 +499,7 @@ BEGIN
-----------------------------
-- 1GbE Monitoring & Control
-----------------------------
- u_ta2_unb2b_1GbE_mc : ENTITY ta2_unb2b_1GbE_mc_lib.ta2_unb2b_1GbE_mc
+ u_ta2_unb2b_1GbE : ENTITY ta2_unb2b_1GbE_lib.ta2_unb2b_1GbE
PORT MAP (
st_clk => st_clk,
st_rst => st_rst,
@@ -521,10 +519,13 @@ BEGIN
);
- -----------------------------
+ --------------------------------------
-- Monitoring & Control UNB protocol
- -----------------------------
+ --------------------------------------
u_ta2_unb2b_mm_io : ENTITY ta2_unb2b_mm_io_lib.ta2_unb2b_mm_io
+ GENERIC MAP(
+ g_use_opencl => TRUE
+ )
PORT MAP (
mm_clk => mm_clk,
mm_rst => mm_rst,
@@ -532,20 +533,17 @@ BEGIN
kernel_clk => board_kernel_clk_clk,
kernel_reset => i_kernel_rst,
- ctrl_mosi => ta2_unb2b_mm_io_ctrl_mosi,
- ctrl_miso => ta2_unb2b_mm_io_ctrl_miso,
- data_mosi => ta2_unb2b_mm_io_data_mosi,
- data_miso => ta2_unb2b_mm_io_data_miso,
+ mm_mosi => reg_ta2_unb2b_mm_io_mosi,
+ mm_miso => reg_ta2_unb2b_mm_io_miso,
+ snk_in => ta2_unb2b_mm_io_snk_in,
+ snk_out => ta2_unb2b_mm_io_snk_out,
src_out => ta2_unb2b_mm_io_src_out,
src_in => ta2_unb2b_mm_io_src_in
);
-
-
-
----------
-- ADC
----------
@@ -689,9 +687,12 @@ BEGIN
board_kernel_stream_snk_1GbE_valid => ta2_unb2b_1GbE_snk_in.valid,
board_kernel_stream_snk_1GbE_ready => ta2_unb2b_1GbE_snk_out.ready,
- board_kernel_stream_src_mm_io_data => ta2_unb2b_mm_io_src_out.data(31 DOWNTO 0),
+ board_kernel_stream_src_mm_io_data => ta2_unb2b_mm_io_src_out.data(71 DOWNTO 0),
board_kernel_stream_src_mm_io_valid => ta2_unb2b_mm_io_src_out.valid,
board_kernel_stream_src_mm_io_ready => ta2_unb2b_mm_io_src_in.ready,
+ board_kernel_stream_snk_mm_io_data => ta2_unb2b_mm_io_snk_in.data(31 DOWNTO 0),
+ board_kernel_stream_snk_mm_io_valid => ta2_unb2b_mm_io_snk_in.valid,
+ board_kernel_stream_snk_mm_io_ready => ta2_unb2b_mm_io_snk_out.ready,
board_kernel_stream_src_ADC_data => ta2_unb2b_ADC_src_out_arr(0).data(15 DOWNTO 0),
board_kernel_stream_src_ADC_valid => ta2_unb2b_ADC_src_out_arr(0).valid,
@@ -1003,19 +1004,12 @@ BEGIN
kernel_register_mem_writedata => board_kernel_register_mem_writedata,
kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
- reg_mmdp_data_1_address_export => ta2_unb2b_mm_io_data_mosi.address(0 DOWNTO 0),
- reg_mmdp_data_1_write_export => ta2_unb2b_mm_io_data_mosi.wr,
- reg_mmdp_data_1_writedata_export => ta2_unb2b_mm_io_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_mmdp_data_1_read_export => ta2_unb2b_mm_io_data_mosi.rd,
- reg_mmdp_data_1_readdata_export => ta2_unb2b_mm_io_data_miso.rddata(c_word_w-1 DOWNTO 0),
-
- reg_mmdp_ctrl_1_address_export => ta2_unb2b_mm_io_ctrl_mosi.address(0 DOWNTO 0),
- reg_mmdp_ctrl_1_read_export => ta2_unb2b_mm_io_ctrl_mosi.rd,
- reg_mmdp_ctrl_1_readdata_export => ta2_unb2b_mm_io_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_mmdp_ctrl_1_write_export => ta2_unb2b_mm_io_ctrl_mosi.wr,
- reg_mmdp_ctrl_1_writedata_export => ta2_unb2b_mm_io_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
-
+ reg_ta2_unb2b_mm_io_address_export => reg_ta2_unb2b_mm_io_mosi.address(7 DOWNTO 0),
+ reg_ta2_unb2b_mm_io_read_export => reg_ta2_unb2b_mm_io_mosi.rd,
+ reg_ta2_unb2b_mm_io_readdata_export => reg_ta2_unb2b_mm_io_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_ta2_unb2b_mm_io_write_export => reg_ta2_unb2b_mm_io_mosi.wr,
+ reg_ta2_unb2b_mm_io_writedata_export => reg_ta2_unb2b_mm_io_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_ta2_unb2b_mm_io_waitrequest_export => reg_ta2_unb2b_mm_io_miso.waitrequest,
kernel_mem0_waitrequest => board_kernel_mem0_waitrequest,
kernel_mem0_readdata => board_kernel_mem0_readdata,
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
index 2196157cf8..382c0043c8 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
@@ -29,7 +29,6 @@ USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE top_components_pkg IS
-
component board is
port (
avs_eth_0_clk_export : out std_logic; -- export
@@ -85,6 +84,24 @@ PACKAGE top_components_pkg IS
kernel_cra_debugaccess : out std_logic; -- debugaccess
kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
kernel_interface_sw_reset_in_reset : in std_logic := 'X'; -- reset
+ ddr4a_pll_ref_clk : in std_logic := 'X'; -- clk
+ ddr4a_oct_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
+ ddr4a_mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
+ ddr4a_mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
+ ddr4a_mem_a : out std_logic_vector(16 downto 0); -- mem_a
+ ddr4a_mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
+ ddr4a_mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
+ ddr4a_mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
+ ddr4a_mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
+ ddr4a_mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
+ ddr4a_mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
+ ddr4a_mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
+ ddr4a_mem_par : out std_logic_vector(0 downto 0); -- mem_par
+ ddr4a_mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
+ ddr4a_mem_dqs : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs
+ ddr4a_mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs_n
+ ddr4a_mem_dq : inout std_logic_vector(63 downto 0) := (others => 'X'); -- mem_dq
+ ddr4a_mem_dbi_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dbi_n
pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
pio_pps_clk_export : out std_logic; -- export
pio_pps_read_export : out std_logic; -- export
@@ -164,6 +181,14 @@ PACKAGE top_components_pkg IS
reg_ta2_unb2b_jesd204b_waitrequest_export : in std_logic := 'X'; -- export
reg_ta2_unb2b_jesd204b_write_export : out std_logic; -- export
reg_ta2_unb2b_jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ta2_unb2b_mm_io_reset_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_clk_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_ta2_unb2b_mm_io_write_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ta2_unb2b_mm_io_read_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ta2_unb2b_mm_io_waitrequest_export : in std_logic := 'X'; -- export
reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
reg_unb_pmbus_clk_export : out std_logic; -- export
reg_unb_pmbus_read_export : out std_logic; -- export
@@ -191,197 +216,10 @@ PACKAGE top_components_pkg IS
rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
rom_system_info_reset_export : out std_logic; -- export
rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_1_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_1_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_1_read_export : out std_logic; -- export
- reg_mmdp_ctrl_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_1_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_1_write_export : out std_logic; -- export
- reg_mmdp_ctrl_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_1_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_1_clk_export : out std_logic; -- export
- reg_mmdp_data_1_read_export : out std_logic; -- export
- reg_mmdp_data_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_1_reset_export : out std_logic; -- export
- reg_mmdp_data_1_write_export : out std_logic; -- export
- reg_mmdp_data_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- ddr4a_pll_ref_clk : in std_logic := 'X'; -- clk
- ddr4a_oct_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- ddr4a_mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- ddr4a_mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- ddr4a_mem_a : out std_logic_vector(16 downto 0); -- mem_a
- ddr4a_mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- ddr4a_mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- ddr4a_mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- ddr4a_mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- ddr4a_mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- ddr4a_mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- ddr4a_mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- ddr4a_mem_par : out std_logic_vector(0 downto 0); -- mem_par
- ddr4a_mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
- ddr4a_mem_dqs : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs
- ddr4a_mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs_n
- ddr4a_mem_dq : inout std_logic_vector(63 downto 0) := (others => 'X'); -- mem_dq
- ddr4a_mem_dbi_n : inout std_logic_vector(7 downto 0) := (others => 'X') -- mem_dbi_n
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component board;
--- component board is
--- port (
--- avs_eth_0_clk_export : out std_logic; -- export
--- avs_eth_0_irq_export : in std_logic := 'X'; -- export
--- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
--- avs_eth_0_ram_read_export : out std_logic; -- export
--- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
--- avs_eth_0_ram_write_export : out std_logic; -- export
--- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
--- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
--- avs_eth_0_reg_read_export : out std_logic; -- export
--- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
--- avs_eth_0_reg_write_export : out std_logic; -- export
--- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
--- avs_eth_0_reset_export : out std_logic; -- export
--- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
--- avs_eth_0_tse_read_export : out std_logic; -- export
--- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
--- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
--- avs_eth_0_tse_write_export : out std_logic; -- export
--- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
--- clk_clk : in std_logic := 'X'; -- clk
--- kernel_clk_clk : out std_logic; -- clk
--- kernel_clk2x_clk : out std_logic; -- clk
--- kernel_cra_waitrequest : in std_logic := 'X'; -- waitrequest
--- kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
--- kernel_cra_readdatavalid : in std_logic := 'X'; -- readdatavalid
--- kernel_cra_burstcount : out std_logic_vector(0 downto 0); -- burstcount
--- kernel_cra_writedata : out std_logic_vector(63 downto 0); -- writedata
--- kernel_cra_address : out std_logic_vector(29 downto 0); -- address
--- kernel_cra_write : out std_logic; -- write
--- kernel_cra_read : out std_logic; -- read
--- kernel_cra_byteenable : out std_logic_vector(7 downto 0); -- byteenable
--- kernel_cra_debugaccess : out std_logic; -- debugaccess
--- kernel_interface_sw_reset_in_reset : in std_logic := 'X'; -- reset
--- kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
--- kernel_register_mem_address : in std_logic_vector(6 downto 0) := (others => 'X'); -- address
--- kernel_register_mem_clken : in std_logic := 'X'; -- clken
--- kernel_register_mem_chipselect : in std_logic := 'X'; -- chipselect
--- kernel_register_mem_write : in std_logic := 'X'; -- write
--- kernel_register_mem_readdata : out std_logic_vector(255 downto 0); -- readdata
--- kernel_register_mem_writedata : in std_logic_vector(255 downto 0) := (others => 'X'); -- writedata
--- kernel_register_mem_byteenable : in std_logic_vector(31 downto 0) := (others => 'X'); -- byteenable
--- kernel_reset_reset_n : out std_logic; -- reset_n
--- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
--- pio_pps_clk_export : out std_logic; -- export
--- pio_pps_read_export : out std_logic; -- export
--- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
--- pio_pps_reset_export : out std_logic; -- export
--- pio_pps_write_export : out std_logic; -- export
--- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
--- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
--- pio_system_info_clk_export : out std_logic; -- export
--- pio_system_info_read_export : out std_logic; -- export
--- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
--- pio_system_info_reset_export : out std_logic; -- export
--- pio_system_info_write_export : out std_logic; -- export
--- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
--- pio_wdi_external_connection_export : out std_logic; -- export
--- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
--- reg_dpmm_ctrl_clk_export : out std_logic; -- export
--- reg_dpmm_ctrl_read_export : out std_logic; -- export
--- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
--- reg_dpmm_ctrl_reset_export : out std_logic; -- export
--- reg_dpmm_ctrl_write_export : out std_logic; -- export
--- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
--- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
--- reg_dpmm_data_clk_export : out std_logic; -- export
--- reg_dpmm_data_read_export : out std_logic; -- export
--- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
--- reg_dpmm_data_reset_export : out std_logic; -- export
--- reg_dpmm_data_write_export : out std_logic; -- export
--- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
--- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
--- reg_epcs_clk_export : out std_logic; -- export
--- reg_epcs_read_export : out std_logic; -- export
--- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
--- reg_epcs_reset_export : out std_logic; -- export
--- reg_epcs_write_export : out std_logic; -- export
--- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
--- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
--- reg_fpga_temp_sens_clk_export : out std_logic; -- export
--- reg_fpga_temp_sens_read_export : out std_logic; -- export
--- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
--- reg_fpga_temp_sens_reset_export : out std_logic; -- export
--- reg_fpga_temp_sens_write_export : out std_logic; -- export
--- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
--- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
--- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
--- reg_fpga_voltage_sens_read_export : out std_logic; -- export
--- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
--- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
--- reg_fpga_voltage_sens_write_export : out std_logic; -- export
--- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
--- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
--- reg_mmdp_ctrl_clk_export : out std_logic; -- export
--- reg_mmdp_ctrl_read_export : out std_logic; -- export
--- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
--- reg_mmdp_ctrl_reset_export : out std_logic; -- export
--- reg_mmdp_ctrl_write_export : out std_logic; -- export
--- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
--- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
--- reg_mmdp_data_clk_export : out std_logic; -- export
--- reg_mmdp_data_read_export : out std_logic; -- export
--- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
--- reg_mmdp_data_reset_export : out std_logic; -- export
--- reg_mmdp_data_write_export : out std_logic; -- export
--- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
--- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
--- reg_remu_clk_export : out std_logic; -- export
--- reg_remu_read_export : out std_logic; -- export
--- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
--- reg_remu_reset_export : out std_logic; -- export
--- reg_remu_write_export : out std_logic; -- export
--- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
--- reg_ta2_unb2b_jesd204b_address_export : out std_logic_vector(7 downto 0); -- export
--- reg_ta2_unb2b_jesd204b_clk_export : out std_logic; -- export
--- reg_ta2_unb2b_jesd204b_read_export : out std_logic; -- export
--- reg_ta2_unb2b_jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
--- reg_ta2_unb2b_jesd204b_reset_export : out std_logic; -- export
--- reg_ta2_unb2b_jesd204b_waitrequest_export : in std_logic := 'X'; -- export
--- reg_ta2_unb2b_jesd204b_write_export : out std_logic; -- export
--- reg_ta2_unb2b_jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
--- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
--- reg_unb_pmbus_clk_export : out std_logic; -- export
--- reg_unb_pmbus_read_export : out std_logic; -- export
--- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
--- reg_unb_pmbus_reset_export : out std_logic; -- export
--- reg_unb_pmbus_write_export : out std_logic; -- export
--- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
--- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
--- reg_unb_sens_clk_export : out std_logic; -- export
--- reg_unb_sens_read_export : out std_logic; -- export
--- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
--- reg_unb_sens_reset_export : out std_logic; -- export
--- reg_unb_sens_write_export : out std_logic; -- export
--- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
--- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
--- reg_wdi_clk_export : out std_logic; -- export
--- reg_wdi_read_export : out std_logic; -- export
--- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
--- reg_wdi_reset_export : out std_logic; -- export
--- reg_wdi_write_export : out std_logic; -- export
--- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
--- reset_reset_n : in std_logic := 'X'; -- reset_n
--- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
--- rom_system_info_clk_export : out std_logic; -- export
--- rom_system_info_read_export : out std_logic; -- export
--- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
--- rom_system_info_reset_export : out std_logic; -- export
--- rom_system_info_write_export : out std_logic; -- export
--- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
--- );
--- end component board;
-
component freeze_wrapper is
port (
board_kernel_clk_clk : in std_logic; --input
@@ -452,11 +290,14 @@ PACKAGE top_components_pkg IS
board_kernel_stream_snk_1GbE_data : out std_logic_vector(39 downto 0);
board_kernel_stream_snk_1GbE_valid : out std_logic;
board_kernel_stream_snk_1GbE_ready : in std_logic;
-
- board_kernel_stream_src_mm_io_data : in std_logic_vector(31 downto 0);
+
+ board_kernel_stream_src_mm_io_data : in std_logic_vector(71 downto 0);
board_kernel_stream_src_mm_io_valid : in std_logic;
- board_kernel_stream_src_mm_io_ready : out std_logic;
-
+ board_kernel_stream_src_mm_io_ready : out std_logic;
+ board_kernel_stream_snk_mm_io_data : out std_logic_vector(31 downto 0);
+ board_kernel_stream_snk_mm_io_valid : out std_logic;
+ board_kernel_stream_snk_mm_io_ready : out std_logic;
+
board_kernel_stream_src_ADC_data : in std_logic_vector(15 downto 0);
board_kernel_stream_src_ADC_valid : in std_logic;
board_kernel_stream_src_ADC_ready : out std_logic
diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/hdllib.cfg b/applications/ta2/ip/ta2_unb2b_mm_io/hdllib.cfg
index 734d741fb8..274d179d59 100644
--- a/applications/ta2/ip/ta2_unb2b_mm_io/hdllib.cfg
+++ b/applications/ta2/ip/ta2_unb2b_mm_io/hdllib.cfg
@@ -7,6 +7,7 @@ hdl_lib_technology = ip_arria10_e1sg
synth_files =
ta2_unb2b_mm_io.vhd
test_bench_files =
+ tb_ta2_unb2b_mm_io.vhd
regression_test_vhdl =
diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd b/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
index f722afbfad..e8dd9ac102 100644
--- a/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
+++ b/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
@@ -1,48 +1,59 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2019
+-- --------------------------------------------------------------------------
+-- Copyright 2020
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--------------------------------------------------------------------------------
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+-- --------------------------------------------------------------------------
-- Author:
-- . Reinier van der Walle
-- Purpose:
--- . Provide 1G ethernet I/O interface (BSP) for OpenCL kernel on Arria10
+-- . Provide Monitor and control I/O interface for OpenCL kernel on Arria10
-- Description:
--- . This core consists of glue logic between the OpenCL kernel IO channel and dp sosi/siso interface to ctrl_unb2b_board:
+-- . This core consists of two dual clock fifos and glue logic to be used between
+-- the OpenCL kernel IO channel and dp MM interface to board qsys.
-- . Details:
-- . This core was developed for use on the Uniboard2b.
--- .
--- . The data field of the ST-avalon interface is also used to provide
--- . SOP, EOP and empty meta-data. The implementation of this is shown below.
--- +-----------+---------+--------------------------------------------------------+
--- | Bit range | Name | Description |
--- +-----------+---------+--------------------------------------------------------+
--- | [0:31] | payload | Packet payload |
--- +-----------+---------+--------------------------------------------------------+
--- | 32 | sop | Start of packet signal |
--- +-----------+---------+--------------------------------------------------------+
--- | 33 | eop | End of packet signal |
--- +-----------+---------+--------------------------------------------------------+
--- | [34:37] | - | reserved bits |
--- +-----------+---------+--------------------------------------------------------+
--- | [38:39] | empty | On EOP, this field indicates how many bytes are unused |
--- +-----------+---------+--------------------------------------------------------+
+-- . The implementation of the MM data mapped onto the IO channel is shown below.
+--
+-- MOSI -> IO channel (72 bits)
+-- +-----------+---------+----------------------------------+
+-- | Bit range | Name | Description |
+-- +-----------+---------+----------------------------------+
+-- | [0:31] | wrdata | Write data |
+-- +-----------+---------+----------------------------------+
+-- | [32:63] | address | Address |
+-- +-----------+---------+----------------------------------+
+-- | [64] | rd/wr | '1' = wr, '0' = rd |
+-- +-----------+---------+----------------------------------+
+-- | [65:71] | - | reserved bits |
+-- +-----------+---------+----------------------------------+
+--
+-- IO channel (32) bits -> MISO
+-- +-----------+---------+----------------------------------+
+-- | Bit range | Name | Description |
+-- +-----------+---------+----------------------------------+
+-- | [0:31] | rddata | Read data |
+-- +-----------+---------+----------------------------------+
+--
+-- . The generic: g_use_opencl can be used for testing perposes. When g_use_opencl
+-- is FALSE, the core wil use an internal rtl model that emulates an OpenCL kernel.
+-- This model has 4 register on addresses 0:3. On addr 1, the rddata = wrdata +1 and
+-- on addr 2, the rddata = wrdata +2, to make them distinguishable. The others
+-- registers are rddata = wrdata.
+-- --------------------------------------------------------------------------
LIBRARY IEEE, common_lib, dp_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
@@ -51,65 +62,93 @@ USE dp_lib.dp_stream_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE common_lib.common_interface_layers_pkg.ALL;
-ENTITY ta2_unb2b_mm_io IS
+ENTITY ta2_unb2b_mm_io IS
+ GENERIC (
+ g_use_opencl : BOOLEAN := TRUE
+ );
PORT (
- mm_clk : IN STD_LOGIC;
- mm_rst : IN STD_LOGIC;
-
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
- kernel_clk : IN STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
- kernel_reset : IN STD_LOGIC;
+ kernel_clk : IN STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
+ kernel_reset : IN STD_LOGIC;
-- MM registers
- ctrl_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ctrl_miso : OUT t_mem_miso;
+ mm_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ mm_miso : OUT t_mem_miso;
- data_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- data_miso : OUT t_mem_miso := c_mem_miso_rst;
-
- src_out : OUT t_dp_sosi;
- src_in : IN t_dp_siso
+ -- DP
+ snk_in : IN t_dp_sosi;
+ snk_out : OUT t_dp_siso;
+
+ src_out : OUT t_dp_sosi;
+ src_in : IN t_dp_siso
);
END ta2_unb2b_mm_io;
ARCHITECTURE str OF ta2_unb2b_mm_io IS
- CONSTANT c_fifo_size : NATURAL := 512;
+ CONSTANT c_fifo_size : NATURAL := 8;
+ CONSTANT c_wr_data_w : NATURAL := 72;
+ CONSTANT c_rd_data_w : NATURAL := 32;
SIGNAL wr_usedw : STD_LOGIC_VECTOR(ceil_log2(c_fifo_size)-1 DOWNTO 0);
- SIGNAL wr_sosi : t_dp_sosi;
-BEGIN
+ SIGNAL rd_usedw : STD_LOGIC_VECTOR(ceil_log2(c_fifo_size)-1 DOWNTO 0);
+ SIGNAL wr_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL wr_siso : t_dp_siso := c_dp_siso_rdy;
+ SIGNAL rd_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL rd_siso : t_dp_siso := c_dp_siso_rdy;
+ SIGNAL busy : STD_LOGIC := '0';
+ SIGNAL done : STD_LOGIC := '0';
-
- -----------------------------------------------------------------------------
- -- dp_fifo from mm
- -----------------------------------------------------------------------------
+ SIGNAL is_reading : BOOLEAN := FALSE;
+ SIGNAL cnt : NATURAL := 0;
+ SIGNAL c_cnt_max : NATURAL := 3;
+
+ SIGNAL in_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL in_siso : t_dp_siso := c_dp_siso_rst;
+ SIGNAL out_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL out_siso : t_dp_siso := c_dp_siso_rst;
+
+ SIGNAL reg_a : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL reg_b : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL reg_c : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL reg_d : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
- u_mms_dp_fifo_from_mm : ENTITY dp_lib.mms_dp_fifo_from_mm
- GENERIC MAP (
- g_wr_fifo_depth => c_fifo_size
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- wr_sosi => wr_sosi,
- ctrl_mosi => ctrl_mosi,
- ctrl_miso => ctrl_miso,
- data_mosi => data_mosi,
- data_miso => data_miso,
- wr_usedw => wr_usedw
- );
+BEGIN
+ -- Connect MM <-> DP
+ wr_sosi.data(31 DOWNTO 0) <= mm_mosi.wrdata(31 DOWNTO 0);
+ mm_miso.rddata(31 DOWNTO 0) <= rd_sosi.data(31 DOWNTO 0);
+
+ wr_sosi.data(63 DOWNTO 32) <= mm_mosi.address(31 DOWNTO 0);
+ wr_sosi.data(64) <= mm_mosi.wr;
+ done <= wr_siso.ready WHEN mm_mosi.wr = '1' ELSE rd_sosi.valid;
+ mm_miso.waitrequest <= NOT done;
+ wr_sosi.valid <= (mm_mosi.wr OR mm_mosi.rd) WHEN busy = '0' ELSE '0';
+
+ p_valid : PROCESS(mm_clk)
+ BEGIN
+ IF (rising_edge(mm_clk)) THEN
+ IF (mm_mosi.wr OR mm_mosi.rd) = '1' THEN
+ busy <= '1';
+ END IF;
+ IF done = '1' THEN
+ busy <= '0';
+ END IF;
+ END IF;
+ END PROCESS;
-----------------------------------------------------------------------------
- -- dual clock FIFO
+ -- dual clock FIFOs
-----------------------------------------------------------------------------
-
- u_dp_fifo_dc : ENTITY dp_lib.dp_fifo_dc
+ u_dp_fifo_dc_wr : ENTITY dp_lib.dp_fifo_dc
GENERIC MAP (
g_technology => c_tech_arria10_e1sg,
- g_data_w => c_word_w,
- g_fifo_size => c_fifo_size
+ g_data_w => c_wr_data_w,
+ g_use_ctrl => FALSE, -- No sop & eop
+ g_fifo_size => c_fifo_size,
+ g_fifo_rl => 0
)
PORT MAP (
wr_rst => mm_rst,
@@ -120,11 +159,99 @@ BEGIN
wr_usedw => wr_usedw,
snk_in => wr_sosi,
+ snk_out => wr_siso,
+
+ src_in => out_siso,
+ src_out => out_sosi
+ );
+
+
+ u_dp_fifo_dc_rd : ENTITY dp_lib.dp_fifo_dc
+ GENERIC MAP (
+ g_technology => c_tech_arria10_e1sg,
+ g_data_w => c_rd_data_w,
+ g_use_ctrl => FALSE, -- No sop & eop
+ g_fifo_size => c_fifo_size,
+ g_fifo_rl => 0
+ )
+ PORT MAP (
+ wr_rst => kernel_reset,
+ wr_clk => kernel_clk,
+ rd_rst => mm_rst,
+ rd_clk => mm_clk,
+
+ wr_usedw => rd_usedw,
+
+ snk_in => in_sosi,
+ snk_out => in_siso,
- src_in => src_in,
- src_out => src_out
+ src_in => rd_siso,
+ src_out => rd_sosi
);
+gen_no_opencl : IF NOT g_use_opencl GENERATE
+ -- simulate an OpenCL kernel response (rl=0)
+ p_is_reading : PROCESS(kernel_clk)
+ BEGIN
+ IF rising_edge(kernel_clk) THEN
+ IF cnt >= c_cnt_max THEN
+ cnt <= 0;
+ is_reading <= FALSE;
+ ELSE
+ cnt <= cnt+1;
+ END IF;
+ IF in_sosi.valid = '1' THEN
+ is_reading <= TRUE;
+ cnt <= 0;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ p_stim_st : PROCESS(out_sosi, in_siso, is_reading)
+ BEGIN
+ in_sosi.valid <= '0';
+ IF out_sosi.valid='1' THEN
+ IF out_sosi.data(64) = '1' THEN -- Write request
+ IF TO_UINT(out_sosi.data(63 DOWNTO 56)) = 0 THEN
+ reg_a <= out_sosi.data(31 DOWNTO 0);
+ ELSIF TO_UINT(out_sosi.data(63 DOWNTO 56)) = 1 THEN
+ reg_b <= TO_UVEC(TO_UINT(out_sosi.data(31 DOWNTO 24))+1, 8) & out_sosi.data(23 DOWNTO 0); -- wrdata +1 to make distinguishable
+ ELSIF TO_UINT(out_sosi.data(63 DOWNTO 56)) = 2 THEN
+ reg_c <= out_sosi.data(31 DOWNTO 0);
+ ELSIF TO_UINT(out_sosi.data(63 DOWNTO 56)) = 3 THEN
+ reg_d <= TO_UVEC(TO_UINT(out_sosi.data(31 DOWNTO 24))+2, 8) & out_sosi.data(23 DOWNTO 0); -- wrdata +2 to make distinguishable
+ END IF;
+ out_siso.ready <= '1';
+ ELSE -- read request
+ IF NOT is_reading THEN
+ out_siso.ready <= '1';
+ in_sosi.valid <= '1';
+ IF TO_UINT(out_sosi.data(63 DOWNTO 56)) = 0 THEN
+ in_sosi.data(31 DOWNTO 0) <= reg_a;
+ ELSIF TO_UINT(out_sosi.data(63 DOWNTO 56)) = 1 THEN
+ in_sosi.data(31 DOWNTO 0) <= reg_b;
+ ELSIF TO_UINT(out_sosi.data(63 DOWNTO 56)) = 2 THEN
+ in_sosi.data(31 DOWNTO 0) <= reg_c;
+ ELSIF TO_UINT(out_sosi.data(63 DOWNTO 56)) = 3 THEN
+ in_sosi.data(31 DOWNTO 0) <= reg_d;
+ ELSE
+ in_sosi.data(31 DOWNTO 0) <= (OTHERS => '0');
+ END IF;
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ src_out <= c_dp_sosi_rst;
+ snk_out <= c_dp_siso_rdy;
+END GENERATE;
+
+gen_opencl : IF g_use_opencl GENERATE
+ src_out <= out_sosi;
+ out_siso <= src_in;
+ snk_out <= in_siso;
+ in_sosi <= snk_in;
+END GENERATE;
END str;
diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd b/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
new file mode 100644
index 0000000000..0ba60ac15b
--- /dev/null
+++ b/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
@@ -0,0 +1,179 @@
+-- --------------------------------------------------------------------------
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+
+-- --------------------------------------------------------------------------
+-- Author:
+-- . Reinier van der Walle
+-- Purpose:
+-- . tb for ta2_unb2b_mm_io
+-- Description:
+-- Simple testbench that provides MM stimuli of writing a
+-- register and then reading it back.
+-- . Usage -> as 10; run -a
+-- --------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, dp_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE dp_lib.tb_dp_pkg.ALL;
+
+ENTITY tb_ta2_unb2b_mm_io IS
+END tb_ta2_unb2b_mm_io;
+
+
+ARCHITECTURE tb OF tb_ta2_unb2b_mm_io IS
+ CONSTANT c_data_value : NATURAL := 10;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL clk : STD_LOGIC := '1';
+ SIGNAL rst : STD_LOGIC := '1';
+
+ SIGNAL reg_a : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL reg_b : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL reg_c : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL reg_d : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+
+ SIGNAL in_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL in_siso : t_dp_siso := c_dp_siso_rst;
+ SIGNAL out_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL out_siso : t_dp_siso := c_dp_siso_rst;
+
+ SIGNAL mm_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL mm_miso : t_mem_miso := c_mem_miso_rst;
+
+ SIGNAL busy : BOOLEAN := FALSE;
+
+BEGIN
+
+ clk <= (NOT clk) OR tb_end AFTER clk_period/2;
+ rst <= '1', '0' AFTER clk_period*7;
+
+ p_verify : PROCESS
+ BEGIN
+ WAIT UNTIL tb_end = '1';
+ ASSERT TO_UINT(mm_miso.rddata(31 DOWNTO 0)) = c_data_value REPORT "Wrong read data." SEVERITY ERROR;
+ END PROCESS;
+
+ u_dut : ENTITY work.ta2_unb2b_mm_io
+ GENERIC MAP(
+ g_use_opencl => FALSE
+ )
+ PORT MAP(
+ -- Memory-mapped clock domain
+ mm_rst => rst,
+ mm_clk => clk,
+
+ mm_mosi => mm_mosi,
+ mm_miso => mm_miso,
+
+ -- Streaming clock domain
+ kernel_reset => rst,
+ kernel_clk => clk,
+
+ -- ST sinks
+ snk_out => in_siso,
+ snk_in => in_sosi,
+ -- ST source
+ src_in => out_siso,
+ src_out => out_sosi
+ );
+
+
+ p_stim_mm : PROCESS
+ BEGIN
+ WAIT UNTIL rst='0';
+ proc_common_wait_some_cycles(clk, 15); -- give dc fifos time to initialize
+ proc_mem_mm_bus_wr(333, c_data_value, clk, mm_miso, mm_mosi); -- write value to unused address.
+ proc_mem_mm_bus_wr(0, c_data_value, clk, mm_miso, mm_mosi); -- write value to address 0.
+ proc_mem_mm_bus_wr(1, c_data_value+1, clk, mm_miso, mm_mosi); -- write value +1 to address 1.
+ proc_mem_mm_bus_wr(2, c_data_value+2, clk, mm_miso, mm_mosi); -- write value +2 to address 2.
+ proc_mem_mm_bus_wr(3, c_data_value+3, clk, mm_miso, mm_mosi); -- write value +3 to address 3.
+
+ proc_common_wait_some_cycles(clk, 5);
+ proc_mem_mm_bus_rd(333, clk, mm_miso, mm_mosi); -- read address from undefined address.
+ proc_mem_mm_bus_rd(3, clk, mm_miso, mm_mosi); -- read address 3.
+ proc_mem_mm_bus_rd(2, clk, mm_miso, mm_mosi); -- read address 2.
+ proc_mem_mm_bus_rd(1, clk, mm_miso, mm_mosi); -- read address 1.
+ proc_mem_mm_bus_rd(0, clk, mm_miso, mm_mosi); -- read address 0.
+
+ proc_common_wait_some_cycles(clk, 15);
+
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+
+ -- simulate an OpenCL kernel response (rl=0)
+ p_busy : PROCESS
+ BEGIN
+ WHILE tb_end = '0' LOOP
+ IF in_sosi.valid = '1' THEN
+ proc_common_wait_some_cycles(clk, 1);
+ busy <= TRUE;
+ proc_common_wait_some_cycles(clk, 3); -- simulate request time
+ busy <= FALSE;
+ ELSE
+ proc_common_wait_some_cycles(clk, 1);
+ END IF;
+ END LOOP;
+ WAIT;
+ END PROCESS;
+
+ p_stim_st : PROCESS(out_sosi, in_siso, busy)
+ BEGIN
+ in_sosi.valid <= '0';
+ IF out_sosi.valid='1' THEN
+ IF out_sosi.data(64) = '1' THEN -- Write request
+ IF TO_UINT(out_sosi.data(63 DOWNTO 56)) = 0 THEN
+ reg_a <= out_sosi.data(31 DOWNTO 0);
+ ELSIF TO_UINT(out_sosi.data(63 DOWNTO 56)) = 1 THEN
+ reg_b <= TO_UVEC(TO_UINT(out_sosi.data(31 DOWNTO 24))+1, 8) & out_sosi.data(23 DOWNTO 0);
+ ELSIF TO_UINT(out_sosi.data(63 DOWNTO 56)) = 2 THEN
+ reg_c <= out_sosi.data(31 DOWNTO 0);
+ ELSIF TO_UINT(out_sosi.data(63 DOWNTO 56)) = 3 THEN
+ reg_d <= TO_UVEC(TO_UINT(out_sosi.data(31 DOWNTO 24))+2, 8) & out_sosi.data(23 DOWNTO 0);
+ END IF;
+ out_siso.ready <= '1';
+ ELSE -- read request
+ IF NOT busy THEN
+ out_siso.ready <= '1';
+ in_sosi.valid <= '1';
+ IF TO_UINT(out_sosi.data(63 DOWNTO 56)) = 0 THEN
+ in_sosi.data(31 DOWNTO 0) <= reg_a;
+ ELSIF TO_UINT(out_sosi.data(63 DOWNTO 56)) = 1 THEN
+ in_sosi.data(31 DOWNTO 0) <= reg_b;
+ ELSIF TO_UINT(out_sosi.data(63 DOWNTO 56)) = 2 THEN
+ in_sosi.data(31 DOWNTO 0) <= reg_c;
+ ELSIF TO_UINT(out_sosi.data(63 DOWNTO 56)) = 3 THEN
+ in_sosi.data(31 DOWNTO 0) <= reg_d;
+ ELSE
+ in_sosi.data(31 DOWNTO 0) <= (OTHERS => '0');
+ END IF;
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+
+END tb;
+
--
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