diff --git a/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
index 74d40c08438dc590daabef91fe1508d1c5cbd40e..35e26e4734a5cb50ade05317cb0754107ce6c3ca 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
@@ -25,8 +25,10 @@
 --   > run -all
 -- --------------------------------------------------------------------------
 
-LIBRARY IEEE;
+LIBRARY IEEE, technology_lib;
 USE IEEE.std_logic_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
 
 ENTITY tb_tb_common_complex_mult IS
 END tb_tb_common_complex_mult;
@@ -45,9 +47,12 @@ BEGIN
   
   -- IP variants
   u_ip_18b      : ENTITY work.tb_common_complex_mult GENERIC MAP ("IP", 18, FALSE, 1, 0, 1, 1);
-  --u_ip_27b      : ENTITY work.tb_common_complex_mult GENERIC MAP ("IP", 27, FALSE, 1, 0, 1, 1);
   u_ip_18b_conj : ENTITY work.tb_common_complex_mult GENERIC MAP ("IP", 18,  TRUE, 1, 0, 1, 1);
-  --u_ip_27b_conj : ENTITY work.tb_common_complex_mult GENERIC MAP ("IP", 27,  TRUE, 1, 0, 1, 1);
+
+  --gen_27b : IF c_tech_select_default /= c_tech_stratixiv GENERATE
+  --  u_ip_27b      : ENTITY work.tb_common_complex_mult GENERIC MAP ("IP", 27, FALSE, 1, 0, 1, 1);
+  --  u_ip_27b_conj : ENTITY work.tb_common_complex_mult GENERIC MAP ("IP", 27,  TRUE, 1, 0, 1, 1);
+  --END GENERATE;
 
   -- RTL variants
   u_rtl_18b      : ENTITY work.tb_common_complex_mult GENERIC MAP ("RTL", 18, FALSE, 1, 0, 1, 1);