diff --git a/libraries/technology/10gbase_r/hdllib.cfg b/libraries/technology/10gbase_r/hdllib.cfg
index 6fd0f1dfc474cd08e7ebac4f872060e433a71daa..9b6302cee07394995810edc824cda4cfd3f5e6b7 100644
--- a/libraries/technology/10gbase_r/hdllib.cfg
+++ b/libraries/technology/10gbase_r/hdllib.cfg
@@ -1,19 +1,20 @@
hdl_lib_name = tech_10gbase_r
hdl_library_clause_name = tech_10gbase_r_lib
hdl_lib_uses_synth = technology common tech_pll tech_transceiver
-hdl_lib_uses_ip = ip_arria10_phy_10gbase_r ip_arria10_e3sge3_phy_10gbase_r ip_arria10_e1sg_phy_10gbase_r
- ip_arria10_phy_10gbase_r_4 ip_arria10_e3sge3_phy_10gbase_r_4 ip_arria10_e1sg_phy_10gbase_r_4
- ip_arria10_phy_10gbase_r_12 ip_arria10_e3sge3_phy_10gbase_r_12 ip_arria10_e1sg_phy_10gbase_r_12
- ip_arria10_phy_10gbase_r_24 ip_arria10_e3sge3_phy_10gbase_r_24 ip_arria10_e1sg_phy_10gbase_r_24
- ip_arria10_phy_10gbase_r_48 ip_arria10_e3sge3_phy_10gbase_r_48 ip_arria10_e1sg_phy_10gbase_r_48
- ip_arria10_transceiver_pll_10g ip_arria10_e3sge3_transceiver_pll_10g ip_arria10_e1sg_transceiver_pll_10g
- ip_arria10_transceiver_reset_controller_1 ip_arria10_e3sge3_transceiver_reset_controller_1 ip_arria10_e1sg_transceiver_reset_controller_1
- ip_arria10_transceiver_reset_controller_4 ip_arria10_e3sge3_transceiver_reset_controller_4 ip_arria10_e1sg_transceiver_reset_controller_4
- ip_arria10_transceiver_reset_controller_12 ip_arria10_e3sge3_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12
- ip_arria10_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24
- ip_arria10_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48 ip_arria10_e1sg_transceiver_reset_controller_48
- ip_arria10_e1sg_phy_10gbase_r_3
- ip_arria10_e1sg_transceiver_reset_controller_3
+hdl_lib_uses_ip = ip_arria10_phy_10gbase_r ip_arria10_e3sge3_phy_10gbase_r
+ ip_arria10_e1sg_phy_10gbase_r ip_arria10_e2sg_phy_10gbase_r
+ ip_arria10_phy_10gbase_r_4 ip_arria10_e3sge3_phy_10gbase_r_4 ip_arria10_e1sg_phy_10gbase_r_4 ip_arria10_e2sg_phy_10gbase_r_4
+ ip_arria10_phy_10gbase_r_12 ip_arria10_e3sge3_phy_10gbase_r_12 ip_arria10_e1sg_phy_10gbase_r_12 ip_arria10_e2sg_phy_10gbase_r_12
+ ip_arria10_phy_10gbase_r_24 ip_arria10_e3sge3_phy_10gbase_r_24 ip_arria10_e1sg_phy_10gbase_r_24 ip_arria10_e2sg_phy_10gbase_r_24
+ ip_arria10_phy_10gbase_r_48 ip_arria10_e3sge3_phy_10gbase_r_48 ip_arria10_e1sg_phy_10gbase_r_48 ip_arria10_e2sg_phy_10gbase_r_48
+ ip_arria10_transceiver_pll_10g ip_arria10_e3sge3_transceiver_pll_10g ip_arria10_e1sg_transceiver_pll_10g ip_arria10_e2sg_transceiver_pll_10g
+ ip_arria10_transceiver_reset_controller_1 ip_arria10_e3sge3_transceiver_reset_controller_1 ip_arria10_e1sg_transceiver_reset_controller_1 ip_arria10_e2sg_transceiver_reset_controller_1
+ ip_arria10_transceiver_reset_controller_4 ip_arria10_e3sge3_transceiver_reset_controller_4 ip_arria10_e1sg_transceiver_reset_controller_4 ip_arria10_e2sg_transceiver_reset_controller_4
+ ip_arria10_transceiver_reset_controller_12 ip_arria10_e3sge3_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12 ip_arria10_e2sg_transceiver_reset_controller_12
+ ip_arria10_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24 ip_arria10_e2sg_transceiver_reset_controller_24
+ ip_arria10_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48 ip_arria10_e1sg_transceiver_reset_controller_48 ip_arria10_e2sg_transceiver_reset_controller_48
+ ip_arria10_e1sg_phy_10gbase_r_3 ip_arria10_e2sg_phy_10gbase_r_3
+ ip_arria10_e1sg_transceiver_reset_controller_3 ip_arria10_e2sg_transceiver_reset_controller_3
hdl_lib_uses_sim =
hdl_lib_technology =
@@ -51,7 +52,19 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e1sg_transceiver_reset_controller_3 ip_arria10_e1sg_transceiver_reset_controller_3_altera_xcvr_reset_control_180
ip_arria10_e1sg_transceiver_reset_controller_4 ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_180
ip_arria10_e1sg_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_180
- ip_arria10_e1sg_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_180
+ ip_arria10_e2sg_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_180
+ ip_arria10_e2sg_phy_10gbase_r ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_151
+ ip_arria10_e2sg_phy_10gbase_r_3 ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_194
+ ip_arria10_e2sg_phy_10gbase_r_4 ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_194
+ ip_arria10_e2sg_phy_10gbase_r_12 ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_194
+ ip_arria10_e2sg_phy_10gbase_r_24 ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_194
+ ip_arria10_e2sg_phy_10gbase_r_48 ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_194
+ ip_arria10_e2sg_transceiver_pll_10g ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_194
+ ip_arria10_e2sg_transceiver_reset_controller_1 ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_194
+ ip_arria10_e2sg_transceiver_reset_controller_3 ip_arria10_e1sg_transceiver_reset_controller_3_altera_xcvr_reset_control_194
+ ip_arria10_e2sg_transceiver_reset_controller_4 ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_194
+ ip_arria10_e2sg_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_194
+ ip_arria10_e2sg_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_194
synth_files =
sim_10gbase_r.vhd
@@ -59,6 +72,7 @@ synth_files =
tech_10gbase_r_arria10.vhd
tech_10gbase_r_arria10_e3sge3.vhd
tech_10gbase_r_arria10_e1sg.vhd
+ tech_10gbase_r_arria10_e2sg.vhd
tech_10gbase_r.vhd
test_bench_files =
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r.vhd b/libraries/technology/10gbase_r/tech_10gbase_r.vhd
index 43f06b9b0ff201e9a8530bc100a17ff9fdf1adce..8d8d53de9753214944ea94635461f7ceb74862f7 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r.vhd
@@ -43,6 +43,8 @@ ENTITY tech_10gbase_r IS
reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso : OUT t_mem_miso;
reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_ip_arria10_e1sg_phy_10gbase_r_24_miso : OUT t_mem_miso;
+ reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_ip_arria10_e2sg_phy_10gbase_r_24_miso : OUT t_mem_miso;
-- Transceiver ATX PLL reference clock
tr_ref_clk_644 : IN STD_LOGIC; -- 644.531250 MHz
@@ -102,6 +104,18 @@ BEGIN
xgmii_tx_ready_arr, xgmii_rx_ready_arr, xgmii_tx_dc_arr, xgmii_rx_dc_arr,
tx_serial_arr, rx_serial_arr);
END GENERATE;
+
+ gen_ip_arria10_e2sg : IF c_use_technology=TRUE AND g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ENTITY work.tech_10gbase_r_arria10_e2sg
+ GENERIC MAP (g_sim, g_nof_channels)
+ PORT MAP (mm_clk, mm_rst,
+ reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi,
+ reg_ip_arria10_e2sg_phy_10gbase_r_24_miso,
+ tr_ref_clk_644,
+ clk_156, rst_156,
+ xgmii_tx_ready_arr, xgmii_rx_ready_arr, xgmii_tx_dc_arr, xgmii_rx_dc_arr,
+ tx_serial_arr, rx_serial_arr);
+ END GENERATE;
gem_sim_10gbase_r : IF c_use_sim_model=TRUE GENERATE
u0 : ENTITY work.sim_10gbase_r
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a48d4bc6571fcd72b8f853beb2c1c5399d04c811
--- /dev/null
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd
@@ -0,0 +1,653 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_180;
+LIBRARY ip_arria10_e2sg_phy_10gbase_r_3_altera_xcvr_native_a10_180;
+LIBRARY ip_arria10_e2sg_phy_10gbase_r_4_altera_xcvr_native_a10_180;
+LIBRARY ip_arria10_e2sg_phy_10gbase_r_12_altera_xcvr_native_a10_180;
+LIBRARY ip_arria10_e2sg_phy_10gbase_r_24_altera_xcvr_native_a10_180;
+LIBRARY ip_arria10_e2sg_phy_10gbase_r_48_altera_xcvr_native_a10_180;
+LIBRARY ip_arria10_e2sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_180;
+LIBRARY ip_arria10_e2sg_transceiver_reset_controller_1_altera_xcvr_reset_control_180;
+LIBRARY ip_arria10_e2sg_transceiver_reset_controller_4_altera_xcvr_reset_control_180;
+LIBRARY ip_arria10_e2sg_transceiver_reset_controller_12_altera_xcvr_reset_control_180;
+LIBRARY ip_arria10_e2sg_transceiver_reset_controller_24_altera_xcvr_reset_control_180;
+LIBRARY ip_arria10_e2sg_transceiver_reset_controller_48_altera_xcvr_reset_control_180;
+
+LIBRARY IEEE, tech_pll_lib, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE tech_pll_lib.tech_pll_component_pkg.ALL;
+USE work.tech_10gbase_r_component_pkg.ALL;
+
+ENTITY tech_10gbase_r_arria10_e2sg IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_nof_channels : NATURAL := 1
+ );
+ PORT (
+ -- MM
+ mm_clk : IN STD_LOGIC := '0';
+ mm_rst : IN STD_LOGIC := '0';
+ reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi : IN t_mem_mosi:= c_mem_mosi_rst;
+ reg_ip_arria10_e2sg_phy_10gbase_r_24_miso : OUT t_mem_miso;
+
+
+ -- Transceiver ATX PLL reference clock
+ tr_ref_clk_644 : IN STD_LOGIC; -- 644.531250 MHz
+
+ -- XGMII clocks
+ clk_156 : IN STD_LOGIC; -- 156.25 MHz
+ rst_156 : IN STD_LOGIC;
+
+ -- XGMII interface
+ xgmii_tx_ready_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- can be used for xon flow control
+ xgmii_rx_ready_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- typically leave not connected
+ xgmii_tx_dc_arr : IN t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
+ xgmii_rx_dc_arr : OUT t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
+
+ -- PHY serial IO
+ tx_serial_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ rx_serial_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+ );
+END tech_10gbase_r_arria10_e2sg;
+
+
+ARCHITECTURE str OF tech_10gbase_r_arria10_e2sg IS
+
+ -- FIXME check selection of g_nof_channels to be 1,4,12 or 24
+
+ --CONSTANT c_nof_channels_per_ip : NATURAL := sel_a_b(g_nof_channels=24, 24, 1); -- only support single 1 or block of 12
+ --CONSTANT c_nof_channels_per_ip : NATURAL := 24 WHEN g_nof_channels=24 ELSE 12 WHEN g_nof_channels=12 ELSE 1;
+ CONSTANT c_nof_channels_per_ip : NATURAL := g_nof_channels;
+
+
+ CONSTANT IP_SIZE : NATURAL := c_nof_channels_per_ip; -- short constant name alias to improve index readability
+ CONSTANT IP_SIZE_DATA : NATURAL := IP_SIZE * c_xgmii_data_w;
+ CONSTANT IP_SIZE_CONTROL : NATURAL := IP_SIZE * c_xgmii_nof_lanes;
+
+ SIGNAL tx_serial_clk : STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+ SIGNAL tr_coreclkin : STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+ SIGNAL tx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit
+ SIGNAL rx_parallel_data_arr : t_xgmii_d_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit
+ SIGNAL tx_control_arr : t_xgmii_c_arr(g_nof_channels-1 DOWNTO 0); -- 8 bit
+ SIGNAL rx_control_arr : t_xgmii_c_arr(g_nof_channels-1 DOWNTO 0); -- 8 bit
+
+ -- IP block SLV signals
+ SIGNAL tx_serial_clk_slv : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL tr_coreclkin_slv : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL tx_parallel_data_arr_slv : STD_LOGIC_VECTOR(g_nof_channels*c_xgmii_data_w-1 DOWNTO 0); -- 64 bit
+ SIGNAL rx_parallel_data_arr_slv : STD_LOGIC_VECTOR(g_nof_channels*c_xgmii_data_w-1 DOWNTO 0); -- 64 bit
+ SIGNAL tx_control_arr_slv : STD_LOGIC_VECTOR(g_nof_channels*c_xgmii_nof_lanes-1 DOWNTO 0); -- 8 bit
+ SIGNAL rx_control_arr_slv : STD_LOGIC_VECTOR(g_nof_channels*c_xgmii_nof_lanes-1 DOWNTO 0); -- 8 bit
+
+ -- transceiver reset controller
+ SIGNAL tx_analogreset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'1');
+ SIGNAL tx_digitalreset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'1');
+ SIGNAL rx_analogreset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'1');
+ SIGNAL rx_digitalreset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'1');
+ SIGNAL tx_cal_busy_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL rx_cal_busy_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL rx_is_lockedtodata_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0');
+
+ SIGNAL cal_busy_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0');
+
+ -- transceiver ATX PLL for 10G
+ SIGNAL atx_pll_powerdown_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL atx_pll_locked_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL atx_pll_locked : STD_LOGIC;
+ SIGNAL atx_pll_cal_busy : STD_LOGIC;
+
+BEGIN
+
+ -- Clocks
+ tr_coreclkin(0) <= clk_156;
+
+ gen_glue_logic : FOR I IN 0 TO g_nof_channels-1 GENERATE
+ -- Reset controller
+ cal_busy_arr(I) <= tx_cal_busy_arr(I) OR atx_pll_cal_busy;
+
+ -- On hardware use atx_pll_locked for all channels, in simulation model some timing difference between the channels
+ gen_hw : IF g_sim=FALSE GENERATE
+ atx_pll_locked_arr(I) <= atx_pll_locked;
+ END GENERATE;
+ gen_sim : IF g_sim=TRUE GENERATE
+ atx_pll_locked_arr(I) <= TRANSPORT atx_pll_locked AFTER tech_pll_clk_156_period*I;
+ END GENERATE;
+
+ -- XGMII
+ tx_parallel_data_arr(I) <= func_xgmii_d(xgmii_tx_dc_arr(I));
+ tx_control_arr(I) <= func_xgmii_c(xgmii_tx_dc_arr(I));
+
+ xgmii_rx_dc_arr(I) <= func_xgmii_dc(rx_parallel_data_arr(I), rx_control_arr(I));
+ END GENERATE;
+
+
+ gen_phy_1 : IF c_nof_channels_per_ip=1 GENERATE
+ gen_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
+ u_ip_arria10_e2sg_phy_10gbase_r : ip_arria10_e2sg_phy_10gbase_r
+ PORT MAP (
+ tx_analogreset => tx_analogreset_arr(I DOWNTO I),
+ tx_digitalreset => tx_digitalreset_arr(I DOWNTO I),
+ rx_analogreset => rx_analogreset_arr(I DOWNTO I),
+ rx_digitalreset => rx_digitalreset_arr(I DOWNTO I),
+ tx_cal_busy => tx_cal_busy_arr(I DOWNTO I),
+ rx_cal_busy => rx_cal_busy_arr(I DOWNTO I),
+
+ tx_serial_clk0 => tx_serial_clk,
+ rx_cdr_refclk0 => tr_ref_clk_644,
+ tx_serial_data => tx_serial_arr(I DOWNTO I),
+ rx_serial_data => rx_serial_arr(I DOWNTO I),
+
+ rx_is_lockedtoref => OPEN,
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(I DOWNTO I),
+
+ tx_coreclkin => tr_coreclkin, -- 156.25 MHz
+ rx_coreclkin => tr_coreclkin, -- 156.25 MHz
+
+ tx_parallel_data => tx_parallel_data_arr(I),
+ rx_parallel_data => rx_parallel_data_arr(I),
+ tx_control => tx_control_arr(I),
+ rx_control => rx_control_arr(I)
+
+ --tx_err_ins : in std_logic := '0'; -- tx_err_ins.tx_err_ins
+ --tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ --tx_enh_fifo_full : out std_logic_vector(0 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ --tx_enh_fifo_pfull : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ --tx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ --tx_enh_fifo_pempty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+
+ --rx_enh_data_valid : out std_logic_vector(0 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ --rx_enh_fifo_full : out std_logic_vector(0 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ --rx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ --rx_enh_fifo_del : out std_logic_vector(0 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ --rx_enh_fifo_insert : out std_logic_vector(0 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ --rx_enh_highber : out std_logic_vector(0 downto 0); -- rx_enh_highber.rx_enh_highber
+ --rx_enh_blk_lock : out std_logic_vector(0 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+
+ --unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- unused_tx_parallel_data.unused_tx_parallel_data
+ --unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ --unused_rx_parallel_data : out std_logic_vector(63 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ --unused_rx_control : out std_logic_vector(11 downto 0); -- unused_rx_control.unused_rx_control
+ );
+
+ u_ip_arria10_e2sg_transceiver_reset_controller_1 : ip_arria10_e2sg_transceiver_reset_controller_1
+ PORT MAP (
+ clock => clk_156,
+ reset => rst_156,
+ pll_powerdown => atx_pll_powerdown_arr(I DOWNTO I),
+ tx_analogreset => tx_analogreset_arr(I DOWNTO I),
+ tx_digitalreset => tx_digitalreset_arr(I DOWNTO I),
+ tx_ready => xgmii_tx_ready_arr(I DOWNTO I),
+ pll_locked => atx_pll_locked_arr(I DOWNTO I),
+ pll_select => "0", -- set to zero when using one PLL
+ tx_cal_busy => cal_busy_arr(I DOWNTO I),
+ rx_analogreset => rx_analogreset_arr(I DOWNTO I),
+ rx_digitalreset => rx_digitalreset_arr(I DOWNTO I),
+ rx_ready => xgmii_rx_ready_arr(I DOWNTO I),
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(I DOWNTO I),
+ rx_cal_busy => rx_cal_busy_arr(I DOWNTO I)
+ );
+ END GENERATE;
+ END GENERATE;
+
+ gen_phy_3 : IF c_nof_channels_per_ip=3 GENERATE
+ tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0));
+ tr_coreclkin_slv <= (OTHERS=>tr_coreclkin(0));
+
+ gen_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
+ tx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w) <= tx_parallel_data_arr(I);
+ tx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes) <= tx_control_arr(I);
+
+ rx_parallel_data_arr(I) <= rx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w);
+ rx_control_arr(I) <= rx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes);
+ END GENERATE;
+
+ u_ip_arria10_e2sg_phy_10gbase_r_3 : ip_arria10_e2sg_phy_10gbase_r_3
+ PORT MAP (
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+
+ --rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+
+ --tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
+ --rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
+
+ --tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
+ --tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ --tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ --tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ --tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ --tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ --tx_pma_div_clkout : out std_logic_vector(11 downto 0); -- tx_pma_div_clkout.clk
+
+ --rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+ --rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ --rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ --rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ --rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ --rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ --rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
+
+ --unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
+ --unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ --unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ --unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ );
+
+ u_ip_arria10_e2sg_transceiver_reset_controller_3 : ip_arria10_e2sg_transceiver_reset_controller_3
+ PORT MAP (
+ clock => clk_156, -- : in std_logic := '0'; -- clock.clk
+ pll_locked => atx_pll_locked_arr(0 DOWNTO 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_powerdown => atx_pll_powerdown_arr(0 DOWNTO 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ reset => rst_156, -- : in std_logic := '0'; -- reset.reset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 DOWNTO 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ );
+ END GENERATE;
+
+ gen_phy_4 : IF c_nof_channels_per_ip=4 GENERATE
+ tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0));
+ tr_coreclkin_slv <= (OTHERS=>tr_coreclkin(0));
+
+ gen_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
+ tx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w) <= tx_parallel_data_arr(I);
+ tx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes) <= tx_control_arr(I);
+
+ rx_parallel_data_arr(I) <= rx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w);
+ rx_control_arr(I) <= rx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes);
+ END GENERATE;
+
+ u_ip_arria10_e2sg_phy_10gbase_r_4 : ip_arria10_e2sg_phy_10gbase_r_4
+ PORT MAP (
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+
+ --rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+
+ --tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
+ --rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
+
+ --tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
+ --tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ --tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ --tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ --tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ --tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ --tx_pma_div_clkout : out std_logic_vector(11 downto 0); -- tx_pma_div_clkout.clk
+
+ --rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+ --rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ --rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ --rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ --rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ --rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ --rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
+
+ --unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
+ --unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ --unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ --unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ );
+
+ u_ip_arria10_e2sg_transceiver_reset_controller_4 : ip_arria10_e2sg_transceiver_reset_controller_4
+ PORT MAP (
+ clock => clk_156, -- : in std_logic := '0'; -- clock.clk
+ pll_locked => atx_pll_locked_arr(0 DOWNTO 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_powerdown => atx_pll_powerdown_arr(0 DOWNTO 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ reset => rst_156, -- : in std_logic := '0'; -- reset.reset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 DOWNTO 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ );
+ END GENERATE;
+
+
+
+
+ gen_phy_12 : IF c_nof_channels_per_ip=12 GENERATE
+ tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0));
+ tr_coreclkin_slv <= (OTHERS=>tr_coreclkin(0));
+
+ gen_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
+ tx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w) <= tx_parallel_data_arr(I);
+ tx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes) <= tx_control_arr(I);
+
+ rx_parallel_data_arr(I) <= rx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w);
+ rx_control_arr(I) <= rx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes);
+ END GENERATE;
+
+ u_ip_arria10_e2sg_phy_10gbase_r_12 : ip_arria10_e2sg_phy_10gbase_r_12
+ PORT MAP (
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+
+ --rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+
+ --tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
+ --rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
+
+ --tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
+ --tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ --tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ --tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ --tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ --tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ --tx_pma_div_clkout : out std_logic_vector(11 downto 0); -- tx_pma_div_clkout.clk
+
+ --rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+ --rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ --rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ --rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ --rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ --rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ --rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
+
+ --unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
+ --unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ --unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ --unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ );
+
+ u_ip_arria10_e2sg_transceiver_reset_controller_12 : ip_arria10_e2sg_transceiver_reset_controller_12
+ PORT MAP (
+ clock => clk_156, -- : in std_logic := '0'; -- clock.clk
+ pll_locked => atx_pll_locked_arr(0 DOWNTO 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_powerdown => atx_pll_powerdown_arr(0 DOWNTO 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ reset => rst_156, -- : in std_logic := '0'; -- reset.reset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 DOWNTO 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ );
+ END GENERATE;
+
+
+
+
+ gen_phy_24 : IF c_nof_channels_per_ip=24 GENERATE
+ tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0));
+ tr_coreclkin_slv <= (OTHERS=>tr_coreclkin(0));
+
+ gen_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
+ tx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w) <= tx_parallel_data_arr(I);
+ tx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes) <= tx_control_arr(I);
+
+ rx_parallel_data_arr(I) <= rx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w);
+ rx_control_arr(I) <= rx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes);
+ END GENERATE;
+
+ u_ip_arria10_e2sg_phy_10gbase_r_24 : ip_arria10_e2sg_phy_10gbase_r_24
+ PORT MAP (
+ reconfig_write(0) => reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi.wr, -- in std_logic_vector(0 downto 0)
+ reconfig_read(0) => reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi.rd, -- in std_logic_vector(0 downto 0)
+ reconfig_address => reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi.address(14 DOWNTO 0), -- in std_logic_vector(14 downto 0)
+ reconfig_writedata => reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi.wrdata(c_word_w-1 DOWNTO 0), -- in std_logic_vector(31 downto 0)
+ reconfig_readdata => reg_ip_arria10_e2sg_phy_10gbase_r_24_miso.rddata(c_word_w-1 DOWNTO 0), -- out std_logic_vector(31 downto 0);
+ reconfig_waitrequest(0) => reg_ip_arria10_e2sg_phy_10gbase_r_24_miso.waitrequest, -- out std_logic_vector(0 downto 0);
+ reconfig_clk(0) => mm_clk, -- in std_logic_vector(0 downto 0)
+ reconfig_reset(0) => mm_rst,
+
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+
+ --rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+
+ --tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
+ --rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
+
+ --tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
+ --tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ --tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ --tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ --tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ --tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ --tx_pma_div_clkout : out std_logic_vector(11 downto 0); -- tx_pma_div_clkout.clk
+
+ --rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+ --rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ --rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ --rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ --rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ --rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ --rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
+
+ --unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
+ --unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ --unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ --unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ );
+
+ u_ip_arria10_e2sg_transceiver_reset_controller_24 : ip_arria10_e2sg_transceiver_reset_controller_24
+ PORT MAP (
+ clock => clk_156, -- : in std_logic := '0'; -- clock.clk
+ pll_locked => atx_pll_locked_arr(0 DOWNTO 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_powerdown => atx_pll_powerdown_arr(0 DOWNTO 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ reset => rst_156, -- : in std_logic := '0'; -- reset.reset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 DOWNTO 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ );
+ END GENERATE;
+
+
+
+
+ gen_phy_48 : IF c_nof_channels_per_ip=48 GENERATE
+ tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0));
+ tr_coreclkin_slv <= (OTHERS=>tr_coreclkin(0));
+
+ gen_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
+ tx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w) <= tx_parallel_data_arr(I);
+ tx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes) <= tx_control_arr(I);
+
+ rx_parallel_data_arr(I) <= rx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w);
+ rx_control_arr(I) <= rx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes);
+ END GENERATE;
+
+ u_ip_arria10_e2sg_phy_10gbase_r_48 : ip_arria10_e2sg_phy_10gbase_r_48
+ PORT MAP (
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+
+ tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
+ tx_serial_data => tx_serial_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ rx_serial_data => rx_serial_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+
+ --rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+
+ tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+
+ tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ tx_control => tx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ rx_control => rx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
+
+ --tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
+ --rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
+
+ --tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
+ --tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ --tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ --tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ --tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ --tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ --tx_pma_div_clkout : out std_logic_vector(11 downto 0); -- tx_pma_div_clkout.clk
+
+ --rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+ --rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ --rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ --rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ --rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ --rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ --rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
+
+ --unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
+ --unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ --unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ --unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ );
+
+ u_ip_arria10_e2sg_transceiver_reset_controller_48 : ip_arria10_e2sg_transceiver_reset_controller_48
+ PORT MAP (
+ clock => clk_156, -- : in std_logic := '0'; -- clock.clk
+ pll_locked => atx_pll_locked_arr(0 DOWNTO 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_powerdown => atx_pll_powerdown_arr(0 DOWNTO 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ reset => rst_156, -- : in std_logic := '0'; -- reset.reset
+ rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_cal_busy => cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 DOWNTO 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ );
+ END GENERATE;
+
+
+ -- ATX PLL
+ u_ip_arria10_e2sg_transceiver_pll_10g : ip_arria10_e2sg_transceiver_pll_10g
+ PORT MAP (
+ pll_powerdown => atx_pll_powerdown_arr(0), -- only use reset controller 0 for ATX PLL power down, leave others not used
+ pll_refclk0 => tr_ref_clk_644,
+ pll_locked => atx_pll_locked,
+ pll_cal_busy => atx_pll_cal_busy,
+ mcgb_rst => atx_pll_powerdown_arr(0),
+ mcgb_serial_clk => tx_serial_clk(0)
+ );
+
+END str;
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
index e53273e5bbccf47ee1c57bb545bd0580153d4a64..fa7196f732e812a6709294ca703fb0adf60f4008 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
@@ -1255,4 +1255,465 @@ PACKAGE tech_10gbase_r_component_pkg IS
);
END COMPONENT;
+ ------------------------------------------------------------------------------
+ -- ip_arria10_e2sg
+ ------------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e2sg_phy_10gbase_r IS
+ PORT (
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_clkout : out std_logic_vector(0 downto 0); -- rx_clkout.clk
+ rx_control : out std_logic_vector(7 downto 0); -- rx_control.rx_control
+ rx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_enh_blk_lock : out std_logic_vector(0 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_data_valid : out std_logic_vector(0 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_fifo_del : out std_logic_vector(0 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_full : out std_logic_vector(0 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_insert : out std_logic_vector(0 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_highber : out std_logic_vector(0 downto 0); -- rx_enh_highber.rx_enh_highber
+ rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtoref : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_parallel_data : out std_logic_vector(63 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_prbs_done : out std_logic_vector(0 downto 0); -- rx_prbs_done.rx_prbs_done
+ rx_prbs_err : out std_logic_vector(0 downto 0); -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err_clr : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_seriallpbken : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
+ tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_clkout : out std_logic_vector(0 downto 0); -- tx_clkout.clk
+ tx_control : in std_logic_vector(7 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_full : out std_logic_vector(0 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_pempty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pfull : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_err_ins : in std_logic := '0'; -- tx_err_ins.tx_err_ins
+ tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_serial_clk0 : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data.tx_serial_data
+ unused_rx_control : out std_logic_vector(11 downto 0); -- unused_rx_control.unused_rx_control
+ unused_rx_parallel_data : out std_logic_vector(63 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ );
+ END COMPONENT;
+
+ component ip_arria10_e2sg_phy_10gbase_r_3 is
+ port (
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- write
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- read
+ reconfig_address : in std_logic_vector(11 downto 0) := (others => 'X'); -- address
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ reconfig_readdata : out std_logic_vector(31 downto 0); -- readdata
+ reconfig_waitrequest : out std_logic_vector(0 downto 0); -- waitrequest
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset
+ rx_analogreset : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_analogreset
+ rx_cal_busy : out std_logic_vector(2 downto 0); -- rx_cal_busy
+ rx_cdr_refclk0 : in std_logic := 'X'; -- clk
+ rx_clkout : out std_logic_vector(2 downto 0); -- clk
+ rx_control : out std_logic_vector(23 downto 0); -- rx_control
+ rx_coreclkin : in std_logic_vector(2 downto 0) := (others => 'X'); -- clk
+ rx_digitalreset : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_digitalreset
+ rx_enh_blk_lock : out std_logic_vector(2 downto 0); -- rx_enh_blk_lock
+ rx_enh_data_valid : out std_logic_vector(2 downto 0); -- rx_enh_data_valid
+ rx_enh_fifo_del : out std_logic_vector(2 downto 0); -- rx_enh_fifo_del
+ rx_enh_fifo_empty : out std_logic_vector(2 downto 0); -- rx_enh_fifo_empty
+ rx_enh_fifo_full : out std_logic_vector(2 downto 0); -- rx_enh_fifo_full
+ rx_enh_fifo_insert : out std_logic_vector(2 downto 0); -- rx_enh_fifo_insert
+ rx_enh_highber : out std_logic_vector(2 downto 0); -- rx_enh_highber
+ rx_is_lockedtodata : out std_logic_vector(2 downto 0); -- rx_is_lockedtodata
+ rx_is_lockedtoref : out std_logic_vector(2 downto 0); -- rx_is_lockedtoref
+ rx_parallel_data : out std_logic_vector(191 downto 0); -- rx_parallel_data
+ rx_prbs_done : out std_logic_vector(2 downto 0); -- rx_prbs_done
+ rx_prbs_err : out std_logic_vector(2 downto 0); -- rx_prbs_err
+ rx_prbs_err_clr : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_prbs_err_clr
+ rx_serial_data : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_serial_data
+ rx_seriallpbken : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_seriallpbken
+ tx_analogreset : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_analogreset
+ tx_cal_busy : out std_logic_vector(2 downto 0); -- tx_cal_busy
+ tx_clkout : out std_logic_vector(2 downto 0); -- clk
+ tx_control : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_control
+ tx_coreclkin : in std_logic_vector(2 downto 0) := (others => 'X'); -- clk
+ tx_digitalreset : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_digitalreset
+ tx_enh_data_valid : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_enh_data_valid
+ tx_enh_fifo_empty : out std_logic_vector(2 downto 0); -- tx_enh_fifo_empty
+ tx_enh_fifo_full : out std_logic_vector(2 downto 0); -- tx_enh_fifo_full
+ tx_enh_fifo_pempty : out std_logic_vector(2 downto 0); -- tx_enh_fifo_pempty
+ tx_enh_fifo_pfull : out std_logic_vector(2 downto 0); -- tx_enh_fifo_pfull
+ tx_err_ins : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_err_ins
+ tx_parallel_data : in std_logic_vector(191 downto 0) := (others => 'X'); -- tx_parallel_data
+ tx_serial_clk0 : in std_logic_vector(2 downto 0) := (others => 'X'); -- clk
+ tx_serial_data : out std_logic_vector(2 downto 0); -- tx_serial_data
+ unused_rx_control : out std_logic_vector(35 downto 0); -- unused_rx_control
+ unused_rx_parallel_data : out std_logic_vector(191 downto 0); -- unused_rx_parallel_data
+ unused_tx_control : in std_logic_vector(26 downto 0) := (others => 'X'); -- unused_tx_control
+ unused_tx_parallel_data : in std_logic_vector(191 downto 0) := (others => 'X') -- unused_tx_parallel_data
+ );
+ end component;
+
+
+ COMPONENT ip_arria10_e2sg_phy_10gbase_r_4
+ port (
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
+ reconfig_address : in std_logic_vector(11 downto 0) := (others => '0'); -- .address
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
+ rx_analogreset : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : out std_logic_vector(3 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_clkout : out std_logic_vector(3 downto 0); -- rx_clkout.clk
+ rx_control : out std_logic_vector(31 downto 0); -- rx_control.rx_control
+ rx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_enh_blk_lock : out std_logic_vector(3 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_data_valid : out std_logic_vector(3 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_fifo_del : out std_logic_vector(3 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_empty : out std_logic_vector(3 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_full : out std_logic_vector(3 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_insert : out std_logic_vector(3 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_highber : out std_logic_vector(3 downto 0); -- rx_enh_highber.rx_enh_highber
+ rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_parallel_data : out std_logic_vector(255 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_prbs_done : out std_logic_vector(3 downto 0); -- rx_prbs_done.rx_prbs_done
+ rx_prbs_err : out std_logic_vector(3 downto 0); -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err_clr : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
+ tx_analogreset : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : out std_logic_vector(3 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_clkout : out std_logic_vector(3 downto 0); -- tx_clkout.clk
+ tx_control : in std_logic_vector(31 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_coreclkin : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_digitalreset : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_enh_data_valid : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_fifo_empty : out std_logic_vector(3 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_full : out std_logic_vector(3 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_pempty : out std_logic_vector(3 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pfull : out std_logic_vector(3 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_err_ins : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
+ tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_serial_clk0 : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_data : out std_logic_vector(3 downto 0); -- tx_serial_data.tx_serial_data
+ unused_rx_control : out std_logic_vector(47 downto 0); -- unused_rx_control.unused_rx_control
+ unused_rx_parallel_data : out std_logic_vector(255 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_tx_control : in std_logic_vector(35 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ unused_tx_parallel_data : in std_logic_vector(255 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_phy_10gbase_r_12
+ PORT (
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
+ reconfig_address : in std_logic_vector(13 downto 0) := (others => '0'); -- .address
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
+ rx_analogreset : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
+ rx_control : out std_logic_vector(95 downto 0); -- rx_control.rx_control
+ rx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
+ rx_is_lockedtodata : out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_parallel_data : out std_logic_vector(767 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_prbs_done : out std_logic_vector(11 downto 0); -- rx_prbs_done.rx_prbs_done
+ rx_prbs_err : out std_logic_vector(11 downto 0); -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err_clr : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_serial_data : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_seriallpbken : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
+ tx_analogreset : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
+ tx_control : in std_logic_vector(95 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_coreclkin : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_digitalreset : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
+ tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_serial_clk0 : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_data : out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
+ unused_rx_control : out std_logic_vector(143 downto 0); -- unused_rx_control.unused_rx_control
+ unused_rx_parallel_data : out std_logic_vector(767 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_tx_control : in std_logic_vector(107 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ unused_tx_parallel_data : in std_logic_vector(767 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_phy_10gbase_r_24
+ PORT (
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
+ reconfig_address : in std_logic_vector(14 downto 0) := (others => '0'); -- .address
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
+ rx_analogreset : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : out std_logic_vector(23 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_clkout : out std_logic_vector(23 downto 0); -- rx_clkout.clk
+ rx_control : out std_logic_vector(191 downto 0); -- rx_control.rx_control
+ rx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_enh_blk_lock : out std_logic_vector(23 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_data_valid : out std_logic_vector(23 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_fifo_del : out std_logic_vector(23 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_empty : out std_logic_vector(23 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_full : out std_logic_vector(23 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_insert : out std_logic_vector(23 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_highber : out std_logic_vector(23 downto 0); -- rx_enh_highber.rx_enh_highber
+ rx_is_lockedtodata : out std_logic_vector(23 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtoref : out std_logic_vector(23 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_parallel_data : out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_prbs_done : out std_logic_vector(23 downto 0); -- rx_prbs_done.rx_prbs_done
+ rx_prbs_err : out std_logic_vector(23 downto 0); -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err_clr : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_serial_data : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_seriallpbken : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
+ tx_analogreset : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : out std_logic_vector(23 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_clkout : out std_logic_vector(23 downto 0); -- tx_clkout.clk
+ tx_control : in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_coreclkin : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_digitalreset : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_fifo_empty : out std_logic_vector(23 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_full : out std_logic_vector(23 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_pempty : out std_logic_vector(23 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pfull : out std_logic_vector(23 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_err_ins : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
+ tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_serial_clk0 : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_data : out std_logic_vector(23 downto 0); -- tx_serial_data.tx_serial_data
+ unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
+ unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_phy_10gbase_r_48
+ PORT (
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => '0'); -- .read
+ reconfig_address : in std_logic_vector(15 downto 0) := (others => '0'); -- .address
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reconfig_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ reconfig_waitrequest : out std_logic_vector(0 downto 0); -- .waitrequest
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_clk.clk
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_reset.reset
+ rx_analogreset : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : out std_logic_vector(47 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_clkout : out std_logic_vector(47 downto 0); -- rx_clkout.clk
+ rx_control : out std_logic_vector(383 downto 0); -- rx_control.rx_control
+ rx_coreclkin : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_digitalreset : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_enh_blk_lock : out std_logic_vector(47 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_data_valid : out std_logic_vector(47 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_fifo_del : out std_logic_vector(47 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_empty : out std_logic_vector(47 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_full : out std_logic_vector(47 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_insert : out std_logic_vector(47 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_highber : out std_logic_vector(47 downto 0); -- rx_enh_highber.rx_enh_highber
+ rx_is_lockedtodata : out std_logic_vector(47 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtoref : out std_logic_vector(47 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_parallel_data : out std_logic_vector(3071 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_prbs_done : out std_logic_vector(47 downto 0); -- rx_prbs_done.rx_prbs_done
+ rx_prbs_err : out std_logic_vector(47 downto 0); -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err_clr : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_serial_data : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_seriallpbken : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
+ tx_analogreset : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : out std_logic_vector(47 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_clkout : out std_logic_vector(47 downto 0); -- tx_clkout.clk
+ tx_control : in std_logic_vector(383 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_coreclkin : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_digitalreset : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_enh_data_valid : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_fifo_empty : out std_logic_vector(47 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_full : out std_logic_vector(47 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_pempty : out std_logic_vector(47 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pfull : out std_logic_vector(47 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_err_ins : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
+ tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_serial_clk0 : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_data : out std_logic_vector(47 downto 0); -- tx_serial_data.tx_serial_data
+ unused_rx_control : out std_logic_vector(575 downto 0); -- unused_rx_control.unused_rx_control
+ unused_rx_parallel_data : out std_logic_vector(3071 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_tx_control : in std_logic_vector(431 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ unused_tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_transceiver_pll_10g IS
+ PORT (
+ mcgb_rst : in std_logic := '0'; -- mcgb_rst.mcgb_rst
+ mcgb_serial_clk : out std_logic; -- mcgb_serial_clk.clk
+ pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
+ pll_locked : out std_logic; -- pll_locked.pll_locked
+ pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
+ pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
+ reconfig_write0 : in std_logic := '0'; -- reconfig_avmm0.write
+ reconfig_read0 : in std_logic := '0'; -- .read
+ reconfig_address0 : in std_logic_vector(9 downto 0) := (others => '0'); -- .address
+ reconfig_writedata0 : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reconfig_readdata0 : out std_logic_vector(31 downto 0); -- .readdata
+ reconfig_waitrequest0 : out std_logic; -- .waitrequest
+ reconfig_clk0 : in std_logic := '0'; -- reconfig_clk0.clk
+ reconfig_reset0 : in std_logic := '0'; -- reconfig_reset0.reset
+ tx_serial_clk : out std_logic -- tx_serial_clk.clk
+-- pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
+-- pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
+-- pll_locked : out std_logic; -- pll_locked.pll_locked
+-- pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
+-- mcgb_rst : in std_logic := '0';
+-- mcgb_serial_clk : out std_logic -- tx_serial_clk.clk
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_transceiver_reset_controller_1 IS
+ PORT (
+ clock : in std_logic := '0'; -- clock.clk
+ reset : in std_logic := '0'; -- reset.reset
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ tx_analogreset : out std_logic_vector(0 downto 0); -- tx_analogreset.tx_analogreset
+ tx_digitalreset : out std_logic_vector(0 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready : out std_logic_vector(0 downto 0); -- tx_ready.tx_ready
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ tx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset.rx_analogreset
+ rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_ready : out std_logic_vector(0 downto 0); -- rx_ready.rx_ready
+ rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0') -- rx_cal_busy.rx_cal_busy
+ );
+ END COMPONENT;
+
+ component ip_arria10_e2sg_transceiver_reset_controller_3 is
+ port (
+ clock : in std_logic := 'X'; -- clk
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
+ pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
+ reset : in std_logic := 'X'; -- reset
+ rx_analogreset : out std_logic_vector(2 downto 0); -- rx_analogreset
+ rx_cal_busy : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_cal_busy
+ rx_digitalreset : out std_logic_vector(2 downto 0); -- rx_digitalreset
+ rx_is_lockedtodata : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ rx_ready : out std_logic_vector(2 downto 0); -- rx_ready
+ tx_analogreset : out std_logic_vector(2 downto 0); -- tx_analogreset
+ tx_cal_busy : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_cal_busy
+ tx_digitalreset : out std_logic_vector(2 downto 0); -- tx_digitalreset
+ tx_ready : out std_logic_vector(2 downto 0) -- tx_ready
+ );
+ end component;
+
+ COMPONENT ip_arria10_e2sg_transceiver_reset_controller_4
+ port (
+ clock : in std_logic := '0'; -- clock.clk
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ reset : in std_logic := '0'; -- reset.reset
+ rx_analogreset : out std_logic_vector(3 downto 0); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset : out std_logic_vector(3 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready : out std_logic_vector(3 downto 0); -- rx_ready.rx_ready
+ tx_analogreset : out std_logic_vector(3 downto 0); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset : out std_logic_vector(3 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready : out std_logic_vector(3 downto 0) -- tx_ready.tx_ready
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_transceiver_reset_controller_12
+ PORT (
+ clock : in std_logic := '0'; -- clock.clk
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ reset : in std_logic := '0'; -- reset.reset
+ rx_analogreset : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
+ tx_analogreset : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_transceiver_reset_controller_24
+ PORT (
+ clock : in std_logic := '0'; -- clock.clk
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ reset : in std_logic := '0'; -- reset.reset
+ rx_analogreset : out std_logic_vector(23 downto 0); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset : out std_logic_vector(23 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata : in std_logic_vector(23 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready : out std_logic_vector(23 downto 0); -- rx_ready.rx_ready
+ tx_analogreset : out std_logic_vector(23 downto 0); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : in std_logic_vector(23 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset : out std_logic_vector(23 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready : out std_logic_vector(23 downto 0) -- tx_ready.tx_ready
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_transceiver_reset_controller_48
+ PORT (
+ clock : in std_logic := '0'; -- clock.clk
+ pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
+ pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
+ reset : in std_logic := '0'; -- reset.reset
+ rx_analogreset : out std_logic_vector(47 downto 0); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset : out std_logic_vector(47 downto 0); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata : in std_logic_vector(47 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready : out std_logic_vector(47 downto 0); -- rx_ready.rx_ready
+ tx_analogreset : out std_logic_vector(47 downto 0); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : in std_logic_vector(47 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset : out std_logic_vector(47 downto 0); -- tx_digitalreset.tx_digitalreset
+ tx_ready : out std_logic_vector(47 downto 0) -- tx_ready.tx_ready
+ );
+ END COMPONENT;
+
END tech_10gbase_r_component_pkg;
diff --git a/libraries/technology/clkbuf/hdllib.cfg b/libraries/technology/clkbuf/hdllib.cfg
index 8f8e995b7cb826a3c2268fe4501c3930de332712..c5e8d11c97e13449f0f404c5c95feeb05337fa2e 100644
--- a/libraries/technology/clkbuf/hdllib.cfg
+++ b/libraries/technology/clkbuf/hdllib.cfg
@@ -1,13 +1,14 @@
hdl_lib_name = tech_clkbuf
hdl_library_clause_name = tech_clkbuf_lib
hdl_lib_uses_synth = technology common
-hdl_lib_uses_ip = ip_arria10_clkbuf_global ip_arria10_e3sge3_clkbuf_global ip_arria10_e1sg_clkbuf_global
+hdl_lib_uses_ip = ip_arria10_clkbuf_global ip_arria10_e3sge3_clkbuf_global ip_arria10_e1sg_clkbuf_global ip_arria10_e2sg_clkbuf_global
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_clkbuf_global ip_arria10_clkbuf_global_altclkctrl_150
ip_arria10_e3sge3_clkbuf_global ip_arria10_e3sge3_clkbuf_global_altclkctrl_151
ip_arria10_e1sg_clkbuf_global ip_arria10_e1sg_clkbuf_global_altclkctrl_180
+ ip_arria10_e2sg_clkbuf_global ip_arria10_e2sg_clkbuf_global_altclkctrl_194
synth_files =
tech_clkbuf_component_pkg.vhd
diff --git a/libraries/technology/clkbuf/tech_clkbuf.vhd b/libraries/technology/clkbuf/tech_clkbuf.vhd
index 621bc2a7c2460b59a06a47da2cc5fac0a32d96e5..d0efd721c144144382e46e7ced177bb48306fbde 100644
--- a/libraries/technology/clkbuf/tech_clkbuf.vhd
+++ b/libraries/technology/clkbuf/tech_clkbuf.vhd
@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_clkbuf_global_altclkctrl_150;
LIBRARY ip_arria10_e3sge3_clkbuf_global_altclkctrl_151;
LIBRARY ip_arria10_e1sg_clkbuf_global_altclkctrl_180;
+LIBRARY ip_arria10_e2sg_clkbuf_global_altclkctrl_194;
ENTITY tech_clkbuf IS
GENERIC (
@@ -81,4 +82,16 @@ BEGIN
);
END GENERATE;
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e2sg
+ -----------------------------------------------------------------------------
+
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg AND g_clock_net="GLOBAL" GENERATE
+ u0 : ip_arria10_e2Ssg_clkbuf_global
+ PORT MAP (
+ inclk => inclk, -- inclk
+ outclk => outclk -- outclk
+ );
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd b/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd
index b398fe748185c853b324abfd2db36f3759b46c87..0a8c5bd423eef721619a044610c3a822dd0c66d8 100644
--- a/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd
+++ b/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd
@@ -60,5 +60,16 @@ PACKAGE tech_clkbuf_component_pkg IS
);
END COMPONENT;
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e2sg
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e2sg_clkbuf_global IS
+ PORT (
+ inclk : in std_logic := '0'; -- altclkctrl_input.inclk
+ outclk : out std_logic -- altclkctrl_output.outclk
+ );
+ END COMPONENT;
+
END tech_clkbuf_component_pkg;
diff --git a/libraries/technology/ddr/hdllib.cfg b/libraries/technology/ddr/hdllib.cfg
index c19a8419fdc68e5d91c75e81c992b76a24dcfbb0..4f653f1ac02336cf0a73521e35b844d7713c83ae 100644
--- a/libraries/technology/ddr/hdllib.cfg
+++ b/libraries/technology/ddr/hdllib.cfg
@@ -17,6 +17,8 @@ hdl_lib_uses_ip = ip_stratixiv_ddr3_uphy_4g_800_master
ip_arria10_e1sg_ddr4_8g_1600
ip_arria10_e1sg_ddr4_4g_2000
ip_arria10_e1sg_ddr4_8g_2400
+ ip_arria10_e2sg_ddr4_8g_1600
+ ip_arria10_e2sg_ddr4_8g_2400
hdl_lib_uses_sim = ip_stratixiv_ddr3_mem_model
ip_arria10_ddr4_mem_model_141
hdl_lib_technology =
@@ -39,6 +41,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e1sg_ddr4_8g_2400 ip_arria10_e1sg_ddr4_8g_2400_altera_emif_180
ip_stratixiv_ddr3_mem_model ip_stratixiv_ddr3_mem_model_lib
ip_arria10_ddr4_mem_model_141 ip_arria10_ddr4_mem_model_141
+ ip_arria10_e2sg_ddr4_8g_1600 ip_arria10_e2sg_ddr4_8g_1600_altera_emif_194
+ ip_arria10_e2sg_ddr4_8g_2400 ip_arria10_e2sg_ddr4_8g_2400_altera_emif_194
synth_files =
tech_ddr_pkg.vhd
@@ -48,6 +52,7 @@ synth_files =
tech_ddr_arria10.vhd
tech_ddr_arria10_e3sge3.vhd
tech_ddr_arria10_e1sg.vhd
+ tech_ddr_arria10_e2sg.vhd
tech_ddr.vhd
test_bench_files =
diff --git a/libraries/technology/ddr/tech_ddr.vhd b/libraries/technology/ddr/tech_ddr.vhd
index e125d3eca3a10a57d8076dc480c243dcd71f10e3..ec34468154f7d8a1e690ddec70b72df7f03e8dc4 100644
--- a/libraries/technology/ddr/tech_ddr.vhd
+++ b/libraries/technology/ddr/tech_ddr.vhd
@@ -113,6 +113,15 @@ BEGIN
phy4_in, phy4_io, phy4_ou);
END GENERATE;
+ gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ENTITY work.tech_ddr_arria10_e2sg
+ GENERIC MAP (g_tech_ddr)
+ PORT MAP (ref_clk, ref_rst,
+ ctlr_gen_clk, ctlr_gen_rst,
+ ctlr_mosi, ctlr_miso,
+ phy4_in, phy4_io, phy4_ou);
+ END GENERATE;
+
END GENERATE;
-----------------------------------------------------------------------------
diff --git a/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd b/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7d5becab3bc3c233a7dfa747a9a156d7e502b3ec
--- /dev/null
+++ b/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd
@@ -0,0 +1,201 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+
+-- Purpose: DDR4 memory access component for Arria10.
+-- Description:
+-- Remarks:
+-- . The local_init_done goes high some time after power up. It could have been
+-- AND-ed with ctlr_miso.waitrequest_n. However the timing closure for
+-- ctlr_miso.waitrequest_n can be critical, so therefore it is better not
+-- to combinatorially load it with the AND local_init_done. Instead a
+-- ctlr_miso.done field was added and used to pass on local_init_done. In fact
+-- for normal operation it is sufficient to only wait for
+-- ctlr_miso.waitrequest_n. The ctlr_miso.init_done is then only used for
+-- DDR interface monitoring purposes.
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_arria10_e2sg_ddr4_8g_1600_altera_emif_194;
+LIBRARY ip_arria10_e2sg_ddr4_8g_2400_altera_emif_194;
+
+LIBRARY IEEE, technology_lib, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE work.tech_ddr_pkg.ALL;
+USE work.tech_ddr_component_pkg.ALL;
+
+ENTITY tech_ddr_arria10_e2sg IS
+ GENERIC (
+ g_tech_ddr : t_c_tech_ddr
+ );
+ PORT (
+ -- PLL reference clock
+ ref_clk : IN STD_LOGIC;
+ ref_rst : IN STD_LOGIC;
+
+ -- Controller user interface
+ ctlr_gen_clk : OUT STD_LOGIC;
+ ctlr_gen_rst : OUT STD_LOGIC;
+
+ ctlr_mosi : IN t_mem_ctlr_mosi;
+ ctlr_miso : OUT t_mem_ctlr_miso;
+
+ -- PHY interface
+ phy_in : IN t_tech_ddr4_phy_in;
+ phy_io : INOUT t_tech_ddr4_phy_io;
+ phy_ou : OUT t_tech_ddr4_phy_ou
+ );
+END tech_ddr_arria10_e2sg;
+
+
+ARCHITECTURE str OF tech_ddr_arria10_e2sg IS
+
+ CONSTANT c_gigabytes : NATURAL := func_tech_ddr_module_size(g_tech_ddr);
+
+ CONSTANT c_ctlr_address_w : NATURAL := func_tech_ddr_ctlr_address_w(g_tech_ddr);
+ CONSTANT c_ctlr_data_w : NATURAL := 576;--func_tech_ddr_ctlr_data_w( g_tech_ddr);
+
+ SIGNAL i_ctlr_gen_clk : STD_LOGIC;
+ SIGNAL ref_rst_n : STD_LOGIC;
+ SIGNAL ctlr_gen_rst_n : STD_LOGIC := '0';
+
+ SIGNAL local_cal_success : STD_LOGIC;
+ SIGNAL local_cal_fail : STD_LOGIC;
+
+BEGIN
+
+ ctlr_gen_clk <= i_ctlr_gen_clk;
+
+ ref_rst_n <= NOT ref_rst;
+ ctlr_gen_rst <= NOT ctlr_gen_rst_n;
+
+
+
+ gen_ip_arria10_e2sg_ddr4_8g_1600 : IF g_tech_ddr.name="DDR4" AND c_gigabytes=8 AND g_tech_ddr.mts=1600 GENERATE
+
+ u_ip_arria10_e2sg_ddr4_8g_1600 : ip_arria10_e2sg_ddr4_8g_1600
+ PORT MAP (
+ amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_read_0 => ctlr_mosi.rd, -- .read
+ amm_write_0 => ctlr_mosi.wr, -- .write
+ amm_address_0 => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0), -- .address
+ amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w-1 DOWNTO 0), -- .readdata
+ amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0), -- .writedata
+ amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
+ amm_byteenable_0 => (OTHERS=>'1'), -- .byteenable
+ amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
+ emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
+ emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
+ global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- mem_conduit_end.mem_ck
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n
+ mem_a => phy_ou.a(g_tech_ddr.a_w-1 DOWNTO 0), -- .mem_a
+ sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
+ mem_bg => phy_ou.bg(g_tech_ddr.bg_w-1 DOWNTO 0), -- .mem_bg
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- .mem_cke
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w-1 DOWNTO 0), -- .mem_odt
+ sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
+ sl(mem_par) => phy_ou.par, -- .mem_par
+ mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
+ mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w-1 DOWNTO 0), -- .mem_dbi_n
+ oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
+ pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
+ local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
+ local_cal_fail => local_cal_fail -- .local_cal_fail
+ );
+
+ -- Signals in DDR3 that are not available with DDR4:
+ --
+ --avl_burstbegin => ctlr_mosi.burstbegin, -- .beginbursttransfer
+ -- beginbursttransfer is obselete for new Avalon designs, because the slave can count valid data itself to know when a new burst starts
+ --
+ --local_init_done => ctlr_miso.done, -- status.local_init_done
+ -- local_init_done = ctlr_init_done originally and mapped to ctlr_miso.done for the DDR3 IP. For the DDR4 IP the local_cal_success and
+ -- NOT local_cal_fail seem to serve as local_init_done
+
+ ctlr_miso.done <= local_cal_success AND NOT local_cal_fail WHEN rising_edge(i_ctlr_gen_clk);
+ ctlr_miso.cal_ok <= local_cal_success;
+ ctlr_miso.cal_fail <= local_cal_fail;
+
+ END GENERATE;
+
+ gen_ip_arria10_e2sg_ddr4_8g_2400 : IF g_tech_ddr.name="DDR4" AND c_gigabytes=8 AND g_tech_ddr.mts=2400 GENERATE
+
+ u_ip_arria10_e2sg_ddr4_8g_2400 : ip_arria10_e2sg_ddr4_8g_2400
+ PORT MAP (
+ amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_read_0 => ctlr_mosi.rd, -- .read
+ amm_write_0 => ctlr_mosi.wr, -- .write
+ amm_address_0 => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0), -- .address
+ amm_readdata_0 => ctlr_miso.rddata(c_ctlr_data_w-1 DOWNTO 0), -- .readdata
+ amm_writedata_0 => ctlr_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0), -- .writedata
+ amm_burstcount_0 => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
+ amm_byteenable_0 => (OTHERS=>'1'), -- .byteenable
+ amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
+ emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
+ emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
+ global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
+ mem_ck => phy_ou.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- mem_conduit_end.mem_ck
+ mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n
+ mem_a => phy_ou.a(g_tech_ddr.a_w-1 DOWNTO 0), -- .mem_a
+ sl(mem_act_n) => phy_ou.act_n, -- .mem_act_n
+ mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
+ mem_bg => phy_ou.bg(g_tech_ddr.bg_w-1 DOWNTO 0), -- .mem_bg
+ mem_cke => phy_ou.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- .mem_cke
+ mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
+ mem_odt => phy_ou.odt(g_tech_ddr.odt_w-1 DOWNTO 0), -- .mem_odt
+ sl(mem_reset_n) => phy_ou.reset_n, -- .mem_reset_n
+ sl(mem_par) => phy_ou.par, -- .mem_par
+ mem_alert_n => slv(phy_in.alert_n), -- .mem_alert_n
+ mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
+ mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
+ mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
+ mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w-1 DOWNTO 0), -- .mem_dbi_n
+ oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
+ pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
+ local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
+ local_cal_fail => local_cal_fail -- .local_cal_fail
+ );
+
+ -- Signals in DDR3 that are not available with DDR4:
+ --
+ --avl_burstbegin => ctlr_mosi.burstbegin, -- .beginbursttransfer
+ -- beginbursttransfer is obselete for new Avalon designs, because the slave can count valid data itself to know when a new burst starts
+ --
+ --local_init_done => ctlr_miso.done, -- status.local_init_done
+ -- local_init_done = ctlr_init_done originally and mapped to ctlr_miso.done for the DDR3 IP. For the DDR4 IP the local_cal_success and
+ -- NOT local_cal_fail seem to serve as local_init_done
+
+ ctlr_miso.done <= local_cal_success AND NOT local_cal_fail WHEN rising_edge(i_ctlr_gen_clk);
+ ctlr_miso.cal_ok <= local_cal_success;
+ ctlr_miso.cal_fail <= local_cal_fail;
+
+ END GENERATE;
+
+END str;
diff --git a/libraries/technology/ddr/tech_ddr_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
index 2284612023138e43eac50447b5d0bf100d3c70f5..52d1159aa6d8458ee1b02e96abd86df36e5f7cd2 100644
--- a/libraries/technology/ddr/tech_ddr_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
@@ -604,7 +604,82 @@ PACKAGE tech_ddr_component_pkg IS
local_cal_fail : out std_logic -- .local_cal_fail
);
END COMPONENT;
-
+
+ -- Dual rank version for e2sg
+ COMPONENT ip_arria10_e2sg_ddr4_8g_1600 IS
+ PORT (
+ amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_read_0 : in std_logic := '0'; -- .read
+ amm_write_0 : in std_logic := '0'; -- .write
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => '0'); -- .address
+ amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
+ amm_readdatavalid_0 : out std_logic; -- .readdatavalid
+ emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
+ emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
+ global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
+ mem_ck : out std_logic_vector(1 downto 0); -- mem_conduit_end.mem_ck
+ mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
+ mem_a : out std_logic_vector(16 downto 0); -- .mem_a
+ mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
+ mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
+ mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
+ mem_cke : out std_logic_vector(1 downto 0); -- .mem_cke
+ mem_cs_n : out std_logic_vector(1 downto 0); -- .mem_cs_n
+ mem_odt : out std_logic_vector(1 downto 0); -- .mem_odt
+ mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
+ mem_par : out std_logic_vector(0 downto 0); -- .mem_par
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
+ oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
+ pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
+ local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
+ local_cal_fail : out std_logic -- .local_cal_fail
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_ddr4_8g_2400 IS
+ PORT (
+ amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_read_0 : in std_logic := '0'; -- .read
+ amm_write_0 : in std_logic := '0'; -- .write
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => '0'); -- .address
+ amm_readdata_0 : out std_logic_vector(575 downto 0); -- .readdata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => '0'); -- .writedata
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => '0'); -- .byteenable
+ amm_readdatavalid_0 : out std_logic; -- .readdatavalid
+ emif_usr_clk : out std_logic; -- emif_usr_clk_clock_source.clk
+ emif_usr_reset_n : out std_logic; -- emif_usr_reset_reset_source.reset_n
+ global_reset_n : in std_logic := '0'; -- global_reset_reset_sink.reset_n
+ mem_ck : out std_logic_vector(1 downto 0); -- mem_conduit_end.mem_ck
+ mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
+ mem_a : out std_logic_vector(16 downto 0); -- .mem_a
+ mem_act_n : out std_logic_vector(0 downto 0); -- .mem_act_n
+ mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
+ mem_bg : out std_logic_vector(1 downto 0); -- .mem_bg
+ mem_cke : out std_logic_vector(1 downto 0); -- .mem_cke
+ mem_cs_n : out std_logic_vector(1 downto 0); -- .mem_cs_n
+ mem_odt : out std_logic_vector(1 downto 0); -- .mem_odt
+ mem_reset_n : out std_logic_vector(0 downto 0); -- .mem_reset_n
+ mem_par : out std_logic_vector(0 downto 0); -- .mem_par
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_alert_n
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dbi_n
+ oct_rzqin : in std_logic := '0'; -- oct_conduit_end.oct_rzqin
+ pll_ref_clk : in std_logic := '0'; -- pll_ref_clk_clock_sink.clk
+ local_cal_success : out std_logic; -- status_conduit_end.local_cal_success
+ local_cal_fail : out std_logic -- .local_cal_fail
+ );
+ END COMPONENT;
+
END tech_ddr_component_pkg;
PACKAGE BODY tech_ddr_component_pkg IS
diff --git a/libraries/technology/eth_10g/hdllib.cfg b/libraries/technology/eth_10g/hdllib.cfg
index 71ceeaedd741088c8f3eea66ba17725ca36aa2aa..4c7a63445a617edfbe77926df45e4b1d38d32bba 100644
--- a/libraries/technology/eth_10g/hdllib.cfg
+++ b/libraries/technology/eth_10g/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = tech_eth_10g
hdl_library_clause_name = tech_eth_10g_lib
-hdl_lib_uses_synth = technology tech_pll tech_mac_10g common dp ip_stratixiv_eth_10g ip_arria10_eth_10g ip_arria10_e3sge3_eth_10g ip_arria10_e1sg_eth_10g
+hdl_lib_uses_synth = technology tech_pll tech_mac_10g common dp ip_stratixiv_eth_10g ip_arria10_eth_10g ip_arria10_e3sge3_eth_10g ip_arria10_e1sg_eth_10g ip_arria10_e2sg_eth_10g
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -8,6 +8,7 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_eth_10g ip_arria10_eth_10g_lib
ip_arria10_e3sge3_eth_10g ip_arria10_e3sge3_eth_10g_lib
ip_arria10_e1sg_eth_10g ip_arria10_e1sg_eth_10g_lib
+ ip_arria10_e2sg_eth_10g ip_arria10_e2sg_eth_10g_lib
synth_files =
tech_eth_10g_component_pkg.vhd
@@ -15,6 +16,7 @@ synth_files =
tech_eth_10g_arria10.vhd
tech_eth_10g_arria10_e3sge3.vhd
tech_eth_10g_arria10_e1sg.vhd
+ tech_eth_10g_arria10_e2sg.vhd
tech_eth_10g_clocks.vhd
tech_eth_10g.vhd
diff --git a/libraries/technology/eth_10g/tech_eth_10g.vhd b/libraries/technology/eth_10g/tech_eth_10g.vhd
index aa885fedae2ba562c23eb2f4bec5b52ac2ee568e..901ffac3b5af74bca9214a5c56658de05a8273cd 100644
--- a/libraries/technology/eth_10g/tech_eth_10g.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g.vhd
@@ -311,4 +311,49 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ENTITY work.tech_eth_10g_arria10_e2sg
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_nof_channels => g_nof_channels,
+ g_direction => g_direction,
+ g_use_loopback => g_use_loopback,
+ g_pre_header_padding => g_pre_header_padding
+ )
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => tr_ref_clk_644,
+
+ -- Data clocks
+ clk_312 => tr_ref_clk_312,
+ clk_156 => tr_ref_clk_156,
+ rst_156 => tr_ref_rst_156,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mac_mosi => mac_mosi,
+ mac_miso => mac_miso,
+
+ reg_eth10g_mosi => reg_eth10g_mosi,
+ reg_eth10g_miso => reg_eth10g_miso,
+
+ reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
+ reg_ip_arria10_e2sg_phy_10gbase_r_24_miso => reg_10gbase_r_24_miso,
+
+ -- ST
+ tx_snk_in_arr => tx_snk_in_arr, -- 64 bit data @ tr_ref_clk_156
+ tx_snk_out_arr => tx_snk_out_arr,
+
+ rx_src_out_arr => rx_src_out_arr, -- 64 bit data @ tr_ref_clk_156
+ rx_src_in_arr => rx_src_in_arr,
+
+ -- Serial
+ serial_tx_arr => serial_tx_arr,
+ serial_rx_arr => serial_rx_arr
+ );
+ END GENERATE;
+
END str;
diff --git a/libraries/technology/eth_10g/tech_eth_10g_arria10_e2sg.vhd b/libraries/technology/eth_10g/tech_eth_10g_arria10_e2sg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3b98fea9426310d386889a0020aed291e8fd7ef1
--- /dev/null
+++ b/libraries/technology/eth_10g/tech_eth_10g_arria10_e2sg.vhd
@@ -0,0 +1,187 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+
+-- Purpose: Combine mac_10g and 10gbase_r for c_tech_arria10_e2sg
+-- Description
+--
+-- The clocks come from an external central fPLL:
+--
+-- tx_ref_clk_644 --> fPLL --> clk_312
+-- clk_156, rst_156
+-- Blockdiagram:
+--
+-- 312 156 644
+-- _________ | | | ____________
+-- | | | | | | |
+-- | |<--/ | \-->| |
+-- | |<-----+----->| |
+-- | | | |
+-- | | XGMII | |
+-- tx_snk --->|tech_ |------------>|tech_ |---> serial_tx
+-- rx_src <---|mac_10g|<------------|10gbase_r |<--- serial_rx
+-- | | | |
+-- |_______|--\ /--|__________|
+-- | | |
+-- mac_mm | |
+-- | v
+-- ( v xgmii_tx_ready)
+-- tx_snk_out.xon <--(xgmii_link_status[1:0])
+--
+-- . g_direction:
+-- "TX_RX" = Default support bidir
+-- "TX_ONLY" = Uses a bidir MAC and connects the MAC Tx to the MAC RX.
+-- "RX_ONLY" = Same as "TX_RX"
+-- See tech_eth_10g_stratixiv.vhd for more details.
+--
+-- Remarks:
+-- . xgmii_link_status:
+-- When the xgmii_tx_ready from the 10gbase_r and the xgmii_link_status from
+-- the mac_10g are both be OK then the tx_snk.xon is asserted to allow the
+-- user data transmission.
+-- The tb_tech_eth_10g reveals that xgmii_tx_ready goes high after some power
+-- up time and then remains active independent of link_fault.
+-- A link fault eg. due to rx disconnect is detected by the link fault status:
+-- 0 = OK
+-- 1 = local fault
+-- 2 = remote fault
+--
+-- From google search:
+-- Link fault Operation
+-- 1) Device B detects loss of signal. Local fault is signaled by PHY of Device B to Device B.
+-- 2) Device B ceases transmission of MAC frames and transmits remote fault to Device A.
+-- 3) Device A receives remote fault from Device B.
+-- 4) Device A stops sending frames, continuously generates Idle.
+--
+-- Hence when the xgmii_link_status is OK then the other side is also OK so
+-- then it is also appropriate to release tx_snk.xon.
+--
+-- The XGMII link status can be monitored via the reg_eth10 MM register:
+--
+-- addr data[31:0]
+-- 0 [0] = tx_snk_out_arr(I).xon
+-- [1] = xgmii_tx_ready_arr(I)
+-- [3:2] = xgmii_link_status_arr(I)
+--
+
+LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_mac_10g_lib, ip_arria10_e2sg_eth_10g_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
+USE work.tech_eth_10g_component_pkg.ALL;
+
+ENTITY tech_eth_10g_arria10_e2sg IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
+ g_nof_channels : NATURAL := 1;
+ g_direction : STRING := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_use_loopback : BOOLEAN := FALSE;
+ g_pre_header_padding : BOOLEAN := FALSE
+ );
+ PORT (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 : IN STD_LOGIC := '0'; -- 644.531250 MHz for 10GBASE-R
+
+ -- Data clocks
+ clk_312 : IN STD_LOGIC := '0';
+ clk_156 : IN STD_LOGIC := '0';
+ rst_156 : IN STD_LOGIC := '0';
+
+ -- MM
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+
+ mac_mosi : IN t_mem_mosi; -- MAG_10G (CSR)
+ mac_miso : OUT t_mem_miso;
+
+ reg_eth10g_mosi : IN t_mem_mosi; -- ETH10G (link status register)
+ reg_eth10g_miso : OUT t_mem_miso;
+
+ reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_ip_arria10_e2sg_phy_10gbase_r_24_miso : OUT t_mem_miso;
+
+ -- ST
+ tx_snk_in_arr : IN t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156
+ tx_snk_out_arr : OUT t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156
+ rx_src_in_arr : IN t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ -- Serial
+ serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+ );
+END tech_eth_10g_arria10_e2sg;
+
+
+ARCHITECTURE str OF tech_eth_10g_arria10_e2sg IS
+
+BEGIN
+ u_ip_arria10_e2sg_eth_10g : ip_arria10_e2sg_eth_10g
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_nof_channels => g_nof_channels,
+ g_direction => g_direction,
+ g_use_loopback => g_use_loopback,
+ g_pre_header_padding => g_pre_header_padding
+ )
+ PORT MAP(
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => tr_ref_clk_644,
+
+ -- Data clocks
+ clk_312 => clk_312,
+ clk_156 => clk_156,
+ rst_156 => rst_156,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mac_mosi => mac_mosi,
+ mac_miso => mac_miso,
+
+ reg_eth10g_mosi => reg_eth10g_mosi,
+ reg_eth10g_miso => reg_eth10g_miso,
+
+ reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi => reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi,
+ reg_ip_arria10_e2sg_phy_10gbase_r_24_miso => reg_ip_arria10_e2sg_phy_10gbase_r_24_miso,
+
+ -- ST
+ tx_snk_in_arr => tx_snk_in_arr,
+ tx_snk_out_arr => tx_snk_out_arr,
+
+ rx_src_out_arr => rx_src_out_arr,
+ rx_src_in_arr => rx_src_in_arr,
+
+ -- Serial
+ serial_tx_arr => serial_tx_arr,
+ serial_rx_arr => serial_rx_arr
+ );
+
+END str;
diff --git a/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd b/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd
index 2e9f9805f0c353573ac31da705c3dde4f0fcbf73..1e5cf5a8703be817b54856775632e1c7dc658000 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd
@@ -85,7 +85,7 @@ BEGIN
eth_rx_rst_arr <= rx_rst_arr;
END GENERATE;
- gen_clocks_10gbase_r : IF g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg GENERATE
+ gen_clocks_10gbase_r : IF g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg GENERATE
eth_tx_clk_arr <= (OTHERS=>tr_ref_clk_156);
eth_tx_rst_arr <= (OTHERS=>tr_ref_rst_156);
diff --git a/libraries/technology/eth_10g/tech_eth_10g_component_pkg.vhd b/libraries/technology/eth_10g/tech_eth_10g_component_pkg.vhd
index 0b2b4b4894d47efb176ed71a3424dbe9bf384503..b3d74c6db9d2224676922e88229353505400ccd8 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_component_pkg.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_component_pkg.vhd
@@ -172,6 +172,7 @@ PACKAGE tech_eth_10g_component_pkg IS
serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
);
END COMPONENT;
+
------------------------------------------------------------------------------
-- ip_arria10_e1sg
------------------------------------------------------------------------------
@@ -220,6 +221,54 @@ PACKAGE tech_eth_10g_component_pkg IS
);
END COMPONENT;
+ ------------------------------------------------------------------------------
+ -- ip_arria10_e2sg
+ ------------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e2sg_eth_10g IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
+ g_nof_channels : NATURAL := 1;
+ g_direction : STRING := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_use_loopback : BOOLEAN := FALSE;
+ g_pre_header_padding : BOOLEAN := FALSE
+ );
+ PORT (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 : IN STD_LOGIC := '0'; -- 644.531250 MHz for 10GBASE-R
+
+ -- Data clocks
+ clk_312 : IN STD_LOGIC := '0';
+ clk_156 : IN STD_LOGIC := '0';
+ rst_156 : IN STD_LOGIC := '0';
+
+ -- MM
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+
+ mac_mosi : IN t_mem_mosi; -- MAG_10G (CSR)
+ mac_miso : OUT t_mem_miso;
+
+ reg_eth10g_mosi : IN t_mem_mosi; -- ETH10G (link status register)
+ reg_eth10g_miso : OUT t_mem_miso;
+
+ reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_ip_arria10_e2sg_phy_10gbase_r_24_miso : OUT t_mem_miso;
+
+ -- ST
+ tx_snk_in_arr : IN t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156
+ tx_snk_out_arr : OUT t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156
+ rx_src_in_arr : IN t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ -- Serial
+ serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
END tech_eth_10g_component_pkg;
PACKAGE BODY tech_eth_10g_component_pkg IS
diff --git a/libraries/technology/fifo/hdllib.cfg b/libraries/technology/fifo/hdllib.cfg
index 94cd2d59f246b344fd5019cf1b090247fd25468c..e8bd853aafbd62706a63a2e6daabdef02571149b 100644
--- a/libraries/technology/fifo/hdllib.cfg
+++ b/libraries/technology/fifo/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = tech_fifo
hdl_library_clause_name = tech_fifo_lib
-hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo ip_arria10_e1sg_fifo
+hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo ip_arria10_e1sg_fifo ip_arria10_e2sg_fifo
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -8,6 +8,7 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_fifo ip_arria10_fifo_lib
ip_arria10_e3sge3_fifo ip_arria10_e3sge3_fifo_lib
ip_arria10_e1sg_fifo ip_arria10_e1sg_fifo_lib
+ ip_arria10_e2sg_fifo ip_arria10_e2sg_fifo_lib
synth_files =
tech_fifo_component_pkg.vhd
diff --git a/libraries/technology/fifo/tech_fifo_component_pkg.vhd b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
index 7ba288c714efa0bcbac4916579be70c7c322c08d..f325b78e7b904474735804721fbd1ddf1435034f 100644
--- a/libraries/technology/fifo/tech_fifo_component_pkg.vhd
+++ b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
@@ -287,5 +287,70 @@ PACKAGE tech_fifo_component_pkg IS
);
END COMPONENT;
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e2sg
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e2sg_fifo_sc IS
+ GENERIC (
+ g_use_eab : STRING := "ON";
+ g_dat_w : NATURAL := 20;
+ g_nof_words : NATURAL := 1024
+ );
+ PORT (
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdreq : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ full : OUT STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
+ usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_fifo_dc IS
+ GENERIC (
+ g_use_eab : STRING := "ON";
+ g_dat_w : NATURAL := 20;
+ g_nof_words : NATURAL := 1024
+ );
+ PORT (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
+ wrfull : OUT STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_fifo_dc_mixed_widths IS
+ GENERIC (
+ g_nof_words : NATURAL := 1024; -- FIFO size in nof wr_dat words
+ g_wrdat_w : NATURAL := 20;
+ g_rddat_w : NATURAL := 10
+ );
+ PORT (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
+ wrfull : OUT STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
END tech_fifo_component_pkg;
diff --git a/libraries/technology/fifo/tech_fifo_dc.vhd b/libraries/technology/fifo/tech_fifo_dc.vhd
index f51d503dbfebdbaece3f92601779d14866bf7309..997612ba611b5575ab2bd8c2e1a29d084a4275c2 100644
--- a/libraries/technology/fifo/tech_fifo_dc.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc.vhd
@@ -30,6 +30,7 @@ LIBRARY ip_stratixiv_fifo_lib;
LIBRARY ip_arria10_fifo_lib;
LIBRARY ip_arria10_e3sge3_fifo_lib;
LIBRARY ip_arria10_e1sg_fifo_lib;
+LIBRARY ip_arria10_e2sg_fifo_lib;
ENTITY tech_fifo_dc IS
GENERIC (
@@ -82,4 +83,10 @@ BEGIN
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
END GENERATE;
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_fifo_dc
+ GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
+ PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
index d1219d60eb6918c81d9eafb59bc6b874499646c4..5aba78979bb35ac2b70cc65d9dca8064553e93b0 100644
--- a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
@@ -30,6 +30,7 @@ LIBRARY ip_stratixiv_fifo_lib;
LIBRARY ip_arria10_fifo_lib;
LIBRARY ip_arria10_e3sge3_fifo_lib;
LIBRARY ip_arria10_e1sg_fifo_lib;
+LIBRARY ip_arria10_e2sg_fifo_lib;
ENTITY tech_fifo_dc_mixed_widths IS
GENERIC (
@@ -81,5 +82,11 @@ BEGIN
GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
END GENERATE;
-
+
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_fifo_dc_mixed_widths
+ GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
+ PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/fifo/tech_fifo_sc.vhd b/libraries/technology/fifo/tech_fifo_sc.vhd
index 88fae12daf892f4b2c0d3480d3eca99b4375f643..4e95260d01e30f918700c8e5ebcd3a07ddadc44c 100644
--- a/libraries/technology/fifo/tech_fifo_sc.vhd
+++ b/libraries/technology/fifo/tech_fifo_sc.vhd
@@ -30,6 +30,7 @@ LIBRARY ip_stratixiv_fifo_lib;
LIBRARY ip_arria10_fifo_lib;
LIBRARY ip_arria10_e3sge3_fifo_lib;
LIBRARY ip_arria10_e1sg_fifo_lib;
+LIBRARY ip_arria10_e2sg_fifo_lib;
ENTITY tech_fifo_sc IS
GENERIC (
@@ -79,5 +80,11 @@ BEGIN
GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
END GENERATE;
+
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_fifo_sc
+ GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
+ PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
+ END GENERATE;
END ARCHITECTURE;
diff --git a/libraries/technology/flash/hdllib.cfg b/libraries/technology/flash/hdllib.cfg
index bbb6a855c1ddd20f6665c5c715b41fbca0fc94b4..815d88851c3e84e7370e503ef7424b3fbbb59327 100644
--- a/libraries/technology/flash/hdllib.cfg
+++ b/libraries/technology/flash/hdllib.cfg
@@ -8,6 +8,8 @@ hdl_lib_uses_synth = technology
ip_arria10_e3sge3_remote_update
ip_arria10_e1sg_asmi_parallel # modelsim crashes when asmi_parallel ip is used(segmentation violation)
ip_arria10_e1sg_remote_update
+ ip_arria10_e2sg_asmi_parallel
+ ip_arria10_e2sg_remote_update
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -18,6 +20,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_remote_update ip_arria10_e3sge3_remote_update_altera_remote_update_151
ip_arria10_e1sg_asmi_parallel ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_180
ip_arria10_e1sg_remote_update ip_arria10_e1sg_remote_update_altera_remote_update_180
+ ip_arria10_e2sg_asmi_parallel ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_194
+ ip_arria10_e2sg_remote_update ip_arria10_e1sg_remote_update_altera_remote_update_194
synth_files =
diff --git a/libraries/technology/flash/tech_flash_asmi_parallel.vhd b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
index a546364ef186e3b588e1b9e605a909d6f61b772b..a6ed43c72f3af49a401d59108126bbcd7dc64333 100644
--- a/libraries/technology/flash/tech_flash_asmi_parallel.vhd
+++ b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
@@ -89,4 +89,10 @@ BEGIN
PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write, reset, sce, en4b_addr);
END GENERATE;
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_asmi_parallel
+ PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write, reset, sce, en4b_addr);
+ END GENERATE;
+
+
END ARCHITECTURE;
diff --git a/libraries/technology/flash/tech_flash_component_pkg.vhd b/libraries/technology/flash/tech_flash_component_pkg.vhd
index 240ada1756f6301a1cfd328f0736c12638bdf918..5839bf349d3bc1e3b98b8cdcd257903470d6e4dd 100644
--- a/libraries/technology/flash/tech_flash_component_pkg.vhd
+++ b/libraries/technology/flash/tech_flash_component_pkg.vhd
@@ -195,6 +195,47 @@ PACKAGE tech_flash_component_pkg IS
);
end component ip_arria10_e1sg_remote_update;
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e2sg
+ -----------------------------------------------------------------------------
+
+ component ip_arria10_e2sg_asmi_parallel is
+ port (
+ addr : in std_logic_vector(31 downto 0);
+ clkin : in std_logic;
+ datain : in std_logic_vector(7 downto 0);
+ rden : in std_logic;
+ read : in std_logic;
+ sector_erase : in std_logic;
+ shift_bytes : in std_logic;
+ wren : in std_logic;
+ write : in std_logic;
+ busy : out std_logic;
+ data_valid : out std_logic;
+ dataout : out std_logic_vector(7 downto 0);
+ illegal_erase : out std_logic;
+ illegal_write : out std_logic;
+ reset : in std_logic;
+ sce : in std_logic_vector(2 downto 0);
+ en4b_addr : in std_logic
+ );
+ end component ip_arria10_e2sg_asmi_parallel;
+
+ component ip_arria10_e2sg_remote_update is
+ port (
+ clock : in std_logic;
+ data_in : in std_logic_vector(31 downto 0);
+ param : in std_logic_vector(2 downto 0);
+ read_param : in std_logic;
+ reconfig : in std_logic;
+ reset : in std_logic;
+ reset_timer : in std_logic;
+ write_param : in std_logic;
+ busy : out std_logic;
+ data_out : out std_logic_vector(31 downto 0)
+ );
+ end component ip_arria10_e2sg_remote_update;
+
function tech_flash_addr_w( technology: in integer ) return integer;
function tech_flash_data_w( technology: in integer ) return integer;
@@ -210,7 +251,7 @@ package body tech_flash_component_pkg is
if technology = c_tech_arria10 then
return 32;
end if;
- if technology = c_tech_arria10_e3sge3 or technology = c_tech_arria10_e1sg then
+ if technology = c_tech_arria10_e3sge3 or technology = c_tech_arria10_e1sg or technology = c_tech_arria10_e2sg then
return 32;
end if;
end;
@@ -223,7 +264,7 @@ package body tech_flash_component_pkg is
if technology = c_tech_arria10 then
return 32;
end if;
- if technology = c_tech_arria10_e3sge3 or technology = c_tech_arria10_e1sg then
+ if technology = c_tech_arria10_e3sge3 or technology = c_tech_arria10_e1sg or technology = c_tech_arria10_e2sg then
return 32;
end if;
end;
diff --git a/libraries/technology/flash/tech_flash_remote_update.vhd b/libraries/technology/flash/tech_flash_remote_update.vhd
index 8c54bb8882de34ac5f1ed5d1be9dbd2f57396f88..3933fc69e22d7c4e827400899b738448dfd72d2d 100644
--- a/libraries/technology/flash/tech_flash_remote_update.vhd
+++ b/libraries/technology/flash/tech_flash_remote_update.vhd
@@ -32,6 +32,7 @@ LIBRARY ip_stratixiv_flash_lib;
LIBRARY ip_arria10_remote_update_altera_remote_update_150;
LIBRARY ip_arria10_e3sge3_remote_update_altera_remote_update_151;
LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_180;
+LIBRARY ip_arria10_e2sg_remote_update_altera_remote_update_194;
ENTITY tech_flash_remote_update IS
GENERIC (
@@ -79,4 +80,9 @@ BEGIN
PORT MAP (clock, data_in, param, read_param, reconfig, reset, reset_timer, write_param, busy, data_out);
END GENERATE;
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_remote_update
+ PORT MAP (clock, data_in, param, read_param, reconfig, reset, reset_timer, write_param, busy, data_out);
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/fpga_temp_sens/hdllib.cfg b/libraries/technology/fpga_temp_sens/hdllib.cfg
index 97baab475173f09c03d28879b67dc3f1d4685518..c9708019d4bcbec28f2a4ee2847604941a5f08a1 100644
--- a/libraries/technology/fpga_temp_sens/hdllib.cfg
+++ b/libraries/technology/fpga_temp_sens/hdllib.cfg
@@ -1,12 +1,14 @@
hdl_lib_name = tech_fpga_temp_sens
hdl_library_clause_name = tech_fpga_temp_sens_lib
-hdl_lib_uses_synth = technology common ip_arria10_temp_sense ip_arria10_e3sge3_temp_sense ip_arria10_e1sg_temp_sense
+hdl_lib_uses_synth = technology common ip_arria10_temp_sense ip_arria10_e3sge3_temp_sense ip_arria10_e1sg_temp_sense
+ ip_arria10_e2sg_temp_sense
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_temp_sense ip_arria10_temp_sense_altera_temp_sense_150
ip_arria10_e3sge3_temp_sense ip_arria10_e3sge3_temp_sense_altera_temp_sense_151
ip_arria10_e1sg_temp_sense ip_arria10_e1sg_temp_sense_altera_temp_sense_180
+ ip_arria10_e2sg_temp_sense ip_arria10_e2sg_temp_sense_altera_temp_sense_194
synth_files =
tech_fpga_temp_sens_component_pkg.vhd
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
index 749310fa3d6bb0ad3dc51d1aaa1abd880551d96c..f9e6e9d018e362abf15b479cde2a71448d10905a 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
@@ -30,6 +30,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_temp_sense_altera_temp_sense_150;
LIBRARY ip_arria10_e3sge3_temp_sense_altera_temp_sense_151;
LIBRARY ip_arria10_e1sg_temp_sense_altera_temp_sense_180;
+LIBRARY ip_arria10_e2sg_temp_sense_altera_temp_sense_194;
ENTITY tech_fpga_temp_sens IS
@@ -78,4 +79,14 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_temp_sense
+ PORT MAP (
+ corectl => corectl, -- corectl.corectl
+ reset => reset, -- reset.reset
+ tempout => tempout, -- tempout.tempout
+ eoc => eoc -- eoc.eoc
+ );
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
index 9fa8feb814cb86a1aa5f0a645d0902023adb592f..aaeb4e4523af10f9600c40512d96a3ddd642e825 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
@@ -53,5 +53,14 @@ PACKAGE tech_fpga_temp_sens_component_pkg IS
);
END COMPONENT;
+ COMPONENT ip_arria10_e2sg_temp_sense IS
+ PORT (
+ corectl : IN STD_LOGIC := '0'; -- corectl.corectl
+ eoc : OUT STD_LOGIC; -- eoc.eoc
+ reset : IN STD_LOGIC := '0'; -- reset.reset
+ tempout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) -- tempout.tempout
+ );
+ END COMPONENT;
+
END tech_fpga_temp_sens_component_pkg;
diff --git a/libraries/technology/fpga_voltage_sens/hdllib.cfg b/libraries/technology/fpga_voltage_sens/hdllib.cfg
index a9c9d063c01f162f1d8a2bdb6406bfa6bcf7a68b..c43b39cf5c12d362b45b9adb8f895359e5f17661 100644
--- a/libraries/technology/fpga_voltage_sens/hdllib.cfg
+++ b/libraries/technology/fpga_voltage_sens/hdllib.cfg
@@ -1,12 +1,14 @@
hdl_lib_name = tech_fpga_voltage_sens
hdl_library_clause_name = tech_fpga_voltage_sens_lib
hdl_lib_uses_synth = technology common ip_arria10_voltage_sense ip_arria10_e3sge3_voltage_sense ip_arria10_e1sg_voltage_sense
+ ip_arria10_e1sg_voltage_sense
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_voltage_sense ip_arria10_voltage_sense_altera_voltage_sense_150
ip_arria10_e3sge3_voltage_sense ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151
ip_arria10_e1sg_voltage_sense ip_arria10_e1sg_voltage_sense_altera_voltage_sense_180
+ ip_arria10_e2sg_voltage_sense ip_arria10_e2sg_voltage_sense_altera_voltage_sense_194
synth_files =
tech_fpga_voltage_sens_component_pkg.vhd
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
index f16657aba07348b85c295e2878517ff53c47ca47..a409789620ceb0978bc10892db447ee3db5ff0ba 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_voltage_sense_altera_voltage_sense_150;
LIBRARY ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151;
LIBRARY ip_arria10_e1sg_voltage_sense_altera_voltage_sense_180;
+LIBRARY ip_arria10_esg_voltage_sense_altera_voltage_sense_180;
ENTITY tech_fpga_voltage_sens IS
@@ -113,4 +114,23 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_voltage_sense
+ PORT MAP (
+ clock_clk => clock_clk,
+ reset_sink_reset => reset_sink_reset,
+ controller_csr_address => controller_csr_address,
+ controller_csr_read => controller_csr_read,
+ controller_csr_write => controller_csr_write,
+ controller_csr_writedata => controller_csr_writedata,
+ controller_csr_readdata => controller_csr_readdata,
+ sample_store_csr_address => sample_store_csr_address,
+ sample_store_csr_read => sample_store_csr_read,
+ sample_store_csr_write => sample_store_csr_write,
+ sample_store_csr_writedata => sample_store_csr_writedata,
+ sample_store_csr_readdata => sample_store_csr_readdata,
+ sample_store_irq_irq => sample_store_irq_irq
+ );
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
index 586f694dca15b23e8143f2f8409777f6118e6f57..040ccb3aa9eda337ee12cab003863a49bf3e5dc3 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
@@ -80,5 +80,23 @@ PACKAGE tech_fpga_voltage_sens_component_pkg IS
);
END COMPONENT;
+ COMPONENT ip_arria10_e2sg_voltage_sense IS
+ PORT (
+ clock_clk : in STD_LOGIC := '0';
+ reset_sink_reset : in STD_LOGIC;
+ controller_csr_address : in STD_LOGIC := '0';
+ controller_csr_read : in STD_LOGIC := '0';
+ controller_csr_write : in STD_LOGIC := '0';
+ controller_csr_writedata : in STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
+ controller_csr_readdata : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
+ sample_store_csr_address : in STD_LOGIC_VECTOR(3 downto 0) := "0000";
+ sample_store_csr_read : in STD_LOGIC := '0';
+ sample_store_csr_write : in STD_LOGIC := '0';
+ sample_store_csr_writedata : in STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
+ sample_store_csr_readdata : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
+ sample_store_irq_irq : out STD_LOGIC
+ );
+ END COMPONENT;
+
END tech_fpga_voltage_sens_component_pkg;
diff --git a/libraries/technology/fractional_pll/hdllib.cfg b/libraries/technology/fractional_pll/hdllib.cfg
index 4814f9b5de2f475328906e2e8244a4a625d963f5..d4dcea39a9e91d98ff824827e80aa2c5983c8558 100644
--- a/libraries/technology/fractional_pll/hdllib.cfg
+++ b/libraries/technology/fractional_pll/hdllib.cfg
@@ -1,8 +1,10 @@
hdl_lib_name = tech_fractional_pll
hdl_library_clause_name = tech_fractional_pll_lib
hdl_lib_uses_synth = technology common
-hdl_lib_uses_ip = ip_arria10_fractional_pll_clk200 ip_arria10_e3sge3_fractional_pll_clk200 ip_arria10_e1sg_fractional_pll_clk200
- ip_arria10_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk125 ip_arria10_e1sg_fractional_pll_clk125
+hdl_lib_uses_ip = ip_arria10_fractional_pll_clk200 ip_arria10_e3sge3_fractional_pll_clk200
+ ip_arria10_e1sg_fractional_pll_clk200 ip_arria10_e2sg_fractional_pll_clk200
+ ip_arria10_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk125
+ ip_arria10_e1sg_fractional_pll_clk125 ip_arria10_e1sg_fractional_pll_clk125
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -12,6 +14,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151
ip_arria10_e1sg_fractional_pll_clk200 ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_180
ip_arria10_e1sg_fractional_pll_clk125 ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_180
+ ip_arria10_e2sg_fractional_pll_clk200 ip_arria10_e2sg_fractional_pll_clk200_altera_xcvr_fpll_a10_194
+ ip_arria10_e2sg_fractional_pll_clk125 ip_arria10_e2sg_fractional_pll_clk125_altera_xcvr_fpll_a10_194
synth_files =
tech_fractional_pll_component_pkg.vhd
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
index 287a6098d48ea5d2e847716cca7f7592a8824161..1234aff5b89da14bbf68870eb8f70f48e78caf2e 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151;
LIBRARY ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_180;
+LIBRARY ip_arria10_e2sg_fractional_pll_clk125_altera_xcvr_fpll_a10_194;
ENTITY tech_fractional_pll_clk125 IS
GENERIC (
@@ -91,4 +92,18 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_fractional_pll_clk125
+ PORT MAP (
+ outclk0 => c0, -- outclk0.clk
+ outclk1 => c1, -- outclk1.clk
+ outclk2 => c2, -- outclk2.clk
+ outclk3 => c3, -- outclk3.clk
+ pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
+ pll_locked => locked, -- pll_locked.pll_locked
+ pll_powerdown => areset, -- pll_powerdown.pll_powerdown
+ pll_refclk0 => inclk0 -- pll_refclk0.clk
+ );
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
index 4a986c4c47ed2d40b2cafb367bbeaa372e76a45e..5ad3783021cb9188d8592e766c07be0532fe68fd 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_fractional_pll_clk200_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151;
LIBRARY ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_180;
+LIBRARY ip_arria10_e2sg_fractional_pll_clk200_altera_xcvr_fpll_a10_194;
ENTITY tech_fractional_pll_clk200 IS
GENERIC (
@@ -87,5 +88,18 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_fractional_pll_clk200
+ PORT MAP (
+ outclk0 => c0, -- outclk0.clk
+ outclk1 => c1, -- outclk1.clk
+ outclk2 => c2, -- outclk2.clk
+ pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
+ pll_locked => locked, -- pll_locked.pll_locked
+ pll_powerdown => areset, -- pll_powerdown.pll_powerdown
+ pll_refclk0 => inclk0 -- pll_refclk0.clk
+ );
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd
index d1b5292366d92230113ebafba396acd58c5c828f..f711f12c62daa9214f9652c2f42517d1139b46e2 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd
@@ -118,6 +118,37 @@ PACKAGE tech_fractional_pll_component_pkg IS
pll_refclk0 : in std_logic := '0' -- pll_refclk0.clk
);
END COMPONENT;
-
+
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e2sg
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e2sg_fractional_pll_clk200 IS
+ PORT
+ (
+ outclk0 : out std_logic; -- outclk0.clk
+ outclk1 : out std_logic; -- outclk1.clk
+ outclk2 : out std_logic; -- outclk2.clk
+ pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
+ pll_locked : out std_logic; -- pll_locked.pll_locked
+ pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
+ pll_refclk0 : in std_logic := '0' -- pll_refclk0.clk
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_fractional_pll_clk125 IS
+ PORT
+ (
+ outclk0 : out std_logic; -- outclk0.clk
+ outclk1 : out std_logic; -- outclk1.clk
+ outclk2 : out std_logic; -- outclk2.clk
+ outclk3 : out std_logic; -- outclk2.clk
+ pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
+ pll_locked : out std_logic; -- pll_locked.pll_locked
+ pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
+ pll_refclk0 : in std_logic := '0' -- pll_refclk0.clk
+ );
+ END COMPONENT;
+
END tech_fractional_pll_component_pkg;
diff --git a/libraries/technology/iobuf/hdllib.cfg b/libraries/technology/iobuf/hdllib.cfg
index c6b41564dead3241c71e6446f6dcc5bccde24b40..90c8611b009eb63a3bb5749f9fd75afeee2ecddc 100644
--- a/libraries/technology/iobuf/hdllib.cfg
+++ b/libraries/technology/iobuf/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = tech_iobuf
hdl_library_clause_name = tech_iobuf_lib
-hdl_lib_uses_synth = technology ip_stratixiv_ddio ip_arria10_ddio ip_arria10_e3sge3_ddio ip_arria10_e1sg_ddio
+hdl_lib_uses_synth = technology ip_stratixiv_ddio ip_arria10_ddio ip_arria10_e3sge3_ddio ip_arria10_e1sg_ddio ip_arria10_e2sg_ddio
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -8,6 +8,7 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_ddio ip_arria10_ddio_lib
ip_arria10_e3sge3_ddio ip_arria10_e3sge3_ddio_lib
ip_arria10_e1sg_ddio ip_arria10_e1sg_ddio_lib
+ ip_arria10_e2sg_ddio ip_arria10_e2sg_ddio_lib
synth_files =
tech_iobuf_component_pkg.vhd
diff --git a/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd b/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
index 115d9789fdc7a051d52c1c773322bb4dc84126e6..77849a784102d1e407eda20e7aa7764bb379255a 100644
--- a/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
@@ -157,4 +157,36 @@ PACKAGE tech_iobuf_component_pkg IS
);
END COMPONENT;
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e2sg
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e2sg_ddio_in IS
+ GENERIC (
+ g_width : NATURAL := 1
+ );
+ PORT (
+ in_dat : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ in_clk : IN STD_LOGIC;
+ in_clk_en : IN STD_LOGIC := '1'; -- Not Connected
+ rst : IN STD_LOGIC := '0';
+ out_dat_hi : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ out_dat_lo : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_ddio_out IS
+ GENERIC(
+ g_width : NATURAL := 1
+ );
+ PORT (
+ rst : IN STD_LOGIC := '0';
+ in_clk : IN STD_LOGIC;
+ in_clk_en : IN STD_LOGIC := '1'; -- Not Connected
+ in_dat_hi : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ in_dat_lo : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ out_dat : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
END tech_iobuf_component_pkg;
diff --git a/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd b/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
index 92e49a5c0bc12e222bae4bbfb69a87f419852dcd..75a38114590dedfdb33605d18b2a337fed584986 100644
--- a/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
@@ -30,6 +30,7 @@ LIBRARY ip_stratixiv_ddio_lib;
LIBRARY ip_arria10_ddio_lib;
LIBRARY ip_arria10_e3sge3_ddio_lib;
LIBRARY ip_arria10_e1sg_ddio_lib;
+LIBRARY ip_arria10_e2sg_ddio_lib;
ENTITY tech_iobuf_ddio_in IS
GENERIC (
@@ -75,4 +76,10 @@ BEGIN
PORT MAP (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
END GENERATE;
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_ddio_in
+ GENERIC MAP (g_width)
+ PORT MAP (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd b/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
index 2c4fe9e5812f6039635d46048d6183c04ec3d746..1547d4bd2c1386819e4209b9f4e8869f515fc6e4 100644
--- a/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
@@ -30,6 +30,7 @@ LIBRARY ip_stratixiv_ddio_lib;
LIBRARY ip_arria10_ddio_lib;
LIBRARY ip_arria10_e3sge3_ddio_lib;
LIBRARY ip_arria10_e1sg_ddio_lib;
+LIBRARY ip_arria10_e2sg_ddio_lib;
ENTITY tech_iobuf_ddio_out IS
GENERIC (
@@ -74,5 +75,11 @@ BEGIN
GENERIC MAP (g_width)
PORT MAP (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
END GENERATE;
-
+
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_ddio_out
+ GENERIC MAP (g_width)
+ PORT MAP (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/ip_arria10_e2sg/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/clkbuf_global/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1f8b03270d5107bf7f50aa5701219c59c3fcfa87
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/clkbuf_global/compile_ip.tcl
@@ -0,0 +1,34 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_clkbuf_global/sim"
+
+ vcom "$IP_DIR/ip_arria10_e2sg_clkbuf_global.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/clkbuf_global/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..132a96bf48e9042ff866aac9261f6dcfbd2cfb80
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/clkbuf_global/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_clkbuf_global
+hdl_library_clause_name = ip_arria10_e2sg_clkbuf_global_altclkctrl_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altclkctrl_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/clkbuf_global/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_clkbuf_global/ip_arria10_e2sg_clkbuf_global.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_clkbuf_global.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/clkbuf_global/ip_arria10_e2sg_clkbuf_global.qsys b/libraries/technology/ip_arria10_e2sg/clkbuf_global/ip_arria10_e2sg_clkbuf_global.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..d9cf6ed47ed4e9f8a5962c10c1081746b52864fb
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/clkbuf_global/ip_arria10_e2sg_clkbuf_global.qsys
@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_clkbuf_global">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element altclkctrl_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="altclkctrl_input"
+ internal="altclkctrl_0.altclkctrl_input"
+ type="conduit"
+ dir="end">
+ <port name="inclk" internal="inclk" />
+ </interface>
+ <interface
+ name="altclkctrl_output"
+ internal="altclkctrl_0.altclkctrl_output"
+ type="conduit"
+ dir="end">
+ <port name="outclk" internal="outclk" />
+ </interface>
+ <module
+ name="altclkctrl_0"
+ kind="altclkctrl"
+ version="19.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CLOCK_TYPE" value="1" />
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="ENA_REGISTER_MODE" value="1" />
+ <parameter name="GUI_USE_ENA" value="false" />
+ <parameter name="NUMBER_OF_CLOCKS" value="1" />
+ <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/complex_mult/README.txt b/libraries/technology/ip_arria10_e2sg/complex_mult/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..c9a33bbdfc0710640b0f4e967376ce8a5627e40e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/complex_mult/README.txt
@@ -0,0 +1,55 @@
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/complex_mult
+
+1) Porting
+2) IP component
+3) Compilation, simulation and verification
+4) Synthesis
+5) Remarks
+
+
+1) Porting
+
+The complex_mult IP was ported manually from Quartus v11.1 for Stratix IV to Quartus 15.0 for Arria10 by creating it in Qsys using
+the same parameter settings.
+
+
+2) IP component
+
+The generated IP is not kept in SVN, only the Qsys source file:
+
+ ip_arria10_complex_mult.qsys
+
+Therefore first the IP needs to be generated using:
+
+ ./generate_ip.sh
+
+
+3) Compilation, simulation and verification
+
+The generated IP also contains a msim_setup.tcl file that was used to manually create:
+
+ compile_ip.tcl
+
+This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code.
+
+
+4) Synthesis
+
+No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
+
+ ip_arria10_complex_mult.qip
+
+is included in the hdllib.cfg and contains what is needed to synthesize the IP.
+
+
+5) Remarks
+
+a) Use generated IP specific library clause name
+
+ The generated ip_arria10_<lib_name>.vhd uses an IP specific library name. Therefore the hdllib.cfg uses the IP
+ specific library as library clause name to make it known:
+
+ hdl_lib_name = ip_arria10_<lib_name>
+ hdl_library_clause_name = ip_arria10_<lib_name>_<ip_specific>
+
+
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c3522eac8615ad4fa5f72cec6cfa111a5668f7d5
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult/sim"
+vmap altmult_complex_180 ./work/
+ vlog "$IP_DIR/../altmult_complex_180/synth/ip_arria10_e2sg_complex_mult_altmult_complex_180_nkpx3mi.v" -work altmult_complex_180
+ #vlog "$IP_DIR/ip_arria10_e2sg_complex_mult_bb.v"
diff --git a/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..5fe17d7cf2d9b78a2c21fc94f9a5f9e1e99a9b31
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_complex_mult
+hdl_library_clause_name = ip_arria10_e2sg_complex_mult_altmult_complex_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_complex_mult/ip_arria10_e2sg_complex_mult.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_complex_mult.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/complex_mult/ip_arria10_e2sg_complex_mult.qsys b/libraries/technology/ip_arria10_e2sg/complex_mult/ip_arria10_e2sg_complex_mult.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..1b6592957af13fbd6f4fce39205853674829e81f
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/complex_mult/ip_arria10_e2sg_complex_mult.qsys
@@ -0,0 +1,122 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_complex_mult">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element altmult_complex_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="aclr" internal="altmult_complex_0.aclr" type="reset" dir="end">
+ <port name="aclr" internal="aclr" />
+ </interface>
+ <interface
+ name="clock"
+ internal="altmult_complex_0.clock"
+ type="clock"
+ dir="end">
+ <port name="clock" internal="clock" />
+ </interface>
+ <interface name="complex_input" internal="altmult_complex_0.complex_input" />
+ <interface name="complex_output" internal="altmult_complex_0.complex_output" />
+ <interface
+ name="dataa_imag"
+ internal="altmult_complex_0.dataa_imag"
+ type="conduit"
+ dir="end">
+ <port name="dataa_imag" internal="dataa_imag" />
+ </interface>
+ <interface
+ name="dataa_real"
+ internal="altmult_complex_0.dataa_real"
+ type="conduit"
+ dir="end">
+ <port name="dataa_real" internal="dataa_real" />
+ </interface>
+ <interface
+ name="datab_imag"
+ internal="altmult_complex_0.datab_imag"
+ type="conduit"
+ dir="end">
+ <port name="datab_imag" internal="datab_imag" />
+ </interface>
+ <interface
+ name="datab_real"
+ internal="altmult_complex_0.datab_real"
+ type="conduit"
+ dir="end">
+ <port name="datab_real" internal="datab_real" />
+ </interface>
+ <interface name="ena" internal="altmult_complex_0.ena" type="conduit" dir="end">
+ <port name="ena" internal="ena" />
+ </interface>
+ <interface
+ name="result_imag"
+ internal="altmult_complex_0.result_imag"
+ type="conduit"
+ dir="end">
+ <port name="result_imag" internal="result_imag" />
+ </interface>
+ <interface
+ name="result_real"
+ internal="altmult_complex_0.result_real"
+ type="conduit"
+ dir="end">
+ <port name="result_real" internal="result_real" />
+ </interface>
+ <module
+ name="altmult_complex_0"
+ kind="altmult_complex"
+ version="19.1.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_CLEAR_TYPE" value="ACLR" />
+ <parameter name="GUI_DYNAMIC_COMPLEX" value="false" />
+ <parameter name="GUI_USE_CLKEN" value="true" />
+ <parameter name="IMPLEMENTATION_STYLE" value="AUTO" />
+ <parameter name="PIPELINE" value="3" />
+ <parameter name="REPRESENTATION_A" value="1" />
+ <parameter name="REPRESENTATION_B" value="1" />
+ <parameter name="WIDTH_A" value="18" />
+ <parameter name="WIDTH_B" value="18" />
+ <parameter name="WIDTH_RESULT" value="36" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/README.txt b/libraries/technology/ip_arria10_e2sg/ddio/README.txt
new file mode 100755
index 0000000000000000000000000000000000000000..1823e822ffac72fd6dfccb16917ab9972bed2a75
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ddio/README.txt
@@ -0,0 +1,73 @@
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddio
+
+Contents:
+
+1) DDIO components
+2) Arria10 IP
+3) Synthesis trials
+4) Issues
+
+
+1) DDIO components:
+ ip_arria10_ddio_in.vhd = Double Date Rate input
+ ip_arria10_ddio_out.vhd = Double Date Rate output
+
+
+2) Arria10 IP
+
+ The StratixIV IP uses altddio_in and altddio_out. First a Megawizard file for this StratixIV IP was made using the settings that
+ were used in common_ddio_in.vhd and common_ddio_out.vhd. This Megawizard IP file was then opened in Quartus to be able to let
+ Quartus 14 convert them using the altera_gpio component for Arria10.
+
+ The altera_gpio component is not part of the default Quartus 14.0a10 tool libraries, but instead it is created by Qsys together
+ with the IP. This makes that the altera_gpio can not easily be used in simulation and synthesis like was possible with altera_mf
+ in for Stratix IV (Quartus 11.1).
+
+ The ddio_in component is used by the PPSH and the ddio_out component is used by the ADUH. In both cases the g_width=1.
+ The Arria10 IP can be generated using a fixed width of 1. Therefore the width was set to 1 in the conversion from MegaWizard
+ to Qsys and the qsys files are stored as:
+
+ ip_arria10_ddio_in_1.qsys
+ ip_arria10_ddio_out_1.qsys
+
+ If the application would need a wider port then it can achieve this by instantiating the IP multiple times. This approach
+ avoids having to generate DDIO IP for every possible width. An alternative would be:
+ - to generate IP for e.g. width=16 and assuming that that is sufficient for all applications. Any application that uses less
+ width then leaves these IO unconnected so that the unused IO will get optimized away by synthesis.
+ - create the IP when it is needed, this scheme is more difficult to manage but is something to consider for the future.
+
+ The IP needs to be generated with:
+
+ ./generate_ip.sh
+
+ to create the simulation and synthesis files, because these are initially not kept in SVN.
+
+
+3) Synthesis trials
+
+ The Quartus project:
+
+ quartus/ddio.qpf
+
+ was used to verify that the DDIO IP actually synthesise to the appropriate FPGA resources.
+ Use the Quartus GUI to manually select a top level component for synthesis e.g. by right clicking the entity vhd file
+ in the file tab of the Quartus project navigator window.
+ Then check the resource usage in the synthesis and fitter reports.
+
+
+4) Issues
+
+a) Simulation model does not work (for Quartus 14.1, not tried for Quartus 15.0)
+
+ The simulation model for the DDIO does not compile ok because a din port is missing in the ddio_out en a dout port is
+ missing in the ddio_in. Adding this ports manualy does work for compile, but when the component is loaded as a simulation
+ then Modelsim reports some internal error on the IP. The compile also does not work when using 'do msim_setup.tcl', so
+ there is something wrong with the DDIO simulation model. The synthesis of the DDIO IP using ddio.qpf does work.
+
+ The work around is not not use the simulation model, but instead use a behavioral simulation model for the IP:
+ sim/ip_arria10_ddio_in_1.vhd
+ sim/ip_arria10_ddio_out_1.vhd
+ sim/tb_ip_arria10_ddio_1.vhd = self checking tb for ip_arria10_ddio_in_1 -> ip_arria10_ddio_out_1
+
+ The selection between the IP model or the behavioral model is made in the compile_ip.tcl script.
+
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..9dc7dea90223fbe552033843df38ead3707ef6c7
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl
@@ -0,0 +1,69 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+set IPMODEL "SIM";
+#set IPMODEL "PHY";
+
+if {$IPMODEL=="PHY"} {
+ # OUTDATED AND NOT USED!!
+ # This file is based on Qsys-generated file msim_setup.tcl.
+ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddio_in_1/sim"
+
+ #vlib ./work/ ;# Assume library work already exists
+ vmap ip_arria10_ddio_in_1_altera_gpio_core_180 ./work/
+ vmap ip_arria10_ddio_in_1_altera_gpio_180 ./work/
+
+ vlog -sv "$IP_DIR/../altera_gpio_core_180/sim/mentor/altera_gpio.sv" -work ip_arria10_ddio_in_1_altera_gpio_core_180
+
+ vcom "$IP_DIR/../altera_gpio_180/sim/ip_arria10_ddio_in_1_altera_gpio_180_umwov7y.vhd" -work ip_arria10_ddio_in_1_altera_gpio_180
+ vcom "$IP_DIR/ip_arria10_ddio_in_1.vhd"
+
+
+ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddio_out_1/sim"
+
+ #vlib ./work/ ;# Assume library work already exists
+ vmap ip_arria10_ddio_out_1_altera_gpio_core_180 ./work/
+ vmap ip_arria10_ddio_out_1_altera_gpio_180 ./work/
+
+ vlog -sv "$IP_DIR/../altera_gpio_core_180/sim/mentor/altera_gpio.sv" -work ip_arria10_ddio_out_1_altera_gpio_core_180
+
+ vcom "$IP_DIR/../altera_gpio_180/sim/ip_arria10_ddio_out_1_altera_gpio_180_c3jcq7i.vhd" -work ip_arria10_ddio_out_1_altera_gpio_180
+ vcom "$IP_DIR/ip_arria10_ddio_out_1.vhd"
+
+} else {
+
+ # This file uses a behavioral model because the PHY model does not compile OK, see README.txt.
+ set SIM_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e2sg/ddio/sim/"
+
+ vcom "$SIM_DIR/ip_arria10_e2sg_ddio_in_1.vhd"
+ vcom "$SIM_DIR/ip_arria10_e2sg_ddio_out_1.vhd"
+ vcom "$SIM_DIR/tb_ip_arria10_e2sg_ddio_1.vhd"
+
+}
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/ddio/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..64f68201fe1d7c5c5db2ff0b4ac0f21c355fd76b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ddio/hdllib.cfg
@@ -0,0 +1,28 @@
+hdl_lib_name = ip_arria10_e2sg_ddio
+hdl_library_clause_name = ip_arria10_e2sg_ddio_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+ ip_arria10_e2sg_ddio_in.vhd
+ ip_arria10_e2sg_ddio_out.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddio_in_1/ip_arria10_e2sg_ddio_in_1.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddio_out_1/ip_arria10_e2sg_ddio_out_1.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_ddio_in_1.qsys
+ ip_arria10_e2sg_ddio_out_1.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in.vhd b/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b088417ccff51d9f1a44da59ff564fe2abf92727
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in.vhd
@@ -0,0 +1,69 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Wrapper for ip_arria10_e2sg_ddio_in_1 to support g_width >= 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY ip_arria10_e2sg_ddio_in IS
+ GENERIC (
+ g_width : NATURAL := 1
+ );
+ PORT (
+ in_dat : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ in_clk : IN STD_LOGIC;
+ in_clk_en : IN STD_LOGIC := '1'; -- Not Connected
+ rst : IN STD_LOGIC := '0';
+ out_dat_hi : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ out_dat_lo : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+ );
+END ip_arria10_e2sg_ddio_in;
+
+
+ARCHITECTURE str OF ip_arria10_e2sg_ddio_in IS
+
+ component ip_arria10_e2sg_ddio_in_1 is
+ port (
+ datain : in std_logic_vector(0 downto 0) := (others => '0'); -- pad_in.export
+ inclock : in std_logic := '0'; -- ck.export
+ aclr : in std_logic := '0'; -- aclr.export
+ dataout_h : out std_logic_vector(0 downto 0); -- dataout_h.fragment
+ dataout_l : out std_logic_vector(0 downto 0) -- dataout_l.fragment
+ );
+ end component;
+
+BEGIN
+
+ gen_w : FOR I IN g_width-1 DOWNTO 0 GENERATE
+
+ u_ip_arria10_e2sg_ddio_in_1 : ip_arria10_e2sg_ddio_in_1
+ PORT MAP (
+ datain => in_dat(I DOWNTO I),
+ inclock => in_clk,
+ aclr => rst,
+ dataout_h => out_dat_hi(I DOWNTO I),
+ dataout_l => out_dat_lo(I DOWNTO I)
+ );
+
+ END GENERATE;
+
+END str;
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in_1.qsys b/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in_1.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..074f66f1b1a64a537ff7453740188cfc457a07b7
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in_1.qsys
@@ -0,0 +1,108 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_ddio_in_1">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element ip_arria10_ddio_in_1
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="aclr"
+ internal="ip_arria10_ddio_in_1.aclr"
+ type="conduit"
+ dir="end">
+ <port name="aclr" internal="aclr" />
+ </interface>
+ <interface name="ck" internal="ip_arria10_ddio_in_1.ck" type="conduit" dir="end">
+ <port name="inclock" internal="inclock" />
+ </interface>
+ <interface
+ name="dataout_h"
+ internal="ip_arria10_ddio_in_1.dataout_h"
+ type="conduit"
+ dir="end">
+ <port name="dataout_h" internal="dataout_h" />
+ </interface>
+ <interface
+ name="dataout_l"
+ internal="ip_arria10_ddio_in_1.dataout_l"
+ type="conduit"
+ dir="end">
+ <port name="dataout_l" internal="dataout_l" />
+ </interface>
+ <interface name="din" internal="ip_arria10_ddio_in_1.din" />
+ <interface name="dout" internal="ip_arria10_ddio_in_1.dout" />
+ <interface
+ name="pad_in"
+ internal="ip_arria10_ddio_in_1.pad_in"
+ type="conduit"
+ dir="end">
+ <port name="datain" internal="datain" />
+ </interface>
+ <interface name="pad_out" internal="ip_arria10_ddio_in_1.pad_out" />
+ <module
+ name="ip_arria10_ddio_in_1"
+ kind="altera_gpio"
+ version="19.3.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="EXT_DRIVER_PARAM" value="false" />
+ <parameter name="GENERATE_SDC_FILE" value="false" />
+ <parameter name="IP_MIGRATE_PORT_MAP_FILE">altddio_in_port_map.csv</parameter>
+ <parameter name="PIN_TYPE_GUI" value="Input" />
+ <parameter name="SIZE" value="1" />
+ <parameter name="SYS_INFO_DEVICE" value="10AX115U3F45E2SG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_areset_mode" value="Clear" />
+ <parameter name="gui_bus_hold" value="false" />
+ <parameter name="gui_diff_buff" value="false" />
+ <parameter name="gui_enable_cke" value="false" />
+ <parameter name="gui_enable_migratable_port_names" value="true" />
+ <parameter name="gui_enable_termination_ports" value="false" />
+ <parameter name="gui_hr_logic" value="false" />
+ <parameter name="gui_io_reg_mode" value="DDIO" />
+ <parameter name="gui_open_drain" value="false" />
+ <parameter name="gui_pseudo_diff" value="false" />
+ <parameter name="gui_separate_io_clks" value="false" />
+ <parameter name="gui_sreset_mode" value="None" />
+ <parameter name="gui_use_oe" value="false" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_out.vhd b/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_out.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..fb83b5b2bf875bbf614af2f81bb9b83efd3c1b7b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_out.vhd
@@ -0,0 +1,67 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Wrapper for ip_arria10_e2sg_ddio_out_1 to support g_width >= 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY ip_arria10_e2sg_ddio_out IS
+ GENERIC(
+ g_width : NATURAL := 1
+ );
+ PORT (
+ rst : IN STD_LOGIC := '0';
+ in_clk : IN STD_LOGIC;
+ in_clk_en : IN STD_LOGIC := '1'; -- Not Connected
+ in_dat_hi : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ in_dat_lo : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ out_dat : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+ );
+END ip_arria10_e2sg_ddio_out;
+
+
+ARCHITECTURE str OF ip_arria10_e2sg_ddio_out IS
+
+ component ip_arria10_e2sg_ddio_out_1 is
+ port (
+ dataout : out std_logic_vector(0 downto 0); -- pad_out.export
+ outclock : in std_logic := '0'; -- ck.export
+ aclr : in std_logic := '0'; -- aclr.export
+ datain_h : in std_logic_vector(0 downto 0) := (others => '0'); -- datain_h.fragment
+ datain_l : in std_logic_vector(0 downto 0) := (others => '0') -- datain_l.fragment
+ );
+ end component;
+
+BEGIN
+
+ gen_w : FOR I IN g_width-1 DOWNTO 0 GENERATE
+ u_ip_arria10_e2sg_ddio_out_1 : ip_arria10_e2sg_ddio_out_1
+ PORT MAP (
+ dataout => out_dat(I DOWNTO I),
+ outclock => in_clk,
+ aclr => rst,
+ datain_h => in_dat_hi(I DOWNTO I),
+ datain_l => in_dat_lo(I DOWNTO I)
+ );
+ END GENERATE;
+
+END str;
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_out_1.qsys b/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_out_1.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..f7a5da58c57cc124a6fcfc9520d8d901f270f0d1
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_out_1.qsys
@@ -0,0 +1,110 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_ddio_out_1">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element ip_arria10_ddio_out_1
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="aclr"
+ internal="ip_arria10_ddio_out_1.aclr"
+ type="conduit"
+ dir="end">
+ <port name="aclr" internal="aclr" />
+ </interface>
+ <interface
+ name="ck"
+ internal="ip_arria10_ddio_out_1.ck"
+ type="conduit"
+ dir="end">
+ <port name="outclock" internal="outclock" />
+ </interface>
+ <interface
+ name="datain_h"
+ internal="ip_arria10_ddio_out_1.datain_h"
+ type="conduit"
+ dir="end">
+ <port name="datain_h" internal="datain_h" />
+ </interface>
+ <interface
+ name="datain_l"
+ internal="ip_arria10_ddio_out_1.datain_l"
+ type="conduit"
+ dir="end">
+ <port name="datain_l" internal="datain_l" />
+ </interface>
+ <interface name="din" internal="ip_arria10_ddio_out_1.din" />
+ <interface
+ name="pad_out"
+ internal="ip_arria10_ddio_out_1.pad_out"
+ type="conduit"
+ dir="end">
+ <port name="dataout" internal="dataout" />
+ </interface>
+ <module
+ name="ip_arria10_ddio_out_1"
+ kind="altera_gpio"
+ version="19.3.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="EXT_DRIVER_PARAM" value="false" />
+ <parameter name="GENERATE_SDC_FILE" value="false" />
+ <parameter name="IP_MIGRATE_PORT_MAP_FILE">altddio_out_port_map.csv</parameter>
+ <parameter name="PIN_TYPE_GUI" value="Output" />
+ <parameter name="SIZE" value="1" />
+ <parameter name="SYS_INFO_DEVICE" value="10AX115U3F45E2SG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_areset_mode" value="Clear" />
+ <parameter name="gui_bus_hold" value="false" />
+ <parameter name="gui_diff_buff" value="false" />
+ <parameter name="gui_enable_cke" value="false" />
+ <parameter name="gui_enable_migratable_port_names" value="true" />
+ <parameter name="gui_enable_termination_ports" value="false" />
+ <parameter name="gui_hr_logic" value="false" />
+ <parameter name="gui_io_reg_mode" value="DDIO" />
+ <parameter name="gui_open_drain" value="false" />
+ <parameter name="gui_pseudo_diff" value="false" />
+ <parameter name="gui_separate_io_clks" value="false" />
+ <parameter name="gui_sreset_mode" value="None" />
+ <parameter name="gui_use_oe" value="false" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e1sg_ddio_in_1.vhd b/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e1sg_ddio_in_1.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7a9f6aae7ab433162bc1aff638541f44cbeacb27
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e1sg_ddio_in_1.vhd
@@ -0,0 +1,65 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Simulation model for DDIO in
+-- Description:
+-- The double data rate datain samples that arrive at time series t0, t1, t2,
+-- ... get output with samples t0, t2, ... in dataout_l and samples t1, t3,
+-- ... in dataout_h. Hence dataout = dataout_h & dataout_l contains the
+-- time series samples in little endian format with the first sample in the
+-- LSpart as shown in the timing diagram:
+-- _ _ _ _
+-- inclock | |_| |_| |_| |_
+-- datain 0 1 2 3 4 5 6 7
+-- in_dat_r 1 3 5
+-- in_dat_f 0 2 4
+-- dataout_h 1 3 5
+-- dataout_l 0 2 4
+--
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY ip_arria10_e2sg_ddio_in_1 IS
+ PORT (
+ datain : IN STD_LOGIC_VECTOR(0 downto 0) := (others => '0');
+ inclock : IN STD_LOGIC := '0';
+ aclr : IN STD_LOGIC := '0';
+ dataout_h : OUT STD_LOGIC_VECTOR(0 downto 0);
+ dataout_l : OUT STD_LOGIC_VECTOR(0 downto 0)
+ );
+END ip_arria10_e2sg_ddio_in_1;
+
+
+ARCHITECTURE beh OF ip_arria10_e2sg_ddio_in_1 IS
+
+ SIGNAL in_dat_r : STD_LOGIC;
+ SIGNAL in_dat_f : STD_LOGIC;
+
+BEGIN
+
+ in_dat_r <= datain(0) WHEN rising_edge(inclock);
+ in_dat_f <= datain(0) WHEN falling_edge(inclock);
+
+ dataout_h <= (OTHERS=>in_dat_r);
+ dataout_l <= (OTHERS=>in_dat_f) WHEN rising_edge(inclock);
+
+END beh;
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e1sg_ddio_out_1.vhd b/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e1sg_ddio_out_1.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..780e967d4a912ef8d3622f4202f61e71bd12d1d1
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e1sg_ddio_out_1.vhd
@@ -0,0 +1,59 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Simulation model for DDIO out
+-- Description:
+-- This function is the inverse of DDIO in as described in ip_arria10_e2sg_ddio_in_1.
+-- The timing diagram:
+-- _ _ _ _ _
+-- outclock | |_| |_| |_| |_| |_
+-- datain_h 1 3 5
+-- datain_l 0 2 4
+-- dataout @ r 1 3 5
+-- dataout @ f 0 2 4
+-- dataout 0 1 2 3 4 5 6 7
+--
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY ip_arria10_e2sg_ddio_out_1 IS
+ PORT (
+ dataout : OUT STD_LOGIC_VECTOR(0 downto 0);
+ outclock : IN STD_LOGIC := '0';
+ aclr : IN STD_LOGIC := '0';
+ datain_h : IN STD_LOGIC_VECTOR(0 downto 0) := (others=>'0');
+ datain_l : IN STD_LOGIC_VECTOR(0 downto 0) := (others=>'0')
+ );
+END ip_arria10_e2sg_ddio_out_1;
+
+
+ARCHITECTURE beh OF ip_arria10_e2sg_ddio_out_1 IS
+
+ SIGNAL out_dat_r : STD_LOGIC;
+ SIGNAL out_dat_f : STD_LOGIC;
+
+BEGIN
+
+ dataout <= datain_l WHEN falling_edge(outclock) ELSE
+ datain_h WHEN rising_edge(outclock);
+
+END beh;
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd b/libraries/technology/ip_arria10_e2sg/ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e944f9363737c339a0441bb1efcefdaa7e7bafb8
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd
@@ -0,0 +1,126 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Test bench for the DDIO in and out simulation models
+-- Description:
+-- _ _ _ _
+-- inclock | |_| |_| |_| |_
+-- datain 0 1 2 3 4 5 6 7
+-- data_h 1 3 5
+-- data_l 0 2 4
+-- dataout 0 1 2 3 4 5 6 7
+--
+-- Usage:
+-- The tb is self checking (p_verify) and self stopping (tb_end)
+--
+-- . Load the simulation by right mouse selecting the entity in library work
+-- > as 3
+-- > run -a
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY tb_ip_arria10_e2sg_ddio_1 IS
+END tb_ip_arria10_e2sg_ddio_1;
+
+
+ARCHITECTURE tb OF tb_ip_arria10_e2sg_ddio_1 IS
+
+ CONSTANT c_clk_period : TIME := 10 ns;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL clk : STD_LOGIC := '1';
+ SIGNAL in_dat : STD_LOGIC;
+ SIGNAL in_data : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL data_h : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL data_l : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL out_data : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL out_dat : STD_LOGIC;
+ SIGNAL out_dat_exp : STD_LOGIC;
+
+BEGIN
+
+ tb_end <= '0', '1' AFTER 100*c_clk_period;
+
+ clk <= NOT clk OR tb_end AFTER c_clk_period/2;
+
+ p_in : PROCESS
+ BEGIN
+ -- 0
+ in_dat <= '0';
+ WAIT UNTIL falling_edge(clk);
+ in_dat <= '0';
+ WAIT UNTIL rising_edge(clk);
+ -- 1
+ in_dat <= '0';
+ WAIT UNTIL falling_edge(clk);
+ in_dat <= '1';
+ WAIT UNTIL rising_edge(clk);
+ -- 2
+ in_dat <= '1';
+ WAIT UNTIL falling_edge(clk);
+ in_dat <= '0';
+ WAIT UNTIL rising_edge(clk);
+ -- 3
+ in_dat <= '1';
+ WAIT UNTIL falling_edge(clk);
+ in_dat <= '1';
+ WAIT UNTIL rising_edge(clk);
+ -- 2
+ in_dat <= '1';
+ WAIT UNTIL falling_edge(clk);
+ in_dat <= '0';
+ WAIT UNTIL rising_edge(clk);
+ END PROCESS;
+
+ in_data(0) <= in_dat;
+
+ u_ddio_in : ENTITY work.ip_arria10_e2sg_ddio_in_1
+ PORT MAP (
+ datain => in_data,
+ inclock => clk,
+ dataout_h => data_h,
+ dataout_l => data_l
+ );
+
+ u_ddio_out : ENTITY work.ip_arria10_e2sg_ddio_out_1
+ PORT MAP (
+ dataout => out_data,
+ outclock => clk,
+ datain_h => data_h,
+ datain_l => data_l
+ );
+
+ out_dat <= out_data(0);
+
+ out_dat_exp <= TRANSPORT in_dat AFTER c_clk_period*1.5 + 1 ps;
+
+ p_verify : PROCESS(clk)
+ BEGIN
+ IF falling_edge(clk) THEN
+ ASSERT out_dat=out_dat_exp REPORT "tb_ip_arria10_e2sg_ddio_1: Error, unexpeced data at falling edge";
+ END IF;
+ IF rising_edge(clk) THEN
+ ASSERT out_dat=out_dat_exp REPORT "tb_ip_arria10_e2sg_ddio_1: Error, unexpeced data at rising edge";
+ END IF;
+ END PROCESS;
+
+END tb;
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d88b025be7ce9f6f9b057c2d7e4d564d18ab0815
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/compile_ip.tcl
@@ -0,0 +1,34 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+
+ vcom "$IP_DIR/ip_arria10_e2sg_ddr4_8g_1600.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/copy_hex_files.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..8f7f7b97ecd1d4a229ba2a836252fd4a84a9408a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/copy_hex_files.tcl
@@ -0,0 +1,33 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+
+# Copy ROM/RAM files to simulation directory
+if {[file isdirectory $IP_DIR]} {
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_151_4thorvi_seq_cal_sim.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_151_4thorvi_seq_cal_synth.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_151_4thorvi_seq_params_sim.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_151_4thorvi_seq_params_synth.hex ./
+}
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..27316bba4be0b2742ec1fd35669bbf8c0c09aad6
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg
@@ -0,0 +1,25 @@
+hdl_lib_name = ip_arria10_e2sg_ddr4_8g_1600
+hdl_library_clause_name = ip_arria10_e2sg_ddr4_8g_1600_altera_emif_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_merlin_master_translator_180 ip_arria10_e2sg_altera_emif_cal_slave_nf_180 ip_arria10_e2sg_altera_avalon_onchip_memory2_180 ip_arria10_e2sg_altera_mm_interconnect_180 ip_arria10_e2sg_altera_reset_controller_180 ip_arria10_e2sg_altera_emif_arch_nf_180 ip_arria10_e2sg_altera_emif_180 ip_arria10_e2sg_altera_avalon_mm_bridge_180 ip_arria10_e2sg_altera_merlin_slave_translator_180 ip_arria10_e2sg_altera_avalon_sc_fifo_180 ip_arria10_e2sg_altera_avalon_st_packets_to_bytes_180 ip_arria10_e2sg_altera_ip_col_if_180 ip_arria10_e2sg_altera_jtag_dc_streaming_180 ip_arria10_e2sg_alt_mem_if_jtag_master_180 ip_arria10_e2sg_altera_avalon_st_bytes_to_packets_180 ip_arria10_e2sg_altera_avalon_packets_to_master_180 ip_arria10_e2sg_channel_adapter_180 ip_arria10_e2sg_timing_adapter_180
+
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_ddr4_8g_1600.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600.qsys b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..4c82a2c5103e5e8393499a3944cf2109a907876d
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600.qsys
@@ -0,0 +1,1343 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_ddr4_8g_1600">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element emif_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>ctrl_amm_0</key>
+ <value>
+ <connectionPointName>ctrl_amm_0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='ctrl_amm_0' start='0x0' end='0x240000000' datawidth='576' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>34</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>576</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>ctrl_mmr_slave_0</key>
+ <value>
+ <connectionPointName>ctrl_mmr_slave_0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='ctrl_mmr_slave_0' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>12</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>emif_usr_clk</key>
+ <value>
+ <connectionPointName>emif_usr_clk</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>200000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="ctrl_amm_0"
+ internal="emif_0.ctrl_amm_0"
+ type="avalon"
+ dir="end">
+ <port name="amm_address_0" internal="amm_address_0" />
+ <port name="amm_burstcount_0" internal="amm_burstcount_0" />
+ <port name="amm_byteenable_0" internal="amm_byteenable_0" />
+ <port name="amm_read_0" internal="amm_read_0" />
+ <port name="amm_readdata_0" internal="amm_readdata_0" />
+ <port name="amm_readdatavalid_0" internal="amm_readdatavalid_0" />
+ <port name="amm_ready_0" internal="amm_ready_0" />
+ <port name="amm_write_0" internal="amm_write_0" />
+ <port name="amm_writedata_0" internal="amm_writedata_0" />
+ </interface>
+ <interface
+ name="ctrl_mmr_slave_0"
+ internal="emif_0.ctrl_mmr_slave_0"
+ type="avalon"
+ dir="end">
+ <port name="mmr_slave_address_0" internal="mmr_slave_address_0" />
+ <port
+ name="mmr_slave_beginbursttransfer_0"
+ internal="mmr_slave_beginbursttransfer_0" />
+ <port name="mmr_slave_burstcount_0" internal="mmr_slave_burstcount_0" />
+ <port name="mmr_slave_read_0" internal="mmr_slave_read_0" />
+ <port name="mmr_slave_readdata_0" internal="mmr_slave_readdata_0" />
+ <port name="mmr_slave_readdatavalid_0" internal="mmr_slave_readdatavalid_0" />
+ <port name="mmr_slave_waitrequest_0" internal="mmr_slave_waitrequest_0" />
+ <port name="mmr_slave_write_0" internal="mmr_slave_write_0" />
+ <port name="mmr_slave_writedata_0" internal="mmr_slave_writedata_0" />
+ </interface>
+ <interface
+ name="emif_usr_clk"
+ internal="emif_0.emif_usr_clk"
+ type="clock"
+ dir="start">
+ <port name="emif_usr_clk" internal="emif_usr_clk" />
+ </interface>
+ <interface
+ name="emif_usr_reset_n"
+ internal="emif_0.emif_usr_reset_n"
+ type="reset"
+ dir="start">
+ <port name="emif_usr_reset_n" internal="emif_usr_reset_n" />
+ </interface>
+ <interface
+ name="global_reset_n"
+ internal="emif_0.global_reset_n"
+ type="reset"
+ dir="end">
+ <port name="global_reset_n" internal="global_reset_n" />
+ </interface>
+ <interface name="mem" internal="emif_0.mem" type="conduit" dir="end">
+ <port name="mem_a" internal="mem_a" />
+ <port name="mem_act_n" internal="mem_act_n" />
+ <port name="mem_alert_n" internal="mem_alert_n" />
+ <port name="mem_ba" internal="mem_ba" />
+ <port name="mem_bg" internal="mem_bg" />
+ <port name="mem_ck" internal="mem_ck" />
+ <port name="mem_ck_n" internal="mem_ck_n" />
+ <port name="mem_cke" internal="mem_cke" />
+ <port name="mem_cs_n" internal="mem_cs_n" />
+ <port name="mem_dbi_n" internal="mem_dbi_n" />
+ <port name="mem_dq" internal="mem_dq" />
+ <port name="mem_dqs" internal="mem_dqs" />
+ <port name="mem_dqs_n" internal="mem_dqs_n" />
+ <port name="mem_odt" internal="mem_odt" />
+ <port name="mem_par" internal="mem_par" />
+ <port name="mem_reset_n" internal="mem_reset_n" />
+ </interface>
+ <interface name="oct" internal="emif_0.oct" type="conduit" dir="end">
+ <port name="oct_rzqin" internal="oct_rzqin" />
+ </interface>
+ <interface
+ name="pll_ref_clk"
+ internal="emif_0.pll_ref_clk"
+ type="clock"
+ dir="end">
+ <port name="pll_ref_clk" internal="pll_ref_clk" />
+ </interface>
+ <interface name="status" internal="emif_0.status" type="conduit" dir="end">
+ <port name="local_cal_fail" internal="local_cal_fail" />
+ <port name="local_cal_success" internal="local_cal_success" />
+ </interface>
+ <module
+ name="emif_0"
+ kind="altera_emif"
+ version="19.1.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR3_MAX_DQS_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_DDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR3_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR3_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_USER_RCLK_SLEW_RATE" value="5.0" />
+ <parameter name="BOARD_DDR3_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_USER_RDATA_SLEW_RATE" value="2.5" />
+ <parameter name="BOARD_DDR3_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR3_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_DDR3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_DDR4_AC_TO_CK_SKEW_NS" value="5.0E-4" />
+ <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS" value="0.0055" />
+ <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS" value="0.006" />
+ <parameter name="BOARD_DDR4_DQS_TO_CK_SKEW_NS" value="-0.2285" />
+ <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.231" />
+ <parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.291" />
+ <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.072" />
+ <parameter name="BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.137" />
+ <parameter name="BOARD_DDR4_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_USER_AC_SLEW_RATE" value="1.16" />
+ <parameter name="BOARD_DDR4_USER_CK_SLEW_RATE" value="2.43" />
+ <parameter name="BOARD_DDR4_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_USER_RCLK_SLEW_RATE" value="3.7" />
+ <parameter name="BOARD_DDR4_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_USER_RDATA_SLEW_RATE" value="2.2" />
+ <parameter name="BOARD_DDR4_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_USER_WCLK_SLEW_RATE" value="3.7" />
+ <parameter name="BOARD_DDR4_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_USER_WDATA_SLEW_RATE" value="2.16" />
+ <parameter name="BOARD_DDR4_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_DDR4_USE_DEFAULT_SLEW_RATES" value="false" />
+ <parameter name="BOARD_LPDDR3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+ <parameter name="BOARD_LPDDR3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_LPDDR3_MAX_DQS_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_LPDDR3_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_LPDDR3_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_LPDDR3_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_RDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_LPDDR3_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_LPDDR3_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_QDR2_AC_TO_K_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_D_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR2_MAX_K_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USER_K_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR2_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR2_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_USER_RDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_QDR2_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_QDR4_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_DK_TO_CK_SKEW_NS" value="-0.02" />
+ <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR4_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR4_MAX_DK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_QDR4_SKEW_BETWEEN_DK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR4_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR4_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_RCLK_SLEW_RATE" value="5.0" />
+ <parameter name="BOARD_QDR4_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_RDATA_SLEW_RATE" value="2.5" />
+ <parameter name="BOARD_QDR4_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR4_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR4_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_QDR4_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_RLD3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_DK_TO_CK_SKEW_NS" value="-0.02" />
+ <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
+ <parameter name="BOARD_RLD3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_RLD3_MAX_DK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_RLD3_SKEW_BETWEEN_DK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_RLD3_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_RLD3_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_USER_RCLK_SLEW_RATE" value="7.0" />
+ <parameter name="BOARD_RLD3_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_USER_RDATA_SLEW_RATE" value="3.5" />
+ <parameter name="BOARD_RLD3_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_RLD3_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_RLD3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_RLD3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="CAL_DEBUG_CLOCK_FREQUENCY" value="50000000" />
+ <parameter name="CTRL_DDR3_ADDR_ORDER_ENUM">DDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_DDR3_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_DDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_DDR3_ECC_AUTO_CORRECTION_EN" value="false" />
+ <parameter name="CTRL_DDR3_ECC_EN" value="false" />
+ <parameter name="CTRL_DDR3_ECC_READDATAERROR_EN" value="false" />
+ <parameter name="CTRL_DDR3_MMR_EN" value="false" />
+ <parameter name="CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_REORDER_EN" value="true" />
+ <parameter name="CTRL_DDR3_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR3_STARVE_LIMIT" value="10" />
+ <parameter name="CTRL_DDR3_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_DDR3_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_ADDR_ORDER_ENUM">DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG</parameter>
+ <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_DDR4_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_DDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_DDR4_ECC_AUTO_CORRECTION_EN" value="false" />
+ <parameter name="CTRL_DDR4_ECC_EN" value="false" />
+ <parameter name="CTRL_DDR4_ECC_READDATAERROR_EN" value="false" />
+ <parameter name="CTRL_DDR4_MMR_EN" value="true" />
+ <parameter name="CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_REORDER_EN" value="true" />
+ <parameter name="CTRL_DDR4_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR4_STARVE_LIMIT" value="10" />
+ <parameter name="CTRL_DDR4_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_DDR4_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_ADDR_ORDER_ENUM">LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_LPDDR3_MMR_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_REORDER_EN" value="true" />
+ <parameter name="CTRL_LPDDR3_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_STARVE_LIMIT" value="10" />
+ <parameter name="CTRL_LPDDR3_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
+ <parameter name="CTRL_QDR2_AVL_MAX_BURST_COUNT" value="4" />
+ <parameter name="CTRL_QDR2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC" value="0" />
+ <parameter name="CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC" value="0" />
+ <parameter name="CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
+ <parameter name="CTRL_QDR4_AVL_MAX_BURST_COUNT" value="4" />
+ <parameter name="CTRL_QDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_QDR4_DEF_RAW_TURNAROUND_DELAY_CYC" value="4" />
+ <parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
+ <parameter name="DIAG_DB_RESET_AUTO_RELEASE" value="avl_release" />
+ <parameter name="DIAG_DDR3_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_DDR3_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_DDR3_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_DDR3_CAL_ADDR0" value="0" />
+ <parameter name="DIAG_DDR3_CAL_ADDR1" value="8" />
+ <parameter name="DIAG_DDR3_CAL_ENABLE_MICRON_AP" value="false" />
+ <parameter name="DIAG_DDR3_CAL_ENABLE_NON_DES" value="false" />
+ <parameter name="DIAG_DDR3_CAL_FULL_CAL_ON_RESET" value="true" />
+ <parameter name="DIAG_DDR3_CA_DESKEW_EN" value="false" />
+ <parameter name="DIAG_DDR3_CA_LEVEL_EN" value="true" />
+ <parameter name="DIAG_DDR3_DISABLE_AFI_P2C_REGISTERS" value="false" />
+ <parameter name="DIAG_DDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
+ <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR3_EXPORT_TG_CFG_AVALON_SLAVE">TG_CFG_AMM_EXPORT_MODE_EXPORT</parameter>
+ <parameter name="DIAG_DDR3_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_DDR3_INFI_TG2_ERR_TEST" value="false" />
+ <parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_DDR3_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR3_SIM_VERBOSE" value="true" />
+ <parameter name="DIAG_DDR3_USER_SIM_MEMORY_PRELOAD" value="false" />
+ <parameter name="DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE">EMIF_PRI_PRELOAD.txt</parameter>
+ <parameter name="DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE">EMIF_SEC_PRELOAD.txt</parameter>
+ <parameter name="DIAG_DDR3_USER_USE_SIM_MEMORY_VALIDATION_TG" value="true" />
+ <parameter name="DIAG_DDR3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_DDR4_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_DDR4_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_DDR4_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_DDR4_CAL_ADDR0" value="0" />
+ <parameter name="DIAG_DDR4_CAL_ADDR1" value="8" />
+ <parameter name="DIAG_DDR4_CAL_ENABLE_NON_DES" value="false" />
+ <parameter name="DIAG_DDR4_CAL_FULL_CAL_ON_RESET" value="true" />
+ <parameter name="DIAG_DDR4_DISABLE_AFI_P2C_REGISTERS" value="false" />
+ <parameter name="DIAG_DDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
+ <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_JTAG</parameter>
+ <parameter name="DIAG_DDR4_EXPORT_TG_CFG_AVALON_SLAVE">TG_CFG_AMM_EXPORT_MODE_EXPORT</parameter>
+ <parameter name="DIAG_DDR4_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_DDR4_INFI_TG2_ERR_TEST" value="false" />
+ <parameter name="DIAG_DDR4_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_DDR4_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_DDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR4_SIM_VERBOSE" value="true" />
+ <parameter name="DIAG_DDR4_SKIP_CA_DESKEW" value="false" />
+ <parameter name="DIAG_DDR4_SKIP_CA_LEVEL" value="false" />
+ <parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="true" />
+ <parameter name="DIAG_DDR4_USER_SIM_MEMORY_PRELOAD" value="false" />
+ <parameter name="DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE">EMIF_PRI_PRELOAD.txt</parameter>
+ <parameter name="DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE">EMIF_SEC_PRELOAD.txt</parameter>
+ <parameter name="DIAG_DDR4_USER_USE_SIM_MEMORY_VALIDATION_TG" value="true" />
+ <parameter name="DIAG_DDR4_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_ECLIPSE_DEBUG" value="false" />
+ <parameter name="DIAG_ENABLE_HPS_EMIF_DEBUG" value="false" />
+ <parameter name="DIAG_ENABLE_JTAG_UART" value="false" />
+ <parameter name="DIAG_ENABLE_JTAG_UART_HEX" value="false" />
+ <parameter name="DIAG_EXPORT_PLL_LOCKED" value="false" />
+ <parameter name="DIAG_EXPORT_PLL_REF_CLK_OUT" value="false" />
+ <parameter name="DIAG_EXPORT_VJI" value="false" />
+ <parameter name="DIAG_EXPOSE_DFT_SIGNALS" value="false" />
+ <parameter name="DIAG_EXTRA_CONFIGS" value="" />
+ <parameter name="DIAG_EXT_DOCS" value="false" />
+ <parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
+ <parameter name="DIAG_EX_DESIGN_SEPARATE_RESETS" value="false" />
+ <parameter name="DIAG_FAST_SIM_OVERRIDE">FAST_SIM_OVERRIDE_DEFAULT</parameter>
+ <parameter name="DIAG_HMC_HRC" value="auto" />
+ <parameter name="DIAG_LPDDR3_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_LPDDR3_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_LPDDR3_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_LPDDR3_DISABLE_AFI_P2C_REGISTERS" value="false" />
+ <parameter name="DIAG_LPDDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
+ <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_LPDDR3_EXPORT_TG_CFG_AVALON_SLAVE">TG_CFG_AMM_EXPORT_MODE_EXPORT</parameter>
+ <parameter name="DIAG_LPDDR3_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_LPDDR3_INFI_TG2_ERR_TEST" value="false" />
+ <parameter name="DIAG_LPDDR3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_LPDDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_LPDDR3_SIM_VERBOSE" value="true" />
+ <parameter name="DIAG_LPDDR3_SKIP_CA_DESKEW" value="false" />
+ <parameter name="DIAG_LPDDR3_SKIP_CA_LEVEL" value="false" />
+ <parameter name="DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD" value="false" />
+ <parameter name="DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE">EMIF_PRI_PRELOAD.txt</parameter>
+ <parameter name="DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE">EMIF_SEC_PRELOAD.txt</parameter>
+ <parameter name="DIAG_LPDDR3_USER_USE_SIM_MEMORY_VALIDATION_TG" value="true" />
+ <parameter name="DIAG_LPDDR3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_QDR2_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_QDR2_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_QDR2_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_QDR2_DISABLE_AFI_P2C_REGISTERS" value="false" />
+ <parameter name="DIAG_QDR2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
+ <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR2_EXPORT_TG_CFG_AVALON_SLAVE">TG_CFG_AMM_EXPORT_MODE_EXPORT</parameter>
+ <parameter name="DIAG_QDR2_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_QDR2_INFI_TG2_ERR_TEST" value="false" />
+ <parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_QDR2_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR2_SIM_VERBOSE" value="true" />
+ <parameter name="DIAG_QDR2_USER_SIM_MEMORY_PRELOAD" value="false" />
+ <parameter name="DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE">EMIF_PRI_PRELOAD.txt</parameter>
+ <parameter name="DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE">EMIF_SEC_PRELOAD.txt</parameter>
+ <parameter name="DIAG_QDR2_USER_USE_SIM_MEMORY_VALIDATION_TG" value="true" />
+ <parameter name="DIAG_QDR2_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_QDR4_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_QDR4_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_QDR4_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_QDR4_DISABLE_AFI_P2C_REGISTERS" value="false" />
+ <parameter name="DIAG_QDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
+ <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR4_EXPORT_TG_CFG_AVALON_SLAVE">TG_CFG_AMM_EXPORT_MODE_EXPORT</parameter>
+ <parameter name="DIAG_QDR4_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_QDR4_INFI_TG2_ERR_TEST" value="false" />
+ <parameter name="DIAG_QDR4_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_QDR4_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_QDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR4_SIM_VERBOSE" value="true" />
+ <parameter name="DIAG_QDR4_SKIP_VREF_CAL" value="false" />
+ <parameter name="DIAG_QDR4_USER_SIM_MEMORY_PRELOAD" value="false" />
+ <parameter name="DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE">EMIF_PRI_PRELOAD.txt</parameter>
+ <parameter name="DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE">EMIF_SEC_PRELOAD.txt</parameter>
+ <parameter name="DIAG_QDR4_USER_USE_SIM_MEMORY_VALIDATION_TG" value="true" />
+ <parameter name="DIAG_QDR4_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RLD2_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_RLD2_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_RLD2_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_RLD2_DISABLE_AFI_P2C_REGISTERS" value="false" />
+ <parameter name="DIAG_RLD2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
+ <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD2_EXPORT_TG_CFG_AVALON_SLAVE">TG_CFG_AMM_EXPORT_MODE_EXPORT</parameter>
+ <parameter name="DIAG_RLD2_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_RLD2_INFI_TG2_ERR_TEST" value="false" />
+ <parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_RLD2_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD2_SIM_VERBOSE" value="true" />
+ <parameter name="DIAG_RLD2_USER_SIM_MEMORY_PRELOAD" value="false" />
+ <parameter name="DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE">EMIF_PRI_PRELOAD.txt</parameter>
+ <parameter name="DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE">EMIF_SEC_PRELOAD.txt</parameter>
+ <parameter name="DIAG_RLD2_USER_USE_SIM_MEMORY_VALIDATION_TG" value="true" />
+ <parameter name="DIAG_RLD2_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RLD3_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_RLD3_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_RLD3_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_RLD3_CA_DESKEW_EN" value="false" />
+ <parameter name="DIAG_RLD3_CA_LEVEL_EN" value="false" />
+ <parameter name="DIAG_RLD3_DISABLE_AFI_P2C_REGISTERS" value="false" />
+ <parameter name="DIAG_RLD3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
+ <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD3_EXPORT_TG_CFG_AVALON_SLAVE">TG_CFG_AMM_EXPORT_MODE_EXPORT</parameter>
+ <parameter name="DIAG_RLD3_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_RLD3_INFI_TG2_ERR_TEST" value="false" />
+ <parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_RLD3_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD3_SIM_VERBOSE" value="true" />
+ <parameter name="DIAG_RLD3_USER_SIM_MEMORY_PRELOAD" value="false" />
+ <parameter name="DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE">EMIF_PRI_PRELOAD.txt</parameter>
+ <parameter name="DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE">EMIF_SEC_PRELOAD.txt</parameter>
+ <parameter name="DIAG_RLD3_USER_USE_SIM_MEMORY_VALIDATION_TG" value="true" />
+ <parameter name="DIAG_RLD3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RS232_UART_BAUDRATE" value="57600" />
+ <parameter name="DIAG_SEQ_RESET_AUTO_RELEASE" value="avl" />
+ <parameter name="DIAG_SIM_REGTEST_MODE" value="false" />
+ <parameter name="DIAG_SOFT_NIOS_CLOCK_FREQUENCY" value="100" />
+ <parameter name="DIAG_SOFT_NIOS_MODE">SOFT_NIOS_MODE_DISABLED</parameter>
+ <parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
+ <parameter name="DIAG_TG_AVL_2_NUM_CFG_INTERFACES" value="0" />
+ <parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
+ <parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
+ <parameter name="DIAG_USE_RS232_UART" value="false" />
+ <parameter name="DIAG_VERBOSE_IOAUX" value="false" />
+ <parameter name="EX_DESIGN_GUI_DDR3_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR3_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_DDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_DDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_DDR4_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR4_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_DDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_DDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter
+ name="EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT"
+ value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR2_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR2_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_QDR2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR4_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR4_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_QDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD2_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD2_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_RLD2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD3_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD3_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_RLD3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="INTERNAL_TESTING_MODE" value="false" />
+ <parameter name="IS_ED_SLAVE" value="false" />
+ <parameter name="MEM_DDR3_ALERT_N_DQS_GROUP" value="0" />
+ <parameter name="MEM_DDR3_ALERT_N_PLACEMENT_ENUM">DDR3_ALERT_N_PLACEMENT_AC_LANES</parameter>
+ <parameter name="MEM_DDR3_ASR_ENUM" value="DDR3_ASR_MANUAL" />
+ <parameter name="MEM_DDR3_ATCL_ENUM" value="DDR3_ATCL_DISABLED" />
+ <parameter name="MEM_DDR3_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_DDR3_BL_ENUM" value="DDR3_BL_BL8" />
+ <parameter name="MEM_DDR3_BT_ENUM" value="DDR3_BT_SEQUENTIAL" />
+ <parameter name="MEM_DDR3_CFG_GEN_DBE" value="false" />
+ <parameter name="MEM_DDR3_CFG_GEN_SBE" value="false" />
+ <parameter name="MEM_DDR3_CKE_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR3_CK_WIDTH" value="1" />
+ <parameter name="MEM_DDR3_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_DDR3_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN" value="false" />
+ <parameter name="MEM_DDR3_DLL_EN" value="true" />
+ <parameter name="MEM_DDR3_DM_EN" value="true" />
+ <parameter name="MEM_DDR3_DQ_PER_DQS" value="8" />
+ <parameter name="MEM_DDR3_DQ_WIDTH" value="72" />
+ <parameter name="MEM_DDR3_DRV_STR_ENUM" value="DDR3_DRV_STR_RZQ_7" />
+ <parameter name="MEM_DDR3_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
+ <parameter name="MEM_DDR3_HIDE_ADV_MR_SETTINGS" value="true" />
+ <parameter name="MEM_DDR3_LRDIMM_EXTENDED_CONFIG" value="000000000000000000" />
+ <parameter name="MEM_DDR3_MIRROR_ADDRESSING_EN" value="true" />
+ <parameter name="MEM_DDR3_NUM_OF_DIMMS" value="1" />
+ <parameter name="MEM_DDR3_PD_ENUM" value="DDR3_PD_OFF" />
+ <parameter name="MEM_DDR3_RANKS_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR3_RDIMM_CONFIG" value="0000000000000000" />
+ <parameter name="MEM_DDR3_ROW_ADDR_WIDTH" value="15" />
+ <parameter name="MEM_DDR3_RTT_NOM_ENUM">DDR3_RTT_NOM_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR3_RTT_WR_ENUM" value="DDR3_RTT_WR_RZQ_4" />
+ <parameter name="MEM_DDR3_R_ODT0_1X1" value="off" />
+ <parameter name="MEM_DDR3_R_ODT0_2X2" value="off,off" />
+ <parameter name="MEM_DDR3_R_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_R_ODT0_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR3_R_ODT1_2X2" value="off,off" />
+ <parameter name="MEM_DDR3_R_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_R_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_R_ODT2_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR3_R_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR3_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_SPEEDBIN_ENUM" value="DDR3_SPEEDBIN_2133" />
+ <parameter name="MEM_DDR3_SRT_ENUM" value="DDR3_SRT_NORMAL" />
+ <parameter name="MEM_DDR3_TCL" value="14" />
+ <parameter name="MEM_DDR3_TDH_DC_MV" value="100" />
+ <parameter name="MEM_DDR3_TDH_PS" value="55" />
+ <parameter name="MEM_DDR3_TDQSCK_PS" value="180" />
+ <parameter name="MEM_DDR3_TDQSQ_PS" value="75" />
+ <parameter name="MEM_DDR3_TDQSS_CYC" value="0.27" />
+ <parameter name="MEM_DDR3_TDSH_CYC" value="0.18" />
+ <parameter name="MEM_DDR3_TDSS_CYC" value="0.18" />
+ <parameter name="MEM_DDR3_TDS_AC_MV" value="135" />
+ <parameter name="MEM_DDR3_TDS_PS" value="53" />
+ <parameter name="MEM_DDR3_TFAW_NS" value="25.0" />
+ <parameter name="MEM_DDR3_TIH_DC_MV" value="100" />
+ <parameter name="MEM_DDR3_TIH_PS" value="95" />
+ <parameter name="MEM_DDR3_TINIT_US" value="500" />
+ <parameter name="MEM_DDR3_TIS_AC_MV" value="135" />
+ <parameter name="MEM_DDR3_TIS_PS" value="60" />
+ <parameter name="MEM_DDR3_TMRD_CK_CYC" value="4" />
+ <parameter name="MEM_DDR3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_DDR3_TQSH_CYC" value="0.4" />
+ <parameter name="MEM_DDR3_TRAS_NS" value="33.0" />
+ <parameter name="MEM_DDR3_TRCD_NS" value="13.09" />
+ <parameter name="MEM_DDR3_TREFI_US" value="7.8" />
+ <parameter name="MEM_DDR3_TRFC_NS" value="160.0" />
+ <parameter name="MEM_DDR3_TRP_NS" value="13.09" />
+ <parameter name="MEM_DDR3_TRRD_CYC" value="6" />
+ <parameter name="MEM_DDR3_TRTP_CYC" value="8" />
+ <parameter name="MEM_DDR3_TWLH_PS" value="125.0" />
+ <parameter name="MEM_DDR3_TWLS_PS" value="125.0" />
+ <parameter name="MEM_DDR3_TWR_NS" value="15.0" />
+ <parameter name="MEM_DDR3_TWTR_CYC" value="8" />
+ <parameter name="MEM_DDR3_USE_DEFAULT_ODT" value="true" />
+ <parameter name="MEM_DDR3_WTCL" value="10" />
+ <parameter name="MEM_DDR3_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_DDR3_W_ODT0_2X2" value="on,off" />
+ <parameter name="MEM_DDR3_W_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT0_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODT1_2X2" value="off,on" />
+ <parameter name="MEM_DDR3_W_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT2_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR3_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_AC_PARITY_LATENCY">DDR4_AC_PARITY_LATENCY_DISABLE</parameter>
+ <parameter name="MEM_DDR4_AC_PERSISTENT_ERROR" value="false" />
+ <parameter name="MEM_DDR4_ALERT_N_AC_LANE" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_AC_PIN" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_DQS_GROUP" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_PLACEMENT_ENUM">DDR4_ALERT_N_PLACEMENT_DATA_LANES</parameter>
+ <parameter name="MEM_DDR4_ALERT_PAR_EN" value="true" />
+ <parameter name="MEM_DDR4_ASR_ENUM">DDR4_ASR_MANUAL_NORMAL</parameter>
+ <parameter name="MEM_DDR4_ATCL_ENUM" value="DDR4_ATCL_DISABLED" />
+ <parameter name="MEM_DDR4_BANK_ADDR_WIDTH" value="2" />
+ <parameter name="MEM_DDR4_BANK_GROUP_WIDTH" value="2" />
+ <parameter name="MEM_DDR4_BL_ENUM" value="DDR4_BL_BL8" />
+ <parameter name="MEM_DDR4_BT_ENUM" value="DDR4_BT_SEQUENTIAL" />
+ <parameter name="MEM_DDR4_CAL_MODE" value="0" />
+ <parameter name="MEM_DDR4_CFG_GEN_DBE" value="false" />
+ <parameter name="MEM_DDR4_CFG_GEN_SBE" value="false" />
+ <parameter name="MEM_DDR4_CHIP_ID_WIDTH" value="0" />
+ <parameter name="MEM_DDR4_CKE_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR4_CK_WIDTH" value="2" />
+ <parameter name="MEM_DDR4_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_DDR4_DB_DQ_DRV_ENUM">DDR4_DB_DRV_STR_RZQ_7</parameter>
+ <parameter name="MEM_DDR4_DB_RTT_NOM_ENUM">DDR4_DB_RTT_NOM_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_DB_RTT_PARK_ENUM">DDR4_DB_RTT_PARK_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_DB_RTT_WR_ENUM">DDR4_DB_RTT_WR_RZQ_3</parameter>
+ <parameter name="MEM_DDR4_DEFAULT_VREFOUT" value="false" />
+ <parameter name="MEM_DDR4_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN" value="false" />
+ <parameter name="MEM_DDR4_DLL_EN" value="true" />
+ <parameter name="MEM_DDR4_DM_EN" value="true" />
+ <parameter name="MEM_DDR4_DQ_PER_DQS" value="8" />
+ <parameter name="MEM_DDR4_DQ_WIDTH" value="72" />
+ <parameter name="MEM_DDR4_DRV_STR_ENUM" value="DDR4_DRV_STR_RZQ_7" />
+ <parameter name="MEM_DDR4_FINE_GRANULARITY_REFRESH">DDR4_FINE_REFRESH_FIXED_1X</parameter>
+ <parameter name="MEM_DDR4_FORMAT_ENUM" value="MEM_FORMAT_SODIMM" />
+ <parameter name="MEM_DDR4_GEARDOWN" value="DDR4_GEARDOWN_HR" />
+ <parameter name="MEM_DDR4_HIDE_ADV_MR_SETTINGS" value="true" />
+ <parameter name="MEM_DDR4_INTERNAL_VREFDQ_MONITOR" value="false" />
+ <parameter name="MEM_DDR4_LRDIMM_ODT_LESS_BS" value="true" />
+ <parameter name="MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM" value="240" />
+ <parameter name="MEM_DDR4_LRDIMM_VREFDQ_VALUE" value="1D" />
+ <parameter name="MEM_DDR4_MAX_POWERDOWN" value="false" />
+ <parameter name="MEM_DDR4_MIRROR_ADDRESSING_EN" value="true" />
+ <parameter name="MEM_DDR4_MPR_READ_FORMAT">DDR4_MPR_READ_FORMAT_SERIAL</parameter>
+ <parameter name="MEM_DDR4_NUM_OF_DIMMS" value="1" />
+ <parameter name="MEM_DDR4_ODT_IN_POWERDOWN" value="true" />
+ <parameter name="MEM_DDR4_PER_DRAM_ADDR" value="false" />
+ <parameter name="MEM_DDR4_RANKS_PER_DIMM" value="2" />
+ <parameter name="MEM_DDR4_RCD_CA_IBT_ENUM" value="DDR4_RCD_CA_IBT_100" />
+ <parameter name="MEM_DDR4_RCD_CKE_IBT_ENUM">DDR4_RCD_CKE_IBT_100</parameter>
+ <parameter name="MEM_DDR4_RCD_CS_IBT_ENUM" value="DDR4_RCD_CS_IBT_100" />
+ <parameter name="MEM_DDR4_RCD_ODT_IBT_ENUM">DDR4_RCD_ODT_IBT_100</parameter>
+ <parameter name="MEM_DDR4_READ_DBI" value="false" />
+ <parameter name="MEM_DDR4_READ_PREAMBLE" value="2" />
+ <parameter name="MEM_DDR4_READ_PREAMBLE_TRAINING" value="false" />
+ <parameter name="MEM_DDR4_ROW_ADDR_WIDTH" value="15" />
+ <parameter name="MEM_DDR4_RTT_NOM_ENUM" value="DDR4_RTT_NOM_RZQ_4" />
+ <parameter name="MEM_DDR4_RTT_PARK">DDR4_RTT_PARK_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_RTT_WR_ENUM">DDR4_RTT_WR_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_R_ODT0_1X1" value="on" />
+ <parameter name="MEM_DDR4_R_ODT0_2X2" value="on,off" />
+ <parameter name="MEM_DDR4_R_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_R_ODT0_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR4_R_ODT1_2X2" value="off,on" />
+ <parameter name="MEM_DDR4_R_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_R_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_R_ODT2_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR4_R_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR4_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR4_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_SELF_RFSH_ABORT" value="false" />
+ <parameter name="MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB" value="0" />
+ <parameter name="MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB" value="0" />
+ <parameter name="MEM_DDR4_SPD_135_RCD_REV" value="0" />
+ <parameter name="MEM_DDR4_SPD_137_RCD_CA_DRV" value="101" />
+ <parameter name="MEM_DDR4_SPD_138_RCD_CK_DRV" value="5" />
+ <parameter name="MEM_DDR4_SPD_139_DB_REV" value="0" />
+ <parameter name="MEM_DDR4_SPD_140_DRAM_VREFDQ_R0" value="29" />
+ <parameter name="MEM_DDR4_SPD_141_DRAM_VREFDQ_R1" value="29" />
+ <parameter name="MEM_DDR4_SPD_142_DRAM_VREFDQ_R2" value="29" />
+ <parameter name="MEM_DDR4_SPD_143_DRAM_VREFDQ_R3" value="29" />
+ <parameter name="MEM_DDR4_SPD_144_DB_VREFDQ" value="37" />
+ <parameter name="MEM_DDR4_SPD_145_DB_MDQ_DRV" value="21" />
+ <parameter name="MEM_DDR4_SPD_148_DRAM_DRV" value="0" />
+ <parameter name="MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM" value="20" />
+ <parameter name="MEM_DDR4_SPD_152_DRAM_RTT_PARK" value="39" />
+ <parameter name="MEM_DDR4_SPEEDBIN_ENUM" value="DDR4_SPEEDBIN_2133" />
+ <parameter name="MEM_DDR4_TCCD_L_CYC" value="5" />
+ <parameter name="MEM_DDR4_TCCD_S_CYC" value="4" />
+ <parameter name="MEM_DDR4_TCL" value="11" />
+ <parameter name="MEM_DDR4_TDIVW_DJ_CYC" value="0.1" />
+ <parameter name="MEM_DDR4_TDIVW_TOTAL_UI" value="0.1" />
+ <parameter name="MEM_DDR4_TDQSCK_PS" value="170" />
+ <parameter name="MEM_DDR4_TDQSQ_PS" value="66" />
+ <parameter name="MEM_DDR4_TDQSQ_UI" value="0.16" />
+ <parameter name="MEM_DDR4_TDQSS_CYC" value="0.27" />
+ <parameter name="MEM_DDR4_TDSH_CYC" value="0.18" />
+ <parameter name="MEM_DDR4_TDSS_CYC" value="0.18" />
+ <parameter name="MEM_DDR4_TDVWP_UI" value="0.72" />
+ <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA" value="false" />
+ <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE">DDR4_TEMP_CONTROLLED_RFSH_NORMAL</parameter>
+ <parameter name="MEM_DDR4_TEMP_SENSOR_READOUT" value="false" />
+ <parameter name="MEM_DDR4_TFAW_DLR_CYC" value="16" />
+ <parameter name="MEM_DDR4_TFAW_NS" value="21.0" />
+ <parameter name="MEM_DDR4_TIH_DC_MV" value="75" />
+ <parameter name="MEM_DDR4_TIH_PS" value="105" />
+ <parameter name="MEM_DDR4_TINIT_US" value="500" />
+ <parameter name="MEM_DDR4_TIS_AC_MV" value="100" />
+ <parameter name="MEM_DDR4_TIS_PS" value="80" />
+ <parameter name="MEM_DDR4_TMRD_CK_CYC" value="8" />
+ <parameter name="MEM_DDR4_TQH_CYC" value="0.38" />
+ <parameter name="MEM_DDR4_TQH_UI" value="0.76" />
+ <parameter name="MEM_DDR4_TQSH_CYC" value="0.38" />
+ <parameter name="MEM_DDR4_TRAS_NS" value="33.0" />
+ <parameter name="MEM_DDR4_TRCD_NS" value="14.06" />
+ <parameter name="MEM_DDR4_TREFI_US" value="7.8" />
+ <parameter name="MEM_DDR4_TRFC_DLR_NS" value="90.0" />
+ <parameter name="MEM_DDR4_TRFC_NS" value="260.0" />
+ <parameter name="MEM_DDR4_TRP_NS" value="14.06" />
+ <parameter name="MEM_DDR4_TRRD_DLR_CYC" value="4" />
+ <parameter name="MEM_DDR4_TRRD_L_CYC" value="5" />
+ <parameter name="MEM_DDR4_TRRD_S_CYC" value="3" />
+ <parameter name="MEM_DDR4_TWLH_CYC" value="0.13" />
+ <parameter name="MEM_DDR4_TWLH_PS" value="0.0" />
+ <parameter name="MEM_DDR4_TWLS_CYC" value="0.13" />
+ <parameter name="MEM_DDR4_TWLS_PS" value="0.0" />
+ <parameter name="MEM_DDR4_TWR_NS" value="15.0" />
+ <parameter name="MEM_DDR4_TWTR_L_CYC" value="6" />
+ <parameter name="MEM_DDR4_TWTR_S_CYC" value="2" />
+ <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_RANGE">DDR4_VREFDQ_TRAINING_RANGE_1</parameter>
+ <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_VALUE" value="68.0" />
+ <parameter name="MEM_DDR4_USE_DEFAULT_ODT" value="false" />
+ <parameter name="MEM_DDR4_VDIVW_TOTAL" value="136" />
+ <parameter name="MEM_DDR4_WRITE_CRC" value="false" />
+ <parameter name="MEM_DDR4_WRITE_DBI" value="false" />
+ <parameter name="MEM_DDR4_WRITE_PREAMBLE" value="1" />
+ <parameter name="MEM_DDR4_WTCL" value="9" />
+ <parameter name="MEM_DDR4_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_DDR4_W_ODT0_2X2" value="on,off" />
+ <parameter name="MEM_DDR4_W_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT0_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODT1_2X2" value="off,on" />
+ <parameter name="MEM_DDR4_W_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT2_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR4_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR4_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_LPDDR3_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_LPDDR3_BL" value="LPDDR3_BL_BL8" />
+ <parameter name="MEM_LPDDR3_CK_WIDTH" value="1" />
+ <parameter name="MEM_LPDDR3_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_LPDDR3_DATA_LATENCY" value="LPDDR3_DL_RL12_WL6" />
+ <parameter name="MEM_LPDDR3_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_LPDDR3_DM_EN" value="true" />
+ <parameter name="MEM_LPDDR3_DQODT">LPDDR3_DQODT_DISABLE</parameter>
+ <parameter name="MEM_LPDDR3_DQ_WIDTH" value="32" />
+ <parameter name="MEM_LPDDR3_DRV_STR">LPDDR3_DRV_STR_40D_40U</parameter>
+ <parameter name="MEM_LPDDR3_PDODT">LPDDR3_PDODT_DISABLED</parameter>
+ <parameter name="MEM_LPDDR3_ROW_ADDR_WIDTH" value="15" />
+ <parameter name="MEM_LPDDR3_R_ODT0_1X1" value="off" />
+ <parameter name="MEM_LPDDR3_R_ODT0_2X2" value="off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT0_4X4" value="off,off,on,on" />
+ <parameter name="MEM_LPDDR3_R_ODT1_2X2" value="off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT1_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT2_4X4" value="on,on,off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT3_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_LPDDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_LPDDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_LPDDR3_SPEEDBIN_ENUM">LPDDR3_SPEEDBIN_1600</parameter>
+ <parameter name="MEM_LPDDR3_TDH_DC_MV" value="100" />
+ <parameter name="MEM_LPDDR3_TDH_PS" value="100" />
+ <parameter name="MEM_LPDDR3_TDQSCKDL" value="614" />
+ <parameter name="MEM_LPDDR3_TDQSQ_PS" value="135" />
+ <parameter name="MEM_LPDDR3_TDQSS_CYC" value="1.25" />
+ <parameter name="MEM_LPDDR3_TDSH_CYC" value="0.2" />
+ <parameter name="MEM_LPDDR3_TDSS_CYC" value="0.2" />
+ <parameter name="MEM_LPDDR3_TDS_AC_MV" value="150" />
+ <parameter name="MEM_LPDDR3_TDS_PS" value="75" />
+ <parameter name="MEM_LPDDR3_TFAW_NS" value="50.0" />
+ <parameter name="MEM_LPDDR3_TIH_DC_MV" value="100" />
+ <parameter name="MEM_LPDDR3_TIH_PS" value="100" />
+ <parameter name="MEM_LPDDR3_TINIT_US" value="500" />
+ <parameter name="MEM_LPDDR3_TIS_AC_MV" value="150" />
+ <parameter name="MEM_LPDDR3_TIS_PS" value="75" />
+ <parameter name="MEM_LPDDR3_TMRR_CK_CYC" value="4" />
+ <parameter name="MEM_LPDDR3_TMRW_CK_CYC" value="10" />
+ <parameter name="MEM_LPDDR3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_LPDDR3_TQSH_CYC" value="0.38" />
+ <parameter name="MEM_LPDDR3_TRAS_NS" value="42.5" />
+ <parameter name="MEM_LPDDR3_TRCD_NS" value="18.75" />
+ <parameter name="MEM_LPDDR3_TREFI_US" value="3.9" />
+ <parameter name="MEM_LPDDR3_TRFC_NS" value="210.0" />
+ <parameter name="MEM_LPDDR3_TRP_NS" value="18.75" />
+ <parameter name="MEM_LPDDR3_TRRD_CYC" value="2" />
+ <parameter name="MEM_LPDDR3_TRTP_CYC" value="4" />
+ <parameter name="MEM_LPDDR3_TWLH_PS" value="175.0" />
+ <parameter name="MEM_LPDDR3_TWLS_PS" value="175.0" />
+ <parameter name="MEM_LPDDR3_TWR_NS" value="15.0" />
+ <parameter name="MEM_LPDDR3_TWTR_CYC" value="4" />
+ <parameter name="MEM_LPDDR3_USE_DEFAULT_ODT" value="true" />
+ <parameter name="MEM_LPDDR3_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_LPDDR3_W_ODT0_2X2" value="on,off" />
+ <parameter name="MEM_LPDDR3_W_ODT0_4X4" value="on,on,on,on" />
+ <parameter name="MEM_LPDDR3_W_ODT1_2X2" value="off,on" />
+ <parameter name="MEM_LPDDR3_W_ODT1_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_W_ODT2_4X4" value="on,on,on,on" />
+ <parameter name="MEM_LPDDR3_W_ODT3_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_LPDDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_LPDDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_QDR2_ADDR_WIDTH" value="19" />
+ <parameter name="MEM_QDR2_BL" value="4" />
+ <parameter name="MEM_QDR2_BWS_EN" value="true" />
+ <parameter name="MEM_QDR2_DATA_PER_DEVICE" value="36" />
+ <parameter name="MEM_QDR2_INTERNAL_JITTER_NS" value="0.08" />
+ <parameter name="MEM_QDR2_SPEEDBIN_ENUM" value="QDR2_SPEEDBIN_633" />
+ <parameter name="MEM_QDR2_TCCQO_NS" value="0.45" />
+ <parameter name="MEM_QDR2_TCQDOH_NS" value="-0.09" />
+ <parameter name="MEM_QDR2_TCQD_NS" value="0.09" />
+ <parameter name="MEM_QDR2_TCQH_NS" value="0.71" />
+ <parameter name="MEM_QDR2_THA_NS" value="0.18" />
+ <parameter name="MEM_QDR2_THD_NS" value="0.18" />
+ <parameter name="MEM_QDR2_TRL_CYC" value="2.5" />
+ <parameter name="MEM_QDR2_TSA_NS" value="0.23" />
+ <parameter name="MEM_QDR2_TSD_NS" value="0.23" />
+ <parameter name="MEM_QDR2_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_QDR4_AC_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_ADDR_INV_ENA" value="false" />
+ <parameter name="MEM_QDR4_ADDR_WIDTH" value="21" />
+ <parameter name="MEM_QDR4_CK_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_DATA_INV_ENA" value="false" />
+ <parameter name="MEM_QDR4_DATA_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_DQ_PER_PORT_PER_DEVICE" value="36" />
+ <parameter name="MEM_QDR4_MEM_TYPE_ENUM" value="MEM_XP" />
+ <parameter name="MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+ <parameter name="MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+ <parameter name="MEM_QDR4_SKIP_ODT_SWEEPING" value="true" />
+ <parameter name="MEM_QDR4_SPEEDBIN_ENUM" value="QDR4_SPEEDBIN_2133" />
+ <parameter name="MEM_QDR4_TASH_PS" value="170" />
+ <parameter name="MEM_QDR4_TCKDK_MAX_PS" value="150" />
+ <parameter name="MEM_QDR4_TCKDK_MIN_PS" value="-150" />
+ <parameter name="MEM_QDR4_TCKQK_MAX_PS" value="225" />
+ <parameter name="MEM_QDR4_TCSH_PS" value="170" />
+ <parameter name="MEM_QDR4_TISH_PS" value="150" />
+ <parameter name="MEM_QDR4_TQH_CYC" value="0.4" />
+ <parameter name="MEM_QDR4_TQKQ_MAX_PS" value="75" />
+ <parameter name="MEM_QDR4_USE_ADDR_PARITY" value="false" />
+ <parameter name="MEM_QDR4_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD2_ADDR_WIDTH" value="21" />
+ <parameter name="MEM_RLD2_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_RLD2_BL" value="4" />
+ <parameter name="MEM_RLD2_CONFIG_ENUM">RLD2_CONFIG_TRC_8_TRL_8_TWL_9</parameter>
+ <parameter name="MEM_RLD2_DM_EN" value="true" />
+ <parameter name="MEM_RLD2_DQ_PER_DEVICE" value="9" />
+ <parameter name="MEM_RLD2_DRIVE_IMPEDENCE_ENUM">RLD2_DRIVE_IMPEDENCE_INTERNAL_50</parameter>
+ <parameter name="MEM_RLD2_ODT_MODE_ENUM" value="RLD2_ODT_ON" />
+ <parameter name="MEM_RLD2_REFRESH_INTERVAL_US" value="0.24" />
+ <parameter name="MEM_RLD2_SPEEDBIN_ENUM" value="RLD2_SPEEDBIN_18" />
+ <parameter name="MEM_RLD2_TAH_NS" value="0.3" />
+ <parameter name="MEM_RLD2_TAS_NS" value="0.3" />
+ <parameter name="MEM_RLD2_TCKDK_MAX_NS" value="0.3" />
+ <parameter name="MEM_RLD2_TCKDK_MIN_NS" value="-0.3" />
+ <parameter name="MEM_RLD2_TCKH_CYC" value="0.45" />
+ <parameter name="MEM_RLD2_TCKQK_MAX_NS" value="0.2" />
+ <parameter name="MEM_RLD2_TDH_NS" value="0.17" />
+ <parameter name="MEM_RLD2_TDS_NS" value="0.17" />
+ <parameter name="MEM_RLD2_TQKH_HCYC" value="0.9" />
+ <parameter name="MEM_RLD2_TQKQ_MAX_NS" value="0.12" />
+ <parameter name="MEM_RLD2_TQKQ_MIN_NS" value="-0.12" />
+ <parameter name="MEM_RLD2_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_ADDR_WIDTH" value="20" />
+ <parameter name="MEM_RLD3_AREF_PROTOCOL_ENUM" value="RLD3_AREF_BAC" />
+ <parameter name="MEM_RLD3_BANK_ADDR_WIDTH" value="4" />
+ <parameter name="MEM_RLD3_BL" value="2" />
+ <parameter name="MEM_RLD3_DATA_LATENCY_MODE_ENUM" value="RLD3_DL_RL16_WL17" />
+ <parameter name="MEM_RLD3_DEPTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_DM_EN" value="true" />
+ <parameter name="MEM_RLD3_DQ_PER_DEVICE" value="36" />
+ <parameter name="MEM_RLD3_ODT_MODE_ENUM" value="RLD3_ODT_40" />
+ <parameter name="MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM">RLD3_OUTPUT_DRIVE_40</parameter>
+ <parameter name="MEM_RLD3_SPEEDBIN_ENUM" value="RLD3_SPEEDBIN_093E" />
+ <parameter name="MEM_RLD3_TCKDK_MAX_CYC" value="0.27" />
+ <parameter name="MEM_RLD3_TCKDK_MIN_CYC" value="-0.27" />
+ <parameter name="MEM_RLD3_TCKQK_MAX_PS" value="135" />
+ <parameter name="MEM_RLD3_TDH_DC_MV" value="100" />
+ <parameter name="MEM_RLD3_TDH_PS" value="5" />
+ <parameter name="MEM_RLD3_TDS_AC_MV" value="150" />
+ <parameter name="MEM_RLD3_TDS_PS" value="-30" />
+ <parameter name="MEM_RLD3_TIH_DC_MV" value="100" />
+ <parameter name="MEM_RLD3_TIH_PS" value="65" />
+ <parameter name="MEM_RLD3_TIS_AC_MV" value="150" />
+ <parameter name="MEM_RLD3_TIS_PS" value="85" />
+ <parameter name="MEM_RLD3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_RLD3_TQKQ_MAX_PS" value="75" />
+ <parameter name="MEM_RLD3_T_RC_MODE_ENUM" value="RLD3_TRC_9" />
+ <parameter name="MEM_RLD3_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_WRITE_PROTOCOL_ENUM" value="RLD3_WRITE_1BANK" />
+ <parameter name="PHY_DDR3_CAL_ADDR0" value="0" />
+ <parameter name="PHY_DDR3_CAL_ADDR1" value="8" />
+ <parameter name="PHY_DDR3_CAL_ENABLE_NON_DES" value="true" />
+ <parameter name="PHY_DDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_DDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_DDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
+ <parameter name="PHY_DDR3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_DDR3_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_DDR3_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_DDR3_IO_VOLTAGE" value="1.5" />
+ <parameter name="PHY_DDR3_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_DDR3_MIMIC_HPS_EMIF" value="false" />
+ <parameter name="PHY_DDR3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR3_USER_AUTO_STARTING_VREFIN_EN" value="true" />
+ <parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_DLL_CORE_UPDN_EN" value="true" />
+ <parameter name="PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_DDR3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_DDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_STARTING_VREFIN" value="70.0" />
+ <parameter name="PHY_DDR4_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_DDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_DDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
+ <parameter name="PHY_DDR4_DEFAULT_IO" value="false" />
+ <parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="false" />
+ <parameter name="PHY_DDR4_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_DDR4_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="800.0" />
+ <parameter name="PHY_DDR4_MIMIC_HPS_EMIF" value="false" />
+ <parameter name="PHY_DDR4_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_DDR4_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="IO_STD_SSTL_12" />
+ <parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="OUT_OCT_40_CAL" />
+ <parameter name="PHY_DDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR4_USER_AUTO_STARTING_VREFIN_EN" value="true" />
+ <parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="IO_STD_SSTL_12" />
+ <parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="OUT_OCT_40_CAL" />
+ <parameter name="PHY_DDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR4_USER_CLAMSHELL_EN" value="false" />
+ <parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="IN_OCT_60_CAL" />
+ <parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="IO_STD_POD_12" />
+ <parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="OUT_OCT_34_CAL" />
+ <parameter name="PHY_DDR4_USER_DLL_CORE_UPDN_EN" value="true" />
+ <parameter name="PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_DDR4_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="IO_STD_CMOS_12" />
+ <parameter name="PHY_DDR4_USER_REF_CLK_FREQ_MHZ" value="25.0" />
+ <parameter name="PHY_DDR4_USER_RZQ_IO_STD_ENUM" value="IO_STD_CMOS_12" />
+ <parameter name="PHY_DDR4_USER_STARTING_VREFIN" value="70.0" />
+ <parameter name="PHY_LPDDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_LPDDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_LPDDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
+ <parameter name="PHY_LPDDR3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_LPDDR3_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_LPDDR3_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_LPDDR3_MEM_CLK_FREQ_MHZ" value="800.0" />
+ <parameter name="PHY_LPDDR3_MIMIC_HPS_EMIF" value="false" />
+ <parameter name="PHY_LPDDR3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_LPDDR3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_LPDDR3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_LPDDR3_USER_AUTO_STARTING_VREFIN_EN" value="true" />
+ <parameter name="PHY_LPDDR3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_LPDDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_DLL_CORE_UPDN_EN" value="false" />
+ <parameter name="PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_LPDDR3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_LPDDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_STARTING_VREFIN" value="70.0" />
+ <parameter name="PHY_QDR2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_QDR2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_QDR2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
+ <parameter name="PHY_QDR2_DEFAULT_IO" value="true" />
+ <parameter name="PHY_QDR2_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_QDR2_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_QDR2_IO_VOLTAGE" value="1.5" />
+ <parameter name="PHY_QDR2_MEM_CLK_FREQ_MHZ" value="633.333" />
+ <parameter name="PHY_QDR2_MIMIC_HPS_EMIF" value="false" />
+ <parameter name="PHY_QDR2_RATE_ENUM" value="RATE_HALF" />
+ <parameter name="PHY_QDR2_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_QDR2_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR2_USER_AUTO_STARTING_VREFIN_EN" value="true" />
+ <parameter name="PHY_QDR2_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR2_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_DLL_CORE_UPDN_EN" value="false" />
+ <parameter name="PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_QDR2_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_QDR2_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_STARTING_VREFIN" value="70.0" />
+ <parameter name="PHY_QDR4_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_QDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_QDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
+ <parameter name="PHY_QDR4_DEFAULT_IO" value="true" />
+ <parameter name="PHY_QDR4_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_QDR4_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_QDR4_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_QDR4_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_QDR4_MIMIC_HPS_EMIF" value="false" />
+ <parameter name="PHY_QDR4_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_QDR4_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_QDR4_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR4_USER_AUTO_STARTING_VREFIN_EN" value="true" />
+ <parameter name="PHY_QDR4_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_DLL_CORE_UPDN_EN" value="true" />
+ <parameter name="PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_QDR4_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_QDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_STARTING_VREFIN" value="70.0" />
+ <parameter name="PHY_RLD2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_RLD2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_RLD2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
+ <parameter name="PHY_RLD2_DEFAULT_IO" value="true" />
+ <parameter name="PHY_RLD2_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_RLD2_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_RLD2_IO_VOLTAGE" value="1.8" />
+ <parameter name="PHY_RLD2_MEM_CLK_FREQ_MHZ" value="533.333" />
+ <parameter name="PHY_RLD2_MIMIC_HPS_EMIF" value="false" />
+ <parameter name="PHY_RLD2_RATE_ENUM" value="RATE_HALF" />
+ <parameter name="PHY_RLD2_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_RLD2_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD2_USER_AUTO_STARTING_VREFIN_EN" value="true" />
+ <parameter name="PHY_RLD2_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD2_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_DLL_CORE_UPDN_EN" value="false" />
+ <parameter name="PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_RLD2_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_RLD2_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_STARTING_VREFIN" value="70.0" />
+ <parameter name="PHY_RLD3_CONFIG_ENUM" value="CONFIG_PHY_ONLY" />
+ <parameter name="PHY_RLD3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_RLD3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
+ <parameter name="PHY_RLD3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_RLD3_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_RLD3_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_RLD3_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_RLD3_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_RLD3_MIMIC_HPS_EMIF" value="false" />
+ <parameter name="PHY_RLD3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_RLD3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_RLD3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD3_USER_AUTO_STARTING_VREFIN_EN" value="true" />
+ <parameter name="PHY_RLD3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_DLL_CORE_UPDN_EN" value="false" />
+ <parameter name="PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_RLD3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_STARTING_VREFIN" value="70.0" />
+ <parameter name="PLL_ADD_EXTRA_CLKS" value="false" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_0" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_1" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_2" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_3" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_4" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_0" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_1" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_2" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_3" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_4" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8" value="0" />
+ <parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
+ <parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
+ <parameter name="SHORT_QSYS_INTERFACE_NAMES" value="true" />
+ <parameter name="SYS_INFO_DEVICE" value="10AX115U3F45E2SG" />
+ <parameter name="SYS_INFO_DEVICE_DIE_REVISIONS" value="" />
+ <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="SYS_INFO_DEVICE_POWER_MODEL" value="STANDARD" />
+ <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="SYS_INFO_DEVICE_TEMPERATURE_GRADE" value="EXTENDED" />
+ <parameter name="SYS_INFO_UNIQUE_ID">ip_arria10_e2sg_ddr4_8g_1600_emif_0</parameter>
+ <parameter name="TRAIT_SUPPORTS_VID" value="0" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1889f0a0e45cbbbfef0ed44dfbcaa7a85a08b518
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/compile_ip.tcl
@@ -0,0 +1,34 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
+
+ vcom "$IP_DIR/ip_arria10_e2sg_ddr4_8g_2400.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/copy_hex_files.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..37f218bda8baa54a853e5a7981624800e105989b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/copy_hex_files.tcl
@@ -0,0 +1,33 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/sim"
+
+# Copy ROM/RAM files to simulation directory
+if {[file isdirectory $IP_DIR]} {
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_151_izxxuoi_seq_cal_sim.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_151_izxxuoi_seq_cal_synth.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_151_izxxuoi_seq_params_sim.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e2sg_ddr4_8g_2400_altera_emif_arch_nf_151_izxxuoi_seq_params_synth.hex ./
+}
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..ad4fc49ab4fe3afa4fc606e7442320901c26a26b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_ddr4_8g_2400
+hdl_library_clause_name = ip_arria10_e2sg_ddr4_8g_2400_altera_emif_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_merlin_master_translator_180 ip_arria10_e2sg_altera_emif_cal_slave_nf_180 ip_arria10_e2sg_altera_avalon_onchip_memory2_180 ip_arria10_e2sg_altera_mm_interconnect_180 ip_arria10_e2sg_altera_reset_controller_180 ip_arria10_e2sg_altera_emif_arch_nf_180 ip_arria10_e2sg_altera_emif_180 ip_arria10_e2sg_altera_avalon_mm_bridge_180 ip_arria10_e2sg_altera_merlin_slave_translator_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddr4_8g_2400/ip_arria10_e2sg_ddr4_8g_2400.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_ddr4_8g_2400.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/ip_arria10_e2sg_ddr4_8g_2400.qsys b/libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/ip_arria10_e2sg_ddr4_8g_2400.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..5a828ee7b6d5f9fdb06bba6702a083ef60cb766e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/ip_arria10_e2sg_ddr4_8g_2400.qsys
@@ -0,0 +1,1317 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_ddr4_8g_2400">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysPro" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element ddr4_inst
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>ctrl_amm_avalon_slave_0</key>
+ <value>
+ <connectionPointName>ctrl_amm_avalon_slave_0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='ctrl_amm_avalon_slave_0' start='0x0' end='0x240000000' datawidth='576' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>34</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>576</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>emif_usr_clk_clock_source</key>
+ <value>
+ <connectionPointName>emif_usr_clk_clock_source</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>300000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="ctrl_amm_avalon_slave_0"
+ internal="ddr4_inst.ctrl_amm_avalon_slave_0"
+ type="avalon"
+ dir="end">
+ <port name="amm_address_0" internal="amm_address_0" />
+ <port name="amm_burstcount_0" internal="amm_burstcount_0" />
+ <port name="amm_byteenable_0" internal="amm_byteenable_0" />
+ <port name="amm_read_0" internal="amm_read_0" />
+ <port name="amm_readdata_0" internal="amm_readdata_0" />
+ <port name="amm_readdatavalid_0" internal="amm_readdatavalid_0" />
+ <port name="amm_ready_0" internal="amm_ready_0" />
+ <port name="amm_write_0" internal="amm_write_0" />
+ <port name="amm_writedata_0" internal="amm_writedata_0" />
+ </interface>
+ <interface
+ name="emif_usr_clk_clock_source"
+ internal="ddr4_inst.emif_usr_clk_clock_source"
+ type="clock"
+ dir="start">
+ <port name="emif_usr_clk" internal="emif_usr_clk" />
+ </interface>
+ <interface
+ name="emif_usr_reset_reset_source"
+ internal="ddr4_inst.emif_usr_reset_reset_source"
+ type="reset"
+ dir="start">
+ <port name="emif_usr_reset_n" internal="emif_usr_reset_n" />
+ </interface>
+ <interface
+ name="global_reset_reset_sink"
+ internal="ddr4_inst.global_reset_reset_sink"
+ type="reset"
+ dir="end">
+ <port name="global_reset_n" internal="global_reset_n" />
+ </interface>
+ <interface
+ name="mem_conduit_end"
+ internal="ddr4_inst.mem_conduit_end"
+ type="conduit"
+ dir="end">
+ <port name="mem_a" internal="mem_a" />
+ <port name="mem_act_n" internal="mem_act_n" />
+ <port name="mem_alert_n" internal="mem_alert_n" />
+ <port name="mem_ba" internal="mem_ba" />
+ <port name="mem_bg" internal="mem_bg" />
+ <port name="mem_ck" internal="mem_ck" />
+ <port name="mem_ck_n" internal="mem_ck_n" />
+ <port name="mem_cke" internal="mem_cke" />
+ <port name="mem_cs_n" internal="mem_cs_n" />
+ <port name="mem_dbi_n" internal="mem_dbi_n" />
+ <port name="mem_dq" internal="mem_dq" />
+ <port name="mem_dqs" internal="mem_dqs" />
+ <port name="mem_dqs_n" internal="mem_dqs_n" />
+ <port name="mem_odt" internal="mem_odt" />
+ <port name="mem_par" internal="mem_par" />
+ <port name="mem_reset_n" internal="mem_reset_n" />
+ </interface>
+ <interface
+ name="oct_conduit_end"
+ internal="ddr4_inst.oct_conduit_end"
+ type="conduit"
+ dir="end">
+ <port name="oct_rzqin" internal="oct_rzqin" />
+ </interface>
+ <interface
+ name="pll_ref_clk_clock_sink"
+ internal="ddr4_inst.pll_ref_clk_clock_sink"
+ type="clock"
+ dir="end">
+ <port name="pll_ref_clk" internal="pll_ref_clk" />
+ </interface>
+ <interface
+ name="status_conduit_end"
+ internal="ddr4_inst.status_conduit_end"
+ type="conduit"
+ dir="end">
+ <port name="local_cal_fail" internal="local_cal_fail" />
+ <port name="local_cal_success" internal="local_cal_success" />
+ </interface>
+ <module
+ name="ddr4_inst"
+ kind="altera_emif"
+ version="19.1.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR3_MAX_DQS_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_DDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_USER_AC_ISI_NS" value="0.094" />
+ <parameter name="BOARD_DDR3_USER_AC_SLEW_RATE" value="1.0" />
+ <parameter name="BOARD_DDR3_USER_CK_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR3_USER_RCLK_ISI_NS" value="0.094" />
+ <parameter name="BOARD_DDR3_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR3_USER_RDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_DDR3_USER_RDATA_SLEW_RATE" value="2.5" />
+ <parameter name="BOARD_DDR3_USER_WCLK_ISI_NS" value="0.031" />
+ <parameter name="BOARD_DDR3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR3_USER_WDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_DDR3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_DDR3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_DDR4_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_DQS_TO_CK_SKEW_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED" value="true" />
+ <parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_USER_AC_ISI_NS" value="0.094" />
+ <parameter name="BOARD_DDR4_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR4_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR4_USER_RCLK_ISI_NS" value="0.094" />
+ <parameter name="BOARD_DDR4_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR4_USER_RDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_DDR4_USER_RDATA_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR4_USER_WCLK_ISI_NS" value="0.031" />
+ <parameter name="BOARD_DDR4_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR4_USER_WDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_DDR4_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR4_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_DDR4_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_LPDDR3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+ <parameter name="BOARD_LPDDR3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_LPDDR3_MAX_DQS_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_LPDDR3_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_LPDDR3_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_LPDDR3_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_RDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_LPDDR3_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_LPDDR3_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_QDR2_AC_TO_K_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_D_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR2_MAX_K_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_USER_AC_ISI_NS" value="0.094" />
+ <parameter name="BOARD_QDR2_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USER_K_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR2_USER_RCLK_ISI_NS" value="0.094" />
+ <parameter name="BOARD_QDR2_USER_RCLK_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USER_RDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_QDR2_USER_RDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USER_WCLK_ISI_NS" value="0.031" />
+ <parameter name="BOARD_QDR2_USER_WDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_QDR2_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_QDR2_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_QDR4_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_DK_TO_CK_SKEW_NS" value="-0.02" />
+ <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR4_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR4_MAX_DK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_QDR4_SKEW_BETWEEN_DK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR4_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR4_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR4_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_RDATA_SLEW_RATE" value="3.5" />
+ <parameter name="BOARD_QDR4_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR4_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR4_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_QDR4_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_RLD3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_DK_TO_CK_SKEW_NS" value="-0.02" />
+ <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
+ <parameter name="BOARD_RLD3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_RLD3_MAX_DK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_RLD3_SKEW_BETWEEN_DK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_USER_AC_ISI_NS" value="0.094" />
+ <parameter name="BOARD_RLD3_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_RLD3_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_RLD3_USER_RCLK_ISI_NS" value="0.094" />
+ <parameter name="BOARD_RLD3_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_RLD3_USER_RDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_RLD3_USER_RDATA_SLEW_RATE" value="3.5" />
+ <parameter name="BOARD_RLD3_USER_WCLK_ISI_NS" value="0.031" />
+ <parameter name="BOARD_RLD3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_RLD3_USER_WDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_RLD3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_RLD3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_RLD3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="CAL_DEBUG_CLOCK_FREQUENCY" value="50000000" />
+ <parameter name="CTRL_DDR3_ADDR_ORDER_ENUM">DDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_DDR3_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_DDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_DDR3_ECC_AUTO_CORRECTION_EN" value="false" />
+ <parameter name="CTRL_DDR3_ECC_EN" value="false" />
+ <parameter name="CTRL_DDR3_ECC_READDATAERROR_EN" value="false" />
+ <parameter name="CTRL_DDR3_MMR_EN" value="false" />
+ <parameter name="CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_REORDER_EN" value="true" />
+ <parameter name="CTRL_DDR3_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR3_STARVE_LIMIT" value="63" />
+ <parameter name="CTRL_DDR3_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_DDR3_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_ADDR_ORDER_ENUM">DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG</parameter>
+ <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_DDR4_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_DDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_DDR4_ECC_AUTO_CORRECTION_EN" value="false" />
+ <parameter name="CTRL_DDR4_ECC_EN" value="false" />
+ <parameter name="CTRL_DDR4_ECC_READDATAERROR_EN" value="false" />
+ <parameter name="CTRL_DDR4_MMR_EN" value="false" />
+ <parameter name="CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_REORDER_EN" value="true" />
+ <parameter name="CTRL_DDR4_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR4_STARVE_LIMIT" value="63" />
+ <parameter name="CTRL_DDR4_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_DDR4_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_ADDR_ORDER_ENUM">LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_LPDDR3_MMR_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_REORDER_EN" value="true" />
+ <parameter name="CTRL_LPDDR3_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_STARVE_LIMIT" value="10" />
+ <parameter name="CTRL_LPDDR3_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
+ <parameter name="CTRL_QDR2_AVL_MAX_BURST_COUNT" value="4" />
+ <parameter name="CTRL_QDR2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC" value="0" />
+ <parameter name="CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC" value="0" />
+ <parameter name="CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
+ <parameter name="CTRL_QDR4_AVL_MAX_BURST_COUNT" value="4" />
+ <parameter name="CTRL_QDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_QDR4_DEF_RAW_TURNAROUND_DELAY_CYC" value="4" />
+ <parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
+ <parameter name="DIAG_DB_RESET_AUTO_RELEASE" value="avl_release" />
+ <parameter name="DIAG_DDR3_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_DDR3_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_DDR3_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_DDR3_CAL_ADDR0" value="0" />
+ <parameter name="DIAG_DDR3_CAL_ADDR1" value="8" />
+ <parameter name="DIAG_DDR3_CAL_ENABLE_MICRON_AP" value="false" />
+ <parameter name="DIAG_DDR3_CAL_ENABLE_NON_DES" value="false" />
+ <parameter name="DIAG_DDR3_CAL_FULL_CAL_ON_RESET" value="true" />
+ <parameter name="DIAG_DDR3_CA_DESKEW_EN" value="false" />
+ <parameter name="DIAG_DDR3_CA_LEVEL_EN" value="true" />
+ <parameter name="DIAG_DDR3_DISABLE_AFI_P2C_REGISTERS" value="false" />
+ <parameter name="DIAG_DDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
+ <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR3_EXPORT_TG_CFG_AVALON_SLAVE">TG_CFG_AMM_EXPORT_MODE_EXPORT</parameter>
+ <parameter name="DIAG_DDR3_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_DDR3_INFI_TG2_ERR_TEST" value="false" />
+ <parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_DDR3_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR3_SIM_VERBOSE" value="true" />
+ <parameter name="DIAG_DDR3_USER_SIM_MEMORY_PRELOAD" value="false" />
+ <parameter name="DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE">EMIF_PRI_PRELOAD.txt</parameter>
+ <parameter name="DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE">EMIF_SEC_PRELOAD.txt</parameter>
+ <parameter name="DIAG_DDR3_USER_USE_SIM_MEMORY_VALIDATION_TG" value="true" />
+ <parameter name="DIAG_DDR3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_DDR4_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_DDR4_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_DDR4_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_DDR4_CAL_ADDR0" value="0" />
+ <parameter name="DIAG_DDR4_CAL_ADDR1" value="8" />
+ <parameter name="DIAG_DDR4_CAL_ENABLE_NON_DES" value="false" />
+ <parameter name="DIAG_DDR4_CAL_FULL_CAL_ON_RESET" value="true" />
+ <parameter name="DIAG_DDR4_DISABLE_AFI_P2C_REGISTERS" value="false" />
+ <parameter name="DIAG_DDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
+ <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR4_EXPORT_TG_CFG_AVALON_SLAVE">TG_CFG_AMM_EXPORT_MODE_EXPORT</parameter>
+ <parameter name="DIAG_DDR4_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_DDR4_INFI_TG2_ERR_TEST" value="false" />
+ <parameter name="DIAG_DDR4_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_DDR4_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_DDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR4_SIM_VERBOSE" value="true" />
+ <parameter name="DIAG_DDR4_SKIP_CA_DESKEW" value="false" />
+ <parameter name="DIAG_DDR4_SKIP_CA_LEVEL" value="false" />
+ <parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="true" />
+ <parameter name="DIAG_DDR4_USER_SIM_MEMORY_PRELOAD" value="false" />
+ <parameter name="DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE">EMIF_PRI_PRELOAD.txt</parameter>
+ <parameter name="DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE">EMIF_SEC_PRELOAD.txt</parameter>
+ <parameter name="DIAG_DDR4_USER_USE_SIM_MEMORY_VALIDATION_TG" value="true" />
+ <parameter name="DIAG_DDR4_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_ECLIPSE_DEBUG" value="false" />
+ <parameter name="DIAG_ENABLE_HPS_EMIF_DEBUG" value="false" />
+ <parameter name="DIAG_ENABLE_JTAG_UART" value="false" />
+ <parameter name="DIAG_ENABLE_JTAG_UART_HEX" value="false" />
+ <parameter name="DIAG_EXPORT_PLL_LOCKED" value="false" />
+ <parameter name="DIAG_EXPORT_PLL_REF_CLK_OUT" value="false" />
+ <parameter name="DIAG_EXPORT_VJI" value="false" />
+ <parameter name="DIAG_EXPOSE_DFT_SIGNALS" value="false" />
+ <parameter name="DIAG_EXTRA_CONFIGS" value="" />
+ <parameter name="DIAG_EXT_DOCS" value="false" />
+ <parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
+ <parameter name="DIAG_EX_DESIGN_SEPARATE_RESETS" value="false" />
+ <parameter name="DIAG_FAST_SIM_OVERRIDE">FAST_SIM_OVERRIDE_DEFAULT</parameter>
+ <parameter name="DIAG_HMC_HRC" value="auto" />
+ <parameter name="DIAG_LPDDR3_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_LPDDR3_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_LPDDR3_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_LPDDR3_DISABLE_AFI_P2C_REGISTERS" value="false" />
+ <parameter name="DIAG_LPDDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
+ <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_LPDDR3_EXPORT_TG_CFG_AVALON_SLAVE">TG_CFG_AMM_EXPORT_MODE_EXPORT</parameter>
+ <parameter name="DIAG_LPDDR3_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_LPDDR3_INFI_TG2_ERR_TEST" value="false" />
+ <parameter name="DIAG_LPDDR3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_LPDDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_LPDDR3_SIM_VERBOSE" value="true" />
+ <parameter name="DIAG_LPDDR3_SKIP_CA_DESKEW" value="false" />
+ <parameter name="DIAG_LPDDR3_SKIP_CA_LEVEL" value="false" />
+ <parameter name="DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD" value="false" />
+ <parameter name="DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE">EMIF_PRI_PRELOAD.txt</parameter>
+ <parameter name="DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE">EMIF_SEC_PRELOAD.txt</parameter>
+ <parameter name="DIAG_LPDDR3_USER_USE_SIM_MEMORY_VALIDATION_TG" value="true" />
+ <parameter name="DIAG_LPDDR3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_QDR2_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_QDR2_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_QDR2_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_QDR2_DISABLE_AFI_P2C_REGISTERS" value="false" />
+ <parameter name="DIAG_QDR2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
+ <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR2_EXPORT_TG_CFG_AVALON_SLAVE">TG_CFG_AMM_EXPORT_MODE_EXPORT</parameter>
+ <parameter name="DIAG_QDR2_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_QDR2_INFI_TG2_ERR_TEST" value="false" />
+ <parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_QDR2_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR2_SIM_VERBOSE" value="true" />
+ <parameter name="DIAG_QDR2_USER_SIM_MEMORY_PRELOAD" value="false" />
+ <parameter name="DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE">EMIF_PRI_PRELOAD.txt</parameter>
+ <parameter name="DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE">EMIF_SEC_PRELOAD.txt</parameter>
+ <parameter name="DIAG_QDR2_USER_USE_SIM_MEMORY_VALIDATION_TG" value="true" />
+ <parameter name="DIAG_QDR2_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_QDR4_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_QDR4_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_QDR4_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_QDR4_DISABLE_AFI_P2C_REGISTERS" value="false" />
+ <parameter name="DIAG_QDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
+ <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR4_EXPORT_TG_CFG_AVALON_SLAVE">TG_CFG_AMM_EXPORT_MODE_EXPORT</parameter>
+ <parameter name="DIAG_QDR4_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_QDR4_INFI_TG2_ERR_TEST" value="false" />
+ <parameter name="DIAG_QDR4_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_QDR4_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_QDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR4_SIM_VERBOSE" value="true" />
+ <parameter name="DIAG_QDR4_SKIP_VREF_CAL" value="false" />
+ <parameter name="DIAG_QDR4_USER_SIM_MEMORY_PRELOAD" value="false" />
+ <parameter name="DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE">EMIF_PRI_PRELOAD.txt</parameter>
+ <parameter name="DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE">EMIF_SEC_PRELOAD.txt</parameter>
+ <parameter name="DIAG_QDR4_USER_USE_SIM_MEMORY_VALIDATION_TG" value="true" />
+ <parameter name="DIAG_QDR4_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RLD2_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_RLD2_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_RLD2_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_RLD2_DISABLE_AFI_P2C_REGISTERS" value="false" />
+ <parameter name="DIAG_RLD2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
+ <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD2_EXPORT_TG_CFG_AVALON_SLAVE">TG_CFG_AMM_EXPORT_MODE_EXPORT</parameter>
+ <parameter name="DIAG_RLD2_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_RLD2_INFI_TG2_ERR_TEST" value="false" />
+ <parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_RLD2_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD2_SIM_VERBOSE" value="true" />
+ <parameter name="DIAG_RLD2_USER_SIM_MEMORY_PRELOAD" value="false" />
+ <parameter name="DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE">EMIF_PRI_PRELOAD.txt</parameter>
+ <parameter name="DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE">EMIF_SEC_PRELOAD.txt</parameter>
+ <parameter name="DIAG_RLD2_USER_USE_SIM_MEMORY_VALIDATION_TG" value="true" />
+ <parameter name="DIAG_RLD2_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RLD3_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_RLD3_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_RLD3_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_RLD3_CA_DESKEW_EN" value="false" />
+ <parameter name="DIAG_RLD3_CA_LEVEL_EN" value="false" />
+ <parameter name="DIAG_RLD3_DISABLE_AFI_P2C_REGISTERS" value="false" />
+ <parameter name="DIAG_RLD3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
+ <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD3_EXPORT_TG_CFG_AVALON_SLAVE">TG_CFG_AMM_EXPORT_MODE_EXPORT</parameter>
+ <parameter name="DIAG_RLD3_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_RLD3_INFI_TG2_ERR_TEST" value="false" />
+ <parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_RLD3_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD3_SIM_VERBOSE" value="true" />
+ <parameter name="DIAG_RLD3_USER_SIM_MEMORY_PRELOAD" value="false" />
+ <parameter name="DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE">EMIF_PRI_PRELOAD.txt</parameter>
+ <parameter name="DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE">EMIF_SEC_PRELOAD.txt</parameter>
+ <parameter name="DIAG_RLD3_USER_USE_SIM_MEMORY_VALIDATION_TG" value="true" />
+ <parameter name="DIAG_RLD3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RS232_UART_BAUDRATE" value="57600" />
+ <parameter name="DIAG_SEQ_RESET_AUTO_RELEASE" value="avl" />
+ <parameter name="DIAG_SIM_REGTEST_MODE" value="false" />
+ <parameter name="DIAG_SOFT_NIOS_CLOCK_FREQUENCY" value="100" />
+ <parameter name="DIAG_SOFT_NIOS_MODE">SOFT_NIOS_MODE_DISABLED</parameter>
+ <parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
+ <parameter name="DIAG_TG_AVL_2_NUM_CFG_INTERFACES" value="0" />
+ <parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
+ <parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
+ <parameter name="DIAG_USE_RS232_UART" value="false" />
+ <parameter name="DIAG_VERBOSE_IOAUX" value="false" />
+ <parameter name="EX_DESIGN_GUI_DDR3_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR3_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_DDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_DDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_DDR4_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR4_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_DDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_DDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter
+ name="EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT"
+ value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR2_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR2_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_QDR2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR4_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR4_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_QDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD2_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD2_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_RLD2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD3_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD3_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_RLD3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="INTERNAL_TESTING_MODE" value="false" />
+ <parameter name="IS_ED_SLAVE" value="false" />
+ <parameter name="MEM_DDR3_ALERT_N_DQS_GROUP" value="0" />
+ <parameter name="MEM_DDR3_ALERT_N_PLACEMENT_ENUM">DDR3_ALERT_N_PLACEMENT_AC_LANES</parameter>
+ <parameter name="MEM_DDR3_ASR_ENUM" value="DDR3_ASR_MANUAL" />
+ <parameter name="MEM_DDR3_ATCL_ENUM" value="DDR3_ATCL_DISABLED" />
+ <parameter name="MEM_DDR3_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_DDR3_BL_ENUM" value="DDR3_BL_BL8" />
+ <parameter name="MEM_DDR3_BT_ENUM" value="DDR3_BT_SEQUENTIAL" />
+ <parameter name="MEM_DDR3_CFG_GEN_DBE" value="false" />
+ <parameter name="MEM_DDR3_CFG_GEN_SBE" value="false" />
+ <parameter name="MEM_DDR3_CKE_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR3_CK_WIDTH" value="1" />
+ <parameter name="MEM_DDR3_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_DDR3_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN" value="false" />
+ <parameter name="MEM_DDR3_DLL_EN" value="true" />
+ <parameter name="MEM_DDR3_DM_EN" value="true" />
+ <parameter name="MEM_DDR3_DQ_PER_DQS" value="8" />
+ <parameter name="MEM_DDR3_DQ_WIDTH" value="72" />
+ <parameter name="MEM_DDR3_DRV_STR_ENUM" value="DDR3_DRV_STR_RZQ_6" />
+ <parameter name="MEM_DDR3_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
+ <parameter name="MEM_DDR3_HIDE_ADV_MR_SETTINGS" value="true" />
+ <parameter name="MEM_DDR3_LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
+ <parameter name="MEM_DDR3_MIRROR_ADDRESSING_EN" value="false" />
+ <parameter name="MEM_DDR3_NUM_OF_DIMMS" value="1" />
+ <parameter name="MEM_DDR3_PD_ENUM" value="DDR3_PD_OFF" />
+ <parameter name="MEM_DDR3_RANKS_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR3_RDIMM_CONFIG" value="0000000000000000" />
+ <parameter name="MEM_DDR3_ROW_ADDR_WIDTH" value="14" />
+ <parameter name="MEM_DDR3_RTT_NOM_ENUM">DDR3_RTT_NOM_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR3_RTT_WR_ENUM">DDR3_RTT_WR_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR3_R_ODT0_1X1" value="off" />
+ <parameter name="MEM_DDR3_R_ODT0_2X2" value="off,on" />
+ <parameter name="MEM_DDR3_R_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_R_ODT0_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR3_R_ODT1_2X2" value="on,off" />
+ <parameter name="MEM_DDR3_R_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_R_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_R_ODT2_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR3_R_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR3_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_SPEEDBIN_ENUM" value="DDR3_SPEEDBIN_2133" />
+ <parameter name="MEM_DDR3_SRT_ENUM" value="DDR3_SRT_NORMAL" />
+ <parameter name="MEM_DDR3_TCL" value="7" />
+ <parameter name="MEM_DDR3_TDH_DC_MV" value="100" />
+ <parameter name="MEM_DDR3_TDH_PS" value="55" />
+ <parameter name="MEM_DDR3_TDQSCK_PS" value="180" />
+ <parameter name="MEM_DDR3_TDQSQ_PS" value="75" />
+ <parameter name="MEM_DDR3_TDQSS_CYC" value="0.27" />
+ <parameter name="MEM_DDR3_TDSH_CYC" value="0.18" />
+ <parameter name="MEM_DDR3_TDSS_CYC" value="0.18" />
+ <parameter name="MEM_DDR3_TDS_AC_MV" value="135" />
+ <parameter name="MEM_DDR3_TDS_PS" value="53" />
+ <parameter name="MEM_DDR3_TFAW_NS" value="25.0" />
+ <parameter name="MEM_DDR3_TIH_DC_MV" value="100" />
+ <parameter name="MEM_DDR3_TIH_PS" value="95" />
+ <parameter name="MEM_DDR3_TINIT_US" value="500" />
+ <parameter name="MEM_DDR3_TIS_AC_MV" value="135" />
+ <parameter name="MEM_DDR3_TIS_PS" value="60" />
+ <parameter name="MEM_DDR3_TMRD_CK_CYC" value="4" />
+ <parameter name="MEM_DDR3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_DDR3_TQSH_CYC" value="0.4" />
+ <parameter name="MEM_DDR3_TRAS_NS" value="33.0" />
+ <parameter name="MEM_DDR3_TRCD_NS" value="13.09" />
+ <parameter name="MEM_DDR3_TREFI_US" value="7.8" />
+ <parameter name="MEM_DDR3_TRFC_NS" value="160.0" />
+ <parameter name="MEM_DDR3_TRP_NS" value="13.09" />
+ <parameter name="MEM_DDR3_TRRD_CYC" value="6" />
+ <parameter name="MEM_DDR3_TRTP_CYC" value="8" />
+ <parameter name="MEM_DDR3_TWLH_PS" value="125.0" />
+ <parameter name="MEM_DDR3_TWLS_PS" value="125.0" />
+ <parameter name="MEM_DDR3_TWR_NS" value="15.0" />
+ <parameter name="MEM_DDR3_TWTR_CYC" value="4" />
+ <parameter name="MEM_DDR3_USE_DEFAULT_ODT" value="true" />
+ <parameter name="MEM_DDR3_WTCL" value="6" />
+ <parameter name="MEM_DDR3_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_DDR3_W_ODT0_2X2" value="on,on" />
+ <parameter name="MEM_DDR3_W_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT0_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODT1_2X2" value="on,on" />
+ <parameter name="MEM_DDR3_W_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT2_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR3_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_AC_PARITY_LATENCY">DDR4_AC_PARITY_LATENCY_DISABLE</parameter>
+ <parameter name="MEM_DDR4_AC_PERSISTENT_ERROR" value="false" />
+ <parameter name="MEM_DDR4_ALERT_N_AC_LANE" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_AC_PIN" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_DQS_GROUP" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_PLACEMENT_ENUM">DDR4_ALERT_N_PLACEMENT_DATA_LANES</parameter>
+ <parameter name="MEM_DDR4_ALERT_PAR_EN" value="true" />
+ <parameter name="MEM_DDR4_ASR_ENUM">DDR4_ASR_MANUAL_NORMAL</parameter>
+ <parameter name="MEM_DDR4_ATCL_ENUM" value="DDR4_ATCL_DISABLED" />
+ <parameter name="MEM_DDR4_BANK_ADDR_WIDTH" value="2" />
+ <parameter name="MEM_DDR4_BANK_GROUP_WIDTH" value="2" />
+ <parameter name="MEM_DDR4_BL_ENUM" value="DDR4_BL_BL8" />
+ <parameter name="MEM_DDR4_BT_ENUM" value="DDR4_BT_SEQUENTIAL" />
+ <parameter name="MEM_DDR4_CAL_MODE" value="0" />
+ <parameter name="MEM_DDR4_CFG_GEN_DBE" value="false" />
+ <parameter name="MEM_DDR4_CFG_GEN_SBE" value="false" />
+ <parameter name="MEM_DDR4_CHIP_ID_WIDTH" value="0" />
+ <parameter name="MEM_DDR4_CKE_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR4_CK_WIDTH" value="2" />
+ <parameter name="MEM_DDR4_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_DDR4_DB_DQ_DRV_ENUM">DDR4_DB_DRV_STR_RZQ_7</parameter>
+ <parameter name="MEM_DDR4_DB_RTT_NOM_ENUM">DDR4_DB_RTT_NOM_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_DB_RTT_PARK_ENUM">DDR4_DB_RTT_PARK_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_DB_RTT_WR_ENUM">DDR4_DB_RTT_WR_RZQ_3</parameter>
+ <parameter name="MEM_DDR4_DEFAULT_VREFOUT" value="false" />
+ <parameter name="MEM_DDR4_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN" value="false" />
+ <parameter name="MEM_DDR4_DLL_EN" value="true" />
+ <parameter name="MEM_DDR4_DM_EN" value="true" />
+ <parameter name="MEM_DDR4_DQ_PER_DQS" value="8" />
+ <parameter name="MEM_DDR4_DQ_WIDTH" value="72" />
+ <parameter name="MEM_DDR4_DRV_STR_ENUM" value="DDR4_DRV_STR_RZQ_7" />
+ <parameter name="MEM_DDR4_FINE_GRANULARITY_REFRESH">DDR4_FINE_REFRESH_FIXED_1X</parameter>
+ <parameter name="MEM_DDR4_FORMAT_ENUM" value="MEM_FORMAT_SODIMM" />
+ <parameter name="MEM_DDR4_GEARDOWN" value="DDR4_GEARDOWN_HR" />
+ <parameter name="MEM_DDR4_HIDE_ADV_MR_SETTINGS" value="true" />
+ <parameter name="MEM_DDR4_INTERNAL_VREFDQ_MONITOR" value="false" />
+ <parameter name="MEM_DDR4_LRDIMM_ODT_LESS_BS" value="true" />
+ <parameter name="MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM" value="240" />
+ <parameter name="MEM_DDR4_LRDIMM_VREFDQ_VALUE" value="1D" />
+ <parameter name="MEM_DDR4_MAX_POWERDOWN" value="false" />
+ <parameter name="MEM_DDR4_MIRROR_ADDRESSING_EN" value="false" />
+ <parameter name="MEM_DDR4_MPR_READ_FORMAT">DDR4_MPR_READ_FORMAT_SERIAL</parameter>
+ <parameter name="MEM_DDR4_NUM_OF_DIMMS" value="1" />
+ <parameter name="MEM_DDR4_ODT_IN_POWERDOWN" value="true" />
+ <parameter name="MEM_DDR4_PER_DRAM_ADDR" value="false" />
+ <parameter name="MEM_DDR4_RANKS_PER_DIMM" value="2" />
+ <parameter name="MEM_DDR4_RCD_CA_IBT_ENUM" value="DDR4_RCD_CA_IBT_100" />
+ <parameter name="MEM_DDR4_RCD_CKE_IBT_ENUM">DDR4_RCD_CKE_IBT_100</parameter>
+ <parameter name="MEM_DDR4_RCD_CS_IBT_ENUM" value="DDR4_RCD_CS_IBT_100" />
+ <parameter name="MEM_DDR4_RCD_ODT_IBT_ENUM">DDR4_RCD_ODT_IBT_100</parameter>
+ <parameter name="MEM_DDR4_READ_DBI" value="false" />
+ <parameter name="MEM_DDR4_READ_PREAMBLE" value="1" />
+ <parameter name="MEM_DDR4_READ_PREAMBLE_TRAINING" value="false" />
+ <parameter name="MEM_DDR4_ROW_ADDR_WIDTH" value="15" />
+ <parameter name="MEM_DDR4_RTT_NOM_ENUM">DDR4_RTT_NOM_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_RTT_PARK">DDR4_RTT_PARK_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_RTT_WR_ENUM">DDR4_RTT_WR_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_R_ODT0_1X1" value="off" />
+ <parameter name="MEM_DDR4_R_ODT0_2X2" value="off,on" />
+ <parameter name="MEM_DDR4_R_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_R_ODT0_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR4_R_ODT1_2X2" value="on,off" />
+ <parameter name="MEM_DDR4_R_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_R_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_R_ODT2_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR4_R_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR4_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR4_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_SELF_RFSH_ABORT" value="false" />
+ <parameter name="MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB" value="0" />
+ <parameter name="MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB" value="0" />
+ <parameter name="MEM_DDR4_SPD_135_RCD_REV" value="0" />
+ <parameter name="MEM_DDR4_SPD_137_RCD_CA_DRV" value="101" />
+ <parameter name="MEM_DDR4_SPD_138_RCD_CK_DRV" value="5" />
+ <parameter name="MEM_DDR4_SPD_139_DB_REV" value="0" />
+ <parameter name="MEM_DDR4_SPD_140_DRAM_VREFDQ_R0" value="29" />
+ <parameter name="MEM_DDR4_SPD_141_DRAM_VREFDQ_R1" value="29" />
+ <parameter name="MEM_DDR4_SPD_142_DRAM_VREFDQ_R2" value="29" />
+ <parameter name="MEM_DDR4_SPD_143_DRAM_VREFDQ_R3" value="29" />
+ <parameter name="MEM_DDR4_SPD_144_DB_VREFDQ" value="37" />
+ <parameter name="MEM_DDR4_SPD_145_DB_MDQ_DRV" value="21" />
+ <parameter name="MEM_DDR4_SPD_148_DRAM_DRV" value="0" />
+ <parameter name="MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM" value="20" />
+ <parameter name="MEM_DDR4_SPD_152_DRAM_RTT_PARK" value="39" />
+ <parameter name="MEM_DDR4_SPEEDBIN_ENUM" value="DDR4_SPEEDBIN_2400" />
+ <parameter name="MEM_DDR4_TCCD_L_CYC" value="5" />
+ <parameter name="MEM_DDR4_TCCD_S_CYC" value="4" />
+ <parameter name="MEM_DDR4_TCL" value="18" />
+ <parameter name="MEM_DDR4_TDIVW_DJ_CYC" value="0.1" />
+ <parameter name="MEM_DDR4_TDIVW_TOTAL_UI" value="0.2" />
+ <parameter name="MEM_DDR4_TDQSCK_PS" value="180" />
+ <parameter name="MEM_DDR4_TDQSQ_PS" value="66" />
+ <parameter name="MEM_DDR4_TDQSQ_UI" value="0.16" />
+ <parameter name="MEM_DDR4_TDQSS_CYC" value="0.27" />
+ <parameter name="MEM_DDR4_TDSH_CYC" value="0.18" />
+ <parameter name="MEM_DDR4_TDSS_CYC" value="0.18" />
+ <parameter name="MEM_DDR4_TDVWP_UI" value="0.72" />
+ <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA" value="false" />
+ <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE">DDR4_TEMP_CONTROLLED_RFSH_NORMAL</parameter>
+ <parameter name="MEM_DDR4_TEMP_SENSOR_READOUT" value="false" />
+ <parameter name="MEM_DDR4_TFAW_DLR_CYC" value="16" />
+ <parameter name="MEM_DDR4_TFAW_NS" value="25.0" />
+ <parameter name="MEM_DDR4_TIH_DC_MV" value="75" />
+ <parameter name="MEM_DDR4_TIH_PS" value="95" />
+ <parameter name="MEM_DDR4_TINIT_US" value="500" />
+ <parameter name="MEM_DDR4_TIS_AC_MV" value="100" />
+ <parameter name="MEM_DDR4_TIS_PS" value="60" />
+ <parameter name="MEM_DDR4_TMRD_CK_CYC" value="8" />
+ <parameter name="MEM_DDR4_TQH_CYC" value="0.38" />
+ <parameter name="MEM_DDR4_TQH_UI" value="0.76" />
+ <parameter name="MEM_DDR4_TQSH_CYC" value="0.38" />
+ <parameter name="MEM_DDR4_TRAS_NS" value="33.0" />
+ <parameter name="MEM_DDR4_TRCD_NS" value="14.06" />
+ <parameter name="MEM_DDR4_TREFI_US" value="7.8" />
+ <parameter name="MEM_DDR4_TRFC_DLR_NS" value="90.0" />
+ <parameter name="MEM_DDR4_TRFC_NS" value="160.0" />
+ <parameter name="MEM_DDR4_TRP_NS" value="14.06" />
+ <parameter name="MEM_DDR4_TRRD_DLR_CYC" value="4" />
+ <parameter name="MEM_DDR4_TRRD_L_CYC" value="5" />
+ <parameter name="MEM_DDR4_TRRD_S_CYC" value="4" />
+ <parameter name="MEM_DDR4_TWLH_CYC" value="0.13" />
+ <parameter name="MEM_DDR4_TWLH_PS" value="0.0" />
+ <parameter name="MEM_DDR4_TWLS_CYC" value="0.13" />
+ <parameter name="MEM_DDR4_TWLS_PS" value="0.0" />
+ <parameter name="MEM_DDR4_TWR_NS" value="15.0" />
+ <parameter name="MEM_DDR4_TWTR_L_CYC" value="4" />
+ <parameter name="MEM_DDR4_TWTR_S_CYC" value="2" />
+ <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_RANGE">DDR4_VREFDQ_TRAINING_RANGE_1</parameter>
+ <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_VALUE" value="60.0" />
+ <parameter name="MEM_DDR4_USE_DEFAULT_ODT" value="true" />
+ <parameter name="MEM_DDR4_VDIVW_TOTAL" value="136" />
+ <parameter name="MEM_DDR4_WRITE_CRC" value="false" />
+ <parameter name="MEM_DDR4_WRITE_DBI" value="false" />
+ <parameter name="MEM_DDR4_WRITE_PREAMBLE" value="1" />
+ <parameter name="MEM_DDR4_WTCL" value="18" />
+ <parameter name="MEM_DDR4_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_DDR4_W_ODT0_2X2" value="on,on" />
+ <parameter name="MEM_DDR4_W_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT0_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODT1_2X2" value="on,on" />
+ <parameter name="MEM_DDR4_W_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT2_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR4_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR4_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_LPDDR3_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_LPDDR3_BL" value="LPDDR3_BL_BL8" />
+ <parameter name="MEM_LPDDR3_CK_WIDTH" value="1" />
+ <parameter name="MEM_LPDDR3_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_LPDDR3_DATA_LATENCY" value="LPDDR3_DL_RL12_WL6" />
+ <parameter name="MEM_LPDDR3_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_LPDDR3_DM_EN" value="true" />
+ <parameter name="MEM_LPDDR3_DQODT">LPDDR3_DQODT_DISABLE</parameter>
+ <parameter name="MEM_LPDDR3_DQ_WIDTH" value="32" />
+ <parameter name="MEM_LPDDR3_DRV_STR">LPDDR3_DRV_STR_40D_40U</parameter>
+ <parameter name="MEM_LPDDR3_PDODT">LPDDR3_PDODT_DISABLED</parameter>
+ <parameter name="MEM_LPDDR3_ROW_ADDR_WIDTH" value="15" />
+ <parameter name="MEM_LPDDR3_R_ODT0_1X1" value="off" />
+ <parameter name="MEM_LPDDR3_R_ODT0_2X2" value="off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT0_4X4" value="off,off,on,on" />
+ <parameter name="MEM_LPDDR3_R_ODT1_2X2" value="off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT1_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT2_4X4" value="on,on,off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT3_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_LPDDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_LPDDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_LPDDR3_SPEEDBIN_ENUM">LPDDR3_SPEEDBIN_1600</parameter>
+ <parameter name="MEM_LPDDR3_TDH_DC_MV" value="100" />
+ <parameter name="MEM_LPDDR3_TDH_PS" value="100" />
+ <parameter name="MEM_LPDDR3_TDQSCKDL" value="614" />
+ <parameter name="MEM_LPDDR3_TDQSQ_PS" value="135" />
+ <parameter name="MEM_LPDDR3_TDQSS_CYC" value="1.25" />
+ <parameter name="MEM_LPDDR3_TDSH_CYC" value="0.2" />
+ <parameter name="MEM_LPDDR3_TDSS_CYC" value="0.2" />
+ <parameter name="MEM_LPDDR3_TDS_AC_MV" value="150" />
+ <parameter name="MEM_LPDDR3_TDS_PS" value="75" />
+ <parameter name="MEM_LPDDR3_TFAW_NS" value="50.0" />
+ <parameter name="MEM_LPDDR3_TIH_DC_MV" value="100" />
+ <parameter name="MEM_LPDDR3_TIH_PS" value="100" />
+ <parameter name="MEM_LPDDR3_TINIT_US" value="500" />
+ <parameter name="MEM_LPDDR3_TIS_AC_MV" value="150" />
+ <parameter name="MEM_LPDDR3_TIS_PS" value="75" />
+ <parameter name="MEM_LPDDR3_TMRR_CK_CYC" value="4" />
+ <parameter name="MEM_LPDDR3_TMRW_CK_CYC" value="10" />
+ <parameter name="MEM_LPDDR3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_LPDDR3_TQSH_CYC" value="0.38" />
+ <parameter name="MEM_LPDDR3_TRAS_NS" value="42.5" />
+ <parameter name="MEM_LPDDR3_TRCD_NS" value="18.75" />
+ <parameter name="MEM_LPDDR3_TREFI_US" value="3.9" />
+ <parameter name="MEM_LPDDR3_TRFC_NS" value="210.0" />
+ <parameter name="MEM_LPDDR3_TRP_NS" value="18.75" />
+ <parameter name="MEM_LPDDR3_TRRD_CYC" value="2" />
+ <parameter name="MEM_LPDDR3_TRTP_CYC" value="4" />
+ <parameter name="MEM_LPDDR3_TWLH_PS" value="175.0" />
+ <parameter name="MEM_LPDDR3_TWLS_PS" value="175.0" />
+ <parameter name="MEM_LPDDR3_TWR_NS" value="15.0" />
+ <parameter name="MEM_LPDDR3_TWTR_CYC" value="4" />
+ <parameter name="MEM_LPDDR3_USE_DEFAULT_ODT" value="true" />
+ <parameter name="MEM_LPDDR3_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_LPDDR3_W_ODT0_2X2" value="on,off" />
+ <parameter name="MEM_LPDDR3_W_ODT0_4X4" value="on,on,on,on" />
+ <parameter name="MEM_LPDDR3_W_ODT1_2X2" value="off,on" />
+ <parameter name="MEM_LPDDR3_W_ODT1_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_W_ODT2_4X4" value="on,on,on,on" />
+ <parameter name="MEM_LPDDR3_W_ODT3_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_LPDDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_LPDDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_QDR2_ADDR_WIDTH" value="19" />
+ <parameter name="MEM_QDR2_BL" value="4" />
+ <parameter name="MEM_QDR2_BWS_EN" value="true" />
+ <parameter name="MEM_QDR2_DATA_PER_DEVICE" value="36" />
+ <parameter name="MEM_QDR2_INTERNAL_JITTER_NS" value="0.08" />
+ <parameter name="MEM_QDR2_SPEEDBIN_ENUM" value="QDR2_SPEEDBIN_633" />
+ <parameter name="MEM_QDR2_TCCQO_NS" value="0.45" />
+ <parameter name="MEM_QDR2_TCQDOH_NS" value="-0.09" />
+ <parameter name="MEM_QDR2_TCQD_NS" value="0.09" />
+ <parameter name="MEM_QDR2_TCQH_NS" value="0.71" />
+ <parameter name="MEM_QDR2_THA_NS" value="0.18" />
+ <parameter name="MEM_QDR2_THD_NS" value="0.18" />
+ <parameter name="MEM_QDR2_TRL_CYC" value="2.5" />
+ <parameter name="MEM_QDR2_TSA_NS" value="0.23" />
+ <parameter name="MEM_QDR2_TSD_NS" value="0.23" />
+ <parameter name="MEM_QDR2_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_QDR4_AC_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_ADDR_INV_ENA" value="false" />
+ <parameter name="MEM_QDR4_ADDR_WIDTH" value="21" />
+ <parameter name="MEM_QDR4_CK_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_DATA_INV_ENA" value="false" />
+ <parameter name="MEM_QDR4_DATA_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_DQ_PER_PORT_PER_DEVICE" value="36" />
+ <parameter name="MEM_QDR4_MEM_TYPE_ENUM" value="MEM_XP" />
+ <parameter name="MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+ <parameter name="MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+ <parameter name="MEM_QDR4_SKIP_ODT_SWEEPING" value="true" />
+ <parameter name="MEM_QDR4_SPEEDBIN_ENUM" value="QDR4_SPEEDBIN_2133" />
+ <parameter name="MEM_QDR4_TASH_PS" value="170" />
+ <parameter name="MEM_QDR4_TCKDK_MAX_PS" value="150" />
+ <parameter name="MEM_QDR4_TCKDK_MIN_PS" value="-150" />
+ <parameter name="MEM_QDR4_TCKQK_MAX_PS" value="225" />
+ <parameter name="MEM_QDR4_TCSH_PS" value="170" />
+ <parameter name="MEM_QDR4_TISH_PS" value="150" />
+ <parameter name="MEM_QDR4_TQH_CYC" value="0.4" />
+ <parameter name="MEM_QDR4_TQKQ_MAX_PS" value="75" />
+ <parameter name="MEM_QDR4_USE_ADDR_PARITY" value="false" />
+ <parameter name="MEM_QDR4_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD2_ADDR_WIDTH" value="21" />
+ <parameter name="MEM_RLD2_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_RLD2_BL" value="4" />
+ <parameter name="MEM_RLD2_CONFIG_ENUM">RLD2_CONFIG_TRC_8_TRL_8_TWL_9</parameter>
+ <parameter name="MEM_RLD2_DM_EN" value="true" />
+ <parameter name="MEM_RLD2_DQ_PER_DEVICE" value="9" />
+ <parameter name="MEM_RLD2_DRIVE_IMPEDENCE_ENUM">RLD2_DRIVE_IMPEDENCE_INTERNAL_50</parameter>
+ <parameter name="MEM_RLD2_ODT_MODE_ENUM" value="RLD2_ODT_ON" />
+ <parameter name="MEM_RLD2_REFRESH_INTERVAL_US" value="0.24" />
+ <parameter name="MEM_RLD2_SPEEDBIN_ENUM" value="RLD2_SPEEDBIN_18" />
+ <parameter name="MEM_RLD2_TAH_NS" value="0.3" />
+ <parameter name="MEM_RLD2_TAS_NS" value="0.3" />
+ <parameter name="MEM_RLD2_TCKDK_MAX_NS" value="0.3" />
+ <parameter name="MEM_RLD2_TCKDK_MIN_NS" value="-0.3" />
+ <parameter name="MEM_RLD2_TCKH_CYC" value="0.45" />
+ <parameter name="MEM_RLD2_TCKQK_MAX_NS" value="0.2" />
+ <parameter name="MEM_RLD2_TDH_NS" value="0.17" />
+ <parameter name="MEM_RLD2_TDS_NS" value="0.17" />
+ <parameter name="MEM_RLD2_TQKH_HCYC" value="0.9" />
+ <parameter name="MEM_RLD2_TQKQ_MAX_NS" value="0.12" />
+ <parameter name="MEM_RLD2_TQKQ_MIN_NS" value="-0.12" />
+ <parameter name="MEM_RLD2_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_ADDR_WIDTH" value="20" />
+ <parameter name="MEM_RLD3_AREF_PROTOCOL_ENUM" value="RLD3_AREF_BAC" />
+ <parameter name="MEM_RLD3_BANK_ADDR_WIDTH" value="4" />
+ <parameter name="MEM_RLD3_BL" value="2" />
+ <parameter name="MEM_RLD3_DATA_LATENCY_MODE_ENUM" value="RLD3_DL_RL16_WL17" />
+ <parameter name="MEM_RLD3_DEPTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_DM_EN" value="true" />
+ <parameter name="MEM_RLD3_DQ_PER_DEVICE" value="36" />
+ <parameter name="MEM_RLD3_ODT_MODE_ENUM" value="RLD3_ODT_40" />
+ <parameter name="MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM">RLD3_OUTPUT_DRIVE_40</parameter>
+ <parameter name="MEM_RLD3_SPEEDBIN_ENUM" value="RLD3_SPEEDBIN_093E" />
+ <parameter name="MEM_RLD3_TCKDK_MAX_CYC" value="0.27" />
+ <parameter name="MEM_RLD3_TCKDK_MIN_CYC" value="-0.27" />
+ <parameter name="MEM_RLD3_TCKQK_MAX_PS" value="135" />
+ <parameter name="MEM_RLD3_TDH_DC_MV" value="100" />
+ <parameter name="MEM_RLD3_TDH_PS" value="5" />
+ <parameter name="MEM_RLD3_TDS_AC_MV" value="150" />
+ <parameter name="MEM_RLD3_TDS_PS" value="-30" />
+ <parameter name="MEM_RLD3_TIH_DC_MV" value="100" />
+ <parameter name="MEM_RLD3_TIH_PS" value="65" />
+ <parameter name="MEM_RLD3_TIS_AC_MV" value="150" />
+ <parameter name="MEM_RLD3_TIS_PS" value="85" />
+ <parameter name="MEM_RLD3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_RLD3_TQKQ_MAX_PS" value="75" />
+ <parameter name="MEM_RLD3_T_RC_MODE_ENUM" value="RLD3_TRC_9" />
+ <parameter name="MEM_RLD3_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_WRITE_PROTOCOL_ENUM" value="RLD3_WRITE_1BANK" />
+ <parameter name="PHY_DDR3_CAL_ADDR0" value="0" />
+ <parameter name="PHY_DDR3_CAL_ADDR1" value="8" />
+ <parameter name="PHY_DDR3_CAL_ENABLE_NON_DES" value="true" />
+ <parameter name="PHY_DDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_DDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_DDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
+ <parameter name="PHY_DDR3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_DDR3_DEFAULT_REF_CLK_FREQ" value="false" />
+ <parameter name="PHY_DDR3_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_DDR3_IO_VOLTAGE" value="1.5" />
+ <parameter name="PHY_DDR3_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_DDR3_MIMIC_HPS_EMIF" value="false" />
+ <parameter name="PHY_DDR3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR3_USER_AUTO_STARTING_VREFIN_EN" value="true" />
+ <parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_DLL_CORE_UPDN_EN" value="true" />
+ <parameter name="PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_DDR3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_REF_CLK_FREQ_MHZ" value="133.333" />
+ <parameter name="PHY_DDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_STARTING_VREFIN" value="70.0" />
+ <parameter name="PHY_DDR4_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_DDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_DDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
+ <parameter name="PHY_DDR4_DEFAULT_IO" value="true" />
+ <parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="false" />
+ <parameter name="PHY_DDR4_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_DDR4_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="1200.0" />
+ <parameter name="PHY_DDR4_MIMIC_HPS_EMIF" value="false" />
+ <parameter name="PHY_DDR4_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_DDR4_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR4_USER_AUTO_STARTING_VREFIN_EN" value="true" />
+ <parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR4_USER_CLAMSHELL_EN" value="false" />
+ <parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_DLL_CORE_UPDN_EN" value="true" />
+ <parameter name="PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_DDR4_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_REF_CLK_FREQ_MHZ" value="25.0" />
+ <parameter name="PHY_DDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_STARTING_VREFIN" value="70.0" />
+ <parameter name="PHY_LPDDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_LPDDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_LPDDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
+ <parameter name="PHY_LPDDR3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_LPDDR3_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_LPDDR3_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_LPDDR3_MEM_CLK_FREQ_MHZ" value="800.0" />
+ <parameter name="PHY_LPDDR3_MIMIC_HPS_EMIF" value="false" />
+ <parameter name="PHY_LPDDR3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_LPDDR3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_LPDDR3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_LPDDR3_USER_AUTO_STARTING_VREFIN_EN" value="true" />
+ <parameter name="PHY_LPDDR3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_LPDDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_DLL_CORE_UPDN_EN" value="false" />
+ <parameter name="PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_LPDDR3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_LPDDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_STARTING_VREFIN" value="70.0" />
+ <parameter name="PHY_QDR2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_QDR2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_QDR2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
+ <parameter name="PHY_QDR2_DEFAULT_IO" value="true" />
+ <parameter name="PHY_QDR2_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_QDR2_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_QDR2_IO_VOLTAGE" value="1.5" />
+ <parameter name="PHY_QDR2_MEM_CLK_FREQ_MHZ" value="633.333" />
+ <parameter name="PHY_QDR2_MIMIC_HPS_EMIF" value="false" />
+ <parameter name="PHY_QDR2_RATE_ENUM" value="RATE_HALF" />
+ <parameter name="PHY_QDR2_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_QDR2_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR2_USER_AUTO_STARTING_VREFIN_EN" value="true" />
+ <parameter name="PHY_QDR2_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR2_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_DLL_CORE_UPDN_EN" value="false" />
+ <parameter name="PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_QDR2_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_QDR2_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_STARTING_VREFIN" value="70.0" />
+ <parameter name="PHY_QDR4_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_QDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_QDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
+ <parameter name="PHY_QDR4_DEFAULT_IO" value="true" />
+ <parameter name="PHY_QDR4_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_QDR4_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_QDR4_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_QDR4_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_QDR4_MIMIC_HPS_EMIF" value="false" />
+ <parameter name="PHY_QDR4_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_QDR4_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_QDR4_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR4_USER_AUTO_STARTING_VREFIN_EN" value="true" />
+ <parameter name="PHY_QDR4_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_DLL_CORE_UPDN_EN" value="true" />
+ <parameter name="PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_QDR4_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_QDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_STARTING_VREFIN" value="70.0" />
+ <parameter name="PHY_RLD2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_RLD2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_RLD2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
+ <parameter name="PHY_RLD2_DEFAULT_IO" value="true" />
+ <parameter name="PHY_RLD2_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_RLD2_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_RLD2_IO_VOLTAGE" value="1.8" />
+ <parameter name="PHY_RLD2_MEM_CLK_FREQ_MHZ" value="533.333" />
+ <parameter name="PHY_RLD2_MIMIC_HPS_EMIF" value="false" />
+ <parameter name="PHY_RLD2_RATE_ENUM" value="RATE_HALF" />
+ <parameter name="PHY_RLD2_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_RLD2_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD2_USER_AUTO_STARTING_VREFIN_EN" value="true" />
+ <parameter name="PHY_RLD2_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD2_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_DLL_CORE_UPDN_EN" value="false" />
+ <parameter name="PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_RLD2_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_RLD2_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_STARTING_VREFIN" value="70.0" />
+ <parameter name="PHY_RLD3_CONFIG_ENUM" value="CONFIG_PHY_ONLY" />
+ <parameter name="PHY_RLD3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_RLD3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT" value="false" />
+ <parameter name="PHY_RLD3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_RLD3_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_RLD3_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_RLD3_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_RLD3_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_RLD3_MIMIC_HPS_EMIF" value="false" />
+ <parameter name="PHY_RLD3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_RLD3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_RLD3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD3_USER_AUTO_STARTING_VREFIN_EN" value="true" />
+ <parameter name="PHY_RLD3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_DLL_CORE_UPDN_EN" value="false" />
+ <parameter name="PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_RLD3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_STARTING_VREFIN" value="70.0" />
+ <parameter name="PLL_ADD_EXTRA_CLKS" value="false" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_0" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_1" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_2" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_3" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_4" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_0" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_1" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_2" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_3" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_4" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8" value="0" />
+ <parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
+ <parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
+ <parameter name="SHORT_QSYS_INTERFACE_NAMES" value="false" />
+ <parameter name="SYS_INFO_DEVICE" value="10AX115U3F45E2SG" />
+ <parameter name="SYS_INFO_DEVICE_DIE_REVISIONS" value="" />
+ <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="SYS_INFO_DEVICE_POWER_MODEL" value="STANDARD" />
+ <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="SYS_INFO_DEVICE_TEMPERATURE_GRADE" value="EXTENDED" />
+ <parameter name="SYS_INFO_UNIQUE_ID">ip_arria10_e2sg_ddr4_8g_2400_ddr4_inst</parameter>
+ <parameter name="TRAIT_SUPPORTS_VID" value="0" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/eth_10g/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/eth_10g/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..97af5290d9a650ef154e0792455d5e9f0ed734cd
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/eth_10g/hdllib.cfg
@@ -0,0 +1,15 @@
+hdl_lib_name = ip_arria10_e2sg_eth_10g
+hdl_library_clause_name = ip_arria10_e2sg_eth_10g_lib
+hdl_lib_uses_synth = technology tech_pll tech_mac_10g tech_10gbase_r common dp
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+ ip_arria10_e2sg_eth_10g.vhd
+
+test_bench_files =
+
+[modelsim_project_file]
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_arria10_e2sg/eth_10g/ip_arria10_e2sg_eth_10g.vhd b/libraries/technology/ip_arria10_e2sg/eth_10g/ip_arria10_e2sg_eth_10g.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..85914052e686eabfef3bed39a8870ac6b0e50617
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/eth_10g/ip_arria10_e2sg_eth_10g.vhd
@@ -0,0 +1,334 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+
+-- Purpose: Combine mac_10g and 10gbase_r for c_tech_arria10_e2sg
+-- Description
+--
+-- The clocks come from an external central fPLL:
+--
+-- tx_ref_clk_644 --> fPLL --> clk_312
+-- clk_156, rst_156
+-- Blockdiagram:
+--
+-- 312 156 644
+-- _________ | | | ____________
+-- | | | | | | |
+-- | |<--/ | \-->| |
+-- | |<-----+----->| |
+-- | | | |
+-- | | XGMII | |
+-- tx_snk --->|tech_ |------------>|tech_ |---> serial_tx
+-- rx_src <---|mac_10g|<------------|10gbase_r |<--- serial_rx
+-- | | | |
+-- |_______|--\ /--|__________|
+-- | | |
+-- mac_mm | |
+-- | v
+-- ( v xgmii_tx_ready)
+-- tx_snk_out.xon <--(xgmii_link_status[1:0])
+--
+-- . g_direction:
+-- "TX_RX" = Default support bidir
+-- "TX_ONLY" = Uses a bidir MAC and connects the MAC Tx to the MAC RX.
+-- "RX_ONLY" = Same as "TX_RX"
+-- See tech_eth_10g_stratixiv.vhd for more details.
+--
+-- Remarks:
+-- . xgmii_link_status:
+-- When the xgmii_tx_ready from the 10gbase_r and the xgmii_link_status from
+-- the mac_10g are both be OK then the tx_snk.xon is asserted to allow the
+-- user data transmission.
+-- The tb_tech_eth_10g reveals that xgmii_tx_ready goes high after some power
+-- up time and then remains active independent of link_fault.
+-- A link fault eg. due to rx disconnect is detected by the link fault status:
+-- 0 = OK
+-- 1 = local fault
+-- 2 = remote fault
+--
+-- From google search:
+-- Link fault Operation
+-- 1) Device B detects loss of signal. Local fault is signaled by PHY of Device B to Device B.
+-- 2) Device B ceases transmission of MAC frames and transmits remote fault to Device A.
+-- 3) Device A receives remote fault from Device B.
+-- 4) Device A stops sending frames, continuously generates Idle.
+--
+-- Hence when the xgmii_link_status is OK then the other side is also OK so
+-- then it is also appropriate to release tx_snk.xon.
+--
+-- The XGMII link status can be monitored via the reg_eth10 MM register:
+--
+-- addr data[31:0]
+-- 0 [0] = tx_snk_out_arr(I).xon
+-- [1] = xgmii_tx_ready_arr(I)
+-- [3:2] = xgmii_link_status_arr(I)
+--
+
+LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_10gbase_r_lib, tech_mac_10g_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
+
+ENTITY ip_arria10_e2sg_eth_10g IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
+ g_nof_channels : NATURAL := 1;
+ g_direction : STRING := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_use_loopback : BOOLEAN := FALSE;
+ g_pre_header_padding : BOOLEAN := FALSE
+ );
+ PORT (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 : IN STD_LOGIC := '0'; -- 644.531250 MHz for 10GBASE-R
+
+ -- Data clocks
+ clk_312 : IN STD_LOGIC := '0';
+ clk_156 : IN STD_LOGIC := '0';
+ rst_156 : IN STD_LOGIC := '0';
+
+ -- MM
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+
+ mac_mosi : IN t_mem_mosi; -- MAG_10G (CSR)
+ mac_miso : OUT t_mem_miso;
+
+ reg_eth10g_mosi : IN t_mem_mosi; -- ETH10G (link status register)
+ reg_eth10g_miso : OUT t_mem_miso;
+
+ reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_ip_arria10_e2sg_phy_10gbase_r_24_miso : OUT t_mem_miso;
+
+ -- ST
+ tx_snk_in_arr : IN t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156
+ tx_snk_out_arr : OUT t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156
+ rx_src_in_arr : IN t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ -- Serial
+ serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+ );
+END ip_arria10_e2sg_eth_10g;
+
+
+ARCHITECTURE str OF ip_arria10_e2sg_eth_10g IS
+
+ -- Enable or disable the conditions that must be ok to release tx_snk_out_arr xon
+ CONSTANT c_check_link_status : BOOLEAN := TRUE; --g_direction/="TX_ONLY";
+ CONSTANT c_check_xgmii_tx_ready : BOOLEAN := TRUE; --g_direction/="RX_ONLY";
+
+ SIGNAL i_tx_snk_out_arr : t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ -- MAG_10G control status registers
+ SIGNAL mac_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
+ SIGNAL mac_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
+
+ -- XON control
+ SIGNAL mac_snk_out_arr : t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ -- XGMII
+ SIGNAL xgmii_link_status_arr : t_tech_mac_10g_xgmii_status_arr(g_nof_channels-1 DOWNTO 0); -- 2 bit, from MAC_10g
+ SIGNAL xgmii_tx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- 1 bit, from PHY 10gbase_r
+ SIGNAL xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
+ SIGNAL xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
+ SIGNAL xgmii_tx_dc_arr_loopback : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
+ SIGNAL xgmii_rx_dc_arr_loopback : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
+ SIGNAL xgmii_internal_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
+
+ -- Link status monitor
+ CONSTANT c_mem_reg_eth10g_adr_w : NATURAL := 1;
+ CONSTANT c_mem_reg_eth10g_dat_w : NATURAL := 32;
+ CONSTANT c_mem_reg_eth10g_nof_data : NATURAL := 1;
+ CONSTANT c_mem_reg_eth10g : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_eth10g_adr_w , c_mem_reg_eth10g_dat_w , c_mem_reg_eth10g_nof_data, 'X');
+
+ SIGNAL reg_eth10g_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
+ SIGNAL reg_eth10g_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
+
+ SIGNAL mm_reg_eth10g_arr : t_slv_32_arr(g_nof_channels-1 DOWNTO 0);
+
+BEGIN
+ tx_snk_out_arr <= i_tx_snk_out_arr;
+
+ gen_mac : FOR I IN 0 TO g_nof_channels-1 GENERATE
+
+ i_tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready; -- pass on MAC cycle accurate backpressure
+
+ p_xon_flow_control : PROCESS(clk_156)
+ VARIABLE v_xgmii_link_status : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "00";
+ VARIABLE v_xgmii_tx_ready : STD_LOGIC := '1';
+ BEGIN
+ IF rising_edge(clk_156) THEN
+ i_tx_snk_out_arr(I).xon <= '0';
+
+ -- First gather all conditions that are enabled to affect xon. The default value is such that it enables xon when the condition is not checked.
+ IF c_check_link_status =TRUE THEN v_xgmii_link_status := xgmii_link_status_arr(I); END IF; -- check both remote fault [1] and local fault [0]
+ IF c_check_xgmii_tx_ready=TRUE THEN v_xgmii_tx_ready := xgmii_tx_ready_arr(I); END IF;
+
+ -- Now apply the conditions to xon
+ IF v_xgmii_tx_ready='1' AND v_xgmii_link_status="00" THEN
+ i_tx_snk_out_arr(I).xon <= '1'; -- XON when Tx PHY is ready and XGMII is ok
+ END IF;
+ END IF;
+ END PROCESS;
+
+ u_tech_mac_10g : ENTITY tech_mac_10g_lib.tech_mac_10g
+ GENERIC MAP (
+ g_technology => c_tech_arria10_e2sg,
+ g_pre_header_padding => g_pre_header_padding
+ )
+ PORT MAP (
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ csr_mosi => mac_mosi_arr(I),
+ csr_miso => mac_miso_arr(I),
+
+ -- ST
+ tx_clk_312 => clk_312,
+ tx_clk_156 => clk_156,
+ tx_rst => rst_156,
+ tx_snk_in => tx_snk_in_arr(I), -- 64 bit data
+ tx_snk_out => mac_snk_out_arr(I),
+
+ rx_clk_312 => clk_312,
+ rx_clk_156 => clk_156,
+ rx_rst => rst_156,
+ rx_src_out => rx_src_out_arr(I), -- 64 bit data
+ rx_src_in => rx_src_in_arr(I),
+
+ -- XGMII
+ xgmii_link_status => xgmii_link_status_arr(I),
+ xgmii_tx_data => xgmii_tx_dc_arr(I),
+ xgmii_rx_data => xgmii_internal_dc_arr(I)
+ );
+ END GENERATE;
+
+ xgmii_internal_dc_arr <= xgmii_tx_dc_arr WHEN g_direction="TX_ONLY" ELSE xgmii_rx_dc_arr;
+
+ u_tech_10gbase_r: ENTITY tech_10gbase_r_lib.tech_10gbase_r
+ GENERIC MAP (
+ g_technology => c_tech_arria10_e2sg,
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_nof_channels => g_nof_channels
+ )
+ PORT MAP (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi => reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi,
+ reg_ip_arria10_e2sg_phy_10gbase_r_24_miso => reg_ip_arria10_e2sg_phy_10gbase_r_24_miso,
+
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => tr_ref_clk_644,
+
+ -- XGMII clocks
+ clk_156 => clk_156,
+ rst_156 => rst_156,
+
+ -- XGMII interface
+ xgmii_tx_ready_arr => xgmii_tx_ready_arr,
+ xgmii_rx_ready_arr => OPEN,
+ xgmii_tx_dc_arr => xgmii_tx_dc_arr_loopback,
+ xgmii_rx_dc_arr => xgmii_rx_dc_arr_loopback,
+
+ -- PHY serial IO
+ tx_serial_arr => serial_tx_arr,
+ rx_serial_arr => serial_rx_arr
+ );
+
+ gen_loopback : IF g_use_loopback = TRUE GENERATE
+ xgmii_tx_dc_arr_loopback <= xgmii_rx_dc_arr_loopback;
+ END GENERATE;
+
+ gen_forward : IF g_use_loopback = FALSE GENERATE
+ xgmii_tx_dc_arr_loopback <= xgmii_tx_dc_arr;
+ xgmii_rx_dc_arr <= xgmii_rx_dc_arr_loopback;
+ END GENERATE;
+
+ gen_reg_eth10g : FOR I IN 0 TO g_nof_channels-1 GENERATE
+ mm_reg_eth10g_arr(I) <= RESIZE_UVEC(xgmii_link_status_arr(I) & xgmii_tx_ready_arr(I) & i_tx_snk_out_arr(I).xon, c_mem_reg_eth10g_dat_w);
+
+ u_reg_map : ENTITY common_lib.common_reg_r_w_dc
+ GENERIC MAP (
+ g_cross_clock_domain => TRUE,
+ g_in_new_latency => 0,
+ g_readback => FALSE,
+ g_reg => c_mem_reg_eth10g,
+ g_init_reg => (OTHERS => '0')
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => rst_156,
+ st_clk => clk_156,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_eth10g_mosi_arr(I),
+ sla_out => reg_eth10g_miso_arr(I),
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_new => '1',
+ in_reg => mm_reg_eth10g_arr(I),
+ out_reg => OPEN
+ );
+ END GENERATE;
+
+
+ -----------------------------------------------------------------------------
+ -- MM bus mux
+ -----------------------------------------------------------------------------
+ u_common_mem_mux_mac : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_channels,
+ g_mult_addr_w => func_tech_mac_10g_csr_addr_w(c_tech_arria10)
+ )
+ PORT MAP (
+ mosi => mac_mosi,
+ miso => mac_miso,
+ mosi_arr => mac_mosi_arr,
+ miso_arr => mac_miso_arr
+ );
+
+ u_common_mem_mux_eth10g : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_channels,
+ g_mult_addr_w => c_mem_reg_eth10g_adr_w
+ )
+ PORT MAP (
+ mosi => reg_eth10g_mosi,
+ miso => reg_eth10g_miso,
+ mosi_arr => reg_eth10g_mosi_arr,
+ miso_arr => reg_eth10g_miso_arr
+ );
+
+END str;
diff --git a/libraries/technology/ip_arria10_e2sg/fifo/README.txt b/libraries/technology/ip_arria10_e2sg/fifo/README.txt
new file mode 100755
index 0000000000000000000000000000000000000000..6db25b6412e89ebde6decb09c13f7e14890315b0
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/fifo/README.txt
@@ -0,0 +1,61 @@
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/fifo
+
+Contents:
+
+1) FIFO components
+2) Arria10 IP
+3) Implementation options (LUTs or block RAM)
+4) Synthesis trials
+5) Issues
+
+
+1) FIFO components:
+
+ ip_arria10_fifo_sc = Single clock FIFO
+ ip_arria10_fifo_dc = Dual clock FIFO
+ ip_arria10_fifo_dc_mixed_widths = Dual clock FIFO with different read and write data widths (ratio power of 2)
+
+
+2) Arria10 IP
+
+ The IP was ported from Stratix IV by:
+
+ . copy original MegaWizard <fifo_name>.vhd file
+ . rename <fifo_name>.vhd into ip_arria10_<fifo_name>.vhd (also replace name inside the file)
+ . commit the fifo/ip_arria10_<fifo_name>.vhd to preserve the MegaWizard original
+ . open in to Quartus 14, set device family to Arria10 and finish automatically convert to Qsys
+ . then generate HDL (select VHDL for both sim and synth) and finish to save it as ip_arria10_<fifo_name>.qsys
+
+ this yields:
+
+ ip_arria10_fifo_sc.qsys
+ ip_arria10_fifo_dc.qsys
+ ip_arria10_fifo_dc_mixed_widths.qsys
+
+ The Arria10 FIFO IP still uses the altera_mf package (so not the altera_lnsim package as with the block RAM). The
+ FIFOs map to the altera_mf components to scfifo, dcfifo and dcfifo_mixed_widths.
+
+ The IP only needs to be generated with ./generate_ip.sh if it need to be modified, because the ip_arria10_fifo_*.vhd
+ directly instantiates the altera_mf component.
+
+ The instantiation is copied manually from the ip_arria10_fifo_*/fifo_140/sim/ip_arria10_fifo_*.vhd and
+ saved in the <fifo_name>.vhd file. So then the MegaWizard vhd file is overwritten, but that is fine because it is
+ no longer needed, it could easily be derived from the original in $UNB and it is still as a previous verion in SVN.
+
+
+3) Implementation options (LUTs or block RAM)
+
+ The IP FIFO can be set to use LUTs (MLAB) or block RAM (M20K) via g_use_eab.
+
+
+4) Synthesis trials
+
+ The quartus/fifo.qpf Quartus project was used to verify that the FIFO IP actually synthesise to the appropriate FPGA resources.
+ Use the Quartus GUI to manually select a top level component for synthesis e.g. by right clicking the entity vhd file
+ in the file tab of the Quartus project navigator window.
+ Then check the resource usage in the synthesis and fitter reports.
+
+
+5) Issues
+
+ No issues.
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/fifo/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/fifo/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..cfdb7ced1c47403f0dc45dafd552fdbfadf2e064
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/fifo/hdllib.cfg
@@ -0,0 +1,26 @@
+hdl_lib_name = ip_arria10_e2sg_fifo
+hdl_library_clause_name = ip_arria10_e2sg_fifo_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+ ip_arria10_e2sg_fifo_sc.vhd
+ ip_arria10_e2sg_fifo_dc.vhd
+ ip_arria10_e2sg_fifo_dc_mixed_widths.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_fifo_sc.qsys
+ ip_arria10_e2sg_fifo_dc.qsys
+ ip_arria10_e2sg_fifo_dc_mixed_widths.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc.qsys b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..9fa1571d8f111b68e4ed6aabd5909b43bb20d67f
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc.qsys
@@ -0,0 +1,116 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_fifo_dc">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element ip_arria10_fifo_dc
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="fifo_input"
+ internal="ip_arria10_fifo_dc.fifo_input"
+ type="conduit"
+ dir="end">
+ <port name="aclr" internal="aclr" />
+ <port name="data" internal="data" />
+ <port name="rdclk" internal="rdclk" />
+ <port name="rdreq" internal="rdreq" />
+ <port name="wrclk" internal="wrclk" />
+ <port name="wrreq" internal="wrreq" />
+ </interface>
+ <interface
+ name="fifo_output"
+ internal="ip_arria10_fifo_dc.fifo_output"
+ type="conduit"
+ dir="end">
+ <port name="q" internal="q" />
+ <port name="rdempty" internal="rdempty" />
+ <port name="rdusedw" internal="rdusedw" />
+ <port name="wrfull" internal="wrfull" />
+ <port name="wrusedw" internal="wrusedw" />
+ </interface>
+ <module
+ name="ip_arria10_fifo_dc"
+ kind="fifo"
+ version="19.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_AlmostEmpty" value="false" />
+ <parameter name="GUI_AlmostEmptyThr" value="-1" />
+ <parameter name="GUI_AlmostFull" value="false" />
+ <parameter name="GUI_AlmostFullThr" value="-1" />
+ <parameter name="GUI_CLOCKS_ARE_SYNCHRONIZED" value="0" />
+ <parameter name="GUI_Clock" value="4" />
+ <parameter name="GUI_DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT" value="true" />
+ <parameter name="GUI_Depth" value="256" />
+ <parameter name="GUI_ENABLE_ECC" value="false" />
+ <parameter name="GUI_Empty" value="true" />
+ <parameter name="GUI_Full" value="true" />
+ <parameter name="GUI_LE_BasedFIFO" value="false" />
+ <parameter name="GUI_LegacyRREQ" value="1" />
+ <parameter name="GUI_MAX_DEPTH" value="Auto" />
+ <parameter name="GUI_MAX_DEPTH_BY_9" value="false" />
+ <parameter name="GUI_OVERFLOW_CHECKING" value="false" />
+ <parameter name="GUI_Optimize" value="1" />
+ <parameter name="GUI_Optimize_max" value="1" />
+ <parameter name="GUI_RAM_BLOCK_TYPE" value="Auto" />
+ <parameter name="GUI_TESTBENCH" value="false" />
+ <parameter name="GUI_UNDERFLOW_CHECKING" value="false" />
+ <parameter name="GUI_UsedW" value="true" />
+ <parameter name="GUI_Width" value="8" />
+ <parameter name="GUI_dc_aclr" value="true" />
+ <parameter name="GUI_delaypipe" value="5" />
+ <parameter name="GUI_diff_widths" value="false" />
+ <parameter name="GUI_msb_usedw" value="false" />
+ <parameter name="GUI_output_width" value="8" />
+ <parameter name="GUI_read_aclr_synch" value="false" />
+ <parameter name="GUI_rsEmpty" value="true" />
+ <parameter name="GUI_rsFull" value="false" />
+ <parameter name="GUI_rsUsedW" value="true" />
+ <parameter name="GUI_sc_aclr" value="false" />
+ <parameter name="GUI_sc_sclr" value="false" />
+ <parameter name="GUI_synStage" value="3" />
+ <parameter name="GUI_write_aclr_synch" value="true" />
+ <parameter name="GUI_wsEmpty" value="false" />
+ <parameter name="GUI_wsFull" value="true" />
+ <parameter name="GUI_wsUsedW" value="true" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc.vhd b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d821610dd15fd7c4a384202f67ff952dc1dd1ed5
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc.vhd
@@ -0,0 +1,122 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Instantiate FIFO IP with generics
+-- Description:
+-- Copied component declaration and instance example from generated/fifo_140/sim/ip_arria10_e2sg_fifo_dc_fifo_140_c4o7vda.vhd
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY technology_lib;
+USE technology_lib.technology_pkg.ALL;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY ip_arria10_e2sg_fifo_dc IS
+ GENERIC (
+ g_use_eab : STRING := "ON";
+ g_dat_w : NATURAL := 20;
+ g_nof_words : NATURAL := 1024
+ );
+ PORT (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
+ wrfull : OUT STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+END ip_arria10_e2sg_fifo_dc;
+
+
+ARCHITECTURE SYN OF ip_arria10_e2sg_fifo_dc IS
+
+ COMPONENT dcfifo
+ GENERIC (
+ intended_device_family : STRING;
+ lpm_numwords : NATURAL;
+ lpm_showahead : STRING;
+ lpm_type : STRING;
+ lpm_width : NATURAL;
+ lpm_widthu : NATURAL;
+ overflow_checking : STRING;
+ rdsync_delaypipe : NATURAL;
+ read_aclr_synch : STRING;
+ underflow_checking : STRING;
+ use_eab : STRING;
+ write_aclr_synch : STRING;
+ wrsync_delaypipe : NATURAL
+ );
+ PORT (
+ aclr : IN STD_LOGIC;
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC;
+ rdreq : IN STD_LOGIC;
+ wrclk : IN STD_LOGIC;
+ wrreq : IN STD_LOGIC;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdempty : OUT STD_LOGIC;
+ rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
+ wrfull : OUT STD_LOGIC;
+ wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+BEGIN
+
+ u_dcfifo : dcfifo
+ GENERIC MAP (
+ intended_device_family => "Arria 10",
+ lpm_numwords => g_nof_words,
+ lpm_showahead => "OFF",
+ lpm_type => "dcfifo",
+ lpm_width => g_dat_w,
+ lpm_widthu => tech_ceil_log2(g_nof_words),
+ overflow_checking => "ON",
+ rdsync_delaypipe => 5,
+ read_aclr_synch => "OFF",
+ underflow_checking => "ON",
+ use_eab => g_use_eab,
+ write_aclr_synch => "ON",
+ wrsync_delaypipe => 5
+ )
+ PORT MAP (
+ aclr => aclr,
+ data => data,
+ rdclk => rdclk,
+ rdreq => rdreq,
+ wrclk => wrclk,
+ wrreq => wrreq,
+ q => q,
+ rdempty => rdempty,
+ rdusedw => rdusedw,
+ wrfull => wrfull,
+ wrusedw => wrusedw
+ );
+
+END SYN;
diff --git a/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc_mixed_widths.qsys b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc_mixed_widths.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..fb54d0ccd51d0ecc710cf4cd14f1c3b2533bc487
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc_mixed_widths.qsys
@@ -0,0 +1,116 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_fifo_dc_mixed_widths">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element ip_arria10_fifo_dc_mixed_widths
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="fifo_input"
+ internal="ip_arria10_fifo_dc_mixed_widths.fifo_input"
+ type="conduit"
+ dir="end">
+ <port name="aclr" internal="aclr" />
+ <port name="data" internal="data" />
+ <port name="rdclk" internal="rdclk" />
+ <port name="rdreq" internal="rdreq" />
+ <port name="wrclk" internal="wrclk" />
+ <port name="wrreq" internal="wrreq" />
+ </interface>
+ <interface
+ name="fifo_output"
+ internal="ip_arria10_fifo_dc_mixed_widths.fifo_output"
+ type="conduit"
+ dir="end">
+ <port name="q" internal="q" />
+ <port name="rdempty" internal="rdempty" />
+ <port name="rdusedw" internal="rdusedw" />
+ <port name="wrfull" internal="wrfull" />
+ <port name="wrusedw" internal="wrusedw" />
+ </interface>
+ <module
+ name="ip_arria10_fifo_dc_mixed_widths"
+ kind="fifo"
+ version="19.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_AlmostEmpty" value="false" />
+ <parameter name="GUI_AlmostEmptyThr" value="-1" />
+ <parameter name="GUI_AlmostFull" value="false" />
+ <parameter name="GUI_AlmostFullThr" value="-1" />
+ <parameter name="GUI_CLOCKS_ARE_SYNCHRONIZED" value="0" />
+ <parameter name="GUI_Clock" value="4" />
+ <parameter name="GUI_DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT" value="true" />
+ <parameter name="GUI_Depth" value="256" />
+ <parameter name="GUI_ENABLE_ECC" value="false" />
+ <parameter name="GUI_Empty" value="true" />
+ <parameter name="GUI_Full" value="true" />
+ <parameter name="GUI_LE_BasedFIFO" value="false" />
+ <parameter name="GUI_LegacyRREQ" value="1" />
+ <parameter name="GUI_MAX_DEPTH" value="Auto" />
+ <parameter name="GUI_MAX_DEPTH_BY_9" value="false" />
+ <parameter name="GUI_OVERFLOW_CHECKING" value="false" />
+ <parameter name="GUI_Optimize" value="1" />
+ <parameter name="GUI_Optimize_max" value="1" />
+ <parameter name="GUI_RAM_BLOCK_TYPE" value="Auto" />
+ <parameter name="GUI_TESTBENCH" value="false" />
+ <parameter name="GUI_UNDERFLOW_CHECKING" value="false" />
+ <parameter name="GUI_UsedW" value="true" />
+ <parameter name="GUI_Width" value="8" />
+ <parameter name="GUI_dc_aclr" value="true" />
+ <parameter name="GUI_delaypipe" value="5" />
+ <parameter name="GUI_diff_widths" value="true" />
+ <parameter name="GUI_msb_usedw" value="false" />
+ <parameter name="GUI_output_width" value="16" />
+ <parameter name="GUI_read_aclr_synch" value="false" />
+ <parameter name="GUI_rsEmpty" value="true" />
+ <parameter name="GUI_rsFull" value="false" />
+ <parameter name="GUI_rsUsedW" value="true" />
+ <parameter name="GUI_sc_aclr" value="false" />
+ <parameter name="GUI_sc_sclr" value="false" />
+ <parameter name="GUI_synStage" value="3" />
+ <parameter name="GUI_write_aclr_synch" value="true" />
+ <parameter name="GUI_wsEmpty" value="false" />
+ <parameter name="GUI_wsFull" value="true" />
+ <parameter name="GUI_wsUsedW" value="true" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc_mixed_widths.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6c0da7b2295fd43f46aedbc0ef8f38e2b5d6c08a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc_mixed_widths.vhd
@@ -0,0 +1,126 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Instantiate FIFO IP with generics
+-- Description:
+-- Copied component declaration and instance example from generated/fifo_140/sim/ip_arria10_e2sg_fifo_dc_mixed_widths_fifo_140_5csdcfa.vhd
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY technology_lib;
+USE technology_lib.technology_pkg.ALL;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY ip_arria10_e2sg_fifo_dc_mixed_widths IS
+ GENERIC (
+ g_nof_words : NATURAL := 1024; -- FIFO size in nof wr_dat words
+ g_wrdat_w : NATURAL := 20;
+ g_rddat_w : NATURAL := 10
+ );
+ PORT (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
+ wrfull : OUT STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+END ip_arria10_e2sg_fifo_dc_mixed_widths;
+
+
+ARCHITECTURE SYN OF ip_arria10_e2sg_fifo_dc_mixed_widths IS
+
+ COMPONENT dcfifo_mixed_widths
+ GENERIC (
+ intended_device_family : STRING;
+ lpm_numwords : NATURAL;
+ lpm_showahead : STRING;
+ lpm_type : STRING;
+ lpm_width : NATURAL;
+ lpm_widthu : NATURAL;
+ lpm_widthu_r : NATURAL;
+ lpm_width_r : NATURAL;
+ overflow_checking : STRING;
+ rdsync_delaypipe : NATURAL;
+ read_aclr_synch : STRING;
+ underflow_checking : STRING;
+ use_eab : STRING;
+ write_aclr_synch : STRING;
+ wrsync_delaypipe : NATURAL
+ );
+ PORT (
+ aclr : IN STD_LOGIC;
+ data : IN STD_LOGIC_VECTOR (data'RANGE);
+ rdclk : IN STD_LOGIC;
+ rdreq : IN STD_LOGIC;
+ wrclk : IN STD_LOGIC;
+ wrreq : IN STD_LOGIC;
+ q : OUT STD_LOGIC_VECTOR (q'RANGE);
+ rdempty : OUT STD_LOGIC;
+ rdusedw : OUT STD_LOGIC_VECTOR (rdusedw'RANGE);
+ wrfull : OUT STD_LOGIC;
+ wrusedw : OUT STD_LOGIC_VECTOR (wrusedw'RANGE)
+ );
+ END COMPONENT;
+
+BEGIN
+
+ dcfifo_mixed_widths_component : dcfifo_mixed_widths
+ GENERIC MAP (
+ intended_device_family => "Arria 10",
+ lpm_numwords => g_nof_words,
+ lpm_showahead => "OFF",
+ lpm_type => "dcfifo_mixed_widths",
+ lpm_width => g_wrdat_w,
+ lpm_widthu => tech_ceil_log2(g_nof_words),
+ lpm_widthu_r => tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w),
+ lpm_width_r => g_rddat_w,
+ overflow_checking => "ON",
+ rdsync_delaypipe => 5,
+ read_aclr_synch => "OFF",
+ underflow_checking => "ON",
+ use_eab => "ON",
+ write_aclr_synch => "ON",
+ wrsync_delaypipe => 5
+ )
+ PORT MAP (
+ aclr => aclr,
+ data => data,
+ rdclk => rdclk,
+ rdreq => rdreq,
+ wrclk => wrclk,
+ wrreq => wrreq,
+ q => q,
+ rdempty => rdempty,
+ rdusedw => rdusedw,
+ wrfull => wrfull,
+ wrusedw => wrusedw
+ );
+
+END SYN;
diff --git a/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_sc.qsys b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_sc.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..a59de97d75abf48abd525a1fd3d0d25542324d5a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_sc.qsys
@@ -0,0 +1,111 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_fifo_sc">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation"
+ categories="System"
+ tool="QsysPro" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element ip_arria10_fifo_sc
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="fifo_input"
+ internal="ip_arria10_fifo_sc.fifo_input"
+ type="conduit"
+ dir="end">
+ <port name="aclr" internal="aclr" />
+ <port name="clock" internal="clock" />
+ <port name="data" internal="data" />
+ <port name="rdreq" internal="rdreq" />
+ <port name="wrreq" internal="wrreq" />
+ </interface>
+ <interface
+ name="fifo_output"
+ internal="ip_arria10_fifo_sc.fifo_output"
+ type="conduit"
+ dir="end">
+ <port name="empty" internal="empty" />
+ <port name="full" internal="full" />
+ <port name="q" internal="q" />
+ <port name="usedw" internal="usedw" />
+ </interface>
+ <module
+ name="ip_arria10_fifo_sc"
+ kind="fifo"
+ version="19.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_AlmostEmpty" value="false" />
+ <parameter name="GUI_AlmostEmptyThr" value="-1" />
+ <parameter name="GUI_AlmostFull" value="false" />
+ <parameter name="GUI_AlmostFullThr" value="-1" />
+ <parameter name="GUI_CLOCKS_ARE_SYNCHRONIZED" value="1" />
+ <parameter name="GUI_Clock" value="0" />
+ <parameter name="GUI_DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT" value="true" />
+ <parameter name="GUI_Depth" value="256" />
+ <parameter name="GUI_ENABLE_ECC" value="false" />
+ <parameter name="GUI_Empty" value="true" />
+ <parameter name="GUI_Full" value="true" />
+ <parameter name="GUI_LE_BasedFIFO" value="false" />
+ <parameter name="GUI_LegacyRREQ" value="1" />
+ <parameter name="GUI_MAX_DEPTH" value="Auto" />
+ <parameter name="GUI_MAX_DEPTH_BY_9" value="false" />
+ <parameter name="GUI_OVERFLOW_CHECKING" value="false" />
+ <parameter name="GUI_Optimize" value="1" />
+ <parameter name="GUI_Optimize_max" value="1" />
+ <parameter name="GUI_RAM_BLOCK_TYPE" value="Auto" />
+ <parameter name="GUI_TESTBENCH" value="false" />
+ <parameter name="GUI_UNDERFLOW_CHECKING" value="false" />
+ <parameter name="GUI_UsedW" value="true" />
+ <parameter name="GUI_Width" value="8" />
+ <parameter name="GUI_dc_aclr" value="false" />
+ <parameter name="GUI_delaypipe" value="5" />
+ <parameter name="GUI_diff_widths" value="false" />
+ <parameter name="GUI_msb_usedw" value="false" />
+ <parameter name="GUI_output_width" value="8" />
+ <parameter name="GUI_read_aclr_synch" value="false" />
+ <parameter name="GUI_rsEmpty" value="true" />
+ <parameter name="GUI_rsFull" value="false" />
+ <parameter name="GUI_rsUsedW" value="false" />
+ <parameter name="GUI_sc_aclr" value="true" />
+ <parameter name="GUI_sc_sclr" value="false" />
+ <parameter name="GUI_synStage" value="3" />
+ <parameter name="GUI_write_aclr_synch" value="false" />
+ <parameter name="GUI_wsEmpty" value="false" />
+ <parameter name="GUI_wsFull" value="true" />
+ <parameter name="GUI_wsUsedW" value="false" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_sc.vhd b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_sc.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..93a1eed1196007feb5a3292e258b97404145759b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_sc.vhd
@@ -0,0 +1,110 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Instantiate FIFO IP with generics
+-- Description:
+-- Copied component declaration and instance example from generated/fifo_140/sim/ip_arria10_e2sg_fifo_sc_fifo_140_pkqwcbi.vhd
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY technology_lib;
+USE technology_lib.technology_pkg.ALL;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY ip_arria10_e2sg_fifo_sc IS
+ GENERIC (
+ g_use_eab : STRING := "ON";
+ g_dat_w : NATURAL := 20;
+ g_nof_words : NATURAL := 1024
+ );
+ PORT (
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdreq : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ full : OUT STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
+ usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+END ip_arria10_e2sg_fifo_sc;
+
+
+ARCHITECTURE SYN OF ip_arria10_e2sg_fifo_sc IS
+
+ COMPONENT scfifo
+ GENERIC (
+ add_ram_output_register : STRING;
+ intended_device_family : STRING;
+ lpm_numwords : NATURAL;
+ lpm_showahead : STRING;
+ lpm_type : STRING;
+ lpm_width : NATURAL;
+ lpm_widthu : NATURAL;
+ overflow_checking : STRING;
+ underflow_checking : STRING;
+ use_eab : STRING
+ );
+ PORT (
+ aclr : IN STD_LOGIC;
+ clock : IN STD_LOGIC;
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdreq : IN STD_LOGIC;
+ wrreq : IN STD_LOGIC;
+ empty : OUT STD_LOGIC;
+ full : OUT STD_LOGIC;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+BEGIN
+
+ u_scfifo : scfifo
+ GENERIC MAP (
+ add_ram_output_register => "ON",
+ intended_device_family => "Arria 10",
+ lpm_numwords => g_nof_words,
+ lpm_showahead => "OFF",
+ lpm_type => "scfifo",
+ lpm_width => g_dat_w,
+ lpm_widthu => tech_ceil_log2(g_nof_words),
+ overflow_checking => "ON",
+ underflow_checking => "ON",
+ use_eab => g_use_eab
+ )
+ PORT MAP (
+ aclr => aclr,
+ clock => clock,
+ data => data,
+ rdreq => rdreq,
+ wrreq => wrreq,
+ empty => empty,
+ full => full,
+ q => q,
+ usedw => usedw
+ );
+
+END SYN;
diff --git a/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..923d3754c63c8123bf538e26b1d7ba55c1644d29
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_asmi_parallel/sim"
+
+
+ vcom "$IP_DIR/ip_arria10_e2sg_asmi_parallel.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..d3d03d20d597882aff8f6a889c304868f273cc79
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_asmi_parallel
+hdl_library_clause_name = ip_arria10_e2sg_asmi_parallel_altera_asmi_parallel_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_asmi_parallel_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_asmi_parallel/ip_arria10_e2sg_asmi_parallel.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_asmi_parallel.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/ip_arria10_e2sg_asmi_parallel.qsys b/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/ip_arria10_e2sg_asmi_parallel.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..06b07be2232bc568791e9f57d57f0028a01043c2
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/ip_arria10_e2sg_asmi_parallel.qsys
@@ -0,0 +1,175 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_asmi_parallel">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element asmi_parallel_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="addr" internal="asmi_parallel_0.addr" type="conduit" dir="end">
+ <port name="addr" internal="addr" />
+ </interface>
+ <interface name="busy" internal="asmi_parallel_0.busy" type="conduit" dir="end">
+ <port name="busy" internal="busy" />
+ </interface>
+ <interface name="clkin" internal="asmi_parallel_0.clkin" type="clock" dir="end">
+ <port name="clkin" internal="clkin" />
+ </interface>
+ <interface
+ name="data_valid"
+ internal="asmi_parallel_0.data_valid"
+ type="conduit"
+ dir="end">
+ <port name="data_valid" internal="data_valid" />
+ </interface>
+ <interface
+ name="datain"
+ internal="asmi_parallel_0.datain"
+ type="conduit"
+ dir="end">
+ <port name="datain" internal="datain" />
+ </interface>
+ <interface
+ name="dataout"
+ internal="asmi_parallel_0.dataout"
+ type="conduit"
+ dir="end">
+ <port name="dataout" internal="dataout" />
+ </interface>
+ <interface name="die_erase" internal="asmi_parallel_0.die_erase" />
+ <interface
+ name="en4b_addr"
+ internal="asmi_parallel_0.en4b_addr"
+ type="conduit"
+ dir="end">
+ <port name="en4b_addr" internal="en4b_addr" />
+ </interface>
+ <interface
+ name="ex4b_addr"
+ internal="asmi_parallel_0.ex4b_addr"
+ type="conduit"
+ dir="end">
+ <port name="ex4b_addr" internal="ex4b_addr" />
+ </interface>
+ <interface name="fast_read" internal="asmi_parallel_0.fast_read" />
+ <interface
+ name="illegal_erase"
+ internal="asmi_parallel_0.illegal_erase"
+ type="conduit"
+ dir="end">
+ <port name="illegal_erase" internal="illegal_erase" />
+ </interface>
+ <interface
+ name="illegal_write"
+ internal="asmi_parallel_0.illegal_write"
+ type="conduit"
+ dir="end">
+ <port name="illegal_write" internal="illegal_write" />
+ </interface>
+ <interface name="rden" internal="asmi_parallel_0.rden" type="conduit" dir="end">
+ <port name="rden" internal="rden" />
+ </interface>
+ <interface name="read" internal="asmi_parallel_0.read" type="conduit" dir="end">
+ <port name="read" internal="read" />
+ </interface>
+ <interface name="reset" internal="asmi_parallel_0.reset" type="reset" dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface name="sce" internal="asmi_parallel_0.sce" type="conduit" dir="end">
+ <port name="sce" internal="sce" />
+ </interface>
+ <interface
+ name="sector_erase"
+ internal="asmi_parallel_0.sector_erase"
+ type="conduit"
+ dir="end">
+ <port name="sector_erase" internal="sector_erase" />
+ </interface>
+ <interface
+ name="shift_bytes"
+ internal="asmi_parallel_0.shift_bytes"
+ type="conduit"
+ dir="end">
+ <port name="shift_bytes" internal="shift_bytes" />
+ </interface>
+ <interface name="wren" internal="asmi_parallel_0.wren" type="conduit" dir="end">
+ <port name="wren" internal="wren" />
+ </interface>
+ <interface
+ name="write"
+ internal="asmi_parallel_0.write"
+ type="conduit"
+ dir="end">
+ <port name="write" internal="write" />
+ </interface>
+ <module
+ name="asmi_parallel_0"
+ kind="altera_asmi_parallel"
+ version="19.1.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
+ <parameter name="DATA_WIDTH" value="STANDARD" />
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="ENABLE_SIM" value="false" />
+ <parameter name="EPCS_TYPE" value="EPCQL1024" />
+ <parameter name="FLASH_RSTPIN" value="FALSE" />
+ <parameter name="INTENDED_DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="PAGE_SIZE" value="256" />
+ <parameter name="WRITE_DUMMY_CLK" value="0" />
+ <parameter name="gui_bulk_erase" value="false" />
+ <parameter name="gui_die_erase" value="false" />
+ <parameter name="gui_ex4b_addr" value="true" />
+ <parameter name="gui_fast_read" value="false" />
+ <parameter name="gui_page_write" value="true" />
+ <parameter name="gui_read_address" value="false" />
+ <parameter name="gui_read_dummyclk" value="false" />
+ <parameter name="gui_read_rdid" value="false" />
+ <parameter name="gui_read_sid" value="false" />
+ <parameter name="gui_read_status" value="false" />
+ <parameter name="gui_sector_erase" value="true" />
+ <parameter name="gui_sector_protect" value="false" />
+ <parameter name="gui_single_write" value="false" />
+ <parameter name="gui_use_asmiblock" value="false" />
+ <parameter name="gui_use_eab" value="false" />
+ <parameter name="gui_wren" value="true" />
+ <parameter name="gui_write" value="true" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/flash/remote_update/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..a0166b1708199ec0bb38af3cac4a487ebbda1db4
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/flash/remote_update/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_remote_update/sim"
+
+
+ vcom "$IP_DIR/ip_arria10_e2sg_remote_update.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..348f30e1b597e086b6994fafe076e6956be9a538
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_remote_update
+hdl_library_clause_name = ip_arria10_e2sg_remote_update_altera_remote_update_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_remote_update_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/flash/remote_update/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_remote_update/ip_arria10_e2sg_remote_update.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_remote_update.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/flash/remote_update/ip_arria10_e2sg_remote_update.qsys b/libraries/technology/ip_arria10_e2sg/flash/remote_update/ip_arria10_e2sg_remote_update.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..e38df044a331cb0989ecbe9e2225173048851ff6
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/flash/remote_update/ip_arria10_e2sg_remote_update.qsys
@@ -0,0 +1,127 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_remote_update">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element remote_update_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="busy" internal="remote_update_0.busy" type="conduit" dir="end">
+ <port name="busy" internal="busy" />
+ </interface>
+ <interface name="clock" internal="remote_update_0.clock" type="clock" dir="end">
+ <port name="clock" internal="clock" />
+ </interface>
+ <interface
+ name="ctl_nupdt"
+ internal="remote_update_0.ctl_nupdt"
+ type="conduit"
+ dir="end">
+ <port name="ctl_nupdt" internal="ctl_nupdt" />
+ </interface>
+ <interface
+ name="data_in"
+ internal="remote_update_0.data_in"
+ type="conduit"
+ dir="end">
+ <port name="data_in" internal="data_in" />
+ </interface>
+ <interface
+ name="data_out"
+ internal="remote_update_0.data_out"
+ type="conduit"
+ dir="end">
+ <port name="data_out" internal="data_out" />
+ </interface>
+ <interface
+ name="param"
+ internal="remote_update_0.param"
+ type="conduit"
+ dir="end">
+ <port name="param" internal="param" />
+ </interface>
+ <interface
+ name="read_param"
+ internal="remote_update_0.read_param"
+ type="conduit"
+ dir="end">
+ <port name="read_param" internal="read_param" />
+ </interface>
+ <interface
+ name="reconfig"
+ internal="remote_update_0.reconfig"
+ type="conduit"
+ dir="end">
+ <port name="reconfig" internal="reconfig" />
+ </interface>
+ <interface name="reset" internal="remote_update_0.reset" type="reset" dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="reset_timer"
+ internal="remote_update_0.reset_timer"
+ type="conduit"
+ dir="end">
+ <port name="reset_timer" internal="reset_timer" />
+ </interface>
+ <interface
+ name="write_param"
+ internal="remote_update_0.write_param"
+ type="conduit"
+ dir="end">
+ <port name="write_param" internal="write_param" />
+ </interface>
+ <module
+ name="remote_update_0"
+ kind="altera_remote_update"
+ version="19.1.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
+ <parameter name="DEVICE" value="10AX115U3F45E2SG" />
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_config_device" value="EPCQL1024" />
+ <parameter name="check_app_pof" value="false" />
+ <parameter name="check_avalon_interface" value="false" />
+ <parameter name="m_support_write_config_check" value="true" />
+ <parameter name="operation_mode" value="REMOTE" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4fe3b4783ebc95f1a5fdd8354121b8e20993494b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/compile_ip.tcl
@@ -0,0 +1,34 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_fractional_pll_clk125/sim"
+
+ vcom "$IP_DIR/ip_arria10_e2sg_fractional_pll_clk125.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..37cd857cffe74616f8ae47e8d8fc77f4af6b1f1a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_fractional_pll_clk125
+hdl_library_clause_name = ip_arria10_e2sg_fractional_pll_clk125_altera_xcvr_fpll_a10_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_fpll_a10_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_fractional_pll_clk125/ip_arria10_e2sg_fractional_pll_clk125.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_fractional_pll_clk125.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/ip_arria10_e2sg_fractional_pll_clk125.qsys b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/ip_arria10_e2sg_fractional_pll_clk125.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..e09c4c105a3e0b7fa39a7532016c41400380fba2
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/ip_arria10_e2sg_fractional_pll_clk125.qsys
@@ -0,0 +1,266 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_fractional_pll_clk125">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element xcvr_fpll_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>outclk0</key>
+ <value>
+ <connectionPointName>outclk0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk1</key>
+ <value>
+ <connectionPointName>outclk1</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk2</key>
+ <value>
+ <connectionPointName>outclk2</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk3</key>
+ <value>
+ <connectionPointName>outclk3</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="hssi_pll_cascade_clk"
+ internal="xcvr_fpll_a10_0.hssi_pll_cascade_clk" />
+ <interface
+ name="outclk0"
+ internal="xcvr_fpll_a10_0.outclk0"
+ type="clock"
+ dir="start">
+ <port name="outclk0" internal="outclk0" />
+ </interface>
+ <interface
+ name="outclk1"
+ internal="xcvr_fpll_a10_0.outclk1"
+ type="clock"
+ dir="start">
+ <port name="outclk1" internal="outclk1" />
+ </interface>
+ <interface
+ name="outclk2"
+ internal="xcvr_fpll_a10_0.outclk2"
+ type="clock"
+ dir="start">
+ <port name="outclk2" internal="outclk2" />
+ </interface>
+ <interface
+ name="outclk3"
+ internal="xcvr_fpll_a10_0.outclk3"
+ type="clock"
+ dir="start">
+ <port name="outclk3" internal="outclk3" />
+ </interface>
+ <interface
+ name="pll_cal_busy"
+ internal="xcvr_fpll_a10_0.pll_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="pll_cal_busy" internal="pll_cal_busy" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="xcvr_fpll_a10_0.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="xcvr_fpll_a10_0.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_refclk0"
+ internal="xcvr_fpll_a10_0.pll_refclk0"
+ type="clock"
+ dir="end">
+ <port name="pll_refclk0" internal="pll_refclk0" />
+ </interface>
+ <interface name="tx_serial_clk" internal="xcvr_fpll_a10_0.tx_serial_clk" />
+ <module
+ name="xcvr_fpll_a10_0"
+ kind="altera_xcvr_fpll_a10"
+ version="19.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="enable_analog_resets" value="0" />
+ <parameter name="enable_bonding_clks" value="0" />
+ <parameter name="enable_ext_lockdetect_ports" value="0" />
+ <parameter name="enable_fb_comp_bonding" value="0" />
+ <parameter name="enable_hfreq_clk" value="0" />
+ <parameter name="enable_mcgb" value="0" />
+ <parameter name="enable_mcgb_pcie_clksw" value="0" />
+ <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
+ <parameter name="enable_pll_reconfig" value="0" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="gui_actual_outclk0_frequency" value="100.0" />
+ <parameter name="gui_actual_outclk1_frequency" value="100.0" />
+ <parameter name="gui_actual_outclk2_frequency" value="100.0" />
+ <parameter name="gui_actual_outclk3_frequency" value="100.0" />
+ <parameter name="gui_actual_refclk_frequency" value="100.0" />
+ <parameter name="gui_bw_sel" value="low" />
+ <parameter name="gui_cascade_outclk_index" value="0" />
+ <parameter name="gui_desired_hssi_cascade_frequency" value="100.0" />
+ <parameter name="gui_desired_outclk0_frequency" value="20.0" />
+ <parameter name="gui_desired_outclk1_frequency" value="50.0" />
+ <parameter name="gui_desired_outclk2_frequency" value="100.0" />
+ <parameter name="gui_desired_outclk3_frequency" value="125.0" />
+ <parameter name="gui_desired_refclk_frequency" value="200.0" />
+ <parameter name="gui_enable_50G_support" value="false" />
+ <parameter name="gui_enable_active_clk" value="false" />
+ <parameter name="gui_enable_cascade_out" value="false" />
+ <parameter name="gui_enable_clk_bad" value="false" />
+ <parameter name="gui_enable_dps" value="false" />
+ <parameter name="gui_enable_fractional" value="false" />
+ <parameter name="gui_enable_hip_cal_done_port" value="0" />
+ <parameter name="gui_enable_manual_config" value="false" />
+ <parameter name="gui_enable_manual_hssi_counters" value="false" />
+ <parameter name="gui_enable_phase_alignment" value="false" />
+ <parameter name="gui_enable_pld_cal_busy_port" value="1" />
+ <parameter name="gui_fpll_mode" value="0" />
+ <parameter name="gui_fractional_x" value="32" />
+ <parameter name="gui_hip_cal_en" value="0" />
+ <parameter name="gui_hssi_output_clock_frequency" value="1250.0" />
+ <parameter name="gui_hssi_prot_mode" value="0" />
+ <parameter name="gui_iqtxrxclk_outclk_index" value="0" />
+ <parameter name="gui_is_downstream_cascaded_pll" value="false" />
+ <parameter name="gui_number_of_output_clocks" value="4" />
+ <parameter name="gui_operation_mode" value="0" />
+ <parameter name="gui_outclk0_actual_phase_shift" value="0.0" />
+ <parameter name="gui_outclk0_actual_phase_shift_deg" value="0.0" />
+ <parameter name="gui_outclk0_desired_phase_shift" value="0.0" />
+ <parameter name="gui_outclk0_phase_shift_unit" value="0" />
+ <parameter name="gui_outclk1_actual_phase_shift" value="0.0" />
+ <parameter name="gui_outclk1_actual_phase_shift_deg" value="0.0" />
+ <parameter name="gui_outclk1_desired_phase_shift" value="0" />
+ <parameter name="gui_outclk1_phase_shift_unit" value="0" />
+ <parameter name="gui_outclk2_actual_phase_shift" value="0 ps" />
+ <parameter name="gui_outclk2_actual_phase_shift_deg" value="0 deg" />
+ <parameter name="gui_outclk2_desired_phase_shift" value="0" />
+ <parameter name="gui_outclk2_phase_shift_unit" value="0" />
+ <parameter name="gui_outclk3_actual_phase_shift" value="0.0" />
+ <parameter name="gui_outclk3_actual_phase_shift_deg" value="0.0" />
+ <parameter name="gui_outclk3_desired_phase_shift" value="0" />
+ <parameter name="gui_outclk3_phase_shift_unit" value="0" />
+ <parameter name="gui_pll_c_counter_0" value="1" />
+ <parameter name="gui_pll_c_counter_1" value="1" />
+ <parameter name="gui_pll_c_counter_2" value="1" />
+ <parameter name="gui_pll_c_counter_3" value="1" />
+ <parameter name="gui_pll_dsm_fractional_division" value="1" />
+ <parameter name="gui_pll_m_counter" value="1" />
+ <parameter name="gui_pll_n_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_k_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_l_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_m_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_n_counter" value="1" />
+ <parameter name="gui_refclk1_frequency" value="100.0" />
+ <parameter name="gui_refclk_cnt" value="1" />
+ <parameter name="gui_refclk_index" value="0" />
+ <parameter name="gui_refclk_switch" value="false" />
+ <parameter name="gui_reference_clock_frequency" value="125.0" />
+ <parameter name="gui_self_reset_enabled" value="false" />
+ <parameter name="gui_switchover_delay" value="0" />
+ <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+ <parameter name="mcgb_aux_clkin_cnt" value="0" />
+ <parameter name="mcgb_div" value="1" />
+ <parameter name="phase_alignment_check_var" value="false" />
+ <parameter name="pma_width" value="64" />
+ <parameter name="rcfg_debug" value="0" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_fpll_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="0" />
+ <parameter name="rcfg_mif_file_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_sv_file_enable" value="0" />
+ <parameter name="rcfg_txt_file_enable" value="0" />
+ <parameter name="set_altera_xcvr_fpll_a10_calibration_en" value="1" />
+ <parameter name="set_capability_reg_enable" value="0" />
+ <parameter name="set_csr_soft_logic_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="silicon_rev" value="false" />
+ <parameter name="support_mode" value="user_mode" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4f8725a2e4aba75800497c381b74e774529e3296
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_fractional_pll_clk200/sim"
+
+
+ vcom "$IP_DIR/ip_arria10_e2sg_fractional_pll_clk200.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..e0b939fec744b93c49bcfc0064c622b24a781cf3
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_fractional_pll_clk200
+hdl_library_clause_name = ip_arria10_e2sg_fractional_pll_clk200_altera_xcvr_fpll_a10_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_fpll_a10_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_fractional_pll_clk200/ip_arria10_e2sg_fractional_pll_clk200.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_fractional_pll_clk200.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/ip_arria10_e2sg_fractional_pll_clk200.qsys b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/ip_arria10_e2sg_fractional_pll_clk200.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..a34206bc493d91a40a53749f6993e09f5ca43a7e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/ip_arria10_e2sg_fractional_pll_clk200.qsys
@@ -0,0 +1,246 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_fractional_pll_clk200">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element xcvr_fpll_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>outclk0</key>
+ <value>
+ <connectionPointName>outclk0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk1</key>
+ <value>
+ <connectionPointName>outclk1</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk2</key>
+ <value>
+ <connectionPointName>outclk2</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="hssi_pll_cascade_clk"
+ internal="xcvr_fpll_a10_0.hssi_pll_cascade_clk" />
+ <interface
+ name="outclk0"
+ internal="xcvr_fpll_a10_0.outclk0"
+ type="clock"
+ dir="start">
+ <port name="outclk0" internal="outclk0" />
+ </interface>
+ <interface
+ name="outclk1"
+ internal="xcvr_fpll_a10_0.outclk1"
+ type="clock"
+ dir="start">
+ <port name="outclk1" internal="outclk1" />
+ </interface>
+ <interface
+ name="outclk2"
+ internal="xcvr_fpll_a10_0.outclk2"
+ type="clock"
+ dir="start">
+ <port name="outclk2" internal="outclk2" />
+ </interface>
+ <interface
+ name="pll_cal_busy"
+ internal="xcvr_fpll_a10_0.pll_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="pll_cal_busy" internal="pll_cal_busy" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="xcvr_fpll_a10_0.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="xcvr_fpll_a10_0.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_refclk0"
+ internal="xcvr_fpll_a10_0.pll_refclk0"
+ type="clock"
+ dir="end">
+ <port name="pll_refclk0" internal="pll_refclk0" />
+ </interface>
+ <interface name="tx_serial_clk" internal="xcvr_fpll_a10_0.tx_serial_clk" />
+ <module
+ name="xcvr_fpll_a10_0"
+ kind="altera_xcvr_fpll_a10"
+ version="19.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="enable_analog_resets" value="0" />
+ <parameter name="enable_bonding_clks" value="0" />
+ <parameter name="enable_ext_lockdetect_ports" value="0" />
+ <parameter name="enable_fb_comp_bonding" value="0" />
+ <parameter name="enable_hfreq_clk" value="0" />
+ <parameter name="enable_mcgb" value="0" />
+ <parameter name="enable_mcgb_pcie_clksw" value="0" />
+ <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
+ <parameter name="enable_pll_reconfig" value="0" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="gui_actual_outclk0_frequency" value="100.0" />
+ <parameter name="gui_actual_outclk1_frequency" value="100.0" />
+ <parameter name="gui_actual_outclk2_frequency" value="100.0" />
+ <parameter name="gui_actual_outclk3_frequency" value="100.0" />
+ <parameter name="gui_actual_refclk_frequency" value="100.0" />
+ <parameter name="gui_bw_sel" value="low" />
+ <parameter name="gui_cascade_outclk_index" value="0" />
+ <parameter name="gui_desired_hssi_cascade_frequency" value="100.0" />
+ <parameter name="gui_desired_outclk0_frequency" value="200.0" />
+ <parameter name="gui_desired_outclk1_frequency" value="200.0" />
+ <parameter name="gui_desired_outclk2_frequency" value="400.0" />
+ <parameter name="gui_desired_outclk3_frequency" value="100.0" />
+ <parameter name="gui_desired_refclk_frequency" value="200.0" />
+ <parameter name="gui_enable_50G_support" value="false" />
+ <parameter name="gui_enable_active_clk" value="false" />
+ <parameter name="gui_enable_cascade_out" value="false" />
+ <parameter name="gui_enable_clk_bad" value="false" />
+ <parameter name="gui_enable_dps" value="false" />
+ <parameter name="gui_enable_fractional" value="false" />
+ <parameter name="gui_enable_hip_cal_done_port" value="0" />
+ <parameter name="gui_enable_manual_config" value="false" />
+ <parameter name="gui_enable_manual_hssi_counters" value="false" />
+ <parameter name="gui_enable_phase_alignment" value="false" />
+ <parameter name="gui_enable_pld_cal_busy_port" value="1" />
+ <parameter name="gui_fpll_mode" value="0" />
+ <parameter name="gui_fractional_x" value="32" />
+ <parameter name="gui_hip_cal_en" value="0" />
+ <parameter name="gui_hssi_output_clock_frequency" value="1250.0" />
+ <parameter name="gui_hssi_prot_mode" value="0" />
+ <parameter name="gui_iqtxrxclk_outclk_index" value="0" />
+ <parameter name="gui_is_downstream_cascaded_pll" value="false" />
+ <parameter name="gui_number_of_output_clocks" value="3" />
+ <parameter name="gui_operation_mode" value="0" />
+ <parameter name="gui_outclk0_actual_phase_shift" value="0.0" />
+ <parameter name="gui_outclk0_actual_phase_shift_deg" value="0.0" />
+ <parameter name="gui_outclk0_desired_phase_shift" value="0.0" />
+ <parameter name="gui_outclk0_phase_shift_unit" value="0" />
+ <parameter name="gui_outclk1_actual_phase_shift" value="0.0" />
+ <parameter name="gui_outclk1_actual_phase_shift_deg" value="0.0" />
+ <parameter name="gui_outclk1_desired_phase_shift" value="90" />
+ <parameter name="gui_outclk1_phase_shift_unit" value="0" />
+ <parameter name="gui_outclk2_actual_phase_shift" value="0 ps" />
+ <parameter name="gui_outclk2_actual_phase_shift_deg" value="0 deg" />
+ <parameter name="gui_outclk2_desired_phase_shift" value="0" />
+ <parameter name="gui_outclk2_phase_shift_unit" value="0" />
+ <parameter name="gui_outclk3_actual_phase_shift" value="0.0" />
+ <parameter name="gui_outclk3_actual_phase_shift_deg" value="0.0" />
+ <parameter name="gui_outclk3_desired_phase_shift" value="0" />
+ <parameter name="gui_outclk3_phase_shift_unit" value="0" />
+ <parameter name="gui_pll_c_counter_0" value="1" />
+ <parameter name="gui_pll_c_counter_1" value="1" />
+ <parameter name="gui_pll_c_counter_2" value="1" />
+ <parameter name="gui_pll_c_counter_3" value="1" />
+ <parameter name="gui_pll_dsm_fractional_division" value="1" />
+ <parameter name="gui_pll_m_counter" value="1" />
+ <parameter name="gui_pll_n_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_k_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_l_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_m_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_n_counter" value="1" />
+ <parameter name="gui_refclk1_frequency" value="100.0" />
+ <parameter name="gui_refclk_cnt" value="1" />
+ <parameter name="gui_refclk_index" value="0" />
+ <parameter name="gui_refclk_switch" value="false" />
+ <parameter name="gui_reference_clock_frequency" value="200.0" />
+ <parameter name="gui_self_reset_enabled" value="false" />
+ <parameter name="gui_switchover_delay" value="0" />
+ <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+ <parameter name="mcgb_aux_clkin_cnt" value="0" />
+ <parameter name="mcgb_div" value="1" />
+ <parameter name="phase_alignment_check_var" value="false" />
+ <parameter name="pma_width" value="64" />
+ <parameter name="rcfg_debug" value="0" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_fpll_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="0" />
+ <parameter name="rcfg_mif_file_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_sv_file_enable" value="0" />
+ <parameter name="rcfg_txt_file_enable" value="0" />
+ <parameter name="set_altera_xcvr_fpll_a10_calibration_en" value="1" />
+ <parameter name="set_capability_reg_enable" value="0" />
+ <parameter name="set_csr_soft_logic_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="silicon_rev" value="false" />
+ <parameter name="support_mode" value="user_mode" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/jesd204b/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..a936c6c687a3b00616ba7fc4d2ba3af701d0fbec
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/hdllib.cfg
@@ -0,0 +1,28 @@
+hdl_lib_name = ip_arria10_e2sg_jesd204b
+hdl_library_clause_name = ip_arria10_e2sg_jesd204b_lib
+hdl_lib_uses_synth = technology tech_pll common dp
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+ ip_arria10_e2sg_jesd204b.vhd
+
+test_bench_files =
+
+[modelsim_project_file]
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_rx/ip_arria10_e2sg_jesd204b_rx.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_rx_core_pll/ip_arria10_e2sg_jesd204b_rx_core_pll.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_rx_reset_seq/ip_arria10_e2sg_jesd204b_rx_reset_seq.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_jesd204b_rx.qsys
+ ip_arria10_e2sg_jesd204b_rx_core_pll.qsys
+ ip_arria10_e2sg_jesd204b_rx_reset_seq.qsys
+ ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12.qsys
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6b6c7c4079db703c9ebb085753f1560c8691e818
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
@@ -0,0 +1,494 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+
+-- Purpose: Combine IP components needed to create a JESD204B interface
+-- Initially supports RX_ONLY for receiving data from an ADC
+-- Description
+--
+--
+
+LIBRARY IEEE, common_lib, dp_lib, technology_lib, ip_arria10_e2sg_jesd204b_rx, ip_arria10_e2sg_jesd204b_rx_reset_seq, ip_arria10_e2sg_jesd204b_rx_core_pll, ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY ip_arria10_e2sg_jesd204b IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
+ g_nof_channels : NATURAL := 1;
+ g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ );
+ PORT (
+ -- JESD204B external signals
+ jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
+ jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+
+ -- Data to fabric
+ rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- Parallel data out to fabric
+ jesd204b_frame_clk : OUT STD_LOGIC := '0'; -- Regenerated data clock to fabric
+
+ -- MM Control
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+
+ jesd204b_mosi : IN t_mem_mosi; -- mm control
+ jesd204b_miso : OUT t_mem_miso;
+
+ -- Serial connections to transceiver pins
+ serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- Not used for ADC
+ serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+ );
+END ip_arria10_e2sg_jesd204b;
+
+
+ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
+
+ -- JESD204 control status registers
+ SIGNAL jesd204b_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
+ SIGNAL jesd204b_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
+ SIGNAL reset_seq_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
+ SIGNAL reset_seq_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
+
+ -- Clocks
+ SIGNAL rxframe_clk : STD_LOGIC;
+ SIGNAL rxlink_clk : STD_LOGIC;
+
+ -- Reset and control signals
+ SIGNAL dev_lane_aligned : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- 1 bit, each interface channel has 1 lane
+ SIGNAL rx_analogreset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL rx_cal_busy_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL rx_digitalreset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL rx_islockedtodata_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL dev_lane_aligned_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL rx_csr_lane_powerdown_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL xcvr_rst_ctrl_rx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL rx_xcvr_ready_in_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL pll_reset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL xcvr_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL rx_avs_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL rxlink_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL rxframe_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL rx_avs_rst_n_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL rxlink_rst_n_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL rxframe_rst_n_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL f2_div1_cnt_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL core_pll_locked : STD_LOGIC;
+ SIGNAL core_pll_locked_reg : STD_LOGIC;
+
+ -- Data path
+ SIGNAL jesd204b_rx_link_data_arr : STD_LOGIC_VECTOR(32*g_nof_channels-1 DOWNTO 0);
+ SIGNAL jesd204b_rx_link_valid_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+
+
+ -- Component declarations for the IP blocks
+
+-- component ip_arria10_e2sg_jesd204b_rx is
+-- port (
+-- jesd204_0_alldev_lane_aligned_export : in std_logic := 'X'; -- export
+-- csr_cf_export : out std_logic_vector(4 downto 0); -- export
+-- csr_cs_export : out std_logic_vector(1 downto 0); -- export
+-- csr_f_export : out std_logic_vector(7 downto 0); -- export
+-- csr_hd_export : out std_logic; -- export
+-- csr_k_export : out std_logic_vector(4 downto 0); -- export
+-- csr_l_export : out std_logic_vector(4 downto 0); -- export
+-- csr_lane_powerdown_export : out std_logic_vector(0 downto 0); -- export
+-- csr_m_export : out std_logic_vector(7 downto 0); -- export
+-- csr_n_export : out std_logic_vector(4 downto 0); -- export
+-- csr_np_export : out std_logic_vector(4 downto 0); -- export
+-- csr_rx_testmode_export : out std_logic_vector(3 downto 0); -- export
+-- csr_s_export : out std_logic_vector(4 downto 0); -- export
+-- dev_lane_aligned_export : out std_logic; -- export
+-- dev_sync_n_export : out std_logic; -- export
+-- jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
+-- jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+-- jesd204_rx_avs_read : in std_logic := 'X'; -- read
+-- jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+-- jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
+-- jesd204_rx_avs_write : in std_logic := 'X'; -- write
+-- jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+-- jesd204_rx_avs_clk_clk : in std_logic := 'X'; -- clk
+-- jesd204_rx_avs_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+-- jesd204_rx_dlb_data_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+-- jesd204_rx_dlb_data_valid_export : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
+-- jesd204_rx_dlb_disperr_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+-- jesd204_rx_dlb_errdetect_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+-- jesd204_rx_dlb_kchar_data_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+-- jesd204_rx_frame_error_export : in std_logic := 'X'; -- export
+-- jesd204_rx_int_irq : out std_logic; -- irq
+-- jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
+-- jesd204_rx_link_valid : out std_logic; -- valid
+-- jesd204_rx_link_ready : in std_logic := 'X'; -- ready
+-- pll_ref_clk_clk : in std_logic := 'X'; -- clk
+-- rx_analogreset_rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
+-- rx_cal_busy_rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
+-- rx_digitalreset_rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
+-- rx_islockedtodata_rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
+-- rx_serial_data_rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
+-- rxlink_clk_clk : in std_logic := 'X'; -- clk
+-- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+-- rxphy_clk_export : out std_logic_vector(0 downto 0); -- export
+-- sof_export : out std_logic_vector(3 downto 0); -- export
+-- somf_export : out std_logic_vector(3 downto 0); -- export
+-- sysref_export : in std_logic := 'X' -- export
+-- );
+-- end component ip_arria10_e2sg_jesd204b_rx;
+
+ component ip_arria10_e2sg_jesd204b_rx_core_pll_cmp is
+ port (
+ locked : out std_logic; -- export
+ outclk_0 : out std_logic; -- clk
+ outclk_1 : out std_logic; -- clk
+ refclk : in std_logic := 'X'; -- clk
+ rst : in std_logic := 'X' -- reset
+ );
+ end component ip_arria10_e2sg_jesd204b_rx_core_pll_cmp;
+
+ component ip_arria10_e2sg_jesd204b_rx_reset_seq_cmp is
+ generic (
+ NUM_OUTPUTS : integer := 3;
+ ENABLE_DEASSERTION_INPUT_QUAL : integer := 0;
+ ENABLE_ASSERTION_SEQUENCE : integer := 0;
+ ENABLE_DEASSERTION_SEQUENCE : integer := 0;
+ MIN_ASRT_TIME : integer := 0;
+ ASRT_DELAY0 : integer := 0;
+ DSRT_DELAY0 : integer := 0;
+ ASRT_REMAP0 : integer := 0;
+ DSRT_REMAP0 : integer := 0;
+ DSRT_QUALCNT_0 : integer := 0;
+ ASRT_DELAY1 : integer := 0;
+ DSRT_DELAY1 : integer := 0;
+ ASRT_REMAP1 : integer := 1;
+ DSRT_REMAP1 : integer := 1;
+ DSRT_QUALCNT_1 : integer := 0;
+ ASRT_DELAY2 : integer := 0;
+ DSRT_DELAY2 : integer := 0;
+ ASRT_REMAP2 : integer := 2;
+ DSRT_REMAP2 : integer := 2;
+ DSRT_QUALCNT_2 : integer := 0;
+ ASRT_DELAY3 : integer := 0;
+ DSRT_DELAY3 : integer := 0;
+ ASRT_REMAP3 : integer := 3;
+ DSRT_REMAP3 : integer := 3;
+ DSRT_QUALCNT_3 : integer := 0;
+ ASRT_DELAY4 : integer := 0;
+ DSRT_DELAY4 : integer := 0;
+ ASRT_REMAP4 : integer := 4;
+ DSRT_REMAP4 : integer := 4;
+ DSRT_QUALCNT_4 : integer := 0;
+ ASRT_DELAY5 : integer := 0;
+ DSRT_DELAY5 : integer := 0;
+ ASRT_REMAP5 : integer := 5;
+ DSRT_REMAP5 : integer := 5;
+ DSRT_QUALCNT_5 : integer := 0;
+ ASRT_DELAY6 : integer := 0;
+ DSRT_DELAY6 : integer := 0;
+ ASRT_REMAP6 : integer := 6;
+ DSRT_REMAP6 : integer := 6;
+ DSRT_QUALCNT_6 : integer := 0;
+ ASRT_DELAY7 : integer := 0;
+ DSRT_DELAY7 : integer := 0;
+ ASRT_REMAP7 : integer := 7;
+ DSRT_REMAP7 : integer := 7;
+ DSRT_QUALCNT_7 : integer := 0;
+ ASRT_DELAY8 : integer := 0;
+ DSRT_DELAY8 : integer := 0;
+ ASRT_REMAP8 : integer := 8;
+ DSRT_REMAP8 : integer := 8;
+ DSRT_QUALCNT_8 : integer := 0;
+ ASRT_DELAY9 : integer := 0;
+ DSRT_DELAY9 : integer := 0;
+ ASRT_REMAP9 : integer := 9;
+ DSRT_REMAP9 : integer := 9;
+ DSRT_QUALCNT_9 : integer := 0
+ );
+ port (
+ av_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ av_readdata : out std_logic_vector(31 downto 0); -- readdata
+ av_read : in std_logic := 'X'; -- read
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ av_write : in std_logic := 'X'; -- write
+ irq : out std_logic; -- irq
+ clk : in std_logic := 'X'; -- clk
+ csr_reset : in std_logic := 'X'; -- reset
+ reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
+ reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
+ reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
+ reset_in0 : in std_logic := 'X'; -- reset
+ reset_out0 : out std_logic; -- reset
+ reset_out1 : out std_logic; -- reset
+ reset_out2 : out std_logic; -- reset
+ reset_out3 : out std_logic; -- reset
+ reset_out4 : out std_logic; -- reset
+ reset_out5 : out std_logic; -- reset
+ reset_out6 : out std_logic; -- reset
+ reset_out7 : out std_logic -- reset
+ );
+ end component ip_arria10_e2sg_jesd204b_rx_reset_seq_cmp;
+
+ component ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12_cmp is
+ port (
+ clock : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ rx_analogreset : out std_logic_vector(11 downto 0); -- rx_analogreset
+ rx_cal_busy : in std_logic_vector(11 downto 0) := (others => 'X'); -- rx_cal_busy
+ rx_digitalreset : out std_logic_vector(11 downto 0); -- rx_digitalreset
+ rx_is_lockedtodata : in std_logic_vector(11 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ rx_ready : out std_logic_vector(11 downto 0) -- rx_ready
+ );
+ end component ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12_cmp;
+
+
+
+BEGIN
+
+ jesd204b_frame_clk <= rxframe_clk;
+
+ gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE
+ gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
+
+ -----------------------------------------------------------------------------
+ -- The JESD204 IP (rx only)
+ -----------------------------------------------------------------------------
+-- u_ip_arria10_e2sg_jesd204b_rx : ip_arria10_e2sg_jesd204b_rx
+-- PORT MAP
+-- (
+-- jesd204_0_alldev_lane_aligned_export => dev_lane_aligned_arr(i),
+-- csr_cf_export => OPEN,
+-- csr_cs_export => OPEN,
+-- csr_f_export => OPEN,
+-- csr_hd_export => OPEN,
+-- csr_k_export => OPEN,
+-- csr_l_export => OPEN,
+-- csr_lane_powerdown_export => rx_csr_lane_powerdown_arr(i downto i),
+-- csr_m_export => OPEN,
+-- csr_n_export => OPEN,
+-- csr_np_export => OPEN,
+-- csr_rx_testmode_export => OPEN,
+-- csr_s_export => OPEN,
+-- dev_lane_aligned_export => dev_lane_aligned_arr(i),
+-- dev_sync_n_export => jesd204b_sync_n_arr(i),
+-- jesd204_rx_avs_chipselect => '0', --jesd204b_mosi_arr(i).chipselect,
+-- jesd204_rx_avs_address => jesd204b_mosi_arr(i).address(7 downto 0),
+-- jesd204_rx_avs_read => jesd204b_mosi_arr(i).rd,
+-- jesd204_rx_avs_readdata => jesd204b_miso_arr(i).rddata(31 downto 0),
+-- jesd204_rx_avs_waitrequest => jesd204b_miso_arr(i).waitrequest,
+-- jesd204_rx_avs_write => jesd204b_mosi_arr(i).wr,
+-- jesd204_rx_avs_writedata => jesd204b_mosi_arr(i).wrdata(31 downto 0),
+-- jesd204_rx_avs_clk_clk => mm_clk,
+-- jesd204_rx_avs_rst_n_reset_n => rx_avs_rst_n_arr(i), -- Todo: Check if this could use mm_rst,
+-- jesd204_rx_dlb_data_export => (others => '0'), -- debug/loopback testing
+-- jesd204_rx_dlb_data_valid_export => (others => '0'), -- debug/loopback testing
+-- jesd204_rx_dlb_disperr_export => (others => '0'), -- debug/loopback testing
+-- jesd204_rx_dlb_errdetect_export => (others => '0'), -- debug/loopback testing
+-- jesd204_rx_dlb_kchar_data_export => (others => '0'), -- debug/loopback testing
+-- jesd204_rx_frame_error_export => '0', -- jesd204_rx_frame_error.export
+-- jesd204_rx_int_irq => OPEN, -- Connected to status IO in example design
+-- jesd204_rx_link_data => jesd204b_rx_link_data_arr(i*32+31 DOWNTO i*32),
+-- jesd204_rx_link_valid => jesd204b_rx_link_valid_arr(i),
+-- jesd204_rx_link_ready => '1',
+-- pll_ref_clk_clk => jesd204b_refclk, -- Aka device_clock, same as reference for the link/frame clock IOPLL (Intel JESD204B-UG p63)
+-- rx_analogreset_rx_analogreset => rx_analogreset_arr(I DOWNTO I),
+-- rx_cal_busy_rx_cal_busy => rx_cal_busy_arr(I DOWNTO I),
+-- rx_digitalreset_rx_digitalreset => rx_digitalreset_arr(I DOWNTO I),
+-- rx_islockedtodata_rx_is_lockedtodata => rx_islockedtodata_arr(I DOWNTO I),
+-- rx_serial_data_rx_serial_data => serial_rx_arr(i downto i),
+-- rxlink_clk_clk => rxlink_clk, -- TODO: still not clear if this should be 100MHz or 200MHz (Intel JESD204B-UG p63)
+-- rxlink_rst_n_reset_n => rxlink_rst_n_arr(i), -- Assoc with rxlink_clk (Intel JESD204B-UG p69)
+-- rxphy_clk_export => OPEN, -- Not used in Subclass 0 (Intel JESD204B-UG p63)
+-- sof_export => OPEN,
+-- somf_export => OPEN,
+-- sysref_export => jesd204b_sysref
+-- );
+
+ u_ip_arria10_e2sg_jesd204b_rx : ENTITY ip_arria10_e2sg_jesd204b_rx.ip_arria10_e2sg_jesd204b_rx
+ PORT MAP
+ (
+ alldev_lane_aligned => dev_lane_aligned_arr(i),
+ csr_cf => OPEN,
+ csr_cs => OPEN,
+ csr_f => OPEN,
+ csr_hd => OPEN,
+ csr_k => OPEN,
+ csr_l => OPEN,
+ csr_lane_powerdown => rx_csr_lane_powerdown_arr(i downto i),
+ csr_m => OPEN,
+ csr_n => OPEN,
+ csr_np => OPEN,
+ csr_rx_testmode => OPEN,
+ csr_s => OPEN,
+ dev_lane_aligned => dev_lane_aligned_arr(i),
+ dev_sync_n => jesd204b_sync_n_arr(i),
+ jesd204_rx_avs_chipselect => '0', --jesd204b_mosi_arr(i).chipselect,
+ jesd204_rx_avs_address => jesd204b_mosi_arr(i).address(7 downto 0),
+ jesd204_rx_avs_read => jesd204b_mosi_arr(i).rd,
+ jesd204_rx_avs_readdata => jesd204b_miso_arr(i).rddata(31 downto 0),
+ jesd204_rx_avs_waitrequest => jesd204b_miso_arr(i).waitrequest,
+ jesd204_rx_avs_write => jesd204b_mosi_arr(i).wr,
+ jesd204_rx_avs_writedata => jesd204b_mosi_arr(i).wrdata(31 downto 0),
+ jesd204_rx_avs_clk => mm_clk,
+ jesd204_rx_avs_rst_n => rx_avs_rst_n_arr(i), -- Todo: Check if this could use mm_rst,
+ jesd204_rx_dlb_data => (others => '0'), -- debug/loopback testing
+ jesd204_rx_dlb_data_valid => (others => '0'), -- debug/loopback testing
+ jesd204_rx_dlb_disperr => (others => '0'), -- debug/loopback testing
+ jesd204_rx_dlb_errdetect => (others => '0'), -- debug/loopback testing
+ jesd204_rx_dlb_kchar_data => (others => '0'), -- debug/loopback testing
+ jesd204_rx_frame_error => '0', -- jesd204_rx_frame_error.export
+ jesd204_rx_int => OPEN, -- Connected to status IO in example design
+ jesd204_rx_link_data => jesd204b_rx_link_data_arr(i*32+31 DOWNTO i*32),
+ jesd204_rx_link_valid => jesd204b_rx_link_valid_arr(i),
+ jesd204_rx_link_ready => '1',
+ pll_ref_clk => jesd204b_refclk, -- Aka device_clock, same as reference for the link/frame clock IOPLL (Intel JESD204B-UG p63)
+ rx_analogreset => rx_analogreset_arr(I DOWNTO I),
+ rx_cal_busy => rx_cal_busy_arr(I DOWNTO I),
+ rx_digitalreset => rx_digitalreset_arr(I DOWNTO I),
+ rx_islockedtodata => rx_islockedtodata_arr(I DOWNTO I),
+ rx_serial_data => serial_rx_arr(i downto i),
+ rxlink_clk => rxlink_clk, -- TODO: still not clear if this should be 100MHz or 200MHz (Intel JESD204B-UG p63)
+ rxlink_rst_n_reset_n => rxlink_rst_n_arr(i), -- Assoc with rxlink_clk (Intel JESD204B-UG p69)
+ rxphy_clk => OPEN, -- Not used in Subclass 0 (Intel JESD204B-UG p63)
+ sof => OPEN,
+ somf => OPEN,
+ sysref => jesd204b_sysref
+ );
+
+ -----------------------------------------------------------------------------
+ -- Reset sequencer for each channel
+ -----------------------------------------------------------------------------
+ u_ip_arria10_e2sg_jesd204b_rx_reset_seq : ENTITY ip_arria10_e2sg_jesd204b_rx_reset_seq.ip_arria10_e2sg_jesd204b_rx_reset_seq
+ PORT MAP (
+ av_address => reset_seq_mosi_arr(i).address(7 downto 0), -- in std_logic_vector(7 downto 0) := (others => '0');
+ av_readdata => reset_seq_miso_arr(i).rddata(31 downto 0),
+ av_read => reset_seq_mosi_arr(i).rd,
+ av_writedata => reset_seq_mosi_arr(i).wrdata(31 downto 0),
+ av_write => reset_seq_mosi_arr(i).wr,
+ irq => open,
+ clk => mm_clk,
+ csr_reset => mm_rst,
+ reset1_dsrt_qual => core_pll_locked_reg, -- Registered copy of the the core pll_locked
+ reset2_dsrt_qual => '1', -- Tied to '1' in example design. Tx xcvr is not used.
+ reset5_dsrt_qual => rx_xcvr_ready_in_arr(i),
+ reset_in0 => mm_rst,
+ reset_out0 => pll_reset_arr(i), -- Use channel 0 to reset the core pll
+ reset_out1 => xcvr_rst_arr(i), -- Use channel 0 to reset the transceiver reset controller
+ reset_out2 => open,
+ reset_out3 => open,
+ reset_out4 => open,
+ reset_out5 => rx_avs_rst_arr(i),
+ reset_out6 => rxlink_rst_arr(i),
+ reset_out7 => rxframe_rst_arr(i)
+ );
+
+ rx_xcvr_ready_in_arr(i) <= rx_csr_lane_powerdown_arr(i) OR xcvr_rst_ctrl_rx_ready_arr(i);
+
+ -- Invert thr active-low resets
+ rx_avs_rst_n_arr(i) <= not rx_avs_rst_arr(i);
+ rxlink_rst_n_arr(i) <= not rxlink_rst_arr(i);
+ rxframe_rst_n_arr(i) <= not rxframe_rst_arr(i);
+
+
+ -----------------------------------------------------------------------------
+ -- Minimal deframer (transport layer)
+ -----------------------------------------------------------------------------
+ p_deframer : PROCESS (rxframe_clk, rxframe_rst_n_arr(i))
+ BEGIN
+ IF rising_edge(rxframe_clk) THEN
+ IF rxframe_rst_n_arr(i) = '0' THEN
+ rx_src_out_arr(i).data(15 downto 0) <= (OTHERS => '0');
+ f2_div1_cnt_arr(i) <= '0';
+ ELSE
+ rx_src_out_arr(i).valid <= jesd204b_rx_link_valid_arr(i);
+ IF jesd204b_rx_link_valid_arr(i) = '0' THEN
+ rx_src_out_arr(i).data(15 downto 0) <= (OTHERS => '0');
+ ELSE
+ IF f2_div1_cnt_arr(i) = '1' THEN
+ rx_src_out_arr(i).data(15 downto 0) <= jesd204b_rx_link_data_arr(32*i+15 downto 32*i);
+ ELSE
+ rx_src_out_arr(i).data(15 downto 0) <= jesd204b_rx_link_data_arr(32*i+31 downto 32*i+16);
+ END IF;
+ f2_div1_cnt_arr(i) <= not f2_div1_cnt_arr(i);
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ END GENERATE;
+
+ -- IOPLL in source synchronous or normal mode. (Intel JESD204B-UG p66)
+ u_ip_arria10_e2sg_jesd204b_rx_corepll : ENTITY ip_arria10_e2sg_jesd204b_rx_core_pll.ip_arria10_e2sg_jesd204b_rx_core_pll
+ PORT MAP (
+ locked => core_pll_locked,
+ outclk_0 => rxlink_clk,
+ outclk_1 => rxframe_clk,
+ refclk => jesd204b_refclk,
+ rst => pll_reset_arr(0)
+ );
+
+ p_pll_locked_reg : PROCESS (mm_rst, mm_clk)
+ BEGIN
+ IF mm_rst = '1' THEN
+ core_pll_locked_reg <= '0';
+ ELSE
+ IF rising_edge(mm_clk) THEN
+ core_pll_locked_reg <= core_pll_locked;
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+ -- Transceiver reset controller. Use g_nof_channels out of 12 channels. Receive only
+ -- Clock set to 100MHz (use mm_clk)
+
+ u_ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control : ENTITY ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12.ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12
+ PORT MAP (
+ clock => mm_clk,
+ reset => xcvr_rst_arr(0), -- From Reset Sequencer output1 as per example design
+ rx_analogreset => rx_analogreset_arr, -- output to reset RX PMA. Release before deasserting link and avs resets (Intel JESD204B-UG p70)
+ rx_cal_busy => rx_cal_busy_arr, -- input from PHY
+ rx_digitalreset => rx_digitalreset_arr, -- output to reset RX PCS. Release before deasserting link and avs resets (Intel JESD204B-UG p70)
+ rx_is_lockedtodata => rx_islockedtodata_arr, -- input from PHY
+ rx_ready => xcvr_rst_ctrl_rx_ready_arr -- From example design: gate with rx_csr_lane_powerdown to reset transceiver
+ );
+
+ END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- MM bus mux
+ -----------------------------------------------------------------------------
+ u_common_mem_mux_mac : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_channels,
+ g_mult_addr_w => 8
+ )
+ PORT MAP (
+ mosi => jesd204b_mosi,
+ miso => jesd204b_miso,
+ mosi_arr => jesd204b_mosi_arr,
+ miso_arr => jesd204b_miso_arr
+ );
+
+
+END str;
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx.ip b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx.ip
new file mode 100644
index 0000000000000000000000000000000000000000..8751987d6b4a16e43796426ce916a880a92d9486
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx.ip
@@ -0,0 +1,3276 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>Intel Corporation</spirit:vendor>
+ <spirit:library>ip_arria10_e2sg_jesd204b_rx</spirit:library>
+ <spirit:name>jesd204_0</spirit:name>
+ <spirit:version>18.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>alldev_lane_aligned</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>alldev_lane_aligned</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>csr_cf</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csr_cf</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
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+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
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+ <spirit:name>ui.blockdiagram.direction</spirit:name>
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+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>csr_cs</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
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+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csr_cs</spirit:name>
+ </spirit:physicalPort>
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+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>csr_f</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
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+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csr_f</spirit:name>
+ </spirit:physicalPort>
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+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
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+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>csr_hd</spirit:name>
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+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csr_hd</spirit:name>
+ </spirit:physicalPort>
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+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value>
+ </spirit:parameter>
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+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>csr_k</spirit:name>
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+ <spirit:slave></spirit:slave>
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+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csr_k</spirit:name>
+ </spirit:physicalPort>
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+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>csr_l</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
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+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
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+ <spirit:physicalPort>
+ <spirit:name>csr_l</spirit:name>
+ </spirit:physicalPort>
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+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
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+ </spirit:parameter>
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+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>csr_lane_powerdown</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
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+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csr_lane_powerdown</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
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+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
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+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
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+ <spirit:vendorExtensions>
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+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
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+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>csr_m</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
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+ <spirit:name>export</spirit:name>
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+ <spirit:physicalPort>
+ <spirit:name>csr_m</spirit:name>
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+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
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+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
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+ <spirit:vendorExtensions>
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+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
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+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
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+ <spirit:name>csr_n</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
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+ <spirit:name>export</spirit:name>
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+ <spirit:physicalPort>
+ <spirit:name>csr_n</spirit:name>
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+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
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+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
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+ <spirit:vendorExtensions>
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+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
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+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>csr_np</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
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+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
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+ <spirit:physicalPort>
+ <spirit:name>csr_np</spirit:name>
+ </spirit:physicalPort>
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+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
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+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
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+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
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+ <spirit:name>ui.blockdiagram.direction</spirit:name>
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+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
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+ <spirit:name>csr_rx_testmode</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
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+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
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+ <spirit:name>csr_rx_testmode</spirit:name>
+ </spirit:physicalPort>
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+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
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+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
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+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
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+ <spirit:name>ui.blockdiagram.direction</spirit:name>
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+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
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+ <spirit:name>csr_s</spirit:name>
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+ <spirit:name>export</spirit:name>
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+ <spirit:name>csr_s</spirit:name>
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+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
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+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
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+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
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+ <spirit:vendorExtensions>
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+ <spirit:name>ui.blockdiagram.direction</spirit:name>
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+ </altera:altera_assignments>
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+ <spirit:name>dev_lane_aligned</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
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+ <spirit:name>export</spirit:name>
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+ <spirit:name>dev_lane_aligned</spirit:name>
+ </spirit:physicalPort>
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+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
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+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
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+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
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+ <spirit:displayName>associatedClock</spirit:displayName>
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+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
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+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
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+ <spirit:name>address</spirit:name>
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+ <spirit:name>jesd204_rx_avs_address</spirit:name>
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+ <spirit:name>jesd204_rx_avs_readdata</spirit:name>
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+ <spirit:name>jesd204_rx_avs_waitrequest</spirit:name>
+ </spirit:physicalPort>
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+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>jesd204_rx_avs_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>jesd204_rx_avs_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">1024</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">jesd204_rx_avs_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">jesd204_rx_avs_rst_n</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>jesd204_rx_avs_clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>jesd204_rx_avs_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>jesd204_rx_avs_rst_n</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset_n</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>jesd204_rx_avs_rst_n</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">jesd204_rx_avs_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>jesd204_rx_dlb_data</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>jesd204_rx_dlb_data</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>jesd204_rx_dlb_data_valid</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>jesd204_rx_dlb_data_valid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>jesd204_rx_dlb_disperr</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>jesd204_rx_dlb_disperr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>jesd204_rx_dlb_errdetect</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>jesd204_rx_dlb_errdetect</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>jesd204_rx_dlb_kchar_data</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>jesd204_rx_dlb_kchar_data</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>jesd204_rx_frame_error</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>jesd204_rx_frame_error</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>jesd204_rx_int</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="interrupt" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>irq</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>jesd204_rx_int</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedAddressablePoint</spirit:name>
+ <spirit:displayName>Associated addressable interface</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedAddressablePoint">ip_arria10_e2sg_jesd204b_rx.jesd204_rx_avs</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">jesd204_rx_avs_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">jesd204_rx_avs_rst_n</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedReceiverOffset</spirit:name>
+ <spirit:displayName>Bridged receiver offset</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bridgedReceiverOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToReceiver</spirit:name>
+ <spirit:displayName>Bridges to receiver</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToReceiver"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>irqScheme</spirit:name>
+ <spirit:displayName>Interrupt scheme</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="irqScheme">NONE</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>jesd204_rx_link</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon_streaming" spirit:version="18.0"></spirit:busType>
+ <spirit:master></spirit:master>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>data</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>jesd204_rx_link_data</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>valid</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>jesd204_rx_link_valid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ready</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>jesd204_rx_link_ready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">rxlink_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">rxlink_rst_n</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>beatsPerCycle</spirit:name>
+ <spirit:displayName>Beats Per Cycle</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="beatsPerCycle">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>dataBitsPerSymbol</spirit:name>
+ <spirit:displayName>Data bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="dataBitsPerSymbol">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>emptyWithinPacket</spirit:name>
+ <spirit:displayName>emptyWithinPacket</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="emptyWithinPacket">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>errorDescriptor</spirit:name>
+ <spirit:displayName>Error descriptor</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="errorDescriptor"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>firstSymbolInHighOrderBits</spirit:name>
+ <spirit:displayName>First Symbol In High-Order Bits</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="firstSymbolInHighOrderBits">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>highOrderSymbolAtMSB</spirit:name>
+ <spirit:displayName>highOrderSymbolAtMSB</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="highOrderSymbolAtMSB">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maxChannel</spirit:name>
+ <spirit:displayName>Maximum channel</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maxChannel">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>packetDescription</spirit:name>
+ <spirit:displayName>Packet description </spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="packetDescription"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readyAllowance</spirit:name>
+ <spirit:displayName>Ready allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readyAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readyLatency</spirit:name>
+ <spirit:displayName>Ready latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readyLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>symbolsPerBeat</spirit:name>
+ <spirit:displayName>Symbols per beat </spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="symbolsPerBeat">1</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>pll_ref_clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>pll_ref_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>rx_analogreset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>rx_analogreset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rx_analogreset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>rx_cal_busy</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>rx_cal_busy</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rx_cal_busy</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>rx_digitalreset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>rx_digitalreset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rx_digitalreset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>rx_islockedtodata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>rx_is_lockedtodata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rx_islockedtodata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>rx_serial_data</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>rx_serial_data</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rx_serial_data</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>rxlink_clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rxlink_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>rxlink_rst_n</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset_n</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rxlink_rst_n_reset_n</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">rxlink_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>rxphy_clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rxphy_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>sof</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>sof</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>somf</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>somf</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>sysref</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>sysref</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
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+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>Intel Corporation</spirit:vendor>
+ <spirit:library>ip_arria10_e2sg_jesd204b_rx</spirit:library>
+ <spirit:name>altera_jesd204</spirit:name>
+ <spirit:version>18.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>wrapper_opt</spirit:name>
+ <spirit:displayName>Jesd204b wrapper</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="wrapper_opt">base_phy</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>sdc_constraint</spirit:name>
+ <spirit:displayName>Set constraint for sdc</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="sdc_constraint">1.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DEVICE_FAMILY</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="DEVICE_FAMILY">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>part_trait_dp</spirit:name>
+ <spirit:displayName>Device Part</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="part_trait_dp">10AX115U3F45E2SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DATA_PATH</spirit:name>
+ <spirit:displayName>Data path</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="DATA_PATH">RX</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SUBCLASSV</spirit:name>
+ <spirit:displayName>Jesd204b subclass</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="SUBCLASSV">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lane_rate</spirit:name>
+ <spirit:displayName>Data rate</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="lane_rate">4000.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PCS_CONFIG</spirit:name>
+ <spirit:displayName>PCS Option</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="PCS_CONFIG">JESD_PCS_CFG1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_type</spirit:name>
+ <spirit:displayName>PLL Type</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="pll_type">CMU</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonded_mode</spirit:name>
+ <spirit:displayName>Bonding Mode </spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonded_mode">bonded</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>REFCLK_FREQ</spirit:name>
+ <spirit:displayName>PLL/CDR Reference Clock Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="REFCLK_FREQ">200.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_analog_voltage</spirit:name>
+ <spirit:displayName>VCCR_GXB and VCCT_GXB supply voltage for the Transceiver</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_analog_voltage">1_0V</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitrev_en</spirit:name>
+ <spirit:displayName>Enable Bit reversal and Byte reversal</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="bitrev_en">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_reconfig_enable</spirit:name>
+ <spirit:displayName>Enable Transceiver Dynamic Reconfiguration</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="pll_reconfig_enable">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>rcfg_jtag_enable</spirit:name>
+ <spirit:displayName>Enable Altera Debug Master Endpoint</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="rcfg_jtag_enable">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>rcfg_shared</spirit:name>
+ <spirit:displayName>Share Reconfiguration Interface</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="rcfg_shared">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>rcfg_enable_split_interface</spirit:name>
+ <spirit:displayName>Provide Separate Reconfiguration Interface for Each Channel</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="rcfg_enable_split_interface">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>set_capability_reg_enable</spirit:name>
+ <spirit:displayName>Enable Capability Registers</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="set_capability_reg_enable">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>set_user_identifier</spirit:name>
+ <spirit:displayName>Set user-defined IP identifier</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="set_user_identifier">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>set_csr_soft_logic_enable</spirit:name>
+ <spirit:displayName>Enable Control and Status Registers</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="set_csr_soft_logic_enable">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>set_prbs_soft_logic_enable</spirit:name>
+ <spirit:displayName>Enable PRBS Soft Accumulators</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="set_prbs_soft_logic_enable">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>L</spirit:name>
+ <spirit:displayName>Lanes per converter device (L)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="L">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>M</spirit:name>
+ <spirit:displayName>Converters per device (M)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="M">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>GUI_EN_CFG_F</spirit:name>
+ <spirit:displayName>Enable manual F configuration</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="GUI_EN_CFG_F">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>GUI_CFG_F</spirit:name>
+ <spirit:displayName>Octets per frame (F)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="GUI_CFG_F">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>F</spirit:name>
+ <spirit:displayName>Octets per frame (F)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="F">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>N</spirit:name>
+ <spirit:displayName>Converter resolution (N)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="N">14</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>N_PRIME</spirit:name>
+ <spirit:displayName>Transmitted bits per sample (N')</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="N_PRIME">16</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>S</spirit:name>
+ <spirit:displayName>Samples per converter per frame (S)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="S">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>K</spirit:name>
+ <spirit:displayName>Frames per multiframe (K)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="K">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SCR</spirit:name>
+ <spirit:displayName>Enable scramble (SCR)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="SCR">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CS</spirit:name>
+ <spirit:displayName>Control Bits (CS)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="CS">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CF</spirit:name>
+ <spirit:displayName>Control Words (CF)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="CF">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>HD</spirit:name>
+ <spirit:displayName>High Density user data format (HD)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="HD">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ECC_EN</spirit:name>
+ <spirit:displayName>Enable Error Code Correction (ECC_EN)</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="ECC_EN">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DLB_TEST</spirit:name>
+ <spirit:displayName>Enable Digital Loop Back Test (DLB_TEST)</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="DLB_TEST">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PHADJ</spirit:name>
+ <spirit:displayName>Phase adjustment request (PHADJ)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="PHADJ">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ADJCNT</spirit:name>
+ <spirit:displayName>Adjustment resolution step count (ADJCNT)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ADJCNT">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ADJDIR</spirit:name>
+ <spirit:displayName>Direction of adjustment (ADJDIR)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ADJDIR">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>OPTIMIZE</spirit:name>
+ <spirit:displayName>CSR Programmability</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="OPTIMIZE">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DID</spirit:name>
+ <spirit:displayName>Device ID</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DID">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>BID</spirit:name>
+ <spirit:displayName>Bank ID</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="BID">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>LID0</spirit:name>
+ <spirit:displayName>Lane0 ID</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="LID0">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FCHK0</spirit:name>
+ <spirit:displayName>Lane0 checksum</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="FCHK0">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>LID1</spirit:name>
+ <spirit:displayName>Lane1 ID</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="LID1">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FCHK1</spirit:name>
+ <spirit:displayName>Lane1 checksum</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="FCHK1">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>LID2</spirit:name>
+ <spirit:displayName>Lane2 ID</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="LID2">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FCHK2</spirit:name>
+ <spirit:displayName>Lane2 checksum</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="FCHK2">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>LID3</spirit:name>
+ <spirit:displayName>Lane3 ID</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="LID3">3</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FCHK3</spirit:name>
+ <spirit:displayName>Lane3 checksum</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="FCHK3">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>LID4</spirit:name>
+ <spirit:displayName>Lane4 ID</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="LID4">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FCHK4</spirit:name>
+ <spirit:displayName>Lane4 checksum</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="FCHK4">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>LID5</spirit:name>
+ <spirit:displayName>Lane5 ID</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="LID5">5</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FCHK5</spirit:name>
+ <spirit:displayName>Lane5 checksum</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="FCHK5">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>LID6</spirit:name>
+ <spirit:displayName>Lane6 ID</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="LID6">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FCHK6</spirit:name>
+ <spirit:displayName>Lane6 checksum</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="FCHK6">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>LID7</spirit:name>
+ <spirit:displayName>Lane7 ID</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="LID7">7</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FCHK7</spirit:name>
+ <spirit:displayName>Lane7 checksum</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="FCHK7">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>d_refclk_freq</spirit:name>
+ <spirit:displayName>PLL/CDR Reference Clock Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="d_refclk_freq">200.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>JESDV</spirit:name>
+ <spirit:displayName>JESDV</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="JESDV">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PMA_WIDTH</spirit:name>
+ <spirit:displayName>PMA_WIDTH</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="PMA_WIDTH">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SER_SIZE</spirit:name>
+ <spirit:displayName>SER_SIZE</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="SER_SIZE">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FK</spirit:name>
+ <spirit:displayName>FK</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="FK">64</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RES1</spirit:name>
+ <spirit:displayName>RES1</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="RES1">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RES2</spirit:name>
+ <spirit:displayName>RES2</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="RES2">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>BIT_REVERSAL</spirit:name>
+ <spirit:displayName>BIT_REVERSAL</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="BIT_REVERSAL">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>BYTE_REVERSAL</spirit:name>
+ <spirit:displayName>BYTE_REVERSAL</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="BYTE_REVERSAL">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ALIGNMENT_PATTERN</spirit:name>
+ <spirit:displayName>ALIGNMENT_PATTERN</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ALIGNMENT_PATTERN">658812</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PULSE_WIDTH</spirit:name>
+ <spirit:displayName>PULSE_WIDTH</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="PULSE_WIDTH">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>LS_FIFO_DEPTH</spirit:name>
+ <spirit:displayName>LS_FIFO_DEPTH</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="LS_FIFO_DEPTH">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>LS_FIFO_WIDTHU</spirit:name>
+ <spirit:displayName>LS_FIFO_WIDTHU</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="LS_FIFO_WIDTHU">5</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>UNUSED_TX_PARALLEL_WIDTH</spirit:name>
+ <spirit:displayName>UNUSED_TX_PARALLEL_WIDTH</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="UNUSED_TX_PARALLEL_WIDTH">92</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>UNUSED_RX_PARALLEL_WIDTH</spirit:name>
+ <spirit:displayName>UNUSED_RX_PARALLEL_WIDTH</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="UNUSED_RX_PARALLEL_WIDTH">72</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>XCVR_PLL_LOCKED_WIDTH</spirit:name>
+ <spirit:displayName>XCVR_PLL_LOCKED_WIDTH</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="XCVR_PLL_LOCKED_WIDTH">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RECONFIG_ADDRESS_WIDTH</spirit:name>
+ <spirit:displayName>RECONFIG_ADDRESS_WIDTH</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="RECONFIG_ADDRESS_WIDTH">10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DEPTH_PIPE</spirit:name>
+ <spirit:displayName>Pipeline stages for link_clk domain reset signal</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DEPTH_PIPE">3</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>xcvr_ip</spirit:name>
+ <spirit:displayName>xcvr_ip</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="xcvr_ip">ltile</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>die_types</spirit:name>
+ <spirit:displayName>die_types</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="die_types"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>die_revisions</spirit:name>
+ <spirit:displayName>die_revisions</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="die_revisions"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>support_c1</spirit:name>
+ <spirit:displayName>support_c1</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="support_c1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>support_c2</spirit:name>
+ <spirit:displayName>support_c2</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="support_c2">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>support_c3</spirit:name>
+ <spirit:displayName>support_c3</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="support_c3">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>crete_tile_status</spirit:name>
+ <spirit:displayName>Transceiver Tile</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="crete_tile_status">ltile</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_user_crete_tile</spirit:name>
+ <spirit:displayName>Transceiver Tile</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_user_crete_tile">etile</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>TEST_COMPONENTS_EN</spirit:name>
+ <spirit:displayName>Add Test Components</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="TEST_COMPONENTS_EN">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>TERMINATE_RECONFIG_EN</spirit:name>
+ <spirit:displayName>Terminate Reconfig Signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="TERMINATE_RECONFIG_EN">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ED_TYPE</spirit:name>
+ <spirit:displayName>Select Design</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ED_TYPE">NONE</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ED_FILESET_SIM</spirit:name>
+ <spirit:displayName>Simulation</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="ED_FILESET_SIM">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ED_FILESET_SYNTH</spirit:name>
+ <spirit:displayName>Synthesis</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="ED_FILESET_SYNTH">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ED_HDL_FORMAT_SIM</spirit:name>
+ <spirit:displayName>HDL Format</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ED_HDL_FORMAT_SIM">VERILOG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ED_SIM_PAT_TESTMODE</spirit:name>
+ <spirit:displayName>Test pattern</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ED_SIM_PAT_TESTMODE">PRBS_7</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ED_HDL_FORMAT_SYNTH</spirit:name>
+ <spirit:displayName>HDL Format</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ED_HDL_FORMAT_SYNTH">VERILOG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ED_DEV_KIT</spirit:name>
+ <spirit:displayName>Select Board</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ED_DEV_KIT">NONE</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>GUI_ED_DEV_KIT</spirit:name>
+ <spirit:displayName>Select Board</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="GUI_ED_DEV_KIT">None</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ED_SINGLE_REFCLK</spirit:name>
+ <spirit:displayName>Single reference clock (Advanced users only. Not recommended.)</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="ED_SINGLE_REFCLK">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ED_3WIRE_SPI</spirit:name>
+ <spirit:displayName>Generate 3-wire SPI module</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="ED_3WIRE_SPI">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SELECT_CUSTOM_DEVICE</spirit:name>
+ <spirit:displayName>Change Target Device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="SELECT_CUSTOM_DEVICE">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_DEVICE</spirit:name>
+ <spirit:displayName>Auto DEVICE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_DEVICE">10AX115U3F45E2SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_DEVICE_SPEEDGRADE</spirit:name>
+ <spirit:displayName>Auto DEVICE_SPEEDGRADE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_DEVICE_SPEEDGRADE">1</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+ element jesd204_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>jesd204_rx_avs</key>
+ <value>
+ <connectionPointName>jesd204_rx_avs</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='jesd204_rx_avs' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>10</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="alldev_lane_aligned" altera:internal="jesd204_0.alldev_lane_aligned" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="alldev_lane_aligned" altera:internal="alldev_lane_aligned"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="csr_cf" altera:internal="jesd204_0.csr_cf" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="csr_cf" altera:internal="csr_cf"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="csr_cs" altera:internal="jesd204_0.csr_cs" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="csr_cs" altera:internal="csr_cs"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="csr_f" altera:internal="jesd204_0.csr_f" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="csr_f" altera:internal="csr_f"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="csr_hd" altera:internal="jesd204_0.csr_hd" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="csr_hd" altera:internal="csr_hd"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="csr_k" altera:internal="jesd204_0.csr_k" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="csr_k" altera:internal="csr_k"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="csr_l" altera:internal="jesd204_0.csr_l" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="csr_l" altera:internal="csr_l"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="csr_lane_powerdown" altera:internal="jesd204_0.csr_lane_powerdown" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="csr_lane_powerdown" altera:internal="csr_lane_powerdown"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="csr_m" altera:internal="jesd204_0.csr_m" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="csr_m" altera:internal="csr_m"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="csr_n" altera:internal="jesd204_0.csr_n" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="csr_n" altera:internal="csr_n"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="csr_np" altera:internal="jesd204_0.csr_np" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="csr_np" altera:internal="csr_np"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="csr_rx_testmode" altera:internal="jesd204_0.csr_rx_testmode" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="csr_rx_testmode" altera:internal="csr_rx_testmode"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="csr_s" altera:internal="jesd204_0.csr_s" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="csr_s" altera:internal="csr_s"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="csr_tx_testmode" altera:internal="jesd204_0.csr_tx_testmode"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="csr_tx_testpattern_a" altera:internal="jesd204_0.csr_tx_testpattern_a"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="csr_tx_testpattern_b" altera:internal="jesd204_0.csr_tx_testpattern_b"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="csr_tx_testpattern_c" altera:internal="jesd204_0.csr_tx_testpattern_c"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="csr_tx_testpattern_d" altera:internal="jesd204_0.csr_tx_testpattern_d"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="dev_lane_aligned" altera:internal="jesd204_0.dev_lane_aligned" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dev_lane_aligned" altera:internal="dev_lane_aligned"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dev_sync_n" altera:internal="jesd204_0.dev_sync_n" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dev_sync_n" altera:internal="dev_sync_n"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="jesd204_rx_avs" altera:internal="jesd204_0.jesd204_rx_avs" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="jesd204_rx_avs_address" altera:internal="jesd204_rx_avs_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="jesd204_rx_avs_chipselect" altera:internal="jesd204_rx_avs_chipselect"></altera:port_mapping>
+ <altera:port_mapping altera:name="jesd204_rx_avs_read" altera:internal="jesd204_rx_avs_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="jesd204_rx_avs_readdata" altera:internal="jesd204_rx_avs_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="jesd204_rx_avs_waitrequest" altera:internal="jesd204_rx_avs_waitrequest"></altera:port_mapping>
+ <altera:port_mapping altera:name="jesd204_rx_avs_write" altera:internal="jesd204_rx_avs_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="jesd204_rx_avs_writedata" altera:internal="jesd204_rx_avs_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="jesd204_rx_avs_clk" altera:internal="jesd204_0.jesd204_rx_avs_clk" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="jesd204_rx_avs_clk" altera:internal="jesd204_rx_avs_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="jesd204_rx_avs_rst_n" altera:internal="jesd204_0.jesd204_rx_avs_rst_n" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="jesd204_rx_avs_rst_n" altera:internal="jesd204_rx_avs_rst_n"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="jesd204_rx_dlb_data" altera:internal="jesd204_0.jesd204_rx_dlb_data" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="jesd204_rx_dlb_data" altera:internal="jesd204_rx_dlb_data"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="jesd204_rx_dlb_data_valid" altera:internal="jesd204_0.jesd204_rx_dlb_data_valid" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="jesd204_rx_dlb_data_valid" altera:internal="jesd204_rx_dlb_data_valid"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="jesd204_rx_dlb_disperr" altera:internal="jesd204_0.jesd204_rx_dlb_disperr" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="jesd204_rx_dlb_disperr" altera:internal="jesd204_rx_dlb_disperr"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="jesd204_rx_dlb_errdetect" altera:internal="jesd204_0.jesd204_rx_dlb_errdetect" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="jesd204_rx_dlb_errdetect" altera:internal="jesd204_rx_dlb_errdetect"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="jesd204_rx_dlb_kchar_data" altera:internal="jesd204_0.jesd204_rx_dlb_kchar_data" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="jesd204_rx_dlb_kchar_data" altera:internal="jesd204_rx_dlb_kchar_data"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="jesd204_rx_frame_error" altera:internal="jesd204_0.jesd204_rx_frame_error" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="jesd204_rx_frame_error" altera:internal="jesd204_rx_frame_error"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="jesd204_rx_int" altera:internal="jesd204_0.jesd204_rx_int" altera:type="interrupt" altera:dir="end">
+ <altera:port_mapping altera:name="jesd204_rx_int" altera:internal="jesd204_rx_int"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="jesd204_rx_link" altera:internal="jesd204_0.jesd204_rx_link" altera:type="avalon_streaming" altera:dir="start">
+ <altera:port_mapping altera:name="jesd204_rx_link_data" altera:internal="jesd204_rx_link_data"></altera:port_mapping>
+ <altera:port_mapping altera:name="jesd204_rx_link_ready" altera:internal="jesd204_rx_link_ready"></altera:port_mapping>
+ <altera:port_mapping altera:name="jesd204_rx_link_valid" altera:internal="jesd204_rx_link_valid"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="jesd204_tx_avs" altera:internal="jesd204_0.jesd204_tx_avs"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="jesd204_tx_avs_clk" altera:internal="jesd204_0.jesd204_tx_avs_clk"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="jesd204_tx_avs_rst_n" altera:internal="jesd204_0.jesd204_tx_avs_rst_n"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="jesd204_tx_dlb_data" altera:internal="jesd204_0.jesd204_tx_dlb_data"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="jesd204_tx_dlb_kchar_data" altera:internal="jesd204_0.jesd204_tx_dlb_kchar_data"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="jesd204_tx_frame_error" altera:internal="jesd204_0.jesd204_tx_frame_error"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="jesd204_tx_frame_ready" altera:internal="jesd204_0.jesd204_tx_frame_ready"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="jesd204_tx_int" altera:internal="jesd204_0.jesd204_tx_int"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="jesd204_tx_link" altera:internal="jesd204_0.jesd204_tx_link"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="mdev_sync_n" altera:internal="jesd204_0.mdev_sync_n"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="pll_locked" altera:internal="jesd204_0.pll_locked"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="pll_ref_clk" altera:internal="jesd204_0.pll_ref_clk" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="pll_ref_clk" altera:internal="pll_ref_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_analogreset" altera:internal="jesd204_0.rx_analogreset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="rx_analogreset" altera:internal="rx_analogreset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_cal_busy" altera:internal="jesd204_0.rx_cal_busy" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="rx_cal_busy" altera:internal="rx_cal_busy"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_csr_cf" altera:internal="jesd204_0.rx_csr_cf"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_csr_cs" altera:internal="jesd204_0.rx_csr_cs"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_csr_f" altera:internal="jesd204_0.rx_csr_f"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_csr_hd" altera:internal="jesd204_0.rx_csr_hd"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_csr_k" altera:internal="jesd204_0.rx_csr_k"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_csr_l" altera:internal="jesd204_0.rx_csr_l"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_csr_lane_powerdown" altera:internal="jesd204_0.rx_csr_lane_powerdown"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_csr_m" altera:internal="jesd204_0.rx_csr_m"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_csr_n" altera:internal="jesd204_0.rx_csr_n"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_csr_np" altera:internal="jesd204_0.rx_csr_np"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_csr_s" altera:internal="jesd204_0.rx_csr_s"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_dev_sync_n" altera:internal="jesd204_0.rx_dev_sync_n"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_digitalreset" altera:internal="jesd204_0.rx_digitalreset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="rx_digitalreset" altera:internal="rx_digitalreset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_islockedtodata" altera:internal="jesd204_0.rx_islockedtodata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="rx_islockedtodata" altera:internal="rx_islockedtodata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_pll_ref_clk" altera:internal="jesd204_0.rx_pll_ref_clk"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_serial_data" altera:internal="jesd204_0.rx_serial_data" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="rx_serial_data" altera:internal="rx_serial_data"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_seriallpbken" altera:internal="jesd204_0.rx_seriallpbken"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_sof" altera:internal="jesd204_0.rx_sof"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_somf" altera:internal="jesd204_0.rx_somf"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_sysref" altera:internal="jesd204_0.rx_sysref"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="rxlink_clk" altera:internal="jesd204_0.rxlink_clk" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="rxlink_clk" altera:internal="rxlink_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="rxlink_rst_n" altera:internal="jesd204_0.rxlink_rst_n" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="rxlink_rst_n_reset_n" altera:internal="rxlink_rst_n_reset_n"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="rxphy_clk" altera:internal="jesd204_0.rxphy_clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="rxphy_clk" altera:internal="rxphy_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="sof" altera:internal="jesd204_0.sof" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="sof" altera:internal="sof"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="somf" altera:internal="jesd204_0.somf" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="somf" altera:internal="somf"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="sync_n" altera:internal="jesd204_0.sync_n"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="sysref" altera:internal="jesd204_0.sysref" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="sysref" altera:internal="sysref"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_analogreset" altera:internal="jesd204_0.tx_analogreset"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_bonding_clocks_ch0" altera:internal="jesd204_0.tx_bonding_clocks_ch0"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_bonding_clocks_ch1" altera:internal="jesd204_0.tx_bonding_clocks_ch1"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_cal_busy" altera:internal="jesd204_0.tx_cal_busy"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_csr_cf" altera:internal="jesd204_0.tx_csr_cf"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_csr_cs" altera:internal="jesd204_0.tx_csr_cs"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_csr_f" altera:internal="jesd204_0.tx_csr_f"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_csr_hd" altera:internal="jesd204_0.tx_csr_hd"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_csr_k" altera:internal="jesd204_0.tx_csr_k"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_csr_l" altera:internal="jesd204_0.tx_csr_l"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_csr_lane_powerdown" altera:internal="jesd204_0.tx_csr_lane_powerdown"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_csr_m" altera:internal="jesd204_0.tx_csr_m"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_csr_n" altera:internal="jesd204_0.tx_csr_n"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_csr_np" altera:internal="jesd204_0.tx_csr_np"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_csr_s" altera:internal="jesd204_0.tx_csr_s"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_dev_sync_n" altera:internal="jesd204_0.tx_dev_sync_n"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_digitalreset" altera:internal="jesd204_0.tx_digitalreset"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_serial_data" altera:internal="jesd204_0.tx_serial_data"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_somf" altera:internal="jesd204_0.tx_somf"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_sysref" altera:internal="jesd204_0.tx_sysref"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="txlink_clk" altera:internal="jesd204_0.txlink_clk"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="txlink_rst_n" altera:internal="jesd204_0.txlink_rst_n"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="txphy_clk" altera:internal="jesd204_0.txphy_clk"></altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx.qsys b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..70aea1f5b102f3aa37fb0aefb87ccf793e81b113
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx.qsys
@@ -0,0 +1,3598 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_jesd204b_rx">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="System"
+ tool="QsysPro" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element jesd204_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>jesd204_rx_avs</key>
+ <value>
+ <connectionPointName>jesd204_rx_avs</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='jesd204_0.jesd204_rx_avs' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>10</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="csr_cf" internal="jesd204_0.csr_cf" type="conduit" dir="end" />
+ <interface name="csr_cs" internal="jesd204_0.csr_cs" type="conduit" dir="end" />
+ <interface name="csr_f" internal="jesd204_0.csr_f" type="conduit" dir="end" />
+ <interface name="csr_hd" internal="jesd204_0.csr_hd" type="conduit" dir="end" />
+ <interface name="csr_k" internal="jesd204_0.csr_k" type="conduit" dir="end" />
+ <interface name="csr_l" internal="jesd204_0.csr_l" type="conduit" dir="end" />
+ <interface
+ name="csr_lane_powerdown"
+ internal="jesd204_0.csr_lane_powerdown"
+ type="conduit"
+ dir="end" />
+ <interface name="csr_m" internal="jesd204_0.csr_m" type="conduit" dir="end" />
+ <interface name="csr_n" internal="jesd204_0.csr_n" type="conduit" dir="end" />
+ <interface name="csr_np" internal="jesd204_0.csr_np" type="conduit" dir="end" />
+ <interface
+ name="csr_rx_testmode"
+ internal="jesd204_0.csr_rx_testmode"
+ type="conduit"
+ dir="end" />
+ <interface name="csr_s" internal="jesd204_0.csr_s" type="conduit" dir="end" />
+ <interface
+ name="dev_lane_aligned"
+ internal="jesd204_0.dev_lane_aligned"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="dev_sync_n"
+ internal="jesd204_0.dev_sync_n"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="jesd204_0_alldev_lane_aligned"
+ internal="jesd204_0.alldev_lane_aligned"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="jesd204_rx_avs"
+ internal="jesd204_0.jesd204_rx_avs"
+ type="avalon"
+ dir="end" />
+ <interface
+ name="jesd204_rx_avs_clk"
+ internal="jesd204_0.jesd204_rx_avs_clk"
+ type="clock"
+ dir="end" />
+ <interface
+ name="jesd204_rx_avs_rst_n"
+ internal="jesd204_0.jesd204_rx_avs_rst_n"
+ type="reset"
+ dir="end" />
+ <interface
+ name="jesd204_rx_dlb_data"
+ internal="jesd204_0.jesd204_rx_dlb_data"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="jesd204_rx_dlb_data_valid"
+ internal="jesd204_0.jesd204_rx_dlb_data_valid"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="jesd204_rx_dlb_disperr"
+ internal="jesd204_0.jesd204_rx_dlb_disperr"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="jesd204_rx_dlb_errdetect"
+ internal="jesd204_0.jesd204_rx_dlb_errdetect"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="jesd204_rx_dlb_kchar_data"
+ internal="jesd204_0.jesd204_rx_dlb_kchar_data"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="jesd204_rx_frame_error"
+ internal="jesd204_0.jesd204_rx_frame_error"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="jesd204_rx_int"
+ internal="jesd204_0.jesd204_rx_int"
+ type="interrupt"
+ dir="end" />
+ <interface
+ name="jesd204_rx_link"
+ internal="jesd204_0.jesd204_rx_link"
+ type="avalon_streaming"
+ dir="start" />
+ <interface
+ name="pll_ref_clk"
+ internal="jesd204_0.pll_ref_clk"
+ type="clock"
+ dir="end" />
+ <interface
+ name="rx_analogreset"
+ internal="jesd204_0.rx_analogreset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rx_cal_busy"
+ internal="jesd204_0.rx_cal_busy"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rx_digitalreset"
+ internal="jesd204_0.rx_digitalreset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rx_islockedtodata"
+ internal="jesd204_0.rx_islockedtodata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rx_serial_data"
+ internal="jesd204_0.rx_serial_data"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rxlink_clk"
+ internal="jesd204_0.rxlink_clk"
+ type="clock"
+ dir="end" />
+ <interface
+ name="rxlink_rst_n"
+ internal="jesd204_0.rxlink_rst_n"
+ type="reset"
+ dir="end" />
+ <interface
+ name="rxphy_clk"
+ internal="jesd204_0.rxphy_clk"
+ type="conduit"
+ dir="end" />
+ <interface name="sof" internal="jesd204_0.sof" type="conduit" dir="end" />
+ <interface name="somf" internal="jesd204_0.somf" type="conduit" dir="end" />
+ <interface name="sysref" internal="jesd204_0.sysref" type="conduit" dir="end" />
+ <module
+ name="jesd204_0"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>alldev_lane_aligned</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>alldev_lane_aligned</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_cf</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_cf</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_cs</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_cs</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>2</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_f</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_f</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_hd</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_hd</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_k</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_k</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_l</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_l</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_lane_powerdown</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_lane_powerdown</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_m</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_m</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_n</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_n</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_np</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_np</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_rx_testmode</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_rx_testmode</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_s</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_s</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>dev_lane_aligned</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>dev_lane_aligned</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>dev_sync_n</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>dev_sync_n</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_avs</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_avs_chipselect</name>
+ <role>chipselect</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>jesd204_rx_avs_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>jesd204_rx_avs_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>jesd204_rx_avs_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>jesd204_rx_avs_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>jesd204_rx_avs_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>jesd204_rx_avs_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>1024</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>jesd204_rx_avs_clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>jesd204_rx_avs_rst_n</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_avs_clk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_avs_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_avs_rst_n</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_avs_rst_n</name>
+ <role>reset_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>jesd204_rx_avs_clk</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_dlb_data</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_dlb_data</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_dlb_data_valid</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_dlb_data_valid</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_dlb_disperr</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_dlb_disperr</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_dlb_errdetect</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_dlb_errdetect</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_dlb_kchar_data</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_dlb_kchar_data</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_frame_error</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_frame_error</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_int</name>
+ <type>interrupt</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_int</name>
+ <role>irq</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedAddressablePoint</key>
+ <value>jesd204_0.jesd204_rx_avs</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>jesd204_rx_avs_clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>jesd204_rx_avs_rst_n</value>
+ </entry>
+ <entry>
+ <key>bridgedReceiverOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToReceiver</key>
+ </entry>
+ <entry>
+ <key>irqScheme</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_link</name>
+ <type>avalon_streaming</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_link_data</name>
+ <role>data</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>jesd204_rx_link_valid</name>
+ <role>valid</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>jesd204_rx_link_ready</name>
+ <role>ready</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>rxlink_clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>rxlink_rst_n</value>
+ </entry>
+ <entry>
+ <key>beatsPerCycle</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>dataBitsPerSymbol</key>
+ <value>32</value>
+ </entry>
+ <entry>
+ <key>emptyWithinPacket</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>errorDescriptor</key>
+ </entry>
+ <entry>
+ <key>firstSymbolInHighOrderBits</key>
+ <value>true</value>
+ </entry>
+ <entry>
+ <key>highOrderSymbolAtMSB</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maxChannel</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>packetDescription</key>
+ <value></value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readyAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readyLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>symbolsPerBeat</key>
+ <value>1</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>pll_ref_clk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>pll_ref_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_analogreset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_analogreset</name>
+ <role>rx_analogreset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_cal_busy</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_cal_busy</name>
+ <role>rx_cal_busy</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_digitalreset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_digitalreset</name>
+ <role>rx_digitalreset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_islockedtodata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_islockedtodata</name>
+ <role>rx_is_lockedtodata</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_serial_data</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_serial_data</name>
+ <role>rx_serial_data</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rxlink_clk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rxlink_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rxlink_rst_n</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rxlink_rst_n_reset_n</name>
+ <role>reset_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>rxlink_clk</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rxphy_clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rxphy_clk</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>sof</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>sof</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>somf</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>somf</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>sysref</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>sysref</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>altera_jesd204</className>
+ <version>19.2.0</version>
+ <displayName>JESD204B Intel FPGA IP</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors/>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>jesd204_rx_avs</key>
+ <value>
+ <connectionPointName>jesd204_rx_avs</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='jesd204_rx_avs' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>10</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>rxlink_clk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rxlink_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rxlink_rst_n</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rxlink_rst_n_reset_n</name>
+ <role>reset_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>rxlink_clk</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_avs_clk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_avs_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_avs_rst_n</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_avs_rst_n</name>
+ <role>reset_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>jesd204_rx_avs_clk</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_avs</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_avs_chipselect</name>
+ <role>chipselect</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>jesd204_rx_avs_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>jesd204_rx_avs_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>jesd204_rx_avs_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>jesd204_rx_avs_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>jesd204_rx_avs_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>jesd204_rx_avs_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>1024</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>jesd204_rx_avs_clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>jesd204_rx_avs_rst_n</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_link</name>
+ <type>avalon_streaming</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_link_data</name>
+ <role>data</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>jesd204_rx_link_valid</name>
+ <role>valid</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>jesd204_rx_link_ready</name>
+ <role>ready</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>rxlink_clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>rxlink_rst_n</value>
+ </entry>
+ <entry>
+ <key>beatsPerCycle</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>dataBitsPerSymbol</key>
+ <value>32</value>
+ </entry>
+ <entry>
+ <key>emptyWithinPacket</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>errorDescriptor</key>
+ </entry>
+ <entry>
+ <key>firstSymbolInHighOrderBits</key>
+ <value>true</value>
+ </entry>
+ <entry>
+ <key>highOrderSymbolAtMSB</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maxChannel</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>packetDescription</key>
+ <value></value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readyAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readyLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>symbolsPerBeat</key>
+ <value>1</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>sof</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>sof</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>somf</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>somf</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>alldev_lane_aligned</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>alldev_lane_aligned</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>dev_lane_aligned</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>dev_lane_aligned</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>dev_sync_n</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>dev_sync_n</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>sysref</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>sysref</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_int</name>
+ <type>interrupt</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_int</name>
+ <role>irq</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedAddressablePoint</key>
+ <value>jesd204_0.jesd204_rx_avs</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>jesd204_rx_avs_clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>jesd204_rx_avs_rst_n</value>
+ </entry>
+ <entry>
+ <key>bridgedReceiverOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToReceiver</key>
+ </entry>
+ <entry>
+ <key>irqScheme</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_rx_testmode</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_rx_testmode</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_f</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_f</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_k</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_k</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_l</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_l</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_m</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_m</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_n</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_n</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_s</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_s</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_cf</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_cf</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_cs</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_cs</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>2</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_hd</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_hd</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_np</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_np</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_lane_powerdown</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_lane_powerdown</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_frame_error</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_frame_error</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_dlb_data</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_dlb_data</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_dlb_data_valid</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_dlb_data_valid</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_dlb_kchar_data</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_dlb_kchar_data</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_dlb_errdetect</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_dlb_errdetect</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>jesd204_rx_dlb_disperr</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>jesd204_rx_dlb_disperr</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>pll_ref_clk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>pll_ref_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rxphy_clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rxphy_clk</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_islockedtodata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_islockedtodata</name>
+ <role>rx_is_lockedtodata</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_cal_busy</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_cal_busy</name>
+ <role>rx_cal_busy</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_analogreset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_analogreset</name>
+ <role>rx_analogreset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_digitalreset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_digitalreset</name>
+ <role>rx_digitalreset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_serial_data</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_serial_data</name>
+ <role>rx_serial_data</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>ip_arria10_e2sg_jesd204b_rx</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>ip_arria10_e2sg_jesd204b_rx</fileSetName>
+ <fileSetFixedName>ip_arria10_e2sg_jesd204b_rx</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>ip_arria10_e2sg_jesd204b_rx</fileSetName>
+ <fileSetFixedName>ip_arria10_e2sg_jesd204b_rx</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>ip_arria10_e2sg_jesd204b_rx</fileSetName>
+ <fileSetFixedName>ip_arria10_e2sg_jesd204b_rx</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip_arria10_e2sg_jesd204b_rx.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx_core_pll.ip b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx_core_pll.ip
new file mode 100644
index 0000000000000000000000000000000000000000..cd75f5aaff5bcf7698fdfa8131ec61f6721f3e88
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx_core_pll.ip
@@ -0,0 +1,4186 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>Intel Corporation</spirit:vendor>
+ <spirit:library>ip_arria10_e2sg_jesd204b_rx_core_pll</spirit:library>
+ <spirit:name>core_pll</spirit:name>
+ <spirit:version>18.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>locked</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>locked</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>outclk0</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:master></spirit:master>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>outclk_0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedDirectClock</spirit:name>
+ <spirit:displayName>Associated direct clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedDirectClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">100000000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clockRateKnown</spirit:name>
+ <spirit:displayName>Clock rate known</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="clockRateKnown">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>outclk1</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:master></spirit:master>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>outclk_1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedDirectClock</spirit:name>
+ <spirit:displayName>Associated direct clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedDirectClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">200000000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clockRateKnown</spirit:name>
+ <spirit:displayName>Clock rate known</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="clockRateKnown">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>refclk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>refclk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">200000000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rst</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">NONE</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>altera_iopll</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>rst</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>refclk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>locked</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>outclk_0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>outclk_1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>Intel Corporation</spirit:vendor>
+ <spirit:library>ip_arria10_e2sg_jesd204b_rx_core_pll</spirit:library>
+ <spirit:name>altera_iopll</spirit:name>
+ <spirit:version>18.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>gui_device_family</spirit:name>
+ <spirit:displayName>Device Family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_device_family">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_device_component</spirit:name>
+ <spirit:displayName>Component</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_device_component">10AX115U3F45E2SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_device_speed_grade</spirit:name>
+ <spirit:displayName>Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_device_speed_grade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_debug_mode</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_debug_mode">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_skip_sdc_generation</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_skip_sdc_generation">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_include_iossm</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_include_iossm">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cal_code_hex_file</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_cal_code_hex_file">iossm.hex</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_parameter_table_hex_file</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_parameter_table_hex_file">seq_params_sim.hex</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_pll_tclk_mux_en</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_pll_tclk_mux_en">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_pll_tclk_sel</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_pll_tclk_sel">pll_tclk_m_src</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_pll_vco_freq_band_0</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_pll_vco_freq_band_0">pll_freq_clk0_disabled</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_pll_vco_freq_band_1</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_pll_vco_freq_band_1">pll_freq_clk1_disabled</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_pll_freqcal_en</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_pll_freqcal_en">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_pll_freqcal_req_flag</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_pll_freqcal_req_flag">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cal_converge</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_cal_converge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cal_error</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_cal_error">cal_clean</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_pll_cal_done</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_pll_cal_done">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_pll_type</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_pll_type">S10_Simple</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_pll_m_cnt_in_src</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_pll_m_cnt_in_src">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_c_cnt_in_src0</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_c_cnt_in_src0">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_c_cnt_in_src1</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_c_cnt_in_src1">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_c_cnt_in_src2</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_c_cnt_in_src2">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_c_cnt_in_src3</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_c_cnt_in_src3">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_c_cnt_in_src4</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_c_cnt_in_src4">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_c_cnt_in_src5</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_c_cnt_in_src5">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_c_cnt_in_src6</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_c_cnt_in_src6">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_c_cnt_in_src7</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_c_cnt_in_src7">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_c_cnt_in_src8</spirit:name>
+ <spirit:displayName></spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_c_cnt_in_src8">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>system_info_device_family</spirit:name>
+ <spirit:displayName>Device Family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="system_info_device_family">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>system_info_device_component</spirit:name>
+ <spirit:displayName>Component</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="system_info_device_component">10AX115U3F45E2SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>system_info_device_speed_grade</spirit:name>
+ <spirit:displayName>Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="system_info_device_speed_grade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>system_part_trait_speed_grade</spirit:name>
+ <spirit:displayName>Speed Grade Trait</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="system_part_trait_speed_grade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_usr_device_speed_grade</spirit:name>
+ <spirit:displayName>Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_usr_device_speed_grade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_en_reconf</spirit:name>
+ <spirit:displayName>Enable dynamic reconfiguration of PLL</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_en_reconf">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_en_dps_ports</spirit:name>
+ <spirit:displayName>Enable access to dynamic phase shift ports</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_en_dps_ports">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_pll_mode</spirit:name>
+ <spirit:displayName>PLL Mode</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_pll_mode">Integer-N PLL</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_use_logical</spirit:name>
+ <spirit:displayName>Use logical PLL</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_use_logical">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_reference_clock_frequency</spirit:name>
+ <spirit:displayName>Reference Clock Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_reference_clock_frequency">200.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_use_coreclk</spirit:name>
+ <spirit:displayName>Refclk source is global clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_use_coreclk">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_refclk_might_change</spirit:name>
+ <spirit:displayName>My reference clock frequency might change</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_refclk_might_change">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_fractional_cout</spirit:name>
+ <spirit:displayName>Fractional carry out</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_fractional_cout">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_prot_mode</spirit:name>
+ <spirit:displayName>prot_mode</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_prot_mode">UNUSED</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_dsm_out_sel</spirit:name>
+ <spirit:displayName>DSM Order</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_dsm_out_sel">1st_order</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_use_locked</spirit:name>
+ <spirit:displayName>Enable locked output port</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_use_locked">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_en_adv_params</spirit:name>
+ <spirit:displayName>Enable physical output clock parameters</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_en_adv_params">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_pll_bandwidth_preset</spirit:name>
+ <spirit:displayName>PLL Bandwidth Preset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_pll_bandwidth_preset">Low</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_lock_setting</spirit:name>
+ <spirit:displayName>Lock Threshold Setting</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_lock_setting">Low Lock Time</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_pll_auto_reset</spirit:name>
+ <spirit:displayName>PLL Auto Reset</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_pll_auto_reset">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_en_lvds_ports</spirit:name>
+ <spirit:displayName>Access to PLL LVDS_CLK/LOADEN output port</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_en_lvds_ports">Disabled</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_operation_mode</spirit:name>
+ <spirit:displayName>Compensation Mode</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_operation_mode">source synchronous</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_feedback_clock</spirit:name>
+ <spirit:displayName>Feedback Clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_feedback_clock">Global Clock</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clock_to_compensate</spirit:name>
+ <spirit:displayName>Compensated Outclk</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_clock_to_compensate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_use_NDFB_modes</spirit:name>
+ <spirit:displayName>Use Nondedicated Feedback Path</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_use_NDFB_modes">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_refclk_switch</spirit:name>
+ <spirit:displayName>Create a second input clock signal 'refclk1'</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_refclk_switch">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_refclk1_frequency</spirit:name>
+ <spirit:displayName>Second Reference Clock Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_refclk1_frequency">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_en_phout_ports</spirit:name>
+ <spirit:displayName>Enable access to PLL DPA output port</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_en_phout_ports">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phout_division</spirit:name>
+ <spirit:displayName>PLL DPA output division</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_phout_division">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_en_extclkout_ports</spirit:name>
+ <spirit:displayName>Enable access to PLL external clock output port</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_en_extclkout_ports">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_number_of_clocks</spirit:name>
+ <spirit:displayName>Number Of Clocks</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_number_of_clocks">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_multiply_factor</spirit:name>
+ <spirit:displayName>Multiply Factor (M-Counter)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_multiply_factor">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_divide_factor_n</spirit:name>
+ <spirit:displayName>Divide Factor (N-Counter)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_divide_factor_n">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_frac_multiply_factor</spirit:name>
+ <spirit:displayName>Fractional Multiply Factor (K)</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_frac_multiply_factor">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_fix_vco_frequency</spirit:name>
+ <spirit:displayName>Specify VCO frequency</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_fix_vco_frequency">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_fixed_vco_frequency</spirit:name>
+ <spirit:displayName>Desired VCO Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_fixed_vco_frequency">600.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_vco_frequency</spirit:name>
+ <spirit:displayName>Actual VCO Frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_vco_frequency">600.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_enable_output_counter_cascading</spirit:name>
+ <spirit:displayName>Enable output counter cascading</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_enable_output_counter_cascading">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_mif_gen_options</spirit:name>
+ <spirit:displayName>MIF Generation Options</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_mif_gen_options">Generate New MIF File</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_new_mif_file_path</spirit:name>
+ <spirit:displayName>Path to New MIF file</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_new_mif_file_path">~/pll.mif</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_existing_mif_file_path</spirit:name>
+ <spirit:displayName>Path to Existing MIF file</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_existing_mif_file_path">~/pll.mif</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_mif_config_name</spirit:name>
+ <spirit:displayName>Name of Current Configuration</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_mif_config_name">unnamed</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_active_clk</spirit:name>
+ <spirit:displayName>Create an 'active_clk' signal to indicate the input clock in use</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_active_clk">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clk_bad</spirit:name>
+ <spirit:displayName>Create a 'clkbad' signal for each of the input clocks</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_clk_bad">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_switchover_mode</spirit:name>
+ <spirit:displayName>Switchover Mode</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_switchover_mode">Automatic Switchover</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_switchover_delay</spirit:name>
+ <spirit:displayName>Switchover Delay</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_switchover_delay">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_enable_cascade_out</spirit:name>
+ <spirit:displayName>Create a 'cascade_out' signal to connect to a downstream PLL</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_enable_cascade_out">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cascade_outclk_index</spirit:name>
+ <spirit:displayName>cascade_out source</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_cascade_outclk_index">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_enable_cascade_in</spirit:name>
+ <spirit:displayName>Create an 'adjpllin' (cascade in) signal to connect to an upstream PLL through IO Column Cascading</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_enable_cascade_in">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_enable_permit_cal</spirit:name>
+ <spirit:displayName>Connect to an upstream PLL through Core Clock Network Cascading (create a permit_cal input signal)</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_enable_permit_cal">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_pll_cascading_mode</spirit:name>
+ <spirit:displayName>Connection Signal Type to Upstream PLL</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_pll_cascading_mode">adjpllin</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_enable_mif_dps</spirit:name>
+ <spirit:displayName>Enable Dynamic Phase Shift for MIF streaming</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_enable_mif_dps">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_dps_cntr</spirit:name>
+ <spirit:displayName>DPS Counter Selection</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_dps_cntr">C0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_dps_num</spirit:name>
+ <spirit:displayName>Number of Dynamic Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_dps_num">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_dps_dir</spirit:name>
+ <spirit:displayName>Dynamic Phase Shift Direction</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_dps_dir">Positive</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_extclkout_0_source</spirit:name>
+ <spirit:displayName>extclk_out[0] source</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_extclkout_0_source">C0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_extclkout_1_source</spirit:name>
+ <spirit:displayName>extclk_out[1] source</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_extclkout_1_source">C0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clock_name_global</spirit:name>
+ <spirit:displayName>Give clocks global names</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_clock_name_global">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clock_name_string0</spirit:name>
+ <spirit:displayName>Clock Name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_clock_name_string0">link_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clock_name_string1</spirit:name>
+ <spirit:displayName>Clock Name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_clock_name_string1">frame_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clock_name_string2</spirit:name>
+ <spirit:displayName>Clock Name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_clock_name_string2">outclk2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clock_name_string3</spirit:name>
+ <spirit:displayName>Clock Name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_clock_name_string3">outclk3</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clock_name_string4</spirit:name>
+ <spirit:displayName>Clock Name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_clock_name_string4">outclk4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clock_name_string5</spirit:name>
+ <spirit:displayName>Clock Name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_clock_name_string5">outclk5</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clock_name_string6</spirit:name>
+ <spirit:displayName>Clock Name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_clock_name_string6">outclk6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clock_name_string7</spirit:name>
+ <spirit:displayName>Clock Name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_clock_name_string7">outclk7</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clock_name_string8</spirit:name>
+ <spirit:displayName>Clock Name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_clock_name_string8">outclk8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clock_name_string9</spirit:name>
+ <spirit:displayName>Clock Name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_clock_name_string9">outclk9</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clock_name_string10</spirit:name>
+ <spirit:displayName>Clock Name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_clock_name_string10">outclk10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clock_name_string11</spirit:name>
+ <spirit:displayName>Clock Name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_clock_name_string11">outclk11</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clock_name_string12</spirit:name>
+ <spirit:displayName>Clock Name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_clock_name_string12">outclk12</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clock_name_string13</spirit:name>
+ <spirit:displayName>Clock Name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_clock_name_string13">outclk13</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clock_name_string14</spirit:name>
+ <spirit:displayName>Clock Name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_clock_name_string14">outclk14</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clock_name_string15</spirit:name>
+ <spirit:displayName>Clock Name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_clock_name_string15">outclk15</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clock_name_string16</spirit:name>
+ <spirit:displayName>Clock Name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_clock_name_string16">outclk16</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_clock_name_string17</spirit:name>
+ <spirit:displayName>Clock Name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_clock_name_string17">outclk17</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_divide_factor_c0</spirit:name>
+ <spirit:displayName>Divide Factor (C-Counter)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_divide_factor_c0">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_divide_factor_c1</spirit:name>
+ <spirit:displayName>Divide Factor (C-Counter)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_divide_factor_c1">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_divide_factor_c2</spirit:name>
+ <spirit:displayName>Divide Factor (C-Counter)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_divide_factor_c2">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_divide_factor_c3</spirit:name>
+ <spirit:displayName>Divide Factor (C-Counter)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_divide_factor_c3">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_divide_factor_c4</spirit:name>
+ <spirit:displayName>Divide Factor (C-Counter)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_divide_factor_c4">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_divide_factor_c5</spirit:name>
+ <spirit:displayName>Divide Factor (C-Counter)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_divide_factor_c5">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_divide_factor_c6</spirit:name>
+ <spirit:displayName>Divide Factor (C-Counter)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_divide_factor_c6">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_divide_factor_c7</spirit:name>
+ <spirit:displayName>Divide Factor (C-Counter)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_divide_factor_c7">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_divide_factor_c8</spirit:name>
+ <spirit:displayName>Divide Factor (C-Counter)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_divide_factor_c8">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_divide_factor_c9</spirit:name>
+ <spirit:displayName>Divide Factor (C-Counter)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_divide_factor_c9">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_divide_factor_c10</spirit:name>
+ <spirit:displayName>Divide Factor (C-Counter)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_divide_factor_c10">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_divide_factor_c11</spirit:name>
+ <spirit:displayName>Divide Factor (C-Counter)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_divide_factor_c11">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_divide_factor_c12</spirit:name>
+ <spirit:displayName>Divide Factor (C-Counter)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_divide_factor_c12">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_divide_factor_c13</spirit:name>
+ <spirit:displayName>Divide Factor (C-Counter)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_divide_factor_c13">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_divide_factor_c14</spirit:name>
+ <spirit:displayName>Divide Factor (C-Counter)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_divide_factor_c14">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_divide_factor_c15</spirit:name>
+ <spirit:displayName>Divide Factor (C-Counter)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_divide_factor_c15">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_divide_factor_c16</spirit:name>
+ <spirit:displayName>Divide Factor (C-Counter)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_divide_factor_c16">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_divide_factor_c17</spirit:name>
+ <spirit:displayName>Divide Factor (C-Counter)</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_divide_factor_c17">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cascade_counter0</spirit:name>
+ <spirit:displayName>Make this a cascade counter</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_cascade_counter0">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cascade_counter1</spirit:name>
+ <spirit:displayName>Make this a cascade counter</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_cascade_counter1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cascade_counter2</spirit:name>
+ <spirit:displayName>Make this a cascade counter</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_cascade_counter2">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cascade_counter3</spirit:name>
+ <spirit:displayName>Make this a cascade counter</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_cascade_counter3">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cascade_counter4</spirit:name>
+ <spirit:displayName>Make this a cascade counter</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_cascade_counter4">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cascade_counter5</spirit:name>
+ <spirit:displayName>Make this a cascade counter</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_cascade_counter5">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cascade_counter6</spirit:name>
+ <spirit:displayName>Make this a cascade counter</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_cascade_counter6">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cascade_counter7</spirit:name>
+ <spirit:displayName>Make this a cascade counter</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_cascade_counter7">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cascade_counter8</spirit:name>
+ <spirit:displayName>Make this a cascade counter</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_cascade_counter8">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cascade_counter9</spirit:name>
+ <spirit:displayName>Make this a cascade counter</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_cascade_counter9">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cascade_counter10</spirit:name>
+ <spirit:displayName>Make this a cascade counter</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_cascade_counter10">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cascade_counter11</spirit:name>
+ <spirit:displayName>Make this a cascade counter</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_cascade_counter11">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cascade_counter12</spirit:name>
+ <spirit:displayName>Make this a cascade counter</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_cascade_counter12">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cascade_counter13</spirit:name>
+ <spirit:displayName>Make this a cascade counter</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_cascade_counter13">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cascade_counter14</spirit:name>
+ <spirit:displayName>Make this a cascade counter</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_cascade_counter14">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cascade_counter15</spirit:name>
+ <spirit:displayName>Make this a cascade counter</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_cascade_counter15">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cascade_counter16</spirit:name>
+ <spirit:displayName>Make this a cascade counter</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_cascade_counter16">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_cascade_counter17</spirit:name>
+ <spirit:displayName>Make this a cascade counter</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="gui_cascade_counter17">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_output_clock_frequency0</spirit:name>
+ <spirit:displayName>Desired Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_output_clock_frequency0">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_output_clock_frequency1</spirit:name>
+ <spirit:displayName>Desired Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_output_clock_frequency1">200.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_output_clock_frequency2</spirit:name>
+ <spirit:displayName>Desired Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_output_clock_frequency2">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_output_clock_frequency3</spirit:name>
+ <spirit:displayName>Desired Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_output_clock_frequency3">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_output_clock_frequency4</spirit:name>
+ <spirit:displayName>Desired Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_output_clock_frequency4">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_output_clock_frequency5</spirit:name>
+ <spirit:displayName>Desired Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_output_clock_frequency5">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_output_clock_frequency6</spirit:name>
+ <spirit:displayName>Desired Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_output_clock_frequency6">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_output_clock_frequency7</spirit:name>
+ <spirit:displayName>Desired Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_output_clock_frequency7">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_output_clock_frequency8</spirit:name>
+ <spirit:displayName>Desired Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_output_clock_frequency8">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_output_clock_frequency9</spirit:name>
+ <spirit:displayName>Desired Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_output_clock_frequency9">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_output_clock_frequency10</spirit:name>
+ <spirit:displayName>Desired Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_output_clock_frequency10">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_output_clock_frequency11</spirit:name>
+ <spirit:displayName>Desired Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_output_clock_frequency11">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_output_clock_frequency12</spirit:name>
+ <spirit:displayName>Desired Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_output_clock_frequency12">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_output_clock_frequency13</spirit:name>
+ <spirit:displayName>Desired Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_output_clock_frequency13">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_output_clock_frequency14</spirit:name>
+ <spirit:displayName>Desired Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_output_clock_frequency14">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_output_clock_frequency15</spirit:name>
+ <spirit:displayName>Desired Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_output_clock_frequency15">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_output_clock_frequency16</spirit:name>
+ <spirit:displayName>Desired Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_output_clock_frequency16">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_output_clock_frequency17</spirit:name>
+ <spirit:displayName>Desired Frequency</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_output_clock_frequency17">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency0</spirit:name>
+ <spirit:displayName>Actual Frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency0">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency1</spirit:name>
+ <spirit:displayName>Actual Frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency1">200.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency2</spirit:name>
+ <spirit:displayName>Actual Frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency2">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency3</spirit:name>
+ <spirit:displayName>Actual Frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency3">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency4</spirit:name>
+ <spirit:displayName>Actual Frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency4">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency5</spirit:name>
+ <spirit:displayName>Actual Frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency5">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency6</spirit:name>
+ <spirit:displayName>Actual Frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency6">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency7</spirit:name>
+ <spirit:displayName>Actual Frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency7">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency8</spirit:name>
+ <spirit:displayName>Actual Frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency8">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency9</spirit:name>
+ <spirit:displayName>Actual Frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency9">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency10</spirit:name>
+ <spirit:displayName>Actual Frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency10">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency11</spirit:name>
+ <spirit:displayName>Actual Frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency11">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency12</spirit:name>
+ <spirit:displayName>Actual Frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency12">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency13</spirit:name>
+ <spirit:displayName>Actual Frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency13">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency14</spirit:name>
+ <spirit:displayName>Actual Frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency14">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency15</spirit:name>
+ <spirit:displayName>Actual Frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency15">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency16</spirit:name>
+ <spirit:displayName>Actual Frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency16">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency17</spirit:name>
+ <spirit:displayName>Actual Frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency17">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency_range0</spirit:name>
+ <spirit:displayName>Legal Frequencies</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency_range0">99.595142,99.607843,99.649123,100.0,100.350877,100.392157</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency_range1</spirit:name>
+ <spirit:displayName>Legal Frequencies</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency_range1">183.333333,185.714286,187.5,200.0,214.285714,216.666667</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency_range2</spirit:name>
+ <spirit:displayName>Legal Frequencies</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency_range2">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency_range3</spirit:name>
+ <spirit:displayName>Legal Frequencies</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency_range3">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency_range4</spirit:name>
+ <spirit:displayName>Legal Frequencies</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency_range4">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency_range5</spirit:name>
+ <spirit:displayName>Legal Frequencies</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency_range5">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency_range6</spirit:name>
+ <spirit:displayName>Legal Frequencies</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency_range6">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency_range7</spirit:name>
+ <spirit:displayName>Legal Frequencies</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency_range7">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency_range8</spirit:name>
+ <spirit:displayName>Legal Frequencies</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency_range8">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency_range9</spirit:name>
+ <spirit:displayName>Legal Frequencies</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency_range9">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency_range10</spirit:name>
+ <spirit:displayName>Legal Frequencies</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency_range10">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency_range11</spirit:name>
+ <spirit:displayName>Legal Frequencies</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency_range11">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency_range12</spirit:name>
+ <spirit:displayName>Legal Frequencies</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency_range12">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency_range13</spirit:name>
+ <spirit:displayName>Legal Frequencies</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency_range13">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency_range14</spirit:name>
+ <spirit:displayName>Legal Frequencies</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency_range14">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency_range15</spirit:name>
+ <spirit:displayName>Legal Frequencies</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency_range15">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency_range16</spirit:name>
+ <spirit:displayName>Legal Frequencies</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency_range16">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_output_clock_frequency_range17</spirit:name>
+ <spirit:displayName>Legal Frequencies</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_output_clock_frequency_range17">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_ps_units0</spirit:name>
+ <spirit:displayName>Phase Shift Units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_ps_units0">ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_ps_units1</spirit:name>
+ <spirit:displayName>Phase Shift Units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_ps_units1">ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_ps_units2</spirit:name>
+ <spirit:displayName>Phase Shift Units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_ps_units2">ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_ps_units3</spirit:name>
+ <spirit:displayName>Phase Shift Units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_ps_units3">ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_ps_units4</spirit:name>
+ <spirit:displayName>Phase Shift Units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_ps_units4">ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_ps_units5</spirit:name>
+ <spirit:displayName>Phase Shift Units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_ps_units5">ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_ps_units6</spirit:name>
+ <spirit:displayName>Phase Shift Units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_ps_units6">ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_ps_units7</spirit:name>
+ <spirit:displayName>Phase Shift Units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_ps_units7">ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_ps_units8</spirit:name>
+ <spirit:displayName>Phase Shift Units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_ps_units8">ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_ps_units9</spirit:name>
+ <spirit:displayName>Phase Shift Units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_ps_units9">ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_ps_units10</spirit:name>
+ <spirit:displayName>Phase Shift Units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_ps_units10">ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_ps_units11</spirit:name>
+ <spirit:displayName>Phase Shift Units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_ps_units11">ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_ps_units12</spirit:name>
+ <spirit:displayName>Phase Shift Units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_ps_units12">ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_ps_units13</spirit:name>
+ <spirit:displayName>Phase Shift Units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_ps_units13">ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_ps_units14</spirit:name>
+ <spirit:displayName>Phase Shift Units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_ps_units14">ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_ps_units15</spirit:name>
+ <spirit:displayName>Phase Shift Units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_ps_units15">ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_ps_units16</spirit:name>
+ <spirit:displayName>Phase Shift Units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_ps_units16">ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_ps_units17</spirit:name>
+ <spirit:displayName>Phase Shift Units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_ps_units17">ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift0</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift0">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift1</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift1">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift2</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift2">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift3</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift3">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift4</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift4">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift5</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift5">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift6</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift6">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift7</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift7">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift8</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift8">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift9</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift9">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift10</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift10">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift11</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift11">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift12</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift12">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift13</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift13">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift14</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift14">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift15</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift15">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift16</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift16">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift17</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift17">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift_deg0</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift_deg0">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift_deg1</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift_deg1">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift_deg2</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift_deg2">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift_deg3</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift_deg3">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift_deg4</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift_deg4">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift_deg5</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift_deg5">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift_deg6</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift_deg6">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift_deg7</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift_deg7">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift_deg8</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift_deg8">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift_deg9</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift_deg9">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift_deg10</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift_deg10">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift_deg11</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift_deg11">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift_deg12</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift_deg12">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift_deg13</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift_deg13">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift_deg14</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift_deg14">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift_deg15</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift_deg15">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift_deg16</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift_deg16">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_phase_shift_deg17</spirit:name>
+ <spirit:displayName>Desired Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_phase_shift_deg17">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift0</spirit:name>
+ <spirit:displayName>Actual phase shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift0">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift1</spirit:name>
+ <spirit:displayName>Actual phase shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift1">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift2</spirit:name>
+ <spirit:displayName>Actual phase shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift2">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift3</spirit:name>
+ <spirit:displayName>Actual phase shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift3">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift4</spirit:name>
+ <spirit:displayName>Actual phase shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift4">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift5</spirit:name>
+ <spirit:displayName>Actual phase shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift5">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift6</spirit:name>
+ <spirit:displayName>Actual phase shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift6">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift7</spirit:name>
+ <spirit:displayName>Actual phase shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift7">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift8</spirit:name>
+ <spirit:displayName>Actual phase shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift8">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift9</spirit:name>
+ <spirit:displayName>Actual phase shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift9">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift10</spirit:name>
+ <spirit:displayName>Actual phase shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift10">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift11</spirit:name>
+ <spirit:displayName>Actual phase shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift11">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift12</spirit:name>
+ <spirit:displayName>Actual phase shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift12">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift13</spirit:name>
+ <spirit:displayName>Actual phase shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift13">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift14</spirit:name>
+ <spirit:displayName>Actual phase shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift14">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift15</spirit:name>
+ <spirit:displayName>Actual phase shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift15">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift16</spirit:name>
+ <spirit:displayName>Actual phase shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift16">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift17</spirit:name>
+ <spirit:displayName>Actual phase shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift17">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_range0</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_range0">0.0,78.1,89.3,104.2,125.0,156.2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_range1</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_range1">0.0,78.1,89.3,104.2,125.0,156.2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_range2</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_range2">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_range3</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_range3">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_range4</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_range4">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_range5</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_range5">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_range6</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_range6">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_range7</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_range7">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_range8</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_range8">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_range9</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_range9">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_range10</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_range10">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_range11</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_range11">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_range12</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_range12">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_range13</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_range13">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_range14</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_range14">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_range15</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_range15">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_range16</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_range16">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_range17</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_range17">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg0</spirit:name>
+ <spirit:displayName>Actual Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg0">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg1</spirit:name>
+ <spirit:displayName>Actual Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg1">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg2</spirit:name>
+ <spirit:displayName>Actual Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg2">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg3</spirit:name>
+ <spirit:displayName>Actual Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg3">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg4</spirit:name>
+ <spirit:displayName>Actual Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg4">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg5</spirit:name>
+ <spirit:displayName>Actual Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg5">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg6</spirit:name>
+ <spirit:displayName>Actual Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg6">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg7</spirit:name>
+ <spirit:displayName>Actual Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg7">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg8</spirit:name>
+ <spirit:displayName>Actual Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg8">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg9</spirit:name>
+ <spirit:displayName>Actual Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg9">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg10</spirit:name>
+ <spirit:displayName>Actual Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg10">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg11</spirit:name>
+ <spirit:displayName>Actual Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg11">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg12</spirit:name>
+ <spirit:displayName>Actual Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg12">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg13</spirit:name>
+ <spirit:displayName>Actual Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg13">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg14</spirit:name>
+ <spirit:displayName>Actual Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg14">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg15</spirit:name>
+ <spirit:displayName>Actual Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg15">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg16</spirit:name>
+ <spirit:displayName>Actual Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg16">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg17</spirit:name>
+ <spirit:displayName>Actual Phase Shift</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg17">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg_range0</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg_range0">0.0,2.8,3.2,3.8,4.5,5.6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg_range1</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg_range1">0.0,5.6,6.4,7.5,9.0,11.2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg_range2</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg_range2">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg_range3</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg_range3">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg_range4</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg_range4">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg_range5</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg_range5">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg_range6</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg_range6">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg_range7</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg_range7">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg_range8</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg_range8">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg_range9</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg_range9">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg_range10</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg_range10">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg_range11</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg_range11">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg_range12</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg_range12">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg_range13</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg_range13">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg_range14</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg_range14">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg_range15</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg_range15">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg_range16</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg_range16">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_phase_shift_deg_range17</spirit:name>
+ <spirit:displayName>Legal Phase Shifts</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_phase_shift_deg_range17">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_duty_cycle0</spirit:name>
+ <spirit:displayName>Desired Duty Cycle</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_duty_cycle0">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_duty_cycle1</spirit:name>
+ <spirit:displayName>Desired Duty Cycle</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_duty_cycle1">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_duty_cycle2</spirit:name>
+ <spirit:displayName>Desired Duty Cycle</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_duty_cycle2">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_duty_cycle3</spirit:name>
+ <spirit:displayName>Desired Duty Cycle</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_duty_cycle3">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_duty_cycle4</spirit:name>
+ <spirit:displayName>Desired Duty Cycle</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_duty_cycle4">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_duty_cycle5</spirit:name>
+ <spirit:displayName>Desired Duty Cycle</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_duty_cycle5">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_duty_cycle6</spirit:name>
+ <spirit:displayName>Desired Duty Cycle</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_duty_cycle6">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_duty_cycle7</spirit:name>
+ <spirit:displayName>Desired Duty Cycle</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_duty_cycle7">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_duty_cycle8</spirit:name>
+ <spirit:displayName>Desired Duty Cycle</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_duty_cycle8">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_duty_cycle9</spirit:name>
+ <spirit:displayName>Desired Duty Cycle</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_duty_cycle9">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_duty_cycle10</spirit:name>
+ <spirit:displayName>Desired Duty Cycle</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_duty_cycle10">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_duty_cycle11</spirit:name>
+ <spirit:displayName>Desired Duty Cycle</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_duty_cycle11">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_duty_cycle12</spirit:name>
+ <spirit:displayName>Desired Duty Cycle</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_duty_cycle12">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_duty_cycle13</spirit:name>
+ <spirit:displayName>Desired Duty Cycle</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_duty_cycle13">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_duty_cycle14</spirit:name>
+ <spirit:displayName>Desired Duty Cycle</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_duty_cycle14">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_duty_cycle15</spirit:name>
+ <spirit:displayName>Desired Duty Cycle</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_duty_cycle15">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_duty_cycle16</spirit:name>
+ <spirit:displayName>Desired Duty Cycle</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_duty_cycle16">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_duty_cycle17</spirit:name>
+ <spirit:displayName>Desired Duty Cycle</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="gui_duty_cycle17">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle0</spirit:name>
+ <spirit:displayName>Actual duty cycle</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle0">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle1</spirit:name>
+ <spirit:displayName>Actual duty cycle</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle1">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle2</spirit:name>
+ <spirit:displayName>Actual duty cycle</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle2">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle3</spirit:name>
+ <spirit:displayName>Actual duty cycle</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle3">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle4</spirit:name>
+ <spirit:displayName>Actual duty cycle</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle4">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle5</spirit:name>
+ <spirit:displayName>Actual duty cycle</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle5">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle6</spirit:name>
+ <spirit:displayName>Actual duty cycle</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle6">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle7</spirit:name>
+ <spirit:displayName>Actual duty cycle</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle7">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle8</spirit:name>
+ <spirit:displayName>Actual duty cycle</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle8">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle9</spirit:name>
+ <spirit:displayName>Actual duty cycle</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle9">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle10</spirit:name>
+ <spirit:displayName>Actual duty cycle</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle10">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle11</spirit:name>
+ <spirit:displayName>Actual duty cycle</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle11">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle12</spirit:name>
+ <spirit:displayName>Actual duty cycle</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle12">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle13</spirit:name>
+ <spirit:displayName>Actual duty cycle</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle13">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle14</spirit:name>
+ <spirit:displayName>Actual duty cycle</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle14">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle15</spirit:name>
+ <spirit:displayName>Actual duty cycle</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle15">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle16</spirit:name>
+ <spirit:displayName>Actual duty cycle</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle16">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle17</spirit:name>
+ <spirit:displayName>Actual duty cycle</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle17">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle_range0</spirit:name>
+ <spirit:displayName>Legal Duty Cycles</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle_range0">45.83,46.43,46.88,50.0,53.12,53.57</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle_range1</spirit:name>
+ <spirit:displayName>Legal Duty Cycles</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle_range1">41.67,42.86,43.75,50.0,56.25,57.14</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle_range2</spirit:name>
+ <spirit:displayName>Legal Duty Cycles</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle_range2">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle_range3</spirit:name>
+ <spirit:displayName>Legal Duty Cycles</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle_range3">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle_range4</spirit:name>
+ <spirit:displayName>Legal Duty Cycles</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle_range4">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle_range5</spirit:name>
+ <spirit:displayName>Legal Duty Cycles</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle_range5">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle_range6</spirit:name>
+ <spirit:displayName>Legal Duty Cycles</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle_range6">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle_range7</spirit:name>
+ <spirit:displayName>Legal Duty Cycles</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle_range7">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle_range8</spirit:name>
+ <spirit:displayName>Legal Duty Cycles</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle_range8">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle_range9</spirit:name>
+ <spirit:displayName>Legal Duty Cycles</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle_range9">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle_range10</spirit:name>
+ <spirit:displayName>Legal Duty Cycles</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle_range10">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle_range11</spirit:name>
+ <spirit:displayName>Legal Duty Cycles</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle_range11">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle_range12</spirit:name>
+ <spirit:displayName>Legal Duty Cycles</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle_range12">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle_range13</spirit:name>
+ <spirit:displayName>Legal Duty Cycles</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle_range13">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle_range14</spirit:name>
+ <spirit:displayName>Legal Duty Cycles</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle_range14">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle_range15</spirit:name>
+ <spirit:displayName>Legal Duty Cycles</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle_range15">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle_range16</spirit:name>
+ <spirit:displayName>Legal Duty Cycles</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle_range16">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_actual_duty_cycle_range17</spirit:name>
+ <spirit:displayName>Legal Duty Cycles</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="gui_actual_duty_cycle_range17">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>parameterTable_names</spirit:name>
+ <spirit:displayName>Parameter Names</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="parameterTable_names">M-Counter Divide Setting,N-Counter Divide Setting,VCO Frequency,C-Counter-0 Divide Setting,C-Counter-1 Divide Setting,C-Counter-2 Divide Setting,C-Counter-3 Divide Setting,C-Counter-4 Divide Setting,C-Counter-5 Divide Setting,C-Counter-6 Divide Setting,C-Counter-7 Divide Setting,C-Counter-8 Divide Setting,PLL Auto Reset,M-Counter Hi Divide,M-Counter Lo Divide,M-Counter Even Duty Enable,M-Counter Bypass Enable,N-Counter Hi Divide,N-Counter Lo Divide,N-Counter Even Duty Enable,N-Counter Bypass Enable,C-Counter-0 Hi Divide,C-Counter-1 Hi Divide,C-Counter-2 Hi Divide,C-Counter-3 Hi Divide,C-Counter-4 Hi Divide,C-Counter-5 Hi Divide,C-Counter-6 Hi Divide,C-Counter-7 Hi Divide,C-Counter-8 Hi Divide,C-Counter-0 Lo Divide,C-Counter-1 Lo Divide,C-Counter-2 Lo Divide,C-Counter-3 Lo Divide,C-Counter-4 Lo Divide,C-Counter-5 Lo Divide,C-Counter-6 Lo Divide,C-Counter-7 Lo Divide,C-Counter-8 Lo Divide,C-Counter-0 Even Duty Enable,C-Counter-1 Even Duty Enable,C-Counter-2 Even Duty Enable,C-Counter-3 Even Duty Enable,C-Counter-4 Even Duty Enable,C-Counter-5 Even Duty Enable,C-Counter-6 Even Duty Enable,C-Counter-7 Even Duty Enable,C-Counter-8 Even Duty Enable,C-Counter-0 Bypass Enable,C-Counter-1 Bypass Enable,C-Counter-2 Bypass Enable,C-Counter-3 Bypass Enable,C-Counter-4 Bypass Enable,C-Counter-5 Bypass Enable,C-Counter-6 Bypass Enable,C-Counter-7 Bypass Enable,C-Counter-8 Bypass Enable,C-Counter-0 Preset,C-Counter-1 Preset,C-Counter-2 Preset,C-Counter-3 Preset,C-Counter-4 Preset,C-Counter-5 Preset,C-Counter-6 Preset,C-Counter-7 Preset,C-Counter-8 Preset,C-Counter-0 Phase Mux Preset,C-Counter-1 Phase Mux Preset,C-Counter-2 Phase Mux Preset,C-Counter-3 Phase Mux Preset,C-Counter-4 Phase Mux Preset,C-Counter-5 Phase Mux Preset,C-Counter-6 Phase Mux Preset,C-Counter-7 Phase Mux Preset,C-Counter-8 Phase Mux Preset,Charge Pump Current,Bandwidth Control</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>parameterTable_values</spirit:name>
+ <spirit:displayName>Parameter Values</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="parameterTable_values">4,1,800.0 MHz,8,4,1,1,1,1,1,1,1,false,2,2,false,false,256,256,false,true,4,2,256,256,256,256,256,256,256,4,2,256,256,256,256,256,256,256,false,false,false,false,false,false,false,false,false,false,false,true,true,true,true,true,true,true,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,pll_cp_setting10,pll_bw_res_setting2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>mifTable_names</spirit:name>
+ <spirit:displayName>MIF File Property</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="mifTable_names">The MIF file specified does not yet exist</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>mifTable_values</spirit:name>
+ <spirit:displayName>Values</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="mifTable_values"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_m_cnt_basic</spirit:name>
+ <spirit:displayName>pll_m_cnt_basic</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="pll_m_cnt_basic">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_m_cnt</spirit:name>
+ <spirit:displayName>pll_m_cnt</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="pll_m_cnt">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prot_mode</spirit:name>
+ <spirit:displayName>prot_mode</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="prot_mode">BASIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>m_cnt_hi_div</spirit:name>
+ <spirit:displayName>m_cnt_hi_div</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="m_cnt_hi_div">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>eff_m_cnt</spirit:name>
+ <spirit:displayName>eff_m_cnt</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="eff_m_cnt">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>multiply_factor</spirit:name>
+ <spirit:displayName>multiply_factor</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="multiply_factor">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>use_core_refclk</spirit:name>
+ <spirit:displayName>use_core_refclk</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="use_core_refclk">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>m_cnt_lo_div</spirit:name>
+ <spirit:displayName>m_cnt_lo_div</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="m_cnt_lo_div">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>n_cnt_hi_div</spirit:name>
+ <spirit:displayName>n_cnt_hi_div</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="n_cnt_hi_div">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>n_cnt_lo_div</spirit:name>
+ <spirit:displayName>n_cnt_lo_div</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="n_cnt_lo_div">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>m_cnt_bypass_en</spirit:name>
+ <spirit:displayName>m_cnt_bypass_en</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="m_cnt_bypass_en">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>n_cnt_bypass_en</spirit:name>
+ <spirit:displayName>n_cnt_bypass_en</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="n_cnt_bypass_en">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>m_cnt_odd_div_duty_en</spirit:name>
+ <spirit:displayName>m_cnt_odd_div_duty_en</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="m_cnt_odd_div_duty_en">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>n_cnt_odd_div_duty_en</spirit:name>
+ <spirit:displayName>n_cnt_odd_div_duty_en</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="n_cnt_odd_div_duty_en">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_vco_div</spirit:name>
+ <spirit:displayName>pll_vco_div</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="pll_vco_div">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_cp_current</spirit:name>
+ <spirit:displayName>pll_cp_current</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="pll_cp_current">pll_cp_setting10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_bwctrl</spirit:name>
+ <spirit:displayName>pll_bwctrl</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="pll_bwctrl">pll_bw_res_setting2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_ripplecap_ctrl</spirit:name>
+ <spirit:displayName>pll_ripplecap_ctrl</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="pll_ripplecap_ctrl"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_fractional_division</spirit:name>
+ <spirit:displayName>pll_fractional_division</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="pll_fractional_division">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>fractional_vco_multiplier</spirit:name>
+ <spirit:displayName>fractional_vco_multiplier</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="fractional_vco_multiplier">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>reference_clock_frequency</spirit:name>
+ <spirit:displayName>reference_clock_frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="reference_clock_frequency">200.0 MHz</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_fractional_cout</spirit:name>
+ <spirit:displayName>pll_fractional_cout</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="pll_fractional_cout">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_dsm_out_sel</spirit:name>
+ <spirit:displayName>pll_dsm_out_sel</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="pll_dsm_out_sel">1st_order</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>operation_mode</spirit:name>
+ <spirit:displayName>operation_mode</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="operation_mode">source_synchronous</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>number_of_clocks</spirit:name>
+ <spirit:displayName>number_of_clocks</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="number_of_clocks">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>number_of_outclks</spirit:name>
+ <spirit:displayName>number_of_outclks</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="number_of_outclks">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_vcoph_div</spirit:name>
+ <spirit:displayName>pll_vcoph_div</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="pll_vcoph_div">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_type</spirit:name>
+ <spirit:displayName>pll_type</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="pll_type">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_subtype</spirit:name>
+ <spirit:displayName>pll_subtype</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="pll_subtype">General</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_output_clk_frequency</spirit:name>
+ <spirit:displayName>pll_output_clk_frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="pll_output_clk_frequency">800.0 MHz</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>mimic_fbclk_type</spirit:name>
+ <spirit:displayName>mimic_fbclk_type</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="mimic_fbclk_type">gclk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_bw_sel</spirit:name>
+ <spirit:displayName>pll_bw_sel</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="pll_bw_sel">Low</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_slf_rst</spirit:name>
+ <spirit:displayName>pll_slf_rst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="pll_slf_rst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_fbclk_mux_1</spirit:name>
+ <spirit:displayName>pll_fbclk_mux_1</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="pll_fbclk_mux_1">pll_fbclk_mux_1_glb</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_fbclk_mux_2</spirit:name>
+ <spirit:displayName>pll_fbclk_mux_2</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="pll_fbclk_mux_2">pll_fbclk_mux_2_fb_1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_m_cnt_in_src</spirit:name>
+ <spirit:displayName>pll_m_cnt_in_src</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="pll_m_cnt_in_src">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_clkin_0_src</spirit:name>
+ <spirit:displayName>pll_clkin_0_src</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="pll_clkin_0_src">clk_0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>refclk1_frequency</spirit:name>
+ <spirit:displayName>refclk1_frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="refclk1_frequency">100.0 MHz</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_clk_loss_sw_en</spirit:name>
+ <spirit:displayName>pll_clk_loss_sw_en</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="pll_clk_loss_sw_en">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_manu_clk_sw_en</spirit:name>
+ <spirit:displayName>pll_manu_clk_sw_en</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="pll_manu_clk_sw_en">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_auto_clk_sw_en</spirit:name>
+ <spirit:displayName>pll_auto_clk_sw_en</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="pll_auto_clk_sw_en">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_clkin_1_src</spirit:name>
+ <spirit:displayName>pll_clkin_1_src</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="pll_clkin_1_src">clk_0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_clk_sw_dly</spirit:name>
+ <spirit:displayName>pll_clk_sw_dly</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="pll_clk_sw_dly">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_extclk_0_cnt_src</spirit:name>
+ <spirit:displayName>pll_extclk_0_cnt_src</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="pll_extclk_0_cnt_src">pll_extclk_cnt_src_vss</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_extclk_1_cnt_src</spirit:name>
+ <spirit:displayName>pll_extclk_1_cnt_src</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="pll_extclk_1_cnt_src">pll_extclk_cnt_src_vss</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_lock_fltr_cfg</spirit:name>
+ <spirit:displayName>pll_lock_fltr_cfg</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="pll_lock_fltr_cfg">100</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_unlock_fltr_cfg</spirit:name>
+ <spirit:displayName>pll_unlock_fltr_cfg</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="pll_unlock_fltr_cfg">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lock_mode</spirit:name>
+ <spirit:displayName>lock_mode</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lock_mode">low_lock_time</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clock_to_compensate</spirit:name>
+ <spirit:displayName>clock_to_compensate</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="clock_to_compensate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clock_name_global</spirit:name>
+ <spirit:displayName>clock_name_global</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="clock_name_global">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_freqcal_en</spirit:name>
+ <spirit:displayName>pll_freqcal_en</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="pll_freqcal_en">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_defer_cal_user_mode</spirit:name>
+ <spirit:displayName>pll_defer_cal_user_mode</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="pll_defer_cal_user_mode">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>dprio_interface_sel</spirit:name>
+ <spirit:displayName>dprio_interface_sel</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="dprio_interface_sel">3</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_hi_div0</spirit:name>
+ <spirit:displayName>c_cnt_hi_div0</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_hi_div0">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_hi_div1</spirit:name>
+ <spirit:displayName>c_cnt_hi_div1</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_hi_div1">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_hi_div2</spirit:name>
+ <spirit:displayName>c_cnt_hi_div2</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_hi_div2">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_hi_div3</spirit:name>
+ <spirit:displayName>c_cnt_hi_div3</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_hi_div3">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_hi_div4</spirit:name>
+ <spirit:displayName>c_cnt_hi_div4</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_hi_div4">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_hi_div5</spirit:name>
+ <spirit:displayName>c_cnt_hi_div5</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_hi_div5">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_hi_div6</spirit:name>
+ <spirit:displayName>c_cnt_hi_div6</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_hi_div6">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_hi_div7</spirit:name>
+ <spirit:displayName>c_cnt_hi_div7</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_hi_div7">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_hi_div8</spirit:name>
+ <spirit:displayName>c_cnt_hi_div8</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_hi_div8">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_hi_div9</spirit:name>
+ <spirit:displayName>c_cnt_hi_div9</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_hi_div9">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_hi_div10</spirit:name>
+ <spirit:displayName>c_cnt_hi_div10</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_hi_div10">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_hi_div11</spirit:name>
+ <spirit:displayName>c_cnt_hi_div11</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_hi_div11">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_hi_div12</spirit:name>
+ <spirit:displayName>c_cnt_hi_div12</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_hi_div12">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_hi_div13</spirit:name>
+ <spirit:displayName>c_cnt_hi_div13</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_hi_div13">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_hi_div14</spirit:name>
+ <spirit:displayName>c_cnt_hi_div14</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_hi_div14">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_hi_div15</spirit:name>
+ <spirit:displayName>c_cnt_hi_div15</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_hi_div15">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_hi_div16</spirit:name>
+ <spirit:displayName>c_cnt_hi_div16</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_hi_div16">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_hi_div17</spirit:name>
+ <spirit:displayName>c_cnt_hi_div17</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_hi_div17">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_lo_div0</spirit:name>
+ <spirit:displayName>c_cnt_lo_div0</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_lo_div0">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_lo_div1</spirit:name>
+ <spirit:displayName>c_cnt_lo_div1</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_lo_div1">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_lo_div2</spirit:name>
+ <spirit:displayName>c_cnt_lo_div2</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_lo_div2">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_lo_div3</spirit:name>
+ <spirit:displayName>c_cnt_lo_div3</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_lo_div3">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_lo_div4</spirit:name>
+ <spirit:displayName>c_cnt_lo_div4</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_lo_div4">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_lo_div5</spirit:name>
+ <spirit:displayName>c_cnt_lo_div5</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_lo_div5">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_lo_div6</spirit:name>
+ <spirit:displayName>c_cnt_lo_div6</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_lo_div6">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_lo_div7</spirit:name>
+ <spirit:displayName>c_cnt_lo_div7</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_lo_div7">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_lo_div8</spirit:name>
+ <spirit:displayName>c_cnt_lo_div8</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_lo_div8">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_lo_div9</spirit:name>
+ <spirit:displayName>c_cnt_lo_div9</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_lo_div9">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_lo_div10</spirit:name>
+ <spirit:displayName>c_cnt_lo_div10</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_lo_div10">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_lo_div11</spirit:name>
+ <spirit:displayName>c_cnt_lo_div11</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_lo_div11">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_lo_div12</spirit:name>
+ <spirit:displayName>c_cnt_lo_div12</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_lo_div12">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_lo_div13</spirit:name>
+ <spirit:displayName>c_cnt_lo_div13</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_lo_div13">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_lo_div14</spirit:name>
+ <spirit:displayName>c_cnt_lo_div14</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_lo_div14">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_lo_div15</spirit:name>
+ <spirit:displayName>c_cnt_lo_div15</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_lo_div15">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_lo_div16</spirit:name>
+ <spirit:displayName>c_cnt_lo_div16</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_lo_div16">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_lo_div17</spirit:name>
+ <spirit:displayName>c_cnt_lo_div17</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_lo_div17">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_prst0</spirit:name>
+ <spirit:displayName>c_cnt_prst0</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_prst0">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_prst1</spirit:name>
+ <spirit:displayName>c_cnt_prst1</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_prst1">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_prst2</spirit:name>
+ <spirit:displayName>c_cnt_prst2</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_prst2">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_prst3</spirit:name>
+ <spirit:displayName>c_cnt_prst3</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_prst3">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_prst4</spirit:name>
+ <spirit:displayName>c_cnt_prst4</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_prst4">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_prst5</spirit:name>
+ <spirit:displayName>c_cnt_prst5</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_prst5">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_prst6</spirit:name>
+ <spirit:displayName>c_cnt_prst6</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_prst6">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_prst7</spirit:name>
+ <spirit:displayName>c_cnt_prst7</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_prst7">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_prst8</spirit:name>
+ <spirit:displayName>c_cnt_prst8</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_prst8">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_prst9</spirit:name>
+ <spirit:displayName>c_cnt_prst9</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_prst9">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_prst10</spirit:name>
+ <spirit:displayName>c_cnt_prst10</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_prst10">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_prst11</spirit:name>
+ <spirit:displayName>c_cnt_prst11</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_prst11">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_prst12</spirit:name>
+ <spirit:displayName>c_cnt_prst12</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_prst12">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_prst13</spirit:name>
+ <spirit:displayName>c_cnt_prst13</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_prst13">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_prst14</spirit:name>
+ <spirit:displayName>c_cnt_prst14</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_prst14">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_prst15</spirit:name>
+ <spirit:displayName>c_cnt_prst15</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_prst15">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_prst16</spirit:name>
+ <spirit:displayName>c_cnt_prst16</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_prst16">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_prst17</spirit:name>
+ <spirit:displayName>c_cnt_prst17</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_prst17">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_ph_mux_prst0</spirit:name>
+ <spirit:displayName>c_cnt_ph_mux_prst0</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_ph_mux_prst0">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_ph_mux_prst1</spirit:name>
+ <spirit:displayName>c_cnt_ph_mux_prst1</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_ph_mux_prst1">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_ph_mux_prst2</spirit:name>
+ <spirit:displayName>c_cnt_ph_mux_prst2</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_ph_mux_prst2">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_ph_mux_prst3</spirit:name>
+ <spirit:displayName>c_cnt_ph_mux_prst3</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_ph_mux_prst3">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_ph_mux_prst4</spirit:name>
+ <spirit:displayName>c_cnt_ph_mux_prst4</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_ph_mux_prst4">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_ph_mux_prst5</spirit:name>
+ <spirit:displayName>c_cnt_ph_mux_prst5</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_ph_mux_prst5">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_ph_mux_prst6</spirit:name>
+ <spirit:displayName>c_cnt_ph_mux_prst6</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_ph_mux_prst6">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_ph_mux_prst7</spirit:name>
+ <spirit:displayName>c_cnt_ph_mux_prst7</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_ph_mux_prst7">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_ph_mux_prst8</spirit:name>
+ <spirit:displayName>c_cnt_ph_mux_prst8</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_ph_mux_prst8">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_ph_mux_prst9</spirit:name>
+ <spirit:displayName>c_cnt_ph_mux_prst9</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_ph_mux_prst9">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_ph_mux_prst10</spirit:name>
+ <spirit:displayName>c_cnt_ph_mux_prst10</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_ph_mux_prst10">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_ph_mux_prst11</spirit:name>
+ <spirit:displayName>c_cnt_ph_mux_prst11</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_ph_mux_prst11">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_ph_mux_prst12</spirit:name>
+ <spirit:displayName>c_cnt_ph_mux_prst12</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_ph_mux_prst12">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_ph_mux_prst13</spirit:name>
+ <spirit:displayName>c_cnt_ph_mux_prst13</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_ph_mux_prst13">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_ph_mux_prst14</spirit:name>
+ <spirit:displayName>c_cnt_ph_mux_prst14</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_ph_mux_prst14">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_ph_mux_prst15</spirit:name>
+ <spirit:displayName>c_cnt_ph_mux_prst15</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_ph_mux_prst15">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_ph_mux_prst16</spirit:name>
+ <spirit:displayName>c_cnt_ph_mux_prst16</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_ph_mux_prst16">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_ph_mux_prst17</spirit:name>
+ <spirit:displayName>c_cnt_ph_mux_prst17</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="c_cnt_ph_mux_prst17">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_in_src0</spirit:name>
+ <spirit:displayName>c_cnt_in_src0</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="c_cnt_in_src0">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_in_src1</spirit:name>
+ <spirit:displayName>c_cnt_in_src1</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="c_cnt_in_src1">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_in_src2</spirit:name>
+ <spirit:displayName>c_cnt_in_src2</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="c_cnt_in_src2">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_in_src3</spirit:name>
+ <spirit:displayName>c_cnt_in_src3</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="c_cnt_in_src3">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_in_src4</spirit:name>
+ <spirit:displayName>c_cnt_in_src4</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="c_cnt_in_src4">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_in_src5</spirit:name>
+ <spirit:displayName>c_cnt_in_src5</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="c_cnt_in_src5">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_in_src6</spirit:name>
+ <spirit:displayName>c_cnt_in_src6</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="c_cnt_in_src6">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_in_src7</spirit:name>
+ <spirit:displayName>c_cnt_in_src7</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="c_cnt_in_src7">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_in_src8</spirit:name>
+ <spirit:displayName>c_cnt_in_src8</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="c_cnt_in_src8">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_in_src9</spirit:name>
+ <spirit:displayName>c_cnt_in_src9</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="c_cnt_in_src9">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_in_src10</spirit:name>
+ <spirit:displayName>c_cnt_in_src10</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="c_cnt_in_src10">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_in_src11</spirit:name>
+ <spirit:displayName>c_cnt_in_src11</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="c_cnt_in_src11">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_in_src12</spirit:name>
+ <spirit:displayName>c_cnt_in_src12</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="c_cnt_in_src12">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_in_src13</spirit:name>
+ <spirit:displayName>c_cnt_in_src13</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="c_cnt_in_src13">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_in_src14</spirit:name>
+ <spirit:displayName>c_cnt_in_src14</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="c_cnt_in_src14">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_in_src15</spirit:name>
+ <spirit:displayName>c_cnt_in_src15</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="c_cnt_in_src15">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_in_src16</spirit:name>
+ <spirit:displayName>c_cnt_in_src16</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="c_cnt_in_src16">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_in_src17</spirit:name>
+ <spirit:displayName>c_cnt_in_src17</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="c_cnt_in_src17">c_m_cnt_in_src_ph_mux_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_bypass_en0</spirit:name>
+ <spirit:displayName>c_cnt_bypass_en0</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_bypass_en0">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_bypass_en1</spirit:name>
+ <spirit:displayName>c_cnt_bypass_en1</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_bypass_en1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_bypass_en2</spirit:name>
+ <spirit:displayName>c_cnt_bypass_en2</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_bypass_en2">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_bypass_en3</spirit:name>
+ <spirit:displayName>c_cnt_bypass_en3</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_bypass_en3">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_bypass_en4</spirit:name>
+ <spirit:displayName>c_cnt_bypass_en4</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_bypass_en4">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_bypass_en5</spirit:name>
+ <spirit:displayName>c_cnt_bypass_en5</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_bypass_en5">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_bypass_en6</spirit:name>
+ <spirit:displayName>c_cnt_bypass_en6</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_bypass_en6">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_bypass_en7</spirit:name>
+ <spirit:displayName>c_cnt_bypass_en7</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_bypass_en7">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_bypass_en8</spirit:name>
+ <spirit:displayName>c_cnt_bypass_en8</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_bypass_en8">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_bypass_en9</spirit:name>
+ <spirit:displayName>c_cnt_bypass_en9</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_bypass_en9">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_bypass_en10</spirit:name>
+ <spirit:displayName>c_cnt_bypass_en10</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_bypass_en10">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_bypass_en11</spirit:name>
+ <spirit:displayName>c_cnt_bypass_en11</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_bypass_en11">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_bypass_en12</spirit:name>
+ <spirit:displayName>c_cnt_bypass_en12</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_bypass_en12">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_bypass_en13</spirit:name>
+ <spirit:displayName>c_cnt_bypass_en13</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_bypass_en13">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_bypass_en14</spirit:name>
+ <spirit:displayName>c_cnt_bypass_en14</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_bypass_en14">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_bypass_en15</spirit:name>
+ <spirit:displayName>c_cnt_bypass_en15</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_bypass_en15">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_bypass_en16</spirit:name>
+ <spirit:displayName>c_cnt_bypass_en16</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_bypass_en16">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_bypass_en17</spirit:name>
+ <spirit:displayName>c_cnt_bypass_en17</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_bypass_en17">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_odd_div_duty_en0</spirit:name>
+ <spirit:displayName>c_cnt_odd_div_duty_en0</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_odd_div_duty_en0">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_odd_div_duty_en1</spirit:name>
+ <spirit:displayName>c_cnt_odd_div_duty_en1</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_odd_div_duty_en1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_odd_div_duty_en2</spirit:name>
+ <spirit:displayName>c_cnt_odd_div_duty_en2</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_odd_div_duty_en2">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_odd_div_duty_en3</spirit:name>
+ <spirit:displayName>c_cnt_odd_div_duty_en3</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_odd_div_duty_en3">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_odd_div_duty_en4</spirit:name>
+ <spirit:displayName>c_cnt_odd_div_duty_en4</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_odd_div_duty_en4">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_odd_div_duty_en5</spirit:name>
+ <spirit:displayName>c_cnt_odd_div_duty_en5</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_odd_div_duty_en5">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_odd_div_duty_en6</spirit:name>
+ <spirit:displayName>c_cnt_odd_div_duty_en6</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_odd_div_duty_en6">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_odd_div_duty_en7</spirit:name>
+ <spirit:displayName>c_cnt_odd_div_duty_en7</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_odd_div_duty_en7">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_odd_div_duty_en8</spirit:name>
+ <spirit:displayName>c_cnt_odd_div_duty_en8</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_odd_div_duty_en8">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_odd_div_duty_en9</spirit:name>
+ <spirit:displayName>c_cnt_odd_div_duty_en9</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_odd_div_duty_en9">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_odd_div_duty_en10</spirit:name>
+ <spirit:displayName>c_cnt_odd_div_duty_en10</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_odd_div_duty_en10">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_odd_div_duty_en11</spirit:name>
+ <spirit:displayName>c_cnt_odd_div_duty_en11</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_odd_div_duty_en11">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_odd_div_duty_en12</spirit:name>
+ <spirit:displayName>c_cnt_odd_div_duty_en12</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_odd_div_duty_en12">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_odd_div_duty_en13</spirit:name>
+ <spirit:displayName>c_cnt_odd_div_duty_en13</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_odd_div_duty_en13">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_odd_div_duty_en14</spirit:name>
+ <spirit:displayName>c_cnt_odd_div_duty_en14</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_odd_div_duty_en14">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_odd_div_duty_en15</spirit:name>
+ <spirit:displayName>c_cnt_odd_div_duty_en15</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_odd_div_duty_en15">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_odd_div_duty_en16</spirit:name>
+ <spirit:displayName>c_cnt_odd_div_duty_en16</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_odd_div_duty_en16">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>c_cnt_odd_div_duty_en17</spirit:name>
+ <spirit:displayName>c_cnt_odd_div_duty_en17</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="c_cnt_odd_div_duty_en17">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>output_clock_frequency0</spirit:name>
+ <spirit:displayName>output_clock_frequency0</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="output_clock_frequency0">100.000000 MHz</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>output_clock_frequency1</spirit:name>
+ <spirit:displayName>output_clock_frequency1</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="output_clock_frequency1">200.000000 MHz</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>output_clock_frequency2</spirit:name>
+ <spirit:displayName>output_clock_frequency2</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="output_clock_frequency2">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>output_clock_frequency3</spirit:name>
+ <spirit:displayName>output_clock_frequency3</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="output_clock_frequency3">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>output_clock_frequency4</spirit:name>
+ <spirit:displayName>output_clock_frequency4</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="output_clock_frequency4">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>output_clock_frequency5</spirit:name>
+ <spirit:displayName>output_clock_frequency5</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="output_clock_frequency5">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>output_clock_frequency6</spirit:name>
+ <spirit:displayName>output_clock_frequency6</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="output_clock_frequency6">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>output_clock_frequency7</spirit:name>
+ <spirit:displayName>output_clock_frequency7</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="output_clock_frequency7">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>output_clock_frequency8</spirit:name>
+ <spirit:displayName>output_clock_frequency8</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="output_clock_frequency8">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>output_clock_frequency9</spirit:name>
+ <spirit:displayName>output_clock_frequency9</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="output_clock_frequency9">0 MHz</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>output_clock_frequency10</spirit:name>
+ <spirit:displayName>output_clock_frequency10</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="output_clock_frequency10">0 MHz</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>output_clock_frequency11</spirit:name>
+ <spirit:displayName>output_clock_frequency11</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="output_clock_frequency11">0 MHz</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>output_clock_frequency12</spirit:name>
+ <spirit:displayName>output_clock_frequency12</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="output_clock_frequency12">0 MHz</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>output_clock_frequency13</spirit:name>
+ <spirit:displayName>output_clock_frequency13</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="output_clock_frequency13">0 MHz</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>output_clock_frequency14</spirit:name>
+ <spirit:displayName>output_clock_frequency14</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="output_clock_frequency14">0 MHz</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>output_clock_frequency15</spirit:name>
+ <spirit:displayName>output_clock_frequency15</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="output_clock_frequency15">0 MHz</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>output_clock_frequency16</spirit:name>
+ <spirit:displayName>output_clock_frequency16</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="output_clock_frequency16">0 MHz</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>output_clock_frequency17</spirit:name>
+ <spirit:displayName>output_clock_frequency17</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="output_clock_frequency17">0 MHz</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>phase_shift0</spirit:name>
+ <spirit:displayName>phase_shift0</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="phase_shift0">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>phase_shift1</spirit:name>
+ <spirit:displayName>phase_shift1</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="phase_shift1">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>phase_shift2</spirit:name>
+ <spirit:displayName>phase_shift2</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="phase_shift2">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>phase_shift3</spirit:name>
+ <spirit:displayName>phase_shift3</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="phase_shift3">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>phase_shift4</spirit:name>
+ <spirit:displayName>phase_shift4</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="phase_shift4">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>phase_shift5</spirit:name>
+ <spirit:displayName>phase_shift5</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="phase_shift5">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>phase_shift6</spirit:name>
+ <spirit:displayName>phase_shift6</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="phase_shift6">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>phase_shift7</spirit:name>
+ <spirit:displayName>phase_shift7</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="phase_shift7">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>phase_shift8</spirit:name>
+ <spirit:displayName>phase_shift8</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="phase_shift8">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>phase_shift9</spirit:name>
+ <spirit:displayName>phase_shift9</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="phase_shift9">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>phase_shift10</spirit:name>
+ <spirit:displayName>phase_shift10</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="phase_shift10">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>phase_shift11</spirit:name>
+ <spirit:displayName>phase_shift11</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="phase_shift11">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>phase_shift12</spirit:name>
+ <spirit:displayName>phase_shift12</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="phase_shift12">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>phase_shift13</spirit:name>
+ <spirit:displayName>phase_shift13</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="phase_shift13">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>phase_shift14</spirit:name>
+ <spirit:displayName>phase_shift14</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="phase_shift14">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>phase_shift15</spirit:name>
+ <spirit:displayName>phase_shift15</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="phase_shift15">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>phase_shift16</spirit:name>
+ <spirit:displayName>phase_shift16</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="phase_shift16">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>phase_shift17</spirit:name>
+ <spirit:displayName>phase_shift17</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="phase_shift17">0 ps</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>duty_cycle0</spirit:name>
+ <spirit:displayName>duty_cycle0</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="duty_cycle0">50</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>duty_cycle1</spirit:name>
+ <spirit:displayName>duty_cycle1</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="duty_cycle1">50</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>duty_cycle2</spirit:name>
+ <spirit:displayName>duty_cycle2</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="duty_cycle2">50</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>duty_cycle3</spirit:name>
+ <spirit:displayName>duty_cycle3</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="duty_cycle3">50</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>duty_cycle4</spirit:name>
+ <spirit:displayName>duty_cycle4</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="duty_cycle4">50</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>duty_cycle5</spirit:name>
+ <spirit:displayName>duty_cycle5</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="duty_cycle5">50</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>duty_cycle6</spirit:name>
+ <spirit:displayName>duty_cycle6</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="duty_cycle6">50</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>duty_cycle7</spirit:name>
+ <spirit:displayName>duty_cycle7</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="duty_cycle7">50</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>duty_cycle8</spirit:name>
+ <spirit:displayName>duty_cycle8</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="duty_cycle8">50</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>duty_cycle9</spirit:name>
+ <spirit:displayName>duty_cycle9</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="duty_cycle9">50</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>duty_cycle10</spirit:name>
+ <spirit:displayName>duty_cycle10</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="duty_cycle10">50</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>duty_cycle11</spirit:name>
+ <spirit:displayName>duty_cycle11</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="duty_cycle11">50</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>duty_cycle12</spirit:name>
+ <spirit:displayName>duty_cycle12</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="duty_cycle12">50</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>duty_cycle13</spirit:name>
+ <spirit:displayName>duty_cycle13</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="duty_cycle13">50</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>duty_cycle14</spirit:name>
+ <spirit:displayName>duty_cycle14</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="duty_cycle14">50</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>duty_cycle15</spirit:name>
+ <spirit:displayName>duty_cycle15</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="duty_cycle15">50</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>duty_cycle16</spirit:name>
+ <spirit:displayName>duty_cycle16</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="duty_cycle16">50</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>duty_cycle17</spirit:name>
+ <spirit:displayName>duty_cycle17</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="duty_cycle17">50</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clock_name_0</spirit:name>
+ <spirit:displayName>clock_name_0</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clock_name_0">link_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clock_name_1</spirit:name>
+ <spirit:displayName>clock_name_1</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clock_name_1">frame_clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clock_name_2</spirit:name>
+ <spirit:displayName>clock_name_2</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clock_name_2"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clock_name_3</spirit:name>
+ <spirit:displayName>clock_name_3</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clock_name_3"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clock_name_4</spirit:name>
+ <spirit:displayName>clock_name_4</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clock_name_4"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clock_name_5</spirit:name>
+ <spirit:displayName>clock_name_5</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clock_name_5"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clock_name_6</spirit:name>
+ <spirit:displayName>clock_name_6</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clock_name_6"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clock_name_7</spirit:name>
+ <spirit:displayName>clock_name_7</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clock_name_7"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clock_name_8</spirit:name>
+ <spirit:displayName>clock_name_8</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clock_name_8"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clock_name_global_0</spirit:name>
+ <spirit:displayName>clock_name_global_0</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="clock_name_global_0">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clock_name_global_1</spirit:name>
+ <spirit:displayName>clock_name_global_1</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="clock_name_global_1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clock_name_global_2</spirit:name>
+ <spirit:displayName>clock_name_global_2</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="clock_name_global_2">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clock_name_global_3</spirit:name>
+ <spirit:displayName>clock_name_global_3</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="clock_name_global_3">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clock_name_global_4</spirit:name>
+ <spirit:displayName>clock_name_global_4</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="clock_name_global_4">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clock_name_global_5</spirit:name>
+ <spirit:displayName>clock_name_global_5</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="clock_name_global_5">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clock_name_global_6</spirit:name>
+ <spirit:displayName>clock_name_global_6</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="clock_name_global_6">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clock_name_global_7</spirit:name>
+ <spirit:displayName>clock_name_global_7</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="clock_name_global_7">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clock_name_global_8</spirit:name>
+ <spirit:displayName>clock_name_global_8</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="clock_name_global_8">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>divide_factor0</spirit:name>
+ <spirit:displayName>divide_factor0</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="divide_factor0">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>divide_factor1</spirit:name>
+ <spirit:displayName>divide_factor1</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="divide_factor1">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>divide_factor2</spirit:name>
+ <spirit:displayName>divide_factor2</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="divide_factor2">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>divide_factor3</spirit:name>
+ <spirit:displayName>divide_factor3</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="divide_factor3">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>divide_factor4</spirit:name>
+ <spirit:displayName>divide_factor4</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="divide_factor4">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>divide_factor5</spirit:name>
+ <spirit:displayName>divide_factor5</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="divide_factor5">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>divide_factor6</spirit:name>
+ <spirit:displayName>divide_factor6</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="divide_factor6">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>divide_factor7</spirit:name>
+ <spirit:displayName>divide_factor7</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="divide_factor7">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>divide_factor8</spirit:name>
+ <spirit:displayName>divide_factor8</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="divide_factor8">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_tclk_mux_en</spirit:name>
+ <spirit:displayName>pll_tclk_mux_en</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="pll_tclk_mux_en">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_tclk_sel</spirit:name>
+ <spirit:displayName>pll_tclk_sel</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="pll_tclk_sel">pll_tclk_m_src</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_vco_freq_band_0</spirit:name>
+ <spirit:displayName>pll_vco_freq_band_0</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="pll_vco_freq_band_0">pll_freq_clk0_disabled</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_vco_freq_band_1</spirit:name>
+ <spirit:displayName>pll_vco_freq_band_1</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="pll_vco_freq_band_1">pll_freq_clk1_disabled</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_freqcal_req_flag</spirit:name>
+ <spirit:displayName>pll_freqcal_req_flag</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="pll_freqcal_req_flag">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>cal_converge</spirit:name>
+ <spirit:displayName>cal_converge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="cal_converge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>cal_error</spirit:name>
+ <spirit:displayName>cal_error</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="cal_error">cal_clean</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>pll_cal_done</spirit:name>
+ <spirit:displayName>pll_cal_done</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="pll_cal_done">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>include_iossm</spirit:name>
+ <spirit:displayName>include_iossm</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="include_iossm">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>cal_code_hex_file</spirit:name>
+ <spirit:displayName>cal_code_hex_file</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="cal_code_hex_file">iossm.hex</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>parameter_table_hex_file</spirit:name>
+ <spirit:displayName>parameter_table_hex_file</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="parameter_table_hex_file">seq_params_sim.hex</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>iossm_nios_sim_clk_period_ps</spirit:name>
+ <spirit:displayName>iossm_nios_sim_clk_period_ps</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="iossm_nios_sim_clk_period_ps">1333</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_number_of_family_allowable_clocks</spirit:name>
+ <spirit:displayName>hp_number_of_family_allowable_clocks</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="hp_number_of_family_allowable_clocks">9</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_previous_num_clocks</spirit:name>
+ <spirit:displayName>hp_previous_num_clocks</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="hp_previous_num_clocks">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_vco_frequency_fp</spirit:name>
+ <spirit:displayName>hp_actual_vco_frequency_fp</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_vco_frequency_fp">600.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_parameter_update_message</spirit:name>
+ <spirit:displayName>hp_parameter_update_message</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="hp_parameter_update_message">{altera_iopll::util::pll_send_message DEBUG {Starting parameter update messages: gui_output_clock_frequency0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_device_family }} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_device_component }} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_device_speed_grade }} {altera_iopll::util::pll_send_message DEBUG {-- in callback gui_output_clock_frequency_callback }} {altera_iopll::util::pll_send_message DEBUG { -- in update gui_output_clock_frequency0}} {altera_iopll::util::pll_send_message DEBUG { -- Updating all outclk values in order, starting with freq 0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency1}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift1}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle1}} {altera_iopll::util::pll_send_message DEBUG {-- done callback gui_output_clock_frequency_callback }} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_device_family }} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_device_component }} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_device_speed_grade }} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_dps_cntr}} {altera_iopll::util::pll_send_message DEBUG { -- in update_gui_extclkout_source}} {altera_iopll::util::pll_send_message DEBUG { -- in update_gui_cascade_outclk_index}} {altera_iopll::util::pll_send_message DEBUG { -- in update gui_clock_to_compensate}} {altera_iopll::util::pll_send_message DEBUG { -- in update_gui_pll_bandwidth_preset}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_vco_frequency}} {altera_iopll::util::pll_send_message DEBUG { -- Updating all outclk values in order, starting with freq 0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency1}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift1}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle0}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle1}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency2}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift2}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle2}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency3}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift3}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle3}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency4}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift4}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle4}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency5}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift5}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle5}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency6}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift6}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle6}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency7}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift7}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle7}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_output_clock_frequency8}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_phase_shift8}} {altera_iopll::util::pll_send_message DEBUG {-- in update gui_actual_duty_cycle8}}</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_qsys_scripting_mode</spirit:name>
+ <spirit:displayName>hp_qsys_scripting_mode</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hp_qsys_scripting_mode">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_output_clock_frequency_fp0</spirit:name>
+ <spirit:displayName>hp_actual_output_clock_frequency_fp0</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_output_clock_frequency_fp0">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_output_clock_frequency_fp1</spirit:name>
+ <spirit:displayName>hp_actual_output_clock_frequency_fp1</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_output_clock_frequency_fp1">200.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_output_clock_frequency_fp2</spirit:name>
+ <spirit:displayName>hp_actual_output_clock_frequency_fp2</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_output_clock_frequency_fp2">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_output_clock_frequency_fp3</spirit:name>
+ <spirit:displayName>hp_actual_output_clock_frequency_fp3</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_output_clock_frequency_fp3">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_output_clock_frequency_fp4</spirit:name>
+ <spirit:displayName>hp_actual_output_clock_frequency_fp4</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_output_clock_frequency_fp4">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_output_clock_frequency_fp5</spirit:name>
+ <spirit:displayName>hp_actual_output_clock_frequency_fp5</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_output_clock_frequency_fp5">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_output_clock_frequency_fp6</spirit:name>
+ <spirit:displayName>hp_actual_output_clock_frequency_fp6</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_output_clock_frequency_fp6">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_output_clock_frequency_fp7</spirit:name>
+ <spirit:displayName>hp_actual_output_clock_frequency_fp7</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_output_clock_frequency_fp7">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_output_clock_frequency_fp8</spirit:name>
+ <spirit:displayName>hp_actual_output_clock_frequency_fp8</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_output_clock_frequency_fp8">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_output_clock_frequency_fp9</spirit:name>
+ <spirit:displayName>hp_actual_output_clock_frequency_fp9</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_output_clock_frequency_fp9">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_output_clock_frequency_fp10</spirit:name>
+ <spirit:displayName>hp_actual_output_clock_frequency_fp10</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_output_clock_frequency_fp10">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_output_clock_frequency_fp11</spirit:name>
+ <spirit:displayName>hp_actual_output_clock_frequency_fp11</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_output_clock_frequency_fp11">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_output_clock_frequency_fp12</spirit:name>
+ <spirit:displayName>hp_actual_output_clock_frequency_fp12</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_output_clock_frequency_fp12">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_output_clock_frequency_fp13</spirit:name>
+ <spirit:displayName>hp_actual_output_clock_frequency_fp13</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_output_clock_frequency_fp13">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_output_clock_frequency_fp14</spirit:name>
+ <spirit:displayName>hp_actual_output_clock_frequency_fp14</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_output_clock_frequency_fp14">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_output_clock_frequency_fp15</spirit:name>
+ <spirit:displayName>hp_actual_output_clock_frequency_fp15</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_output_clock_frequency_fp15">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_output_clock_frequency_fp16</spirit:name>
+ <spirit:displayName>hp_actual_output_clock_frequency_fp16</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_output_clock_frequency_fp16">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_output_clock_frequency_fp17</spirit:name>
+ <spirit:displayName>hp_actual_output_clock_frequency_fp17</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_output_clock_frequency_fp17">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_phase_shift_fp0</spirit:name>
+ <spirit:displayName>hp_actual_phase_shift_fp0</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_phase_shift_fp0">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_phase_shift_fp1</spirit:name>
+ <spirit:displayName>hp_actual_phase_shift_fp1</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_phase_shift_fp1">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_phase_shift_fp2</spirit:name>
+ <spirit:displayName>hp_actual_phase_shift_fp2</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_phase_shift_fp2">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_phase_shift_fp3</spirit:name>
+ <spirit:displayName>hp_actual_phase_shift_fp3</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_phase_shift_fp3">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_phase_shift_fp4</spirit:name>
+ <spirit:displayName>hp_actual_phase_shift_fp4</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_phase_shift_fp4">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_phase_shift_fp5</spirit:name>
+ <spirit:displayName>hp_actual_phase_shift_fp5</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_phase_shift_fp5">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_phase_shift_fp6</spirit:name>
+ <spirit:displayName>hp_actual_phase_shift_fp6</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_phase_shift_fp6">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_phase_shift_fp7</spirit:name>
+ <spirit:displayName>hp_actual_phase_shift_fp7</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_phase_shift_fp7">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_phase_shift_fp8</spirit:name>
+ <spirit:displayName>hp_actual_phase_shift_fp8</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_phase_shift_fp8">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_phase_shift_fp9</spirit:name>
+ <spirit:displayName>hp_actual_phase_shift_fp9</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_phase_shift_fp9">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_phase_shift_fp10</spirit:name>
+ <spirit:displayName>hp_actual_phase_shift_fp10</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_phase_shift_fp10">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_phase_shift_fp11</spirit:name>
+ <spirit:displayName>hp_actual_phase_shift_fp11</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_phase_shift_fp11">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_phase_shift_fp12</spirit:name>
+ <spirit:displayName>hp_actual_phase_shift_fp12</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_phase_shift_fp12">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_phase_shift_fp13</spirit:name>
+ <spirit:displayName>hp_actual_phase_shift_fp13</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_phase_shift_fp13">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_phase_shift_fp14</spirit:name>
+ <spirit:displayName>hp_actual_phase_shift_fp14</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_phase_shift_fp14">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_phase_shift_fp15</spirit:name>
+ <spirit:displayName>hp_actual_phase_shift_fp15</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_phase_shift_fp15">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_phase_shift_fp16</spirit:name>
+ <spirit:displayName>hp_actual_phase_shift_fp16</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_phase_shift_fp16">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_phase_shift_fp17</spirit:name>
+ <spirit:displayName>hp_actual_phase_shift_fp17</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_phase_shift_fp17">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_duty_cycle_fp0</spirit:name>
+ <spirit:displayName>hp_actual_duty_cycle_fp0</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_duty_cycle_fp0">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_duty_cycle_fp1</spirit:name>
+ <spirit:displayName>hp_actual_duty_cycle_fp1</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_duty_cycle_fp1">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_duty_cycle_fp2</spirit:name>
+ <spirit:displayName>hp_actual_duty_cycle_fp2</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_duty_cycle_fp2">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_duty_cycle_fp3</spirit:name>
+ <spirit:displayName>hp_actual_duty_cycle_fp3</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_duty_cycle_fp3">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_duty_cycle_fp4</spirit:name>
+ <spirit:displayName>hp_actual_duty_cycle_fp4</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_duty_cycle_fp4">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_duty_cycle_fp5</spirit:name>
+ <spirit:displayName>hp_actual_duty_cycle_fp5</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_duty_cycle_fp5">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_duty_cycle_fp6</spirit:name>
+ <spirit:displayName>hp_actual_duty_cycle_fp6</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_duty_cycle_fp6">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_duty_cycle_fp7</spirit:name>
+ <spirit:displayName>hp_actual_duty_cycle_fp7</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_duty_cycle_fp7">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_duty_cycle_fp8</spirit:name>
+ <spirit:displayName>hp_actual_duty_cycle_fp8</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_duty_cycle_fp8">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_duty_cycle_fp9</spirit:name>
+ <spirit:displayName>hp_actual_duty_cycle_fp9</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_duty_cycle_fp9">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_duty_cycle_fp10</spirit:name>
+ <spirit:displayName>hp_actual_duty_cycle_fp10</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_duty_cycle_fp10">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_duty_cycle_fp11</spirit:name>
+ <spirit:displayName>hp_actual_duty_cycle_fp11</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_duty_cycle_fp11">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_duty_cycle_fp12</spirit:name>
+ <spirit:displayName>hp_actual_duty_cycle_fp12</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_duty_cycle_fp12">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_duty_cycle_fp13</spirit:name>
+ <spirit:displayName>hp_actual_duty_cycle_fp13</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_duty_cycle_fp13">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_duty_cycle_fp14</spirit:name>
+ <spirit:displayName>hp_actual_duty_cycle_fp14</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_duty_cycle_fp14">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_duty_cycle_fp15</spirit:name>
+ <spirit:displayName>hp_actual_duty_cycle_fp15</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_duty_cycle_fp15">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_duty_cycle_fp16</spirit:name>
+ <spirit:displayName>hp_actual_duty_cycle_fp16</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_duty_cycle_fp16">50.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hp_actual_duty_cycle_fp17</spirit:name>
+ <spirit:displayName>hp_actual_duty_cycle_fp17</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:id="hp_actual_duty_cycle_fp17">50.0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.dts.compatible</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.compatible">altr,pll</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.dts.group</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.group">clock</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.dts.vendor</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.vendor">altr</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+ element core_pll
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>locked</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>locked</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>outclk0</name>
+ <type>clock</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>outclk_0</name>
+ <role>clk</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedDirectClock</key>
+ </entry>
+ <entry>
+ <key>clockRate</key>
+ <value>100000000</value>
+ </entry>
+ <entry>
+ <key>clockRateKnown</key>
+ <value>true</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>outclk1</name>
+ <type>clock</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>outclk_1</name>
+ <role>clk</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedDirectClock</key>
+ </entry>
+ <entry>
+ <key>clockRate</key>
+ <value>100000000</value>
+ </entry>
+ <entry>
+ <key>clockRateKnown</key>
+ <value>true</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>refclk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>refclk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>200000000</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rst</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>outclk0</key>
+ <value>
+ <connectionPointName>outclk0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk1</key>
+ <value>
+ <connectionPointName>outclk1</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>200000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="locked" altera:internal="core_pll.locked" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="locked" altera:internal="locked"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="outclk0" altera:internal="core_pll.outclk0" altera:type="clock" altera:dir="start">
+ <altera:port_mapping altera:name="outclk_0" altera:internal="outclk_0"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="outclk1" altera:internal="core_pll.outclk1" altera:type="clock" altera:dir="start">
+ <altera:port_mapping altera:name="outclk_1" altera:internal="outclk_1"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="refclk" altera:internal="core_pll.refclk" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="refclk" altera:internal="refclk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="core_pll.reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="rst" altera:internal="rst"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx_core_pll.qsys b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx_core_pll.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..4f7ad9f6336c6e66ca5f51061d454c6b81195750
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx_core_pll.qsys
@@ -0,0 +1,572 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_jesd204b_rx_core_pll">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="System"
+ tool="QsysPro" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element iopll_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>outclk0</key>
+ <value>
+ <connectionPointName>outclk0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk1</key>
+ <value>
+ <connectionPointName>outclk1</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>200000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="locked" internal="iopll_0.locked" type="conduit" dir="end" />
+ <interface name="outclk0" internal="iopll_0.outclk0" type="clock" dir="start" />
+ <interface name="outclk1" internal="iopll_0.outclk1" type="clock" dir="start" />
+ <interface name="refclk" internal="iopll_0.refclk" type="clock" dir="end" />
+ <interface name="reset" internal="iopll_0.reset" type="reset" dir="end" />
+ <module
+ name="iopll_0"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>locked</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>locked</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>outclk0</name>
+ <type>clock</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>outclk_0</name>
+ <role>clk</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedDirectClock</key>
+ </entry>
+ <entry>
+ <key>clockRate</key>
+ <value>100000000</value>
+ </entry>
+ <entry>
+ <key>clockRateKnown</key>
+ <value>true</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>outclk1</name>
+ <type>clock</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>outclk_1</name>
+ <role>clk</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedDirectClock</key>
+ </entry>
+ <entry>
+ <key>clockRate</key>
+ <value>200000000</value>
+ </entry>
+ <entry>
+ <key>clockRateKnown</key>
+ <value>true</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>refclk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>refclk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>200000000</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rst</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>altera_iopll</className>
+ <version>19.3.0</version>
+ <displayName>IOPLL Intel FPGA IP</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors/>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>outclk0</key>
+ <value>
+ <connectionPointName>outclk0</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk1</key>
+ <value>
+ <connectionPointName>outclk1</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>200000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rst</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>refclk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>refclk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>200000000</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>locked</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>locked</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>outclk0</name>
+ <type>clock</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>outclk_0</name>
+ <role>clk</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedDirectClock</key>
+ </entry>
+ <entry>
+ <key>clockRate</key>
+ <value>100000000</value>
+ </entry>
+ <entry>
+ <key>clockRateKnown</key>
+ <value>true</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>outclk1</name>
+ <type>clock</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>outclk_1</name>
+ <role>clk</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedDirectClock</key>
+ </entry>
+ <entry>
+ <key>clockRate</key>
+ <value>200000000</value>
+ </entry>
+ <entry>
+ <key>clockRateKnown</key>
+ <value>true</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>ip_arria10_e2sg_jesd204b_rx_core_pll</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>ip_arria10_e2sg_jesd204b_rx_core_pll</fileSetName>
+ <fileSetFixedName>ip_arria10_e2sg_jesd204b_rx_core_pll</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>ip_arria10_e2sg_jesd204b_rx_core_pll</fileSetName>
+ <fileSetFixedName>ip_arria10_e2sg_jesd204b_rx_core_pll</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>ip_arria10_e2sg_jesd204b_rx_core_pll</fileSetName>
+ <fileSetFixedName>ip_arria10_e2sg_jesd204b_rx_core_pll</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip_arria10_e2sg_jesd204b_rx_core_pll.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.dts.compatible</key>
+ <value>altr,pll</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.group</key>
+ <value>clock</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.dts.vendor</key>
+ <value>altr</value>
+ </entry>
+ </assignmentValueMap>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx_reset_seq.ip b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx_reset_seq.ip
new file mode 100644
index 0000000000000000000000000000000000000000..d0d2f5fa65ed2c07bea22141b8b890d42ffb87fb
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx_reset_seq.ip
@@ -0,0 +1,2318 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>Intel Corporation</spirit:vendor>
+ <spirit:library>ip_arria10_e2sg_jesd204b_rx_reset_seq</spirit:library>
+ <spirit:name>reset_seq</spirit:name>
+ <spirit:version>18.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>av_csr</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>av_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>av_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>av_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>av_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>av_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">SYMBOLS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">csr_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">SYMBOLS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>av_csr_irq</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="interrupt" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>irq</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>irq</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedAddressablePoint</spirit:name>
+ <spirit:displayName>Associated addressable interface</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedAddressablePoint">ip_arria10_e2sg_jesd204b_rx_reset_seq.av_csr</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">csr_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedReceiverOffset</spirit:name>
+ <spirit:displayName>Bridged receiver offset</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bridgedReceiverOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToReceiver</spirit:name>
+ <spirit:displayName>Bridges to receiver</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToReceiver"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>irqScheme</spirit:name>
+ <spirit:displayName>Interrupt scheme</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="irqScheme">NONE</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>csr_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csr_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">NONE</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset1_dsrt_qual</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset1_dsrt_qual</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>reset1_dsrt_qual</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset2_dsrt_qual</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset2_dsrt_qual</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>reset2_dsrt_qual</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset5_dsrt_qual</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset5_dsrt_qual</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>reset5_dsrt_qual</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset_in0</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>reset_in0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">NONE</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset_out0</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:master></spirit:master>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>reset_out0</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedDirectReset</spirit:name>
+ <spirit:displayName>Associated direct reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedDirectReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedResetSinks</spirit:name>
+ <spirit:displayName>Associated reset sinks</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedResetSinks">reset_in0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">BOTH</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset_out1</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:master></spirit:master>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>reset_out1</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedDirectReset</spirit:name>
+ <spirit:displayName>Associated direct reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedDirectReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedResetSinks</spirit:name>
+ <spirit:displayName>Associated reset sinks</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedResetSinks">reset_in0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">BOTH</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset_out2</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:master></spirit:master>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>reset_out2</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedDirectReset</spirit:name>
+ <spirit:displayName>Associated direct reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedDirectReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedResetSinks</spirit:name>
+ <spirit:displayName>Associated reset sinks</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedResetSinks">reset_in0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">BOTH</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset_out3</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:master></spirit:master>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>reset_out3</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedDirectReset</spirit:name>
+ <spirit:displayName>Associated direct reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedDirectReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedResetSinks</spirit:name>
+ <spirit:displayName>Associated reset sinks</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedResetSinks">reset_in0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">BOTH</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset_out4</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:master></spirit:master>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>reset_out4</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedDirectReset</spirit:name>
+ <spirit:displayName>Associated direct reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedDirectReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedResetSinks</spirit:name>
+ <spirit:displayName>Associated reset sinks</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedResetSinks">reset_in0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">BOTH</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset_out5</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:master></spirit:master>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>reset_out5</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedDirectReset</spirit:name>
+ <spirit:displayName>Associated direct reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedDirectReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedResetSinks</spirit:name>
+ <spirit:displayName>Associated reset sinks</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedResetSinks">reset_in0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">BOTH</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset_out6</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:master></spirit:master>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>reset_out6</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedDirectReset</spirit:name>
+ <spirit:displayName>Associated direct reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedDirectReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedResetSinks</spirit:name>
+ <spirit:displayName>Associated reset sinks</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedResetSinks">reset_in0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">BOTH</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset_out7</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:master></spirit:master>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>reset_out7</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedDirectReset</spirit:name>
+ <spirit:displayName>Associated direct reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedDirectReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedResetSinks</spirit:name>
+ <spirit:displayName>Associated reset sinks</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedResetSinks">reset_in0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">BOTH</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>altera_reset_sequencer</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>reset_in0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>reset_out0</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>reset_out1</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>reset_out2</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>reset_out3</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>reset_out4</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>reset_out5</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>reset_out6</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>reset_out7</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>reset1_dsrt_qual</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>reset2_dsrt_qual</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>reset5_dsrt_qual</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csr_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>av_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>7</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>av_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>av_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>av_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>av_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>irq</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>Intel Corporation</spirit:vendor>
+ <spirit:library>ip_arria10_e2sg_jesd204b_rx_reset_seq</spirit:library>
+ <spirit:name>altera_reset_sequencer</spirit:name>
+ <spirit:version>18.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>NUM_OUTPUTS</spirit:name>
+ <spirit:displayName>Number of reset outputs</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="NUM_OUTPUTS">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>NUM_INPUTS</spirit:name>
+ <spirit:displayName>Number of reset inputs</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="NUM_INPUTS">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_RESET_REQUEST_INPUT</spirit:name>
+ <spirit:displayName>Enable reset request as input to sequencer</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ENABLE_RESET_REQUEST_INPUT">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_DEASSERTION_INPUT_QUAL</spirit:name>
+ <spirit:displayName>Bit-wise enable for input signal qualification</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ENABLE_DEASSERTION_INPUT_QUAL">38</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_ASSERTION_SEQUENCE</spirit:name>
+ <spirit:displayName>Enable reset assertion sequence</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ENABLE_ASSERTION_SEQUENCE">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_DEASSERTION_SEQUENCE</spirit:name>
+ <spirit:displayName>Enable reset de-assertion sequence</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ENABLE_DEASSERTION_SEQUENCE">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MIN_ASRT_TIME</spirit:name>
+ <spirit:displayName>Minimum reset assertion time</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="MIN_ASRT_TIME">20</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_DELAY0</spirit:name>
+ <spirit:displayName>Assertion Delay between reset_in to reset0</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ASRT_DELAY0">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_DELAY0</spirit:name>
+ <spirit:displayName>De-assertion Delay between reset_in to reset0</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_DELAY0">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_REMAP0</spirit:name>
+ <spirit:displayName>reset_out0 assert sequence #</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ASRT_REMAP0">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_REMAP0</spirit:name>
+ <spirit:displayName>reset_out0 de-assert sequence #</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_REMAP0">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_QUALCNT_0</spirit:name>
+ <spirit:displayName>Deglitch count for de-assertion of reset0_drst_qual</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_QUALCNT_0">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_DELAY1</spirit:name>
+ <spirit:displayName>Assertion Delay between reset0 to reset1</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ASRT_DELAY1">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_DELAY1</spirit:name>
+ <spirit:displayName>De-assertion Delay between reset0 to reset1</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_DELAY1">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_REMAP1</spirit:name>
+ <spirit:displayName>reset_out1 assert sequence #</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ASRT_REMAP1">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_REMAP1</spirit:name>
+ <spirit:displayName>reset_out1 de-assert sequence #</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_REMAP1">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_QUALCNT_1</spirit:name>
+ <spirit:displayName>Deglitch count for de-assertion of reset1_drst_qual</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_QUALCNT_1">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_DELAY2</spirit:name>
+ <spirit:displayName>Assertion Delay between reset1 to reset2</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ASRT_DELAY2">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_DELAY2</spirit:name>
+ <spirit:displayName>De-assertion Delay between reset1 to reset2</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_DELAY2">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_REMAP2</spirit:name>
+ <spirit:displayName>reset_out2 assert sequence #</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ASRT_REMAP2">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_REMAP2</spirit:name>
+ <spirit:displayName>reset_out2 de-assert sequence #</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_REMAP2">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_QUALCNT_2</spirit:name>
+ <spirit:displayName>Deglitch count for de-assertion of reset2_drst_qual</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_QUALCNT_2">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_DELAY3</spirit:name>
+ <spirit:displayName>Assertion Delay between reset2 to reset3</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ASRT_DELAY3">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_DELAY3</spirit:name>
+ <spirit:displayName>De-assertion Delay between reset2 to reset3</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_DELAY3">20</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_REMAP3</spirit:name>
+ <spirit:displayName>reset_out3 assert sequence #</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ASRT_REMAP3">3</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_REMAP3</spirit:name>
+ <spirit:displayName>reset_out3 de-assert sequence #</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_REMAP3">3</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_QUALCNT_3</spirit:name>
+ <spirit:displayName>Deglitch count for de-assertion of reset3_drst_qual</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_QUALCNT_3">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_DELAY4</spirit:name>
+ <spirit:displayName>Assertion Delay between reset3 to reset4</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ASRT_DELAY4">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_DELAY4</spirit:name>
+ <spirit:displayName>De-assertion Delay between reset3 to reset4</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_DELAY4">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_REMAP4</spirit:name>
+ <spirit:displayName>reset_out4 assert sequence #</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ASRT_REMAP4">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_REMAP4</spirit:name>
+ <spirit:displayName>reset_out4 de-assert sequence #</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_REMAP4">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_QUALCNT_4</spirit:name>
+ <spirit:displayName>Deglitch count for de-assertion of reset4_drst_qual</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_QUALCNT_4">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_DELAY5</spirit:name>
+ <spirit:displayName>Assertion Delay between reset4 to reset5</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ASRT_DELAY5">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_DELAY5</spirit:name>
+ <spirit:displayName>De-assertion Delay between reset4 to reset5</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_DELAY5">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_REMAP5</spirit:name>
+ <spirit:displayName>reset_out5 assert sequence #</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ASRT_REMAP5">5</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_REMAP5</spirit:name>
+ <spirit:displayName>reset_out5 de-assert sequence #</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_REMAP5">5</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_QUALCNT_5</spirit:name>
+ <spirit:displayName>Deglitch count for de-assertion of reset5_drst_qual</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_QUALCNT_5">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_DELAY6</spirit:name>
+ <spirit:displayName>Assertion Delay between reset5 to reset6</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ASRT_DELAY6">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_DELAY6</spirit:name>
+ <spirit:displayName>De-assertion Delay between reset5 to reset6</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_DELAY6">20</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_REMAP6</spirit:name>
+ <spirit:displayName>reset_out6 assert sequence #</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ASRT_REMAP6">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_REMAP6</spirit:name>
+ <spirit:displayName>reset_out6 de-assert sequence #</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_REMAP6">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_QUALCNT_6</spirit:name>
+ <spirit:displayName>Deglitch count for de-assertion of reset6_drst_qual</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_QUALCNT_6">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_DELAY7</spirit:name>
+ <spirit:displayName>Assertion Delay between reset6 to reset7</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ASRT_DELAY7">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_DELAY7</spirit:name>
+ <spirit:displayName>De-assertion Delay between reset6 to reset7</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_DELAY7">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_REMAP7</spirit:name>
+ <spirit:displayName>reset_out7 assert sequence #</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ASRT_REMAP7">7</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_REMAP7</spirit:name>
+ <spirit:displayName>reset_out7 de-assert sequence #</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_REMAP7">7</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_QUALCNT_7</spirit:name>
+ <spirit:displayName>Deglitch count for de-assertion of reset7_drst_qual</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_QUALCNT_7">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_DELAY8</spirit:name>
+ <spirit:displayName>Assertion Delay between reset7 to reset8</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ASRT_DELAY8">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_DELAY8</spirit:name>
+ <spirit:displayName>De-assertion Delay between reset7 to reset8</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_DELAY8">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_REMAP8</spirit:name>
+ <spirit:displayName>reset_out8 assert sequence #</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ASRT_REMAP8">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_REMAP8</spirit:name>
+ <spirit:displayName>reset_out8 de-assert sequence #</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_REMAP8">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_QUALCNT_8</spirit:name>
+ <spirit:displayName>Deglitch count for de-assertion of reset8_drst_qual</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_QUALCNT_8">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_DELAY9</spirit:name>
+ <spirit:displayName>Assertion Delay between reset8 to reset9</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ASRT_DELAY9">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_DELAY9</spirit:name>
+ <spirit:displayName>De-assertion Delay between reset8 to reset9</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_DELAY9">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_REMAP9</spirit:name>
+ <spirit:displayName>reset_out9 assert sequence #</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ASRT_REMAP9">9</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_REMAP9</spirit:name>
+ <spirit:displayName>reset_out9 de-assert sequence #</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_REMAP9">9</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_QUALCNT_9</spirit:name>
+ <spirit:displayName>Deglitch count for de-assertion of reset9_drst_qual</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="DSRT_QUALCNT_9">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_CSR</spirit:name>
+ <spirit:displayName>Enable Reset Sequencer CSR</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="ENABLE_CSR">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RESET_OUT_NAME</spirit:name>
+ <spirit:displayName>reset_out#</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="RESET_OUT_NAME">reset_out0,reset_out1,reset_out2,reset_out3,reset_out4,reset_out5,reset_out6,reset_out7</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>LIST_ASRT_SEQ</spirit:name>
+ <spirit:displayName>ASRT Seq#</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="LIST_ASRT_SEQ">0,1,2,3,4,5,6,7,8,9</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>LIST_DSRT_SEQ</spirit:name>
+ <spirit:displayName>DSRT Seq #</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="LIST_DSRT_SEQ">0,1,2,3,4,5,6,7,8,9</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>LIST_ASRT_DELAY</spirit:name>
+ <spirit:displayName>ASRT Delay Cycle#</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="LIST_ASRT_DELAY">0,0,0,0,0,0,0,0,0,0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>LIST_DSRT_DELAY</spirit:name>
+ <spirit:displayName>DSRT Delay Cycle# / Deglitch#</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="LIST_DSRT_DELAY">2,2,2,20,0,2,20,0,0,0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_DSRT_QUAL</spirit:name>
+ <spirit:displayName>USE_DSRT_QUAL</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="USE_DSRT_QUAL">0,1,1,0,0,1,0,0,0,0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASRT_SEQ_MSG</spirit:name>
+ <spirit:displayName>Assertion Sequence</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ASRT_SEQ_MSG">SEQUENCE DISABLED (All Delays are 0)</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DSRT_SEQ_MSG</spirit:name>
+ <spirit:displayName>De-assertion Sequence</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="DSRT_SEQ_MSG"><![CDATA[reset_in_deasserted-> #2-> reset_out0 ->wait_dqual1-> reset_out1 ->wait_dqual2-> reset_out2 -> #20-> reset_out3 + reset_out4 ->wait_dqual5-> reset_out5 -> #20-> reset_out6 + reset_out7]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+ element reset_seq
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>av_csr</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>av_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>av_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>av_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>av_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>av_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>SYMBOLS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>csr_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>SYMBOLS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>2</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>av_csr_irq</name>
+ <type>interrupt</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>irq</name>
+ <role>irq</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedAddressablePoint</key>
+ <value>altjesd_ss_RX_reset_seq.av_csr</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>csr_reset</value>
+ </entry>
+ <entry>
+ <key>bridgedReceiverOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToReceiver</key>
+ </entry>
+ <entry>
+ <key>irqScheme</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset1_dsrt_qual</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset1_dsrt_qual</name>
+ <role>reset1_dsrt_qual</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset2_dsrt_qual</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset2_dsrt_qual</name>
+ <role>reset2_dsrt_qual</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset5_dsrt_qual</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset5_dsrt_qual</name>
+ <role>reset5_dsrt_qual</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_in0</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset_in0</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out0</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out0</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out1</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out1</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out2</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out2</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out3</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out3</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out4</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out4</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out5</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out5</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out6</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out6</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out7</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out7</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>av_csr</key>
+ <value>
+ <connectionPointName>av_csr</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='av_csr' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="av_csr" altera:internal="reset_seq.av_csr" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="av_address" altera:internal="av_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="av_read" altera:internal="av_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="av_readdata" altera:internal="av_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="av_write" altera:internal="av_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="av_writedata" altera:internal="av_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="av_csr_irq" altera:internal="reset_seq.av_csr_irq" altera:type="interrupt" altera:dir="end">
+ <altera:port_mapping altera:name="irq" altera:internal="irq"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="reset_seq.clk" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="clk" altera:internal="clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="csr_reset" altera:internal="reset_seq.csr_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csr_reset" altera:internal="csr_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset1_dsrt_qual" altera:internal="reset_seq.reset1_dsrt_qual" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="reset1_dsrt_qual" altera:internal="reset1_dsrt_qual"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset2_dsrt_qual" altera:internal="reset_seq.reset2_dsrt_qual" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="reset2_dsrt_qual" altera:internal="reset2_dsrt_qual"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset5_dsrt_qual" altera:internal="reset_seq.reset5_dsrt_qual" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="reset5_dsrt_qual" altera:internal="reset5_dsrt_qual"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset_in0" altera:internal="reset_seq.reset_in0" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="reset_in0" altera:internal="reset_in0"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset_out0" altera:internal="reset_seq.reset_out0" altera:type="reset" altera:dir="start">
+ <altera:port_mapping altera:name="reset_out0" altera:internal="reset_out0"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset_out1" altera:internal="reset_seq.reset_out1" altera:type="reset" altera:dir="start">
+ <altera:port_mapping altera:name="reset_out1" altera:internal="reset_out1"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset_out2" altera:internal="reset_seq.reset_out2" altera:type="reset" altera:dir="start">
+ <altera:port_mapping altera:name="reset_out2" altera:internal="reset_out2"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset_out3" altera:internal="reset_seq.reset_out3" altera:type="reset" altera:dir="start">
+ <altera:port_mapping altera:name="reset_out3" altera:internal="reset_out3"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset_out4" altera:internal="reset_seq.reset_out4" altera:type="reset" altera:dir="start">
+ <altera:port_mapping altera:name="reset_out4" altera:internal="reset_out4"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset_out5" altera:internal="reset_seq.reset_out5" altera:type="reset" altera:dir="start">
+ <altera:port_mapping altera:name="reset_out5" altera:internal="reset_out5"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset_out6" altera:internal="reset_seq.reset_out6" altera:type="reset" altera:dir="start">
+ <altera:port_mapping altera:name="reset_out6" altera:internal="reset_out6"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset_out7" altera:internal="reset_seq.reset_out7" altera:type="reset" altera:dir="start">
+ <altera:port_mapping altera:name="reset_out7" altera:internal="reset_out7"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx_reset_seq.qsys b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx_reset_seq.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..a22b6e66b7e813a3e98b4e289a87c4cddd9ce6da
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx_reset_seq.qsys
@@ -0,0 +1,1740 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_jesd204b_rx_reset_seq">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="System"
+ tool="QsysPro" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element reset_sequencer_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>av_csr</key>
+ <value>
+ <connectionPointName>av_csr</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='reset_sequencer_0.av_csr' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="av_csr"
+ internal="reset_sequencer_0.av_csr"
+ type="avalon"
+ dir="end" />
+ <interface name="clk" internal="reset_sequencer_0.clk" type="clock" dir="end" />
+ <interface
+ name="csr_reset"
+ internal="reset_sequencer_0.csr_reset"
+ type="reset"
+ dir="end" />
+ <interface
+ name="irq"
+ internal="reset_sequencer_0.av_csr_irq"
+ type="interrupt"
+ dir="end" />
+ <interface
+ name="reset1_dsrt_qual"
+ internal="reset_sequencer_0.reset1_dsrt_qual"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reset2_dsrt_qual"
+ internal="reset_sequencer_0.reset2_dsrt_qual"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reset5_dsrt_qual"
+ internal="reset_sequencer_0.reset5_dsrt_qual"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reset_in0"
+ internal="reset_sequencer_0.reset_in0"
+ type="reset"
+ dir="end" />
+ <interface
+ name="reset_out0"
+ internal="reset_sequencer_0.reset_out0"
+ type="reset"
+ dir="start" />
+ <interface
+ name="reset_out1"
+ internal="reset_sequencer_0.reset_out1"
+ type="reset"
+ dir="start" />
+ <interface
+ name="reset_out2"
+ internal="reset_sequencer_0.reset_out2"
+ type="reset"
+ dir="start" />
+ <interface
+ name="reset_out3"
+ internal="reset_sequencer_0.reset_out3"
+ type="reset"
+ dir="start" />
+ <interface
+ name="reset_out4"
+ internal="reset_sequencer_0.reset_out4"
+ type="reset"
+ dir="start" />
+ <interface
+ name="reset_out5"
+ internal="reset_sequencer_0.reset_out5"
+ type="reset"
+ dir="start" />
+ <interface
+ name="reset_out6"
+ internal="reset_sequencer_0.reset_out6"
+ type="reset"
+ dir="start" />
+ <interface
+ name="reset_out7"
+ internal="reset_sequencer_0.reset_out7"
+ type="reset"
+ dir="start" />
+ <module
+ name="reset_sequencer_0"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>av_csr</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>av_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>av_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>av_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>av_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>av_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>SYMBOLS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>csr_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>SYMBOLS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>2</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>av_csr_irq</name>
+ <type>interrupt</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>irq</name>
+ <role>irq</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedAddressablePoint</key>
+ <value>reset_sequencer_0.av_csr</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>csr_reset</value>
+ </entry>
+ <entry>
+ <key>bridgedReceiverOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToReceiver</key>
+ </entry>
+ <entry>
+ <key>irqScheme</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset1_dsrt_qual</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset1_dsrt_qual</name>
+ <role>reset1_dsrt_qual</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset2_dsrt_qual</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset2_dsrt_qual</name>
+ <role>reset2_dsrt_qual</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset5_dsrt_qual</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset5_dsrt_qual</name>
+ <role>reset5_dsrt_qual</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_in0</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset_in0</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out0</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out0</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out1</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out1</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out2</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out2</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out3</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out3</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out4</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out4</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out5</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out5</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out6</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out6</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out7</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out7</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>altera_reset_sequencer</className>
+ <version>19.1</version>
+ <displayName>Reset Sequencer Intel FPGA IP</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors/>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>av_csr</key>
+ <value>
+ <connectionPointName>av_csr</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='av_csr' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>clk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_in0</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset_in0</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out0</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out0</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out1</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out1</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out2</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out2</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out3</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out3</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out4</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out4</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out5</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out5</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out6</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out6</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset_out7</name>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <ports>
+ <port>
+ <name>reset_out7</name>
+ <role>reset</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedDirectReset</key>
+ </entry>
+ <entry>
+ <key>associatedResetSinks</key>
+ <value>reset_in0</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>BOTH</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset1_dsrt_qual</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset1_dsrt_qual</name>
+ <role>reset1_dsrt_qual</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset2_dsrt_qual</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset2_dsrt_qual</name>
+ <role>reset2_dsrt_qual</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset5_dsrt_qual</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset5_dsrt_qual</name>
+ <role>reset5_dsrt_qual</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>csr_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csr_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>av_csr</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>av_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>av_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>av_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>av_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>av_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>false</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>SYMBOLS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>csr_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>SYMBOLS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>2</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>av_csr_irq</name>
+ <type>interrupt</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>irq</name>
+ <role>irq</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedAddressablePoint</key>
+ <value>reset_seq.av_csr</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>csr_reset</value>
+ </entry>
+ <entry>
+ <key>bridgedReceiverOffset</key>
+ </entry>
+ <entry>
+ <key>bridgesToReceiver</key>
+ </entry>
+ <entry>
+ <key>irqScheme</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>ip_arria10_e2sg_jesd204b_rx_reset_seq</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>ip_arria10_e2sg_jesd204b_rx_reset_seq</fileSetName>
+ <fileSetFixedName>ip_arria10_e2sg_jesd204b_rx_reset_seq</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>ip_arria10_e2sg_jesd204b_rx_reset_seq</fileSetName>
+ <fileSetFixedName>ip_arria10_e2sg_jesd204b_rx_reset_seq</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>ip_arria10_e2sg_jesd204b_rx_reset_seq</fileSetName>
+ <fileSetFixedName>ip_arria10_e2sg_jesd204b_rx_reset_seq</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip_arria10_e2sg_jesd204b_rx_reset_seq.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12.ip b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12.ip
new file mode 100644
index 0000000000000000000000000000000000000000..918b5bc3bfef526bc0bbb86c83c9c3d2b9e0c7eb
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12.ip
@@ -0,0 +1,912 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>Intel Corporation</spirit:vendor>
+ <spirit:library>ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12</spirit:library>
+ <spirit:name>xcvr_reset_control_0</spirit:name>
+ <spirit:version>18.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>clock</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>clock</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">NONE</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>rx_analogreset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>rx_analogreset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rx_analogreset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>rx_cal_busy</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>rx_cal_busy</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rx_cal_busy</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>rx_digitalreset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>rx_digitalreset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rx_digitalreset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>rx_is_lockedtodata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>rx_is_lockedtodata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rx_is_lockedtodata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">input</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>rx_ready</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>rx_ready</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rx_ready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ui.blockdiagram.direction</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>altera_xcvr_reset_control</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>clock</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>rx_analogreset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>11</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>rx_digitalreset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>11</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>rx_ready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>11</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>rx_is_lockedtodata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>11</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>rx_cal_busy</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>11</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>Intel Corporation</spirit:vendor>
+ <spirit:library>ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12</spirit:library>
+ <spirit:name>altera_xcvr_reset_control</spirit:name>
+ <spirit:version>18.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device_family</spirit:name>
+ <spirit:displayName>device_family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device_family">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CHANNELS</spirit:name>
+ <spirit:displayName>Number of transceiver channels</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="CHANNELS">12</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLLS</spirit:name>
+ <spirit:displayName>Number of TX PLLs</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="PLLS">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SYS_CLK_IN_MHZ</spirit:name>
+ <spirit:displayName>Input clock frequency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="SYS_CLK_IN_MHZ">100</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SYNCHRONIZE_RESET</spirit:name>
+ <spirit:displayName>Synchronize reset input</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="SYNCHRONIZE_RESET">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>REDUCED_SIM_TIME</spirit:name>
+ <spirit:displayName>Use fast reset for simulation</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="REDUCED_SIM_TIME">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_split_interfaces</spirit:name>
+ <spirit:displayName>Separate interface per channel/PLL</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_split_interfaces">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>TX_PLL_ENABLE</spirit:name>
+ <spirit:displayName>Enable TX PLL reset control</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="TX_PLL_ENABLE">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>T_PLL_POWERDOWN</spirit:name>
+ <spirit:displayName>pll_powerdown duration</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="T_PLL_POWERDOWN">1000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SYNCHRONIZE_PLL_RESET</spirit:name>
+ <spirit:displayName>Synchronize reset input for PLL powerdown</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="SYNCHRONIZE_PLL_RESET">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>TX_ENABLE</spirit:name>
+ <spirit:displayName>Enable TX channel reset control</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="TX_ENABLE">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>TX_PER_CHANNEL</spirit:name>
+ <spirit:displayName>Use separate TX reset per channel</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="TX_PER_CHANNEL">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_tx_auto_reset</spirit:name>
+ <spirit:displayName>TX digital reset mode</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_tx_auto_reset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>T_TX_ANALOGRESET</spirit:name>
+ <spirit:displayName>tx_analogreset duration</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="T_TX_ANALOGRESET">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>T_TX_DIGITALRESET</spirit:name>
+ <spirit:displayName>tx_digitalreset duration</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="T_TX_DIGITALRESET">20</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>T_PLL_LOCK_HYST</spirit:name>
+ <spirit:displayName>pll_locked input hysteresis</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="T_PLL_LOCK_HYST">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_pll_cal_busy</spirit:name>
+ <spirit:displayName>Enable pll_cal_busy input port</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_pll_cal_busy">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>EN_PLL_CAL_BUSY</spirit:name>
+ <spirit:displayName>EN_PLL_CAL_BUSY</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="EN_PLL_CAL_BUSY">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RX_ENABLE</spirit:name>
+ <spirit:displayName>Enable RX channel reset control</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="RX_ENABLE">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RX_PER_CHANNEL</spirit:name>
+ <spirit:displayName>Use separate RX reset per channel</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="RX_PER_CHANNEL">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>gui_rx_auto_reset</spirit:name>
+ <spirit:displayName>RX digital reset mode</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="gui_rx_auto_reset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>T_RX_ANALOGRESET</spirit:name>
+ <spirit:displayName>rx_analogreset duration</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="T_RX_ANALOGRESET">70000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>T_RX_DIGITALRESET</spirit:name>
+ <spirit:displayName>rx_digitalreset duration</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="T_RX_DIGITALRESET">4000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>l_terminate_pll</spirit:name>
+ <spirit:displayName>l_terminate_pll</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="l_terminate_pll">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>l_terminate_tx</spirit:name>
+ <spirit:displayName>l_terminate_tx</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="l_terminate_tx">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>l_terminate_rx</spirit:name>
+ <spirit:displayName>l_terminate_rx</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="l_terminate_rx">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>l_terminate_tx_manual</spirit:name>
+ <spirit:displayName>l_terminate_tx_manual</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="l_terminate_tx_manual">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>l_terminate_rx_manual</spirit:name>
+ <spirit:displayName>l_terminate_rx_manual</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="l_terminate_rx_manual">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>l_tx_manual_term</spirit:name>
+ <spirit:displayName>l_tx_manual_term</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="l_tx_manual_term">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>l_rx_manual_term</spirit:name>
+ <spirit:displayName>l_rx_manual_term</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="l_rx_manual_term">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>l_pll_select_split</spirit:name>
+ <spirit:displayName>l_pll_select_split</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="l_pll_select_split">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>l_pll_select_width</spirit:name>
+ <spirit:displayName>l_pll_select_width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="l_pll_select_width">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>l_pll_select_base</spirit:name>
+ <spirit:displayName>l_pll_select_base</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="l_pll_select_base">1</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+ element xcvr_reset_control_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>clock</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>clock</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_analogreset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_analogreset</name>
+ <role>rx_analogreset</role>
+ <direction>Output</direction>
+ <width>12</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_cal_busy</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_cal_busy</name>
+ <role>rx_cal_busy</role>
+ <direction>Input</direction>
+ <width>12</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_digitalreset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_digitalreset</name>
+ <role>rx_digitalreset</role>
+ <direction>Output</direction>
+ <width>12</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_is_lockedtodata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_is_lockedtodata</name>
+ <role>rx_is_lockedtodata</role>
+ <direction>Input</direction>
+ <width>12</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_ready</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_ready</name>
+ <role>rx_ready</role>
+ <direction>Output</direction>
+ <width>12</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="clock" altera:internal="xcvr_reset_control_0.clock" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="clock" altera:internal="clock"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="pll_locked" altera:internal="xcvr_reset_control_0.pll_locked"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="pll_powerdown" altera:internal="xcvr_reset_control_0.pll_powerdown"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="pll_select" altera:internal="xcvr_reset_control_0.pll_select"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="xcvr_reset_control_0.reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="reset" altera:internal="reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_analogreset" altera:internal="xcvr_reset_control_0.rx_analogreset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="rx_analogreset" altera:internal="rx_analogreset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_cal_busy" altera:internal="xcvr_reset_control_0.rx_cal_busy" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="rx_cal_busy" altera:internal="rx_cal_busy"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_digitalreset" altera:internal="xcvr_reset_control_0.rx_digitalreset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="rx_digitalreset" altera:internal="rx_digitalreset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_is_lockedtodata" altera:internal="xcvr_reset_control_0.rx_is_lockedtodata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="rx_is_lockedtodata" altera:internal="rx_is_lockedtodata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="rx_ready" altera:internal="xcvr_reset_control_0.rx_ready" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="rx_ready" altera:internal="rx_ready"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_analogreset" altera:internal="xcvr_reset_control_0.tx_analogreset"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_cal_busy" altera:internal="xcvr_reset_control_0.tx_cal_busy"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_digitalreset" altera:internal="xcvr_reset_control_0.tx_digitalreset"></altera:interface_mapping>
+ <altera:interface_mapping altera:name="tx_ready" altera:internal="xcvr_reset_control_0.tx_ready"></altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12.qsys b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..afe9ab1627f52c3b5fc5ae0a6c84d128c1f595f3
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12.qsys
@@ -0,0 +1,639 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="System"
+ tool="QsysPro" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element xcvr_reset_control_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="clock"
+ internal="xcvr_reset_control_0.clock"
+ type="clock"
+ dir="end" />
+ <interface name="pll_powerdown" internal="xcvr_reset_control_0.pll_powerdown" />
+ <interface
+ name="reset"
+ internal="xcvr_reset_control_0.reset"
+ type="reset"
+ dir="end" />
+ <interface
+ name="rx_analogreset"
+ internal="xcvr_reset_control_0.rx_analogreset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rx_cal_busy"
+ internal="xcvr_reset_control_0.rx_cal_busy"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rx_digitalreset"
+ internal="xcvr_reset_control_0.rx_digitalreset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rx_is_lockedtodata"
+ internal="xcvr_reset_control_0.rx_is_lockedtodata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rx_ready"
+ internal="xcvr_reset_control_0.rx_ready"
+ type="conduit"
+ dir="end" />
+ <module
+ name="xcvr_reset_control_0"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>clock</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>clock</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_analogreset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_analogreset</name>
+ <role>rx_analogreset</role>
+ <direction>Output</direction>
+ <width>12</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_cal_busy</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_cal_busy</name>
+ <role>rx_cal_busy</role>
+ <direction>Input</direction>
+ <width>12</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_digitalreset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_digitalreset</name>
+ <role>rx_digitalreset</role>
+ <direction>Output</direction>
+ <width>12</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_is_lockedtodata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_is_lockedtodata</name>
+ <role>rx_is_lockedtodata</role>
+ <direction>Input</direction>
+ <width>12</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_ready</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_ready</name>
+ <role>rx_ready</role>
+ <direction>Output</direction>
+ <width>12</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>altera_xcvr_reset_control</className>
+ <version>19.1</version>
+ <displayName>Transceiver PHY Reset Controller Intel FPGA IP</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>Stratix V</parameterDefaultValue>
+ <parameterName>device_family</parameterName>
+ <parameterType>java.lang.String</parameterType>
+ <systemInfotype>DEVICE_FAMILY</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos/>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>clock</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>clock</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_analogreset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_analogreset</name>
+ <role>rx_analogreset</role>
+ <direction>Output</direction>
+ <width>12</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_digitalreset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_digitalreset</name>
+ <role>rx_digitalreset</role>
+ <direction>Output</direction>
+ <width>12</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_ready</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_ready</name>
+ <role>rx_ready</role>
+ <direction>Output</direction>
+ <width>12</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>output</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_is_lockedtodata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_is_lockedtodata</name>
+ <role>rx_is_lockedtodata</role>
+ <direction>Input</direction>
+ <width>12</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>rx_cal_busy</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>rx_cal_busy</name>
+ <role>rx_cal_busy</role>
+ <direction>Input</direction>
+ <width>12</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>ui.blockdiagram.direction</key>
+ <value>input</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12</fileSetName>
+ <fileSetFixedName>ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12</fileSetName>
+ <fileSetFixedName>ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12</fileSetName>
+ <fileSetFixedName>ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/mac_10g/README.txt b/libraries/technology/ip_arria10_e2sg/mac_10g/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..c775402d02b409cbc5f046ee91549577ddf8c52a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/mac_10g/README.txt
@@ -0,0 +1,55 @@
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g
+
+1) Porting
+2) IP component
+3) Compilation, simulation and verification
+4) Synthesis
+5) Remarks
+
+
+1) Porting
+
+The mac_10g IP was ported manually from Quartus v11.1 for Stratix IV to Quartus 14.0a10 for Arria10 by creating it in Qsys using
+the same parameter settings.
+
+
+2) IP component
+
+The generated IP is not kept in SVN, only the Qsys source file:
+
+ ip_arria10_mac_10g.qsys
+
+Therefore first the IP needs to be generated using:
+
+ ./generate_ip.sh
+
+
+3) Compilation, simulation and verification
+
+The genrated IP also contains a msim_setup.tcl file that was used to manually create:
+
+ compile_ip.tcl
+
+This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code.
+
+
+4) Synthesis
+
+No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
+
+ ip_arria10_mac_10g.qip
+
+is included in the hdllib.cfg and contains what is needed to synthesize the IP.
+
+
+5) Remarks
+
+a) Use generated IP specific library clause name
+
+ The generated ip_arria10_<lib_name>.vhd uses an IP specific library name. Therefore the hdllib.cfg uses the IP
+ specific library as library claus name to make it known:
+
+ hdl_lib_name = ip_arria10_<lib_name>
+ hdl_library_clause_name = ip_arria10_<lib_name>_<ip_specific>
+
+
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/mac_10g/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f7f37290b061064ae6303e4ce53f382935df23d6
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/mac_10g/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_mac_10g/sim"
+
+
+ vcom "$IP_DIR/ip_arria10_e2sg_mac_10g.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/mac_10g/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..649239b180b8c5541e6fdc95ac39cea72c1ffb65
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/mac_10g/hdllib.cfg
@@ -0,0 +1,27 @@
+hdl_lib_name = ip_arria10_e2sg_mac_10g
+hdl_library_clause_name = ip_arria10_e2sg_mac_10g_alt_em10g32_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_alt_em10g32_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+ # The generated testbench is listed here to create a simulation configuration for it. However
+ # the tb is commented because it is not useful, see generate_ip.sh.
+ #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e2sg_mac_10g_tb.vhd
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/mac_10g/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_mac_10g/ip_arria10_e2sg_mac_10g.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_mac_10g.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/mac_10g/ip_arria10_e2sg_mac_10g.qsys b/libraries/technology/ip_arria10_e2sg/mac_10g/ip_arria10_e2sg_mac_10g.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..d6d1f04d8531b2f5b81e9d2bebe1610ffbdf4073
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/mac_10g/ip_arria10_e2sg_mac_10g.qsys
@@ -0,0 +1,272 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_mac_10g">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element alt_em10g32_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>csr</key>
+ <value>
+ <connectionPointName>csr</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='csr' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>15</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="avalon_st_pause"
+ internal="alt_em10g32_0.avalon_st_pause"
+ type="avalon_streaming"
+ dir="end">
+ <port name="avalon_st_pause_data" internal="avalon_st_pause_data" />
+ </interface>
+ <interface
+ name="avalon_st_rx"
+ internal="alt_em10g32_0.avalon_st_rx"
+ type="avalon_streaming"
+ dir="start">
+ <port name="avalon_st_rx_data" internal="avalon_st_rx_data" />
+ <port name="avalon_st_rx_empty" internal="avalon_st_rx_empty" />
+ <port name="avalon_st_rx_endofpacket" internal="avalon_st_rx_endofpacket" />
+ <port name="avalon_st_rx_error" internal="avalon_st_rx_error" />
+ <port name="avalon_st_rx_ready" internal="avalon_st_rx_ready" />
+ <port
+ name="avalon_st_rx_startofpacket"
+ internal="avalon_st_rx_startofpacket" />
+ <port name="avalon_st_rx_valid" internal="avalon_st_rx_valid" />
+ </interface>
+ <interface
+ name="avalon_st_rxstatus"
+ internal="alt_em10g32_0.avalon_st_rxstatus"
+ type="avalon_streaming"
+ dir="start">
+ <port name="avalon_st_rxstatus_data" internal="avalon_st_rxstatus_data" />
+ <port name="avalon_st_rxstatus_error" internal="avalon_st_rxstatus_error" />
+ <port name="avalon_st_rxstatus_valid" internal="avalon_st_rxstatus_valid" />
+ </interface>
+ <interface
+ name="avalon_st_tx"
+ internal="alt_em10g32_0.avalon_st_tx"
+ type="avalon_streaming"
+ dir="end">
+ <port name="avalon_st_tx_data" internal="avalon_st_tx_data" />
+ <port name="avalon_st_tx_empty" internal="avalon_st_tx_empty" />
+ <port name="avalon_st_tx_endofpacket" internal="avalon_st_tx_endofpacket" />
+ <port name="avalon_st_tx_error" internal="avalon_st_tx_error" />
+ <port name="avalon_st_tx_ready" internal="avalon_st_tx_ready" />
+ <port
+ name="avalon_st_tx_startofpacket"
+ internal="avalon_st_tx_startofpacket" />
+ <port name="avalon_st_tx_valid" internal="avalon_st_tx_valid" />
+ </interface>
+ <interface
+ name="avalon_st_txstatus"
+ internal="alt_em10g32_0.avalon_st_txstatus"
+ type="avalon_streaming"
+ dir="start">
+ <port name="avalon_st_txstatus_data" internal="avalon_st_txstatus_data" />
+ <port name="avalon_st_txstatus_error" internal="avalon_st_txstatus_error" />
+ <port name="avalon_st_txstatus_valid" internal="avalon_st_txstatus_valid" />
+ </interface>
+ <interface name="csr" internal="alt_em10g32_0.csr" type="avalon" dir="end">
+ <port name="csr_address" internal="csr_address" />
+ <port name="csr_read" internal="csr_read" />
+ <port name="csr_readdata" internal="csr_readdata" />
+ <port name="csr_waitrequest" internal="csr_waitrequest" />
+ <port name="csr_write" internal="csr_write" />
+ <port name="csr_writedata" internal="csr_writedata" />
+ </interface>
+ <interface
+ name="csr_clk"
+ internal="alt_em10g32_0.csr_clk"
+ type="clock"
+ dir="end">
+ <port name="csr_clk" internal="csr_clk" />
+ </interface>
+ <interface
+ name="csr_rst_n"
+ internal="alt_em10g32_0.csr_rst_n"
+ type="reset"
+ dir="end">
+ <port name="csr_rst_n" internal="csr_rst_n" />
+ </interface>
+ <interface
+ name="link_fault_status_xgmii_rx"
+ internal="alt_em10g32_0.link_fault_status_xgmii_rx"
+ type="avalon_streaming"
+ dir="start">
+ <port
+ name="link_fault_status_xgmii_rx_data"
+ internal="link_fault_status_xgmii_rx_data" />
+ </interface>
+ <interface
+ name="rx_156_25_clk"
+ internal="alt_em10g32_0.rx_156_25_clk"
+ type="clock"
+ dir="end">
+ <port name="rx_156_25_clk" internal="rx_156_25_clk" />
+ </interface>
+ <interface
+ name="rx_312_5_clk"
+ internal="alt_em10g32_0.rx_312_5_clk"
+ type="clock"
+ dir="end">
+ <port name="rx_312_5_clk" internal="rx_312_5_clk" />
+ </interface>
+ <interface
+ name="rx_rst_n"
+ internal="alt_em10g32_0.rx_rst_n"
+ type="reset"
+ dir="end">
+ <port name="rx_rst_n" internal="rx_rst_n" />
+ </interface>
+ <interface
+ name="tx_156_25_clk"
+ internal="alt_em10g32_0.tx_156_25_clk"
+ type="clock"
+ dir="end">
+ <port name="tx_156_25_clk" internal="tx_156_25_clk" />
+ </interface>
+ <interface
+ name="tx_312_5_clk"
+ internal="alt_em10g32_0.tx_312_5_clk"
+ type="clock"
+ dir="end">
+ <port name="tx_312_5_clk" internal="tx_312_5_clk" />
+ </interface>
+ <interface
+ name="tx_rst_n"
+ internal="alt_em10g32_0.tx_rst_n"
+ type="reset"
+ dir="end">
+ <port name="tx_rst_n" internal="tx_rst_n" />
+ </interface>
+ <interface
+ name="unidirectional"
+ internal="alt_em10g32_0.unidirectional"
+ type="conduit"
+ dir="end">
+ <port name="unidirectional_en" internal="unidirectional_en" />
+ <port
+ name="unidirectional_force_remote_fault"
+ internal="unidirectional_force_remote_fault" />
+ <port
+ name="unidirectional_remote_fault_dis"
+ internal="unidirectional_remote_fault_dis" />
+ </interface>
+ <interface
+ name="xgmii_rx"
+ internal="alt_em10g32_0.xgmii_rx"
+ type="avalon_streaming"
+ dir="end">
+ <port name="xgmii_rx" internal="xgmii_rx" />
+ </interface>
+ <interface name="xgmii_rx_control" internal="alt_em10g32_0.xgmii_rx_control" />
+ <interface name="xgmii_rx_data" internal="alt_em10g32_0.xgmii_rx_data" />
+ <interface
+ name="xgmii_tx"
+ internal="alt_em10g32_0.xgmii_tx"
+ type="avalon_streaming"
+ dir="start">
+ <port name="xgmii_tx" internal="xgmii_tx" />
+ </interface>
+ <interface name="xgmii_tx_control" internal="alt_em10g32_0.xgmii_tx_control" />
+ <interface name="xgmii_tx_data" internal="alt_em10g32_0.xgmii_tx_data" />
+ <module
+ name="alt_em10g32_0"
+ kind="alt_em10g32"
+ version="19.3.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="ANLG_VOLTAGE" value="1_0V" />
+ <parameter name="DATAPATH_OPTION" value="3" />
+ <parameter name="DEVICE" value="10AX115U3F45E2SG" />
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="DEVKIT_DEVICE" value="10AX115S4F45E3SGE3" />
+ <parameter name="ENABLE_10GBASER_REG_MODE" value="0" />
+ <parameter name="ENABLE_1G10G_MAC" value="0" />
+ <parameter name="ENABLE_ADME" value="0" />
+ <parameter name="ENABLE_ASYMMETRY" value="0" />
+ <parameter name="ENABLE_ED_FILESET_SIM" value="1" />
+ <parameter name="ENABLE_ED_FILESET_SYNTHESIS" value="1" />
+ <parameter name="ENABLE_MEM_ECC" value="0" />
+ <parameter name="ENABLE_P2P" value="0" />
+ <parameter name="ENABLE_PFC" value="0" />
+ <parameter name="ENABLE_PTP_1STEP" value="0" />
+ <parameter name="ENABLE_SUPP_ADDR" value="0" />
+ <parameter name="ENABLE_TIMESTAMPING" value="0" />
+ <parameter name="ENABLE_TXRX_DATAPATH" value="1" />
+ <parameter name="ENABLE_UNIDIRECTIONAL" value="1" />
+ <parameter name="INSERT_CSR_ADAPTOR" value="1" />
+ <parameter name="INSERT_ST_ADAPTOR" value="1" />
+ <parameter name="INSERT_XGMII_ADAPTOR" value="1" />
+ <parameter name="INSTANTIATE_STATISTICS" value="1" />
+ <parameter name="INTERNAL_FEATURE" value="false" />
+ <parameter name="PFC_PRIORITY_NUMBER" value="8" />
+ <parameter name="PREAMBLE_PASSTHROUGH" value="0" />
+ <parameter name="PR_READY" value="0" />
+ <parameter name="QSF_PATH">LL10G_Ethernet_A10_10GBASER/</parameter>
+ <parameter name="REGISTER_BASED_STATISTICS" value="1" />
+ <parameter name="SELECT_CUSTOM_DEVICE" value="1" />
+ <parameter name="SELECT_ED_FILESET" value="0" />
+ <parameter name="SELECT_NUMBER_OF_CHANNEL" value="1" />
+ <parameter name="SELECT_SUPPORTED_VARIANT" value="10" />
+ <parameter name="SELECT_TARGETED_DEVICE" value="0" />
+ <parameter name="SHOW_HIDDEN_OPTIONS" value="0" />
+ <parameter name="TIME_OF_DAY_FORMAT" value="2" />
+ <parameter name="TSTAMP_FP_WIDTH" value="4" />
+ <parameter name="die_types" value="" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/mult_add2/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/mult_add2/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..15a889ac4bd6c99e72081b80cdb069dd0fc62f3a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/mult_add2/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_mult_add2
+hdl_library_clause_name = ip_arria10_e2sg_mult_add2_lib
+hdl_lib_uses_synth = technology common
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+ ip_arria10_e2sg_mult_add2_rtl.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_arria10_e2sg/mult_add2/ip_arria10_e2sg_mult_add2_rtl.vhd b/libraries/technology/ip_arria10_e2sg/mult_add2/ip_arria10_e2sg_mult_add2_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2e42f1afb5ecf058fbdc4f85a38e624161f1eb64
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/mult_add2/ip_arria10_e2sg_mult_add2_rtl.vhd
@@ -0,0 +1,203 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2009
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Based on ip_stratixiv_mult_add2_rtl
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+
+
+------------------------------------------------------------------------------
+-- Function:
+-- . res = a0 * b0 + a1 * b1
+-- . res = a0 * b0 - a1 * b1
+------------------------------------------------------------------------------
+
+ENTITY ip_arria10_e2sg_mult_add2_rtl IS
+ GENERIC (
+ g_in_a_w : POSITIVE;
+ g_in_b_w : POSITIVE;
+ g_res_w : POSITIVE; -- g_in_a_w + g_in_b_w + log2(2)
+ g_force_dsp : BOOLEAN := TRUE; -- when TRUE resize input width to >= 18
+ g_add_sub : STRING := "ADD"; -- or "SUB"
+ g_nof_mult : INTEGER := 2; -- fixed
+ g_pipeline_input : NATURAL := 1; -- 0 or 1
+ g_pipeline_product : NATURAL := 0; -- 0 or 1
+ g_pipeline_adder : NATURAL := 1; -- 0 or 1
+ g_pipeline_output : NATURAL := 1 -- >= 0
+ );
+ PORT (
+ rst : IN STD_LOGIC := '0';
+ clk : IN STD_LOGIC;
+ clken : IN STD_LOGIC := '1';
+ in_a : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
+ in_b : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
+ res : OUT STD_LOGIC_VECTOR(g_res_w-1 DOWNTO 0)
+ );
+END ip_arria10_e2sg_mult_add2_rtl;
+
+
+ARCHITECTURE str OF ip_arria10_e2sg_mult_add2_rtl IS
+
+ -- Extra output pipelining is only needed when g_pipeline_output > 1
+ CONSTANT c_pipeline_output : NATURAL := sel_a_b(g_pipeline_output>0, g_pipeline_output-1, 0);
+
+ CONSTANT c_prod_w : NATURAL := g_in_a_w+g_in_b_w;
+ CONSTANT c_sum_w : NATURAL := c_prod_w+1;
+
+ -- registers
+ SIGNAL reg_a0 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL reg_b0 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL reg_a1 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL reg_b1 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL reg_prod0 : SIGNED(c_prod_w-1 DOWNTO 0);
+ SIGNAL reg_prod1 : SIGNED(c_prod_w-1 DOWNTO 0);
+ SIGNAL reg_sum : SIGNED(c_sum_w-1 DOWNTO 0);
+ SIGNAL reg_result : SIGNED(g_res_w-1 DOWNTO 0);
+
+ -- combinatorial
+ SIGNAL nxt_a0 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL nxt_b0 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL nxt_a1 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL nxt_b1 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL nxt_prod0 : SIGNED(c_prod_w-1 DOWNTO 0);
+ SIGNAL nxt_prod1 : SIGNED(c_prod_w-1 DOWNTO 0);
+ SIGNAL nxt_sum : SIGNED(c_sum_w-1 DOWNTO 0);
+ SIGNAL nxt_result : SIGNED(g_res_w-1 DOWNTO 0);
+
+ -- the active signals
+ SIGNAL a0 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL b0 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL a1 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL b1 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL prod0 : SIGNED(c_prod_w-1 DOWNTO 0);
+ SIGNAL prod1 : SIGNED(c_prod_w-1 DOWNTO 0);
+ SIGNAL sum : SIGNED(c_sum_w-1 DOWNTO 0);
+ SIGNAL result : SIGNED(g_res_w-1 DOWNTO 0);
+
+BEGIN
+
+ ------------------------------------------------------------------------------
+ -- Registers
+ ------------------------------------------------------------------------------
+
+ -- Put all potential registers in a single process for optimal DSP inferrence
+ -- Use rst only if it is supported by the DSP primitive, else leave it at '0'
+ p_reg : PROCESS (rst, clk)
+ BEGIN
+ IF rising_edge(clk) THEN
+ IF rst='1' THEN
+ reg_a0 <= (OTHERS=>'0');
+ reg_b0 <= (OTHERS=>'0');
+ reg_a1 <= (OTHERS=>'0');
+ reg_b1 <= (OTHERS=>'0');
+ reg_prod0 <= (OTHERS=>'0');
+ reg_prod1 <= (OTHERS=>'0');
+ reg_sum <= (OTHERS=>'0');
+ reg_result <= (OTHERS=>'0');
+ ELSIF clken='1' THEN
+ reg_a0 <= nxt_a0; -- inputs
+ reg_b0 <= nxt_b0;
+ reg_a1 <= nxt_a1;
+ reg_b1 <= nxt_b1;
+ reg_prod0 <= nxt_prod0; -- products
+ reg_prod1 <= nxt_prod1;
+ reg_sum <= nxt_sum; -- sum
+ reg_result <= nxt_result; -- result sum after optional rounding
+ END IF;
+ END IF;
+ END PROCESS;
+
+ ------------------------------------------------------------------------------
+ -- Inputs
+ ------------------------------------------------------------------------------
+
+ nxt_a0 <= SIGNED(in_a( g_in_a_w-1 DOWNTO 0));
+ nxt_b0 <= SIGNED(in_b( g_in_b_w-1 DOWNTO 0));
+ nxt_a1 <= SIGNED(in_a(2*g_in_a_w-1 DOWNTO g_in_a_w));
+ nxt_b1 <= SIGNED(in_b(2*g_in_b_w-1 DOWNTO g_in_b_w));
+
+ no_input_reg : IF g_pipeline_input=0 GENERATE -- wired
+ a0 <= nxt_a0;
+ b0 <= nxt_b0;
+ a1 <= nxt_a1;
+ b1 <= nxt_b1;
+ END GENERATE;
+
+ gen_input_reg : IF g_pipeline_input>0 GENERATE -- register input
+ a0 <= reg_a0;
+ b0 <= reg_b0;
+ a1 <= reg_a1;
+ b1 <= reg_b1;
+ END GENERATE;
+
+ ------------------------------------------------------------------------------
+ -- Products
+ ------------------------------------------------------------------------------
+
+ nxt_prod0 <= a0 * b0;
+ nxt_prod1 <= a1 * b1;
+
+ no_product_reg : IF g_pipeline_product=0 GENERATE -- wired
+ prod0 <= nxt_prod0;
+ prod1 <= nxt_prod1;
+ END GENERATE;
+ gen_product_reg : IF g_pipeline_product>0 GENERATE -- register
+ prod0 <= reg_prod0;
+ prod1 <= reg_prod1;
+ END GENERATE;
+
+ ------------------------------------------------------------------------------
+ -- Sum
+ ------------------------------------------------------------------------------
+ gen_add : IF g_add_sub = "ADD" GENERATE
+ nxt_sum <= RESIZE_NUM(prod0, c_sum_w) + prod1;
+ END GENERATE;
+ gen_sub : IF g_add_sub = "SUB" GENERATE
+ nxt_sum <= RESIZE_NUM(prod0, c_sum_w) - prod1;
+ END GENERATE;
+
+ no_adder_reg : IF g_pipeline_adder=0 GENERATE -- wired
+ sum <= nxt_sum;
+ END GENERATE;
+ gen_adder_reg : IF g_pipeline_adder>0 GENERATE -- register
+ sum <= reg_sum;
+ END GENERATE;
+
+
+ ------------------------------------------------------------------------------
+ -- Result sum after optional rounding
+ ------------------------------------------------------------------------------
+
+ nxt_result <= RESIZE_NUM(sum, g_res_w);
+
+ no_result_reg : IF g_pipeline_output=0 GENERATE -- wired
+ result <= nxt_result;
+ END GENERATE;
+ gen_result_reg : IF g_pipeline_output>0 GENERATE -- register
+ result <= reg_result;
+ END GENERATE;
+
+ res <= STD_LOGIC_VECTOR(result);
+
+END str;
diff --git a/libraries/technology/ip_arria10_e2sg/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/mult_add4/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..53afb110624ab2fb326243e7a2feec2315811a09
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/mult_add4/compile_ip.tcl
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_mult_add4/sim"
+
+vmap ip_arria10_e2sg_mult_add4 ./work/
+vmap altera_mult_add_180 ./work/
+
+
+ vcom "$IP_DIR/../altera_mult_add_180/sim/ip_arria10_e2sg_mult_add4_altera_mult_add_180_o5e3uui.vhd" -work altera_mult_add_180
+ vcom "$IP_DIR/ip_arria10_e2sg_mult_add4.vhd" -work ip_arria10_e2sg_mult_add4
diff --git a/libraries/technology/ip_arria10_e2sg/mult_add4/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/mult_add4/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..e8b3a294ca7e43ede41bc70fbf3690ce96ec4690
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/mult_add4/hdllib.cfg
@@ -0,0 +1,21 @@
+hdl_lib_name = ip_arria10_e2sg_mult_add4
+hdl_library_clause_name = ip_arria10_e2sg_mult_add4_lib
+hdl_lib_uses_synth = technology common
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+ ip_arria10_e2sg_mult_add4_rtl.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_mult_add4.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/mult_add4/ip_arria10_e2sg_mult_add4.qsys b/libraries/technology/ip_arria10_e2sg/mult_add4/ip_arria10_e2sg_mult_add4.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..77fd3072a015667b6ab3ce865976eb41b1322b78
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/mult_add4/ip_arria10_e2sg_mult_add4.qsys
@@ -0,0 +1,212 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_mult_add4">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element mult_add_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="aclr0" internal="mult_add_0.aclr0" type="reset" dir="end">
+ <port name="aclr0" internal="aclr0" />
+ </interface>
+ <interface name="clock0" internal="mult_add_0.clock0" type="clock" dir="end">
+ <port name="clock0" internal="clock0" />
+ </interface>
+ <interface name="dataa_0" internal="mult_add_0.dataa_0" type="conduit" dir="end">
+ <port name="dataa_0" internal="dataa_0" />
+ </interface>
+ <interface name="dataa_1" internal="mult_add_0.dataa_1" type="conduit" dir="end">
+ <port name="dataa_1" internal="dataa_1" />
+ </interface>
+ <interface name="dataa_2" internal="mult_add_0.dataa_2" type="conduit" dir="end">
+ <port name="dataa_2" internal="dataa_2" />
+ </interface>
+ <interface name="dataa_3" internal="mult_add_0.dataa_3" type="conduit" dir="end">
+ <port name="dataa_3" internal="dataa_3" />
+ </interface>
+ <interface name="datab_0" internal="mult_add_0.datab_0" type="conduit" dir="end">
+ <port name="datab_0" internal="datab_0" />
+ </interface>
+ <interface name="datab_1" internal="mult_add_0.datab_1" type="conduit" dir="end">
+ <port name="datab_1" internal="datab_1" />
+ </interface>
+ <interface name="datab_2" internal="mult_add_0.datab_2" type="conduit" dir="end">
+ <port name="datab_2" internal="datab_2" />
+ </interface>
+ <interface name="datab_3" internal="mult_add_0.datab_3" type="conduit" dir="end">
+ <port name="datab_3" internal="datab_3" />
+ </interface>
+ <interface name="datac_0" internal="mult_add_0.datac_0" />
+ <interface name="datac_1" internal="mult_add_0.datac_1" />
+ <interface name="datac_2" internal="mult_add_0.datac_2" />
+ <interface name="datac_3" internal="mult_add_0.datac_3" />
+ <interface name="ena0" internal="mult_add_0.ena0" type="conduit" dir="end">
+ <port name="ena0" internal="ena0" />
+ </interface>
+ <interface name="result" internal="mult_add_0.result" type="conduit" dir="end">
+ <port name="result" internal="result" />
+ </interface>
+ <module
+ name="mult_add_0"
+ kind="altera_mult_add"
+ version="19.1.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="accum_direction" value="ADD" />
+ <parameter name="accumulator" value="NO" />
+ <parameter name="chainout_adder" value="NO" />
+ <parameter name="chainout_adder_direction" value="ADD" />
+ <parameter name="coef0_0" value="0" />
+ <parameter name="coef0_1" value="0" />
+ <parameter name="coef0_2" value="0" />
+ <parameter name="coef0_3" value="0" />
+ <parameter name="coef0_4" value="0" />
+ <parameter name="coef0_5" value="0" />
+ <parameter name="coef0_6" value="0" />
+ <parameter name="coef0_7" value="0" />
+ <parameter name="coef1_0" value="0" />
+ <parameter name="coef1_1" value="0" />
+ <parameter name="coef1_2" value="0" />
+ <parameter name="coef1_3" value="0" />
+ <parameter name="coef1_4" value="0" />
+ <parameter name="coef1_5" value="0" />
+ <parameter name="coef1_6" value="0" />
+ <parameter name="coef1_7" value="0" />
+ <parameter name="coef2_0" value="0" />
+ <parameter name="coef2_1" value="0" />
+ <parameter name="coef2_2" value="0" />
+ <parameter name="coef2_3" value="0" />
+ <parameter name="coef2_4" value="0" />
+ <parameter name="coef2_5" value="0" />
+ <parameter name="coef2_6" value="0" />
+ <parameter name="coef2_7" value="0" />
+ <parameter name="coef3_0" value="0" />
+ <parameter name="coef3_1" value="0" />
+ <parameter name="coef3_2" value="0" />
+ <parameter name="coef3_3" value="0" />
+ <parameter name="coef3_4" value="0" />
+ <parameter name="coef3_5" value="0" />
+ <parameter name="coef3_6" value="0" />
+ <parameter name="coef3_7" value="0" />
+ <parameter name="gui_4th_asynchronous_clear" value="false" />
+ <parameter name="gui_accum_sload_register_aclr" value="NONE" />
+ <parameter name="gui_accum_sload_register_clock" value="CLOCK0" />
+ <parameter name="gui_accum_sload_register_sclr" value="NONE" />
+ <parameter name="gui_accumulate_port_select" value="0" />
+ <parameter name="gui_addnsub_multiplier_aclr1" value="NONE" />
+ <parameter name="gui_addnsub_multiplier_aclr3" value="NONE" />
+ <parameter name="gui_addnsub_multiplier_register1" value="false" />
+ <parameter name="gui_addnsub_multiplier_register1_clock" value="CLOCK0" />
+ <parameter name="gui_addnsub_multiplier_register3" value="false" />
+ <parameter name="gui_addnsub_multiplier_register3_clock" value="CLOCK0" />
+ <parameter name="gui_addnsub_multiplier_sclr1" value="NONE" />
+ <parameter name="gui_addnsub_multiplier_sclr3" value="NONE" />
+ <parameter name="gui_associated_clock_enable" value="true" />
+ <parameter name="gui_coef_register" value="false" />
+ <parameter name="gui_coef_register_aclr" value="NONE" />
+ <parameter name="gui_coef_register_clock" value="CLOCK0" />
+ <parameter name="gui_coef_register_sclr" value="NONE" />
+ <parameter name="gui_datac_input_register" value="false" />
+ <parameter name="gui_datac_input_register_aclr" value="ACLR0" />
+ <parameter name="gui_datac_input_register_clock" value="CLOCK0" />
+ <parameter name="gui_datac_input_register_sclr" value="NONE" />
+ <parameter name="gui_double_accum" value="false" />
+ <parameter name="gui_ena_preload_const" value="false" />
+ <parameter name="gui_input_latency_aclr" value="ACLR0" />
+ <parameter name="gui_input_latency_clock" value="CLOCK0" />
+ <parameter name="gui_input_latency_sclr" value="NONE" />
+ <parameter name="gui_input_register_a" value="false" />
+ <parameter name="gui_input_register_a_aclr" value="ACLR0" />
+ <parameter name="gui_input_register_a_clock" value="CLOCK0" />
+ <parameter name="gui_input_register_a_sclr" value="NONE" />
+ <parameter name="gui_input_register_b" value="false" />
+ <parameter name="gui_input_register_b_aclr" value="ACLR0" />
+ <parameter name="gui_input_register_b_clock" value="CLOCK0" />
+ <parameter name="gui_input_register_b_sclr" value="NONE" />
+ <parameter name="gui_multiplier1_direction" value="ADD" />
+ <parameter name="gui_multiplier3_direction" value="ADD" />
+ <parameter name="gui_multiplier_a_input" value="Multiplier input" />
+ <parameter name="gui_multiplier_b_input" value="Multiplier input" />
+ <parameter name="gui_multiplier_register" value="false" />
+ <parameter name="gui_multiplier_register_aclr" value="NONE" />
+ <parameter name="gui_multiplier_register_clock" value="CLOCK0" />
+ <parameter name="gui_multiplier_register_sclr" value="NONE" />
+ <parameter name="gui_output_register" value="false" />
+ <parameter name="gui_output_register_aclr" value="NONE" />
+ <parameter name="gui_output_register_clock" value="CLOCK0" />
+ <parameter name="gui_output_register_sclr" value="NONE" />
+ <parameter name="gui_pipelining" value="1" />
+ <parameter name="gui_preadder_direction" value="ADD" />
+ <parameter name="gui_register_signa" value="false" />
+ <parameter name="gui_register_signa_aclr" value="NONE" />
+ <parameter name="gui_register_signa_clock" value="CLOCK0" />
+ <parameter name="gui_register_signa_sclr" value="NONE" />
+ <parameter name="gui_register_signb" value="false" />
+ <parameter name="gui_register_signb_aclr" value="NONE" />
+ <parameter name="gui_register_signb_clock" value="CLOCK0" />
+ <parameter name="gui_register_signb_sclr" value="NONE" />
+ <parameter name="gui_representation_a" value="SIGNED" />
+ <parameter name="gui_representation_b" value="SIGNED" />
+ <parameter name="gui_scanouta_register" value="false" />
+ <parameter name="gui_scanouta_register_aclr" value="NONE" />
+ <parameter name="gui_scanouta_register_clock" value="CLOCK0" />
+ <parameter name="gui_scanouta_register_sclr" value="NONE" />
+ <parameter name="gui_systolic_delay" value="false" />
+ <parameter name="gui_systolic_delay_aclr" value="NONE" />
+ <parameter name="gui_systolic_delay_clock" value="CLOCK0" />
+ <parameter name="gui_systolic_delay_sclr" value="NONE" />
+ <parameter name="gui_use_subnadd" value="false" />
+ <parameter name="latency" value="3" />
+ <parameter name="loadconst_value" value="64" />
+ <parameter name="negate_aclr" value="NONE" />
+ <parameter name="negate_register" value="UNREGISTERED" />
+ <parameter name="negate_sclr" value="NONE" />
+ <parameter name="number_of_multipliers" value="4" />
+ <parameter name="port_negate" value="PORT_UNUSED" />
+ <parameter name="preadder_mode" value="SIMPLE" />
+ <parameter name="reg_autovec_sim" value="false" />
+ <parameter name="selected_device_family" value="Arria 10" />
+ <parameter name="width_a" value="18" />
+ <parameter name="width_b" value="18" />
+ <parameter name="width_c" value="16" />
+ <parameter name="width_coef" value="18" />
+ <parameter name="width_result" value="38" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/mult_add4/ip_arria10_e2sg_mult_add4_rtl.vhd b/libraries/technology/ip_arria10_e2sg/mult_add4/ip_arria10_e2sg_mult_add4_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..301d16b1c69e4502bff31e411595170a3fa21740
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/mult_add4/ip_arria10_e2sg_mult_add4_rtl.vhd
@@ -0,0 +1,272 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+
+-- Function:
+-- . res = (a0 * b0 +- a1 * b1) +- (a2 * b2 +- a3 * b3)
+
+ENTITY ip_arria10_e2sg_mult_add4_rtl IS
+ GENERIC (
+ g_in_a_w : POSITIVE;
+ g_in_b_w : POSITIVE;
+ g_res_w : POSITIVE; -- g_in_a_w + g_in_b_w + log2(4)
+ g_force_dsp : BOOLEAN := TRUE; -- when TRUE resize input width to >= 18
+ g_add_sub0 : STRING := "ADD"; -- or "SUB"
+ g_add_sub1 : STRING := "ADD"; -- or "SUB"
+ g_add_sub : STRING := "ADD"; -- or "SUB" only available with rtl architecture
+ g_nof_mult : INTEGER := 4; -- fixed
+ g_pipeline_input : NATURAL := 1; -- 0 or 1
+ g_pipeline_product : NATURAL := 0; -- 0 or 1
+ g_pipeline_adder : NATURAL := 1; -- 0 or 1, first sum
+ g_pipeline_output : NATURAL := 1 -- >= 0, second sum and optional rounding
+ );
+ PORT (
+ rst : IN STD_LOGIC := '0';
+ clk : IN STD_LOGIC;
+ clken : IN STD_LOGIC := '1';
+ in_a : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
+ in_b : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
+ res : OUT STD_LOGIC_VECTOR(g_res_w-1 DOWNTO 0)
+ );
+END ip_arria10_e2sg_mult_add4_rtl;
+
+ARCHITECTURE str OF ip_arria10_e2sg_mult_add4_rtl IS
+
+ -- Extra output pipelining is only needed when g_pipeline_output > 1
+ CONSTANT c_pipeline_output : NATURAL := sel_a_b(g_pipeline_output>0, g_pipeline_output-1, 0);
+
+ -- registers
+ SIGNAL reg_a0 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL reg_b0 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL reg_a1 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL reg_b1 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL reg_a2 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL reg_b2 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL reg_a3 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL reg_b3 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL reg_prod0 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL reg_prod1 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL reg_prod2 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL reg_prod3 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL reg_sum0 : SIGNED(g_in_a_w+g_in_b_w DOWNTO 0);
+ SIGNAL reg_sum1 : SIGNED(g_in_a_w+g_in_b_w DOWNTO 0);
+ SIGNAL reg_result : SIGNED(res'RANGE);
+
+ -- combinatorial
+ SIGNAL nxt_a0 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL nxt_b0 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL nxt_a1 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL nxt_b1 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL nxt_a2 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL nxt_b2 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL nxt_a3 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL nxt_b3 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL nxt_prod0 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL nxt_prod1 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL nxt_prod2 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL nxt_prod3 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL nxt_sum0 : SIGNED(g_in_a_w+g_in_b_w DOWNTO 0);
+ SIGNAL nxt_sum1 : SIGNED(g_in_a_w+g_in_b_w DOWNTO 0);
+ SIGNAL nxt_result : SIGNED(res'RANGE);
+
+ -- the active signals
+ SIGNAL a0 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL b0 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL a1 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL b1 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL a2 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL b2 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL a3 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL b3 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL prod0 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL prod1 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL prod2 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL prod3 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL sum0 : SIGNED(g_in_a_w+g_in_b_w DOWNTO 0);
+ SIGNAL sum1 : SIGNED(g_in_a_w+g_in_b_w DOWNTO 0);
+ SIGNAL sum : SIGNED(g_in_a_w+g_in_b_w+1 DOWNTO 0);
+ SIGNAL result : SIGNED(res'RANGE);
+
+BEGIN
+
+ ------------------------------------------------------------------------------
+ -- Registers
+ ------------------------------------------------------------------------------
+
+ -- Put all potential registers in a single process for optimal DSP inferrence
+ -- Use rst only if it is supported by the DSP primitive, else leave it at '0'
+ p_reg : PROCESS (rst, clk)
+ BEGIN
+ IF rising_edge(clk) THEN
+ IF rst='1' THEN
+ reg_a0 <= (OTHERS=>'0');
+ reg_b0 <= (OTHERS=>'0');
+ reg_a1 <= (OTHERS=>'0');
+ reg_b1 <= (OTHERS=>'0');
+ reg_a2 <= (OTHERS=>'0');
+ reg_b2 <= (OTHERS=>'0');
+ reg_a3 <= (OTHERS=>'0');
+ reg_b3 <= (OTHERS=>'0');
+ reg_prod0 <= (OTHERS=>'0');
+ reg_prod1 <= (OTHERS=>'0');
+ reg_prod2 <= (OTHERS=>'0');
+ reg_prod3 <= (OTHERS=>'0');
+ reg_sum0 <= (OTHERS=>'0');
+ reg_sum1 <= (OTHERS=>'0');
+ reg_result <= (OTHERS=>'0');
+ ELSIF clken='1' THEN
+ reg_a0 <= nxt_a0; -- inputs
+ reg_b0 <= nxt_b0;
+ reg_a1 <= nxt_a1;
+ reg_b1 <= nxt_b1;
+ reg_a2 <= nxt_a2;
+ reg_b2 <= nxt_b2;
+ reg_a3 <= nxt_a3;
+ reg_b3 <= nxt_b3;
+ reg_prod0 <= nxt_prod0; -- products
+ reg_prod1 <= nxt_prod1;
+ reg_prod2 <= nxt_prod2;
+ reg_prod3 <= nxt_prod3;
+ reg_sum0 <= nxt_sum0; -- first sum
+ reg_sum1 <= nxt_sum1;
+ reg_result <= nxt_result; -- result second sum after optional rounding
+ END IF;
+ END IF;
+ END PROCESS;
+
+ ------------------------------------------------------------------------------
+ -- Inputs
+ ------------------------------------------------------------------------------
+
+ nxt_a0 <= SIGNED(in_a( g_in_a_w-1 DOWNTO 0));
+ nxt_b0 <= SIGNED(in_b( g_in_b_w-1 DOWNTO 0));
+ nxt_a1 <= SIGNED(in_a(2*g_in_a_w-1 DOWNTO g_in_a_w));
+ nxt_b1 <= SIGNED(in_b(2*g_in_b_w-1 DOWNTO g_in_b_w));
+ nxt_a2 <= SIGNED(in_a(3*g_in_a_w-1 DOWNTO 2*g_in_a_w));
+ nxt_b2 <= SIGNED(in_b(3*g_in_b_w-1 DOWNTO 2*g_in_b_w));
+ nxt_a3 <= SIGNED(in_a(4*g_in_a_w-1 DOWNTO 3*g_in_a_w));
+ nxt_b3 <= SIGNED(in_b(4*g_in_b_w-1 DOWNTO 3*g_in_b_w));
+
+ no_input_reg : IF g_pipeline_input=0 GENERATE -- wired
+ a0 <= nxt_a0;
+ b0 <= nxt_b0;
+ a1 <= nxt_a1;
+ b1 <= nxt_b1;
+ a2 <= nxt_a2;
+ b2 <= nxt_b2;
+ a3 <= nxt_a3;
+ b3 <= nxt_b3;
+ END GENERATE;
+
+ gen_input_reg : IF g_pipeline_input>0 GENERATE -- register input
+ a0 <= reg_a0;
+ b0 <= reg_b0;
+ a1 <= reg_a1;
+ b1 <= reg_b1;
+ a2 <= reg_a2;
+ b2 <= reg_b2;
+ a3 <= reg_a3;
+ b3 <= reg_b3;
+ END GENERATE;
+
+ ------------------------------------------------------------------------------
+ -- Products
+ ------------------------------------------------------------------------------
+
+ nxt_prod0 <= a0 * b0;
+ nxt_prod1 <= a1 * b1;
+ nxt_prod2 <= a2 * b2;
+ nxt_prod3 <= a3 * b3;
+
+ no_product_reg : IF g_pipeline_product=0 GENERATE -- wired
+ prod0 <= nxt_prod0;
+ prod1 <= nxt_prod1;
+ prod2 <= nxt_prod2;
+ prod3 <= nxt_prod3;
+ END GENERATE;
+ gen_product_reg : IF g_pipeline_product>0 GENERATE -- register
+ prod0 <= reg_prod0;
+ prod1 <= reg_prod1;
+ prod2 <= reg_prod2;
+ prod3 <= reg_prod3;
+ END GENERATE;
+
+ ------------------------------------------------------------------------------
+ -- First sum
+ ------------------------------------------------------------------------------
+ gen_add0 : IF g_add_sub0 = "ADD" GENERATE
+ nxt_sum0 <= RESIZE_NUM(prod0, sum0'LENGTH) + prod1;
+ END GENERATE;
+ gen_sub0 : IF g_add_sub0 = "SUB" GENERATE
+ nxt_sum0 <= RESIZE_NUM(prod0, sum0'LENGTH) - prod1;
+ END GENERATE;
+
+ gen_add1 : IF g_add_sub1 = "ADD" GENERATE
+ nxt_sum1 <= RESIZE_NUM(prod2, sum1'LENGTH) + prod3;
+ END GENERATE;
+ gen_sub1 : IF g_add_sub1 = "SUB" GENERATE
+ nxt_sum1 <= RESIZE_NUM(prod2, sum1'LENGTH) - prod3;
+ END GENERATE;
+
+ -- Optinal first sum register
+ no_adder_reg : IF g_pipeline_adder=0 GENERATE -- wired
+ sum0 <= nxt_sum0;
+ sum1 <= nxt_sum1;
+ END GENERATE;
+ gen_adder_reg : IF g_pipeline_adder>0 GENERATE -- register
+ sum0 <= reg_sum0;
+ sum1 <= reg_sum1;
+ END GENERATE;
+
+
+ ------------------------------------------------------------------------------
+ -- Second sum
+ ------------------------------------------------------------------------------
+
+ -- No register for second sum, gets combined with result register
+ gen_add : IF g_add_sub = "ADD" GENERATE
+ sum <= RESIZE_NUM(sum0, sum'LENGTH) + sum1;
+ END GENERATE;
+ gen_sub : IF g_add_sub = "SUB" GENERATE
+ sum <= RESIZE_NUM(sum0, sum'LENGTH) - sum1;
+ END GENERATE;
+
+
+ ------------------------------------------------------------------------------
+ -- Result sum after optional rounding
+ ------------------------------------------------------------------------------
+
+ nxt_result <= RESIZE_NUM(sum, res'LENGTH);
+
+ no_result_reg : IF g_pipeline_output=0 GENERATE -- wired
+ result <= nxt_result;
+ END GENERATE;
+ gen_result_reg : IF g_pipeline_output>0 GENERATE -- register
+ result <= reg_result;
+ END GENERATE;
+
+ res <= STD_LOGIC_VECTOR(result);
+
+END str;
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..77ae9c3528d82b79d00f43e19726275fedb5a807
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r/sim"
+
+
+ vcom "$IP_DIR/ip_arria10_e2sg_phy_10gbase_r.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..1af09e1d6aea8af29a176a0daba0b137329c05b1
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_phy_10gbase_r
+hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r/ip_arria10_e2sg_phy_10gbase_r.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_phy_10gbase_r.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/ip_arria10_e2sg_phy_10gbase_r.qsys b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/ip_arria10_e2sg_phy_10gbase_r.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..6f53174fb2e76821c8a15f2b2a9ee9dc9c237226
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/ip_arria10_e2sg_phy_10gbase_r.qsys
@@ -0,0 +1,604 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_phy_10gbase_r">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element xcvr_native_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="reconfig_avmm" internal="xcvr_native_a10_0.reconfig_avmm" />
+ <interface name="reconfig_clk" internal="xcvr_native_a10_0.reconfig_clk" />
+ <interface name="reconfig_reset" internal="xcvr_native_a10_0.reconfig_reset" />
+ <interface
+ name="rx_analogreset"
+ internal="xcvr_native_a10_0.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="xcvr_native_a10_0.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_cdr_refclk0"
+ internal="xcvr_native_a10_0.rx_cdr_refclk0"
+ type="conduit"
+ dir="end">
+ <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
+ </interface>
+ <interface
+ name="rx_clkout"
+ internal="xcvr_native_a10_0.rx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="rx_clkout" internal="rx_clkout" />
+ </interface>
+ <interface
+ name="rx_control"
+ internal="xcvr_native_a10_0.rx_control"
+ type="conduit"
+ dir="end">
+ <port name="rx_control" internal="rx_control" />
+ </interface>
+ <interface
+ name="rx_coreclkin"
+ internal="xcvr_native_a10_0.rx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="rx_coreclkin" internal="rx_coreclkin" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="xcvr_native_a10_0.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_enh_blk_lock"
+ internal="xcvr_native_a10_0.rx_enh_blk_lock"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
+ </interface>
+ <interface
+ name="rx_enh_data_valid"
+ internal="xcvr_native_a10_0.rx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_del"
+ internal="xcvr_native_a10_0.rx_enh_fifo_del"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_del" internal="rx_enh_fifo_del" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.rx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_empty" internal="rx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_full"
+ internal="xcvr_native_a10_0.rx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_full" internal="rx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_insert"
+ internal="xcvr_native_a10_0.rx_enh_fifo_insert"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_insert" internal="rx_enh_fifo_insert" />
+ </interface>
+ <interface
+ name="rx_enh_highber"
+ internal="xcvr_native_a10_0.rx_enh_highber"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_highber" internal="rx_enh_highber" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="xcvr_native_a10_0.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_is_lockedtoref"
+ internal="xcvr_native_a10_0.rx_is_lockedtoref"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtoref" internal="rx_is_lockedtoref" />
+ </interface>
+ <interface
+ name="rx_parallel_data"
+ internal="xcvr_native_a10_0.rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_parallel_data" internal="rx_parallel_data" />
+ </interface>
+ <interface
+ name="rx_prbs_done"
+ internal="xcvr_native_a10_0.rx_prbs_done"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_done" internal="rx_prbs_done" />
+ </interface>
+ <interface
+ name="rx_prbs_err"
+ internal="xcvr_native_a10_0.rx_prbs_err"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err" internal="rx_prbs_err" />
+ </interface>
+ <interface
+ name="rx_prbs_err_clr"
+ internal="xcvr_native_a10_0.rx_prbs_err_clr"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err_clr" internal="rx_prbs_err_clr" />
+ </interface>
+ <interface
+ name="rx_serial_data"
+ internal="xcvr_native_a10_0.rx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_serial_data" internal="rx_serial_data" />
+ </interface>
+ <interface
+ name="rx_seriallpbken"
+ internal="xcvr_native_a10_0.rx_seriallpbken"
+ type="conduit"
+ dir="end">
+ <port name="rx_seriallpbken" internal="rx_seriallpbken" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="xcvr_native_a10_0.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="xcvr_native_a10_0.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_clkout"
+ internal="xcvr_native_a10_0.tx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="tx_clkout" internal="tx_clkout" />
+ </interface>
+ <interface
+ name="tx_control"
+ internal="xcvr_native_a10_0.tx_control"
+ type="conduit"
+ dir="end">
+ <port name="tx_control" internal="tx_control" />
+ </interface>
+ <interface
+ name="tx_coreclkin"
+ internal="xcvr_native_a10_0.tx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="tx_coreclkin" internal="tx_coreclkin" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="xcvr_native_a10_0.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_enh_data_valid"
+ internal="xcvr_native_a10_0.tx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_empty" internal="tx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_full"
+ internal="xcvr_native_a10_0.tx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_full" internal="tx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pempty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pempty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pempty" internal="tx_enh_fifo_pempty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pfull"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pfull"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pfull" internal="tx_enh_fifo_pfull" />
+ </interface>
+ <interface
+ name="tx_err_ins"
+ internal="xcvr_native_a10_0.tx_err_ins"
+ type="conduit"
+ dir="end">
+ <port name="tx_err_ins" internal="tx_err_ins" />
+ </interface>
+ <interface
+ name="tx_parallel_data"
+ internal="xcvr_native_a10_0.tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_parallel_data" internal="tx_parallel_data" />
+ </interface>
+ <interface name="tx_pma_clkout" internal="xcvr_native_a10_0.tx_pma_clkout" />
+ <interface
+ name="tx_pma_div_clkout"
+ internal="xcvr_native_a10_0.tx_pma_div_clkout" />
+ <interface
+ name="tx_serial_clk0"
+ internal="xcvr_native_a10_0.tx_serial_clk0"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_clk0" internal="tx_serial_clk0" />
+ </interface>
+ <interface
+ name="tx_serial_data"
+ internal="xcvr_native_a10_0.tx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_data" internal="tx_serial_data" />
+ </interface>
+ <interface
+ name="unused_rx_control"
+ internal="xcvr_native_a10_0.unused_rx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_control" internal="unused_rx_control" />
+ </interface>
+ <interface
+ name="unused_rx_parallel_data"
+ internal="xcvr_native_a10_0.unused_rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
+ </interface>
+ <interface
+ name="unused_tx_control"
+ internal="xcvr_native_a10_0.unused_tx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_control" internal="unused_tx_control" />
+ </interface>
+ <interface
+ name="unused_tx_parallel_data"
+ internal="xcvr_native_a10_0.unused_tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
+ </interface>
+ <module
+ name="xcvr_native_a10_0"
+ kind="altera_xcvr_native_a10"
+ version="19.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="anlg_enable_rx_default_ovr" value="0" />
+ <parameter name="anlg_enable_tx_default_ovr" value="0" />
+ <parameter name="anlg_link" value="sr" />
+ <parameter name="anlg_rx_adp_ctle_acgain_4s">radp_ctle_acgain_4s_1</parameter>
+ <parameter name="anlg_rx_adp_ctle_eqz_1s_sel">radp_ctle_eqz_1s_sel_3</parameter>
+ <parameter name="anlg_rx_adp_dfe_fxtap1" value="radp_dfe_fxtap1_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap10" value="radp_dfe_fxtap10_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap11" value="radp_dfe_fxtap11_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap2" value="radp_dfe_fxtap2_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap3" value="radp_dfe_fxtap3_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap4" value="radp_dfe_fxtap4_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap5" value="radp_dfe_fxtap5_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap6" value="radp_dfe_fxtap6_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap7" value="radp_dfe_fxtap7_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap8" value="radp_dfe_fxtap8_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap9" value="radp_dfe_fxtap9_0" />
+ <parameter name="anlg_rx_adp_vga_sel" value="radp_vga_sel_2" />
+ <parameter name="anlg_rx_eq_dc_gain_trim" value="stg2_gain7" />
+ <parameter name="anlg_rx_one_stage_enable" value="s1_mode" />
+ <parameter name="anlg_rx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_analog_mode" value="user_custom" />
+ <parameter name="anlg_tx_compensation_en" value="enable" />
+ <parameter name="anlg_tx_pre_emp_sign_1st_post_tap" value="fir_post_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_2nd_post_tap" value="fir_post_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_1t" value="fir_pre_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_2t" value="fir_pre_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_1st_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_2nd_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_1t" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_2t" value="0" />
+ <parameter name="anlg_tx_slew_rate_ctrl" value="slew_r7" />
+ <parameter name="anlg_tx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_vod_output_swing_ctrl" value="0" />
+ <parameter name="anlg_voltage" value="1_1V" />
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="bonded_mode" value="not_bonded" />
+ <parameter name="cdr_refclk_cnt" value="1" />
+ <parameter name="cdr_refclk_select" value="0" />
+ <parameter name="channels" value="1" />
+ <parameter name="design_environment" value="NATIVE" />
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="disable_continuous_dfe" value="false" />
+ <parameter name="duplex_mode" value="duplex" />
+ <parameter name="enable_analog_settings" value="0" />
+ <parameter name="enable_hard_reset" value="0" />
+ <parameter name="enable_hip" value="0" />
+ <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="enable_pcie_data_mask_option" value="0" />
+ <parameter name="enable_pcie_dfe_ip" value="false" />
+ <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
+ <parameter name="enable_port_pipe_rx_polarity" value="0" />
+ <parameter name="enable_port_rx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enable_port_rx_enh_blk_lock" value="1" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count_c10" value="0" />
+ <parameter name="enable_port_rx_enh_crc32_err" value="0" />
+ <parameter name="enable_port_rx_enh_data_valid" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_del" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_insert" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
+ <parameter name="enable_port_rx_enh_frame" value="0" />
+ <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_rx_enh_frame_lock" value="0" />
+ <parameter name="enable_port_rx_enh_highber" value="1" />
+ <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
+ <parameter name="enable_port_rx_is_lockedtodata" value="1" />
+ <parameter name="enable_port_rx_is_lockedtoref" value="1" />
+ <parameter name="enable_port_rx_pma_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_clkslip" value="0" />
+ <parameter name="enable_port_rx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_rx_polinv" value="0" />
+ <parameter name="enable_port_rx_seriallpbken" value="1" />
+ <parameter name="enable_port_rx_seriallpbken_tx" value="1" />
+ <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
+ <parameter name="enable_port_rx_std_bitslip" value="0" />
+ <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_rx_std_byterev_ena" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
+ <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_tx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_tx_enh_bitslip" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pempty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pfull" value="1" />
+ <parameter name="enable_port_tx_enh_frame" value="0" />
+ <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
+ <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_tx_pma_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_elecidle" value="0" />
+ <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_tx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_tx_pma_rxfound" value="0" />
+ <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
+ <parameter name="enable_port_tx_polinv" value="0" />
+ <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
+ <parameter name="enable_ports_adaptation" value="0" />
+ <parameter name="enable_ports_pipe_g3_analog" value="0" />
+ <parameter name="enable_ports_pipe_hclk" value="0" />
+ <parameter name="enable_ports_pipe_rx_elecidle" value="0" />
+ <parameter name="enable_ports_pipe_sw" value="0" />
+ <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
+ <parameter name="enable_ports_rx_manual_ppm" value="0" />
+ <parameter name="enable_ports_rx_prbs" value="1" />
+ <parameter name="enable_simple_interface" value="1" />
+ <parameter name="enable_skp_ports" value="0" />
+ <parameter name="enable_split_interface" value="0" />
+ <parameter name="enable_transparent_pcs" value="0" />
+ <parameter name="enable_upi_pipeline_options" value="0" />
+ <parameter name="enh_low_latency_enable" value="0" />
+ <parameter name="enh_pcs_pma_width" value="32" />
+ <parameter name="enh_pld_pcs_width" value="66" />
+ <parameter name="enh_rx_64b66b_enable" value="1" />
+ <parameter name="enh_rx_bitslip_enable" value="0" />
+ <parameter name="enh_rx_blksync_enable" value="1" />
+ <parameter name="enh_rx_crcchk_enable" value="0" />
+ <parameter name="enh_rx_descram_enable" value="1" />
+ <parameter name="enh_rx_dispchk_enable" value="0" />
+ <parameter name="enh_rx_frmsync_enable" value="0" />
+ <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
+ <parameter name="enh_rx_krfec_err_mark_enable" value="0" />
+ <parameter name="enh_rx_krfec_err_mark_type" value="10G" />
+ <parameter name="enh_rx_polinv_enable" value="0" />
+ <parameter name="enh_rxfifo_align_del" value="0" />
+ <parameter name="enh_rxfifo_control_del" value="0" />
+ <parameter name="enh_rxfifo_mode" value="10GBase-R" />
+ <parameter name="enh_rxfifo_pempty" value="2" />
+ <parameter name="enh_rxfifo_pfull" value="23" />
+ <parameter name="enh_rxtxfifo_double_width" value="0" />
+ <parameter name="enh_tx_64b66b_enable" value="1" />
+ <parameter name="enh_tx_bitslip_enable" value="0" />
+ <parameter name="enh_tx_crcerr_enable" value="0" />
+ <parameter name="enh_tx_crcgen_enable" value="0" />
+ <parameter name="enh_tx_dispgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_burst_enable" value="0" />
+ <parameter name="enh_tx_frmgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
+ <parameter name="enh_tx_krfec_burst_err_enable" value="0" />
+ <parameter name="enh_tx_krfec_burst_err_len" value="1" />
+ <parameter name="enh_tx_polinv_enable" value="0" />
+ <parameter name="enh_tx_randomdispbit_enable" value="0" />
+ <parameter name="enh_tx_scram_enable" value="1" />
+ <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_tx_sh_err" value="0" />
+ <parameter name="enh_txfifo_mode" value="Phase compensation" />
+ <parameter name="enh_txfifo_pempty" value="2" />
+ <parameter name="enh_txfifo_pfull" value="11" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="number_physical_bonding_clocks" value="1" />
+ <parameter name="pcie_rate_match" value="Bypass" />
+ <parameter name="pcs_direct_width" value="8" />
+ <parameter name="pcs_tx_delay1_ctrl" value="delay1_path0" />
+ <parameter name="pcs_tx_delay1_data_sel" value="one_ff_delay" />
+ <parameter name="pcs_tx_delay2_ctrl" value="delay2_path0" />
+ <parameter name="pll_select" value="0" />
+ <parameter name="plls" value="1" />
+ <parameter name="pma_mode" value="basic" />
+ <parameter name="protocol_mode" value="teng_baser_mode" />
+ <parameter name="rcfg_enable" value="0" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="0" />
+ <parameter name="rcfg_iface_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="0" />
+ <parameter name="rcfg_mif_file_enable" value="0" />
+ <parameter name="rcfg_multi_enable" value="0" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_data0" value="" />
+ <parameter name="rcfg_profile_data1" value="" />
+ <parameter name="rcfg_profile_data2" value="" />
+ <parameter name="rcfg_profile_data3" value="" />
+ <parameter name="rcfg_profile_data4" value="" />
+ <parameter name="rcfg_profile_data5" value="" />
+ <parameter name="rcfg_profile_data6" value="" />
+ <parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_shared" value="0" />
+ <parameter name="rcfg_sv_file_enable" value="0" />
+ <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
+ <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
+ <parameter name="rx_pma_dfe_fixed_taps" value="3" />
+ <parameter name="rx_pma_div_clkout_divider" value="0" />
+ <parameter name="rx_ppm_detect_threshold" value="1000" />
+ <parameter name="set_capability_reg_enable" value="0" />
+ <parameter name="set_cdr_refclk_freq" value="644.531250" />
+ <parameter name="set_csr_soft_logic_enable" value="0" />
+ <parameter name="set_data_rate" value="10312.5" />
+ <parameter name="set_disconnect_analog_resets" value="0" />
+ <parameter name="set_embedded_debug_enable" value="0" />
+ <parameter name="set_enable_calibration" value="0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_odi_soft_logic_enable" value="0" />
+ <parameter name="set_pcs_bonding_master" value="Auto" />
+ <parameter name="set_prbs_soft_logic_enable" value="0" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="sim_reduced_counters" value="false" />
+ <parameter name="std_data_mask_count_multi" value="0" />
+ <parameter name="std_low_latency_bypass_enable" value="0" />
+ <parameter name="std_pcs_pma_width" value="10" />
+ <parameter name="std_rx_8b10b_enable" value="0" />
+ <parameter name="std_rx_bitrev_enable" value="0" />
+ <parameter name="std_rx_byte_deser_mode" value="Disabled" />
+ <parameter name="std_rx_byterev_enable" value="0" />
+ <parameter name="std_rx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_rx_polinv_enable" value="0" />
+ <parameter name="std_rx_rmfifo_mode" value="disabled" />
+ <parameter name="std_rx_rmfifo_pattern_n" value="0" />
+ <parameter name="std_rx_rmfifo_pattern_p" value="0" />
+ <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
+ <parameter name="std_rx_word_aligner_mode" value="bitslip" />
+ <parameter name="std_rx_word_aligner_pattern" value="0" />
+ <parameter name="std_rx_word_aligner_pattern_len" value="7" />
+ <parameter name="std_rx_word_aligner_renumber" value="3" />
+ <parameter name="std_rx_word_aligner_rgnumber" value="3" />
+ <parameter name="std_rx_word_aligner_rknumber" value="3" />
+ <parameter name="std_rx_word_aligner_rvnumber" value="0" />
+ <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
+ <parameter name="std_tx_8b10b_enable" value="0" />
+ <parameter name="std_tx_bitrev_enable" value="0" />
+ <parameter name="std_tx_bitslip_enable" value="0" />
+ <parameter name="std_tx_byte_ser_mode" value="Disabled" />
+ <parameter name="std_tx_byterev_enable" value="0" />
+ <parameter name="std_tx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="tx_pma_clk_div" value="1" />
+ <parameter name="tx_pma_div_clkout_divider" value="33" />
+ <parameter name="validation_rule_select" value="" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e3603311ebdf462074c795637f193835cc925a10
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_12/sim"
+
+
+ vcom "$IP_DIR/ip_arria10_e2sg_phy_10gbase_r_12.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..629ab064772bfb78ad731f0f4ae066e8545d5fa5
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_phy_10gbase_r_12
+hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_12_altera_xcvr_native_a10_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_12/ip_arria10_e2sg_phy_10gbase_r_12.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_phy_10gbase_r_12.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/ip_arria10_e2sg_phy_10gbase_r_12.qsys b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/ip_arria10_e2sg_phy_10gbase_r_12.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..86f7cea5e91563f3508c9405f6c9c61a95b48a45
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/ip_arria10_e2sg_phy_10gbase_r_12.qsys
@@ -0,0 +1,627 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_phy_10gbase_r_12">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element xcvr_native_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="reconfig_avmm"
+ internal="xcvr_native_a10_0.reconfig_avmm"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_address" internal="reconfig_address" />
+ <port name="reconfig_read" internal="reconfig_read" />
+ <port name="reconfig_readdata" internal="reconfig_readdata" />
+ <port name="reconfig_waitrequest" internal="reconfig_waitrequest" />
+ <port name="reconfig_write" internal="reconfig_write" />
+ <port name="reconfig_writedata" internal="reconfig_writedata" />
+ </interface>
+ <interface
+ name="reconfig_clk"
+ internal="xcvr_native_a10_0.reconfig_clk"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_clk" internal="reconfig_clk" />
+ </interface>
+ <interface
+ name="reconfig_reset"
+ internal="xcvr_native_a10_0.reconfig_reset"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_reset" internal="reconfig_reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="xcvr_native_a10_0.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="xcvr_native_a10_0.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_cdr_refclk0"
+ internal="xcvr_native_a10_0.rx_cdr_refclk0"
+ type="conduit"
+ dir="end">
+ <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
+ </interface>
+ <interface
+ name="rx_clkout"
+ internal="xcvr_native_a10_0.rx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="rx_clkout" internal="rx_clkout" />
+ </interface>
+ <interface
+ name="rx_control"
+ internal="xcvr_native_a10_0.rx_control"
+ type="conduit"
+ dir="end">
+ <port name="rx_control" internal="rx_control" />
+ </interface>
+ <interface
+ name="rx_coreclkin"
+ internal="xcvr_native_a10_0.rx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="rx_coreclkin" internal="rx_coreclkin" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="xcvr_native_a10_0.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_enh_blk_lock"
+ internal="xcvr_native_a10_0.rx_enh_blk_lock"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
+ </interface>
+ <interface
+ name="rx_enh_data_valid"
+ internal="xcvr_native_a10_0.rx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_del"
+ internal="xcvr_native_a10_0.rx_enh_fifo_del"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_del" internal="rx_enh_fifo_del" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.rx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_empty" internal="rx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_full"
+ internal="xcvr_native_a10_0.rx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_full" internal="rx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_insert"
+ internal="xcvr_native_a10_0.rx_enh_fifo_insert"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_insert" internal="rx_enh_fifo_insert" />
+ </interface>
+ <interface
+ name="rx_enh_highber"
+ internal="xcvr_native_a10_0.rx_enh_highber"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_highber" internal="rx_enh_highber" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="xcvr_native_a10_0.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_is_lockedtoref"
+ internal="xcvr_native_a10_0.rx_is_lockedtoref"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtoref" internal="rx_is_lockedtoref" />
+ </interface>
+ <interface
+ name="rx_parallel_data"
+ internal="xcvr_native_a10_0.rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_parallel_data" internal="rx_parallel_data" />
+ </interface>
+ <interface
+ name="rx_prbs_done"
+ internal="xcvr_native_a10_0.rx_prbs_done"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_done" internal="rx_prbs_done" />
+ </interface>
+ <interface
+ name="rx_prbs_err"
+ internal="xcvr_native_a10_0.rx_prbs_err"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err" internal="rx_prbs_err" />
+ </interface>
+ <interface
+ name="rx_prbs_err_clr"
+ internal="xcvr_native_a10_0.rx_prbs_err_clr"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err_clr" internal="rx_prbs_err_clr" />
+ </interface>
+ <interface
+ name="rx_serial_data"
+ internal="xcvr_native_a10_0.rx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_serial_data" internal="rx_serial_data" />
+ </interface>
+ <interface
+ name="rx_seriallpbken"
+ internal="xcvr_native_a10_0.rx_seriallpbken"
+ type="conduit"
+ dir="end">
+ <port name="rx_seriallpbken" internal="rx_seriallpbken" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="xcvr_native_a10_0.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="xcvr_native_a10_0.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_clkout"
+ internal="xcvr_native_a10_0.tx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="tx_clkout" internal="tx_clkout" />
+ </interface>
+ <interface
+ name="tx_control"
+ internal="xcvr_native_a10_0.tx_control"
+ type="conduit"
+ dir="end">
+ <port name="tx_control" internal="tx_control" />
+ </interface>
+ <interface
+ name="tx_coreclkin"
+ internal="xcvr_native_a10_0.tx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="tx_coreclkin" internal="tx_coreclkin" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="xcvr_native_a10_0.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_enh_data_valid"
+ internal="xcvr_native_a10_0.tx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_empty" internal="tx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_full"
+ internal="xcvr_native_a10_0.tx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_full" internal="tx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pempty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pempty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pempty" internal="tx_enh_fifo_pempty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pfull"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pfull"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pfull" internal="tx_enh_fifo_pfull" />
+ </interface>
+ <interface
+ name="tx_err_ins"
+ internal="xcvr_native_a10_0.tx_err_ins"
+ type="conduit"
+ dir="end">
+ <port name="tx_err_ins" internal="tx_err_ins" />
+ </interface>
+ <interface
+ name="tx_parallel_data"
+ internal="xcvr_native_a10_0.tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_parallel_data" internal="tx_parallel_data" />
+ </interface>
+ <interface name="tx_pma_clkout" internal="xcvr_native_a10_0.tx_pma_clkout" />
+ <interface
+ name="tx_pma_div_clkout"
+ internal="xcvr_native_a10_0.tx_pma_div_clkout" />
+ <interface
+ name="tx_serial_clk0"
+ internal="xcvr_native_a10_0.tx_serial_clk0"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_clk0" internal="tx_serial_clk0" />
+ </interface>
+ <interface
+ name="tx_serial_data"
+ internal="xcvr_native_a10_0.tx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_data" internal="tx_serial_data" />
+ </interface>
+ <interface
+ name="unused_rx_control"
+ internal="xcvr_native_a10_0.unused_rx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_control" internal="unused_rx_control" />
+ </interface>
+ <interface
+ name="unused_rx_parallel_data"
+ internal="xcvr_native_a10_0.unused_rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
+ </interface>
+ <interface
+ name="unused_tx_control"
+ internal="xcvr_native_a10_0.unused_tx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_control" internal="unused_tx_control" />
+ </interface>
+ <interface
+ name="unused_tx_parallel_data"
+ internal="xcvr_native_a10_0.unused_tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
+ </interface>
+ <module
+ name="xcvr_native_a10_0"
+ kind="altera_xcvr_native_a10"
+ version="19.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="anlg_enable_rx_default_ovr" value="0" />
+ <parameter name="anlg_enable_tx_default_ovr" value="0" />
+ <parameter name="anlg_link" value="sr" />
+ <parameter name="anlg_rx_adp_ctle_acgain_4s">radp_ctle_acgain_4s_1</parameter>
+ <parameter name="anlg_rx_adp_ctle_eqz_1s_sel">radp_ctle_eqz_1s_sel_3</parameter>
+ <parameter name="anlg_rx_adp_dfe_fxtap1" value="radp_dfe_fxtap1_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap10" value="radp_dfe_fxtap10_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap11" value="radp_dfe_fxtap11_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap2" value="radp_dfe_fxtap2_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap3" value="radp_dfe_fxtap3_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap4" value="radp_dfe_fxtap4_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap5" value="radp_dfe_fxtap5_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap6" value="radp_dfe_fxtap6_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap7" value="radp_dfe_fxtap7_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap8" value="radp_dfe_fxtap8_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap9" value="radp_dfe_fxtap9_0" />
+ <parameter name="anlg_rx_adp_vga_sel" value="radp_vga_sel_2" />
+ <parameter name="anlg_rx_eq_dc_gain_trim" value="stg2_gain7" />
+ <parameter name="anlg_rx_one_stage_enable" value="s1_mode" />
+ <parameter name="anlg_rx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_analog_mode" value="user_custom" />
+ <parameter name="anlg_tx_compensation_en" value="enable" />
+ <parameter name="anlg_tx_pre_emp_sign_1st_post_tap" value="fir_post_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_2nd_post_tap" value="fir_post_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_1t" value="fir_pre_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_2t" value="fir_pre_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_1st_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_2nd_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_1t" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_2t" value="0" />
+ <parameter name="anlg_tx_slew_rate_ctrl" value="slew_r7" />
+ <parameter name="anlg_tx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_vod_output_swing_ctrl" value="0" />
+ <parameter name="anlg_voltage" value="1_1V" />
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="bonded_mode" value="not_bonded" />
+ <parameter name="cdr_refclk_cnt" value="1" />
+ <parameter name="cdr_refclk_select" value="0" />
+ <parameter name="channels" value="12" />
+ <parameter name="design_environment" value="NATIVE" />
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="disable_continuous_dfe" value="false" />
+ <parameter name="duplex_mode" value="duplex" />
+ <parameter name="enable_analog_settings" value="0" />
+ <parameter name="enable_hard_reset" value="0" />
+ <parameter name="enable_hip" value="0" />
+ <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="enable_pcie_data_mask_option" value="0" />
+ <parameter name="enable_pcie_dfe_ip" value="false" />
+ <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
+ <parameter name="enable_port_pipe_rx_polarity" value="0" />
+ <parameter name="enable_port_rx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enable_port_rx_enh_blk_lock" value="1" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count_c10" value="0" />
+ <parameter name="enable_port_rx_enh_crc32_err" value="0" />
+ <parameter name="enable_port_rx_enh_data_valid" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_del" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_insert" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
+ <parameter name="enable_port_rx_enh_frame" value="0" />
+ <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_rx_enh_frame_lock" value="0" />
+ <parameter name="enable_port_rx_enh_highber" value="1" />
+ <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
+ <parameter name="enable_port_rx_is_lockedtodata" value="1" />
+ <parameter name="enable_port_rx_is_lockedtoref" value="1" />
+ <parameter name="enable_port_rx_pma_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_clkslip" value="0" />
+ <parameter name="enable_port_rx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_rx_polinv" value="0" />
+ <parameter name="enable_port_rx_seriallpbken" value="1" />
+ <parameter name="enable_port_rx_seriallpbken_tx" value="1" />
+ <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
+ <parameter name="enable_port_rx_std_bitslip" value="0" />
+ <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_rx_std_byterev_ena" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
+ <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_tx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_tx_enh_bitslip" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pempty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pfull" value="1" />
+ <parameter name="enable_port_tx_enh_frame" value="0" />
+ <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
+ <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_tx_pma_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_elecidle" value="0" />
+ <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_tx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_tx_pma_rxfound" value="0" />
+ <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
+ <parameter name="enable_port_tx_polinv" value="0" />
+ <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
+ <parameter name="enable_ports_adaptation" value="0" />
+ <parameter name="enable_ports_pipe_g3_analog" value="0" />
+ <parameter name="enable_ports_pipe_hclk" value="0" />
+ <parameter name="enable_ports_pipe_rx_elecidle" value="0" />
+ <parameter name="enable_ports_pipe_sw" value="0" />
+ <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
+ <parameter name="enable_ports_rx_manual_ppm" value="0" />
+ <parameter name="enable_ports_rx_prbs" value="1" />
+ <parameter name="enable_simple_interface" value="1" />
+ <parameter name="enable_skp_ports" value="0" />
+ <parameter name="enable_split_interface" value="0" />
+ <parameter name="enable_transparent_pcs" value="0" />
+ <parameter name="enable_upi_pipeline_options" value="0" />
+ <parameter name="enh_low_latency_enable" value="0" />
+ <parameter name="enh_pcs_pma_width" value="32" />
+ <parameter name="enh_pld_pcs_width" value="66" />
+ <parameter name="enh_rx_64b66b_enable" value="1" />
+ <parameter name="enh_rx_bitslip_enable" value="0" />
+ <parameter name="enh_rx_blksync_enable" value="1" />
+ <parameter name="enh_rx_crcchk_enable" value="0" />
+ <parameter name="enh_rx_descram_enable" value="1" />
+ <parameter name="enh_rx_dispchk_enable" value="0" />
+ <parameter name="enh_rx_frmsync_enable" value="0" />
+ <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
+ <parameter name="enh_rx_krfec_err_mark_enable" value="0" />
+ <parameter name="enh_rx_krfec_err_mark_type" value="10G" />
+ <parameter name="enh_rx_polinv_enable" value="0" />
+ <parameter name="enh_rxfifo_align_del" value="0" />
+ <parameter name="enh_rxfifo_control_del" value="0" />
+ <parameter name="enh_rxfifo_mode" value="10GBase-R" />
+ <parameter name="enh_rxfifo_pempty" value="2" />
+ <parameter name="enh_rxfifo_pfull" value="23" />
+ <parameter name="enh_rxtxfifo_double_width" value="0" />
+ <parameter name="enh_tx_64b66b_enable" value="1" />
+ <parameter name="enh_tx_bitslip_enable" value="0" />
+ <parameter name="enh_tx_crcerr_enable" value="0" />
+ <parameter name="enh_tx_crcgen_enable" value="0" />
+ <parameter name="enh_tx_dispgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_burst_enable" value="0" />
+ <parameter name="enh_tx_frmgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
+ <parameter name="enh_tx_krfec_burst_err_enable" value="0" />
+ <parameter name="enh_tx_krfec_burst_err_len" value="1" />
+ <parameter name="enh_tx_polinv_enable" value="0" />
+ <parameter name="enh_tx_randomdispbit_enable" value="0" />
+ <parameter name="enh_tx_scram_enable" value="1" />
+ <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_tx_sh_err" value="0" />
+ <parameter name="enh_txfifo_mode" value="Phase compensation" />
+ <parameter name="enh_txfifo_pempty" value="2" />
+ <parameter name="enh_txfifo_pfull" value="11" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="number_physical_bonding_clocks" value="1" />
+ <parameter name="pcie_rate_match" value="Bypass" />
+ <parameter name="pcs_direct_width" value="8" />
+ <parameter name="pcs_tx_delay1_ctrl" value="delay1_path0" />
+ <parameter name="pcs_tx_delay1_data_sel" value="one_ff_delay" />
+ <parameter name="pcs_tx_delay2_ctrl" value="delay2_path0" />
+ <parameter name="pll_select" value="0" />
+ <parameter name="plls" value="1" />
+ <parameter name="pma_mode" value="basic" />
+ <parameter name="protocol_mode" value="teng_baser_mode" />
+ <parameter name="rcfg_enable" value="1" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="1" />
+ <parameter name="rcfg_iface_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="1" />
+ <parameter name="rcfg_mif_file_enable" value="1" />
+ <parameter name="rcfg_multi_enable" value="0" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_data0" value="" />
+ <parameter name="rcfg_profile_data1" value="" />
+ <parameter name="rcfg_profile_data2" value="" />
+ <parameter name="rcfg_profile_data3" value="" />
+ <parameter name="rcfg_profile_data4" value="" />
+ <parameter name="rcfg_profile_data5" value="" />
+ <parameter name="rcfg_profile_data6" value="" />
+ <parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_shared" value="1" />
+ <parameter name="rcfg_sv_file_enable" value="1" />
+ <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
+ <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
+ <parameter name="rx_pma_dfe_fixed_taps" value="3" />
+ <parameter name="rx_pma_div_clkout_divider" value="0" />
+ <parameter name="rx_ppm_detect_threshold" value="1000" />
+ <parameter name="set_capability_reg_enable" value="1" />
+ <parameter name="set_cdr_refclk_freq" value="644.531250" />
+ <parameter name="set_csr_soft_logic_enable" value="1" />
+ <parameter name="set_data_rate" value="10312.5" />
+ <parameter name="set_disconnect_analog_resets" value="0" />
+ <parameter name="set_embedded_debug_enable" value="0" />
+ <parameter name="set_enable_calibration" value="0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_odi_soft_logic_enable" value="0" />
+ <parameter name="set_pcs_bonding_master" value="Auto" />
+ <parameter name="set_prbs_soft_logic_enable" value="1" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="sim_reduced_counters" value="false" />
+ <parameter name="std_data_mask_count_multi" value="0" />
+ <parameter name="std_low_latency_bypass_enable" value="0" />
+ <parameter name="std_pcs_pma_width" value="10" />
+ <parameter name="std_rx_8b10b_enable" value="0" />
+ <parameter name="std_rx_bitrev_enable" value="0" />
+ <parameter name="std_rx_byte_deser_mode" value="Disabled" />
+ <parameter name="std_rx_byterev_enable" value="0" />
+ <parameter name="std_rx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_rx_polinv_enable" value="0" />
+ <parameter name="std_rx_rmfifo_mode" value="disabled" />
+ <parameter name="std_rx_rmfifo_pattern_n" value="0" />
+ <parameter name="std_rx_rmfifo_pattern_p" value="0" />
+ <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
+ <parameter name="std_rx_word_aligner_mode" value="bitslip" />
+ <parameter name="std_rx_word_aligner_pattern" value="0" />
+ <parameter name="std_rx_word_aligner_pattern_len" value="7" />
+ <parameter name="std_rx_word_aligner_renumber" value="3" />
+ <parameter name="std_rx_word_aligner_rgnumber" value="3" />
+ <parameter name="std_rx_word_aligner_rknumber" value="3" />
+ <parameter name="std_rx_word_aligner_rvnumber" value="0" />
+ <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
+ <parameter name="std_tx_8b10b_enable" value="0" />
+ <parameter name="std_tx_bitrev_enable" value="0" />
+ <parameter name="std_tx_bitslip_enable" value="0" />
+ <parameter name="std_tx_byte_ser_mode" value="Disabled" />
+ <parameter name="std_tx_byterev_enable" value="0" />
+ <parameter name="std_tx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="tx_pma_clk_div" value="1" />
+ <parameter name="tx_pma_div_clkout_divider" value="33" />
+ <parameter name="validation_rule_select" value="" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c1b9278620d266e5a3926578eec8685e5521ae37
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_24/sim"
+
+
+ vcom "$IP_DIR/ip_arria10_e2sg_phy_10gbase_r_24.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..ddf0e85afef65e03e6fd58bf78f2a58f034dd35c
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_phy_10gbase_r_24
+hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_24_altera_xcvr_native_a10_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_24/ip_arria10_e2sg_phy_10gbase_r_24.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_phy_10gbase_r_24.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/ip_arria10_e2sg_phy_10gbase_r_24.qsys b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/ip_arria10_e2sg_phy_10gbase_r_24.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..e1de6c2958a8f20801ff66e1e4b64807168e4902
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/ip_arria10_e2sg_phy_10gbase_r_24.qsys
@@ -0,0 +1,627 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_phy_10gbase_r_24">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element xcvr_native_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="reconfig_avmm"
+ internal="xcvr_native_a10_0.reconfig_avmm"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_address" internal="reconfig_address" />
+ <port name="reconfig_read" internal="reconfig_read" />
+ <port name="reconfig_readdata" internal="reconfig_readdata" />
+ <port name="reconfig_waitrequest" internal="reconfig_waitrequest" />
+ <port name="reconfig_write" internal="reconfig_write" />
+ <port name="reconfig_writedata" internal="reconfig_writedata" />
+ </interface>
+ <interface
+ name="reconfig_clk"
+ internal="xcvr_native_a10_0.reconfig_clk"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_clk" internal="reconfig_clk" />
+ </interface>
+ <interface
+ name="reconfig_reset"
+ internal="xcvr_native_a10_0.reconfig_reset"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_reset" internal="reconfig_reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="xcvr_native_a10_0.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="xcvr_native_a10_0.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_cdr_refclk0"
+ internal="xcvr_native_a10_0.rx_cdr_refclk0"
+ type="conduit"
+ dir="end">
+ <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
+ </interface>
+ <interface
+ name="rx_clkout"
+ internal="xcvr_native_a10_0.rx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="rx_clkout" internal="rx_clkout" />
+ </interface>
+ <interface
+ name="rx_control"
+ internal="xcvr_native_a10_0.rx_control"
+ type="conduit"
+ dir="end">
+ <port name="rx_control" internal="rx_control" />
+ </interface>
+ <interface
+ name="rx_coreclkin"
+ internal="xcvr_native_a10_0.rx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="rx_coreclkin" internal="rx_coreclkin" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="xcvr_native_a10_0.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_enh_blk_lock"
+ internal="xcvr_native_a10_0.rx_enh_blk_lock"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
+ </interface>
+ <interface
+ name="rx_enh_data_valid"
+ internal="xcvr_native_a10_0.rx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_del"
+ internal="xcvr_native_a10_0.rx_enh_fifo_del"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_del" internal="rx_enh_fifo_del" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.rx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_empty" internal="rx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_full"
+ internal="xcvr_native_a10_0.rx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_full" internal="rx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_insert"
+ internal="xcvr_native_a10_0.rx_enh_fifo_insert"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_insert" internal="rx_enh_fifo_insert" />
+ </interface>
+ <interface
+ name="rx_enh_highber"
+ internal="xcvr_native_a10_0.rx_enh_highber"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_highber" internal="rx_enh_highber" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="xcvr_native_a10_0.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_is_lockedtoref"
+ internal="xcvr_native_a10_0.rx_is_lockedtoref"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtoref" internal="rx_is_lockedtoref" />
+ </interface>
+ <interface
+ name="rx_parallel_data"
+ internal="xcvr_native_a10_0.rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_parallel_data" internal="rx_parallel_data" />
+ </interface>
+ <interface
+ name="rx_prbs_done"
+ internal="xcvr_native_a10_0.rx_prbs_done"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_done" internal="rx_prbs_done" />
+ </interface>
+ <interface
+ name="rx_prbs_err"
+ internal="xcvr_native_a10_0.rx_prbs_err"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err" internal="rx_prbs_err" />
+ </interface>
+ <interface
+ name="rx_prbs_err_clr"
+ internal="xcvr_native_a10_0.rx_prbs_err_clr"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err_clr" internal="rx_prbs_err_clr" />
+ </interface>
+ <interface
+ name="rx_serial_data"
+ internal="xcvr_native_a10_0.rx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_serial_data" internal="rx_serial_data" />
+ </interface>
+ <interface
+ name="rx_seriallpbken"
+ internal="xcvr_native_a10_0.rx_seriallpbken"
+ type="conduit"
+ dir="end">
+ <port name="rx_seriallpbken" internal="rx_seriallpbken" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="xcvr_native_a10_0.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="xcvr_native_a10_0.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_clkout"
+ internal="xcvr_native_a10_0.tx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="tx_clkout" internal="tx_clkout" />
+ </interface>
+ <interface
+ name="tx_control"
+ internal="xcvr_native_a10_0.tx_control"
+ type="conduit"
+ dir="end">
+ <port name="tx_control" internal="tx_control" />
+ </interface>
+ <interface
+ name="tx_coreclkin"
+ internal="xcvr_native_a10_0.tx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="tx_coreclkin" internal="tx_coreclkin" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="xcvr_native_a10_0.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_enh_data_valid"
+ internal="xcvr_native_a10_0.tx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_empty" internal="tx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_full"
+ internal="xcvr_native_a10_0.tx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_full" internal="tx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pempty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pempty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pempty" internal="tx_enh_fifo_pempty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pfull"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pfull"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pfull" internal="tx_enh_fifo_pfull" />
+ </interface>
+ <interface
+ name="tx_err_ins"
+ internal="xcvr_native_a10_0.tx_err_ins"
+ type="conduit"
+ dir="end">
+ <port name="tx_err_ins" internal="tx_err_ins" />
+ </interface>
+ <interface
+ name="tx_parallel_data"
+ internal="xcvr_native_a10_0.tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_parallel_data" internal="tx_parallel_data" />
+ </interface>
+ <interface name="tx_pma_clkout" internal="xcvr_native_a10_0.tx_pma_clkout" />
+ <interface
+ name="tx_pma_div_clkout"
+ internal="xcvr_native_a10_0.tx_pma_div_clkout" />
+ <interface
+ name="tx_serial_clk0"
+ internal="xcvr_native_a10_0.tx_serial_clk0"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_clk0" internal="tx_serial_clk0" />
+ </interface>
+ <interface
+ name="tx_serial_data"
+ internal="xcvr_native_a10_0.tx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_data" internal="tx_serial_data" />
+ </interface>
+ <interface
+ name="unused_rx_control"
+ internal="xcvr_native_a10_0.unused_rx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_control" internal="unused_rx_control" />
+ </interface>
+ <interface
+ name="unused_rx_parallel_data"
+ internal="xcvr_native_a10_0.unused_rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
+ </interface>
+ <interface
+ name="unused_tx_control"
+ internal="xcvr_native_a10_0.unused_tx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_control" internal="unused_tx_control" />
+ </interface>
+ <interface
+ name="unused_tx_parallel_data"
+ internal="xcvr_native_a10_0.unused_tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
+ </interface>
+ <module
+ name="xcvr_native_a10_0"
+ kind="altera_xcvr_native_a10"
+ version="19.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="anlg_enable_rx_default_ovr" value="0" />
+ <parameter name="anlg_enable_tx_default_ovr" value="0" />
+ <parameter name="anlg_link" value="sr" />
+ <parameter name="anlg_rx_adp_ctle_acgain_4s">radp_ctle_acgain_4s_1</parameter>
+ <parameter name="anlg_rx_adp_ctle_eqz_1s_sel">radp_ctle_eqz_1s_sel_3</parameter>
+ <parameter name="anlg_rx_adp_dfe_fxtap1" value="radp_dfe_fxtap1_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap10" value="radp_dfe_fxtap10_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap11" value="radp_dfe_fxtap11_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap2" value="radp_dfe_fxtap2_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap3" value="radp_dfe_fxtap3_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap4" value="radp_dfe_fxtap4_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap5" value="radp_dfe_fxtap5_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap6" value="radp_dfe_fxtap6_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap7" value="radp_dfe_fxtap7_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap8" value="radp_dfe_fxtap8_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap9" value="radp_dfe_fxtap9_0" />
+ <parameter name="anlg_rx_adp_vga_sel" value="radp_vga_sel_2" />
+ <parameter name="anlg_rx_eq_dc_gain_trim" value="stg2_gain7" />
+ <parameter name="anlg_rx_one_stage_enable" value="s1_mode" />
+ <parameter name="anlg_rx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_analog_mode" value="user_custom" />
+ <parameter name="anlg_tx_compensation_en" value="enable" />
+ <parameter name="anlg_tx_pre_emp_sign_1st_post_tap" value="fir_post_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_2nd_post_tap" value="fir_post_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_1t" value="fir_pre_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_2t" value="fir_pre_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_1st_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_2nd_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_1t" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_2t" value="0" />
+ <parameter name="anlg_tx_slew_rate_ctrl" value="slew_r7" />
+ <parameter name="anlg_tx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_vod_output_swing_ctrl" value="0" />
+ <parameter name="anlg_voltage" value="1_1V" />
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="bonded_mode" value="not_bonded" />
+ <parameter name="cdr_refclk_cnt" value="1" />
+ <parameter name="cdr_refclk_select" value="0" />
+ <parameter name="channels" value="24" />
+ <parameter name="design_environment" value="NATIVE" />
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="disable_continuous_dfe" value="false" />
+ <parameter name="duplex_mode" value="duplex" />
+ <parameter name="enable_analog_settings" value="0" />
+ <parameter name="enable_hard_reset" value="0" />
+ <parameter name="enable_hip" value="0" />
+ <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="enable_pcie_data_mask_option" value="0" />
+ <parameter name="enable_pcie_dfe_ip" value="false" />
+ <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
+ <parameter name="enable_port_pipe_rx_polarity" value="0" />
+ <parameter name="enable_port_rx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enable_port_rx_enh_blk_lock" value="1" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count_c10" value="0" />
+ <parameter name="enable_port_rx_enh_crc32_err" value="0" />
+ <parameter name="enable_port_rx_enh_data_valid" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_del" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_insert" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
+ <parameter name="enable_port_rx_enh_frame" value="0" />
+ <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_rx_enh_frame_lock" value="0" />
+ <parameter name="enable_port_rx_enh_highber" value="1" />
+ <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
+ <parameter name="enable_port_rx_is_lockedtodata" value="1" />
+ <parameter name="enable_port_rx_is_lockedtoref" value="1" />
+ <parameter name="enable_port_rx_pma_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_clkslip" value="0" />
+ <parameter name="enable_port_rx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_rx_polinv" value="0" />
+ <parameter name="enable_port_rx_seriallpbken" value="1" />
+ <parameter name="enable_port_rx_seriallpbken_tx" value="1" />
+ <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
+ <parameter name="enable_port_rx_std_bitslip" value="0" />
+ <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_rx_std_byterev_ena" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
+ <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_tx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_tx_enh_bitslip" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pempty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pfull" value="1" />
+ <parameter name="enable_port_tx_enh_frame" value="0" />
+ <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
+ <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_tx_pma_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_elecidle" value="0" />
+ <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_tx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_tx_pma_rxfound" value="0" />
+ <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
+ <parameter name="enable_port_tx_polinv" value="0" />
+ <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
+ <parameter name="enable_ports_adaptation" value="0" />
+ <parameter name="enable_ports_pipe_g3_analog" value="0" />
+ <parameter name="enable_ports_pipe_hclk" value="0" />
+ <parameter name="enable_ports_pipe_rx_elecidle" value="0" />
+ <parameter name="enable_ports_pipe_sw" value="0" />
+ <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
+ <parameter name="enable_ports_rx_manual_ppm" value="0" />
+ <parameter name="enable_ports_rx_prbs" value="1" />
+ <parameter name="enable_simple_interface" value="1" />
+ <parameter name="enable_skp_ports" value="0" />
+ <parameter name="enable_split_interface" value="0" />
+ <parameter name="enable_transparent_pcs" value="0" />
+ <parameter name="enable_upi_pipeline_options" value="0" />
+ <parameter name="enh_low_latency_enable" value="0" />
+ <parameter name="enh_pcs_pma_width" value="32" />
+ <parameter name="enh_pld_pcs_width" value="66" />
+ <parameter name="enh_rx_64b66b_enable" value="1" />
+ <parameter name="enh_rx_bitslip_enable" value="0" />
+ <parameter name="enh_rx_blksync_enable" value="1" />
+ <parameter name="enh_rx_crcchk_enable" value="0" />
+ <parameter name="enh_rx_descram_enable" value="1" />
+ <parameter name="enh_rx_dispchk_enable" value="0" />
+ <parameter name="enh_rx_frmsync_enable" value="0" />
+ <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
+ <parameter name="enh_rx_krfec_err_mark_enable" value="0" />
+ <parameter name="enh_rx_krfec_err_mark_type" value="10G" />
+ <parameter name="enh_rx_polinv_enable" value="0" />
+ <parameter name="enh_rxfifo_align_del" value="0" />
+ <parameter name="enh_rxfifo_control_del" value="0" />
+ <parameter name="enh_rxfifo_mode" value="10GBase-R" />
+ <parameter name="enh_rxfifo_pempty" value="2" />
+ <parameter name="enh_rxfifo_pfull" value="23" />
+ <parameter name="enh_rxtxfifo_double_width" value="0" />
+ <parameter name="enh_tx_64b66b_enable" value="1" />
+ <parameter name="enh_tx_bitslip_enable" value="0" />
+ <parameter name="enh_tx_crcerr_enable" value="0" />
+ <parameter name="enh_tx_crcgen_enable" value="0" />
+ <parameter name="enh_tx_dispgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_burst_enable" value="0" />
+ <parameter name="enh_tx_frmgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
+ <parameter name="enh_tx_krfec_burst_err_enable" value="0" />
+ <parameter name="enh_tx_krfec_burst_err_len" value="1" />
+ <parameter name="enh_tx_polinv_enable" value="0" />
+ <parameter name="enh_tx_randomdispbit_enable" value="0" />
+ <parameter name="enh_tx_scram_enable" value="1" />
+ <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_tx_sh_err" value="0" />
+ <parameter name="enh_txfifo_mode" value="Phase compensation" />
+ <parameter name="enh_txfifo_pempty" value="2" />
+ <parameter name="enh_txfifo_pfull" value="11" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="number_physical_bonding_clocks" value="1" />
+ <parameter name="pcie_rate_match" value="Bypass" />
+ <parameter name="pcs_direct_width" value="8" />
+ <parameter name="pcs_tx_delay1_ctrl" value="delay1_path0" />
+ <parameter name="pcs_tx_delay1_data_sel" value="one_ff_delay" />
+ <parameter name="pcs_tx_delay2_ctrl" value="delay2_path0" />
+ <parameter name="pll_select" value="0" />
+ <parameter name="plls" value="1" />
+ <parameter name="pma_mode" value="basic" />
+ <parameter name="protocol_mode" value="teng_baser_mode" />
+ <parameter name="rcfg_enable" value="1" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="1" />
+ <parameter name="rcfg_iface_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="1" />
+ <parameter name="rcfg_mif_file_enable" value="1" />
+ <parameter name="rcfg_multi_enable" value="0" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_data0" value="" />
+ <parameter name="rcfg_profile_data1" value="" />
+ <parameter name="rcfg_profile_data2" value="" />
+ <parameter name="rcfg_profile_data3" value="" />
+ <parameter name="rcfg_profile_data4" value="" />
+ <parameter name="rcfg_profile_data5" value="" />
+ <parameter name="rcfg_profile_data6" value="" />
+ <parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_shared" value="1" />
+ <parameter name="rcfg_sv_file_enable" value="1" />
+ <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
+ <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
+ <parameter name="rx_pma_dfe_fixed_taps" value="3" />
+ <parameter name="rx_pma_div_clkout_divider" value="0" />
+ <parameter name="rx_ppm_detect_threshold" value="1000" />
+ <parameter name="set_capability_reg_enable" value="1" />
+ <parameter name="set_cdr_refclk_freq" value="644.531250" />
+ <parameter name="set_csr_soft_logic_enable" value="1" />
+ <parameter name="set_data_rate" value="10312.5" />
+ <parameter name="set_disconnect_analog_resets" value="0" />
+ <parameter name="set_embedded_debug_enable" value="0" />
+ <parameter name="set_enable_calibration" value="0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_odi_soft_logic_enable" value="0" />
+ <parameter name="set_pcs_bonding_master" value="Auto" />
+ <parameter name="set_prbs_soft_logic_enable" value="1" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="sim_reduced_counters" value="false" />
+ <parameter name="std_data_mask_count_multi" value="0" />
+ <parameter name="std_low_latency_bypass_enable" value="0" />
+ <parameter name="std_pcs_pma_width" value="10" />
+ <parameter name="std_rx_8b10b_enable" value="0" />
+ <parameter name="std_rx_bitrev_enable" value="0" />
+ <parameter name="std_rx_byte_deser_mode" value="Disabled" />
+ <parameter name="std_rx_byterev_enable" value="0" />
+ <parameter name="std_rx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_rx_polinv_enable" value="0" />
+ <parameter name="std_rx_rmfifo_mode" value="disabled" />
+ <parameter name="std_rx_rmfifo_pattern_n" value="0" />
+ <parameter name="std_rx_rmfifo_pattern_p" value="0" />
+ <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
+ <parameter name="std_rx_word_aligner_mode" value="bitslip" />
+ <parameter name="std_rx_word_aligner_pattern" value="0" />
+ <parameter name="std_rx_word_aligner_pattern_len" value="7" />
+ <parameter name="std_rx_word_aligner_renumber" value="3" />
+ <parameter name="std_rx_word_aligner_rgnumber" value="3" />
+ <parameter name="std_rx_word_aligner_rknumber" value="3" />
+ <parameter name="std_rx_word_aligner_rvnumber" value="0" />
+ <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
+ <parameter name="std_tx_8b10b_enable" value="0" />
+ <parameter name="std_tx_bitrev_enable" value="0" />
+ <parameter name="std_tx_bitslip_enable" value="0" />
+ <parameter name="std_tx_byte_ser_mode" value="Disabled" />
+ <parameter name="std_tx_byterev_enable" value="0" />
+ <parameter name="std_tx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="tx_pma_clk_div" value="1" />
+ <parameter name="tx_pma_div_clkout_divider" value="33" />
+ <parameter name="validation_rule_select" value="" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5e81bb41af29029a71012512b1c3c2fe2d1a61a5
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_3/sim"
+
+
+ vcom "$IP_DIR/ip_arria10_e2sg_phy_10gbase_r_3.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..c9cfcb42a0df532ff2a6c5a20f02f72d14cf5e12
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_phy_10gbase_r_3
+hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_3_altera_xcvr_native_a10_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_3/ip_arria10_e2sg_phy_10gbase_r_3.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_phy_10gbase_r_3.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/ip_arria10_e2sg_phy_10gbase_r_3.qsys b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/ip_arria10_e2sg_phy_10gbase_r_3.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..a54c573db2d8b70ac8e684c40d16655284c1afe7
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/ip_arria10_e2sg_phy_10gbase_r_3.qsys
@@ -0,0 +1,627 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_phy_10gbase_r_3">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element xcvr_native_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="reconfig_avmm"
+ internal="xcvr_native_a10_0.reconfig_avmm"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_address" internal="reconfig_address" />
+ <port name="reconfig_read" internal="reconfig_read" />
+ <port name="reconfig_readdata" internal="reconfig_readdata" />
+ <port name="reconfig_waitrequest" internal="reconfig_waitrequest" />
+ <port name="reconfig_write" internal="reconfig_write" />
+ <port name="reconfig_writedata" internal="reconfig_writedata" />
+ </interface>
+ <interface
+ name="reconfig_clk"
+ internal="xcvr_native_a10_0.reconfig_clk"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_clk" internal="reconfig_clk" />
+ </interface>
+ <interface
+ name="reconfig_reset"
+ internal="xcvr_native_a10_0.reconfig_reset"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_reset" internal="reconfig_reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="xcvr_native_a10_0.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="xcvr_native_a10_0.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_cdr_refclk0"
+ internal="xcvr_native_a10_0.rx_cdr_refclk0"
+ type="conduit"
+ dir="end">
+ <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
+ </interface>
+ <interface
+ name="rx_clkout"
+ internal="xcvr_native_a10_0.rx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="rx_clkout" internal="rx_clkout" />
+ </interface>
+ <interface
+ name="rx_control"
+ internal="xcvr_native_a10_0.rx_control"
+ type="conduit"
+ dir="end">
+ <port name="rx_control" internal="rx_control" />
+ </interface>
+ <interface
+ name="rx_coreclkin"
+ internal="xcvr_native_a10_0.rx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="rx_coreclkin" internal="rx_coreclkin" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="xcvr_native_a10_0.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_enh_blk_lock"
+ internal="xcvr_native_a10_0.rx_enh_blk_lock"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
+ </interface>
+ <interface
+ name="rx_enh_data_valid"
+ internal="xcvr_native_a10_0.rx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_del"
+ internal="xcvr_native_a10_0.rx_enh_fifo_del"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_del" internal="rx_enh_fifo_del" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.rx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_empty" internal="rx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_full"
+ internal="xcvr_native_a10_0.rx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_full" internal="rx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_insert"
+ internal="xcvr_native_a10_0.rx_enh_fifo_insert"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_insert" internal="rx_enh_fifo_insert" />
+ </interface>
+ <interface
+ name="rx_enh_highber"
+ internal="xcvr_native_a10_0.rx_enh_highber"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_highber" internal="rx_enh_highber" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="xcvr_native_a10_0.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_is_lockedtoref"
+ internal="xcvr_native_a10_0.rx_is_lockedtoref"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtoref" internal="rx_is_lockedtoref" />
+ </interface>
+ <interface
+ name="rx_parallel_data"
+ internal="xcvr_native_a10_0.rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_parallel_data" internal="rx_parallel_data" />
+ </interface>
+ <interface
+ name="rx_prbs_done"
+ internal="xcvr_native_a10_0.rx_prbs_done"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_done" internal="rx_prbs_done" />
+ </interface>
+ <interface
+ name="rx_prbs_err"
+ internal="xcvr_native_a10_0.rx_prbs_err"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err" internal="rx_prbs_err" />
+ </interface>
+ <interface
+ name="rx_prbs_err_clr"
+ internal="xcvr_native_a10_0.rx_prbs_err_clr"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err_clr" internal="rx_prbs_err_clr" />
+ </interface>
+ <interface
+ name="rx_serial_data"
+ internal="xcvr_native_a10_0.rx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_serial_data" internal="rx_serial_data" />
+ </interface>
+ <interface
+ name="rx_seriallpbken"
+ internal="xcvr_native_a10_0.rx_seriallpbken"
+ type="conduit"
+ dir="end">
+ <port name="rx_seriallpbken" internal="rx_seriallpbken" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="xcvr_native_a10_0.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="xcvr_native_a10_0.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_clkout"
+ internal="xcvr_native_a10_0.tx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="tx_clkout" internal="tx_clkout" />
+ </interface>
+ <interface
+ name="tx_control"
+ internal="xcvr_native_a10_0.tx_control"
+ type="conduit"
+ dir="end">
+ <port name="tx_control" internal="tx_control" />
+ </interface>
+ <interface
+ name="tx_coreclkin"
+ internal="xcvr_native_a10_0.tx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="tx_coreclkin" internal="tx_coreclkin" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="xcvr_native_a10_0.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_enh_data_valid"
+ internal="xcvr_native_a10_0.tx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_empty" internal="tx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_full"
+ internal="xcvr_native_a10_0.tx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_full" internal="tx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pempty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pempty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pempty" internal="tx_enh_fifo_pempty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pfull"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pfull"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pfull" internal="tx_enh_fifo_pfull" />
+ </interface>
+ <interface
+ name="tx_err_ins"
+ internal="xcvr_native_a10_0.tx_err_ins"
+ type="conduit"
+ dir="end">
+ <port name="tx_err_ins" internal="tx_err_ins" />
+ </interface>
+ <interface
+ name="tx_parallel_data"
+ internal="xcvr_native_a10_0.tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_parallel_data" internal="tx_parallel_data" />
+ </interface>
+ <interface name="tx_pma_clkout" internal="xcvr_native_a10_0.tx_pma_clkout" />
+ <interface
+ name="tx_pma_div_clkout"
+ internal="xcvr_native_a10_0.tx_pma_div_clkout" />
+ <interface
+ name="tx_serial_clk0"
+ internal="xcvr_native_a10_0.tx_serial_clk0"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_clk0" internal="tx_serial_clk0" />
+ </interface>
+ <interface
+ name="tx_serial_data"
+ internal="xcvr_native_a10_0.tx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_data" internal="tx_serial_data" />
+ </interface>
+ <interface
+ name="unused_rx_control"
+ internal="xcvr_native_a10_0.unused_rx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_control" internal="unused_rx_control" />
+ </interface>
+ <interface
+ name="unused_rx_parallel_data"
+ internal="xcvr_native_a10_0.unused_rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
+ </interface>
+ <interface
+ name="unused_tx_control"
+ internal="xcvr_native_a10_0.unused_tx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_control" internal="unused_tx_control" />
+ </interface>
+ <interface
+ name="unused_tx_parallel_data"
+ internal="xcvr_native_a10_0.unused_tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
+ </interface>
+ <module
+ name="xcvr_native_a10_0"
+ kind="altera_xcvr_native_a10"
+ version="19.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="anlg_enable_rx_default_ovr" value="0" />
+ <parameter name="anlg_enable_tx_default_ovr" value="0" />
+ <parameter name="anlg_link" value="sr" />
+ <parameter name="anlg_rx_adp_ctle_acgain_4s">radp_ctle_acgain_4s_1</parameter>
+ <parameter name="anlg_rx_adp_ctle_eqz_1s_sel">radp_ctle_eqz_1s_sel_3</parameter>
+ <parameter name="anlg_rx_adp_dfe_fxtap1" value="radp_dfe_fxtap1_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap10" value="radp_dfe_fxtap10_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap11" value="radp_dfe_fxtap11_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap2" value="radp_dfe_fxtap2_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap3" value="radp_dfe_fxtap3_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap4" value="radp_dfe_fxtap4_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap5" value="radp_dfe_fxtap5_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap6" value="radp_dfe_fxtap6_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap7" value="radp_dfe_fxtap7_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap8" value="radp_dfe_fxtap8_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap9" value="radp_dfe_fxtap9_0" />
+ <parameter name="anlg_rx_adp_vga_sel" value="radp_vga_sel_2" />
+ <parameter name="anlg_rx_eq_dc_gain_trim" value="stg2_gain7" />
+ <parameter name="anlg_rx_one_stage_enable" value="s1_mode" />
+ <parameter name="anlg_rx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_analog_mode" value="user_custom" />
+ <parameter name="anlg_tx_compensation_en" value="enable" />
+ <parameter name="anlg_tx_pre_emp_sign_1st_post_tap" value="fir_post_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_2nd_post_tap" value="fir_post_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_1t" value="fir_pre_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_2t" value="fir_pre_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_1st_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_2nd_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_1t" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_2t" value="0" />
+ <parameter name="anlg_tx_slew_rate_ctrl" value="slew_r7" />
+ <parameter name="anlg_tx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_vod_output_swing_ctrl" value="0" />
+ <parameter name="anlg_voltage" value="1_1V" />
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="bonded_mode" value="not_bonded" />
+ <parameter name="cdr_refclk_cnt" value="1" />
+ <parameter name="cdr_refclk_select" value="0" />
+ <parameter name="channels" value="3" />
+ <parameter name="design_environment" value="NATIVE" />
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="disable_continuous_dfe" value="false" />
+ <parameter name="duplex_mode" value="duplex" />
+ <parameter name="enable_analog_settings" value="0" />
+ <parameter name="enable_hard_reset" value="0" />
+ <parameter name="enable_hip" value="0" />
+ <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="enable_pcie_data_mask_option" value="0" />
+ <parameter name="enable_pcie_dfe_ip" value="false" />
+ <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
+ <parameter name="enable_port_pipe_rx_polarity" value="0" />
+ <parameter name="enable_port_rx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enable_port_rx_enh_blk_lock" value="1" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count_c10" value="0" />
+ <parameter name="enable_port_rx_enh_crc32_err" value="0" />
+ <parameter name="enable_port_rx_enh_data_valid" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_del" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_insert" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
+ <parameter name="enable_port_rx_enh_frame" value="0" />
+ <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_rx_enh_frame_lock" value="0" />
+ <parameter name="enable_port_rx_enh_highber" value="1" />
+ <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
+ <parameter name="enable_port_rx_is_lockedtodata" value="1" />
+ <parameter name="enable_port_rx_is_lockedtoref" value="1" />
+ <parameter name="enable_port_rx_pma_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_clkslip" value="0" />
+ <parameter name="enable_port_rx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_rx_polinv" value="0" />
+ <parameter name="enable_port_rx_seriallpbken" value="1" />
+ <parameter name="enable_port_rx_seriallpbken_tx" value="1" />
+ <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
+ <parameter name="enable_port_rx_std_bitslip" value="0" />
+ <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_rx_std_byterev_ena" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
+ <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_tx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_tx_enh_bitslip" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pempty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pfull" value="1" />
+ <parameter name="enable_port_tx_enh_frame" value="0" />
+ <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
+ <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_tx_pma_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_elecidle" value="0" />
+ <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_tx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_tx_pma_rxfound" value="0" />
+ <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
+ <parameter name="enable_port_tx_polinv" value="0" />
+ <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
+ <parameter name="enable_ports_adaptation" value="0" />
+ <parameter name="enable_ports_pipe_g3_analog" value="0" />
+ <parameter name="enable_ports_pipe_hclk" value="0" />
+ <parameter name="enable_ports_pipe_rx_elecidle" value="0" />
+ <parameter name="enable_ports_pipe_sw" value="0" />
+ <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
+ <parameter name="enable_ports_rx_manual_ppm" value="0" />
+ <parameter name="enable_ports_rx_prbs" value="1" />
+ <parameter name="enable_simple_interface" value="1" />
+ <parameter name="enable_skp_ports" value="0" />
+ <parameter name="enable_split_interface" value="0" />
+ <parameter name="enable_transparent_pcs" value="0" />
+ <parameter name="enable_upi_pipeline_options" value="0" />
+ <parameter name="enh_low_latency_enable" value="0" />
+ <parameter name="enh_pcs_pma_width" value="32" />
+ <parameter name="enh_pld_pcs_width" value="66" />
+ <parameter name="enh_rx_64b66b_enable" value="1" />
+ <parameter name="enh_rx_bitslip_enable" value="0" />
+ <parameter name="enh_rx_blksync_enable" value="1" />
+ <parameter name="enh_rx_crcchk_enable" value="0" />
+ <parameter name="enh_rx_descram_enable" value="1" />
+ <parameter name="enh_rx_dispchk_enable" value="0" />
+ <parameter name="enh_rx_frmsync_enable" value="0" />
+ <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
+ <parameter name="enh_rx_krfec_err_mark_enable" value="0" />
+ <parameter name="enh_rx_krfec_err_mark_type" value="10G" />
+ <parameter name="enh_rx_polinv_enable" value="0" />
+ <parameter name="enh_rxfifo_align_del" value="0" />
+ <parameter name="enh_rxfifo_control_del" value="0" />
+ <parameter name="enh_rxfifo_mode" value="10GBase-R" />
+ <parameter name="enh_rxfifo_pempty" value="2" />
+ <parameter name="enh_rxfifo_pfull" value="23" />
+ <parameter name="enh_rxtxfifo_double_width" value="0" />
+ <parameter name="enh_tx_64b66b_enable" value="1" />
+ <parameter name="enh_tx_bitslip_enable" value="0" />
+ <parameter name="enh_tx_crcerr_enable" value="0" />
+ <parameter name="enh_tx_crcgen_enable" value="0" />
+ <parameter name="enh_tx_dispgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_burst_enable" value="0" />
+ <parameter name="enh_tx_frmgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
+ <parameter name="enh_tx_krfec_burst_err_enable" value="0" />
+ <parameter name="enh_tx_krfec_burst_err_len" value="1" />
+ <parameter name="enh_tx_polinv_enable" value="0" />
+ <parameter name="enh_tx_randomdispbit_enable" value="0" />
+ <parameter name="enh_tx_scram_enable" value="1" />
+ <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_tx_sh_err" value="0" />
+ <parameter name="enh_txfifo_mode" value="Phase compensation" />
+ <parameter name="enh_txfifo_pempty" value="2" />
+ <parameter name="enh_txfifo_pfull" value="11" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="number_physical_bonding_clocks" value="1" />
+ <parameter name="pcie_rate_match" value="Bypass" />
+ <parameter name="pcs_direct_width" value="8" />
+ <parameter name="pcs_tx_delay1_ctrl" value="delay1_path0" />
+ <parameter name="pcs_tx_delay1_data_sel" value="one_ff_delay" />
+ <parameter name="pcs_tx_delay2_ctrl" value="delay2_path0" />
+ <parameter name="pll_select" value="0" />
+ <parameter name="plls" value="1" />
+ <parameter name="pma_mode" value="basic" />
+ <parameter name="protocol_mode" value="teng_baser_mode" />
+ <parameter name="rcfg_enable" value="1" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="1" />
+ <parameter name="rcfg_iface_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="1" />
+ <parameter name="rcfg_mif_file_enable" value="1" />
+ <parameter name="rcfg_multi_enable" value="0" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_data0" value="" />
+ <parameter name="rcfg_profile_data1" value="" />
+ <parameter name="rcfg_profile_data2" value="" />
+ <parameter name="rcfg_profile_data3" value="" />
+ <parameter name="rcfg_profile_data4" value="" />
+ <parameter name="rcfg_profile_data5" value="" />
+ <parameter name="rcfg_profile_data6" value="" />
+ <parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_shared" value="1" />
+ <parameter name="rcfg_sv_file_enable" value="1" />
+ <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
+ <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
+ <parameter name="rx_pma_dfe_fixed_taps" value="3" />
+ <parameter name="rx_pma_div_clkout_divider" value="0" />
+ <parameter name="rx_ppm_detect_threshold" value="1000" />
+ <parameter name="set_capability_reg_enable" value="1" />
+ <parameter name="set_cdr_refclk_freq" value="644.531250" />
+ <parameter name="set_csr_soft_logic_enable" value="1" />
+ <parameter name="set_data_rate" value="10312.5" />
+ <parameter name="set_disconnect_analog_resets" value="0" />
+ <parameter name="set_embedded_debug_enable" value="0" />
+ <parameter name="set_enable_calibration" value="0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_odi_soft_logic_enable" value="0" />
+ <parameter name="set_pcs_bonding_master" value="Auto" />
+ <parameter name="set_prbs_soft_logic_enable" value="1" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="sim_reduced_counters" value="false" />
+ <parameter name="std_data_mask_count_multi" value="0" />
+ <parameter name="std_low_latency_bypass_enable" value="0" />
+ <parameter name="std_pcs_pma_width" value="10" />
+ <parameter name="std_rx_8b10b_enable" value="0" />
+ <parameter name="std_rx_bitrev_enable" value="0" />
+ <parameter name="std_rx_byte_deser_mode" value="Disabled" />
+ <parameter name="std_rx_byterev_enable" value="0" />
+ <parameter name="std_rx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_rx_polinv_enable" value="0" />
+ <parameter name="std_rx_rmfifo_mode" value="disabled" />
+ <parameter name="std_rx_rmfifo_pattern_n" value="0" />
+ <parameter name="std_rx_rmfifo_pattern_p" value="0" />
+ <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
+ <parameter name="std_rx_word_aligner_mode" value="bitslip" />
+ <parameter name="std_rx_word_aligner_pattern" value="0" />
+ <parameter name="std_rx_word_aligner_pattern_len" value="7" />
+ <parameter name="std_rx_word_aligner_renumber" value="3" />
+ <parameter name="std_rx_word_aligner_rgnumber" value="3" />
+ <parameter name="std_rx_word_aligner_rknumber" value="3" />
+ <parameter name="std_rx_word_aligner_rvnumber" value="0" />
+ <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
+ <parameter name="std_tx_8b10b_enable" value="0" />
+ <parameter name="std_tx_bitrev_enable" value="0" />
+ <parameter name="std_tx_bitslip_enable" value="0" />
+ <parameter name="std_tx_byte_ser_mode" value="Disabled" />
+ <parameter name="std_tx_byterev_enable" value="0" />
+ <parameter name="std_tx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="tx_pma_clk_div" value="1" />
+ <parameter name="tx_pma_div_clkout_divider" value="33" />
+ <parameter name="validation_rule_select" value="" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..a969be29f8e1d8f990c37f3356ee44cb0c3a3b0a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_4/sim"
+
+
+ vcom "$IP_DIR/ip_arria10_e2sg_phy_10gbase_r_4.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..f30aeb66334106332bd0bf27ac97983583c98f44
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_phy_10gbase_r_4
+hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_4_altera_xcvr_native_a10_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_4/ip_arria10_e2sg_phy_10gbase_r_4.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_phy_10gbase_r_4.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/ip_arria10_e2sg_phy_10gbase_r_4.qsys b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/ip_arria10_e2sg_phy_10gbase_r_4.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..ee891a25cff5b6335aeb9daf282dac3dca6f84e0
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/ip_arria10_e2sg_phy_10gbase_r_4.qsys
@@ -0,0 +1,627 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_phy_10gbase_r_4">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element xcvr_native_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="reconfig_avmm"
+ internal="xcvr_native_a10_0.reconfig_avmm"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_address" internal="reconfig_address" />
+ <port name="reconfig_read" internal="reconfig_read" />
+ <port name="reconfig_readdata" internal="reconfig_readdata" />
+ <port name="reconfig_waitrequest" internal="reconfig_waitrequest" />
+ <port name="reconfig_write" internal="reconfig_write" />
+ <port name="reconfig_writedata" internal="reconfig_writedata" />
+ </interface>
+ <interface
+ name="reconfig_clk"
+ internal="xcvr_native_a10_0.reconfig_clk"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_clk" internal="reconfig_clk" />
+ </interface>
+ <interface
+ name="reconfig_reset"
+ internal="xcvr_native_a10_0.reconfig_reset"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_reset" internal="reconfig_reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="xcvr_native_a10_0.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="xcvr_native_a10_0.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_cdr_refclk0"
+ internal="xcvr_native_a10_0.rx_cdr_refclk0"
+ type="conduit"
+ dir="end">
+ <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
+ </interface>
+ <interface
+ name="rx_clkout"
+ internal="xcvr_native_a10_0.rx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="rx_clkout" internal="rx_clkout" />
+ </interface>
+ <interface
+ name="rx_control"
+ internal="xcvr_native_a10_0.rx_control"
+ type="conduit"
+ dir="end">
+ <port name="rx_control" internal="rx_control" />
+ </interface>
+ <interface
+ name="rx_coreclkin"
+ internal="xcvr_native_a10_0.rx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="rx_coreclkin" internal="rx_coreclkin" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="xcvr_native_a10_0.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_enh_blk_lock"
+ internal="xcvr_native_a10_0.rx_enh_blk_lock"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
+ </interface>
+ <interface
+ name="rx_enh_data_valid"
+ internal="xcvr_native_a10_0.rx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_del"
+ internal="xcvr_native_a10_0.rx_enh_fifo_del"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_del" internal="rx_enh_fifo_del" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.rx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_empty" internal="rx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_full"
+ internal="xcvr_native_a10_0.rx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_full" internal="rx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_insert"
+ internal="xcvr_native_a10_0.rx_enh_fifo_insert"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_insert" internal="rx_enh_fifo_insert" />
+ </interface>
+ <interface
+ name="rx_enh_highber"
+ internal="xcvr_native_a10_0.rx_enh_highber"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_highber" internal="rx_enh_highber" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="xcvr_native_a10_0.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_is_lockedtoref"
+ internal="xcvr_native_a10_0.rx_is_lockedtoref"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtoref" internal="rx_is_lockedtoref" />
+ </interface>
+ <interface
+ name="rx_parallel_data"
+ internal="xcvr_native_a10_0.rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_parallel_data" internal="rx_parallel_data" />
+ </interface>
+ <interface
+ name="rx_prbs_done"
+ internal="xcvr_native_a10_0.rx_prbs_done"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_done" internal="rx_prbs_done" />
+ </interface>
+ <interface
+ name="rx_prbs_err"
+ internal="xcvr_native_a10_0.rx_prbs_err"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err" internal="rx_prbs_err" />
+ </interface>
+ <interface
+ name="rx_prbs_err_clr"
+ internal="xcvr_native_a10_0.rx_prbs_err_clr"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err_clr" internal="rx_prbs_err_clr" />
+ </interface>
+ <interface
+ name="rx_serial_data"
+ internal="xcvr_native_a10_0.rx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_serial_data" internal="rx_serial_data" />
+ </interface>
+ <interface
+ name="rx_seriallpbken"
+ internal="xcvr_native_a10_0.rx_seriallpbken"
+ type="conduit"
+ dir="end">
+ <port name="rx_seriallpbken" internal="rx_seriallpbken" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="xcvr_native_a10_0.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="xcvr_native_a10_0.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_clkout"
+ internal="xcvr_native_a10_0.tx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="tx_clkout" internal="tx_clkout" />
+ </interface>
+ <interface
+ name="tx_control"
+ internal="xcvr_native_a10_0.tx_control"
+ type="conduit"
+ dir="end">
+ <port name="tx_control" internal="tx_control" />
+ </interface>
+ <interface
+ name="tx_coreclkin"
+ internal="xcvr_native_a10_0.tx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="tx_coreclkin" internal="tx_coreclkin" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="xcvr_native_a10_0.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_enh_data_valid"
+ internal="xcvr_native_a10_0.tx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_empty" internal="tx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_full"
+ internal="xcvr_native_a10_0.tx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_full" internal="tx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pempty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pempty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pempty" internal="tx_enh_fifo_pempty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pfull"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pfull"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pfull" internal="tx_enh_fifo_pfull" />
+ </interface>
+ <interface
+ name="tx_err_ins"
+ internal="xcvr_native_a10_0.tx_err_ins"
+ type="conduit"
+ dir="end">
+ <port name="tx_err_ins" internal="tx_err_ins" />
+ </interface>
+ <interface
+ name="tx_parallel_data"
+ internal="xcvr_native_a10_0.tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_parallel_data" internal="tx_parallel_data" />
+ </interface>
+ <interface name="tx_pma_clkout" internal="xcvr_native_a10_0.tx_pma_clkout" />
+ <interface
+ name="tx_pma_div_clkout"
+ internal="xcvr_native_a10_0.tx_pma_div_clkout" />
+ <interface
+ name="tx_serial_clk0"
+ internal="xcvr_native_a10_0.tx_serial_clk0"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_clk0" internal="tx_serial_clk0" />
+ </interface>
+ <interface
+ name="tx_serial_data"
+ internal="xcvr_native_a10_0.tx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_data" internal="tx_serial_data" />
+ </interface>
+ <interface
+ name="unused_rx_control"
+ internal="xcvr_native_a10_0.unused_rx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_control" internal="unused_rx_control" />
+ </interface>
+ <interface
+ name="unused_rx_parallel_data"
+ internal="xcvr_native_a10_0.unused_rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
+ </interface>
+ <interface
+ name="unused_tx_control"
+ internal="xcvr_native_a10_0.unused_tx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_control" internal="unused_tx_control" />
+ </interface>
+ <interface
+ name="unused_tx_parallel_data"
+ internal="xcvr_native_a10_0.unused_tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
+ </interface>
+ <module
+ name="xcvr_native_a10_0"
+ kind="altera_xcvr_native_a10"
+ version="19.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="anlg_enable_rx_default_ovr" value="0" />
+ <parameter name="anlg_enable_tx_default_ovr" value="0" />
+ <parameter name="anlg_link" value="sr" />
+ <parameter name="anlg_rx_adp_ctle_acgain_4s">radp_ctle_acgain_4s_1</parameter>
+ <parameter name="anlg_rx_adp_ctle_eqz_1s_sel">radp_ctle_eqz_1s_sel_3</parameter>
+ <parameter name="anlg_rx_adp_dfe_fxtap1" value="radp_dfe_fxtap1_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap10" value="radp_dfe_fxtap10_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap11" value="radp_dfe_fxtap11_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap2" value="radp_dfe_fxtap2_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap3" value="radp_dfe_fxtap3_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap4" value="radp_dfe_fxtap4_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap5" value="radp_dfe_fxtap5_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap6" value="radp_dfe_fxtap6_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap7" value="radp_dfe_fxtap7_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap8" value="radp_dfe_fxtap8_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap9" value="radp_dfe_fxtap9_0" />
+ <parameter name="anlg_rx_adp_vga_sel" value="radp_vga_sel_2" />
+ <parameter name="anlg_rx_eq_dc_gain_trim" value="stg2_gain7" />
+ <parameter name="anlg_rx_one_stage_enable" value="s1_mode" />
+ <parameter name="anlg_rx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_analog_mode" value="user_custom" />
+ <parameter name="anlg_tx_compensation_en" value="enable" />
+ <parameter name="anlg_tx_pre_emp_sign_1st_post_tap" value="fir_post_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_2nd_post_tap" value="fir_post_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_1t" value="fir_pre_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_2t" value="fir_pre_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_1st_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_2nd_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_1t" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_2t" value="0" />
+ <parameter name="anlg_tx_slew_rate_ctrl" value="slew_r7" />
+ <parameter name="anlg_tx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_vod_output_swing_ctrl" value="0" />
+ <parameter name="anlg_voltage" value="1_1V" />
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="bonded_mode" value="not_bonded" />
+ <parameter name="cdr_refclk_cnt" value="1" />
+ <parameter name="cdr_refclk_select" value="0" />
+ <parameter name="channels" value="4" />
+ <parameter name="design_environment" value="NATIVE" />
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="disable_continuous_dfe" value="false" />
+ <parameter name="duplex_mode" value="duplex" />
+ <parameter name="enable_analog_settings" value="0" />
+ <parameter name="enable_hard_reset" value="0" />
+ <parameter name="enable_hip" value="0" />
+ <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="enable_pcie_data_mask_option" value="0" />
+ <parameter name="enable_pcie_dfe_ip" value="false" />
+ <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
+ <parameter name="enable_port_pipe_rx_polarity" value="0" />
+ <parameter name="enable_port_rx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enable_port_rx_enh_blk_lock" value="1" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count_c10" value="0" />
+ <parameter name="enable_port_rx_enh_crc32_err" value="0" />
+ <parameter name="enable_port_rx_enh_data_valid" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_del" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_insert" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
+ <parameter name="enable_port_rx_enh_frame" value="0" />
+ <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_rx_enh_frame_lock" value="0" />
+ <parameter name="enable_port_rx_enh_highber" value="1" />
+ <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
+ <parameter name="enable_port_rx_is_lockedtodata" value="1" />
+ <parameter name="enable_port_rx_is_lockedtoref" value="1" />
+ <parameter name="enable_port_rx_pma_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_clkslip" value="0" />
+ <parameter name="enable_port_rx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_rx_polinv" value="0" />
+ <parameter name="enable_port_rx_seriallpbken" value="1" />
+ <parameter name="enable_port_rx_seriallpbken_tx" value="1" />
+ <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
+ <parameter name="enable_port_rx_std_bitslip" value="0" />
+ <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_rx_std_byterev_ena" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
+ <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_tx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_tx_enh_bitslip" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pempty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pfull" value="1" />
+ <parameter name="enable_port_tx_enh_frame" value="0" />
+ <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
+ <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_tx_pma_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_elecidle" value="0" />
+ <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_tx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_tx_pma_rxfound" value="0" />
+ <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
+ <parameter name="enable_port_tx_polinv" value="0" />
+ <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
+ <parameter name="enable_ports_adaptation" value="0" />
+ <parameter name="enable_ports_pipe_g3_analog" value="0" />
+ <parameter name="enable_ports_pipe_hclk" value="0" />
+ <parameter name="enable_ports_pipe_rx_elecidle" value="0" />
+ <parameter name="enable_ports_pipe_sw" value="0" />
+ <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
+ <parameter name="enable_ports_rx_manual_ppm" value="0" />
+ <parameter name="enable_ports_rx_prbs" value="1" />
+ <parameter name="enable_simple_interface" value="1" />
+ <parameter name="enable_skp_ports" value="0" />
+ <parameter name="enable_split_interface" value="0" />
+ <parameter name="enable_transparent_pcs" value="0" />
+ <parameter name="enable_upi_pipeline_options" value="0" />
+ <parameter name="enh_low_latency_enable" value="0" />
+ <parameter name="enh_pcs_pma_width" value="32" />
+ <parameter name="enh_pld_pcs_width" value="66" />
+ <parameter name="enh_rx_64b66b_enable" value="1" />
+ <parameter name="enh_rx_bitslip_enable" value="0" />
+ <parameter name="enh_rx_blksync_enable" value="1" />
+ <parameter name="enh_rx_crcchk_enable" value="0" />
+ <parameter name="enh_rx_descram_enable" value="1" />
+ <parameter name="enh_rx_dispchk_enable" value="0" />
+ <parameter name="enh_rx_frmsync_enable" value="0" />
+ <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
+ <parameter name="enh_rx_krfec_err_mark_enable" value="0" />
+ <parameter name="enh_rx_krfec_err_mark_type" value="10G" />
+ <parameter name="enh_rx_polinv_enable" value="0" />
+ <parameter name="enh_rxfifo_align_del" value="0" />
+ <parameter name="enh_rxfifo_control_del" value="0" />
+ <parameter name="enh_rxfifo_mode" value="10GBase-R" />
+ <parameter name="enh_rxfifo_pempty" value="2" />
+ <parameter name="enh_rxfifo_pfull" value="23" />
+ <parameter name="enh_rxtxfifo_double_width" value="0" />
+ <parameter name="enh_tx_64b66b_enable" value="1" />
+ <parameter name="enh_tx_bitslip_enable" value="0" />
+ <parameter name="enh_tx_crcerr_enable" value="0" />
+ <parameter name="enh_tx_crcgen_enable" value="0" />
+ <parameter name="enh_tx_dispgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_burst_enable" value="0" />
+ <parameter name="enh_tx_frmgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
+ <parameter name="enh_tx_krfec_burst_err_enable" value="0" />
+ <parameter name="enh_tx_krfec_burst_err_len" value="1" />
+ <parameter name="enh_tx_polinv_enable" value="0" />
+ <parameter name="enh_tx_randomdispbit_enable" value="0" />
+ <parameter name="enh_tx_scram_enable" value="1" />
+ <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_tx_sh_err" value="0" />
+ <parameter name="enh_txfifo_mode" value="Phase compensation" />
+ <parameter name="enh_txfifo_pempty" value="2" />
+ <parameter name="enh_txfifo_pfull" value="11" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="number_physical_bonding_clocks" value="1" />
+ <parameter name="pcie_rate_match" value="Bypass" />
+ <parameter name="pcs_direct_width" value="8" />
+ <parameter name="pcs_tx_delay1_ctrl" value="delay1_path0" />
+ <parameter name="pcs_tx_delay1_data_sel" value="one_ff_delay" />
+ <parameter name="pcs_tx_delay2_ctrl" value="delay2_path0" />
+ <parameter name="pll_select" value="0" />
+ <parameter name="plls" value="1" />
+ <parameter name="pma_mode" value="basic" />
+ <parameter name="protocol_mode" value="teng_baser_mode" />
+ <parameter name="rcfg_enable" value="1" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="1" />
+ <parameter name="rcfg_iface_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="1" />
+ <parameter name="rcfg_mif_file_enable" value="1" />
+ <parameter name="rcfg_multi_enable" value="0" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_data0" value="" />
+ <parameter name="rcfg_profile_data1" value="" />
+ <parameter name="rcfg_profile_data2" value="" />
+ <parameter name="rcfg_profile_data3" value="" />
+ <parameter name="rcfg_profile_data4" value="" />
+ <parameter name="rcfg_profile_data5" value="" />
+ <parameter name="rcfg_profile_data6" value="" />
+ <parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_shared" value="1" />
+ <parameter name="rcfg_sv_file_enable" value="1" />
+ <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
+ <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
+ <parameter name="rx_pma_dfe_fixed_taps" value="3" />
+ <parameter name="rx_pma_div_clkout_divider" value="0" />
+ <parameter name="rx_ppm_detect_threshold" value="1000" />
+ <parameter name="set_capability_reg_enable" value="1" />
+ <parameter name="set_cdr_refclk_freq" value="644.531250" />
+ <parameter name="set_csr_soft_logic_enable" value="1" />
+ <parameter name="set_data_rate" value="10312.5" />
+ <parameter name="set_disconnect_analog_resets" value="0" />
+ <parameter name="set_embedded_debug_enable" value="0" />
+ <parameter name="set_enable_calibration" value="0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_odi_soft_logic_enable" value="0" />
+ <parameter name="set_pcs_bonding_master" value="Auto" />
+ <parameter name="set_prbs_soft_logic_enable" value="1" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="sim_reduced_counters" value="false" />
+ <parameter name="std_data_mask_count_multi" value="0" />
+ <parameter name="std_low_latency_bypass_enable" value="0" />
+ <parameter name="std_pcs_pma_width" value="10" />
+ <parameter name="std_rx_8b10b_enable" value="0" />
+ <parameter name="std_rx_bitrev_enable" value="0" />
+ <parameter name="std_rx_byte_deser_mode" value="Disabled" />
+ <parameter name="std_rx_byterev_enable" value="0" />
+ <parameter name="std_rx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_rx_polinv_enable" value="0" />
+ <parameter name="std_rx_rmfifo_mode" value="disabled" />
+ <parameter name="std_rx_rmfifo_pattern_n" value="0" />
+ <parameter name="std_rx_rmfifo_pattern_p" value="0" />
+ <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
+ <parameter name="std_rx_word_aligner_mode" value="bitslip" />
+ <parameter name="std_rx_word_aligner_pattern" value="0" />
+ <parameter name="std_rx_word_aligner_pattern_len" value="7" />
+ <parameter name="std_rx_word_aligner_renumber" value="3" />
+ <parameter name="std_rx_word_aligner_rgnumber" value="3" />
+ <parameter name="std_rx_word_aligner_rknumber" value="3" />
+ <parameter name="std_rx_word_aligner_rvnumber" value="0" />
+ <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
+ <parameter name="std_tx_8b10b_enable" value="0" />
+ <parameter name="std_tx_bitrev_enable" value="0" />
+ <parameter name="std_tx_bitslip_enable" value="0" />
+ <parameter name="std_tx_byte_ser_mode" value="Disabled" />
+ <parameter name="std_tx_byterev_enable" value="0" />
+ <parameter name="std_tx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="tx_pma_clk_div" value="1" />
+ <parameter name="tx_pma_div_clkout_divider" value="33" />
+ <parameter name="validation_rule_select" value="" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..0cd5157ee40b2b4afba70f273e3ce4a86eddd40d
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_48/sim"
+
+
+ vcom "$IP_DIR/ip_arria10_e2sg_phy_10gbase_r_48.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..8710ab291e08cf3c9158453cd707480252a5b744
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_phy_10gbase_r_48
+hdl_library_clause_name = ip_arria10_e2sg_phy_10gbase_r_48_altera_xcvr_native_a10_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_native_a10_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_48/ip_arria10_e2sg_phy_10gbase_r_48.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_phy_10gbase_r_48.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/ip_arria10_e2sg_phy_10gbase_r_48.qsys b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/ip_arria10_e2sg_phy_10gbase_r_48.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..f4ae71f53f4e6df729599c1f522fdc0a2b5fd3f3
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/ip_arria10_e2sg_phy_10gbase_r_48.qsys
@@ -0,0 +1,627 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_phy_10gbase_r_48">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element xcvr_native_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="reconfig_avmm"
+ internal="xcvr_native_a10_0.reconfig_avmm"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_address" internal="reconfig_address" />
+ <port name="reconfig_read" internal="reconfig_read" />
+ <port name="reconfig_readdata" internal="reconfig_readdata" />
+ <port name="reconfig_waitrequest" internal="reconfig_waitrequest" />
+ <port name="reconfig_write" internal="reconfig_write" />
+ <port name="reconfig_writedata" internal="reconfig_writedata" />
+ </interface>
+ <interface
+ name="reconfig_clk"
+ internal="xcvr_native_a10_0.reconfig_clk"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_clk" internal="reconfig_clk" />
+ </interface>
+ <interface
+ name="reconfig_reset"
+ internal="xcvr_native_a10_0.reconfig_reset"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_reset" internal="reconfig_reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="xcvr_native_a10_0.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="xcvr_native_a10_0.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_cdr_refclk0"
+ internal="xcvr_native_a10_0.rx_cdr_refclk0"
+ type="conduit"
+ dir="end">
+ <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
+ </interface>
+ <interface
+ name="rx_clkout"
+ internal="xcvr_native_a10_0.rx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="rx_clkout" internal="rx_clkout" />
+ </interface>
+ <interface
+ name="rx_control"
+ internal="xcvr_native_a10_0.rx_control"
+ type="conduit"
+ dir="end">
+ <port name="rx_control" internal="rx_control" />
+ </interface>
+ <interface
+ name="rx_coreclkin"
+ internal="xcvr_native_a10_0.rx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="rx_coreclkin" internal="rx_coreclkin" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="xcvr_native_a10_0.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_enh_blk_lock"
+ internal="xcvr_native_a10_0.rx_enh_blk_lock"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
+ </interface>
+ <interface
+ name="rx_enh_data_valid"
+ internal="xcvr_native_a10_0.rx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_del"
+ internal="xcvr_native_a10_0.rx_enh_fifo_del"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_del" internal="rx_enh_fifo_del" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.rx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_empty" internal="rx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_full"
+ internal="xcvr_native_a10_0.rx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_full" internal="rx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_insert"
+ internal="xcvr_native_a10_0.rx_enh_fifo_insert"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_insert" internal="rx_enh_fifo_insert" />
+ </interface>
+ <interface
+ name="rx_enh_highber"
+ internal="xcvr_native_a10_0.rx_enh_highber"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_highber" internal="rx_enh_highber" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="xcvr_native_a10_0.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_is_lockedtoref"
+ internal="xcvr_native_a10_0.rx_is_lockedtoref"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtoref" internal="rx_is_lockedtoref" />
+ </interface>
+ <interface
+ name="rx_parallel_data"
+ internal="xcvr_native_a10_0.rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_parallel_data" internal="rx_parallel_data" />
+ </interface>
+ <interface
+ name="rx_prbs_done"
+ internal="xcvr_native_a10_0.rx_prbs_done"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_done" internal="rx_prbs_done" />
+ </interface>
+ <interface
+ name="rx_prbs_err"
+ internal="xcvr_native_a10_0.rx_prbs_err"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err" internal="rx_prbs_err" />
+ </interface>
+ <interface
+ name="rx_prbs_err_clr"
+ internal="xcvr_native_a10_0.rx_prbs_err_clr"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err_clr" internal="rx_prbs_err_clr" />
+ </interface>
+ <interface
+ name="rx_serial_data"
+ internal="xcvr_native_a10_0.rx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_serial_data" internal="rx_serial_data" />
+ </interface>
+ <interface
+ name="rx_seriallpbken"
+ internal="xcvr_native_a10_0.rx_seriallpbken"
+ type="conduit"
+ dir="end">
+ <port name="rx_seriallpbken" internal="rx_seriallpbken" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="xcvr_native_a10_0.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="xcvr_native_a10_0.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_clkout"
+ internal="xcvr_native_a10_0.tx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="tx_clkout" internal="tx_clkout" />
+ </interface>
+ <interface
+ name="tx_control"
+ internal="xcvr_native_a10_0.tx_control"
+ type="conduit"
+ dir="end">
+ <port name="tx_control" internal="tx_control" />
+ </interface>
+ <interface
+ name="tx_coreclkin"
+ internal="xcvr_native_a10_0.tx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="tx_coreclkin" internal="tx_coreclkin" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="xcvr_native_a10_0.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_enh_data_valid"
+ internal="xcvr_native_a10_0.tx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_empty" internal="tx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_full"
+ internal="xcvr_native_a10_0.tx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_full" internal="tx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pempty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pempty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pempty" internal="tx_enh_fifo_pempty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pfull"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pfull"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pfull" internal="tx_enh_fifo_pfull" />
+ </interface>
+ <interface
+ name="tx_err_ins"
+ internal="xcvr_native_a10_0.tx_err_ins"
+ type="conduit"
+ dir="end">
+ <port name="tx_err_ins" internal="tx_err_ins" />
+ </interface>
+ <interface
+ name="tx_parallel_data"
+ internal="xcvr_native_a10_0.tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_parallel_data" internal="tx_parallel_data" />
+ </interface>
+ <interface name="tx_pma_clkout" internal="xcvr_native_a10_0.tx_pma_clkout" />
+ <interface
+ name="tx_pma_div_clkout"
+ internal="xcvr_native_a10_0.tx_pma_div_clkout" />
+ <interface
+ name="tx_serial_clk0"
+ internal="xcvr_native_a10_0.tx_serial_clk0"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_clk0" internal="tx_serial_clk0" />
+ </interface>
+ <interface
+ name="tx_serial_data"
+ internal="xcvr_native_a10_0.tx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_data" internal="tx_serial_data" />
+ </interface>
+ <interface
+ name="unused_rx_control"
+ internal="xcvr_native_a10_0.unused_rx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_control" internal="unused_rx_control" />
+ </interface>
+ <interface
+ name="unused_rx_parallel_data"
+ internal="xcvr_native_a10_0.unused_rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
+ </interface>
+ <interface
+ name="unused_tx_control"
+ internal="xcvr_native_a10_0.unused_tx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_control" internal="unused_tx_control" />
+ </interface>
+ <interface
+ name="unused_tx_parallel_data"
+ internal="xcvr_native_a10_0.unused_tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
+ </interface>
+ <module
+ name="xcvr_native_a10_0"
+ kind="altera_xcvr_native_a10"
+ version="19.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="anlg_enable_rx_default_ovr" value="0" />
+ <parameter name="anlg_enable_tx_default_ovr" value="0" />
+ <parameter name="anlg_link" value="sr" />
+ <parameter name="anlg_rx_adp_ctle_acgain_4s">radp_ctle_acgain_4s_1</parameter>
+ <parameter name="anlg_rx_adp_ctle_eqz_1s_sel">radp_ctle_eqz_1s_sel_3</parameter>
+ <parameter name="anlg_rx_adp_dfe_fxtap1" value="radp_dfe_fxtap1_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap10" value="radp_dfe_fxtap10_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap11" value="radp_dfe_fxtap11_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap2" value="radp_dfe_fxtap2_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap3" value="radp_dfe_fxtap3_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap4" value="radp_dfe_fxtap4_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap5" value="radp_dfe_fxtap5_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap6" value="radp_dfe_fxtap6_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap7" value="radp_dfe_fxtap7_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap8" value="radp_dfe_fxtap8_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap9" value="radp_dfe_fxtap9_0" />
+ <parameter name="anlg_rx_adp_vga_sel" value="radp_vga_sel_2" />
+ <parameter name="anlg_rx_eq_dc_gain_trim" value="stg2_gain7" />
+ <parameter name="anlg_rx_one_stage_enable" value="s1_mode" />
+ <parameter name="anlg_rx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_analog_mode" value="user_custom" />
+ <parameter name="anlg_tx_compensation_en" value="enable" />
+ <parameter name="anlg_tx_pre_emp_sign_1st_post_tap" value="fir_post_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_2nd_post_tap" value="fir_post_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_1t" value="fir_pre_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_2t" value="fir_pre_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_1st_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_2nd_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_1t" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_2t" value="0" />
+ <parameter name="anlg_tx_slew_rate_ctrl" value="slew_r7" />
+ <parameter name="anlg_tx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_vod_output_swing_ctrl" value="0" />
+ <parameter name="anlg_voltage" value="1_1V" />
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="bonded_mode" value="not_bonded" />
+ <parameter name="cdr_refclk_cnt" value="1" />
+ <parameter name="cdr_refclk_select" value="0" />
+ <parameter name="channels" value="48" />
+ <parameter name="design_environment" value="NATIVE" />
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="disable_continuous_dfe" value="false" />
+ <parameter name="duplex_mode" value="duplex" />
+ <parameter name="enable_analog_settings" value="0" />
+ <parameter name="enable_hard_reset" value="0" />
+ <parameter name="enable_hip" value="0" />
+ <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="enable_pcie_data_mask_option" value="0" />
+ <parameter name="enable_pcie_dfe_ip" value="false" />
+ <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
+ <parameter name="enable_port_pipe_rx_polarity" value="0" />
+ <parameter name="enable_port_rx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enable_port_rx_enh_blk_lock" value="1" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count_c10" value="0" />
+ <parameter name="enable_port_rx_enh_crc32_err" value="0" />
+ <parameter name="enable_port_rx_enh_data_valid" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_del" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_insert" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
+ <parameter name="enable_port_rx_enh_frame" value="0" />
+ <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_rx_enh_frame_lock" value="0" />
+ <parameter name="enable_port_rx_enh_highber" value="1" />
+ <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
+ <parameter name="enable_port_rx_is_lockedtodata" value="1" />
+ <parameter name="enable_port_rx_is_lockedtoref" value="1" />
+ <parameter name="enable_port_rx_pma_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_clkslip" value="0" />
+ <parameter name="enable_port_rx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_rx_polinv" value="0" />
+ <parameter name="enable_port_rx_seriallpbken" value="1" />
+ <parameter name="enable_port_rx_seriallpbken_tx" value="1" />
+ <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
+ <parameter name="enable_port_rx_std_bitslip" value="0" />
+ <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_rx_std_byterev_ena" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
+ <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_tx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_tx_enh_bitslip" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pempty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pfull" value="1" />
+ <parameter name="enable_port_tx_enh_frame" value="0" />
+ <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
+ <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_tx_pma_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_elecidle" value="0" />
+ <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_tx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_tx_pma_rxfound" value="0" />
+ <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
+ <parameter name="enable_port_tx_polinv" value="0" />
+ <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
+ <parameter name="enable_ports_adaptation" value="0" />
+ <parameter name="enable_ports_pipe_g3_analog" value="0" />
+ <parameter name="enable_ports_pipe_hclk" value="0" />
+ <parameter name="enable_ports_pipe_rx_elecidle" value="0" />
+ <parameter name="enable_ports_pipe_sw" value="0" />
+ <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
+ <parameter name="enable_ports_rx_manual_ppm" value="0" />
+ <parameter name="enable_ports_rx_prbs" value="1" />
+ <parameter name="enable_simple_interface" value="1" />
+ <parameter name="enable_skp_ports" value="0" />
+ <parameter name="enable_split_interface" value="0" />
+ <parameter name="enable_transparent_pcs" value="0" />
+ <parameter name="enable_upi_pipeline_options" value="0" />
+ <parameter name="enh_low_latency_enable" value="0" />
+ <parameter name="enh_pcs_pma_width" value="32" />
+ <parameter name="enh_pld_pcs_width" value="66" />
+ <parameter name="enh_rx_64b66b_enable" value="1" />
+ <parameter name="enh_rx_bitslip_enable" value="0" />
+ <parameter name="enh_rx_blksync_enable" value="1" />
+ <parameter name="enh_rx_crcchk_enable" value="0" />
+ <parameter name="enh_rx_descram_enable" value="1" />
+ <parameter name="enh_rx_dispchk_enable" value="0" />
+ <parameter name="enh_rx_frmsync_enable" value="0" />
+ <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
+ <parameter name="enh_rx_krfec_err_mark_enable" value="0" />
+ <parameter name="enh_rx_krfec_err_mark_type" value="10G" />
+ <parameter name="enh_rx_polinv_enable" value="0" />
+ <parameter name="enh_rxfifo_align_del" value="0" />
+ <parameter name="enh_rxfifo_control_del" value="0" />
+ <parameter name="enh_rxfifo_mode" value="10GBase-R" />
+ <parameter name="enh_rxfifo_pempty" value="2" />
+ <parameter name="enh_rxfifo_pfull" value="23" />
+ <parameter name="enh_rxtxfifo_double_width" value="0" />
+ <parameter name="enh_tx_64b66b_enable" value="1" />
+ <parameter name="enh_tx_bitslip_enable" value="0" />
+ <parameter name="enh_tx_crcerr_enable" value="0" />
+ <parameter name="enh_tx_crcgen_enable" value="0" />
+ <parameter name="enh_tx_dispgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_burst_enable" value="0" />
+ <parameter name="enh_tx_frmgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
+ <parameter name="enh_tx_krfec_burst_err_enable" value="0" />
+ <parameter name="enh_tx_krfec_burst_err_len" value="1" />
+ <parameter name="enh_tx_polinv_enable" value="0" />
+ <parameter name="enh_tx_randomdispbit_enable" value="0" />
+ <parameter name="enh_tx_scram_enable" value="1" />
+ <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_tx_sh_err" value="0" />
+ <parameter name="enh_txfifo_mode" value="Phase compensation" />
+ <parameter name="enh_txfifo_pempty" value="2" />
+ <parameter name="enh_txfifo_pfull" value="11" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="number_physical_bonding_clocks" value="1" />
+ <parameter name="pcie_rate_match" value="Bypass" />
+ <parameter name="pcs_direct_width" value="8" />
+ <parameter name="pcs_tx_delay1_ctrl" value="delay1_path0" />
+ <parameter name="pcs_tx_delay1_data_sel" value="one_ff_delay" />
+ <parameter name="pcs_tx_delay2_ctrl" value="delay2_path0" />
+ <parameter name="pll_select" value="0" />
+ <parameter name="plls" value="1" />
+ <parameter name="pma_mode" value="basic" />
+ <parameter name="protocol_mode" value="teng_baser_mode" />
+ <parameter name="rcfg_enable" value="1" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="1" />
+ <parameter name="rcfg_iface_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="1" />
+ <parameter name="rcfg_mif_file_enable" value="1" />
+ <parameter name="rcfg_multi_enable" value="0" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_data0" value="" />
+ <parameter name="rcfg_profile_data1" value="" />
+ <parameter name="rcfg_profile_data2" value="" />
+ <parameter name="rcfg_profile_data3" value="" />
+ <parameter name="rcfg_profile_data4" value="" />
+ <parameter name="rcfg_profile_data5" value="" />
+ <parameter name="rcfg_profile_data6" value="" />
+ <parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_shared" value="1" />
+ <parameter name="rcfg_sv_file_enable" value="1" />
+ <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
+ <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
+ <parameter name="rx_pma_dfe_fixed_taps" value="3" />
+ <parameter name="rx_pma_div_clkout_divider" value="0" />
+ <parameter name="rx_ppm_detect_threshold" value="1000" />
+ <parameter name="set_capability_reg_enable" value="1" />
+ <parameter name="set_cdr_refclk_freq" value="644.531250" />
+ <parameter name="set_csr_soft_logic_enable" value="1" />
+ <parameter name="set_data_rate" value="10312.5" />
+ <parameter name="set_disconnect_analog_resets" value="0" />
+ <parameter name="set_embedded_debug_enable" value="0" />
+ <parameter name="set_enable_calibration" value="0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_odi_soft_logic_enable" value="0" />
+ <parameter name="set_pcs_bonding_master" value="Auto" />
+ <parameter name="set_prbs_soft_logic_enable" value="1" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="sim_reduced_counters" value="false" />
+ <parameter name="std_data_mask_count_multi" value="0" />
+ <parameter name="std_low_latency_bypass_enable" value="0" />
+ <parameter name="std_pcs_pma_width" value="10" />
+ <parameter name="std_rx_8b10b_enable" value="0" />
+ <parameter name="std_rx_bitrev_enable" value="0" />
+ <parameter name="std_rx_byte_deser_mode" value="Disabled" />
+ <parameter name="std_rx_byterev_enable" value="0" />
+ <parameter name="std_rx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_rx_polinv_enable" value="0" />
+ <parameter name="std_rx_rmfifo_mode" value="disabled" />
+ <parameter name="std_rx_rmfifo_pattern_n" value="0" />
+ <parameter name="std_rx_rmfifo_pattern_p" value="0" />
+ <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
+ <parameter name="std_rx_word_aligner_mode" value="bitslip" />
+ <parameter name="std_rx_word_aligner_pattern" value="0" />
+ <parameter name="std_rx_word_aligner_pattern_len" value="7" />
+ <parameter name="std_rx_word_aligner_renumber" value="3" />
+ <parameter name="std_rx_word_aligner_rgnumber" value="3" />
+ <parameter name="std_rx_word_aligner_rknumber" value="3" />
+ <parameter name="std_rx_word_aligner_rvnumber" value="0" />
+ <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
+ <parameter name="std_tx_8b10b_enable" value="0" />
+ <parameter name="std_tx_bitrev_enable" value="0" />
+ <parameter name="std_tx_bitslip_enable" value="0" />
+ <parameter name="std_tx_byte_ser_mode" value="Disabled" />
+ <parameter name="std_tx_byterev_enable" value="0" />
+ <parameter name="std_tx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="tx_pma_clk_div" value="1" />
+ <parameter name="tx_pma_div_clkout_divider" value="33" />
+ <parameter name="validation_rule_select" value="" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/pll_clk125/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d3104e52cfcc79d3cbdc527a1c4f3258379ff5b5
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk125/compile_ip.tcl
@@ -0,0 +1,34 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk125/sim"
+
+ vcom "$IP_DIR/ip_arria10_e2sg_pll_clk125.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/pll_clk125/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..fda6b8e59ccd86456ce2815814c9473978cba1a9
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk125/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_pll_clk125
+hdl_library_clause_name = ip_arria10_e2sg_pll_clk125_altera_iopll_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_iopll_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/pll_clk125/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_pll_clk125/ip_arria10_e2sg_pll_clk125.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_pll_clk125.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk125/ip_arria10_e2sg_pll_clk125.qsys b/libraries/technology/ip_arria10_e2sg/pll_clk125/ip_arria10_e2sg_pll_clk125.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..68b20e0418e9fe3d37c7967963bc857821890374
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk125/ip_arria10_e2sg_pll_clk125.qsys
@@ -0,0 +1,376 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_pll_clk125">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element iopll_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>outclk0</key>
+ <value>
+ <connectionPointName>outclk0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>20000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk1</key>
+ <value>
+ <connectionPointName>outclk1</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>50000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk2</key>
+ <value>
+ <connectionPointName>outclk2</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk3</key>
+ <value>
+ <connectionPointName>outclk3</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="locked" internal="iopll_0.locked" type="conduit" dir="end">
+ <port name="locked" internal="locked" />
+ </interface>
+ <interface name="outclk0" internal="iopll_0.outclk0" type="clock" dir="start">
+ <port name="outclk_0" internal="outclk_0" />
+ </interface>
+ <interface name="outclk1" internal="iopll_0.outclk1" type="clock" dir="start">
+ <port name="outclk_1" internal="outclk_1" />
+ </interface>
+ <interface name="outclk2" internal="iopll_0.outclk2" type="clock" dir="start">
+ <port name="outclk_2" internal="outclk_2" />
+ </interface>
+ <interface name="outclk3" internal="iopll_0.outclk3" type="clock" dir="start">
+ <port name="outclk_3" internal="outclk_3" />
+ </interface>
+ <interface name="refclk" internal="iopll_0.refclk" type="clock" dir="end">
+ <port name="refclk" internal="refclk" />
+ </interface>
+ <interface name="reset" internal="iopll_0.reset" type="reset" dir="end">
+ <port name="rst" internal="rst" />
+ </interface>
+ <module
+ name="iopll_0"
+ kind="altera_iopll"
+ version="19.3.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="gui_active_clk" value="false" />
+ <parameter name="gui_c_cnt_in_src0">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src1">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src2">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src3">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src4">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src5">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src6">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src7">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src8">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_cal_code_hex_file" value="iossm.hex" />
+ <parameter name="gui_cal_converge" value="false" />
+ <parameter name="gui_cal_error" value="cal_clean" />
+ <parameter name="gui_cascade_counter0" value="false" />
+ <parameter name="gui_cascade_counter1" value="false" />
+ <parameter name="gui_cascade_counter10" value="false" />
+ <parameter name="gui_cascade_counter11" value="false" />
+ <parameter name="gui_cascade_counter12" value="false" />
+ <parameter name="gui_cascade_counter13" value="false" />
+ <parameter name="gui_cascade_counter14" value="false" />
+ <parameter name="gui_cascade_counter15" value="false" />
+ <parameter name="gui_cascade_counter16" value="false" />
+ <parameter name="gui_cascade_counter17" value="false" />
+ <parameter name="gui_cascade_counter2" value="false" />
+ <parameter name="gui_cascade_counter3" value="false" />
+ <parameter name="gui_cascade_counter4" value="false" />
+ <parameter name="gui_cascade_counter5" value="false" />
+ <parameter name="gui_cascade_counter6" value="false" />
+ <parameter name="gui_cascade_counter7" value="false" />
+ <parameter name="gui_cascade_counter8" value="false" />
+ <parameter name="gui_cascade_counter9" value="false" />
+ <parameter name="gui_cascade_outclk_index" value="0" />
+ <parameter name="gui_clk_bad" value="false" />
+ <parameter name="gui_clock_name_global" value="false" />
+ <parameter name="gui_clock_name_string0" value="pll_clk20" />
+ <parameter name="gui_clock_name_string1" value="pll_clk50" />
+ <parameter name="gui_clock_name_string10" value="outclk10" />
+ <parameter name="gui_clock_name_string11" value="outclk11" />
+ <parameter name="gui_clock_name_string12" value="outclk12" />
+ <parameter name="gui_clock_name_string13" value="outclk13" />
+ <parameter name="gui_clock_name_string14" value="outclk14" />
+ <parameter name="gui_clock_name_string15" value="outclk15" />
+ <parameter name="gui_clock_name_string16" value="outclk16" />
+ <parameter name="gui_clock_name_string17" value="outclk17" />
+ <parameter name="gui_clock_name_string2" value="pll_clk100" />
+ <parameter name="gui_clock_name_string3" value="pll_clk125" />
+ <parameter name="gui_clock_name_string4" value="outclk4" />
+ <parameter name="gui_clock_name_string5" value="outclk5" />
+ <parameter name="gui_clock_name_string6" value="outclk6" />
+ <parameter name="gui_clock_name_string7" value="outclk7" />
+ <parameter name="gui_clock_name_string8" value="outclk8" />
+ <parameter name="gui_clock_name_string9" value="outclk9" />
+ <parameter name="gui_clock_to_compensate" value="0" />
+ <parameter name="gui_debug_mode" value="false" />
+ <parameter name="gui_divide_factor_c0" value="6" />
+ <parameter name="gui_divide_factor_c1" value="6" />
+ <parameter name="gui_divide_factor_c10" value="6" />
+ <parameter name="gui_divide_factor_c11" value="6" />
+ <parameter name="gui_divide_factor_c12" value="6" />
+ <parameter name="gui_divide_factor_c13" value="6" />
+ <parameter name="gui_divide_factor_c14" value="6" />
+ <parameter name="gui_divide_factor_c15" value="6" />
+ <parameter name="gui_divide_factor_c16" value="6" />
+ <parameter name="gui_divide_factor_c17" value="6" />
+ <parameter name="gui_divide_factor_c2" value="6" />
+ <parameter name="gui_divide_factor_c3" value="6" />
+ <parameter name="gui_divide_factor_c4" value="6" />
+ <parameter name="gui_divide_factor_c5" value="6" />
+ <parameter name="gui_divide_factor_c6" value="6" />
+ <parameter name="gui_divide_factor_c7" value="6" />
+ <parameter name="gui_divide_factor_c8" value="6" />
+ <parameter name="gui_divide_factor_c9" value="6" />
+ <parameter name="gui_divide_factor_n" value="1" />
+ <parameter name="gui_dps_cntr" value="C0" />
+ <parameter name="gui_dps_dir" value="Positive" />
+ <parameter name="gui_dps_num" value="1" />
+ <parameter name="gui_dsm_out_sel" value="1st_order" />
+ <parameter name="gui_duty_cycle0" value="50.0" />
+ <parameter name="gui_duty_cycle1" value="50.0" />
+ <parameter name="gui_duty_cycle10" value="50.0" />
+ <parameter name="gui_duty_cycle11" value="50.0" />
+ <parameter name="gui_duty_cycle12" value="50.0" />
+ <parameter name="gui_duty_cycle13" value="50.0" />
+ <parameter name="gui_duty_cycle14" value="50.0" />
+ <parameter name="gui_duty_cycle15" value="50.0" />
+ <parameter name="gui_duty_cycle16" value="50.0" />
+ <parameter name="gui_duty_cycle17" value="50.0" />
+ <parameter name="gui_duty_cycle2" value="50.0" />
+ <parameter name="gui_duty_cycle3" value="50.0" />
+ <parameter name="gui_duty_cycle4" value="50.0" />
+ <parameter name="gui_duty_cycle5" value="50.0" />
+ <parameter name="gui_duty_cycle6" value="50.0" />
+ <parameter name="gui_duty_cycle7" value="50.0" />
+ <parameter name="gui_duty_cycle8" value="50.0" />
+ <parameter name="gui_duty_cycle9" value="50.0" />
+ <parameter name="gui_en_adv_params" value="false" />
+ <parameter name="gui_en_dps_ports" value="false" />
+ <parameter name="gui_en_extclkout_ports" value="false" />
+ <parameter name="gui_en_lvds_ports" value="Disabled" />
+ <parameter name="gui_en_phout_ports" value="false" />
+ <parameter name="gui_en_reconf" value="false" />
+ <parameter name="gui_enable_cascade_in" value="false" />
+ <parameter name="gui_enable_cascade_out" value="false" />
+ <parameter name="gui_enable_mif_dps" value="false" />
+ <parameter name="gui_enable_output_counter_cascading" value="false" />
+ <parameter name="gui_enable_permit_cal" value="false" />
+ <parameter name="gui_existing_mif_file_path" value="~/pll.mif" />
+ <parameter name="gui_extclkout_0_source" value="C0" />
+ <parameter name="gui_extclkout_1_source" value="C0" />
+ <parameter name="gui_feedback_clock" value="Global Clock" />
+ <parameter name="gui_fix_vco_frequency" value="false" />
+ <parameter name="gui_fixed_vco_frequency" value="600.0" />
+ <parameter name="gui_fixed_vco_frequency_ps" value="1667.0" />
+ <parameter name="gui_frac_multiply_factor" value="1" />
+ <parameter name="gui_fractional_cout" value="32" />
+ <parameter name="gui_include_iossm" value="false" />
+ <parameter name="gui_location_type" value="I/O Bank" />
+ <parameter name="gui_lock_setting" value="Low Lock Time" />
+ <parameter name="gui_mif_config_name" value="unnamed" />
+ <parameter name="gui_mif_gen_options">Generate New MIF File</parameter>
+ <parameter name="gui_multiply_factor" value="6" />
+ <parameter name="gui_new_mif_file_path" value="~/pll.mif" />
+ <parameter name="gui_number_of_clocks" value="4" />
+ <parameter name="gui_operation_mode" value="direct" />
+ <parameter name="gui_output_clock_frequency0" value="20.0" />
+ <parameter name="gui_output_clock_frequency1" value="50.0" />
+ <parameter name="gui_output_clock_frequency10" value="100.0" />
+ <parameter name="gui_output_clock_frequency11" value="100.0" />
+ <parameter name="gui_output_clock_frequency12" value="100.0" />
+ <parameter name="gui_output_clock_frequency13" value="100.0" />
+ <parameter name="gui_output_clock_frequency14" value="100.0" />
+ <parameter name="gui_output_clock_frequency15" value="100.0" />
+ <parameter name="gui_output_clock_frequency16" value="100.0" />
+ <parameter name="gui_output_clock_frequency17" value="100.0" />
+ <parameter name="gui_output_clock_frequency2" value="100.0" />
+ <parameter name="gui_output_clock_frequency3" value="125.0" />
+ <parameter name="gui_output_clock_frequency4" value="100.0" />
+ <parameter name="gui_output_clock_frequency5" value="100.0" />
+ <parameter name="gui_output_clock_frequency6" value="100.0" />
+ <parameter name="gui_output_clock_frequency7" value="100.0" />
+ <parameter name="gui_output_clock_frequency8" value="100.0" />
+ <parameter name="gui_output_clock_frequency9" value="100.0" />
+ <parameter name="gui_output_clock_frequency_ps0" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps1" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps10" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps11" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps12" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps13" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps14" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps15" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps16" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps17" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps2" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps3" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps4" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps5" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps6" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps7" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps8" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps9" value="10000.0" />
+ <parameter name="gui_parameter_table_hex_file" value="seq_params_sim.hex" />
+ <parameter name="gui_phase_shift0" value="0.0" />
+ <parameter name="gui_phase_shift1" value="0.0" />
+ <parameter name="gui_phase_shift10" value="0.0" />
+ <parameter name="gui_phase_shift11" value="0.0" />
+ <parameter name="gui_phase_shift12" value="0.0" />
+ <parameter name="gui_phase_shift13" value="0.0" />
+ <parameter name="gui_phase_shift14" value="0.0" />
+ <parameter name="gui_phase_shift15" value="0.0" />
+ <parameter name="gui_phase_shift16" value="0.0" />
+ <parameter name="gui_phase_shift17" value="0.0" />
+ <parameter name="gui_phase_shift2" value="0.0" />
+ <parameter name="gui_phase_shift3" value="0.0" />
+ <parameter name="gui_phase_shift4" value="0.0" />
+ <parameter name="gui_phase_shift5" value="0.0" />
+ <parameter name="gui_phase_shift6" value="0.0" />
+ <parameter name="gui_phase_shift7" value="0.0" />
+ <parameter name="gui_phase_shift8" value="0.0" />
+ <parameter name="gui_phase_shift9" value="0.0" />
+ <parameter name="gui_phase_shift_deg0" value="0.0" />
+ <parameter name="gui_phase_shift_deg1" value="0.0" />
+ <parameter name="gui_phase_shift_deg10" value="0.0" />
+ <parameter name="gui_phase_shift_deg11" value="0.0" />
+ <parameter name="gui_phase_shift_deg12" value="0.0" />
+ <parameter name="gui_phase_shift_deg13" value="0.0" />
+ <parameter name="gui_phase_shift_deg14" value="0.0" />
+ <parameter name="gui_phase_shift_deg15" value="0.0" />
+ <parameter name="gui_phase_shift_deg16" value="0.0" />
+ <parameter name="gui_phase_shift_deg17" value="0.0" />
+ <parameter name="gui_phase_shift_deg2" value="0.0" />
+ <parameter name="gui_phase_shift_deg3" value="0.0" />
+ <parameter name="gui_phase_shift_deg4" value="0.0" />
+ <parameter name="gui_phase_shift_deg5" value="0.0" />
+ <parameter name="gui_phase_shift_deg6" value="0.0" />
+ <parameter name="gui_phase_shift_deg7" value="0.0" />
+ <parameter name="gui_phase_shift_deg8" value="0.0" />
+ <parameter name="gui_phase_shift_deg9" value="0.0" />
+ <parameter name="gui_phout_division" value="1" />
+ <parameter name="gui_pll_auto_reset" value="false" />
+ <parameter name="gui_pll_bandwidth_preset" value="Low" />
+ <parameter name="gui_pll_cal_done" value="false" />
+ <parameter name="gui_pll_cascading_mode" value="adjpllin" />
+ <parameter name="gui_pll_freqcal_en" value="true" />
+ <parameter name="gui_pll_freqcal_req_flag" value="true" />
+ <parameter name="gui_pll_m_cnt_in_src">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_pll_mode" value="Integer-N PLL" />
+ <parameter name="gui_pll_tclk_mux_en" value="false" />
+ <parameter name="gui_pll_tclk_sel" value="pll_tclk_m_src" />
+ <parameter name="gui_pll_type" value="S10_Simple" />
+ <parameter name="gui_pll_vco_freq_band_0">pll_freq_clk0_disabled</parameter>
+ <parameter name="gui_pll_vco_freq_band_1">pll_freq_clk1_disabled</parameter>
+ <parameter name="gui_prot_mode" value="UNUSED" />
+ <parameter name="gui_ps_units0" value="ps" />
+ <parameter name="gui_ps_units1" value="ps" />
+ <parameter name="gui_ps_units10" value="ps" />
+ <parameter name="gui_ps_units11" value="ps" />
+ <parameter name="gui_ps_units12" value="ps" />
+ <parameter name="gui_ps_units13" value="ps" />
+ <parameter name="gui_ps_units14" value="ps" />
+ <parameter name="gui_ps_units15" value="ps" />
+ <parameter name="gui_ps_units16" value="ps" />
+ <parameter name="gui_ps_units17" value="ps" />
+ <parameter name="gui_ps_units2" value="ps" />
+ <parameter name="gui_ps_units3" value="ps" />
+ <parameter name="gui_ps_units4" value="ps" />
+ <parameter name="gui_ps_units5" value="ps" />
+ <parameter name="gui_ps_units6" value="ps" />
+ <parameter name="gui_ps_units7" value="ps" />
+ <parameter name="gui_ps_units8" value="ps" />
+ <parameter name="gui_ps_units9" value="ps" />
+ <parameter name="gui_refclk1_frequency" value="100.0" />
+ <parameter name="gui_refclk_might_change" value="false" />
+ <parameter name="gui_refclk_switch" value="false" />
+ <parameter name="gui_reference_clock_frequency" value="125.0" />
+ <parameter name="gui_reference_clock_frequency_ps" value="10000.0" />
+ <parameter name="gui_skip_sdc_generation" value="false" />
+ <parameter name="gui_switchover_delay" value="0" />
+ <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+ <parameter name="gui_use_NDFB_modes" value="false" />
+ <parameter name="gui_use_coreclk" value="false" />
+ <parameter name="gui_use_locked" value="true" />
+ <parameter name="gui_use_logical" value="false" />
+ <parameter name="gui_usr_device_speed_grade" value="1" />
+ <parameter name="gui_vco_frequency" value="600.0" />
+ <parameter name="hp_qsys_scripting_mode" value="false" />
+ <parameter name="system_info_device_component" value="10AX115U3F45E2SG" />
+ <parameter name="system_info_device_family" value="Arria 10" />
+ <parameter name="system_info_device_speed_grade" value="2" />
+ <parameter name="system_part_trait_speed_grade" value="2" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/pll_clk200/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ef4a13259c720ebf73155d8d51d62c5a4d99469b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk200/compile_ip.tcl
@@ -0,0 +1,33 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk200/sim"
+ vcom "$IP_DIR/ip_arria10_e2sg_pll_clk200.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/pll_clk200/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..a6e13a55caf25212a950ddf1ed73cabaa79e8064
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk200/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_pll_clk200
+hdl_library_clause_name = ip_arria10_e2sg_pll_clk200_altera_iopll_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_iopll_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/pll_clk200/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_pll_clk200/ip_arria10_e2sg_pll_clk200.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_pll_clk200.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk200/ip_arria10_e2sg_pll_clk200.qsys b/libraries/technology/ip_arria10_e2sg/pll_clk200/ip_arria10_e2sg_pll_clk200.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..02b2df87bcaa5104645bd6eacc052e0af5546e49
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk200/ip_arria10_e2sg_pll_clk200.qsys
@@ -0,0 +1,360 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_pll_clk200">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element iopll_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>outclk0</key>
+ <value>
+ <connectionPointName>outclk0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>200000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk1</key>
+ <value>
+ <connectionPointName>outclk1</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>200000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk2</key>
+ <value>
+ <connectionPointName>outclk2</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>400000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="locked" internal="iopll_0.locked" type="conduit" dir="end">
+ <port name="locked" internal="locked" />
+ </interface>
+ <interface name="outclk0" internal="iopll_0.outclk0" type="clock" dir="start">
+ <port name="outclk_0" internal="outclk_0" />
+ </interface>
+ <interface name="outclk1" internal="iopll_0.outclk1" type="clock" dir="start">
+ <port name="outclk_1" internal="outclk_1" />
+ </interface>
+ <interface name="outclk2" internal="iopll_0.outclk2" type="clock" dir="start">
+ <port name="outclk_2" internal="outclk_2" />
+ </interface>
+ <interface name="refclk" internal="iopll_0.refclk" type="clock" dir="end">
+ <port name="refclk" internal="refclk" />
+ </interface>
+ <interface name="reset" internal="iopll_0.reset" type="reset" dir="end">
+ <port name="rst" internal="rst" />
+ </interface>
+ <module
+ name="iopll_0"
+ kind="altera_iopll"
+ version="19.3.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="gui_active_clk" value="false" />
+ <parameter name="gui_c_cnt_in_src0">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src1">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src2">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src3">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src4">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src5">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src6">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src7">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src8">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_cal_code_hex_file" value="iossm.hex" />
+ <parameter name="gui_cal_converge" value="false" />
+ <parameter name="gui_cal_error" value="cal_clean" />
+ <parameter name="gui_cascade_counter0" value="false" />
+ <parameter name="gui_cascade_counter1" value="false" />
+ <parameter name="gui_cascade_counter10" value="false" />
+ <parameter name="gui_cascade_counter11" value="false" />
+ <parameter name="gui_cascade_counter12" value="false" />
+ <parameter name="gui_cascade_counter13" value="false" />
+ <parameter name="gui_cascade_counter14" value="false" />
+ <parameter name="gui_cascade_counter15" value="false" />
+ <parameter name="gui_cascade_counter16" value="false" />
+ <parameter name="gui_cascade_counter17" value="false" />
+ <parameter name="gui_cascade_counter2" value="false" />
+ <parameter name="gui_cascade_counter3" value="false" />
+ <parameter name="gui_cascade_counter4" value="false" />
+ <parameter name="gui_cascade_counter5" value="false" />
+ <parameter name="gui_cascade_counter6" value="false" />
+ <parameter name="gui_cascade_counter7" value="false" />
+ <parameter name="gui_cascade_counter8" value="false" />
+ <parameter name="gui_cascade_counter9" value="false" />
+ <parameter name="gui_cascade_outclk_index" value="0" />
+ <parameter name="gui_clk_bad" value="false" />
+ <parameter name="gui_clock_name_global" value="false" />
+ <parameter name="gui_clock_name_string0" value="pll_clk200" />
+ <parameter name="gui_clock_name_string1" value="pll_clk200p" />
+ <parameter name="gui_clock_name_string10" value="outclk10" />
+ <parameter name="gui_clock_name_string11" value="outclk11" />
+ <parameter name="gui_clock_name_string12" value="outclk12" />
+ <parameter name="gui_clock_name_string13" value="outclk13" />
+ <parameter name="gui_clock_name_string14" value="outclk14" />
+ <parameter name="gui_clock_name_string15" value="outclk15" />
+ <parameter name="gui_clock_name_string16" value="outclk16" />
+ <parameter name="gui_clock_name_string17" value="outclk17" />
+ <parameter name="gui_clock_name_string2" value="pll_clk400" />
+ <parameter name="gui_clock_name_string3" value="outclk3" />
+ <parameter name="gui_clock_name_string4" value="outclk4" />
+ <parameter name="gui_clock_name_string5" value="outclk5" />
+ <parameter name="gui_clock_name_string6" value="outclk6" />
+ <parameter name="gui_clock_name_string7" value="outclk7" />
+ <parameter name="gui_clock_name_string8" value="outclk8" />
+ <parameter name="gui_clock_name_string9" value="outclk9" />
+ <parameter name="gui_clock_to_compensate" value="0" />
+ <parameter name="gui_debug_mode" value="false" />
+ <parameter name="gui_divide_factor_c0" value="6" />
+ <parameter name="gui_divide_factor_c1" value="6" />
+ <parameter name="gui_divide_factor_c10" value="6" />
+ <parameter name="gui_divide_factor_c11" value="6" />
+ <parameter name="gui_divide_factor_c12" value="6" />
+ <parameter name="gui_divide_factor_c13" value="6" />
+ <parameter name="gui_divide_factor_c14" value="6" />
+ <parameter name="gui_divide_factor_c15" value="6" />
+ <parameter name="gui_divide_factor_c16" value="6" />
+ <parameter name="gui_divide_factor_c17" value="6" />
+ <parameter name="gui_divide_factor_c2" value="6" />
+ <parameter name="gui_divide_factor_c3" value="6" />
+ <parameter name="gui_divide_factor_c4" value="6" />
+ <parameter name="gui_divide_factor_c5" value="6" />
+ <parameter name="gui_divide_factor_c6" value="6" />
+ <parameter name="gui_divide_factor_c7" value="6" />
+ <parameter name="gui_divide_factor_c8" value="6" />
+ <parameter name="gui_divide_factor_c9" value="6" />
+ <parameter name="gui_divide_factor_n" value="1" />
+ <parameter name="gui_dps_cntr" value="C0" />
+ <parameter name="gui_dps_dir" value="Positive" />
+ <parameter name="gui_dps_num" value="1" />
+ <parameter name="gui_dsm_out_sel" value="1st_order" />
+ <parameter name="gui_duty_cycle0" value="50.0" />
+ <parameter name="gui_duty_cycle1" value="50.0" />
+ <parameter name="gui_duty_cycle10" value="50.0" />
+ <parameter name="gui_duty_cycle11" value="50.0" />
+ <parameter name="gui_duty_cycle12" value="50.0" />
+ <parameter name="gui_duty_cycle13" value="50.0" />
+ <parameter name="gui_duty_cycle14" value="50.0" />
+ <parameter name="gui_duty_cycle15" value="50.0" />
+ <parameter name="gui_duty_cycle16" value="50.0" />
+ <parameter name="gui_duty_cycle17" value="50.0" />
+ <parameter name="gui_duty_cycle2" value="50.0" />
+ <parameter name="gui_duty_cycle3" value="50.0" />
+ <parameter name="gui_duty_cycle4" value="50.0" />
+ <parameter name="gui_duty_cycle5" value="50.0" />
+ <parameter name="gui_duty_cycle6" value="50.0" />
+ <parameter name="gui_duty_cycle7" value="50.0" />
+ <parameter name="gui_duty_cycle8" value="50.0" />
+ <parameter name="gui_duty_cycle9" value="50.0" />
+ <parameter name="gui_en_adv_params" value="false" />
+ <parameter name="gui_en_dps_ports" value="false" />
+ <parameter name="gui_en_extclkout_ports" value="false" />
+ <parameter name="gui_en_lvds_ports" value="Disabled" />
+ <parameter name="gui_en_phout_ports" value="false" />
+ <parameter name="gui_en_reconf" value="false" />
+ <parameter name="gui_enable_cascade_in" value="false" />
+ <parameter name="gui_enable_cascade_out" value="false" />
+ <parameter name="gui_enable_mif_dps" value="false" />
+ <parameter name="gui_enable_output_counter_cascading" value="false" />
+ <parameter name="gui_enable_permit_cal" value="false" />
+ <parameter name="gui_existing_mif_file_path" value="~/pll.mif" />
+ <parameter name="gui_extclkout_0_source" value="C0" />
+ <parameter name="gui_extclkout_1_source" value="C0" />
+ <parameter name="gui_feedback_clock" value="Global Clock" />
+ <parameter name="gui_fix_vco_frequency" value="false" />
+ <parameter name="gui_fixed_vco_frequency" value="600.0" />
+ <parameter name="gui_fixed_vco_frequency_ps" value="1667.0" />
+ <parameter name="gui_frac_multiply_factor" value="1" />
+ <parameter name="gui_fractional_cout" value="32" />
+ <parameter name="gui_include_iossm" value="false" />
+ <parameter name="gui_location_type" value="I/O Bank" />
+ <parameter name="gui_lock_setting" value="Low Lock Time" />
+ <parameter name="gui_mif_config_name" value="unnamed" />
+ <parameter name="gui_mif_gen_options">Generate New MIF File</parameter>
+ <parameter name="gui_multiply_factor" value="6" />
+ <parameter name="gui_new_mif_file_path" value="~/pll.mif" />
+ <parameter name="gui_number_of_clocks" value="3" />
+ <parameter name="gui_operation_mode" value="direct" />
+ <parameter name="gui_output_clock_frequency0" value="200.0" />
+ <parameter name="gui_output_clock_frequency1" value="200.0" />
+ <parameter name="gui_output_clock_frequency10" value="100.0" />
+ <parameter name="gui_output_clock_frequency11" value="100.0" />
+ <parameter name="gui_output_clock_frequency12" value="100.0" />
+ <parameter name="gui_output_clock_frequency13" value="100.0" />
+ <parameter name="gui_output_clock_frequency14" value="100.0" />
+ <parameter name="gui_output_clock_frequency15" value="100.0" />
+ <parameter name="gui_output_clock_frequency16" value="100.0" />
+ <parameter name="gui_output_clock_frequency17" value="100.0" />
+ <parameter name="gui_output_clock_frequency2" value="400.0" />
+ <parameter name="gui_output_clock_frequency3" value="100.0" />
+ <parameter name="gui_output_clock_frequency4" value="100.0" />
+ <parameter name="gui_output_clock_frequency5" value="100.0" />
+ <parameter name="gui_output_clock_frequency6" value="100.0" />
+ <parameter name="gui_output_clock_frequency7" value="100.0" />
+ <parameter name="gui_output_clock_frequency8" value="100.0" />
+ <parameter name="gui_output_clock_frequency9" value="100.0" />
+ <parameter name="gui_output_clock_frequency_ps0" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps1" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps10" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps11" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps12" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps13" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps14" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps15" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps16" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps17" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps2" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps3" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps4" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps5" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps6" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps7" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps8" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps9" value="10000.0" />
+ <parameter name="gui_parameter_table_hex_file" value="seq_params_sim.hex" />
+ <parameter name="gui_phase_shift0" value="0.0" />
+ <parameter name="gui_phase_shift1" value="0.0" />
+ <parameter name="gui_phase_shift10" value="0.0" />
+ <parameter name="gui_phase_shift11" value="0.0" />
+ <parameter name="gui_phase_shift12" value="0.0" />
+ <parameter name="gui_phase_shift13" value="0.0" />
+ <parameter name="gui_phase_shift14" value="0.0" />
+ <parameter name="gui_phase_shift15" value="0.0" />
+ <parameter name="gui_phase_shift16" value="0.0" />
+ <parameter name="gui_phase_shift17" value="0.0" />
+ <parameter name="gui_phase_shift2" value="0.0" />
+ <parameter name="gui_phase_shift3" value="0.0" />
+ <parameter name="gui_phase_shift4" value="0.0" />
+ <parameter name="gui_phase_shift5" value="0.0" />
+ <parameter name="gui_phase_shift6" value="0.0" />
+ <parameter name="gui_phase_shift7" value="0.0" />
+ <parameter name="gui_phase_shift8" value="0.0" />
+ <parameter name="gui_phase_shift9" value="0.0" />
+ <parameter name="gui_phase_shift_deg0" value="0.0" />
+ <parameter name="gui_phase_shift_deg1" value="0.0" />
+ <parameter name="gui_phase_shift_deg10" value="0.0" />
+ <parameter name="gui_phase_shift_deg11" value="0.0" />
+ <parameter name="gui_phase_shift_deg12" value="0.0" />
+ <parameter name="gui_phase_shift_deg13" value="0.0" />
+ <parameter name="gui_phase_shift_deg14" value="0.0" />
+ <parameter name="gui_phase_shift_deg15" value="0.0" />
+ <parameter name="gui_phase_shift_deg16" value="0.0" />
+ <parameter name="gui_phase_shift_deg17" value="0.0" />
+ <parameter name="gui_phase_shift_deg2" value="0.0" />
+ <parameter name="gui_phase_shift_deg3" value="0.0" />
+ <parameter name="gui_phase_shift_deg4" value="0.0" />
+ <parameter name="gui_phase_shift_deg5" value="0.0" />
+ <parameter name="gui_phase_shift_deg6" value="0.0" />
+ <parameter name="gui_phase_shift_deg7" value="0.0" />
+ <parameter name="gui_phase_shift_deg8" value="0.0" />
+ <parameter name="gui_phase_shift_deg9" value="0.0" />
+ <parameter name="gui_phout_division" value="1" />
+ <parameter name="gui_pll_auto_reset" value="false" />
+ <parameter name="gui_pll_bandwidth_preset" value="Low" />
+ <parameter name="gui_pll_cal_done" value="false" />
+ <parameter name="gui_pll_cascading_mode" value="adjpllin" />
+ <parameter name="gui_pll_freqcal_en" value="true" />
+ <parameter name="gui_pll_freqcal_req_flag" value="true" />
+ <parameter name="gui_pll_m_cnt_in_src">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_pll_mode" value="Integer-N PLL" />
+ <parameter name="gui_pll_tclk_mux_en" value="false" />
+ <parameter name="gui_pll_tclk_sel" value="pll_tclk_m_src" />
+ <parameter name="gui_pll_type" value="S10_Simple" />
+ <parameter name="gui_pll_vco_freq_band_0">pll_freq_clk0_disabled</parameter>
+ <parameter name="gui_pll_vco_freq_band_1">pll_freq_clk1_disabled</parameter>
+ <parameter name="gui_prot_mode" value="UNUSED" />
+ <parameter name="gui_ps_units0" value="ps" />
+ <parameter name="gui_ps_units1" value="ps" />
+ <parameter name="gui_ps_units10" value="ps" />
+ <parameter name="gui_ps_units11" value="ps" />
+ <parameter name="gui_ps_units12" value="ps" />
+ <parameter name="gui_ps_units13" value="ps" />
+ <parameter name="gui_ps_units14" value="ps" />
+ <parameter name="gui_ps_units15" value="ps" />
+ <parameter name="gui_ps_units16" value="ps" />
+ <parameter name="gui_ps_units17" value="ps" />
+ <parameter name="gui_ps_units2" value="ps" />
+ <parameter name="gui_ps_units3" value="ps" />
+ <parameter name="gui_ps_units4" value="ps" />
+ <parameter name="gui_ps_units5" value="ps" />
+ <parameter name="gui_ps_units6" value="ps" />
+ <parameter name="gui_ps_units7" value="ps" />
+ <parameter name="gui_ps_units8" value="ps" />
+ <parameter name="gui_ps_units9" value="ps" />
+ <parameter name="gui_refclk1_frequency" value="100.0" />
+ <parameter name="gui_refclk_might_change" value="false" />
+ <parameter name="gui_refclk_switch" value="false" />
+ <parameter name="gui_reference_clock_frequency" value="200.0" />
+ <parameter name="gui_reference_clock_frequency_ps" value="10000.0" />
+ <parameter name="gui_skip_sdc_generation" value="false" />
+ <parameter name="gui_switchover_delay" value="0" />
+ <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+ <parameter name="gui_use_NDFB_modes" value="false" />
+ <parameter name="gui_use_coreclk" value="false" />
+ <parameter name="gui_use_locked" value="true" />
+ <parameter name="gui_use_logical" value="false" />
+ <parameter name="gui_usr_device_speed_grade" value="1" />
+ <parameter name="gui_vco_frequency" value="600.0" />
+ <parameter name="hp_qsys_scripting_mode" value="false" />
+ <parameter name="system_info_device_component" value="10AX115U3F45E2SG" />
+ <parameter name="system_info_device_family" value="Arria 10" />
+ <parameter name="system_info_device_speed_grade" value="2" />
+ <parameter name="system_part_trait_speed_grade" value="2" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/pll_clk25/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..284b7227b32d1e3a3ec10d0c42c9a45ee8d1d0e3
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk25/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk25/sim"
+
+
+ vcom "$IP_DIR/ip_arria10_e2sg_pll_clk25.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/pll_clk25/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..899408e3da13746db868e5d261879ab663a1a5cf
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk25/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_pll_clk25
+hdl_library_clause_name = ip_arria10_e2sg_pll_clk25_altera_iopll_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_iopll_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/pll_clk25/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_pll_clk25/ip_arria10_e2sg_pll_clk25.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_pll_clk25.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk25/ip_arria10_e2sg_pll_clk25.qsys b/libraries/technology/ip_arria10_e2sg/pll_clk25/ip_arria10_e2sg_pll_clk25.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..b9bf7c707c0522e8d160b0e728372499a1987e51
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk25/ip_arria10_e2sg_pll_clk25.qsys
@@ -0,0 +1,376 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_pll_clk25">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element iopll_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>outclk0</key>
+ <value>
+ <connectionPointName>outclk0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>20000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk1</key>
+ <value>
+ <connectionPointName>outclk1</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>50000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk2</key>
+ <value>
+ <connectionPointName>outclk2</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk3</key>
+ <value>
+ <connectionPointName>outclk3</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="locked" internal="iopll_0.locked" type="conduit" dir="end">
+ <port name="locked" internal="locked" />
+ </interface>
+ <interface name="outclk0" internal="iopll_0.outclk0" type="clock" dir="start">
+ <port name="outclk_0" internal="outclk_0" />
+ </interface>
+ <interface name="outclk1" internal="iopll_0.outclk1" type="clock" dir="start">
+ <port name="outclk_1" internal="outclk_1" />
+ </interface>
+ <interface name="outclk2" internal="iopll_0.outclk2" type="clock" dir="start">
+ <port name="outclk_2" internal="outclk_2" />
+ </interface>
+ <interface name="outclk3" internal="iopll_0.outclk3" type="clock" dir="start">
+ <port name="outclk_3" internal="outclk_3" />
+ </interface>
+ <interface name="refclk" internal="iopll_0.refclk" type="clock" dir="end">
+ <port name="refclk" internal="refclk" />
+ </interface>
+ <interface name="reset" internal="iopll_0.reset" type="reset" dir="end">
+ <port name="rst" internal="rst" />
+ </interface>
+ <module
+ name="iopll_0"
+ kind="altera_iopll"
+ version="19.3.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="gui_active_clk" value="false" />
+ <parameter name="gui_c_cnt_in_src0">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src1">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src2">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src3">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src4">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src5">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src6">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src7">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_c_cnt_in_src8">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_cal_code_hex_file" value="iossm.hex" />
+ <parameter name="gui_cal_converge" value="false" />
+ <parameter name="gui_cal_error" value="cal_clean" />
+ <parameter name="gui_cascade_counter0" value="false" />
+ <parameter name="gui_cascade_counter1" value="false" />
+ <parameter name="gui_cascade_counter10" value="false" />
+ <parameter name="gui_cascade_counter11" value="false" />
+ <parameter name="gui_cascade_counter12" value="false" />
+ <parameter name="gui_cascade_counter13" value="false" />
+ <parameter name="gui_cascade_counter14" value="false" />
+ <parameter name="gui_cascade_counter15" value="false" />
+ <parameter name="gui_cascade_counter16" value="false" />
+ <parameter name="gui_cascade_counter17" value="false" />
+ <parameter name="gui_cascade_counter2" value="false" />
+ <parameter name="gui_cascade_counter3" value="false" />
+ <parameter name="gui_cascade_counter4" value="false" />
+ <parameter name="gui_cascade_counter5" value="false" />
+ <parameter name="gui_cascade_counter6" value="false" />
+ <parameter name="gui_cascade_counter7" value="false" />
+ <parameter name="gui_cascade_counter8" value="false" />
+ <parameter name="gui_cascade_counter9" value="false" />
+ <parameter name="gui_cascade_outclk_index" value="0" />
+ <parameter name="gui_clk_bad" value="false" />
+ <parameter name="gui_clock_name_global" value="false" />
+ <parameter name="gui_clock_name_string0" value="pll_clk20" />
+ <parameter name="gui_clock_name_string1" value="pll_clk50" />
+ <parameter name="gui_clock_name_string10" value="outclk10" />
+ <parameter name="gui_clock_name_string11" value="outclk11" />
+ <parameter name="gui_clock_name_string12" value="outclk12" />
+ <parameter name="gui_clock_name_string13" value="outclk13" />
+ <parameter name="gui_clock_name_string14" value="outclk14" />
+ <parameter name="gui_clock_name_string15" value="outclk15" />
+ <parameter name="gui_clock_name_string16" value="outclk16" />
+ <parameter name="gui_clock_name_string17" value="outclk17" />
+ <parameter name="gui_clock_name_string2" value="pll_clk100" />
+ <parameter name="gui_clock_name_string3" value="pll_clk125" />
+ <parameter name="gui_clock_name_string4" value="outclk4" />
+ <parameter name="gui_clock_name_string5" value="outclk5" />
+ <parameter name="gui_clock_name_string6" value="outclk6" />
+ <parameter name="gui_clock_name_string7" value="outclk7" />
+ <parameter name="gui_clock_name_string8" value="outclk8" />
+ <parameter name="gui_clock_name_string9" value="outclk9" />
+ <parameter name="gui_clock_to_compensate" value="0" />
+ <parameter name="gui_debug_mode" value="false" />
+ <parameter name="gui_divide_factor_c0" value="6" />
+ <parameter name="gui_divide_factor_c1" value="6" />
+ <parameter name="gui_divide_factor_c10" value="6" />
+ <parameter name="gui_divide_factor_c11" value="6" />
+ <parameter name="gui_divide_factor_c12" value="6" />
+ <parameter name="gui_divide_factor_c13" value="6" />
+ <parameter name="gui_divide_factor_c14" value="6" />
+ <parameter name="gui_divide_factor_c15" value="6" />
+ <parameter name="gui_divide_factor_c16" value="6" />
+ <parameter name="gui_divide_factor_c17" value="6" />
+ <parameter name="gui_divide_factor_c2" value="6" />
+ <parameter name="gui_divide_factor_c3" value="6" />
+ <parameter name="gui_divide_factor_c4" value="6" />
+ <parameter name="gui_divide_factor_c5" value="6" />
+ <parameter name="gui_divide_factor_c6" value="6" />
+ <parameter name="gui_divide_factor_c7" value="6" />
+ <parameter name="gui_divide_factor_c8" value="6" />
+ <parameter name="gui_divide_factor_c9" value="6" />
+ <parameter name="gui_divide_factor_n" value="1" />
+ <parameter name="gui_dps_cntr" value="C0" />
+ <parameter name="gui_dps_dir" value="Positive" />
+ <parameter name="gui_dps_num" value="1" />
+ <parameter name="gui_dsm_out_sel" value="1st_order" />
+ <parameter name="gui_duty_cycle0" value="50.0" />
+ <parameter name="gui_duty_cycle1" value="50.0" />
+ <parameter name="gui_duty_cycle10" value="50.0" />
+ <parameter name="gui_duty_cycle11" value="50.0" />
+ <parameter name="gui_duty_cycle12" value="50.0" />
+ <parameter name="gui_duty_cycle13" value="50.0" />
+ <parameter name="gui_duty_cycle14" value="50.0" />
+ <parameter name="gui_duty_cycle15" value="50.0" />
+ <parameter name="gui_duty_cycle16" value="50.0" />
+ <parameter name="gui_duty_cycle17" value="50.0" />
+ <parameter name="gui_duty_cycle2" value="50.0" />
+ <parameter name="gui_duty_cycle3" value="50.0" />
+ <parameter name="gui_duty_cycle4" value="50.0" />
+ <parameter name="gui_duty_cycle5" value="50.0" />
+ <parameter name="gui_duty_cycle6" value="50.0" />
+ <parameter name="gui_duty_cycle7" value="50.0" />
+ <parameter name="gui_duty_cycle8" value="50.0" />
+ <parameter name="gui_duty_cycle9" value="50.0" />
+ <parameter name="gui_en_adv_params" value="false" />
+ <parameter name="gui_en_dps_ports" value="false" />
+ <parameter name="gui_en_extclkout_ports" value="false" />
+ <parameter name="gui_en_lvds_ports" value="Disabled" />
+ <parameter name="gui_en_phout_ports" value="false" />
+ <parameter name="gui_en_reconf" value="false" />
+ <parameter name="gui_enable_cascade_in" value="false" />
+ <parameter name="gui_enable_cascade_out" value="false" />
+ <parameter name="gui_enable_mif_dps" value="false" />
+ <parameter name="gui_enable_output_counter_cascading" value="false" />
+ <parameter name="gui_enable_permit_cal" value="false" />
+ <parameter name="gui_existing_mif_file_path" value="~/pll.mif" />
+ <parameter name="gui_extclkout_0_source" value="C0" />
+ <parameter name="gui_extclkout_1_source" value="C0" />
+ <parameter name="gui_feedback_clock" value="Global Clock" />
+ <parameter name="gui_fix_vco_frequency" value="false" />
+ <parameter name="gui_fixed_vco_frequency" value="600.0" />
+ <parameter name="gui_fixed_vco_frequency_ps" value="1667.0" />
+ <parameter name="gui_frac_multiply_factor" value="1" />
+ <parameter name="gui_fractional_cout" value="32" />
+ <parameter name="gui_include_iossm" value="false" />
+ <parameter name="gui_location_type" value="I/O Bank" />
+ <parameter name="gui_lock_setting" value="Low Lock Time" />
+ <parameter name="gui_mif_config_name" value="unnamed" />
+ <parameter name="gui_mif_gen_options">Generate New MIF File</parameter>
+ <parameter name="gui_multiply_factor" value="6" />
+ <parameter name="gui_new_mif_file_path" value="~/pll.mif" />
+ <parameter name="gui_number_of_clocks" value="4" />
+ <parameter name="gui_operation_mode" value="direct" />
+ <parameter name="gui_output_clock_frequency0" value="20.0" />
+ <parameter name="gui_output_clock_frequency1" value="50.0" />
+ <parameter name="gui_output_clock_frequency10" value="100.0" />
+ <parameter name="gui_output_clock_frequency11" value="100.0" />
+ <parameter name="gui_output_clock_frequency12" value="100.0" />
+ <parameter name="gui_output_clock_frequency13" value="100.0" />
+ <parameter name="gui_output_clock_frequency14" value="100.0" />
+ <parameter name="gui_output_clock_frequency15" value="100.0" />
+ <parameter name="gui_output_clock_frequency16" value="100.0" />
+ <parameter name="gui_output_clock_frequency17" value="100.0" />
+ <parameter name="gui_output_clock_frequency2" value="100.0" />
+ <parameter name="gui_output_clock_frequency3" value="125.0" />
+ <parameter name="gui_output_clock_frequency4" value="100.0" />
+ <parameter name="gui_output_clock_frequency5" value="100.0" />
+ <parameter name="gui_output_clock_frequency6" value="100.0" />
+ <parameter name="gui_output_clock_frequency7" value="100.0" />
+ <parameter name="gui_output_clock_frequency8" value="100.0" />
+ <parameter name="gui_output_clock_frequency9" value="100.0" />
+ <parameter name="gui_output_clock_frequency_ps0" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps1" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps10" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps11" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps12" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps13" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps14" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps15" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps16" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps17" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps2" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps3" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps4" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps5" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps6" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps7" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps8" value="10000.0" />
+ <parameter name="gui_output_clock_frequency_ps9" value="10000.0" />
+ <parameter name="gui_parameter_table_hex_file" value="seq_params_sim.hex" />
+ <parameter name="gui_phase_shift0" value="0.0" />
+ <parameter name="gui_phase_shift1" value="0.0" />
+ <parameter name="gui_phase_shift10" value="0.0" />
+ <parameter name="gui_phase_shift11" value="0.0" />
+ <parameter name="gui_phase_shift12" value="0.0" />
+ <parameter name="gui_phase_shift13" value="0.0" />
+ <parameter name="gui_phase_shift14" value="0.0" />
+ <parameter name="gui_phase_shift15" value="0.0" />
+ <parameter name="gui_phase_shift16" value="0.0" />
+ <parameter name="gui_phase_shift17" value="0.0" />
+ <parameter name="gui_phase_shift2" value="0.0" />
+ <parameter name="gui_phase_shift3" value="0.0" />
+ <parameter name="gui_phase_shift4" value="0.0" />
+ <parameter name="gui_phase_shift5" value="0.0" />
+ <parameter name="gui_phase_shift6" value="0.0" />
+ <parameter name="gui_phase_shift7" value="0.0" />
+ <parameter name="gui_phase_shift8" value="0.0" />
+ <parameter name="gui_phase_shift9" value="0.0" />
+ <parameter name="gui_phase_shift_deg0" value="0.0" />
+ <parameter name="gui_phase_shift_deg1" value="0.0" />
+ <parameter name="gui_phase_shift_deg10" value="0.0" />
+ <parameter name="gui_phase_shift_deg11" value="0.0" />
+ <parameter name="gui_phase_shift_deg12" value="0.0" />
+ <parameter name="gui_phase_shift_deg13" value="0.0" />
+ <parameter name="gui_phase_shift_deg14" value="0.0" />
+ <parameter name="gui_phase_shift_deg15" value="0.0" />
+ <parameter name="gui_phase_shift_deg16" value="0.0" />
+ <parameter name="gui_phase_shift_deg17" value="0.0" />
+ <parameter name="gui_phase_shift_deg2" value="0.0" />
+ <parameter name="gui_phase_shift_deg3" value="0.0" />
+ <parameter name="gui_phase_shift_deg4" value="0.0" />
+ <parameter name="gui_phase_shift_deg5" value="0.0" />
+ <parameter name="gui_phase_shift_deg6" value="0.0" />
+ <parameter name="gui_phase_shift_deg7" value="0.0" />
+ <parameter name="gui_phase_shift_deg8" value="0.0" />
+ <parameter name="gui_phase_shift_deg9" value="0.0" />
+ <parameter name="gui_phout_division" value="1" />
+ <parameter name="gui_pll_auto_reset" value="false" />
+ <parameter name="gui_pll_bandwidth_preset" value="Low" />
+ <parameter name="gui_pll_cal_done" value="false" />
+ <parameter name="gui_pll_cascading_mode" value="adjpllin" />
+ <parameter name="gui_pll_freqcal_en" value="true" />
+ <parameter name="gui_pll_freqcal_req_flag" value="true" />
+ <parameter name="gui_pll_m_cnt_in_src">c_m_cnt_in_src_ph_mux_clk</parameter>
+ <parameter name="gui_pll_mode" value="Integer-N PLL" />
+ <parameter name="gui_pll_tclk_mux_en" value="false" />
+ <parameter name="gui_pll_tclk_sel" value="pll_tclk_m_src" />
+ <parameter name="gui_pll_type" value="S10_Simple" />
+ <parameter name="gui_pll_vco_freq_band_0">pll_freq_clk0_disabled</parameter>
+ <parameter name="gui_pll_vco_freq_band_1">pll_freq_clk1_disabled</parameter>
+ <parameter name="gui_prot_mode" value="UNUSED" />
+ <parameter name="gui_ps_units0" value="ps" />
+ <parameter name="gui_ps_units1" value="ps" />
+ <parameter name="gui_ps_units10" value="ps" />
+ <parameter name="gui_ps_units11" value="ps" />
+ <parameter name="gui_ps_units12" value="ps" />
+ <parameter name="gui_ps_units13" value="ps" />
+ <parameter name="gui_ps_units14" value="ps" />
+ <parameter name="gui_ps_units15" value="ps" />
+ <parameter name="gui_ps_units16" value="ps" />
+ <parameter name="gui_ps_units17" value="ps" />
+ <parameter name="gui_ps_units2" value="ps" />
+ <parameter name="gui_ps_units3" value="ps" />
+ <parameter name="gui_ps_units4" value="ps" />
+ <parameter name="gui_ps_units5" value="ps" />
+ <parameter name="gui_ps_units6" value="ps" />
+ <parameter name="gui_ps_units7" value="ps" />
+ <parameter name="gui_ps_units8" value="ps" />
+ <parameter name="gui_ps_units9" value="ps" />
+ <parameter name="gui_refclk1_frequency" value="100.0" />
+ <parameter name="gui_refclk_might_change" value="false" />
+ <parameter name="gui_refclk_switch" value="false" />
+ <parameter name="gui_reference_clock_frequency" value="25.0" />
+ <parameter name="gui_reference_clock_frequency_ps" value="10000.0" />
+ <parameter name="gui_skip_sdc_generation" value="false" />
+ <parameter name="gui_switchover_delay" value="0" />
+ <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+ <parameter name="gui_use_NDFB_modes" value="false" />
+ <parameter name="gui_use_coreclk" value="false" />
+ <parameter name="gui_use_locked" value="true" />
+ <parameter name="gui_use_logical" value="false" />
+ <parameter name="gui_usr_device_speed_grade" value="1" />
+ <parameter name="gui_vco_frequency" value="600.0" />
+ <parameter name="hp_qsys_scripting_mode" value="false" />
+ <parameter name="system_info_device_component" value="10AX115U3F45E2SG" />
+ <parameter name="system_info_device_family" value="Arria 10" />
+ <parameter name="system_info_device_speed_grade" value="2" />
+ <parameter name="system_part_trait_speed_grade" value="2" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..2b7ee9fed6f9909fb0117460b1ad72520b7c0eae
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_xgmii_mac_clocks/sim"
+
+
+ vcom "$IP_DIR/ip_arria10_e2sg_pll_xgmii_mac_clocks.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..a92ff004f54896f99ecfc0cf7d72ee5aeb4c44a4
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_pll_xgmii_mac_clocks
+hdl_library_clause_name = ip_arria10_e2sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_fpll_a10_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_pll_xgmii_mac_clocks/ip_arria10_e2sg_pll_xgmii_mac_clocks.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_pll_xgmii_mac_clocks.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/ip_arria10_e2sg_pll_xgmii_mac_clocks.qsys b/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/ip_arria10_e2sg_pll_xgmii_mac_clocks.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..572839a271d7296292735dce0f2e58ac508cf155
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/ip_arria10_e2sg_pll_xgmii_mac_clocks.qsys
@@ -0,0 +1,222 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_pll_xgmii_mac_clocks">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element xcvr_fpll_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>outclk0</key>
+ <value>
+ <connectionPointName>outclk0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk1</key>
+ <value>
+ <connectionPointName>outclk1</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="outclk0"
+ internal="xcvr_fpll_a10_0.outclk0"
+ type="clock"
+ dir="start">
+ <port name="outclk0" internal="outclk0" />
+ </interface>
+ <interface
+ name="outclk1"
+ internal="xcvr_fpll_a10_0.outclk1"
+ type="clock"
+ dir="start">
+ <port name="outclk1" internal="outclk1" />
+ </interface>
+ <interface
+ name="pll_cal_busy"
+ internal="xcvr_fpll_a10_0.pll_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="pll_cal_busy" internal="pll_cal_busy" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="xcvr_fpll_a10_0.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="xcvr_fpll_a10_0.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_refclk0"
+ internal="xcvr_fpll_a10_0.pll_refclk0"
+ type="clock"
+ dir="end">
+ <port name="pll_refclk0" internal="pll_refclk0" />
+ </interface>
+ <module
+ name="xcvr_fpll_a10_0"
+ kind="altera_xcvr_fpll_a10"
+ version="19.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="enable_analog_resets" value="0" />
+ <parameter name="enable_bonding_clks" value="0" />
+ <parameter name="enable_ext_lockdetect_ports" value="0" />
+ <parameter name="enable_fb_comp_bonding" value="0" />
+ <parameter name="enable_hfreq_clk" value="0" />
+ <parameter name="enable_mcgb" value="0" />
+ <parameter name="enable_mcgb_pcie_clksw" value="0" />
+ <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
+ <parameter name="enable_pll_reconfig" value="0" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="gui_actual_outclk0_frequency" value="100.0" />
+ <parameter name="gui_actual_outclk1_frequency" value="100.0" />
+ <parameter name="gui_actual_outclk2_frequency" value="100.0" />
+ <parameter name="gui_actual_outclk3_frequency" value="100.0" />
+ <parameter name="gui_actual_refclk_frequency" value="100.0" />
+ <parameter name="gui_bw_sel" value="low" />
+ <parameter name="gui_cascade_outclk_index" value="0" />
+ <parameter name="gui_desired_hssi_cascade_frequency" value="100.0" />
+ <parameter name="gui_desired_outclk0_frequency" value="156.25" />
+ <parameter name="gui_desired_outclk1_frequency" value="312.5" />
+ <parameter name="gui_desired_outclk2_frequency" value="100.0" />
+ <parameter name="gui_desired_outclk3_frequency" value="100.0" />
+ <parameter name="gui_desired_refclk_frequency" value="100.0" />
+ <parameter name="gui_enable_50G_support" value="false" />
+ <parameter name="gui_enable_active_clk" value="false" />
+ <parameter name="gui_enable_cascade_out" value="false" />
+ <parameter name="gui_enable_clk_bad" value="false" />
+ <parameter name="gui_enable_dps" value="false" />
+ <parameter name="gui_enable_fractional" value="false" />
+ <parameter name="gui_enable_hip_cal_done_port" value="0" />
+ <parameter name="gui_enable_manual_config" value="false" />
+ <parameter name="gui_enable_manual_hssi_counters" value="false" />
+ <parameter name="gui_enable_phase_alignment" value="false" />
+ <parameter name="gui_enable_pld_cal_busy_port" value="1" />
+ <parameter name="gui_fpll_mode" value="0" />
+ <parameter name="gui_fractional_x" value="32" />
+ <parameter name="gui_hip_cal_en" value="0" />
+ <parameter name="gui_hssi_output_clock_frequency" value="1250.0" />
+ <parameter name="gui_hssi_prot_mode" value="0" />
+ <parameter name="gui_iqtxrxclk_outclk_index" value="0" />
+ <parameter name="gui_is_downstream_cascaded_pll" value="false" />
+ <parameter name="gui_number_of_output_clocks" value="2" />
+ <parameter name="gui_operation_mode" value="0" />
+ <parameter name="gui_outclk0_actual_phase_shift" value="0.0" />
+ <parameter name="gui_outclk0_actual_phase_shift_deg" value="0.0" />
+ <parameter name="gui_outclk0_desired_phase_shift" value="0.0" />
+ <parameter name="gui_outclk0_phase_shift_unit" value="0" />
+ <parameter name="gui_outclk1_actual_phase_shift" value="0.0" />
+ <parameter name="gui_outclk1_actual_phase_shift_deg" value="0.0" />
+ <parameter name="gui_outclk1_desired_phase_shift" value="0" />
+ <parameter name="gui_outclk1_phase_shift_unit" value="0" />
+ <parameter name="gui_outclk2_actual_phase_shift" value="0 ps" />
+ <parameter name="gui_outclk2_actual_phase_shift_deg" value="0 deg" />
+ <parameter name="gui_outclk2_desired_phase_shift" value="0" />
+ <parameter name="gui_outclk2_phase_shift_unit" value="0" />
+ <parameter name="gui_outclk3_actual_phase_shift" value="0.0" />
+ <parameter name="gui_outclk3_actual_phase_shift_deg" value="0.0" />
+ <parameter name="gui_outclk3_desired_phase_shift" value="0" />
+ <parameter name="gui_outclk3_phase_shift_unit" value="0" />
+ <parameter name="gui_pll_c_counter_0" value="1" />
+ <parameter name="gui_pll_c_counter_1" value="1" />
+ <parameter name="gui_pll_c_counter_2" value="1" />
+ <parameter name="gui_pll_c_counter_3" value="1" />
+ <parameter name="gui_pll_dsm_fractional_division" value="1" />
+ <parameter name="gui_pll_m_counter" value="1" />
+ <parameter name="gui_pll_n_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_k_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_l_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_m_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_n_counter" value="1" />
+ <parameter name="gui_refclk1_frequency" value="100.0" />
+ <parameter name="gui_refclk_cnt" value="1" />
+ <parameter name="gui_refclk_index" value="0" />
+ <parameter name="gui_refclk_switch" value="false" />
+ <parameter name="gui_reference_clock_frequency" value="644.53125" />
+ <parameter name="gui_self_reset_enabled" value="false" />
+ <parameter name="gui_switchover_delay" value="0" />
+ <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+ <parameter name="mcgb_aux_clkin_cnt" value="0" />
+ <parameter name="mcgb_div" value="1" />
+ <parameter name="phase_alignment_check_var" value="false" />
+ <parameter name="pma_width" value="64" />
+ <parameter name="rcfg_debug" value="0" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_fpll_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="0" />
+ <parameter name="rcfg_mif_file_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_sv_file_enable" value="0" />
+ <parameter name="rcfg_txt_file_enable" value="0" />
+ <parameter name="set_altera_xcvr_fpll_a10_calibration_en" value="1" />
+ <parameter name="set_capability_reg_enable" value="0" />
+ <parameter name="set_csr_soft_logic_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="silicon_rev" value="false" />
+ <parameter name="support_mode" value="user_mode" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/ram/README.txt b/libraries/technology/ip_arria10_e2sg/ram/README.txt
new file mode 100755
index 0000000000000000000000000000000000000000..24ad4ab94e542bd2d642eaa079f4e18624d8c163
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/README.txt
@@ -0,0 +1,97 @@
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ram
+
+Contents:
+
+1) RAM components
+2) ROM components
+3) Arria10 IP
+4) Inferred IP
+5) Memory initialisation file
+6) Implementation options (LUTs or block RAM)
+7) Synthesis trials
+
+
+1) RAM components:
+
+ ip_arria10_ram_crwk_crw = Two read/write ports each port with own port clock and with power of two ratio between port widths
+ ip_arria10_ram_crw_crw = Two read/write ports each port with own port clock and with same address and data width on both ports
+ ip_arria10_ram_cr_cw = One read port with clock and one write port with clock and with same address and data width on both ports
+ ip_arria10_ram_r_w = Single clock, one read port and one write port and with same address and data width on both ports
+
+
+2) ROM components:
+ ip_arria10_rom_r_w = Not available and not needed, because the ip_arria10_ram_r_w can be used for ROM IP by not connecting the
+ write port.
+
+
+3) Arria10 IP
+
+ The IP only needs to be generated with
+
+ ./generate_ip.sh
+
+ if it need to be modified, because the ip_arria10_ram_*.vhd directly instantiates the altera_syncram component.
+
+ The instantiation is copied manually from the ip_arria10_ram_*/ram_2port_140/sim/ip_arria10_ram_*.vhd.
+
+ It appears that the altera_syncram component can be synthesized even though it comes from the altera_lnsim package,
+ that is a simulation package. However it resembles how it worked for Straix IV with altera_mf.
+
+
+4) Inferred IP
+
+ The inferred Altera code was obtained using template insert with Quartus 14.0a10.
+ The ram_crwk_crw can not be inferred.
+ For the other RAM the g_inferred generic is set to FALSE because the inferred instances do not yet support g_init_file.
+ It is possible to init the RAM using a function e.g.:
+
+ function init_ram
+ return memory_t is
+ variable tmp : memory_t := (others => (others => '0'));
+ begin
+ for addr_pos in 0 to 2**ADDR_WIDTH - 1 loop
+ -- Initialize each address with the address itself
+ tmp(addr_pos) := std_logic_vector(to_unsigned(addr_pos, DATA_WIDTH));
+ end loop;
+ return tmp;
+ end init_ram;
+
+ -- Declare the RAM signal and specify a default value. Quartus II
+ -- will create a memory initialization file (.mif) based on the
+ -- default value.
+ signal ram : memory_t := init_ram;
+
+5) Memory initialisation file
+
+ To support the g_init_file requires first reading the file in a certain format. For us an integer format or SLV format
+ with one value per line (line number = address) would be fine. Using SLV format is necessary if the RAM data is wider
+ than 32 bit, because VHDL integer range is only 2**32. The tb_common_pkg has functiosn to read such a file. Quartus
+ creates a mif file from this when it infers the RAM. However our current UniBoard1 designs provide a mif file that fits
+ the RAM IP. Therefore it is easier initially to also use the RAM IP for Arria10. In future for RadioHDL a generic
+ RAM init file format is preferrable though.
+
+
+6) Implementation options (LUTs or block RAM)
+
+ The IP and inferred RAM can be set to use LUTs (MLAB) or block RAM (M20K), however this is not supported yet.
+
+ . For IP RAM this would imply adding a generic to set the appropriate parameter in the altera_syncram
+ . For inferred RAM is would imply adding a generic to be used for the syntype attribute.
+ From http://www.alterawiki.com/wiki/Mapping_SRLs_to_registers,_MLABs,_or_Block_RAMs:
+
+ entity
+ g_ramstyle : STRING := "MLAB,no_rw_check"
+ architecture
+ attribute ramstyle : string;
+
+ signal ram : memory_t := init_ram;
+ attribute ramstyle of ram : signal is g_ramstyle;
+
+
+7) Synthesis trials
+
+ The quartus/ram.qpf Quartus project was used to verify that the inferred RAM and the block RAM IP actually synthesise
+ to the appropriate FPGA resources.
+ Use the Quartus GUI to manually select a top level component for synthesis e.g. by right clicking the entity vhd file
+ in the file tab of the Quartus project navigator window.
+ Then check the resource usage in the synthesis and fitter reports.
diff --git a/libraries/technology/ip_arria10_e2sg/ram/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/ram/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..14fff7a66160db3dce13ac379c7db2811d2f972e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_ram
+hdl_library_clause_name = ip_arria10_e2sg_ram_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+ ip_arria10_e2sg_true_dual_port_ram_dual_clock.vhd
+ ip_arria10_e2sg_simple_dual_port_ram_dual_clock.vhd
+ ip_arria10_e2sg_simple_dual_port_ram_single_clock.vhd
+
+ ip_arria10_e2sg_ram_crwk_crw.vhd
+ ip_arria10_e2sg_ram_crw_crw.vhd
+ ip_arria10_e2sg_ram_cr_cw.vhd
+ ip_arria10_e2sg_ram_r_w.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.qsys b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..b5f64e7f840dcf16f9fd7099cfc5080da291b775
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.qsys
@@ -0,0 +1,145 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_ram_cr_cw">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element ram_2port_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="data" internal="ram_2port_0.data" type="conduit" dir="end">
+ <port name="data" internal="data" />
+ </interface>
+ <interface name="q" internal="ram_2port_0.q" type="conduit" dir="end">
+ <port name="q" internal="q" />
+ </interface>
+ <interface name="ram_input" internal="ram_2port_0.ram_input" />
+ <interface name="ram_output" internal="ram_2port_0.ram_output" />
+ <interface
+ name="rdaddress"
+ internal="ram_2port_0.rdaddress"
+ type="conduit"
+ dir="end">
+ <port name="rdaddress" internal="rdaddress" />
+ </interface>
+ <interface name="rdclock" internal="ram_2port_0.rdclock" type="clock" dir="end">
+ <port name="rdclock" internal="rdclock" />
+ </interface>
+ <interface
+ name="wraddress"
+ internal="ram_2port_0.wraddress"
+ type="conduit"
+ dir="end">
+ <port name="wraddress" internal="wraddress" />
+ </interface>
+ <interface name="wrclock" internal="ram_2port_0.wrclock" type="clock" dir="end">
+ <port name="wrclock" internal="wrclock" />
+ </interface>
+ <interface name="wren" internal="ram_2port_0.wren" type="conduit" dir="end">
+ <port name="wren" internal="wren" />
+ </interface>
+ <module
+ name="ram_2port_0"
+ kind="ram_2port"
+ version="20.0.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_ACLR_READ_INPUT_RDADDRESS" value="false" />
+ <parameter name="GUI_ACLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_ACLR_READ_OUTPUT_QB" value="false" />
+ <parameter name="GUI_BLANK_MEMORY" value="1" />
+ <parameter name="GUI_BYTE_ENABLE_A" value="false" />
+ <parameter name="GUI_BYTE_ENABLE_B" value="false" />
+ <parameter name="GUI_BYTE_ENABLE_WIDTH" value="8" />
+ <parameter name="GUI_CLKEN_ADDRESS_STALL_A" value="false" />
+ <parameter name="GUI_CLKEN_ADDRESS_STALL_B" value="false" />
+ <parameter name="GUI_CLKEN_INPUT_REG_A" value="false" />
+ <parameter name="GUI_CLKEN_INPUT_REG_B" value="false" />
+ <parameter name="GUI_CLKEN_OUTPUT_REG_A" value="false" />
+ <parameter name="GUI_CLKEN_OUTPUT_REG_B" value="false" />
+ <parameter name="GUI_CLKEN_RDADDRESSSTALL" value="false" />
+ <parameter name="GUI_CLKEN_READ_INPUT_REG" value="false" />
+ <parameter name="GUI_CLKEN_READ_OUTPUT_REG" value="false" />
+ <parameter name="GUI_CLKEN_WRADDRESSSTALL" value="false" />
+ <parameter name="GUI_CLKEN_WRITE_INPUT_REG" value="false" />
+ <parameter name="GUI_CLOCK_TYPE" value="1" />
+ <parameter name="GUI_COHERENT_READ" value="false" />
+ <parameter name="GUI_CONSTRAINED_DONT_CARE" value="true" />
+ <parameter name="GUI_DATAA_WIDTH" value="8" />
+ <parameter name="GUI_DIFFERENT_CLKENS" value="false" />
+ <parameter name="GUI_ECCENCBYPASS" value="false" />
+ <parameter name="GUI_ECC_DOUBLE" value="false" />
+ <parameter name="GUI_ECC_PIPELINE" value="false" />
+ <parameter name="GUI_ECC_TRIPLE" value="false" />
+ <parameter name="GUI_FILE_REFERENCE" value="0" />
+ <parameter name="GUI_FORCE_TO_ZERO" value="false" />
+ <parameter name="GUI_INIT_FILE_LAYOUT" value="PORT_B" />
+ <parameter name="GUI_INIT_SIM_TO_X" value="false" />
+ <parameter name="GUI_LC_IMPLEMENTION_OPTIONS" value="0" />
+ <parameter name="GUI_MAX_DEPTH" value="Auto" />
+ <parameter name="GUI_MEMSIZE_BITS" value="256" />
+ <parameter name="GUI_MEMSIZE_WORDS" value="32" />
+ <parameter name="GUI_MEM_IN_BITS" value="0" />
+ <parameter name="GUI_MIF_FILENAME" value="./ram_1024.hex" />
+ <parameter name="GUI_MODE" value="0" />
+ <parameter name="GUI_NBE_A" value="false" />
+ <parameter name="GUI_NBE_B" value="false" />
+ <parameter name="GUI_OPTIMIZATION_OPTION" value="0" />
+ <parameter name="GUI_PR" value="false" />
+ <parameter name="GUI_QA_WIDTH" value="8" />
+ <parameter name="GUI_QB_WIDTH" value="8" />
+ <parameter name="GUI_Q_PORT_MODE" value="2" />
+ <parameter name="GUI_RAM_BLOCK_TYPE" value="Auto" />
+ <parameter name="GUI_RDEN_DOUBLE" value="false" />
+ <parameter name="GUI_RDEN_SINGLE" value="false" />
+ <parameter name="GUI_RDW_A_MODE" value="New Data" />
+ <parameter name="GUI_RDW_B_MODE" value="New Data" />
+ <parameter name="GUI_READ_INPUT_RDADDRESS" value="true" />
+ <parameter name="GUI_READ_OUTPUT_QA" value="true" />
+ <parameter name="GUI_READ_OUTPUT_QB" value="true" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QB" value="false" />
+ <parameter name="GUI_TBENCH" value="false" />
+ <parameter name="GUI_TDP_EMULATE" value="false" />
+ <parameter name="GUI_VAR_WIDTH" value="false" />
+ <parameter name="GUI_WIDTH_ECCENCPARITY" value="8" />
+ <parameter name="GUI_WRITE_INPUT_PORTS" value="true" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7e4d82cefceacecd4814eb924098c5d4a2eea6a6
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd
@@ -0,0 +1,160 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- RadioHDL wrapper
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE technology_lib.technology_pkg.all;
+
+LIBRARY altera_lnsim;
+USE altera_lnsim.altera_lnsim_components.all;
+
+ENTITY ip_arria10_e2sg_ram_cr_cw IS
+ GENERIC (
+ g_inferred : BOOLEAN := FALSE;
+ g_adr_w : NATURAL := 5;
+ g_dat_w : NATURAL := 8;
+ g_nof_words : NATURAL := 2**5;
+ g_rd_latency : NATURAL := 1; -- choose 1 or 2
+ g_init_file : STRING := "UNUSED"
+ );
+ PORT
+ (
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdaddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ wraddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+ wrclk : IN STD_LOGIC := '1';
+ wren : IN STD_LOGIC := '0';
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+ );
+END ip_arria10_e2sg_ram_cr_cw;
+
+
+ARCHITECTURE SYN OF ip_arria10_e2sg_ram_cr_cw IS
+
+ CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
+
+ COMPONENT altera_syncram
+ GENERIC (
+ address_aclr_b : string;
+ address_reg_b : string;
+ clock_enable_input_a : string;
+ clock_enable_input_b : string;
+ clock_enable_output_b : string;
+ init_file : string;
+ intended_device_family : string;
+ lpm_type : string;
+ numwords_a : integer;
+ numwords_b : integer;
+ operation_mode : string;
+ outdata_aclr_b : string;
+ outdata_reg_b : string;
+ power_up_uninitialized : string;
+ widthad_a : integer;
+ widthad_b : integer;
+ width_a : integer;
+ width_b : integer;
+ width_byteena_a : integer
+ );
+ PORT (
+ address_a : in std_logic_vector(g_adr_w-1 downto 0);
+ address_b : in std_logic_vector(g_adr_w-1 downto 0);
+ clock0 : in std_logic;
+ clock1 : in std_logic;
+ data_a : in std_logic_vector(g_dat_w-1 downto 0);
+ wren_a : in std_logic;
+ q_b : out std_logic_vector(g_dat_w-1 downto 0)
+ );
+ END COMPONENT;
+
+ SIGNAL rdaddr : natural range 0 to g_nof_words - 1;
+ SIGNAL wraddr : natural range 0 to g_nof_words - 1;
+
+ SIGNAL out_q : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ SIGNAL reg_q : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+
+BEGIN
+
+ ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e2sg_ram_cr_cw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
+
+ gen_ip : IF g_inferred=FALSE GENERATE
+ -- Copied from ip_arria10_e2sg_ram_cr_cw/ram_2port_140/sim/ip_arria10_e2sg_ram_cr_cw_ram_2port_140_72tpmcy.vhd
+ u_altera_syncram : altera_syncram
+ GENERIC MAP (
+ address_aclr_b => "NONE",
+ address_reg_b => "CLOCK1",
+ clock_enable_input_a => "BYPASS",
+ clock_enable_input_b => "BYPASS",
+ clock_enable_output_b => "BYPASS",
+ init_file => g_init_file,
+ intended_device_family => "Arria 10",
+ lpm_type => "altera_syncram",
+ numwords_a => g_nof_words,
+ numwords_b => g_nof_words,
+ operation_mode => "DUAL_PORT",
+ outdata_aclr_b => "NONE",
+ outdata_reg_b => c_outdata_reg_b,
+ power_up_uninitialized => "FALSE",
+ widthad_a => g_adr_w,
+ widthad_b => g_adr_w,
+ width_a => g_dat_w,
+ width_b => g_dat_w,
+ width_byteena_a => 1
+ )
+ PORT MAP (
+ address_a => wraddress,
+ address_b => rdaddress,
+ clock0 => wrclk,
+ clock1 => rdclk,
+ data_a => data,
+ wren_a => wren,
+ q_b => q
+ );
+ END GENERATE;
+
+ gen_inferred : IF g_inferred=TRUE GENERATE
+ rdaddr <= TO_INTEGER(UNSIGNED(rdaddress));
+ wraddr <= TO_INTEGER(UNSIGNED(wraddress));
+
+ u_mem : entity work.ip_arria10_e2sg_simple_dual_port_ram_dual_clock
+ generic map (
+ DATA_WIDTH => g_dat_w,
+ ADDR_WIDTH => g_adr_w
+ )
+ port map (
+ rclk => rdclk,
+ wclk => wrclk,
+ raddr => rdaddr,
+ waddr => wraddr,
+ data => data,
+ we => wren,
+ q => out_q
+ );
+
+ reg_q <= out_q WHEN rising_edge(rdclk);
+
+ q <= out_q WHEN g_rd_latency=1 ELSE reg_q;
+ END GENERATE;
+
+END SYN;
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.qsys b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..caf4c8882658e34e990fa5e925ba783368569781
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.qsys
@@ -0,0 +1,154 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_ram_crw_crw">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element ram_2port_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="address_a"
+ internal="ram_2port_0.address_a"
+ type="conduit"
+ dir="end">
+ <port name="address_a" internal="address_a" />
+ </interface>
+ <interface
+ name="address_b"
+ internal="ram_2port_0.address_b"
+ type="conduit"
+ dir="end">
+ <port name="address_b" internal="address_b" />
+ </interface>
+ <interface name="clock_a" internal="ram_2port_0.clock_a" type="clock" dir="end">
+ <port name="clock_a" internal="clock_a" />
+ </interface>
+ <interface name="clock_b" internal="ram_2port_0.clock_b" type="clock" dir="end">
+ <port name="clock_b" internal="clock_b" />
+ </interface>
+ <interface name="data_a" internal="ram_2port_0.data_a" type="conduit" dir="end">
+ <port name="data_a" internal="data_a" />
+ </interface>
+ <interface name="data_b" internal="ram_2port_0.data_b" type="conduit" dir="end">
+ <port name="data_b" internal="data_b" />
+ </interface>
+ <interface name="q_a" internal="ram_2port_0.q_a" type="conduit" dir="end">
+ <port name="q_a" internal="q_a" />
+ </interface>
+ <interface name="q_b" internal="ram_2port_0.q_b" type="conduit" dir="end">
+ <port name="q_b" internal="q_b" />
+ </interface>
+ <interface name="ram_input" internal="ram_2port_0.ram_input" />
+ <interface name="ram_output" internal="ram_2port_0.ram_output" />
+ <interface name="wren_a" internal="ram_2port_0.wren_a" type="conduit" dir="end">
+ <port name="wren_a" internal="wren_a" />
+ </interface>
+ <interface name="wren_b" internal="ram_2port_0.wren_b" type="conduit" dir="end">
+ <port name="wren_b" internal="wren_b" />
+ </interface>
+ <module
+ name="ram_2port_0"
+ kind="ram_2port"
+ version="20.0.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_ACLR_READ_INPUT_RDADDRESS" value="false" />
+ <parameter name="GUI_ACLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_ACLR_READ_OUTPUT_QB" value="false" />
+ <parameter name="GUI_BLANK_MEMORY" value="1" />
+ <parameter name="GUI_BYTE_ENABLE_A" value="false" />
+ <parameter name="GUI_BYTE_ENABLE_B" value="false" />
+ <parameter name="GUI_BYTE_ENABLE_WIDTH" value="8" />
+ <parameter name="GUI_CLKEN_ADDRESS_STALL_A" value="false" />
+ <parameter name="GUI_CLKEN_ADDRESS_STALL_B" value="false" />
+ <parameter name="GUI_CLKEN_INPUT_REG_A" value="false" />
+ <parameter name="GUI_CLKEN_INPUT_REG_B" value="false" />
+ <parameter name="GUI_CLKEN_OUTPUT_REG_A" value="false" />
+ <parameter name="GUI_CLKEN_OUTPUT_REG_B" value="false" />
+ <parameter name="GUI_CLKEN_RDADDRESSSTALL" value="false" />
+ <parameter name="GUI_CLKEN_READ_INPUT_REG" value="false" />
+ <parameter name="GUI_CLKEN_READ_OUTPUT_REG" value="false" />
+ <parameter name="GUI_CLKEN_WRADDRESSSTALL" value="false" />
+ <parameter name="GUI_CLKEN_WRITE_INPUT_REG" value="false" />
+ <parameter name="GUI_CLOCK_TYPE" value="4" />
+ <parameter name="GUI_COHERENT_READ" value="false" />
+ <parameter name="GUI_CONSTRAINED_DONT_CARE" value="true" />
+ <parameter name="GUI_DATAA_WIDTH" value="8" />
+ <parameter name="GUI_DIFFERENT_CLKENS" value="false" />
+ <parameter name="GUI_ECCENCBYPASS" value="false" />
+ <parameter name="GUI_ECC_DOUBLE" value="false" />
+ <parameter name="GUI_ECC_PIPELINE" value="false" />
+ <parameter name="GUI_ECC_TRIPLE" value="false" />
+ <parameter name="GUI_FILE_REFERENCE" value="0" />
+ <parameter name="GUI_FORCE_TO_ZERO" value="false" />
+ <parameter name="GUI_INIT_FILE_LAYOUT" value="PORT_B" />
+ <parameter name="GUI_INIT_SIM_TO_X" value="false" />
+ <parameter name="GUI_LC_IMPLEMENTION_OPTIONS" value="0" />
+ <parameter name="GUI_MAX_DEPTH" value="Auto" />
+ <parameter name="GUI_MEMSIZE_BITS" value="256" />
+ <parameter name="GUI_MEMSIZE_WORDS" value="32" />
+ <parameter name="GUI_MEM_IN_BITS" value="0" />
+ <parameter name="GUI_MIF_FILENAME" value="./ram_1024.hex" />
+ <parameter name="GUI_MODE" value="1" />
+ <parameter name="GUI_NBE_A" value="true" />
+ <parameter name="GUI_NBE_B" value="true" />
+ <parameter name="GUI_OPTIMIZATION_OPTION" value="0" />
+ <parameter name="GUI_PR" value="false" />
+ <parameter name="GUI_QA_WIDTH" value="8" />
+ <parameter name="GUI_QB_WIDTH" value="8" />
+ <parameter name="GUI_Q_PORT_MODE" value="2" />
+ <parameter name="GUI_RAM_BLOCK_TYPE" value="Auto" />
+ <parameter name="GUI_RDEN_DOUBLE" value="false" />
+ <parameter name="GUI_RDEN_SINGLE" value="false" />
+ <parameter name="GUI_RDW_A_MODE" value="New Data" />
+ <parameter name="GUI_RDW_B_MODE" value="New Data" />
+ <parameter name="GUI_READ_INPUT_RDADDRESS" value="true" />
+ <parameter name="GUI_READ_OUTPUT_QA" value="true" />
+ <parameter name="GUI_READ_OUTPUT_QB" value="true" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QB" value="false" />
+ <parameter name="GUI_TBENCH" value="false" />
+ <parameter name="GUI_TDP_EMULATE" value="false" />
+ <parameter name="GUI_VAR_WIDTH" value="false" />
+ <parameter name="GUI_WIDTH_ECCENCPARITY" value="8" />
+ <parameter name="GUI_WRITE_INPUT_PORTS" value="true" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..033a87880432c7f50eb7484d458df12e51518838
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd
@@ -0,0 +1,190 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- RadioHDL wrapper
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE technology_lib.technology_pkg.all;
+
+LIBRARY altera_lnsim;
+USE altera_lnsim.altera_lnsim_components.all;
+
+ENTITY ip_arria10_e2sg_ram_crw_crw IS
+ GENERIC (
+ g_inferred : BOOLEAN := FALSE;
+ g_adr_w : NATURAL := 5;
+ g_dat_w : NATURAL := 8;
+ g_nof_words : NATURAL := 2**5;
+ g_rd_latency : NATURAL := 1; -- choose 1 or 2
+ g_init_file : STRING := "UNUSED"
+ );
+ PORT
+ (
+ address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+ address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+ clk_a : IN STD_LOGIC := '1';
+ clk_b : IN STD_LOGIC ;
+ data_a : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ data_b : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ wren_a : IN STD_LOGIC := '0';
+ wren_b : IN STD_LOGIC := '0';
+ q_a : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ q_b : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+ );
+END ip_arria10_e2sg_ram_crw_crw;
+
+
+ARCHITECTURE SYN OF ip_arria10_e2sg_ram_crw_crw IS
+
+ CONSTANT c_outdata_reg_a : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK0");
+ CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
+
+ COMPONENT altera_syncram
+ GENERIC (
+ address_reg_b : string;
+ clock_enable_input_a : string;
+ clock_enable_input_b : string;
+ clock_enable_output_a : string;
+ clock_enable_output_b : string;
+ indata_reg_b : string;
+ init_file : string;
+ intended_device_family : string;
+ lpm_type : string;
+ numwords_a : integer;
+ numwords_b : integer;
+ operation_mode : string;
+ outdata_aclr_a : string;
+ outdata_aclr_b : string;
+ outdata_reg_a : string;
+ outdata_reg_b : string;
+ power_up_uninitialized : string;
+ read_during_write_mode_port_a : string;
+ read_during_write_mode_port_b : string;
+ widthad_a : integer;
+ widthad_b : integer;
+ width_a : integer;
+ width_b : integer;
+ width_byteena_a : integer;
+ width_byteena_b : integer
+ );
+ PORT (
+ address_a : in std_logic_vector(g_adr_w-1 downto 0);
+ address_b : in std_logic_vector(g_adr_w-1 downto 0);
+ clock0 : in std_logic;
+ clock1 : in std_logic;
+ data_a : in std_logic_vector(g_dat_w-1 downto 0);
+ data_b : in std_logic_vector(g_dat_w-1 downto 0);
+ wren_a : in std_logic;
+ wren_b : in std_logic;
+ q_a : out std_logic_vector(g_dat_w - 1 downto 0);
+ q_b : out std_logic_vector(g_dat_w - 1 downto 0)
+ );
+ END COMPONENT;
+
+ SIGNAL addr_a : natural range 0 to g_nof_words - 1;
+ SIGNAL addr_b : natural range 0 to g_nof_words - 1;
+
+ SIGNAL out_a : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ SIGNAL out_b : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+
+ SIGNAL reg_a : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ SIGNAL reg_b : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+
+BEGIN
+
+ ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e2sg_ram_crw_crw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
+
+ gen_ip : IF g_inferred=FALSE GENERATE
+ -- Copied from ip_arria10_e2sg_ram_crw_crw/ram_2port_140/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_140_ehaf5aa.vhd
+ u_altera_syncram : altera_syncram
+ GENERIC MAP (
+ address_reg_b => "CLOCK1",
+ clock_enable_input_a => "BYPASS",
+ clock_enable_input_b => "BYPASS",
+ clock_enable_output_a => "BYPASS",
+ clock_enable_output_b => "BYPASS",
+ indata_reg_b => "CLOCK1",
+ init_file => g_init_file,
+ intended_device_family => "Arria 10",
+ lpm_type => "altera_syncram",
+ numwords_a => g_nof_words,
+ numwords_b => g_nof_words,
+ operation_mode => "BIDIR_DUAL_PORT",
+ outdata_aclr_a => "NONE",
+ outdata_aclr_b => "NONE",
+ outdata_reg_a => c_outdata_reg_a,
+ outdata_reg_b => c_outdata_reg_b,
+ power_up_uninitialized => "FALSE",
+ read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+ read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+ widthad_a => g_adr_w,
+ widthad_b => g_adr_w,
+ width_a => g_dat_w,
+ width_b => g_dat_w,
+ width_byteena_a => 1,
+ width_byteena_b => 1
+ )
+ PORT MAP (
+ address_a => address_a,
+ address_b => address_b,
+ clock0 => clk_a,
+ clock1 => clk_b,
+ data_a => data_a,
+ data_b => data_b,
+ wren_a => wren_a,
+ wren_b => wren_b,
+ q_a => q_a,
+ q_b => q_b
+ );
+ END GENERATE;
+
+ gen_inferred : IF g_inferred=TRUE GENERATE
+ addr_a <= TO_INTEGER(UNSIGNED(address_a));
+ addr_b <= TO_INTEGER(UNSIGNED(address_b));
+
+ u_mem : entity work.ip_arria10_e2sg_true_dual_port_ram_dual_clock
+ generic map (
+ DATA_WIDTH => g_dat_w,
+ ADDR_WIDTH => g_adr_w
+ )
+ port map (
+ clk_a => clk_a,
+ clk_b => clk_b,
+ addr_a => addr_a,
+ addr_b => addr_b,
+ data_a => data_a,
+ data_b => data_b,
+ we_a => wren_a,
+ we_b => wren_b,
+ q_a => out_a,
+ q_b => out_b
+ );
+
+ reg_a <= out_a WHEN rising_edge(clk_a);
+ reg_b <= out_b WHEN rising_edge(clk_b);
+
+ q_a <= out_a WHEN g_rd_latency=1 ELSE reg_a;
+ q_b <= out_b WHEN g_rd_latency=1 ELSE reg_b;
+ END GENERATE;
+
+END SYN;
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crwk_crw.qsys b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crwk_crw.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..96293db15f305b586537a930a11c5482496d2811
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crwk_crw.qsys
@@ -0,0 +1,200 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_ram_crwk_crw">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation"
+ categories="System"
+ tool="QsysPro" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element ip_arria10_ram_crwk_crw
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="address_a"
+ internal="ip_arria10_ram_crwk_crw.address_a"
+ type="conduit"
+ dir="end">
+ <port name="address_a" internal="address_a" />
+ </interface>
+ <interface
+ name="address_b"
+ internal="ip_arria10_ram_crwk_crw.address_b"
+ type="conduit"
+ dir="end">
+ <port name="address_b" internal="address_b" />
+ </interface>
+ <interface
+ name="clock_a"
+ internal="ip_arria10_ram_crwk_crw.clock_a"
+ type="clock"
+ dir="end">
+ <port name="clock_a" internal="clock_a" />
+ </interface>
+ <interface
+ name="clock_b"
+ internal="ip_arria10_ram_crwk_crw.clock_b"
+ type="clock"
+ dir="end">
+ <port name="clock_b" internal="clock_b" />
+ </interface>
+ <interface
+ name="data_a"
+ internal="ip_arria10_ram_crwk_crw.data_a"
+ type="conduit"
+ dir="end">
+ <port name="data_a" internal="data_a" />
+ </interface>
+ <interface
+ name="data_b"
+ internal="ip_arria10_ram_crwk_crw.data_b"
+ type="conduit"
+ dir="end">
+ <port name="data_b" internal="data_b" />
+ </interface>
+ <interface
+ name="q_a"
+ internal="ip_arria10_ram_crwk_crw.q_a"
+ type="conduit"
+ dir="end">
+ <port name="q_a" internal="q_a" />
+ </interface>
+ <interface
+ name="q_b"
+ internal="ip_arria10_ram_crwk_crw.q_b"
+ type="conduit"
+ dir="end">
+ <port name="q_b" internal="q_b" />
+ </interface>
+ <interface name="ram_input" internal="ip_arria10_ram_crwk_crw.ram_input" />
+ <interface name="ram_output" internal="ip_arria10_ram_crwk_crw.ram_output" />
+ <interface
+ name="rden_a"
+ internal="ip_arria10_ram_crwk_crw.rden_a"
+ type="conduit"
+ dir="end">
+ <port name="rden_a" internal="rden_a" />
+ </interface>
+ <interface
+ name="rden_b"
+ internal="ip_arria10_ram_crwk_crw.rden_b"
+ type="conduit"
+ dir="end">
+ <port name="rden_b" internal="rden_b" />
+ </interface>
+ <interface
+ name="wren_a"
+ internal="ip_arria10_ram_crwk_crw.wren_a"
+ type="conduit"
+ dir="end">
+ <port name="wren_a" internal="wren_a" />
+ </interface>
+ <interface
+ name="wren_b"
+ internal="ip_arria10_ram_crwk_crw.wren_b"
+ type="conduit"
+ dir="end">
+ <port name="wren_b" internal="wren_b" />
+ </interface>
+ <module
+ name="ip_arria10_ram_crwk_crw"
+ kind="ram_2port"
+ version="20.0.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_ACLR_READ_INPUT_RDADDRESS" value="false" />
+ <parameter name="GUI_ACLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_ACLR_READ_OUTPUT_QB" value="false" />
+ <parameter name="GUI_BLANK_MEMORY" value="1" />
+ <parameter name="GUI_BYTE_ENABLE_A" value="false" />
+ <parameter name="GUI_BYTE_ENABLE_B" value="false" />
+ <parameter name="GUI_BYTE_ENABLE_WIDTH" value="8" />
+ <parameter name="GUI_CLKEN_ADDRESS_STALL_A" value="false" />
+ <parameter name="GUI_CLKEN_ADDRESS_STALL_B" value="false" />
+ <parameter name="GUI_CLKEN_INPUT_REG_A" value="false" />
+ <parameter name="GUI_CLKEN_INPUT_REG_B" value="false" />
+ <parameter name="GUI_CLKEN_OUTPUT_REG_A" value="false" />
+ <parameter name="GUI_CLKEN_OUTPUT_REG_B" value="false" />
+ <parameter name="GUI_CLKEN_RDADDRESSSTALL" value="false" />
+ <parameter name="GUI_CLKEN_READ_INPUT_REG" value="true" />
+ <parameter name="GUI_CLKEN_READ_OUTPUT_REG" value="true" />
+ <parameter name="GUI_CLKEN_WRADDRESSSTALL" value="false" />
+ <parameter name="GUI_CLKEN_WRITE_INPUT_REG" value="true" />
+ <parameter name="GUI_CLOCK_TYPE" value="4" />
+ <parameter name="GUI_COHERENT_READ" value="false" />
+ <parameter name="GUI_CONSTRAINED_DONT_CARE" value="true" />
+ <parameter name="GUI_DATAA_WIDTH" value="32" />
+ <parameter name="GUI_DIFFERENT_CLKENS" value="false" />
+ <parameter name="GUI_ECCENCBYPASS" value="false" />
+ <parameter name="GUI_ECC_DOUBLE" value="false" />
+ <parameter name="GUI_ECC_PIPELINE" value="false" />
+ <parameter name="GUI_ECC_TRIPLE" value="false" />
+ <parameter name="GUI_FILE_REFERENCE" value="0" />
+ <parameter name="GUI_FORCE_TO_ZERO" value="false" />
+ <parameter name="GUI_INIT_FILE_LAYOUT" value="PORT_B" />
+ <parameter name="GUI_INIT_SIM_TO_X" value="false" />
+ <parameter name="GUI_LC_IMPLEMENTION_OPTIONS" value="0" />
+ <parameter name="GUI_MAX_DEPTH" value="Auto" />
+ <parameter name="GUI_MEMSIZE_BITS" value="256" />
+ <parameter name="GUI_MEMSIZE_WORDS" value="256" />
+ <parameter name="GUI_MEM_IN_BITS" value="0" />
+ <parameter name="GUI_MIF_FILENAME" value="./ram_1024.hex" />
+ <parameter name="GUI_MODE" value="1" />
+ <parameter name="GUI_NBE_A" value="true" />
+ <parameter name="GUI_NBE_B" value="true" />
+ <parameter name="GUI_OPTIMIZATION_OPTION" value="0" />
+ <parameter name="GUI_PR" value="false" />
+ <parameter name="GUI_QA_WIDTH" value="32" />
+ <parameter name="GUI_QB_WIDTH" value="8" />
+ <parameter name="GUI_Q_PORT_MODE" value="2" />
+ <parameter name="GUI_RAM_BLOCK_TYPE" value="Auto" />
+ <parameter name="GUI_RDEN_DOUBLE" value="true" />
+ <parameter name="GUI_RDEN_SINGLE" value="true" />
+ <parameter name="GUI_RDW_A_MODE" value="New Data" />
+ <parameter name="GUI_RDW_B_MODE" value="New Data" />
+ <parameter name="GUI_READ_INPUT_RDADDRESS" value="true" />
+ <parameter name="GUI_READ_OUTPUT_QA" value="true" />
+ <parameter name="GUI_READ_OUTPUT_QB" value="true" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QB" value="false" />
+ <parameter name="GUI_TBENCH" value="false" />
+ <parameter name="GUI_TDP_EMULATE" value="false" />
+ <parameter name="GUI_VAR_WIDTH" value="true" />
+ <parameter name="GUI_WIDTH_ECCENCPARITY" value="8" />
+ <parameter name="GUI_WRITE_INPUT_PORTS" value="true" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crwk_crw.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crwk_crw.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6d2cee79a7125b5435aaf8b1d09482ccb9de83f6
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crwk_crw.vhd
@@ -0,0 +1,142 @@
+-- (C) 2001-2014 Altera Corporation. All rights reserved.
+-- Your use of Altera Corporation's design tools, logic functions and other
+-- software and tools, and its AMPP partner logic functions, and any output
+-- files any of the foregoing (including device programming or simulation
+-- files), and any associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License Subscription
+-- Agreement, Altera MegaCore Function License Agreement, or other applicable
+-- license agreement, including, without limitation, that your use is for the
+-- sole purpose of programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the applicable
+-- agreement for further details.
+
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE technology_lib.technology_pkg.all;
+
+LIBRARY altera_lnsim;
+USE altera_lnsim.altera_lnsim_components.all;
+
+ENTITY ip_arria10_e2sg_ram_crwk_crw IS
+ GENERIC (
+ g_adr_a_w : NATURAL := 5;
+ g_dat_a_w : NATURAL := 32;
+ g_adr_b_w : NATURAL := 4;
+ g_dat_b_w : NATURAL := 64;
+ g_nof_words_a : NATURAL := 2**5;
+ g_nof_words_b : NATURAL := 2**4;
+ g_rd_latency : NATURAL := 1; -- choose 1 or 2
+ g_init_file : STRING := "UNUSED"
+ );
+ PORT
+ (
+ address_a : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
+ address_b : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
+ clk_a : IN STD_LOGIC := '1';
+ clk_b : IN STD_LOGIC ;
+ data_a : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+ data_b : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
+ wren_a : IN STD_LOGIC := '0';
+ wren_b : IN STD_LOGIC := '0';
+ q_a : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+ q_b : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
+ );
+END ip_arria10_e2sg_ram_crwk_crw;
+
+
+ARCHITECTURE SYN OF ip_arria10_e2sg_ram_crwk_crw IS
+
+ CONSTANT c_outdata_reg_a : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK0");
+ CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
+
+ COMPONENT altera_syncram
+ GENERIC (
+ address_reg_b : string;
+ clock_enable_input_a : string;
+ clock_enable_input_b : string;
+ clock_enable_output_a : string;
+ clock_enable_output_b : string;
+ indata_reg_b : string;
+ init_file : string;
+ init_file_layout : string;
+ intended_device_family : string;
+ lpm_type : string;
+ numwords_a : integer;
+ numwords_b : integer;
+ operation_mode : string;
+ outdata_aclr_a : string;
+ outdata_aclr_b : string;
+ outdata_reg_a : string;
+ outdata_reg_b : string;
+ power_up_uninitialized : string;
+ read_during_write_mode_port_a : string;
+ read_during_write_mode_port_b : string;
+ widthad_a : integer;
+ widthad_b : integer;
+ width_a : integer;
+ width_b : integer;
+ width_byteena_a : integer;
+ width_byteena_b : integer
+ );
+ PORT (
+ address_a : in std_logic_vector(g_adr_a_w-1 downto 0);
+ address_b : in std_logic_vector(g_adr_b_w-1 downto 0);
+ clock0 : in std_logic;
+ clock1 : in std_logic;
+ data_a : in std_logic_vector(g_dat_a_w-1 downto 0);
+ data_b : in std_logic_vector(g_dat_b_w-1 downto 0);
+ wren_a : in std_logic;
+ wren_b : in std_logic;
+ q_a : out std_logic_vector(g_dat_a_w - 1 downto 0);
+ q_b : out std_logic_vector(g_dat_b_w - 1 downto 0)
+ );
+ END COMPONENT;
+
+BEGIN
+
+ -- Copied from ip_arria10_e2sg_ram_crwk_crw/ram_2port_140/sim/ip_arria10_e2sg_ram_crwk_crw_ram_2port_140_iyfl3wi.vhd
+ u_altera_syncram : altera_syncram
+ GENERIC MAP (
+ address_reg_b => "CLOCK1",
+ clock_enable_input_a => "BYPASS",
+ clock_enable_input_b => "BYPASS",
+ clock_enable_output_a => "BYPASS",
+ clock_enable_output_b => "BYPASS",
+ indata_reg_b => "CLOCK1",
+ init_file => g_init_file,
+ init_file_layout => "PORT_B",
+ intended_device_family => "Arria 10",
+ lpm_type => "altera_syncram",
+ numwords_a => g_nof_words_a,
+ numwords_b => g_nof_words_b,
+ operation_mode => "BIDIR_DUAL_PORT",
+ outdata_aclr_a => "NONE",
+ outdata_aclr_b => "NONE",
+ outdata_reg_a => c_outdata_reg_a,
+ outdata_reg_b => c_outdata_reg_b,
+ power_up_uninitialized => "FALSE",
+ read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+ read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+ widthad_a => g_adr_a_w,
+ widthad_b => g_adr_b_w,
+ width_a => g_dat_a_w,
+ width_b => g_dat_b_w,
+ width_byteena_a => 1,
+ width_byteena_b => 1
+ )
+ PORT MAP (
+ address_a => address_a,
+ address_b => address_b,
+ clock0 => clk_a,
+ clock1 => clk_b,
+ data_a => data_a,
+ data_b => data_b,
+ wren_a => wren_a,
+ wren_b => wren_b,
+ q_a => q_a,
+ q_b => q_b
+ );
+
+END SYN;
+
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_r_w.qsys b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_r_w.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..5d2254302de088f9dd94018653a683825655ca3f
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_r_w.qsys
@@ -0,0 +1,142 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_ram_r_w">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element ram_2port_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="clock" internal="ram_2port_0.clock" type="clock" dir="end">
+ <port name="clock" internal="clock" />
+ </interface>
+ <interface name="data" internal="ram_2port_0.data" type="conduit" dir="end">
+ <port name="data" internal="data" />
+ </interface>
+ <interface name="q" internal="ram_2port_0.q" type="conduit" dir="end">
+ <port name="q" internal="q" />
+ </interface>
+ <interface name="ram_input" internal="ram_2port_0.ram_input" />
+ <interface name="ram_output" internal="ram_2port_0.ram_output" />
+ <interface
+ name="rdaddress"
+ internal="ram_2port_0.rdaddress"
+ type="conduit"
+ dir="end">
+ <port name="rdaddress" internal="rdaddress" />
+ </interface>
+ <interface
+ name="wraddress"
+ internal="ram_2port_0.wraddress"
+ type="conduit"
+ dir="end">
+ <port name="wraddress" internal="wraddress" />
+ </interface>
+ <interface name="wren" internal="ram_2port_0.wren" type="conduit" dir="end">
+ <port name="wren" internal="wren" />
+ </interface>
+ <module
+ name="ram_2port_0"
+ kind="ram_2port"
+ version="20.0.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_ACLR_READ_INPUT_RDADDRESS" value="false" />
+ <parameter name="GUI_ACLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_ACLR_READ_OUTPUT_QB" value="false" />
+ <parameter name="GUI_BLANK_MEMORY" value="1" />
+ <parameter name="GUI_BYTE_ENABLE_A" value="false" />
+ <parameter name="GUI_BYTE_ENABLE_B" value="false" />
+ <parameter name="GUI_BYTE_ENABLE_WIDTH" value="8" />
+ <parameter name="GUI_CLKEN_ADDRESS_STALL_A" value="false" />
+ <parameter name="GUI_CLKEN_ADDRESS_STALL_B" value="false" />
+ <parameter name="GUI_CLKEN_INPUT_REG_A" value="false" />
+ <parameter name="GUI_CLKEN_INPUT_REG_B" value="false" />
+ <parameter name="GUI_CLKEN_OUTPUT_REG_A" value="false" />
+ <parameter name="GUI_CLKEN_OUTPUT_REG_B" value="false" />
+ <parameter name="GUI_CLKEN_RDADDRESSSTALL" value="false" />
+ <parameter name="GUI_CLKEN_READ_INPUT_REG" value="false" />
+ <parameter name="GUI_CLKEN_READ_OUTPUT_REG" value="false" />
+ <parameter name="GUI_CLKEN_WRADDRESSSTALL" value="false" />
+ <parameter name="GUI_CLKEN_WRITE_INPUT_REG" value="false" />
+ <parameter name="GUI_CLOCK_TYPE" value="0" />
+ <parameter name="GUI_COHERENT_READ" value="false" />
+ <parameter name="GUI_CONSTRAINED_DONT_CARE" value="true" />
+ <parameter name="GUI_DATAA_WIDTH" value="8" />
+ <parameter name="GUI_DIFFERENT_CLKENS" value="false" />
+ <parameter name="GUI_ECCENCBYPASS" value="false" />
+ <parameter name="GUI_ECC_DOUBLE" value="false" />
+ <parameter name="GUI_ECC_PIPELINE" value="false" />
+ <parameter name="GUI_ECC_TRIPLE" value="false" />
+ <parameter name="GUI_FILE_REFERENCE" value="0" />
+ <parameter name="GUI_FORCE_TO_ZERO" value="false" />
+ <parameter name="GUI_INIT_FILE_LAYOUT" value="PORT_B" />
+ <parameter name="GUI_INIT_SIM_TO_X" value="false" />
+ <parameter name="GUI_LC_IMPLEMENTION_OPTIONS" value="0" />
+ <parameter name="GUI_MAX_DEPTH" value="Auto" />
+ <parameter name="GUI_MEMSIZE_BITS" value="256" />
+ <parameter name="GUI_MEMSIZE_WORDS" value="32" />
+ <parameter name="GUI_MEM_IN_BITS" value="0" />
+ <parameter name="GUI_MIF_FILENAME" value="./ram_1024.hex" />
+ <parameter name="GUI_MODE" value="0" />
+ <parameter name="GUI_NBE_A" value="false" />
+ <parameter name="GUI_NBE_B" value="false" />
+ <parameter name="GUI_OPTIMIZATION_OPTION" value="0" />
+ <parameter name="GUI_PR" value="false" />
+ <parameter name="GUI_QA_WIDTH" value="8" />
+ <parameter name="GUI_QB_WIDTH" value="8" />
+ <parameter name="GUI_Q_PORT_MODE" value="2" />
+ <parameter name="GUI_RAM_BLOCK_TYPE" value="Auto" />
+ <parameter name="GUI_RDEN_DOUBLE" value="false" />
+ <parameter name="GUI_RDEN_SINGLE" value="false" />
+ <parameter name="GUI_RDW_A_MODE" value="New Data" />
+ <parameter name="GUI_RDW_B_MODE" value="New Data" />
+ <parameter name="GUI_READ_INPUT_RDADDRESS" value="true" />
+ <parameter name="GUI_READ_OUTPUT_QA" value="true" />
+ <parameter name="GUI_READ_OUTPUT_QB" value="true" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QB" value="false" />
+ <parameter name="GUI_TBENCH" value="false" />
+ <parameter name="GUI_TDP_EMULATE" value="false" />
+ <parameter name="GUI_VAR_WIDTH" value="false" />
+ <parameter name="GUI_WIDTH_ECCENCPARITY" value="8" />
+ <parameter name="GUI_WRITE_INPUT_PORTS" value="true" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_r_w.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_r_w.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0c8dbbb41bf31a85cc111e8b2668a9d848b7f1ba
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_r_w.vhd
@@ -0,0 +1,155 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- RadioHDL wrapper
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE technology_lib.technology_pkg.all;
+
+LIBRARY altera_lnsim;
+USE altera_lnsim.altera_lnsim_components.all;
+
+ENTITY ip_arria10_e2sg_ram_r_w IS
+ GENERIC (
+ g_inferred : BOOLEAN := FALSE;
+ g_adr_w : NATURAL := 5;
+ g_dat_w : NATURAL := 8;
+ g_nof_words : NATURAL := 2**5;
+ g_rd_latency : NATURAL := 1; -- choose 1 or 2
+ g_init_file : STRING := "UNUSED"
+ );
+ PORT (
+ clk : IN STD_LOGIC := '1';
+ data : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
+ rdaddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
+ wraddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
+ wren : IN STD_LOGIC := '0';
+ q : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
+ );
+END ip_arria10_e2sg_ram_r_w;
+
+
+ARCHITECTURE SYN OF ip_arria10_e2sg_ram_r_w IS
+
+ CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
+
+ COMPONENT altera_syncram
+ GENERIC (
+ address_aclr_b : string;
+ address_reg_b : string;
+ clock_enable_input_a : string;
+ clock_enable_input_b : string;
+ clock_enable_output_b : string;
+ init_file : string;
+ intended_device_family : string;
+ lpm_type : string;
+ numwords_a : integer;
+ numwords_b : integer;
+ operation_mode : string;
+ outdata_aclr_b : string;
+ outdata_reg_b : string;
+ power_up_uninitialized : string;
+ widthad_a : integer;
+ widthad_b : integer;
+ width_a : integer;
+ width_b : integer;
+ width_byteena_a : integer
+ );
+ PORT (
+ address_a : in std_logic_vector(g_adr_w-1 downto 0);
+ address_b : in std_logic_vector(g_adr_w-1 downto 0);
+ clock0 : in std_logic;
+ data_a : in std_logic_vector(g_dat_w-1 downto 0);
+ wren_a : in std_logic;
+ q_b : out std_logic_vector(g_dat_w-1 downto 0)
+ );
+ END COMPONENT;
+
+ SIGNAL rdaddr : natural range 0 to g_nof_words - 1;
+ SIGNAL wraddr : natural range 0 to g_nof_words - 1;
+
+ SIGNAL out_q : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ SIGNAL reg_q : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+
+BEGIN
+
+ ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e2sg_ram_r_w : read latency must be 1 (default) or 2" SEVERITY FAILURE;
+
+ gen_ip : IF g_inferred=FALSE GENERATE
+ -- Copied from ip_arria10_e2sg_ram_r_w/ram_2port_140/sim/ip_arria10_e2sg_ram_r_w_ram_2port_140_hukd7xi.vhd
+ u_altera_syncram : altera_syncram
+ GENERIC MAP (
+ address_aclr_b => "NONE",
+ address_reg_b => "CLOCK0",
+ clock_enable_input_a => "BYPASS",
+ clock_enable_input_b => "BYPASS",
+ clock_enable_output_b => "BYPASS",
+ init_file => g_init_file,
+ intended_device_family => "Arria 10",
+ lpm_type => "altera_syncram",
+ numwords_a => g_nof_words,
+ numwords_b => g_nof_words,
+ operation_mode => "DUAL_PORT",
+ outdata_aclr_b => "NONE",
+ outdata_reg_b => c_outdata_reg_b,
+ power_up_uninitialized => "FALSE",
+ widthad_a => g_adr_w,
+ widthad_b => g_adr_w,
+ width_a => g_dat_w,
+ width_b => g_dat_w,
+ width_byteena_a => 1
+ )
+ PORT MAP (
+ address_a => wraddress,
+ address_b => rdaddress,
+ clock0 => clk,
+ data_a => data,
+ wren_a => wren,
+ q_b => q
+ );
+ END GENERATE;
+
+ gen_inferred : IF g_inferred=TRUE GENERATE
+ rdaddr <= TO_INTEGER(UNSIGNED(rdaddress));
+ wraddr <= TO_INTEGER(UNSIGNED(wraddress));
+
+ u_mem : entity work.ip_arria10_e2sg_simple_dual_port_ram_single_clock
+ generic map (
+ DATA_WIDTH => g_dat_w,
+ ADDR_WIDTH => g_adr_w
+ )
+ port map (
+ clk => clk,
+ raddr => rdaddr,
+ waddr => wraddr,
+ data => data,
+ we => wren,
+ q => out_q
+ );
+
+ reg_q <= out_q WHEN rising_edge(clk);
+
+ q <= out_q WHEN g_rd_latency=1 ELSE reg_q;
+ END GENERATE;
+
+END SYN;
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_dual_clock.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_dual_clock.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1b73b9194dd5f0240966844dc63525c8ef427c98
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_dual_clock.vhd
@@ -0,0 +1,80 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- The inferred Altera code was obtained using template insert with Quartus 14.0a10.
+
+-- Quartus II VHDL Template
+-- Simple Dual-Port RAM with different read/write addresses and
+-- different read/write clock
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ip_arria10_e2sg_simple_dual_port_ram_dual_clock is
+
+ generic
+ (
+ DATA_WIDTH : natural := 8;
+ ADDR_WIDTH : natural := 6
+ );
+
+ port
+ (
+ rclk : in std_logic;
+ wclk : in std_logic;
+ raddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+ waddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+ data : in std_logic_vector((DATA_WIDTH-1) downto 0);
+ we : in std_logic := '1';
+ q : out std_logic_vector((DATA_WIDTH -1) downto 0)
+ );
+
+end ip_arria10_e2sg_simple_dual_port_ram_dual_clock;
+
+architecture rtl of ip_arria10_e2sg_simple_dual_port_ram_dual_clock is
+
+ -- Build a 2-D array type for the RAM
+ subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
+ type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
+
+ -- Declare the RAM signal.
+ signal ram : memory_t;
+
+begin
+
+ process(wclk)
+ begin
+ if(rising_edge(wclk)) then
+ if(we = '1') then
+ ram(waddr) <= data;
+ end if;
+ end if;
+ end process;
+
+ process(rclk)
+ begin
+ if(rising_edge(rclk)) then
+ q <= ram(raddr);
+ end if;
+ end process;
+
+end rtl;
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_single_clock.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_single_clock.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bf4b74439e465171aa09ffee45eaa3c3a16b85f9
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_single_clock.vhd
@@ -0,0 +1,76 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- The inferred Altera code was obtained using template insert with Quartus 14.0a10.
+-- Quartus II VHDL Template
+-- Simple Dual-Port RAM with different read/write addresses but
+-- single read/write clock
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ip_arria10_e2sg_simple_dual_port_ram_single_clock is
+
+ generic
+ (
+ DATA_WIDTH : natural := 8;
+ ADDR_WIDTH : natural := 6
+ );
+
+ port
+ (
+ clk : in std_logic;
+ raddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+ waddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+ data : in std_logic_vector((DATA_WIDTH-1) downto 0);
+ we : in std_logic := '1';
+ q : out std_logic_vector((DATA_WIDTH -1) downto 0)
+ );
+
+end ip_arria10_e2sg_simple_dual_port_ram_single_clock;
+
+architecture rtl of ip_arria10_e2sg_simple_dual_port_ram_single_clock is
+
+ -- Build a 2-D array type for the RAM
+ subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
+ type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
+
+ -- Declare the RAM signal.
+ signal ram : memory_t;
+
+begin
+
+ process(clk)
+ begin
+ if(rising_edge(clk)) then
+ if(we = '1') then
+ ram(waddr) <= data;
+ end if;
+
+ -- On a read during a write to the same address, the read will
+ -- return the OLD data at the address
+ q <= ram(raddr);
+ end if;
+ end process;
+
+end rtl;
+
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_true_dual_port_ram_dual_clock.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_true_dual_port_ram_dual_clock.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c460b74fc2e3f879e00897578ad2515d27270407
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_true_dual_port_ram_dual_clock.vhd
@@ -0,0 +1,92 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- The inferred Altera code was obtained using template insert with Quartus 14.0a10.
+
+-- Quartus II VHDL Template
+-- True Dual-Port RAM with dual clock
+--
+-- Read-during-write on port A or B returns newly written data
+--
+-- Read-during-write on port A and B returns unknown data.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ip_arria10_e2sg_true_dual_port_ram_dual_clock is
+
+ generic
+ (
+ DATA_WIDTH : natural := 8;
+ ADDR_WIDTH : natural := 6
+ );
+
+ port
+ (
+ clk_a : in std_logic;
+ clk_b : in std_logic;
+ addr_a : in natural range 0 to 2**ADDR_WIDTH - 1;
+ addr_b : in natural range 0 to 2**ADDR_WIDTH - 1;
+ data_a : in std_logic_vector((DATA_WIDTH-1) downto 0);
+ data_b : in std_logic_vector((DATA_WIDTH-1) downto 0);
+ we_a : in std_logic := '1';
+ we_b : in std_logic := '1';
+ q_a : out std_logic_vector((DATA_WIDTH -1) downto 0);
+ q_b : out std_logic_vector((DATA_WIDTH -1) downto 0)
+ );
+
+end ip_arria10_e2sg_true_dual_port_ram_dual_clock;
+
+architecture rtl of ip_arria10_e2sg_true_dual_port_ram_dual_clock is
+
+ -- Build a 2-D array type for the RAM
+ subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
+ type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
+
+ -- Declare the RAM
+ shared variable ram : memory_t;
+
+begin
+
+ -- Port A
+ process(clk_a)
+ begin
+ if(rising_edge(clk_a)) then
+ if(we_a = '1') then
+ ram(addr_a) := data_a;
+ end if;
+ q_a <= ram(addr_a);
+ end if;
+ end process;
+
+ -- Port B
+ process(clk_b)
+ begin
+ if(rising_edge(clk_b)) then
+ if(we_b = '1') then
+ ram(addr_b) := data_b;
+ end if;
+ q_b <= ram(addr_b);
+ end if;
+ end process;
+
+end rtl;
diff --git a/libraries/technology/ip_arria10_e2sg/temp_sense/README.patch b/libraries/technology/ip_arria10_e2sg/temp_sense/README.patch
new file mode 100644
index 0000000000000000000000000000000000000000..5d049715990215f956082a0c913d1a6816a1758f
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/temp_sense/README.patch
@@ -0,0 +1,4 @@
+The patch is generated with:
+
+diff -cB ip_arria10_e3sge3_temp_sense/altera_temp_sense_151/synth/altera_temp_sense.sdc generated/altera_temp_sense_151/synth/altera_temp_sense.sdc >altera_temp_sense.sdc.patch
+
diff --git a/libraries/technology/ip_arria10_e2sg/temp_sense/altera_temp_sense.sdc.patch b/libraries/technology/ip_arria10_e2sg/temp_sense/altera_temp_sense.sdc.patch
new file mode 100644
index 0000000000000000000000000000000000000000..443cbc214f44448ef772f2e3fbc18771491088f4
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/temp_sense/altera_temp_sense.sdc.patch
@@ -0,0 +1,19 @@
+*** ip_arria10_e3sge3_temp_sense/altera_temp_sense_151/synth/altera_temp_sense.sdc 2016-01-29 09:56:26.683213797 +0100
+--- generated/altera_temp_sense_151/synth/altera_temp_sense.sdc 2016-01-29 09:58:08.553558667 +0100
+***************
+*** 11,15 ****
+ # agreement for further details.
+
+
+! # Create clock for temperature sensor internal clock
+! create_clock -period 1000 -name altera_ts_clk [get_nodes {*altera_temp_sense:temp_sense_0|sd1~sn_adc_ts_clk}]
+\ No newline at end of file
+--- 11,18 ----
+ # agreement for further details.
+
+
+! # Create clock for temperature sensor internal clock
+! create_clock -period 1000 -name altera_ts_clk [get_nodes {*altera_temp_sense:temp_sense_0|sd1~sn_adc_ts_clk}]
+! # extra virtual clock:
+! create_clock -period 1000 -name altera_ts_clk.reg [get_nodes {*altera_temp_sense:temp_sense_0|sd1~sn_adc_ts_clk.reg}]
+!
diff --git a/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..46289f9ec305459f1f5df9c3933c4cb12ebdec0e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl
@@ -0,0 +1,37 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_temp_sense/sim"
+
+vmap altera_temp_sense_180 ./work/
+
+ vlog "$IP_DIR/../altera_temp_sense_180/sim/altera_temp_sense.v" -work altera_temp_sense_180
+ vcom "$IP_DIR/ip_arria10_e2sg_temp_sense.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/temp_sense/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..ffb3cf79622f2a691f8aa840291b6a1e4f72c209
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/temp_sense/hdllib.cfg
@@ -0,0 +1,23 @@
+hdl_lib_name = ip_arria10_e2sg_temp_sense
+hdl_library_clause_name = ip_arria10_e2sg_temp_sense_altera_temp_sense_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+#modelsim_compile_ip_files =
+# $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_temp_sense/ip_arria10_e2sg_temp_sense.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_temp_sense.qsys
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/temp_sense/ip_arria10_e2sg_temp_sense.qsys b/libraries/technology/ip_arria10_e2sg/temp_sense/ip_arria10_e2sg_temp_sense.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..7a0d713c54f77e77eab892068799d3addaf33db7
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/temp_sense/ip_arria10_e2sg_temp_sense.qsys
@@ -0,0 +1,87 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_temp_sense">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element temp_sense_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="clk" internal="temp_sense_0.clk" />
+ <interface
+ name="corectl"
+ internal="temp_sense_0.corectl"
+ type="conduit"
+ dir="end">
+ <port name="corectl" internal="corectl" />
+ </interface>
+ <interface name="eoc" internal="temp_sense_0.eoc" type="conduit" dir="end">
+ <port name="eoc" internal="eoc" />
+ </interface>
+ <interface name="reset" internal="temp_sense_0.reset" type="conduit" dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="tempout"
+ internal="temp_sense_0.tempout"
+ type="conduit"
+ dir="end">
+ <port name="tempout" internal="tempout" />
+ </interface>
+ <interface name="tsdcaldone" internal="temp_sense_0.tsdcaldone" />
+ <interface name="tsdcalo" internal="temp_sense_0.tsdcalo" />
+ <module
+ name="temp_sense_0"
+ kind="altera_temp_sense"
+ version="19.1.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
+ <parameter name="CE_CHECK" value="false" />
+ <parameter name="CLK_FREQUENCY" value="1.0" />
+ <parameter name="CLOCK_DIVIDER_VALUE" value="40" />
+ <parameter name="CLR_CHECK" value="false" />
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="NUMBER_OF_SAMPLES" value="128" />
+ <parameter name="POI_CAL_TEMPERATURE" value="85" />
+ <parameter name="SIM_TSDCALO" value="0" />
+ <parameter name="USER_OFFSET_ENABLE" value="off" />
+ <parameter name="USE_WYS" value="on" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/temp_sense/run_patch.sh b/libraries/technology/ip_arria10_e2sg/temp_sense/run_patch.sh
new file mode 100755
index 0000000000000000000000000000000000000000..c03ae5de5d6f063efe85dc30b77bf10aa55c4dc2
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/temp_sense/run_patch.sh
@@ -0,0 +1,10 @@
+#!/bin/bash
+
+patchfile='altera_temp_sense.sdc.patch'
+
+echo -e "Applying patch: $patchfile\n"
+
+cd generated/altera_temp_sense_151/synth/
+patch <../../../${patchfile}
+
+echo "done."
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..fb04e579cf4beec06569ffc587aa25476ef515ab
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/compile_ip.tcl
@@ -0,0 +1,34 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_pll_10g/sim"
+
+ vcom "$IP_DIR/ip_arria10_e2sg_transceiver_pll_10g.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..e94957fba13f0b4249679ca54aa39867292d57ed
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_transceiver_pll_10g
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_atx_pll_a10_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_pll_10g/ip_arria10_e2sg_transceiver_pll_10g.qip
+
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_transceiver_pll_10g.qsys
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/ip_arria10_e2sg_transceiver_pll_10g.qsys b/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/ip_arria10_e2sg_transceiver_pll_10g.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..3096bce5a3e313d3279a5f0e16ef6331f3d51b44
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/ip_arria10_e2sg_transceiver_pll_10g.qsys
@@ -0,0 +1,221 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_transceiver_pll_10g">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element xcvr_atx_pll_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>reconfig_avmm0</key>
+ <value>
+ <connectionPointName>reconfig_avmm0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='reconfig_avmm0' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>12</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="mcgb_rst"
+ internal="xcvr_atx_pll_a10_0.mcgb_rst"
+ type="conduit"
+ dir="end">
+ <port name="mcgb_rst" internal="mcgb_rst" />
+ </interface>
+ <interface
+ name="mcgb_serial_clk"
+ internal="xcvr_atx_pll_a10_0.mcgb_serial_clk"
+ type="hssi_serial_clock"
+ dir="start">
+ <port name="mcgb_serial_clk" internal="mcgb_serial_clk" />
+ </interface>
+ <interface
+ name="pll_cal_busy"
+ internal="xcvr_atx_pll_a10_0.pll_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="pll_cal_busy" internal="pll_cal_busy" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="xcvr_atx_pll_a10_0.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="xcvr_atx_pll_a10_0.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_refclk0"
+ internal="xcvr_atx_pll_a10_0.pll_refclk0"
+ type="clock"
+ dir="end">
+ <port name="pll_refclk0" internal="pll_refclk0" />
+ </interface>
+ <interface
+ name="reconfig_avmm0"
+ internal="xcvr_atx_pll_a10_0.reconfig_avmm0"
+ type="avalon"
+ dir="end">
+ <port name="reconfig_address0" internal="reconfig_address0" />
+ <port name="reconfig_read0" internal="reconfig_read0" />
+ <port name="reconfig_readdata0" internal="reconfig_readdata0" />
+ <port name="reconfig_waitrequest0" internal="reconfig_waitrequest0" />
+ <port name="reconfig_write0" internal="reconfig_write0" />
+ <port name="reconfig_writedata0" internal="reconfig_writedata0" />
+ </interface>
+ <interface
+ name="reconfig_clk0"
+ internal="xcvr_atx_pll_a10_0.reconfig_clk0"
+ type="clock"
+ dir="end">
+ <port name="reconfig_clk0" internal="reconfig_clk0" />
+ </interface>
+ <interface
+ name="reconfig_reset0"
+ internal="xcvr_atx_pll_a10_0.reconfig_reset0"
+ type="reset"
+ dir="end">
+ <port name="reconfig_reset0" internal="reconfig_reset0" />
+ </interface>
+ <interface
+ name="tx_serial_clk"
+ internal="xcvr_atx_pll_a10_0.tx_serial_clk"
+ type="hssi_serial_clock"
+ dir="start">
+ <port name="tx_serial_clk" internal="tx_serial_clk" />
+ </interface>
+ <module
+ name="xcvr_atx_pll_a10_0"
+ kind="altera_xcvr_atx_pll_a10"
+ version="19.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="bw_sel" value="low" />
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="enable_16G_path" value="0" />
+ <parameter name="enable_8G_path" value="1" />
+ <parameter name="enable_analog_resets" value="0" />
+ <parameter name="enable_bonding_clks" value="0" />
+ <parameter name="enable_cascade_out" value="0" />
+ <parameter name="enable_debug_ports_parameters" value="0" />
+ <parameter name="enable_ext_lockdetect_ports" value="0" />
+ <parameter name="enable_fb_comp_bonding" value="0" />
+ <parameter name="enable_hfreq_clk" value="1" />
+ <parameter name="enable_hip_cal_done_port" value="0" />
+ <parameter name="enable_manual_configuration" value="1" />
+ <parameter name="enable_mcgb" value="1" />
+ <parameter name="enable_mcgb_pcie_clksw" value="0" />
+ <parameter name="enable_pcie_clk" value="0" />
+ <parameter name="enable_pld_atx_cal_busy_port" value="1" />
+ <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
+ <parameter name="enable_pll_reconfig" value="1" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="mcgb_aux_clkin_cnt" value="0" />
+ <parameter name="mcgb_div" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="pma_width" value="64" />
+ <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
+ <parameter name="prot_mode" value="Basic" />
+ <parameter name="rcfg_debug" value="0" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="1" />
+ <parameter name="rcfg_jtag_enable" value="1" />
+ <parameter name="rcfg_mif_file_enable" value="1" />
+ <parameter name="rcfg_multi_enable" value="0" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_data0" value="" />
+ <parameter name="rcfg_profile_data1" value="" />
+ <parameter name="rcfg_profile_data2" value="" />
+ <parameter name="rcfg_profile_data3" value="" />
+ <parameter name="rcfg_profile_data4" value="" />
+ <parameter name="rcfg_profile_data5" value="" />
+ <parameter name="rcfg_profile_data6" value="" />
+ <parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_sv_file_enable" value="1" />
+ <parameter name="rcfg_txt_file_enable" value="0" />
+ <parameter name="refclk_cnt" value="1" />
+ <parameter name="refclk_index" value="0" />
+ <parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
+ <parameter name="set_auto_reference_clock_frequency" value="644.53125" />
+ <parameter name="set_capability_reg_enable" value="1" />
+ <parameter name="set_csr_soft_logic_enable" value="1" />
+ <parameter name="set_fref_clock_frequency" value="100.0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_k_counter" value="1" />
+ <parameter name="set_l_cascade_counter" value="4" />
+ <parameter name="set_l_cascade_predivider" value="1" />
+ <parameter name="set_l_counter" value="2" />
+ <parameter name="set_m_counter" value="1" />
+ <parameter name="set_manual_reference_clock_frequency" value="100.0" />
+ <parameter name="set_output_clock_frequency" value="5156.25" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
+ <parameter name="set_ref_clk_div" value="1" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="silicon_rev" value="false" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="test_mode" value="0" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..acd0d01beafdf9a36f59f649285fa21e7a6e2bb6
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_1/sim"
+
+
+ vcom "$IP_DIR/ip_arria10_e2sg_transceiver_reset_controller_1.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..4a0b08c882118f346b32bddce722b1adc1d7a136
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_transceiver_reset_controller_1
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_1_altera_xcvr_reset_control_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_1/ip_arria10_e2sg_transceiver_reset_controller_1.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_transceiver_reset_controller_1.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/ip_arria10_e2sg_transceiver_reset_controller_1.qsys b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/ip_arria10_e2sg_transceiver_reset_controller_1.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..9f64271e088f3eaeedfdd763af49313099cdebab
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/ip_arria10_e2sg_transceiver_reset_controller_1.qsys
@@ -0,0 +1,173 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_transceiver_reset_controller_1">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element xcvr_reset_control_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="clock"
+ internal="xcvr_reset_control_0.clock"
+ type="clock"
+ dir="end">
+ <port name="clock" internal="clock" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="xcvr_reset_control_0.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="xcvr_reset_control_0.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_select"
+ internal="xcvr_reset_control_0.pll_select"
+ type="conduit"
+ dir="end">
+ <port name="pll_select" internal="pll_select" />
+ </interface>
+ <interface
+ name="reset"
+ internal="xcvr_reset_control_0.reset"
+ type="reset"
+ dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="xcvr_reset_control_0.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="xcvr_reset_control_0.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="xcvr_reset_control_0.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="xcvr_reset_control_0.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_ready"
+ internal="xcvr_reset_control_0.rx_ready"
+ type="conduit"
+ dir="end">
+ <port name="rx_ready" internal="rx_ready" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="xcvr_reset_control_0.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="xcvr_reset_control_0.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="xcvr_reset_control_0.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_ready"
+ internal="xcvr_reset_control_0.tx_ready"
+ type="conduit"
+ dir="end">
+ <port name="tx_ready" internal="tx_ready" />
+ </interface>
+ <module
+ name="xcvr_reset_control_0"
+ kind="altera_xcvr_reset_control"
+ version="19.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CHANNELS" value="1" />
+ <parameter name="PLLS" value="1" />
+ <parameter name="REDUCED_SIM_TIME" value="1" />
+ <parameter name="RX_ENABLE" value="1" />
+ <parameter name="RX_PER_CHANNEL" value="1" />
+ <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+ <parameter name="SYNCHRONIZE_RESET" value="1" />
+ <parameter name="SYS_CLK_IN_MHZ" value="156" />
+ <parameter name="TX_ENABLE" value="1" />
+ <parameter name="TX_PER_CHANNEL" value="0" />
+ <parameter name="TX_PLL_ENABLE" value="1" />
+ <parameter name="T_PLL_LOCK_HYST" value="60" />
+ <parameter name="T_PLL_POWERDOWN" value="1000" />
+ <parameter name="T_RX_ANALOGRESET" value="70000" />
+ <parameter name="T_RX_DIGITALRESET" value="4000" />
+ <parameter name="T_TX_ANALOGRESET" value="70000" />
+ <parameter name="T_TX_DIGITALRESET" value="70000" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_pll_cal_busy" value="0" />
+ <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="gui_split_interfaces" value="0" />
+ <parameter name="gui_tx_auto_reset" value="0" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e5371e0872f8623555348a631ced65524bab8743
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/compile_ip.tcl
@@ -0,0 +1,34 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_12/sim"
+
+ vcom "$IP_DIR/ip_arria10_e2sg_transceiver_reset_controller_12.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..2508a58c562909e113b8f8c255a4823f4da31a50
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_transceiver_reset_controller_12
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_12_altera_xcvr_reset_control_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_12/ip_arria10_e2sg_transceiver_reset_controller_12.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_transceiver_reset_controller_12.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/ip_arria10_e2sg_transceiver_reset_controller_12.qsys b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/ip_arria10_e2sg_transceiver_reset_controller_12.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..7750717329ce3ef943f9a7eee6127de5473d082b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/ip_arria10_e2sg_transceiver_reset_controller_12.qsys
@@ -0,0 +1,173 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_transceiver_reset_controller_12">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element transceiver_reset_controller_inst
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="clock"
+ internal="transceiver_reset_controller_inst.clock"
+ type="clock"
+ dir="end">
+ <port name="clock" internal="clock" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="transceiver_reset_controller_inst.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="transceiver_reset_controller_inst.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_select"
+ internal="transceiver_reset_controller_inst.pll_select"
+ type="conduit"
+ dir="end">
+ <port name="pll_select" internal="pll_select" />
+ </interface>
+ <interface
+ name="reset"
+ internal="transceiver_reset_controller_inst.reset"
+ type="reset"
+ dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="transceiver_reset_controller_inst.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="transceiver_reset_controller_inst.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="transceiver_reset_controller_inst.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_ready"
+ internal="transceiver_reset_controller_inst.rx_ready"
+ type="conduit"
+ dir="end">
+ <port name="rx_ready" internal="rx_ready" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="transceiver_reset_controller_inst.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="transceiver_reset_controller_inst.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="transceiver_reset_controller_inst.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_ready"
+ internal="transceiver_reset_controller_inst.tx_ready"
+ type="conduit"
+ dir="end">
+ <port name="tx_ready" internal="tx_ready" />
+ </interface>
+ <module
+ name="transceiver_reset_controller_inst"
+ kind="altera_xcvr_reset_control"
+ version="19.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CHANNELS" value="12" />
+ <parameter name="PLLS" value="1" />
+ <parameter name="REDUCED_SIM_TIME" value="1" />
+ <parameter name="RX_ENABLE" value="1" />
+ <parameter name="RX_PER_CHANNEL" value="1" />
+ <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+ <parameter name="SYNCHRONIZE_RESET" value="1" />
+ <parameter name="SYS_CLK_IN_MHZ" value="156" />
+ <parameter name="TX_ENABLE" value="1" />
+ <parameter name="TX_PER_CHANNEL" value="0" />
+ <parameter name="TX_PLL_ENABLE" value="1" />
+ <parameter name="T_PLL_LOCK_HYST" value="60" />
+ <parameter name="T_PLL_POWERDOWN" value="1000" />
+ <parameter name="T_RX_ANALOGRESET" value="70000" />
+ <parameter name="T_RX_DIGITALRESET" value="4000" />
+ <parameter name="T_TX_ANALOGRESET" value="70000" />
+ <parameter name="T_TX_DIGITALRESET" value="70000" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_pll_cal_busy" value="0" />
+ <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="gui_split_interfaces" value="0" />
+ <parameter name="gui_tx_auto_reset" value="0" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5bbfb9dc8a990657cf60f8c99de0bc4118021b41
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_24/sim"
+
+
+ vcom "$IP_DIR/ip_arria10_e2sg_transceiver_reset_controller_24.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..77dad4207dc47e21b08e454a551c644bf736da4e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_transceiver_reset_controller_24
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_24_altera_xcvr_reset_control_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_24/ip_arria10_e2sg_transceiver_reset_controller_24.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_transceiver_reset_controller_24.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/ip_arria10_e2sg_transceiver_reset_controller_24.qsys b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/ip_arria10_e2sg_transceiver_reset_controller_24.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..fc126428a4794d88eb37f51e00811be752098590
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/ip_arria10_e2sg_transceiver_reset_controller_24.qsys
@@ -0,0 +1,173 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_transceiver_reset_controller_24">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element transceiver_reset_controller_inst
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="clock"
+ internal="transceiver_reset_controller_inst.clock"
+ type="clock"
+ dir="end">
+ <port name="clock" internal="clock" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="transceiver_reset_controller_inst.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="transceiver_reset_controller_inst.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_select"
+ internal="transceiver_reset_controller_inst.pll_select"
+ type="conduit"
+ dir="end">
+ <port name="pll_select" internal="pll_select" />
+ </interface>
+ <interface
+ name="reset"
+ internal="transceiver_reset_controller_inst.reset"
+ type="reset"
+ dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="transceiver_reset_controller_inst.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="transceiver_reset_controller_inst.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="transceiver_reset_controller_inst.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_ready"
+ internal="transceiver_reset_controller_inst.rx_ready"
+ type="conduit"
+ dir="end">
+ <port name="rx_ready" internal="rx_ready" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="transceiver_reset_controller_inst.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="transceiver_reset_controller_inst.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="transceiver_reset_controller_inst.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_ready"
+ internal="transceiver_reset_controller_inst.tx_ready"
+ type="conduit"
+ dir="end">
+ <port name="tx_ready" internal="tx_ready" />
+ </interface>
+ <module
+ name="transceiver_reset_controller_inst"
+ kind="altera_xcvr_reset_control"
+ version="19.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CHANNELS" value="24" />
+ <parameter name="PLLS" value="1" />
+ <parameter name="REDUCED_SIM_TIME" value="1" />
+ <parameter name="RX_ENABLE" value="1" />
+ <parameter name="RX_PER_CHANNEL" value="1" />
+ <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+ <parameter name="SYNCHRONIZE_RESET" value="1" />
+ <parameter name="SYS_CLK_IN_MHZ" value="156" />
+ <parameter name="TX_ENABLE" value="1" />
+ <parameter name="TX_PER_CHANNEL" value="0" />
+ <parameter name="TX_PLL_ENABLE" value="1" />
+ <parameter name="T_PLL_LOCK_HYST" value="60" />
+ <parameter name="T_PLL_POWERDOWN" value="1000" />
+ <parameter name="T_RX_ANALOGRESET" value="70000" />
+ <parameter name="T_RX_DIGITALRESET" value="4000" />
+ <parameter name="T_TX_ANALOGRESET" value="70000" />
+ <parameter name="T_TX_DIGITALRESET" value="70000" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_pll_cal_busy" value="0" />
+ <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="gui_split_interfaces" value="0" />
+ <parameter name="gui_tx_auto_reset" value="0" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..aebd7ffc4380dabb3247066427752b3d60f9958d
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/compile_ip.tcl
@@ -0,0 +1,34 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_3/sim"
+
+ vcom "$IP_DIR/ip_arria10_e2sg_transceiver_reset_controller_3.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..c3041472761a4d2222266c00aedd56a44f48c27b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/hdllib.cfg
@@ -0,0 +1,23 @@
+hdl_lib_name = ip_arria10_e2sg_transceiver_reset_controller_3
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_3_altera_xcvr_reset_control_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_3/ip_arria10_e2sg_transceiver_reset_controller_3.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_transceiver_reset_controller_3.qsys
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/ip_arria10_e2sg_transceiver_reset_controller_3.qsys b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/ip_arria10_e2sg_transceiver_reset_controller_3.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..e5644189242728028e5c280c016d9d20059974cc
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/ip_arria10_e2sg_transceiver_reset_controller_3.qsys
@@ -0,0 +1,173 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_transceiver_reset_controller_3">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element transceiver_reset_controller_inst
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="clock"
+ internal="transceiver_reset_controller_inst.clock"
+ type="clock"
+ dir="end">
+ <port name="clock" internal="clock" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="transceiver_reset_controller_inst.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="transceiver_reset_controller_inst.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_select"
+ internal="transceiver_reset_controller_inst.pll_select"
+ type="conduit"
+ dir="end">
+ <port name="pll_select" internal="pll_select" />
+ </interface>
+ <interface
+ name="reset"
+ internal="transceiver_reset_controller_inst.reset"
+ type="reset"
+ dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="transceiver_reset_controller_inst.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="transceiver_reset_controller_inst.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="transceiver_reset_controller_inst.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_ready"
+ internal="transceiver_reset_controller_inst.rx_ready"
+ type="conduit"
+ dir="end">
+ <port name="rx_ready" internal="rx_ready" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="transceiver_reset_controller_inst.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="transceiver_reset_controller_inst.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="transceiver_reset_controller_inst.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_ready"
+ internal="transceiver_reset_controller_inst.tx_ready"
+ type="conduit"
+ dir="end">
+ <port name="tx_ready" internal="tx_ready" />
+ </interface>
+ <module
+ name="transceiver_reset_controller_inst"
+ kind="altera_xcvr_reset_control"
+ version="19.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CHANNELS" value="3" />
+ <parameter name="PLLS" value="1" />
+ <parameter name="REDUCED_SIM_TIME" value="1" />
+ <parameter name="RX_ENABLE" value="1" />
+ <parameter name="RX_PER_CHANNEL" value="1" />
+ <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+ <parameter name="SYNCHRONIZE_RESET" value="1" />
+ <parameter name="SYS_CLK_IN_MHZ" value="156" />
+ <parameter name="TX_ENABLE" value="1" />
+ <parameter name="TX_PER_CHANNEL" value="0" />
+ <parameter name="TX_PLL_ENABLE" value="1" />
+ <parameter name="T_PLL_LOCK_HYST" value="60" />
+ <parameter name="T_PLL_POWERDOWN" value="1000" />
+ <parameter name="T_RX_ANALOGRESET" value="70000" />
+ <parameter name="T_RX_DIGITALRESET" value="4000" />
+ <parameter name="T_TX_ANALOGRESET" value="70000" />
+ <parameter name="T_TX_DIGITALRESET" value="70000" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_pll_cal_busy" value="0" />
+ <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="gui_split_interfaces" value="0" />
+ <parameter name="gui_tx_auto_reset" value="0" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..a0dddbff50147a52eddeb782e4516af07abf9fce
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/compile_ip.tcl
@@ -0,0 +1,34 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_4/sim"
+
+ vcom "$IP_DIR/ip_arria10_e2sg_transceiver_reset_controller_4.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..1afba83300023fa1019d5288140501261b0d5b98
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_transceiver_reset_controller_4
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_4_altera_xcvr_reset_control_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_4/ip_arria10_e2sg_transceiver_reset_controller_4.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_transceiver_reset_controller_4.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/ip_arria10_e2sg_transceiver_reset_controller_4.qsys b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/ip_arria10_e2sg_transceiver_reset_controller_4.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..94c08ca1ab375536d3322ee6bae0f24b5be6ee2a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/ip_arria10_e2sg_transceiver_reset_controller_4.qsys
@@ -0,0 +1,173 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_transceiver_reset_controller_4">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element transceiver_reset_controller_inst
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="clock"
+ internal="transceiver_reset_controller_inst.clock"
+ type="clock"
+ dir="end">
+ <port name="clock" internal="clock" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="transceiver_reset_controller_inst.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="transceiver_reset_controller_inst.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_select"
+ internal="transceiver_reset_controller_inst.pll_select"
+ type="conduit"
+ dir="end">
+ <port name="pll_select" internal="pll_select" />
+ </interface>
+ <interface
+ name="reset"
+ internal="transceiver_reset_controller_inst.reset"
+ type="reset"
+ dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="transceiver_reset_controller_inst.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="transceiver_reset_controller_inst.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="transceiver_reset_controller_inst.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_ready"
+ internal="transceiver_reset_controller_inst.rx_ready"
+ type="conduit"
+ dir="end">
+ <port name="rx_ready" internal="rx_ready" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="transceiver_reset_controller_inst.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="transceiver_reset_controller_inst.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="transceiver_reset_controller_inst.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_ready"
+ internal="transceiver_reset_controller_inst.tx_ready"
+ type="conduit"
+ dir="end">
+ <port name="tx_ready" internal="tx_ready" />
+ </interface>
+ <module
+ name="transceiver_reset_controller_inst"
+ kind="altera_xcvr_reset_control"
+ version="19.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CHANNELS" value="4" />
+ <parameter name="PLLS" value="1" />
+ <parameter name="REDUCED_SIM_TIME" value="1" />
+ <parameter name="RX_ENABLE" value="1" />
+ <parameter name="RX_PER_CHANNEL" value="1" />
+ <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+ <parameter name="SYNCHRONIZE_RESET" value="1" />
+ <parameter name="SYS_CLK_IN_MHZ" value="156" />
+ <parameter name="TX_ENABLE" value="1" />
+ <parameter name="TX_PER_CHANNEL" value="0" />
+ <parameter name="TX_PLL_ENABLE" value="1" />
+ <parameter name="T_PLL_LOCK_HYST" value="60" />
+ <parameter name="T_PLL_POWERDOWN" value="1000" />
+ <parameter name="T_RX_ANALOGRESET" value="70000" />
+ <parameter name="T_RX_DIGITALRESET" value="4000" />
+ <parameter name="T_TX_ANALOGRESET" value="70000" />
+ <parameter name="T_TX_DIGITALRESET" value="70000" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_pll_cal_busy" value="0" />
+ <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="gui_split_interfaces" value="0" />
+ <parameter name="gui_tx_auto_reset" value="0" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..bb2f21d04ed3c93a447951c8676a4ff3010b772e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/compile_ip.tcl
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_48/sim"
+
+
+ vcom "$IP_DIR/ip_arria10_e2sg_transceiver_reset_controller_48.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..530f4e613ef31acf0e995e14245fa7f516834a17
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e2sg_transceiver_reset_controller_48
+hdl_library_clause_name = ip_arria10_e2sg_transceiver_reset_controller_48_altera_xcvr_reset_control_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_xcvr_reset_control_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_48/ip_arria10_e2sg_transceiver_reset_controller_48.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_transceiver_reset_controller_48.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/ip_arria10_e2sg_transceiver_reset_controller_48.qsys b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/ip_arria10_e2sg_transceiver_reset_controller_48.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..17bf32e9f11ac10395838a44d5817b86b2ac506f
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/ip_arria10_e2sg_transceiver_reset_controller_48.qsys
@@ -0,0 +1,173 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_transceiver_reset_controller_48">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element transceiver_reset_controller_inst
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="clock"
+ internal="transceiver_reset_controller_inst.clock"
+ type="clock"
+ dir="end">
+ <port name="clock" internal="clock" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="transceiver_reset_controller_inst.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="transceiver_reset_controller_inst.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_select"
+ internal="transceiver_reset_controller_inst.pll_select"
+ type="conduit"
+ dir="end">
+ <port name="pll_select" internal="pll_select" />
+ </interface>
+ <interface
+ name="reset"
+ internal="transceiver_reset_controller_inst.reset"
+ type="reset"
+ dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="transceiver_reset_controller_inst.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="transceiver_reset_controller_inst.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="transceiver_reset_controller_inst.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_ready"
+ internal="transceiver_reset_controller_inst.rx_ready"
+ type="conduit"
+ dir="end">
+ <port name="rx_ready" internal="rx_ready" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="transceiver_reset_controller_inst.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="transceiver_reset_controller_inst.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="transceiver_reset_controller_inst.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_ready"
+ internal="transceiver_reset_controller_inst.tx_ready"
+ type="conduit"
+ dir="end">
+ <port name="tx_ready" internal="tx_ready" />
+ </interface>
+ <module
+ name="transceiver_reset_controller_inst"
+ kind="altera_xcvr_reset_control"
+ version="19.1"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CHANNELS" value="48" />
+ <parameter name="PLLS" value="1" />
+ <parameter name="REDUCED_SIM_TIME" value="1" />
+ <parameter name="RX_ENABLE" value="1" />
+ <parameter name="RX_PER_CHANNEL" value="1" />
+ <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+ <parameter name="SYNCHRONIZE_RESET" value="1" />
+ <parameter name="SYS_CLK_IN_MHZ" value="156" />
+ <parameter name="TX_ENABLE" value="1" />
+ <parameter name="TX_PER_CHANNEL" value="0" />
+ <parameter name="TX_PLL_ENABLE" value="1" />
+ <parameter name="T_PLL_LOCK_HYST" value="60" />
+ <parameter name="T_PLL_POWERDOWN" value="1000" />
+ <parameter name="T_RX_ANALOGRESET" value="70000" />
+ <parameter name="T_RX_DIGITALRESET" value="4000" />
+ <parameter name="T_TX_ANALOGRESET" value="70000" />
+ <parameter name="T_TX_DIGITALRESET" value="70000" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_pll_cal_busy" value="0" />
+ <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="gui_split_interfaces" value="0" />
+ <parameter name="gui_tx_auto_reset" value="0" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/README.txt b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/README.txt
new file mode 100755
index 0000000000000000000000000000000000000000..fa105db173e0dc963f59b1e10b143cf5cc782167
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/README.txt
@@ -0,0 +1,8 @@
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
+
+The ip_arria10_tse_sgmii_gx IP was ported to Quartus 14.0a10 for Arria10 by creating it in Qsys using the same parameter settings as the ip_arria10_tse_sgmii_lvds, but with GX IO.
+
+The tb_ip_arria10_tse_sgmii_gx.vhd verifies the DUT and simulates OK.
+
+For more information see: $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..72131625fde500fcb42c32616d5f52925542f538
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/compile_ip.tcl
@@ -0,0 +1,34 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+
+ vcom "$IP_DIR/ip_arria10_e2sg_tse_sgmii_gx.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..80ce0bd3c7c62e5e4165a0eb0742dc7228129dc7
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/hdllib.cfg
@@ -0,0 +1,25 @@
+hdl_lib_name = ip_arria10_e2sg_tse_sgmii_gx
+hdl_library_clause_name = ip_arria10_e2sg_tse_sgmii_gx_altera_eth_tse_180
+hdl_lib_uses_synth = common
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_eth_tse_180
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+ tb_ip_arria10_e2sg_tse_sgmii_gx.vhd
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/ip_arria10_e2sg_tse_sgmii_gx.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_tse_sgmii_gx.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/ip_arria10_e2sg_tse_sgmii_gx.qsys b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/ip_arria10_e2sg_tse_sgmii_gx.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..0395404ec584536a7f736171f612f2f878140507
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/ip_arria10_e2sg_tse_sgmii_gx.qsys
@@ -0,0 +1,409 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_tse_sgmii_gx">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element eth_tse_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>control_port</key>
+ <value>
+ <connectionPointName>control_port</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='control_port' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>10</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="control_port"
+ internal="eth_tse_0.control_port"
+ type="avalon"
+ dir="end">
+ <port name="reg_addr" internal="reg_addr" />
+ <port name="reg_busy" internal="reg_busy" />
+ <port name="reg_data_in" internal="reg_data_in" />
+ <port name="reg_data_out" internal="reg_data_out" />
+ <port name="reg_rd" internal="reg_rd" />
+ <port name="reg_wr" internal="reg_wr" />
+ </interface>
+ <interface
+ name="control_port_clock_connection"
+ internal="eth_tse_0.control_port_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="clk" internal="clk" />
+ </interface>
+ <interface name="mac_gmii_connection" internal="eth_tse_0.mac_gmii_connection" />
+ <interface name="mac_mii_connection" internal="eth_tse_0.mac_mii_connection" />
+ <interface
+ name="mac_misc_connection"
+ internal="eth_tse_0.mac_misc_connection"
+ type="conduit"
+ dir="end">
+ <port name="ff_rx_a_empty" internal="ff_rx_a_empty" />
+ <port name="ff_rx_a_full" internal="ff_rx_a_full" />
+ <port name="ff_rx_dsav" internal="ff_rx_dsav" />
+ <port name="ff_tx_a_empty" internal="ff_tx_a_empty" />
+ <port name="ff_tx_a_full" internal="ff_tx_a_full" />
+ <port name="ff_tx_crc_fwd" internal="ff_tx_crc_fwd" />
+ <port name="ff_tx_septy" internal="ff_tx_septy" />
+ <port name="rx_err_stat" internal="rx_err_stat" />
+ <port name="rx_frm_type" internal="rx_frm_type" />
+ <port name="tx_ff_uflow" internal="tx_ff_uflow" />
+ </interface>
+ <interface
+ name="mac_status_connection"
+ internal="eth_tse_0.mac_status_connection" />
+ <interface
+ name="pcs_mac_rx_clock_connection"
+ internal="eth_tse_0.pcs_mac_rx_clock_connection" />
+ <interface
+ name="pcs_mac_tx_clock_connection"
+ internal="eth_tse_0.pcs_mac_tx_clock_connection" />
+ <interface
+ name="pcs_ref_clk_clock_connection"
+ internal="eth_tse_0.pcs_ref_clk_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="ref_clk" internal="ref_clk" />
+ </interface>
+ <interface
+ name="receive"
+ internal="eth_tse_0.receive"
+ type="avalon_streaming"
+ dir="start">
+ <port name="ff_rx_data" internal="ff_rx_data" />
+ <port name="ff_rx_dval" internal="ff_rx_dval" />
+ <port name="ff_rx_eop" internal="ff_rx_eop" />
+ <port name="ff_rx_mod" internal="ff_rx_mod" />
+ <port name="ff_rx_rdy" internal="ff_rx_rdy" />
+ <port name="ff_rx_sop" internal="ff_rx_sop" />
+ <port name="rx_err" internal="rx_err" />
+ </interface>
+ <interface
+ name="receive_clock_connection"
+ internal="eth_tse_0.receive_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="ff_rx_clk" internal="ff_rx_clk" />
+ </interface>
+ <interface
+ name="reset_connection"
+ internal="eth_tse_0.reset_connection"
+ type="reset"
+ dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="eth_tse_0.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="eth_tse_0.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_cdr_refclk"
+ internal="eth_tse_0.rx_cdr_refclk"
+ type="clock"
+ dir="end">
+ <port name="rx_cdr_refclk" internal="rx_cdr_refclk" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="eth_tse_0.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="eth_tse_0.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_is_lockedtoref"
+ internal="eth_tse_0.rx_is_lockedtoref"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtoref" internal="rx_is_lockedtoref" />
+ </interface>
+ <interface
+ name="rx_set_locktodata"
+ internal="eth_tse_0.rx_set_locktodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_set_locktodata" internal="rx_set_locktodata" />
+ </interface>
+ <interface
+ name="rx_set_locktoref"
+ internal="eth_tse_0.rx_set_locktoref"
+ type="conduit"
+ dir="end">
+ <port name="rx_set_locktoref" internal="rx_set_locktoref" />
+ </interface>
+ <interface
+ name="serdes_control_connection"
+ internal="eth_tse_0.serdes_control_connection"
+ type="conduit"
+ dir="end">
+ <port name="rx_recovclkout" internal="rx_recovclkout" />
+ </interface>
+ <interface
+ name="serial_connection"
+ internal="eth_tse_0.serial_connection"
+ type="conduit"
+ dir="end">
+ <port name="rxp" internal="rxp" />
+ <port name="txp" internal="txp" />
+ </interface>
+ <interface
+ name="status_led_connection"
+ internal="eth_tse_0.status_led_connection"
+ type="conduit"
+ dir="end">
+ <port name="led_an" internal="led_an" />
+ <port name="led_char_err" internal="led_char_err" />
+ <port name="led_col" internal="led_col" />
+ <port name="led_crs" internal="led_crs" />
+ <port name="led_disp_err" internal="led_disp_err" />
+ <port name="led_link" internal="led_link" />
+ <port name="led_panel_link" internal="led_panel_link" />
+ </interface>
+ <interface name="tbi_connection" internal="eth_tse_0.tbi_connection" />
+ <interface
+ name="transmit"
+ internal="eth_tse_0.transmit"
+ type="avalon_streaming"
+ dir="end">
+ <port name="ff_tx_data" internal="ff_tx_data" />
+ <port name="ff_tx_eop" internal="ff_tx_eop" />
+ <port name="ff_tx_err" internal="ff_tx_err" />
+ <port name="ff_tx_mod" internal="ff_tx_mod" />
+ <port name="ff_tx_rdy" internal="ff_tx_rdy" />
+ <port name="ff_tx_sop" internal="ff_tx_sop" />
+ <port name="ff_tx_wren" internal="ff_tx_wren" />
+ </interface>
+ <interface
+ name="transmit_clock_connection"
+ internal="eth_tse_0.transmit_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="ff_tx_clk" internal="ff_tx_clk" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="eth_tse_0.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="eth_tse_0.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="eth_tse_0.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_serial_clk"
+ internal="eth_tse_0.tx_serial_clk"
+ type="hssi_serial_clock"
+ dir="end">
+ <port name="tx_serial_clk" internal="tx_serial_clk" />
+ </interface>
+ <module
+ name="eth_tse_0"
+ kind="altera_eth_tse"
+ version="19.4.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="AUTO_DEVICE" value="10AX115U3F45E2SG" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="ND_XCVR_RCFG_JTAG_ENABLE" value="0" />
+ <parameter name="ND_XCVR_SET_CAPABILITY_REG_ENABLE" value="0" />
+ <parameter name="ND_XCVR_SET_CSR_SOFT_LOGIC_ENABLE" value="0" />
+ <parameter name="ND_XCVR_SET_USER_IDENTIFIER" value="0" />
+ <parameter name="XCVR_RCFG_JTAG_ENABLE" value="0" />
+ <parameter name="XCVR_SET_CAPABILITY_REG_ENABLE" value="0" />
+ <parameter name="XCVR_SET_CSR_SOFT_LOGIC_ENABLE" value="0" />
+ <parameter name="XCVR_SET_PRBS_SOFT_LOGIC_ENABLE" value="0" />
+ <parameter name="XCVR_SET_USER_IDENTIFIER" value="0" />
+ <parameter name="adpt_multi_enable" value="1" />
+ <parameter name="adpt_recipe_cnt" value="1" />
+ <parameter name="adpt_recipe_data0" value="" />
+ <parameter name="adpt_recipe_data1" value="" />
+ <parameter name="adpt_recipe_data2" value="" />
+ <parameter name="adpt_recipe_data3" value="" />
+ <parameter name="adpt_recipe_data4" value="" />
+ <parameter name="adpt_recipe_data5" value="" />
+ <parameter name="adpt_recipe_data6" value="" />
+ <parameter name="adpt_recipe_data7" value="" />
+ <parameter name="adpt_recipe_select" value="0" />
+ <parameter name="cal_recipe_sel" value="NRZ_28Gbps_VSR" />
+ <parameter name="core_variation" value="MAC_PCS" />
+ <parameter name="ctle_gs1_val_a" value="999" />
+ <parameter name="ctle_gs1_val_b" value="999" />
+ <parameter name="ctle_gs2_val_a" value="999" />
+ <parameter name="ctle_gs2_val_b" value="999" />
+ <parameter name="ctle_hf_max_a" value="999" />
+ <parameter name="ctle_hf_max_b" value="999" />
+ <parameter name="ctle_hf_min_a" value="999" />
+ <parameter name="ctle_hf_min_b" value="999" />
+ <parameter name="ctle_hf_val_a" value="999" />
+ <parameter name="ctle_hf_val_ada_a" value="adaptable" />
+ <parameter name="ctle_hf_val_ada_b" value="adaptable" />
+ <parameter name="ctle_hf_val_b" value="999" />
+ <parameter name="ctle_lf_max_a" value="999" />
+ <parameter name="ctle_lf_max_b" value="999" />
+ <parameter name="ctle_lf_min_a" value="999" />
+ <parameter name="ctle_lf_min_b" value="999" />
+ <parameter name="ctle_lf_val_a" value="999" />
+ <parameter name="ctle_lf_val_ada_a" value="adaptable" />
+ <parameter name="ctle_lf_val_ada_b" value="adaptable" />
+ <parameter name="ctle_lf_val_b" value="999" />
+ <parameter name="deviceDieList" value="" />
+ <parameter name="deviceFamilyName" value="Arria 10" />
+ <parameter name="eg_addr" value="11" />
+ <parameter name="ena_hash" value="false" />
+ <parameter name="enable_alt_reconfig" value="false" />
+ <parameter name="enable_ecc" value="false" />
+ <parameter name="enable_ena" value="32" />
+ <parameter name="enable_gmii_loopback" value="false" />
+ <parameter name="enable_hd_logic" value="false" />
+ <parameter name="enable_hidden_features" value="false" />
+ <parameter name="enable_mac_flow_ctrl" value="false" />
+ <parameter name="enable_mac_vlan" value="false" />
+ <parameter name="enable_magic_detect" value="false" />
+ <parameter name="enable_ptp_1step" value="false" />
+ <parameter name="enable_sgmii" value="false" />
+ <parameter name="enable_shift16" value="true" />
+ <parameter name="enable_sup_addr" value="false" />
+ <parameter name="enable_timestamping" value="false" />
+ <parameter name="enable_use_internal_fifo" value="true" />
+ <parameter name="export_pwrdn" value="false" />
+ <parameter name="ext_stat_cnt_ena" value="false" />
+ <parameter name="ifGMII" value="MII_GMII" />
+ <parameter name="ing_addr" value="11" />
+ <parameter name="max_channels" value="1" />
+ <parameter name="mdio_clk_div" value="40" />
+ <parameter name="nd_phyip_rcfg_enable" value="false" />
+ <parameter name="nf_phyip_rcfg_enable" value="false" />
+ <parameter name="part_trait_bd" value="NIGHTFURY5" />
+ <parameter name="phy_identifier" value="0" />
+ <parameter name="phyip_en_synce_support" value="false" />
+ <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
+ <parameter name="phyip_pll_type" value="CMU" />
+ <parameter name="phyip_pma_bonding_mode" value="x1" />
+ <parameter name="rcp_load_enable" value="0" />
+ <parameter name="rf_a_a" value="999" />
+ <parameter name="rf_a_b" value="999" />
+ <parameter name="rf_b0_a" value="999" />
+ <parameter name="rf_b0_ada_a" value="adaptable" />
+ <parameter name="rf_b0_ada_b" value="adaptable" />
+ <parameter name="rf_b0_b" value="999" />
+ <parameter name="rf_b0t_a" value="999" />
+ <parameter name="rf_b0t_b" value="999" />
+ <parameter name="rf_b1_a" value="999" />
+ <parameter name="rf_b1_ada_a" value="adaptable" />
+ <parameter name="rf_b1_ada_b" value="adaptable" />
+ <parameter name="rf_b1_b" value="999" />
+ <parameter name="rf_p0_val_a" value="999" />
+ <parameter name="rf_p0_val_ada_a" value="adaptable" />
+ <parameter name="rf_p0_val_ada_b" value="adaptable" />
+ <parameter name="rf_p0_val_b" value="999" />
+ <parameter name="rf_p1_max_a" value="999" />
+ <parameter name="rf_p1_max_b" value="999" />
+ <parameter name="rf_p1_min_a" value="999" />
+ <parameter name="rf_p1_min_b" value="999" />
+ <parameter name="rf_p1_val_a" value="999" />
+ <parameter name="rf_p1_val_ada_a" value="adaptable" />
+ <parameter name="rf_p1_val_ada_b" value="adaptable" />
+ <parameter name="rf_p1_val_b" value="999" />
+ <parameter name="rf_p2_max_a" value="999" />
+ <parameter name="rf_p2_max_b" value="999" />
+ <parameter name="rf_p2_min_a" value="999" />
+ <parameter name="rf_p2_min_b" value="999" />
+ <parameter name="rf_p2_val_a" value="999" />
+ <parameter name="rf_p2_val_ada_a" value="adaptable" />
+ <parameter name="rf_p2_val_ada_b" value="adaptable" />
+ <parameter name="rf_p2_val_b" value="999" />
+ <parameter name="rf_reserved0_a" value="999" />
+ <parameter name="rf_reserved0_b" value="999" />
+ <parameter name="rf_reserved1_a" value="999" />
+ <parameter name="rf_reserved1_b" value="999" />
+ <parameter name="starting_channel_number" value="0" />
+ <parameter name="stat_cnt_ena" value="false" />
+ <parameter name="transceiver_type" value="GXB" />
+ <parameter name="tstamp_fp_width" value="4" />
+ <parameter name="useMDIO" value="false" />
+ <parameter name="use_mac_clken" value="false" />
+ <parameter name="use_misc_ports" value="true" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/tb_ip_arria10_e2sg_tse_sgmii_gx.vhd b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/tb_ip_arria10_e2sg_tse_sgmii_gx.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..60e82809ae330f6301193473965f0cea27126a23
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/tb_ip_arria10_e2sg_tse_sgmii_gx.vhd
@@ -0,0 +1,748 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Testbench for ip_arria10_e2sg_tse_sgmii_gx.
+-- Description:
+-- The tb is self checking based on that tx_pkt_cnt=rx_pkt_cnt must be true
+-- at the tb_end.
+-- Usage:
+-- > as 10
+-- > run -all
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+
+
+ENTITY tb_ip_arria10_e2sg_tse_sgmii_gx IS
+END tb_ip_arria10_e2sg_tse_sgmii_gx;
+
+
+ARCHITECTURE tb OF tb_ip_arria10_e2sg_tse_sgmii_gx IS
+
+ CONSTANT sys_clk_period : TIME := 10 ns; -- 100 MHz
+ CONSTANT eth_clk_period : TIME := 8 ns; -- 125 MHz
+ CONSTANT serial_clk_period : TIME := 800 ps; -- 1250 MHz ????
+ CONSTANT cdr_clk_period : TIME := 8000 ps; -- 125 MHz ????
+
+ CONSTANT c_tse_reg_addr_w : NATURAL := 8; -- = max 256 MAC registers
+ CONSTANT c_tse_byte_addr_w : NATURAL := c_tse_reg_addr_w + 2;
+ CONSTANT c_tse_byte_addr_pcs_offset : NATURAL := 16#200#; -- table 4.8, 4.9 in ug_ethernet.pdf
+ CONSTANT c_tse_data_w : NATURAL := c_word_w; -- = 32
+
+ CONSTANT c_tse_symbol_w : NATURAL := c_byte_w; -- = 8
+ CONSTANT c_tse_symbol_max : NATURAL := 2**c_tse_symbol_w-1; -- = 255
+ CONSTANT c_tse_symbols_per_beat : NATURAL := c_tse_data_w / c_tse_symbol_w; -- = 4
+
+ CONSTANT c_tse_pcs_reg_addr_w : NATURAL := 5; -- = max 32 PCS registers
+ CONSTANT c_tse_pcs_halfword_addr_w : NATURAL := c_tse_pcs_reg_addr_w + 1; -- table 4.17 in ug_ethernet.pdf
+ CONSTANT c_tse_pcs_byte_addr_w : NATURAL := c_tse_pcs_reg_addr_w + 2;
+ CONSTANT c_tse_pcs_data_w : NATURAL := c_halfword_w; -- = 16;
+
+ CONSTANT c_tse_empty_w : NATURAL := 2;
+ CONSTANT c_tse_tx_error_w : NATURAL := 1;
+ CONSTANT c_tse_rx_error_w : NATURAL := 6;
+ CONSTANT c_tse_error_w : NATURAL := largest(c_tse_tx_error_w, c_tse_rx_error_w);
+ CONSTANT c_tse_err_stat_w : NATURAL := 18;
+ CONSTANT c_tse_frm_type_w : NATURAL := 4;
+
+ CONSTANT c_tse_tx_fifo_depth : NATURAL := 256; -- nof words for Tx FIFO
+ CONSTANT c_tse_rx_fifo_depth : NATURAL := 256; -- nof words for Rx FIFO
+
+ CONSTANT c_tse_promis_en : BOOLEAN := FALSE;
+ --CONSTANT c_tse_promis_en : BOOLEAN := TRUE;
+
+ CONSTANT c_tx_data_type : NATURAL := 1; -- 0 = symbols, 1 = counter
+ CONSTANT c_tx_ready_latency : NATURAL := 0;
+ CONSTANT c_nof_tx_not_valid : NATURAL := 0; -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+
+ CONSTANT c_eth_dst_mac : STD_LOGIC_VECTOR(47 DOWNTO 0) := X"10FA01020300";
+ CONSTANT c_eth_src_mac : STD_LOGIC_VECTOR(47 DOWNTO 0) := X"123456789ABC"; -- = 12-34-56-78-9A-BC
+ CONSTANT c_eth_ethertype : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"10FA";
+
+ TYPE t_mm_bus IS RECORD
+ -- Master In Slave Out
+ waitreq : STD_LOGIC;
+ rddata : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+ -- Master Out Slave In
+ address : STD_LOGIC_VECTOR(c_tse_byte_addr_w-1 DOWNTO 0);
+ wrdata : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+ wr : STD_LOGIC;
+ rd : STD_LOGIC;
+ END RECORD;
+
+ PROCEDURE proc_dbg_mm_bus(SIGNAL mm_miso : IN t_mm_bus;
+ SIGNAL mm_mosi : IN t_mm_bus;
+ SIGNAL dbg_mm : OUT t_mm_bus) IS
+ BEGIN
+ dbg_mm.waitreq <= mm_miso.waitreq;
+ dbg_mm.rddata <= mm_miso.rddata;
+ dbg_mm.address <= mm_mosi.address;
+ dbg_mm.wrdata <= mm_mosi.wrdata;
+ dbg_mm.wr <= mm_mosi.wr;
+ dbg_mm.rd <= mm_mosi.rd;
+ END proc_dbg_mm_bus;
+
+ -- Wait for MM access (either read or write) finished
+ PROCEDURE proc_mm_access(SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_waitreq : IN STD_LOGIC;
+ SIGNAL mm_access : OUT STD_LOGIC) IS
+ BEGIN
+ mm_access <= '1';
+ WAIT UNTIL rising_edge(mm_clk);
+ WHILE mm_waitreq='1' LOOP
+ WAIT UNTIL rising_edge(mm_clk);
+ END LOOP;
+ mm_access <= '0';
+ END proc_mm_access;
+
+ -- Use word addressing for MAC registers according to table 4.8, 4.9
+ PROCEDURE proc_wr_mac(CONSTANT mac_addr : IN NATURAL;
+ CONSTANT mac_data : IN NATURAL;
+ SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_miso : IN t_mm_bus;
+ SIGNAL mm_mosi : OUT t_mm_bus) IS
+ BEGIN
+ mm_mosi.address <= STD_LOGIC_VECTOR(TO_UNSIGNED(mac_addr, c_tse_byte_addr_w));
+ mm_mosi.wrdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(mac_data, c_tse_data_w));
+ proc_mm_access(mm_clk, mm_miso.waitreq, mm_mosi.wr);
+ END proc_wr_mac;
+
+ PROCEDURE proc_rd_mac(CONSTANT mac_addr : IN NATURAL;
+ SIGNAL mac_data : OUT NATURAL;
+ SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_miso : IN t_mm_bus;
+ SIGNAL mm_mosi : OUT t_mm_bus) IS
+ BEGIN
+ mm_mosi.address <= STD_LOGIC_VECTOR(TO_UNSIGNED(mac_addr, c_tse_byte_addr_w));
+ proc_mm_access(mm_clk, mm_miso.waitreq, mm_mosi.rd);
+ MAC_data <= TO_INTEGER(UNSIGNED(mm_miso.rddata));
+ END proc_rd_mac;
+
+ -- Use halfword addressing for PCS register to match table 4.17
+ PROCEDURE proc_wr_pcs(CONSTANT pcs_addr : IN NATURAL;
+ CONSTANT pcs_data : IN NATURAL;
+ SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_miso : IN t_mm_bus;
+ SIGNAL mm_mosi : OUT t_mm_bus) IS
+ BEGIN
+ mm_mosi.address <= STD_LOGIC_VECTOR(TO_UNSIGNED(pcs_addr*2 + c_tse_byte_addr_pcs_offset, c_tse_byte_addr_w));
+ mm_mosi.wrdata <= (OTHERS=>'0');
+ mm_mosi.wrdata(c_tse_pcs_data_w-1 DOWNTO 0) <= STD_LOGIC_VECTOR(TO_UNSIGNED(pcs_data, c_tse_pcs_data_w));
+ proc_mm_access(mm_clk, mm_miso.waitreq, mm_mosi.wr);
+ END proc_wr_pcs;
+
+ PROCEDURE proc_rd_pcs(CONSTANT pcs_addr : IN NATURAL;
+ SIGNAL pcs_data : OUT NATURAL;
+ SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_miso : IN t_mm_bus;
+ SIGNAL mm_mosi : OUT t_mm_bus) IS
+ BEGIN
+ mm_mosi.address <= STD_LOGIC_VECTOR(TO_UNSIGNED(pcs_addr*2 + c_tse_byte_addr_pcs_offset, c_tse_byte_addr_w));
+ proc_mm_access(mm_clk, mm_miso.waitreq, mm_mosi.rd);
+ pcs_data <= TO_INTEGER(UNSIGNED(mm_miso.rddata(c_tse_pcs_data_w-1 DOWNTO 0)));
+ END proc_rd_pcs;
+
+ TYPE t_tse_stream IS RECORD
+ -- Source In or Sink Out
+ ready : STD_LOGIC;
+ -- Source Out or Sink In
+ data : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+ valid : STD_LOGIC;
+ sop : STD_LOGIC;
+ eop : STD_LOGIC;
+ empty : STD_LOGIC_VECTOR(c_tse_empty_w-1 DOWNTO 0);
+ err : STD_LOGIC_VECTOR(c_tse_error_w-1 DOWNTO 0);
+ END RECORD;
+
+ PROCEDURE proc_dbg_tse_stream_src(SIGNAL src_in : IN t_tse_stream;
+ SIGNAL src_out : IN t_tse_stream;
+ SIGNAL dbg_src : OUT t_tse_stream) IS
+ BEGIN
+ dbg_src.ready <= src_in.ready;
+ dbg_src.data <= src_out.data;
+ dbg_src.valid <= src_out.valid;
+ dbg_src.sop <= src_out.sop;
+ dbg_src.eop <= src_out.eop;
+ dbg_src.empty <= src_out.empty;
+ dbg_src.err <= src_out.err;
+ END proc_dbg_tse_stream_src;
+
+ PROCEDURE proc_dbg_tse_stream_snk(SIGNAL snk_in : IN t_tse_stream;
+ SIGNAL snk_out : IN t_tse_stream;
+ SIGNAL dbg_snk : OUT t_tse_stream) IS
+ BEGIN
+ dbg_snk.ready <= snk_out.ready;
+ dbg_snk.data <= snk_in.data;
+ dbg_snk.valid <= snk_in.valid;
+ dbg_snk.sop <= snk_in.sop;
+ dbg_snk.eop <= snk_in.eop;
+ dbg_snk.empty <= snk_in.empty;
+ dbg_snk.err <= snk_in.err;
+ END proc_dbg_tse_stream_snk;
+
+ -- Handle TX ready
+ -- Only support tx_ready_latency=0 or 1, corresponding to TX_ALMOST_FULL=3 or 4
+ -- Support for tx_ready_latency>1 requires keeping previous ready information
+ -- in a STD_LOGIC_VECTOR(tx_ready_latency-1 DOWNTO 0).
+ PROCEDURE proc_ready_latency(CONSTANT c_latency : IN NATURAL;
+ SIGNAL clk : IN STD_LOGIC;
+ SIGNAL ready : IN STD_LOGIC;
+ CONSTANT c_valid : IN STD_LOGIC;
+ CONSTANT c_sop : IN STD_LOGIC;
+ CONSTANT c_eop : IN STD_LOGIC;
+ SIGNAL out_valid : OUT STD_LOGIC;
+ SIGNAL out_sop : OUT STD_LOGIC;
+ SIGNAL out_eop : OUT STD_LOGIC) IS
+ BEGIN
+ IF c_latency=0 THEN
+ out_valid <= c_valid;
+ out_sop <= c_sop;
+ out_eop <= c_eop;
+ WAIT UNTIL rising_edge(clk);
+ WHILE ready /= '1' LOOP
+ WAIT UNTIL rising_edge(clk);
+ END LOOP;
+ END IF;
+ IF c_latency=1 THEN
+ WHILE ready /= '1' LOOP
+ out_valid <= '0';
+ out_sop <= '0';
+ out_eop <= '0';
+ WAIT UNTIL rising_edge(clk);
+ END LOOP;
+ out_valid <= c_valid;
+ out_sop <= c_sop;
+ out_eop <= c_eop;
+ WAIT UNTIL rising_edge(clk);
+ END IF;
+ END proc_ready_latency;
+
+ -- Transmit user packet
+ -- . Use word aligned payload data, so with half word inserted before the 14 byte header
+ -- . Packets can be send immediately after eachother so new sop directly after last eop
+ -- . The word rate is controlled by respecting ready from the MAC
+ PROCEDURE proc_tx_packet(CONSTANT dst_mac_addr : IN STD_LOGIC_VECTOR(c_eth_dst_mac'RANGE);
+ CONSTANT src_mac_addr : IN STD_LOGIC_VECTOR(c_eth_src_mac'RANGE);
+ CONSTANT ethertype : IN STD_LOGIC_VECTOR(c_eth_ethertype'RANGE);
+ CONSTANT data_len : IN NATURAL; -- in symbols = octets = bytes
+ SIGNAL dp_clk : IN STD_LOGIC;
+ SIGNAL dp_src_in : IN t_tse_stream;
+ SIGNAL dp_src_out : OUT t_tse_stream) IS
+ CONSTANT c_mod : NATURAL := data_len MOD c_tse_symbols_per_beat;
+ CONSTANT c_nof_data_beats : NATURAL := data_len / c_tse_symbols_per_beat + sel_a_b(c_mod, 1, 0);
+ CONSTANT c_empty : NATURAL := sel_a_b(c_mod, c_tse_symbols_per_beat - c_mod, 0);
+ VARIABLE v_sym : UNSIGNED(c_tse_symbol_w-1 DOWNTO 0) := (OTHERS=>'0');
+ VARIABLE v_num : UNSIGNED(c_tse_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ BEGIN
+ -- DST MAC
+ dp_src_out.empty <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, c_tse_empty_w));
+ dp_src_out.data <= (OTHERS=>'0');
+ dp_src_out.data(15 DOWNTO 0) <= hton(dst_mac_addr(15 DOWNTO 0)); -- send to itself
+ proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '1', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+ dp_src_out.data <= hton(dst_mac_addr(47 DOWNTO 16));
+ proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+ -- SRC MAC
+ dp_src_out.data <= hton(src_mac_addr(31 DOWNTO 0));
+ proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+ -- SRC MAC & ETHERTYPE
+ dp_src_out.data <= hton(src_mac_addr(47 DOWNTO 32)) & hton(c_eth_ethertype);
+ -- DATA
+ FOR I IN 0 TO c_nof_data_beats-1 LOOP
+ proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+ IF c_tx_data_type=0 THEN
+ -- data : X"01020304", X"05060708", X"090A0B0C", etc
+ FOR J IN c_tse_symbols_per_beat-1 DOWNTO 0 LOOP
+ v_sym := v_sym + 1;
+ dp_src_out.data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w) <= STD_LOGIC_VECTOR(v_sym);
+ END LOOP;
+ ELSE
+ -- data : X"00000001", X"00000002", X"00000003", etc
+ v_num := v_num + 1;
+ dp_src_out.data <= STD_LOGIC_VECTOR(v_num);
+ END IF;
+ -- tb : pull valid low for some time during the middle of the payload
+ IF c_nof_tx_not_valid > 0 AND I=c_nof_data_beats/2 THEN
+ dp_src_out.valid <= '0';
+ FOR I IN 0 TO c_nof_tx_not_valid LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+ dp_src_out.valid <= '1';
+ END IF;
+ END LOOP;
+ IF c_empty > 0 THEN
+ dp_src_out.empty <= STD_LOGIC_VECTOR(TO_UNSIGNED(c_empty, c_tse_empty_w));
+ FOR J IN c_empty-1 DOWNTO 0 LOOP
+ dp_src_out.data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w) <= (OTHERS=>'0');
+ END LOOP;
+ END IF;
+ proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '1', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+ dp_src_out.data <= (OTHERS=>'0');
+ dp_src_out.valid <= '0';
+ dp_src_out.eop <= '0';
+ dp_src_out.empty <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, c_tse_empty_w));
+ END proc_tx_packet;
+
+ PROCEDURE proc_valid_sop(SIGNAL clk : IN STD_LOGIC;
+ SIGNAL in_valid : IN STD_LOGIC;
+ SIGNAL in_sop : IN STD_LOGIC) IS
+ BEGIN
+ WAIT UNTIL rising_edge(clk);
+ WHILE in_valid /= '1' AND in_sop /= '1' LOOP
+ WAIT UNTIL rising_edge(clk);
+ END LOOP;
+ END proc_valid_sop;
+
+ PROCEDURE proc_valid(SIGNAL clk : IN STD_LOGIC;
+ SIGNAL in_valid : IN STD_LOGIC) IS
+ BEGIN
+ WAIT UNTIL rising_edge(clk);
+ WHILE in_valid /= '1' LOOP
+ WAIT UNTIL rising_edge(clk);
+ END LOOP;
+ END proc_valid;
+
+ -- Receive packet
+ -- . Use word aligned payload data, so with half word inserted before the 14 byte header
+ -- . Packets can be always be received, assume the user application is always ready
+ -- . The CRC32 is also passed on to the user at eop.
+ -- . Note that when empty/=0 then the CRC32 is not word aligned, so therefore use prev_data to be able
+ -- to handle part of last data word in case empty/=0 at eop
+ PROCEDURE proc_rx_packet(CONSTANT dst_mac_addr : IN STD_LOGIC_VECTOR(c_eth_dst_mac'RANGE);
+ CONSTANT src_mac_addr : IN STD_LOGIC_VECTOR(c_eth_src_mac'RANGE);
+ CONSTANT ethertype : IN STD_LOGIC_VECTOR(c_eth_ethertype'RANGE);
+ SIGNAL dp_clk : IN STD_LOGIC;
+ SIGNAL dp_snk_in : IN t_tse_stream;
+ SIGNAL dp_snk_out : OUT t_tse_stream) IS
+ VARIABLE v_sym : UNSIGNED(c_tse_symbol_w-1 DOWNTO 0) := (OTHERS=>'0');
+ VARIABLE v_num : UNSIGNED(c_tse_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ VARIABLE v_empty : NATURAL;
+ VARIABLE v_first : BOOLEAN := TRUE;
+ VARIABLE v_data : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+ VARIABLE v_prev_data : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+ BEGIN
+ -- Keep ff_rx_snk_out.ready='1' all the time
+ dp_snk_out.ready <= '1';
+ -- Verify DST MAC
+ proc_valid_sop(dp_clk, dp_snk_in.valid, dp_snk_in.sop);
+ ASSERT dp_snk_in.data(31 DOWNTO 16) = X"0000" REPORT "RX: Alignment half word not zero" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(15 DOWNTO 0) = hton(dst_mac_addr(15 DOWNTO 0)) REPORT "RX: Wrong dst_mac_addr(15 DOWNTO 0)" SEVERITY ERROR;
+ proc_valid(dp_clk, dp_snk_in.valid);
+ ASSERT dp_snk_in.data(31 DOWNTO 0) = hton(dst_mac_addr(47 DOWNTO 16)) REPORT "RX: Wrong dst_mac_addr(47 DOWNTO 16)" SEVERITY ERROR;
+ -- Verify SRC MAC
+ proc_valid(dp_clk, dp_snk_in.valid);
+ ASSERT dp_snk_in.data(31 DOWNTO 0) = hton(src_mac_addr(31 DOWNTO 0)) REPORT "RX: Wrong src_mac_addr(31 DOWNTO 0)" SEVERITY ERROR;
+ -- Verify SRC MAC & ETHERTYPE
+ proc_valid(dp_clk, dp_snk_in.valid);
+ ASSERT dp_snk_in.data(31 DOWNTO 16) = hton(src_mac_addr(47 DOWNTO 32)) REPORT "RX: Wrong src_mac_addr(47 DOWNTO 32)" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(15 DOWNTO 0) = hton(c_eth_ethertype) REPORT "RX: Wrong ethertype" SEVERITY ERROR;
+ -- Verify DATA
+ v_first := TRUE;
+ proc_valid(dp_clk, dp_snk_in.valid);
+ WHILE dp_snk_in.eop /= '1' LOOP
+ v_prev_data := v_data;
+ v_data := dp_snk_in.data;
+ IF v_first = FALSE THEN
+ IF c_tx_data_type=0 THEN
+ -- data : X"01020304", X"05060708", X"090A0B0C", etc
+ FOR J IN c_tse_symbols_per_beat-1 DOWNTO 0 LOOP
+ v_sym := v_sym + 1;
+ ASSERT UNSIGNED(v_prev_data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w)) = v_sym REPORT "RX: Wrong data symbol" SEVERITY ERROR;
+ END LOOP;
+ ELSE
+ -- data : X"00000001", X"00000002", X"00000003", etc
+ v_num := v_num + 1;
+ ASSERT UNSIGNED(v_prev_data) = v_num REPORT "RX: Wrong data word" SEVERITY ERROR;
+ END IF;
+ END IF;
+ v_first := FALSE;
+ proc_valid(dp_clk, dp_snk_in.valid);
+ END LOOP;
+ -- Verify last DATA and CRC32 if empty /=0 else the last word is only the CRC32
+ v_prev_data := v_data;
+ v_data := dp_snk_in.data;
+ v_empty := TO_INTEGER(UNSIGNED(dp_snk_in.empty));
+ IF v_empty > 0 THEN
+ FOR J IN v_empty-1 DOWNTO 0 LOOP
+ v_prev_data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w) := (OTHERS=>'0');
+ END LOOP;
+ IF c_tx_data_type=0 THEN
+ -- data : X"01020304", X"05060708", X"090A0B0C", etc
+ FOR J IN c_tse_symbols_per_beat-1 DOWNTO v_empty LOOP -- ignore CRC32 symbols in last data word
+ v_sym := v_sym + 1;
+ ASSERT UNSIGNED(v_prev_data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w)) = v_sym REPORT "RX: Wrong empty data symbol" SEVERITY ERROR;
+ END LOOP;
+ ELSE
+ -- data : X"00000001", X"00000002", X"00000003", etc
+ v_num := v_num + 1;
+ FOR J IN v_empty-1 DOWNTO 0 LOOP
+ v_num((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w) := (OTHERS=>'0'); -- force CRC32 symbols in last data word to 0
+ END LOOP;
+ ASSERT UNSIGNED(v_prev_data) = v_num REPORT "RX: Wrong empty data word" SEVERITY ERROR;
+ END IF;
+ ELSE
+ -- No verify on CRC32 word
+ END IF;
+ END proc_rx_packet;
+
+
+ -- Clocks and reset
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL sys_clk : STD_LOGIC := '0';
+ SIGNAL dp_clk : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC;
+
+ -- TSE MAC control interface
+ SIGNAL mm_init : STD_LOGIC := '1';
+ SIGNAL mm_miso : t_mm_bus; -- master in slave out
+ SIGNAL mm_mosi : t_mm_bus; -- master out slave in
+
+ SIGNAL pcs_rddata : NATURAL; -- [c_tse_pcs_data_w-1:0]
+
+ SIGNAL tse_led_an : STD_LOGIC;
+ SIGNAL tse_led_link : STD_LOGIC;
+
+ -- TSE MAC transmit interface
+ -- . Avalon ST source
+ SIGNAL ff_tx_src_in : t_tse_stream;
+ SIGNAL ff_tx_src_out : t_tse_stream;
+ -- . MAC specific
+ SIGNAL ff_tx_crc_fwd : STD_LOGIC;
+ SIGNAL ff_tx_septy : STD_LOGIC;
+ SIGNAL ff_tx_a_full : STD_LOGIC;
+ SIGNAL ff_tx_a_empty : STD_LOGIC;
+ SIGNAL ff_tx_uflow : STD_LOGIC;
+
+ -- TSE MAC receive interface
+ -- . Avalon ST sink
+ SIGNAL ff_rx_snk_in : t_tse_stream;
+ SIGNAL ff_rx_snk_out : t_tse_stream;
+ -- . MAC specific
+ SIGNAL ff_rx_ethertype: STD_LOGIC_VECTOR(c_tse_err_stat_w-1 DOWNTO 0);
+ SIGNAL ff_rx_frm_type : STD_LOGIC_VECTOR(c_tse_frm_type_w-1 DOWNTO 0);
+ SIGNAL ff_rx_dsav : STD_LOGIC;
+ SIGNAL ff_rx_a_full : STD_LOGIC;
+ SIGNAL ff_rx_a_empty : STD_LOGIC;
+
+ -- TSE PHY interface
+ SIGNAL eth_txp : STD_LOGIC;
+ SIGNAL eth_rxp : STD_LOGIC;
+
+ -- TSE PHY GX
+ SIGNAL tx_serial_clk : STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL rx_cdr_refclk : STD_LOGIC := '0';
+
+ -- Verification
+ SIGNAL tx_pkt_cnt : NATURAL := 0;
+ SIGNAL rx_pkt_cnt : NATURAL := 0;
+
+ -- Debug signals to combine valid in and out of records
+ SIGNAL dbg_mm : t_mm_bus;
+ SIGNAL dbg_ff_tx : t_tse_stream;
+ SIGNAL dbg_ff_rx : t_tse_stream;
+
+BEGIN
+
+ eth_clk <= NOT eth_clk AFTER eth_clk_period/2; -- TSE reference clock
+ sys_clk <= NOT sys_clk AFTER sys_clk_period/2; -- System clock
+
+ mm_clk <= sys_clk;
+ dp_clk <= sys_clk;
+
+ -- Debug signals to combine valid in and out of records
+ proc_dbg_mm_bus( mm_miso, mm_mosi, dbg_mm);
+ proc_dbg_tse_stream_src(ff_tx_src_in, ff_tx_src_out, dbg_ff_tx);
+ proc_dbg_tse_stream_snk(ff_rx_snk_in, ff_rx_snk_out, dbg_ff_rx);
+
+ -- run 1 us
+ p_mm_stimuli : PROCESS
+ BEGIN
+ mm_init <= '1';
+ mm_mosi.wr <= '0';
+ mm_mosi.rd <= '0';
+
+ -- reset release
+ mm_rst <= '1';
+ FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
+ mm_rst <= '0';
+ FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
+
+ -- PSC control
+ proc_rd_pcs(16#22#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- REV --> 0x0901
+ proc_wr_pcs(16#28#, 16#0008#, mm_clk, mm_miso, mm_mosi); -- IF_MODE <-- Force 1GbE, no autonegatiation
+ proc_rd_pcs(16#00#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- CONTROL --> 0x1140
+ proc_rd_pcs(16#02#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- STATUS --> 0x000D
+ proc_wr_pcs(16#00#, 16#0140#, mm_clk, mm_miso, mm_mosi); -- CONTROL <-- Auto negotiate disable
+
+ -- MAC control
+ proc_rd_mac(16#000#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- REV --> CUST_VERSION & 0x0901
+ IF c_tse_promis_en=FALSE THEN
+ proc_wr_mac(16#008#, 16#0100004B#, mm_clk, mm_miso, mm_mosi);
+ ELSE
+ proc_wr_mac(16#008#, 16#0100005B#, mm_clk, mm_miso, mm_mosi);
+ END IF;
+ -- COMMAND_CONFIG <--
+ -- Only the bits relevant to UniBoard are explained here, others are 0
+ -- [ 0] = TX_ENA = 1, enable tx datapath
+ -- [ 1] = RX_ENA = 1, enable rx datapath
+ -- [ 2] = XON_GEN = 0
+ -- [ 3] = ETH_SPEED = 1, enable 1GbE operation
+ -- [ 4] = PROMIS_EN = 0, when 1 then receive all frames
+ -- [ 5] = PAD_EN = 0, when 1 enable receive padding removal (requires ethertype=payload length)
+ -- [ 6] = CRC_FWD = 1, enable receive CRC forward
+ -- [ 7] = PAUSE_FWD = 0
+ -- [ 8] = PAUSE_IGNORE = 0
+ -- [ 9] = TX_ADDR_INS = 0, when 1 then MAX overwrites tx SRC MAC with mac_0,1 or one of the supplemental mac
+ -- [ 10] = HD_ENA = 0
+ -- [ 11] = EXCESS_COL = 0
+ -- [ 12] = LATE_COL = 0
+ -- [ 13] = SW_RESET = 0, when 1 MAC disables tx and rx, clear statistics and flushes receive FIFO
+ -- [ 14] = MHAS_SEL = 0, select multicast address resolutions hash-code mode
+ -- [ 15] = LOOP_ENA = 0
+ -- [18-16] = TX_ADDR_SEL[2:0] = 000, TX_ADDR_INS insert mac_0,1 or one of the supplemental mac
+ -- [ 19] = MAGIC_EN = 0
+ -- [ 20] = SLEEP = 0
+ -- [ 21] = WAKEUP = 0
+ -- [ 22] = XOFF_GEN = 0
+ -- [ 23] = CNT_FRM_ENA = 0
+ -- [ 24] = NO_LGTH_CHECK = 1, when 0 then check payload length of received frames (requires ethertype=payload length)
+ -- [ 25] = ENA_10 = 0
+ -- [ 26] = RX_ERR_DISC = 0, when 1 then discard erroneous frames (requires store and forward mode, so rx_section_full=0)
+ -- when 0 then pass on with rx_err[0]=1
+ -- [ 27] = DISABLE_RD_TIMEOUT = 0
+ -- [30-28] = RSVD = 000
+ -- [ 31] = CNT_RESET = 0, when 1 clear statistics
+ proc_wr_mac(16#00C#, 16#56789ABC#, mm_clk, mm_miso, mm_mosi); -- MAC_0
+ proc_wr_mac(16#010#, 16#00001234#, mm_clk, mm_miso, mm_mosi); -- MAC_1 <-- SRC_MAC = 12-34-56-78-9A-BC
+ proc_wr_mac(16#05C#, 16#0000000C#, mm_clk, mm_miso, mm_mosi); -- TX_IPG_LENGTH <-- interpacket gap = 12
+ proc_wr_mac(16#014#, 16#000005EE#, mm_clk, mm_miso, mm_mosi); -- FRM_LENGTH <-- receive max frame length = 1518
+
+ -- FIFO legenda:
+ -- . Tx section full = There is enough data in the FIFO to start reading it, when 0 then store and forward.
+ -- . Rx section full = There is enough data in the FIFO to start reading it, when 0 then store and forward.
+ -- . Tx section empty = There is not much empty space anymore in the FIFO, warn user via ff_tx_septy
+ -- . Rx section empty = There is not much empty space anymore in the FIFO, inform remote device via XOFF flow control
+ -- . Tx almost full = Assert ff_tx_a_full and deassert ff_tx_rdy. Furthermore TX_ALMOST_FULL = c_tx_ready_latency+3,
+ -- so choose 3 for zero tx ready latency
+ -- . Rx almost full = Assert ff_rx_a_full and if the user is not ready ff_rx_rdy then:
+ -- --> break off the reception with an error to avoid FIFO overflow
+ -- . Tx almost empty = Assert ff_tx_a_empty and if the FIFO does not contain a eop yet then:
+ -- --> break off the transmission with an error to avoid FIFO underflow
+ -- . Rx almost empty = Assert ff_rx_a_empty
+ -- Typical FIFO values:
+ -- . TX_SECTION_FULL = 16 > 8 = TX_ALMOST_EMPTY
+ -- . RX_SECTION_FULL = 16 > 8 = RX_ALMOST_EMPTY
+ -- . TX_SECTION_EMPTY = D-16 < D-3 = Tx FIFO depth - TX_ALMOST_FULL
+ -- . RX_SECTION_EMPTY = D-16 < D-8 = Rx FIFO depth - RX_ALMOST_FULL
+ -- . c_tse_tx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Tx user respects ff_tx_rdy, to store a complete
+ -- ETH packet would require 1518 byte, so 2 M9K = 2k * 8b
+ -- . c_tse_rx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Rx user ff_rx_rdy is sufficiently active
+ proc_wr_mac(16#01C#, c_tse_rx_fifo_depth-16, mm_clk, mm_miso, mm_mosi); -- RX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_wr_mac(16#020#, 16, mm_clk, mm_miso, mm_mosi); -- RX_SECTION_FULL <-- default 16
+ proc_wr_mac(16#024#, c_tse_tx_fifo_depth-16, mm_clk, mm_miso, mm_mosi); -- TX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_wr_mac(16#028#, 16, mm_clk, mm_miso, mm_mosi); -- TX_SECTION_FULL <-- default 16, >~ 8 otherwise no tx
+ proc_wr_mac(16#02C#, 8, mm_clk, mm_miso, mm_mosi); -- RX_ALMOST_EMPTY <-- default 8
+ proc_wr_mac(16#030#, 8, mm_clk, mm_miso, mm_mosi); -- RX_ALMOST_FULL <-- default 8
+ proc_wr_mac(16#034#, 8, mm_clk, mm_miso, mm_mosi); -- TX_ALMOST_EMPTY <-- default 8
+ proc_wr_mac(16#038#, c_tx_ready_latency+3, mm_clk, mm_miso, mm_mosi); -- TX_ALMOST_FULL <-- default 3
+
+ proc_rd_mac(16#0E8#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- TX_CMD_STAT --> 0x00040000 : [18]=1 TX_SHIFT16, [17]=0 OMIT_CRC
+ proc_rd_mac(16#0EC#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- RX_CMD_STAT --> 0x02000000 : [25]=1 RX_SHIFT16
+
+ WAIT UNTIL rising_edge(mm_clk);
+ mm_init <= '0';
+
+ WAIT;
+ END PROCESS;
+
+ p_tx_frame : PROCESS
+ BEGIN
+ -- . Avalon ST
+ ff_tx_src_out.data <= (OTHERS=>'0');
+ ff_tx_src_out.valid <= '0';
+ ff_tx_src_out.sop <= '0';
+ ff_tx_src_out.eop <= '0';
+ ff_tx_src_out.empty <= (OTHERS=>'0');
+ ff_tx_src_out.err <= (OTHERS=>'0');
+ -- . MAC specific
+ ff_tx_crc_fwd <= '0';
+
+ WHILE mm_init/='0' LOOP
+ WAIT UNTIL rising_edge(dp_clk);
+ END LOOP;
+ WHILE tse_led_link/='1' LOOP
+ WAIT UNTIL rising_edge(dp_clk);
+ END LOOP;
+ FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, "0000000000010000", 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+ proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1499, dp_clk, ff_tx_src_in, ff_tx_src_out); -- verify st empty
+ proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+
+ FOR I IN 0 TO 1500 * 4 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+
+ p_rx_frame : PROCESS
+ BEGIN
+ -- . Avalon ST
+ ff_rx_snk_out.ready <= '0';
+
+ WHILE mm_init/='0' LOOP
+ WAIT UNTIL rising_edge(dp_clk);
+ END LOOP;
+
+ -- Receive forever
+ WHILE TRUE LOOP
+ proc_rx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, dp_clk, ff_rx_snk_in, ff_rx_snk_out);
+ END LOOP;
+
+ WAIT;
+ END PROCESS;
+
+ dut : ENTITY work.ip_arria10_e2sg_tse_sgmii_gx
+ -- The ip_arria10_e2sg_tse_sgmii_gx needs to be regenerated if its parameters are changed.
+ -- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
+ -- . ENABLE_SUP_ADDR = 0 : An extra MAC addresses can e.g. be used as service MAC for tests
+ -- . ENA_HASH = 0 : A multi cast hash table can be used to address all nodes at once
+ -- . STAT_CNT_ENA = 0 : PHY statistics counts are useful for monitoring, but not realy needed
+ -- . EG_FIFO = 256 : Tx FIFO depth in nof 32 bit words (256 --> 1 M9K)
+ -- . ING_FIFO = 256 : Rx FIFO depth in nof 32 bit words (256 --> 1 M9K)
+ PORT MAP (
+ -- MAC transmit interface
+ -- . Avalon ST
+ ff_tx_clk => dp_clk, -- : in std_logic := '0'; -- transmit_clock_connection.clk
+ ff_tx_rdy => ff_tx_src_in.ready, -- : out std_logic; -- .ready
+ ff_tx_data => ff_tx_src_out.data, -- : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
+ ff_tx_wren => ff_tx_src_out.valid, -- : in std_logic := '0'; -- .valid
+ ff_tx_sop => ff_tx_src_out.sop, -- : in std_logic := '0'; -- .startofpacket
+ ff_tx_eop => ff_tx_src_out.eop, -- : in std_logic := '0'; -- .endofpacket
+ ff_tx_mod => ff_tx_src_out.empty, -- : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
+ ff_tx_err => ff_tx_src_out.err(0), -- : in std_logic := '0'; -- .error
+ -- . MAC specific
+ ff_tx_crc_fwd => ff_tx_crc_fwd, -- : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd -- when '0' MAC inserts CRC32 after eop
+ ff_tx_septy => ff_tx_septy, -- : out std_logic; -- .ff_tx_septy -- when '0' then tx FIFO goes above section-empty threshold
+ ff_tx_a_full => ff_tx_a_full, -- : out std_logic; -- .ff_tx_a_full -- when '1' then tx FIFO goes above almost-full threshold
+ ff_tx_a_empty => ff_tx_a_empty, -- : out std_logic; -- .ff_tx_a_empty -- when '1' then tx FIFO goes below almost-empty threshold
+ tx_ff_uflow => ff_tx_uflow, -- : out std_logic; -- .tx_ff_uflow -- when '1' then tx FIFO underflow
+ -- MAC receive interface
+ -- . Avalon STs
+ ff_rx_clk => dp_clk, -- : in std_logic := '0'; -- receive_clock_connection.clk
+ ff_rx_rdy => ff_rx_snk_out.ready, -- : in std_logic := '0'; -- .ready
+ ff_rx_data => ff_rx_snk_in.data, -- : out std_logic_vector(31 downto 0); -- receive.data
+ ff_rx_dval => ff_rx_snk_in.valid, -- : out std_logic; -- .valid
+ ff_rx_sop => ff_rx_snk_in.sop, -- : out std_logic; -- .startofpacket
+ ff_rx_eop => ff_rx_snk_in.eop, -- : out std_logic; -- .endofpacket
+ ff_rx_mod => ff_rx_snk_in.empty, -- : out std_logic_vector(1 downto 0); -- .empty
+ rx_err => ff_rx_snk_in.err, -- : out std_logic_vector(5 downto 0); -- .error
+ -- [5] collision error (can only occur in half duplex mode)
+ -- [4] PHY error on GMII
+ -- [3] receive frame truncated due to FIFO overflow
+ -- [2] CRC-32 error
+ -- [1] invalid length
+ -- [0] = OR of [1:5]
+ -- . MAC specific
+ rx_err_stat => ff_rx_ethertype, -- : out std_logic_vector(17 downto 0); -- .rx_err_stat -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
+ rx_frm_type => ff_rx_frm_type, -- : out std_logic_vector(3 downto 0); -- .rx_frm_type -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
+ ff_rx_dsav => ff_rx_dsav, -- : out std_logic; -- .ff_rx_dsav -- rx frame available, but not necessarily a complete frame
+ ff_rx_a_full => ff_rx_a_full, -- : out std_logic; -- .ff_rx_a_full -- when '1' then rx FIFO goes above almost-full threshold
+ ff_rx_a_empty => ff_rx_a_empty, -- : out std_logic; -- .ff_rx_a_empty -- when '1' sthen rx FIFO goes below almost-empty threshold
+ -- Reset
+ reset => mm_rst, -- : in std_logic := '0'; -- reset_connection.reset -- asynchronous reset (choose synchronous to mm_clk)
+ -- MM control interface
+ clk => mm_clk, -- : in std_logic := '0'; -- control_port_clock_connection.clk
+ reg_addr => mm_mosi.address(c_tse_byte_addr_w-1 DOWNTO 2), -- : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
+ reg_data_out => mm_miso.rddata, -- : out std_logic_vector(31 downto 0); -- control_port.readdata
+ reg_rd => mm_mosi.rd, -- : in std_logic := '0'; -- .read
+ reg_data_in => mm_mosi.wrdata, -- : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reg_wr => mm_mosi.wr, -- : in std_logic := '0'; -- .write
+ reg_busy => mm_miso.waitreq, -- : out std_logic; -- .waitrequest
+ -- Status LEDs
+ led_an => tse_led_an, -- : out std_logic; -- .an -- '1' = autonegation completed
+ led_link => tse_led_link, -- : out std_logic; -- .link -- '1' = successful link synchronisation
+ led_disp_err => OPEN, -- : out std_logic; -- .disp_err -- TBI character error
+ led_char_err => OPEN, -- : out std_logic; -- .char_err -- TBI disparity errorreceived
+ led_crs => OPEN, -- : out std_logic; -- status_led_connection.crs
+ led_col => OPEN, -- : out std_logic; -- .col
+ -- Serial 1.25 Gbps
+ rx_recovclkout => OPEN, -- : out std_logic; -- serdes_control_connection.export
+ ref_clk => eth_clk, -- : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
+ txp => eth_txp, -- : out std_logic -- .txp_0
+ rxp => eth_rxp, -- : in std_logic := '0'; -- serial_connection.rxp_0
+
+ tx_serial_clk => tx_serial_clk, -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk.clk
+ rx_cdr_refclk => rx_cdr_refclk, -- : in std_logic := '0'; -- rx_cdr_refclk.clk
+ tx_analogreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_digitalreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ rx_analogreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_digitalreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ tx_cal_busy => OPEN, -- : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
+ rx_cal_busy => OPEN, -- : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_set_locktodata => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktodata.rx_set_locktodata
+ rx_set_locktoref => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktoref.rx_set_locktoref
+ rx_is_lockedtoref => OPEN, -- : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtodata => OPEN -- : out std_logic_vector(0 downto 0) -- rx_is_lockedtodata.rx_is_lockedtodata
+ );
+
+ -- To be corrected
+ tx_serial_clk(0) <= NOT tx_serial_clk(0) AFTER serial_clk_period/2; -- ????
+ rx_cdr_refclk <= NOT rx_cdr_refclk AFTER cdr_clk_period/2; -- ????
+
+ -- Loopback
+ eth_rxp <= eth_txp;
+
+ -- Verification
+ tx_pkt_cnt <= tx_pkt_cnt + 1 WHEN ff_tx_src_out.sop='1' AND rising_edge(dp_clk);
+ rx_pkt_cnt <= rx_pkt_cnt + 1 WHEN ff_rx_snk_in.eop='1' AND rising_edge(dp_clk);
+
+ p_tb_end : PROCESS
+ BEGIN
+ WAIT UNTIL tb_end='1';
+
+ -- Verify that all transmitted packets have been received
+ IF tx_pkt_cnt=0 THEN
+ REPORT "No packets were transmitted." SEVERITY ERROR;
+ ELSIF rx_pkt_cnt=0 THEN
+ REPORT "No packets were received." SEVERITY ERROR;
+ ELSIF tx_pkt_cnt/=rx_pkt_cnt THEN
+ REPORT "Not all transmitted packets were received." SEVERITY ERROR;
+ END IF;
+
+ -- Stop the simulation
+ ASSERT FALSE REPORT "Simulation finished." SEVERITY FAILURE;
+ WAIT;
+ END PROCESS;
+
+END tb;
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/README.patch b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/README.patch
new file mode 100644
index 0000000000000000000000000000000000000000..2fdf7a6eb7602fa32297fdc9b794576feafeefe8
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/README.patch
@@ -0,0 +1,3 @@
+The patch is generated with:
+
+diff -cB ip_arria10_e3sge3_tse_sgmii_lvds/altera_lvds_core20_151/synth/sdc_util.tcl generated/altera_lvds_core20_151/synth/sdc_util.tcl > sdc_util.sdc.patch
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/README.txt b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/README.txt
new file mode 100755
index 0000000000000000000000000000000000000000..efe749e3a03ff7e95c29fd5bfc6bb62ae55040a2
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/README.txt
@@ -0,0 +1,4 @@
+README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
+
+See README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
+
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ec4f247a9caba7327656d1b02ae2247645e05a57
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/compile_ip.tcl
@@ -0,0 +1,34 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
+
+ vcom "$IP_DIR/ip_arria10_e2sg_tse_sgmii_lvds.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..f38591623c5f31378b6d5141b049539451165fec
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/hdllib.cfg
@@ -0,0 +1,27 @@
+hdl_lib_name = ip_arria10_e2sg_tse_sgmii_lvds
+hdl_library_clause_name = ip_arria10_e2sg_tse_sgmii_lvds_altera_eth_tse_180
+hdl_lib_uses_synth = common
+hdl_lib_uses_sim = ip_arria10_e2sg_altera_eth_tse_180
+
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+ tb_ip_arria10_e2sg_tse_sgmii_lvds.vhd
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/ip_arria10_e2sg_tse_sgmii_lvds.qip
+
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_tse_sgmii_lvds.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/ip_arria10_e2sg_tse_sgmii_lvds.qsys b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/ip_arria10_e2sg_tse_sgmii_lvds.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..16679fd6d186599d6cc1ee3f4c956c51b7154782
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/ip_arria10_e2sg_tse_sgmii_lvds.qsys
@@ -0,0 +1,325 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_tse_sgmii_lvds">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element eth_tse_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>control_port</key>
+ <value>
+ <connectionPointName>control_port</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='control_port' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>10</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="control_port"
+ internal="eth_tse_0.control_port"
+ type="avalon"
+ dir="end">
+ <port name="reg_addr" internal="reg_addr" />
+ <port name="reg_busy" internal="reg_busy" />
+ <port name="reg_data_in" internal="reg_data_in" />
+ <port name="reg_data_out" internal="reg_data_out" />
+ <port name="reg_rd" internal="reg_rd" />
+ <port name="reg_wr" internal="reg_wr" />
+ </interface>
+ <interface
+ name="control_port_clock_connection"
+ internal="eth_tse_0.control_port_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="clk" internal="clk" />
+ </interface>
+ <interface name="mac_gmii_connection" internal="eth_tse_0.mac_gmii_connection" />
+ <interface name="mac_mii_connection" internal="eth_tse_0.mac_mii_connection" />
+ <interface
+ name="mac_misc_connection"
+ internal="eth_tse_0.mac_misc_connection"
+ type="conduit"
+ dir="end">
+ <port name="ff_rx_a_empty" internal="ff_rx_a_empty" />
+ <port name="ff_rx_a_full" internal="ff_rx_a_full" />
+ <port name="ff_rx_dsav" internal="ff_rx_dsav" />
+ <port name="ff_tx_a_empty" internal="ff_tx_a_empty" />
+ <port name="ff_tx_a_full" internal="ff_tx_a_full" />
+ <port name="ff_tx_crc_fwd" internal="ff_tx_crc_fwd" />
+ <port name="ff_tx_septy" internal="ff_tx_septy" />
+ <port name="rx_err_stat" internal="rx_err_stat" />
+ <port name="rx_frm_type" internal="rx_frm_type" />
+ <port name="tx_ff_uflow" internal="tx_ff_uflow" />
+ </interface>
+ <interface
+ name="mac_status_connection"
+ internal="eth_tse_0.mac_status_connection" />
+ <interface
+ name="pcs_mac_rx_clock_connection"
+ internal="eth_tse_0.pcs_mac_rx_clock_connection" />
+ <interface
+ name="pcs_mac_tx_clock_connection"
+ internal="eth_tse_0.pcs_mac_tx_clock_connection" />
+ <interface
+ name="pcs_ref_clk_clock_connection"
+ internal="eth_tse_0.pcs_ref_clk_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="ref_clk" internal="ref_clk" />
+ </interface>
+ <interface
+ name="receive"
+ internal="eth_tse_0.receive"
+ type="avalon_streaming"
+ dir="start">
+ <port name="ff_rx_data" internal="ff_rx_data" />
+ <port name="ff_rx_dval" internal="ff_rx_dval" />
+ <port name="ff_rx_eop" internal="ff_rx_eop" />
+ <port name="ff_rx_mod" internal="ff_rx_mod" />
+ <port name="ff_rx_rdy" internal="ff_rx_rdy" />
+ <port name="ff_rx_sop" internal="ff_rx_sop" />
+ <port name="rx_err" internal="rx_err" />
+ </interface>
+ <interface
+ name="receive_clock_connection"
+ internal="eth_tse_0.receive_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="ff_rx_clk" internal="ff_rx_clk" />
+ </interface>
+ <interface
+ name="reset_connection"
+ internal="eth_tse_0.reset_connection"
+ type="reset"
+ dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="serdes_control_connection"
+ internal="eth_tse_0.serdes_control_connection"
+ type="conduit"
+ dir="end">
+ <port name="rx_recovclkout" internal="rx_recovclkout" />
+ </interface>
+ <interface
+ name="serial_connection"
+ internal="eth_tse_0.serial_connection"
+ type="conduit"
+ dir="end">
+ <port name="rxp" internal="rxp" />
+ <port name="txp" internal="txp" />
+ </interface>
+ <interface
+ name="status_led_connection"
+ internal="eth_tse_0.status_led_connection"
+ type="conduit"
+ dir="end">
+ <port name="led_an" internal="led_an" />
+ <port name="led_char_err" internal="led_char_err" />
+ <port name="led_col" internal="led_col" />
+ <port name="led_crs" internal="led_crs" />
+ <port name="led_disp_err" internal="led_disp_err" />
+ <port name="led_link" internal="led_link" />
+ <port name="led_panel_link" internal="led_panel_link" />
+ </interface>
+ <interface name="tbi_connection" internal="eth_tse_0.tbi_connection" />
+ <interface
+ name="transmit"
+ internal="eth_tse_0.transmit"
+ type="avalon_streaming"
+ dir="end">
+ <port name="ff_tx_data" internal="ff_tx_data" />
+ <port name="ff_tx_eop" internal="ff_tx_eop" />
+ <port name="ff_tx_err" internal="ff_tx_err" />
+ <port name="ff_tx_mod" internal="ff_tx_mod" />
+ <port name="ff_tx_rdy" internal="ff_tx_rdy" />
+ <port name="ff_tx_sop" internal="ff_tx_sop" />
+ <port name="ff_tx_wren" internal="ff_tx_wren" />
+ </interface>
+ <interface
+ name="transmit_clock_connection"
+ internal="eth_tse_0.transmit_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="ff_tx_clk" internal="ff_tx_clk" />
+ </interface>
+ <module
+ name="eth_tse_0"
+ kind="altera_eth_tse"
+ version="19.4.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="AUTO_DEVICE" value="10AX115U3F45E2SG" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="ND_XCVR_RCFG_JTAG_ENABLE" value="0" />
+ <parameter name="ND_XCVR_SET_CAPABILITY_REG_ENABLE" value="0" />
+ <parameter name="ND_XCVR_SET_CSR_SOFT_LOGIC_ENABLE" value="0" />
+ <parameter name="ND_XCVR_SET_USER_IDENTIFIER" value="0" />
+ <parameter name="XCVR_RCFG_JTAG_ENABLE" value="0" />
+ <parameter name="XCVR_SET_CAPABILITY_REG_ENABLE" value="0" />
+ <parameter name="XCVR_SET_CSR_SOFT_LOGIC_ENABLE" value="0" />
+ <parameter name="XCVR_SET_PRBS_SOFT_LOGIC_ENABLE" value="0" />
+ <parameter name="XCVR_SET_USER_IDENTIFIER" value="0" />
+ <parameter name="adpt_multi_enable" value="1" />
+ <parameter name="adpt_recipe_cnt" value="1" />
+ <parameter name="adpt_recipe_data0" value="" />
+ <parameter name="adpt_recipe_data1" value="" />
+ <parameter name="adpt_recipe_data2" value="" />
+ <parameter name="adpt_recipe_data3" value="" />
+ <parameter name="adpt_recipe_data4" value="" />
+ <parameter name="adpt_recipe_data5" value="" />
+ <parameter name="adpt_recipe_data6" value="" />
+ <parameter name="adpt_recipe_data7" value="" />
+ <parameter name="adpt_recipe_select" value="0" />
+ <parameter name="cal_recipe_sel" value="NRZ_28Gbps_VSR" />
+ <parameter name="core_variation" value="MAC_PCS" />
+ <parameter name="ctle_gs1_val_a" value="999" />
+ <parameter name="ctle_gs1_val_b" value="999" />
+ <parameter name="ctle_gs2_val_a" value="999" />
+ <parameter name="ctle_gs2_val_b" value="999" />
+ <parameter name="ctle_hf_max_a" value="999" />
+ <parameter name="ctle_hf_max_b" value="999" />
+ <parameter name="ctle_hf_min_a" value="999" />
+ <parameter name="ctle_hf_min_b" value="999" />
+ <parameter name="ctle_hf_val_a" value="999" />
+ <parameter name="ctle_hf_val_ada_a" value="adaptable" />
+ <parameter name="ctle_hf_val_ada_b" value="adaptable" />
+ <parameter name="ctle_hf_val_b" value="999" />
+ <parameter name="ctle_lf_max_a" value="999" />
+ <parameter name="ctle_lf_max_b" value="999" />
+ <parameter name="ctle_lf_min_a" value="999" />
+ <parameter name="ctle_lf_min_b" value="999" />
+ <parameter name="ctle_lf_val_a" value="999" />
+ <parameter name="ctle_lf_val_ada_a" value="adaptable" />
+ <parameter name="ctle_lf_val_ada_b" value="adaptable" />
+ <parameter name="ctle_lf_val_b" value="999" />
+ <parameter name="deviceDieList" value="" />
+ <parameter name="deviceFamilyName" value="Arria 10" />
+ <parameter name="eg_addr" value="8" />
+ <parameter name="ena_hash" value="false" />
+ <parameter name="enable_alt_reconfig" value="false" />
+ <parameter name="enable_ecc" value="false" />
+ <parameter name="enable_ena" value="32" />
+ <parameter name="enable_gmii_loopback" value="true" />
+ <parameter name="enable_hd_logic" value="false" />
+ <parameter name="enable_hidden_features" value="false" />
+ <parameter name="enable_mac_flow_ctrl" value="false" />
+ <parameter name="enable_mac_vlan" value="false" />
+ <parameter name="enable_magic_detect" value="false" />
+ <parameter name="enable_ptp_1step" value="false" />
+ <parameter name="enable_sgmii" value="false" />
+ <parameter name="enable_shift16" value="true" />
+ <parameter name="enable_sup_addr" value="false" />
+ <parameter name="enable_timestamping" value="false" />
+ <parameter name="enable_use_internal_fifo" value="true" />
+ <parameter name="export_pwrdn" value="false" />
+ <parameter name="ext_stat_cnt_ena" value="false" />
+ <parameter name="ifGMII" value="MII_GMII" />
+ <parameter name="ing_addr" value="8" />
+ <parameter name="max_channels" value="1" />
+ <parameter name="mdio_clk_div" value="40" />
+ <parameter name="nd_phyip_rcfg_enable" value="false" />
+ <parameter name="nf_phyip_rcfg_enable" value="false" />
+ <parameter name="part_trait_bd" value="NIGHTFURY5" />
+ <parameter name="phy_identifier" value="0" />
+ <parameter name="phyip_en_synce_support" value="false" />
+ <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
+ <parameter name="phyip_pll_type" value="CMU" />
+ <parameter name="phyip_pma_bonding_mode" value="x1" />
+ <parameter name="rcp_load_enable" value="0" />
+ <parameter name="rf_a_a" value="999" />
+ <parameter name="rf_a_b" value="999" />
+ <parameter name="rf_b0_a" value="999" />
+ <parameter name="rf_b0_ada_a" value="adaptable" />
+ <parameter name="rf_b0_ada_b" value="adaptable" />
+ <parameter name="rf_b0_b" value="999" />
+ <parameter name="rf_b0t_a" value="999" />
+ <parameter name="rf_b0t_b" value="999" />
+ <parameter name="rf_b1_a" value="999" />
+ <parameter name="rf_b1_ada_a" value="adaptable" />
+ <parameter name="rf_b1_ada_b" value="adaptable" />
+ <parameter name="rf_b1_b" value="999" />
+ <parameter name="rf_p0_val_a" value="999" />
+ <parameter name="rf_p0_val_ada_a" value="adaptable" />
+ <parameter name="rf_p0_val_ada_b" value="adaptable" />
+ <parameter name="rf_p0_val_b" value="999" />
+ <parameter name="rf_p1_max_a" value="999" />
+ <parameter name="rf_p1_max_b" value="999" />
+ <parameter name="rf_p1_min_a" value="999" />
+ <parameter name="rf_p1_min_b" value="999" />
+ <parameter name="rf_p1_val_a" value="999" />
+ <parameter name="rf_p1_val_ada_a" value="adaptable" />
+ <parameter name="rf_p1_val_ada_b" value="adaptable" />
+ <parameter name="rf_p1_val_b" value="999" />
+ <parameter name="rf_p2_max_a" value="999" />
+ <parameter name="rf_p2_max_b" value="999" />
+ <parameter name="rf_p2_min_a" value="999" />
+ <parameter name="rf_p2_min_b" value="999" />
+ <parameter name="rf_p2_val_a" value="999" />
+ <parameter name="rf_p2_val_ada_a" value="adaptable" />
+ <parameter name="rf_p2_val_ada_b" value="adaptable" />
+ <parameter name="rf_p2_val_b" value="999" />
+ <parameter name="rf_reserved0_a" value="999" />
+ <parameter name="rf_reserved0_b" value="999" />
+ <parameter name="rf_reserved1_a" value="999" />
+ <parameter name="rf_reserved1_b" value="999" />
+ <parameter name="starting_channel_number" value="0" />
+ <parameter name="stat_cnt_ena" value="true" />
+ <parameter name="transceiver_type" value="LVDS_IO" />
+ <parameter name="tstamp_fp_width" value="4" />
+ <parameter name="useMDIO" value="false" />
+ <parameter name="use_mac_clken" value="false" />
+ <parameter name="use_misc_ports" value="true" />
+ </module>
+</system>
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/run_patch.sh b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/run_patch.sh
new file mode 100755
index 0000000000000000000000000000000000000000..05a043f5a296d48fd8a9354894bef22b7c74d5af
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/run_patch.sh
@@ -0,0 +1,10 @@
+#!/bin/bash
+
+patchfile='sdc_util.sdc.patch'
+
+echo -e "Applying patch: $patchfile\n"
+
+cd generated/altera_lvds_core20_160/synth
+patch <../../../${patchfile}
+
+echo "done."
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/sdc_util.sdc.patch b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/sdc_util.sdc.patch
new file mode 100644
index 0000000000000000000000000000000000000000..1cd9335d8eb7728af5909e0af15591a97217f79b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/sdc_util.sdc.patch
@@ -0,0 +1,31 @@
+*** ip_arria10_e3sge3_tse_sgmii_lvds/altera_lvds_core20_160/synth/sdc_util.tcl 2016-01-29 11:25:55.709095784 +0100
+--- generated/altera_lvds_core20_160/synth/sdc_util.tcl 2016-01-29 11:27:18.456556665 +0100
+***************
+*** 63,75 ****
+
+ eval "create_generated_clock \
+ -name $opts(-name) \
+! -source $opts(-source) \
+ -multiply_by $multiply_by \
+ -divide_by $opts(-divide_by) \
+ -phase $opts(-phase) \
+ -duty_cycle $opts(-duty_cycle) \
+ $extra_params \
+! $opts(-target)"
+ }
+
+ proc altera_iosubsystem_get_clock_name_from_target { target } {
+--- 63,75 ----
+
+ eval "create_generated_clock \
+ -name $opts(-name) \
+! -source \{$opts(-source)\} \
+ -multiply_by $multiply_by \
+ -divide_by $opts(-divide_by) \
+ -phase $opts(-phase) \
+ -duty_cycle $opts(-duty_cycle) \
+ $extra_params \
+! \{$opts(-target)\}"
+ }
+
+ proc altera_iosubsystem_get_clock_name_from_target { target } {
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/tb_ip_arria10_e2sg_tse_sgmii_lvds.vhd b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/tb_ip_arria10_e2sg_tse_sgmii_lvds.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..74fdfe4c2826c3c24aa6769fdfce2ceb1eb31443
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/tb_ip_arria10_e2sg_tse_sgmii_lvds.vhd
@@ -0,0 +1,730 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Testbench for ip_arria10_e2sg_tse_sgmii_lvds.
+-- Description:
+-- The testbench in /testbench/tse_sgmii_lvds/tse_sgmii_lvds_tb.vhd that is
+-- generated by the MegaWizard provides an elaborate testbench. For
+-- Uniboard purposes in tb/ a minimal testbench tb_tse_sgmii_lvds.vhd was
+-- derived manually from the generated testbench. This tb_tse_sgmii_lvds
+-- is more easy to use.
+-- The tb is self checking based on that tx_pkt_cnt=rx_pkt_cnt must be true
+-- at the tb_end.
+-- Usage:
+-- > as 10
+-- > run -all
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+
+
+ENTITY tb_ip_arria10_e2sg_tse_sgmii_lvds IS
+END tb_ip_arria10_e2sg_tse_sgmii_lvds;
+
+
+ARCHITECTURE tb OF tb_ip_arria10_e2sg_tse_sgmii_lvds IS
+
+ CONSTANT sys_clk_period : TIME := 10 ns; -- 100 MHz
+ CONSTANT eth_clk_period : TIME := 8 ns; -- 125 MHz
+
+ CONSTANT c_tse_reg_addr_w : NATURAL := 8; -- = max 256 MAC registers
+ CONSTANT c_tse_byte_addr_w : NATURAL := c_tse_reg_addr_w + 2;
+ CONSTANT c_tse_byte_addr_pcs_offset : NATURAL := 16#200#; -- table 4.8, 4.9 in ug_ethernet.pdf
+ CONSTANT c_tse_data_w : NATURAL := c_word_w; -- = 32
+
+ CONSTANT c_tse_symbol_w : NATURAL := c_byte_w; -- = 8
+ CONSTANT c_tse_symbol_max : NATURAL := 2**c_tse_symbol_w-1; -- = 255
+ CONSTANT c_tse_symbols_per_beat : NATURAL := c_tse_data_w / c_tse_symbol_w; -- = 4
+
+ CONSTANT c_tse_pcs_reg_addr_w : NATURAL := 5; -- = max 32 PCS registers
+ CONSTANT c_tse_pcs_halfword_addr_w : NATURAL := c_tse_pcs_reg_addr_w + 1; -- table 4.17 in ug_ethernet.pdf
+ CONSTANT c_tse_pcs_byte_addr_w : NATURAL := c_tse_pcs_reg_addr_w + 2;
+ CONSTANT c_tse_pcs_data_w : NATURAL := c_halfword_w; -- = 16;
+
+ CONSTANT c_tse_empty_w : NATURAL := 2;
+ CONSTANT c_tse_tx_error_w : NATURAL := 1;
+ CONSTANT c_tse_rx_error_w : NATURAL := 6;
+ CONSTANT c_tse_error_w : NATURAL := largest(c_tse_tx_error_w, c_tse_rx_error_w);
+ CONSTANT c_tse_err_stat_w : NATURAL := 18;
+ CONSTANT c_tse_frm_type_w : NATURAL := 4;
+
+ CONSTANT c_tse_tx_fifo_depth : NATURAL := 256; -- nof words for Tx FIFO
+ CONSTANT c_tse_rx_fifo_depth : NATURAL := 256; -- nof words for Rx FIFO
+
+ CONSTANT c_tse_promis_en : BOOLEAN := FALSE;
+ --CONSTANT c_tse_promis_en : BOOLEAN := TRUE;
+
+ CONSTANT c_tx_data_type : NATURAL := 1; -- 0 = symbols, 1 = counter
+ CONSTANT c_tx_ready_latency : NATURAL := 0;
+ CONSTANT c_nof_tx_not_valid : NATURAL := 0; -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+
+ CONSTANT c_eth_dst_mac : STD_LOGIC_VECTOR(47 DOWNTO 0) := X"10FA01020300";
+ CONSTANT c_eth_src_mac : STD_LOGIC_VECTOR(47 DOWNTO 0) := X"123456789ABC"; -- = 12-34-56-78-9A-BC
+ CONSTANT c_eth_ethertype : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"10FA";
+
+ TYPE t_mm_bus IS RECORD
+ -- Master In Slave Out
+ waitreq : STD_LOGIC;
+ rddata : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+ -- Master Out Slave In
+ address : STD_LOGIC_VECTOR(c_tse_byte_addr_w-1 DOWNTO 0);
+ wrdata : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+ wr : STD_LOGIC;
+ rd : STD_LOGIC;
+ END RECORD;
+
+ PROCEDURE proc_dbg_mm_bus(SIGNAL mm_miso : IN t_mm_bus;
+ SIGNAL mm_mosi : IN t_mm_bus;
+ SIGNAL dbg_mm : OUT t_mm_bus) IS
+ BEGIN
+ dbg_mm.waitreq <= mm_miso.waitreq;
+ dbg_mm.rddata <= mm_miso.rddata;
+ dbg_mm.address <= mm_mosi.address;
+ dbg_mm.wrdata <= mm_mosi.wrdata;
+ dbg_mm.wr <= mm_mosi.wr;
+ dbg_mm.rd <= mm_mosi.rd;
+ END proc_dbg_mm_bus;
+
+ -- Wait for MM access (either read or write) finished
+ PROCEDURE proc_mm_access(SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_waitreq : IN STD_LOGIC;
+ SIGNAL mm_access : OUT STD_LOGIC) IS
+ BEGIN
+ mm_access <= '1';
+ WAIT UNTIL rising_edge(mm_clk);
+ WHILE mm_waitreq='1' LOOP
+ WAIT UNTIL rising_edge(mm_clk);
+ END LOOP;
+ mm_access <= '0';
+ END proc_mm_access;
+
+ -- Use word addressing for MAC registers according to table 4.8, 4.9
+ PROCEDURE proc_wr_mac(CONSTANT mac_addr : IN NATURAL;
+ CONSTANT mac_data : IN NATURAL;
+ SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_miso : IN t_mm_bus;
+ SIGNAL mm_mosi : OUT t_mm_bus) IS
+ BEGIN
+ mm_mosi.address <= STD_LOGIC_VECTOR(TO_UNSIGNED(mac_addr, c_tse_byte_addr_w));
+ mm_mosi.wrdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(mac_data, c_tse_data_w));
+ proc_mm_access(mm_clk, mm_miso.waitreq, mm_mosi.wr);
+ END proc_wr_mac;
+
+ PROCEDURE proc_rd_mac(CONSTANT mac_addr : IN NATURAL;
+ SIGNAL mac_data : OUT NATURAL;
+ SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_miso : IN t_mm_bus;
+ SIGNAL mm_mosi : OUT t_mm_bus) IS
+ BEGIN
+ mm_mosi.address <= STD_LOGIC_VECTOR(TO_UNSIGNED(mac_addr, c_tse_byte_addr_w));
+ proc_mm_access(mm_clk, mm_miso.waitreq, mm_mosi.rd);
+ MAC_data <= TO_INTEGER(UNSIGNED(mm_miso.rddata));
+ END proc_rd_mac;
+
+ -- Use halfword addressing for PCS register to match table 4.17
+ PROCEDURE proc_wr_pcs(CONSTANT pcs_addr : IN NATURAL;
+ CONSTANT pcs_data : IN NATURAL;
+ SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_miso : IN t_mm_bus;
+ SIGNAL mm_mosi : OUT t_mm_bus) IS
+ BEGIN
+ mm_mosi.address <= STD_LOGIC_VECTOR(TO_UNSIGNED(pcs_addr*2 + c_tse_byte_addr_pcs_offset, c_tse_byte_addr_w));
+ mm_mosi.wrdata <= (OTHERS=>'0');
+ mm_mosi.wrdata(c_tse_pcs_data_w-1 DOWNTO 0) <= STD_LOGIC_VECTOR(TO_UNSIGNED(pcs_data, c_tse_pcs_data_w));
+ proc_mm_access(mm_clk, mm_miso.waitreq, mm_mosi.wr);
+ END proc_wr_pcs;
+
+ PROCEDURE proc_rd_pcs(CONSTANT pcs_addr : IN NATURAL;
+ SIGNAL pcs_data : OUT NATURAL;
+ SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_miso : IN t_mm_bus;
+ SIGNAL mm_mosi : OUT t_mm_bus) IS
+ BEGIN
+ mm_mosi.address <= STD_LOGIC_VECTOR(TO_UNSIGNED(pcs_addr*2 + c_tse_byte_addr_pcs_offset, c_tse_byte_addr_w));
+ proc_mm_access(mm_clk, mm_miso.waitreq, mm_mosi.rd);
+ pcs_data <= TO_INTEGER(UNSIGNED(mm_miso.rddata(c_tse_pcs_data_w-1 DOWNTO 0)));
+ END proc_rd_pcs;
+
+ TYPE t_tse_stream IS RECORD
+ -- Source In or Sink Out
+ ready : STD_LOGIC;
+ -- Source Out or Sink In
+ data : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+ valid : STD_LOGIC;
+ sop : STD_LOGIC;
+ eop : STD_LOGIC;
+ empty : STD_LOGIC_VECTOR(c_tse_empty_w-1 DOWNTO 0);
+ err : STD_LOGIC_VECTOR(c_tse_error_w-1 DOWNTO 0);
+ END RECORD;
+
+ PROCEDURE proc_dbg_tse_stream_src(SIGNAL src_in : IN t_tse_stream;
+ SIGNAL src_out : IN t_tse_stream;
+ SIGNAL dbg_src : OUT t_tse_stream) IS
+ BEGIN
+ dbg_src.ready <= src_in.ready;
+ dbg_src.data <= src_out.data;
+ dbg_src.valid <= src_out.valid;
+ dbg_src.sop <= src_out.sop;
+ dbg_src.eop <= src_out.eop;
+ dbg_src.empty <= src_out.empty;
+ dbg_src.err <= src_out.err;
+ END proc_dbg_tse_stream_src;
+
+ PROCEDURE proc_dbg_tse_stream_snk(SIGNAL snk_in : IN t_tse_stream;
+ SIGNAL snk_out : IN t_tse_stream;
+ SIGNAL dbg_snk : OUT t_tse_stream) IS
+ BEGIN
+ dbg_snk.ready <= snk_out.ready;
+ dbg_snk.data <= snk_in.data;
+ dbg_snk.valid <= snk_in.valid;
+ dbg_snk.sop <= snk_in.sop;
+ dbg_snk.eop <= snk_in.eop;
+ dbg_snk.empty <= snk_in.empty;
+ dbg_snk.err <= snk_in.err;
+ END proc_dbg_tse_stream_snk;
+
+ -- Handle TX ready
+ -- Only support tx_ready_latency=0 or 1, corresponding to TX_ALMOST_FULL=3 or 4
+ -- Support for tx_ready_latency>1 requires keeping previous ready information
+ -- in a STD_LOGIC_VECTOR(tx_ready_latency-1 DOWNTO 0).
+ PROCEDURE proc_ready_latency(CONSTANT c_latency : IN NATURAL;
+ SIGNAL clk : IN STD_LOGIC;
+ SIGNAL ready : IN STD_LOGIC;
+ CONSTANT c_valid : IN STD_LOGIC;
+ CONSTANT c_sop : IN STD_LOGIC;
+ CONSTANT c_eop : IN STD_LOGIC;
+ SIGNAL out_valid : OUT STD_LOGIC;
+ SIGNAL out_sop : OUT STD_LOGIC;
+ SIGNAL out_eop : OUT STD_LOGIC) IS
+ BEGIN
+ IF c_latency=0 THEN
+ out_valid <= c_valid;
+ out_sop <= c_sop;
+ out_eop <= c_eop;
+ WAIT UNTIL rising_edge(clk);
+ WHILE ready /= '1' LOOP
+ WAIT UNTIL rising_edge(clk);
+ END LOOP;
+ END IF;
+ IF c_latency=1 THEN
+ WHILE ready /= '1' LOOP
+ out_valid <= '0';
+ out_sop <= '0';
+ out_eop <= '0';
+ WAIT UNTIL rising_edge(clk);
+ END LOOP;
+ out_valid <= c_valid;
+ out_sop <= c_sop;
+ out_eop <= c_eop;
+ WAIT UNTIL rising_edge(clk);
+ END IF;
+ END proc_ready_latency;
+
+ -- Transmit user packet
+ -- . Use word aligned payload data, so with half word inserted before the 14 byte header
+ -- . Packets can be send immediately after eachother so new sop directly after last eop
+ -- . The word rate is controlled by respecting ready from the MAC
+ PROCEDURE proc_tx_packet(CONSTANT dst_mac_addr : IN STD_LOGIC_VECTOR(c_eth_dst_mac'RANGE);
+ CONSTANT src_mac_addr : IN STD_LOGIC_VECTOR(c_eth_src_mac'RANGE);
+ CONSTANT ethertype : IN STD_LOGIC_VECTOR(c_eth_ethertype'RANGE);
+ CONSTANT data_len : IN NATURAL; -- in symbols = octets = bytes
+ SIGNAL dp_clk : IN STD_LOGIC;
+ SIGNAL dp_src_in : IN t_tse_stream;
+ SIGNAL dp_src_out : OUT t_tse_stream) IS
+ CONSTANT c_mod : NATURAL := data_len MOD c_tse_symbols_per_beat;
+ CONSTANT c_nof_data_beats : NATURAL := data_len / c_tse_symbols_per_beat + sel_a_b(c_mod, 1, 0);
+ CONSTANT c_empty : NATURAL := sel_a_b(c_mod, c_tse_symbols_per_beat - c_mod, 0);
+ VARIABLE v_sym : UNSIGNED(c_tse_symbol_w-1 DOWNTO 0) := (OTHERS=>'0');
+ VARIABLE v_num : UNSIGNED(c_tse_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ BEGIN
+ -- DST MAC
+ dp_src_out.empty <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, c_tse_empty_w));
+ dp_src_out.data <= (OTHERS=>'0');
+ dp_src_out.data(15 DOWNTO 0) <= hton(dst_mac_addr(15 DOWNTO 0)); -- send to itself
+ proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '1', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+ dp_src_out.data <= hton(dst_mac_addr(47 DOWNTO 16));
+ proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+ -- SRC MAC
+ dp_src_out.data <= hton(src_mac_addr(31 DOWNTO 0));
+ proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+ -- SRC MAC & ETHERTYPE
+ dp_src_out.data <= hton(src_mac_addr(47 DOWNTO 32)) & hton(c_eth_ethertype);
+ -- DATA
+ FOR I IN 0 TO c_nof_data_beats-1 LOOP
+ proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+ IF c_tx_data_type=0 THEN
+ -- data : X"01020304", X"05060708", X"090A0B0C", etc
+ FOR J IN c_tse_symbols_per_beat-1 DOWNTO 0 LOOP
+ v_sym := v_sym + 1;
+ dp_src_out.data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w) <= STD_LOGIC_VECTOR(v_sym);
+ END LOOP;
+ ELSE
+ -- data : X"00000001", X"00000002", X"00000003", etc
+ v_num := v_num + 1;
+ dp_src_out.data <= STD_LOGIC_VECTOR(v_num);
+ END IF;
+ -- tb : pull valid low for some time during the middle of the payload
+ IF c_nof_tx_not_valid > 0 AND I=c_nof_data_beats/2 THEN
+ dp_src_out.valid <= '0';
+ FOR I IN 0 TO c_nof_tx_not_valid LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+ dp_src_out.valid <= '1';
+ END IF;
+ END LOOP;
+ IF c_empty > 0 THEN
+ dp_src_out.empty <= STD_LOGIC_VECTOR(TO_UNSIGNED(c_empty, c_tse_empty_w));
+ FOR J IN c_empty-1 DOWNTO 0 LOOP
+ dp_src_out.data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w) <= (OTHERS=>'0');
+ END LOOP;
+ END IF;
+ proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '1', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+ dp_src_out.data <= (OTHERS=>'0');
+ dp_src_out.valid <= '0';
+ dp_src_out.eop <= '0';
+ dp_src_out.empty <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, c_tse_empty_w));
+ END proc_tx_packet;
+
+ PROCEDURE proc_valid_sop(SIGNAL clk : IN STD_LOGIC;
+ SIGNAL in_valid : IN STD_LOGIC;
+ SIGNAL in_sop : IN STD_LOGIC) IS
+ BEGIN
+ WAIT UNTIL rising_edge(clk);
+ WHILE in_valid /= '1' AND in_sop /= '1' LOOP
+ WAIT UNTIL rising_edge(clk);
+ END LOOP;
+ END proc_valid_sop;
+
+ PROCEDURE proc_valid(SIGNAL clk : IN STD_LOGIC;
+ SIGNAL in_valid : IN STD_LOGIC) IS
+ BEGIN
+ WAIT UNTIL rising_edge(clk);
+ WHILE in_valid /= '1' LOOP
+ WAIT UNTIL rising_edge(clk);
+ END LOOP;
+ END proc_valid;
+
+ -- Receive packet
+ -- . Use word aligned payload data, so with half word inserted before the 14 byte header
+ -- . Packets can be always be received, assume the user application is always ready
+ -- . The CRC32 is also passed on to the user at eop.
+ -- . Note that when empty/=0 then the CRC32 is not word aligned, so therefore use prev_data to be able
+ -- to handle part of last data word in case empty/=0 at eop
+ PROCEDURE proc_rx_packet(CONSTANT dst_mac_addr : IN STD_LOGIC_VECTOR(c_eth_dst_mac'RANGE);
+ CONSTANT src_mac_addr : IN STD_LOGIC_VECTOR(c_eth_src_mac'RANGE);
+ CONSTANT ethertype : IN STD_LOGIC_VECTOR(c_eth_ethertype'RANGE);
+ SIGNAL dp_clk : IN STD_LOGIC;
+ SIGNAL dp_snk_in : IN t_tse_stream;
+ SIGNAL dp_snk_out : OUT t_tse_stream) IS
+ VARIABLE v_sym : UNSIGNED(c_tse_symbol_w-1 DOWNTO 0) := (OTHERS=>'0');
+ VARIABLE v_num : UNSIGNED(c_tse_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ VARIABLE v_empty : NATURAL;
+ VARIABLE v_first : BOOLEAN := TRUE;
+ VARIABLE v_data : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+ VARIABLE v_prev_data : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+ BEGIN
+ -- Keep ff_rx_snk_out.ready='1' all the time
+ dp_snk_out.ready <= '1';
+ -- Verify DST MAC
+ proc_valid_sop(dp_clk, dp_snk_in.valid, dp_snk_in.sop);
+ ASSERT dp_snk_in.data(31 DOWNTO 16) = X"0000" REPORT "RX: Alignment half word not zero" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(15 DOWNTO 0) = hton(dst_mac_addr(15 DOWNTO 0)) REPORT "RX: Wrong dst_mac_addr(15 DOWNTO 0)" SEVERITY ERROR;
+ proc_valid(dp_clk, dp_snk_in.valid);
+ ASSERT dp_snk_in.data(31 DOWNTO 0) = hton(dst_mac_addr(47 DOWNTO 16)) REPORT "RX: Wrong dst_mac_addr(47 DOWNTO 16)" SEVERITY ERROR;
+ -- Verify SRC MAC
+ proc_valid(dp_clk, dp_snk_in.valid);
+ ASSERT dp_snk_in.data(31 DOWNTO 0) = hton(src_mac_addr(31 DOWNTO 0)) REPORT "RX: Wrong src_mac_addr(31 DOWNTO 0)" SEVERITY ERROR;
+ -- Verify SRC MAC & ETHERTYPE
+ proc_valid(dp_clk, dp_snk_in.valid);
+ ASSERT dp_snk_in.data(31 DOWNTO 16) = hton(src_mac_addr(47 DOWNTO 32)) REPORT "RX: Wrong src_mac_addr(47 DOWNTO 32)" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(15 DOWNTO 0) = hton(c_eth_ethertype) REPORT "RX: Wrong ethertype" SEVERITY ERROR;
+ -- Verify DATA
+ v_first := TRUE;
+ proc_valid(dp_clk, dp_snk_in.valid);
+ WHILE dp_snk_in.eop /= '1' LOOP
+ v_prev_data := v_data;
+ v_data := dp_snk_in.data;
+ IF v_first = FALSE THEN
+ IF c_tx_data_type=0 THEN
+ -- data : X"01020304", X"05060708", X"090A0B0C", etc
+ FOR J IN c_tse_symbols_per_beat-1 DOWNTO 0 LOOP
+ v_sym := v_sym + 1;
+ ASSERT UNSIGNED(v_prev_data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w)) = v_sym REPORT "RX: Wrong data symbol" SEVERITY ERROR;
+ END LOOP;
+ ELSE
+ -- data : X"00000001", X"00000002", X"00000003", etc
+ v_num := v_num + 1;
+ ASSERT UNSIGNED(v_prev_data) = v_num REPORT "RX: Wrong data word" SEVERITY ERROR;
+ END IF;
+ END IF;
+ v_first := FALSE;
+ proc_valid(dp_clk, dp_snk_in.valid);
+ END LOOP;
+ -- Verify last DATA and CRC32 if empty /=0 else the last word is only the CRC32
+ v_prev_data := v_data;
+ v_data := dp_snk_in.data;
+ v_empty := TO_INTEGER(UNSIGNED(dp_snk_in.empty));
+ IF v_empty > 0 THEN
+ FOR J IN v_empty-1 DOWNTO 0 LOOP
+ v_prev_data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w) := (OTHERS=>'0');
+ END LOOP;
+ IF c_tx_data_type=0 THEN
+ -- data : X"01020304", X"05060708", X"090A0B0C", etc
+ FOR J IN c_tse_symbols_per_beat-1 DOWNTO v_empty LOOP -- ignore CRC32 symbols in last data word
+ v_sym := v_sym + 1;
+ ASSERT UNSIGNED(v_prev_data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w)) = v_sym REPORT "RX: Wrong empty data symbol" SEVERITY ERROR;
+ END LOOP;
+ ELSE
+ -- data : X"00000001", X"00000002", X"00000003", etc
+ v_num := v_num + 1;
+ FOR J IN v_empty-1 DOWNTO 0 LOOP
+ v_num((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w) := (OTHERS=>'0'); -- force CRC32 symbols in last data word to 0
+ END LOOP;
+ ASSERT UNSIGNED(v_prev_data) = v_num REPORT "RX: Wrong empty data word" SEVERITY ERROR;
+ END IF;
+ ELSE
+ -- No verify on CRC32 word
+ END IF;
+ END proc_rx_packet;
+
+
+ -- Clocks and reset
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL sys_clk : STD_LOGIC := '0';
+ SIGNAL dp_clk : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC;
+
+ -- TSE MAC control interface
+ SIGNAL mm_init : STD_LOGIC := '1';
+ SIGNAL mm_miso : t_mm_bus; -- master in slave out
+ SIGNAL mm_mosi : t_mm_bus; -- master out slave in
+
+ SIGNAL pcs_rddata : NATURAL; -- [c_tse_pcs_data_w-1:0]
+
+ SIGNAL tse_led_an : STD_LOGIC;
+ SIGNAL tse_led_link : STD_LOGIC;
+
+ -- TSE MAC transmit interface
+ -- . Avalon ST source
+ SIGNAL ff_tx_src_in : t_tse_stream;
+ SIGNAL ff_tx_src_out : t_tse_stream;
+ -- . MAC specific
+ SIGNAL ff_tx_crc_fwd : STD_LOGIC;
+ SIGNAL ff_tx_septy : STD_LOGIC;
+ SIGNAL ff_tx_a_full : STD_LOGIC;
+ SIGNAL ff_tx_a_empty : STD_LOGIC;
+ SIGNAL ff_tx_uflow : STD_LOGIC;
+
+ -- TSE MAC receive interface
+ -- . Avalon ST sink
+ SIGNAL ff_rx_snk_in : t_tse_stream;
+ SIGNAL ff_rx_snk_out : t_tse_stream;
+ -- . MAC specific
+ SIGNAL ff_rx_ethertype: STD_LOGIC_VECTOR(c_tse_err_stat_w-1 DOWNTO 0);
+ SIGNAL ff_rx_frm_type : STD_LOGIC_VECTOR(c_tse_frm_type_w-1 DOWNTO 0);
+ SIGNAL ff_rx_dsav : STD_LOGIC;
+ SIGNAL ff_rx_a_full : STD_LOGIC;
+ SIGNAL ff_rx_a_empty : STD_LOGIC;
+
+ -- TSE PHY interface
+ SIGNAL eth_txp : STD_LOGIC;
+ SIGNAL eth_rxp : STD_LOGIC;
+
+ -- Verification
+ SIGNAL tx_pkt_cnt : NATURAL := 0;
+ SIGNAL rx_pkt_cnt : NATURAL := 0;
+
+ -- Debug signals to combine valid in and out of records
+ SIGNAL dbg_mm : t_mm_bus;
+ SIGNAL dbg_ff_tx : t_tse_stream;
+ SIGNAL dbg_ff_rx : t_tse_stream;
+
+BEGIN
+
+ eth_clk <= NOT eth_clk AFTER eth_clk_period/2; -- TSE reference clock
+ sys_clk <= NOT sys_clk AFTER sys_clk_period/2; -- System clock
+
+ mm_clk <= sys_clk;
+ dp_clk <= sys_clk;
+
+ -- Debug signals to combine valid in and out of records
+ proc_dbg_mm_bus( mm_miso, mm_mosi, dbg_mm);
+ proc_dbg_tse_stream_src(ff_tx_src_in, ff_tx_src_out, dbg_ff_tx);
+ proc_dbg_tse_stream_snk(ff_rx_snk_in, ff_rx_snk_out, dbg_ff_rx);
+
+ -- run 1 us
+ p_mm_stimuli : PROCESS
+ BEGIN
+ mm_init <= '1';
+ mm_mosi.wr <= '0';
+ mm_mosi.rd <= '0';
+
+ -- reset release
+ mm_rst <= '1';
+ FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
+ mm_rst <= '0';
+ FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
+
+ -- PSC control
+ proc_rd_pcs(16#22#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- REV --> 0x0901
+ proc_wr_pcs(16#28#, 16#0008#, mm_clk, mm_miso, mm_mosi); -- IF_MODE <-- Force 1GbE, no autonegatiation
+ proc_rd_pcs(16#00#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- CONTROL --> 0x1140
+ proc_rd_pcs(16#02#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- STATUS --> 0x000D
+ proc_wr_pcs(16#00#, 16#0140#, mm_clk, mm_miso, mm_mosi); -- CONTROL <-- Auto negotiate disable
+
+ -- MAC control
+ proc_rd_mac(16#000#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- REV --> CUST_VERSION & 0x0901
+ IF c_tse_promis_en=FALSE THEN
+ proc_wr_mac(16#008#, 16#0100004B#, mm_clk, mm_miso, mm_mosi);
+ ELSE
+ proc_wr_mac(16#008#, 16#0100005B#, mm_clk, mm_miso, mm_mosi);
+ END IF;
+ -- COMMAND_CONFIG <--
+ -- Only the bits relevant to UniBoard are explained here, others are 0
+ -- [ 0] = TX_ENA = 1, enable tx datapath
+ -- [ 1] = RX_ENA = 1, enable rx datapath
+ -- [ 2] = XON_GEN = 0
+ -- [ 3] = ETH_SPEED = 1, enable 1GbE operation
+ -- [ 4] = PROMIS_EN = 0, when 1 then receive all frames
+ -- [ 5] = PAD_EN = 0, when 1 enable receive padding removal (requires ethertype=payload length)
+ -- [ 6] = CRC_FWD = 1, enable receive CRC forward
+ -- [ 7] = PAUSE_FWD = 0
+ -- [ 8] = PAUSE_IGNORE = 0
+ -- [ 9] = TX_ADDR_INS = 0, when 1 then MAX overwrites tx SRC MAC with mac_0,1 or one of the supplemental mac
+ -- [ 10] = HD_ENA = 0
+ -- [ 11] = EXCESS_COL = 0
+ -- [ 12] = LATE_COL = 0
+ -- [ 13] = SW_RESET = 0, when 1 MAC disables tx and rx, clear statistics and flushes receive FIFO
+ -- [ 14] = MHAS_SEL = 0, select multicast address resolutions hash-code mode
+ -- [ 15] = LOOP_ENA = 0
+ -- [18-16] = TX_ADDR_SEL[2:0] = 000, TX_ADDR_INS insert mac_0,1 or one of the supplemental mac
+ -- [ 19] = MAGIC_EN = 0
+ -- [ 20] = SLEEP = 0
+ -- [ 21] = WAKEUP = 0
+ -- [ 22] = XOFF_GEN = 0
+ -- [ 23] = CNT_FRM_ENA = 0
+ -- [ 24] = NO_LGTH_CHECK = 1, when 0 then check payload length of received frames (requires ethertype=payload length)
+ -- [ 25] = ENA_10 = 0
+ -- [ 26] = RX_ERR_DISC = 0, when 1 then discard erroneous frames (requires store and forward mode, so rx_section_full=0)
+ -- when 0 then pass on with rx_err[0]=1
+ -- [ 27] = DISABLE_RD_TIMEOUT = 0
+ -- [30-28] = RSVD = 000
+ -- [ 31] = CNT_RESET = 0, when 1 clear statistics
+ proc_wr_mac(16#00C#, 16#56789ABC#, mm_clk, mm_miso, mm_mosi); -- MAC_0
+ proc_wr_mac(16#010#, 16#00001234#, mm_clk, mm_miso, mm_mosi); -- MAC_1 <-- SRC_MAC = 12-34-56-78-9A-BC
+ proc_wr_mac(16#05C#, 16#0000000C#, mm_clk, mm_miso, mm_mosi); -- TX_IPG_LENGTH <-- interpacket gap = 12
+ proc_wr_mac(16#014#, 16#000005EE#, mm_clk, mm_miso, mm_mosi); -- FRM_LENGTH <-- receive max frame length = 1518
+
+ -- FIFO legenda:
+ -- . Tx section full = There is enough data in the FIFO to start reading it, when 0 then store and forward.
+ -- . Rx section full = There is enough data in the FIFO to start reading it, when 0 then store and forward.
+ -- . Tx section empty = There is not much empty space anymore in the FIFO, warn user via ff_tx_septy
+ -- . Rx section empty = There is not much empty space anymore in the FIFO, inform remote device via XOFF flow control
+ -- . Tx almost full = Assert ff_tx_a_full and deassert ff_tx_rdy. Furthermore TX_ALMOST_FULL = c_tx_ready_latency+3,
+ -- so choose 3 for zero tx ready latency
+ -- . Rx almost full = Assert ff_rx_a_full and if the user is not ready ff_rx_rdy then:
+ -- --> break off the reception with an error to avoid FIFO overflow
+ -- . Tx almost empty = Assert ff_tx_a_empty and if the FIFO does not contain a eop yet then:
+ -- --> break off the transmission with an error to avoid FIFO underflow
+ -- . Rx almost empty = Assert ff_rx_a_empty
+ -- Typical FIFO values:
+ -- . TX_SECTION_FULL = 16 > 8 = TX_ALMOST_EMPTY
+ -- . RX_SECTION_FULL = 16 > 8 = RX_ALMOST_EMPTY
+ -- . TX_SECTION_EMPTY = D-16 < D-3 = Tx FIFO depth - TX_ALMOST_FULL
+ -- . RX_SECTION_EMPTY = D-16 < D-8 = Rx FIFO depth - RX_ALMOST_FULL
+ -- . c_tse_tx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Tx user respects ff_tx_rdy, to store a complete
+ -- ETH packet would require 1518 byte, so 2 M9K = 2k * 8b
+ -- . c_tse_rx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Rx user ff_rx_rdy is sufficiently active
+ proc_wr_mac(16#01C#, c_tse_rx_fifo_depth-16, mm_clk, mm_miso, mm_mosi); -- RX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_wr_mac(16#020#, 16, mm_clk, mm_miso, mm_mosi); -- RX_SECTION_FULL <-- default 16
+ proc_wr_mac(16#024#, c_tse_tx_fifo_depth-16, mm_clk, mm_miso, mm_mosi); -- TX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_wr_mac(16#028#, 16, mm_clk, mm_miso, mm_mosi); -- TX_SECTION_FULL <-- default 16, >~ 8 otherwise no tx
+ proc_wr_mac(16#02C#, 8, mm_clk, mm_miso, mm_mosi); -- RX_ALMOST_EMPTY <-- default 8
+ proc_wr_mac(16#030#, 8, mm_clk, mm_miso, mm_mosi); -- RX_ALMOST_FULL <-- default 8
+ proc_wr_mac(16#034#, 8, mm_clk, mm_miso, mm_mosi); -- TX_ALMOST_EMPTY <-- default 8
+ proc_wr_mac(16#038#, c_tx_ready_latency+3, mm_clk, mm_miso, mm_mosi); -- TX_ALMOST_FULL <-- default 3
+
+ proc_rd_mac(16#0E8#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- TX_CMD_STAT --> 0x00040000 : [18]=1 TX_SHIFT16, [17]=0 OMIT_CRC
+ proc_rd_mac(16#0EC#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- RX_CMD_STAT --> 0x02000000 : [25]=1 RX_SHIFT16
+
+ WAIT UNTIL rising_edge(mm_clk);
+ mm_init <= '0';
+
+ WAIT;
+ END PROCESS;
+
+ p_tx_frame : PROCESS
+ BEGIN
+ -- . Avalon ST
+ ff_tx_src_out.data <= (OTHERS=>'0');
+ ff_tx_src_out.valid <= '0';
+ ff_tx_src_out.sop <= '0';
+ ff_tx_src_out.eop <= '0';
+ ff_tx_src_out.empty <= (OTHERS=>'0');
+ ff_tx_src_out.err <= (OTHERS=>'0');
+ -- . MAC specific
+ ff_tx_crc_fwd <= '0';
+
+ WHILE mm_init/='0' LOOP
+ WAIT UNTIL rising_edge(dp_clk);
+ END LOOP;
+ WHILE tse_led_link/='1' LOOP
+ WAIT UNTIL rising_edge(dp_clk);
+ END LOOP;
+ FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, "0000000000010000", 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+ proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1499, dp_clk, ff_tx_src_in, ff_tx_src_out); -- verify st empty
+ proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+
+ FOR I IN 0 TO 1500 * 2 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+
+ p_rx_frame : PROCESS
+ BEGIN
+ -- . Avalon ST
+ ff_rx_snk_out.ready <= '0';
+
+ WHILE mm_init/='0' LOOP
+ WAIT UNTIL rising_edge(dp_clk);
+ END LOOP;
+
+ -- Receive forever
+ WHILE TRUE LOOP
+ proc_rx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, dp_clk, ff_rx_snk_in, ff_rx_snk_out);
+ END LOOP;
+
+ WAIT;
+ END PROCESS;
+
+ dut : ENTITY work.ip_arria10_e2sg_tse_sgmii_lvds
+ -- The ip_arria10_e2sg_tse_sgmii_lvds needs to be regenerated if its parameters are changed.
+ -- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
+ -- . ENABLE_SUP_ADDR = 0 : An extra MAC addresses can e.g. be used as service MAC for tests
+ -- . ENA_HASH = 0 : A multi cast hash table can be used to address all nodes at once
+ -- . STAT_CNT_ENA = 0 : PHY statistics counts are useful for monitoring, but not realy needed
+ -- . EG_FIFO = 256 : Tx FIFO depth in nof 32 bit words (256 --> 1 M9K)
+ -- . ING_FIFO = 256 : Rx FIFO depth in nof 32 bit words (256 --> 1 M9K)
+ PORT MAP (
+ -- MAC transmit interface
+ -- . Avalon ST
+ ff_tx_clk => dp_clk, -- : in std_logic := '0'; -- transmit_clock_connection.clk
+ ff_tx_rdy => ff_tx_src_in.ready, -- : out std_logic; -- .ready
+ ff_tx_data => ff_tx_src_out.data, -- : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
+ ff_tx_wren => ff_tx_src_out.valid, -- : in std_logic := '0'; -- .valid
+ ff_tx_sop => ff_tx_src_out.sop, -- : in std_logic := '0'; -- .startofpacket
+ ff_tx_eop => ff_tx_src_out.eop, -- : in std_logic := '0'; -- .endofpacket
+ ff_tx_mod => ff_tx_src_out.empty, -- : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
+ ff_tx_err => ff_tx_src_out.err(0), -- : in std_logic := '0'; -- .error
+ -- . MAC specific
+ ff_tx_crc_fwd => ff_tx_crc_fwd, -- : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd -- when '0' MAC inserts CRC32 after eop
+ ff_tx_septy => ff_tx_septy, -- : out std_logic; -- .ff_tx_septy -- when '0' then tx FIFO goes above section-empty threshold
+ ff_tx_a_full => ff_tx_a_full, -- : out std_logic; -- .ff_tx_a_full -- when '1' then tx FIFO goes above almost-full threshold
+ ff_tx_a_empty => ff_tx_a_empty, -- : out std_logic; -- .ff_tx_a_empty -- when '1' then tx FIFO goes below almost-empty threshold
+ tx_ff_uflow => ff_tx_uflow, -- : out std_logic; -- .tx_ff_uflow -- when '1' then tx FIFO underflow
+ -- MAC receive interface
+ -- . Avalon STs
+ ff_rx_clk => dp_clk, -- : in std_logic := '0'; -- receive_clock_connection.clk
+ ff_rx_rdy => ff_rx_snk_out.ready, -- : in std_logic := '0'; -- .ready
+ ff_rx_data => ff_rx_snk_in.data, -- : out std_logic_vector(31 downto 0); -- receive.data
+ ff_rx_dval => ff_rx_snk_in.valid, -- : out std_logic; -- .valid
+ ff_rx_sop => ff_rx_snk_in.sop, -- : out std_logic; -- .startofpacket
+ ff_rx_eop => ff_rx_snk_in.eop, -- : out std_logic; -- .endofpacket
+ ff_rx_mod => ff_rx_snk_in.empty, -- : out std_logic_vector(1 downto 0); -- .empty
+ rx_err => ff_rx_snk_in.err, -- : out std_logic_vector(5 downto 0); -- .error
+ -- [5] collision error (can only occur in half duplex mode)
+ -- [4] PHY error on GMII
+ -- [3] receive frame truncated due to FIFO overflow
+ -- [2] CRC-32 error
+ -- [1] invalid length
+ -- [0] = OR of [1:5]
+ -- . MAC specific
+ rx_err_stat => ff_rx_ethertype, -- : out std_logic_vector(17 downto 0); -- .rx_err_stat -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
+ rx_frm_type => ff_rx_frm_type, -- : out std_logic_vector(3 downto 0); -- .rx_frm_type -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
+ ff_rx_dsav => ff_rx_dsav, -- : out std_logic; -- .ff_rx_dsav -- rx frame available, but not necessarily a complete frame
+ ff_rx_a_full => ff_rx_a_full, -- : out std_logic; -- .ff_rx_a_full -- when '1' then rx FIFO goes above almost-full threshold
+ ff_rx_a_empty => ff_rx_a_empty, -- : out std_logic; -- .ff_rx_a_empty -- when '1' sthen rx FIFO goes below almost-empty threshold
+ -- Reset
+ reset => mm_rst, -- : in std_logic := '0'; -- reset_connection.reset -- asynchronous reset (choose synchronous to mm_clk)
+ -- MM control interface
+ clk => mm_clk, -- : in std_logic := '0'; -- control_port_clock_connection.clk
+ reg_addr => mm_mosi.address(c_tse_byte_addr_w-1 DOWNTO 2), -- : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
+ reg_data_out => mm_miso.rddata, -- : out std_logic_vector(31 downto 0); -- control_port.readdata
+ reg_rd => mm_mosi.rd, -- : in std_logic := '0'; -- .read
+ reg_data_in => mm_mosi.wrdata, -- : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reg_wr => mm_mosi.wr, -- : in std_logic := '0'; -- .write
+ reg_busy => mm_miso.waitreq, -- : out std_logic; -- .waitrequest
+ -- Status LEDs
+ led_an => tse_led_an, -- : out std_logic; -- .an -- '1' = autonegation completed
+ led_link => tse_led_link, -- : out std_logic; -- .link -- '1' = successful link synchronisation
+ led_disp_err => OPEN, -- : out std_logic; -- .disp_err -- TBI character error
+ led_char_err => OPEN, -- : out std_logic; -- .char_err -- TBI disparity errorreceived
+ led_crs => OPEN, -- : out std_logic; -- status_led_connection.crs
+ led_col => OPEN, -- : out std_logic; -- .col
+ -- Serial 1.25 Gbps
+ rx_recovclkout => OPEN, -- : out std_logic; -- serdes_control_connection.export
+ ref_clk => eth_clk, -- : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
+ txp => eth_txp, -- : out std_logic -- .txp_0
+ rxp => eth_rxp -- : in std_logic := '0'; -- serial_connection.rxp_0
+ );
+
+ -- Loopback
+ eth_rxp <= eth_txp;
+
+ -- Verification
+ tx_pkt_cnt <= tx_pkt_cnt + 1 WHEN ff_tx_src_out.sop='1' AND rising_edge(dp_clk);
+ rx_pkt_cnt <= rx_pkt_cnt + 1 WHEN ff_rx_snk_in.eop='1' AND rising_edge(dp_clk);
+
+ p_tb_end : PROCESS
+ BEGIN
+ WAIT UNTIL tb_end='1';
+
+ -- Verify that all transmitted packets have been received
+ IF tx_pkt_cnt=0 THEN
+ REPORT "No packets were transmitted." SEVERITY ERROR;
+ ELSIF rx_pkt_cnt=0 THEN
+ REPORT "No packets were received." SEVERITY ERROR;
+ ELSIF tx_pkt_cnt/=rx_pkt_cnt THEN
+ REPORT "Not all transmitted packets were received." SEVERITY ERROR;
+ END IF;
+
+ -- Stop the simulation
+ ASSERT FALSE REPORT "Simulation finished." SEVERITY FAILURE;
+ WAIT;
+ END PROCESS;
+
+END tb;
diff --git a/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f7efd9f340be3decdca4296b302597caee3a104a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl
@@ -0,0 +1,47 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_voltage_sense/sim"
+
+vmap ip_arria10_e2sg_voltage_sense ./work/
+vmap altera_voltage_sensor_180 ./work/
+vmap altera_voltage_sensor_control_180 ./work/
+vmap altera_voltage_sensor_sample_store_180 ./work/
+
+
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_control_180/sim/mentor/altera_voltage_sensor_control.sv" -work altera_voltage_sensor_control_180
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_control_180/sim/mentor/voltage_sensor_avalon_controlr.sv" -work altera_voltage_sensor_control_180
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_control_180/sim/mentor/voltage_sensor_wrapper.sv" -work altera_voltage_sensor_control_180
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_180/sim/mentor/altera_voltage_sensor_sample_store.sv" -work altera_voltage_sensor_sample_store_180
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_180/sim/mentor/altera_voltage_sensor_sample_store_ram.sv" -work altera_voltage_sensor_sample_store_180
+ vlog -sv "$IP_DIR/../altera_voltage_sensor_sample_store_180/sim/mentor/altera_voltage_sensor_sample_store_register.sv" -work altera_voltage_sensor_sample_store_180
+ vcom "$IP_DIR/../altera_voltage_sensor_180/sim/ip_arria10_e2sg_voltage_sense_altera_voltage_sensor_180_bqre2vy.vhd" -work altera_voltage_sensor_180
+ vcom "$IP_DIR/ip_arria10_e2sg_voltage_sense.vhd" -work ip_arria10_e2sg_voltage_sense
diff --git a/libraries/technology/ip_arria10_e2sg/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/voltage_sense/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..176ede47d43cc7112cfcd6a775e2d4e49c0ec5eb
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/voltage_sense/hdllib.cfg
@@ -0,0 +1,25 @@
+hdl_lib_name = ip_arria10_e2sg_voltage_sense
+hdl_library_clause_name = ip_arria10_e2sg_voltage_sense_altera_voltage_sense_180
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+# There is no simulation model for the FPGA voltage sensor IP
+#modelsim_compile_ip_files =
+# $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_voltage_sense/ip_arria10_e2sg_voltage_sense.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_arria10_e2sg_voltage_sense.qsys
+
diff --git a/libraries/technology/ip_arria10_e2sg/voltage_sense/ip_arria10_e2sg_voltage_sense.qsys b/libraries/technology/ip_arria10_e2sg/voltage_sense/ip_arria10_e2sg_voltage_sense.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..bb8535c56275a0ef6b115a2575f25b333b9583f7
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/voltage_sense/ip_arria10_e2sg_voltage_sense.qsys
@@ -0,0 +1,142 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e2sg_voltage_sense">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $system
+ {
+ }
+ element voltage_sensor_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="device" value="10AX115U3F45E2SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="2" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>controller_csr</key>
+ <value>
+ <connectionPointName>controller_csr</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='controller_csr' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>sample_store_csr</key>
+ <value>
+ <connectionPointName>sample_store_csr</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='sample_store_csr' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>6</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="systemScripts" value="" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="clock" internal="voltage_sensor_0.clock" type="clock" dir="end">
+ <port name="clock_clk" internal="clock_clk" />
+ </interface>
+ <interface
+ name="controller_csr"
+ internal="voltage_sensor_0.controller_csr"
+ type="avalon"
+ dir="end">
+ <port name="controller_csr_address" internal="controller_csr_address" />
+ <port name="controller_csr_read" internal="controller_csr_read" />
+ <port name="controller_csr_readdata" internal="controller_csr_readdata" />
+ <port name="controller_csr_write" internal="controller_csr_write" />
+ <port name="controller_csr_writedata" internal="controller_csr_writedata" />
+ </interface>
+ <interface
+ name="reset_sink"
+ internal="voltage_sensor_0.reset_sink"
+ type="reset"
+ dir="end">
+ <port name="reset_sink_reset" internal="reset_sink_reset" />
+ </interface>
+ <interface
+ name="sample_store_csr"
+ internal="voltage_sensor_0.sample_store_csr"
+ type="avalon"
+ dir="end">
+ <port name="sample_store_csr_address" internal="sample_store_csr_address" />
+ <port name="sample_store_csr_read" internal="sample_store_csr_read" />
+ <port name="sample_store_csr_readdata" internal="sample_store_csr_readdata" />
+ <port name="sample_store_csr_write" internal="sample_store_csr_write" />
+ <port
+ name="sample_store_csr_writedata"
+ internal="sample_store_csr_writedata" />
+ </interface>
+ <interface
+ name="sample_store_irq"
+ internal="voltage_sensor_0.sample_store_irq"
+ type="interrupt"
+ dir="end">
+ <port name="sample_store_irq_irq" internal="sample_store_irq_irq" />
+ </interface>
+ <module
+ name="voltage_sensor_0"
+ kind="altera_voltage_sensor"
+ version="19.1.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="AUTO_DEVICE" value="10AX115U3F45E2SG" />
+ <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="CORE_VAR" value="0" />
+ <parameter name="MEM_TYPE" value="0" />
+ </module>
+</system>
diff --git a/libraries/technology/jesd204b/hdllib.cfg b/libraries/technology/jesd204b/hdllib.cfg
index b2666b1f15aece3806f8b35aa8212e0473fd6471..af4ed49167022faaad18b97797e3d3a08e98c2a0 100644
--- a/libraries/technology/jesd204b/hdllib.cfg
+++ b/libraries/technology/jesd204b/hdllib.cfg
@@ -1,15 +1,17 @@
hdl_lib_name = tech_jesd204b
hdl_library_clause_name = tech_jesd204b_lib
-hdl_lib_uses_synth = technology common dp ip_arria10_e1sg_jesd204b
-hdl_lib_uses_ip = ip_arria10_e1sg_jesd204b
+hdl_lib_uses_synth = technology common dp ip_arria10_e1sg_jesd204b ip_arria10_e2sg_jesd204b
+hdl_lib_uses_ip = ip_arria10_e1sg_jesd204b ip_arria10_e2sg_jesd204b
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
ip_arria10_e1sg_jesd204b ip_arria10_e1sg_jesd204b_alt_em10g32_180
+ ip_arria10_e2sg_jesd204b ip_arria10_e2sg_jesd204b_alt_em10g32_194
synth_files =
tech_jesd204b_component_pkg.vhd
tech_jesd204b_arria10_e1sg.vhd
+ tech_jesd204b_arria10_e2sg.vhd
tech_jesd204b.vhd
test_bench_files =
diff --git a/libraries/technology/jesd204b/tech_jesd204b.vhd b/libraries/technology/jesd204b/tech_jesd204b.vhd
index a301517a16297967fbcb88f400980baae3b48c30..3f9277b48a7329ef1dccfb00f6f2ddf694a00327 100644
--- a/libraries/technology/jesd204b/tech_jesd204b.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b.vhd
@@ -117,4 +117,33 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ENTITY work.tech_jesd204b_arria10_e2sg
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_nof_channels => g_nof_channels,
+ g_direction => g_direction
+ )
+ PORT MAP(
+ jesd204b_refclk => jesd204b_refclk,
+ jesd204b_sysref => jesd204b_sysref,
+ jesd204b_sync_n_arr => jesd204b_sync_n_arr,
+
+ rx_src_out_arr => rx_src_out_arr,
+ jesd204b_frame_clk => jesd204b_frame_clk,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+
+ -- Serial
+ serial_tx_arr => serial_tx_arr,
+ serial_rx_arr => serial_rx_arr
+ );
+ END GENERATE;
+
END str;
diff --git a/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd b/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b1476dadaf00c34d07943cb7d05dd7909328d112
--- /dev/null
+++ b/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd
@@ -0,0 +1,99 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+
+-- Purpose: Wrapper for the Intel Arria 10 e2sg (unb2b, unb2c) tecnology version of the
+-- JESD204b interface for ADCs and DACs
+-- Description
+--
+--
+
+LIBRARY IEEE, common_lib, dp_lib, technology_lib, ip_arria10_e2sg_jesd204b_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.tech_jesd204b_component_pkg.ALL;
+
+ENTITY tech_jesd204b_arria10_e2sg IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
+ g_nof_channels : NATURAL := 12;
+ g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ );
+ PORT (
+ -- JESD204B external signals
+ jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
+ jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+
+ -- Data to fabric
+ rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- Parallel data out to fabric
+ jesd204b_frame_clk : OUT STD_LOGIC := '0'; -- Regenerated data clock to fabric
+
+ -- MM Control
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+
+ jesd204b_mosi : IN t_mem_mosi; -- mm control
+ jesd204b_miso : OUT t_mem_miso;
+
+ -- Serial connections to transceiver pins
+ serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- Not used for ADC
+ serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+ );
+END tech_jesd204b_arria10_e2sg;
+
+
+ARCHITECTURE str OF tech_jesd204b_arria10_e2sg IS
+
+BEGIN
+ u_ip_arria10_e2sg_jesd204b : ip_arria10_e2sg_jesd204b
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_nof_channels => g_nof_channels,
+ g_direction => g_direction
+ )
+ PORT MAP(
+ jesd204b_refclk => jesd204b_refclk,
+ jesd204b_sysref => jesd204b_sysref,
+ jesd204b_sync_n_arr => jesd204b_sync_n_arr,
+
+ rx_src_out_arr => rx_src_out_arr,
+ jesd204b_frame_clk => jesd204b_frame_clk,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+
+ -- Serial
+ serial_tx_arr => serial_tx_arr,
+ serial_rx_arr => serial_rx_arr
+ );
+
+END str;
diff --git a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
index 59b6c20e9911cd6498573c4ccf5af19132f820cd..5ec26377673de0b9e17f26aa45b46c2379c0133f 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
@@ -65,6 +65,40 @@ PACKAGE tech_jesd204b_component_pkg IS
);
END COMPONENT;
+ ------------------------------------------------------------------------------
+ -- ip_arria10_e2sg
+ ------------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e2sg_jesd204b IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
+ g_nof_channels : NATURAL := 1;
+ g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ );
+ PORT (
+ -- JESD204B external signals
+ jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
+ jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
+ jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+
+ -- Data to fabric
+ rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- Parallel data out to fabric
+ jesd204b_frame_clk : OUT STD_LOGIC := '0'; -- Regenerated data clock to fabric
+
+ -- MM Control
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+
+ jesd204b_mosi : IN t_mem_mosi; -- mm control
+ jesd204b_miso : OUT t_mem_miso;
+
+ -- Serial connections to transceiver pins
+ serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- Not used for ADC
+ serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
END tech_jesd204b_component_pkg;
PACKAGE BODY tech_jesd204b_component_pkg IS
diff --git a/libraries/technology/mac_10g/hdllib.cfg b/libraries/technology/mac_10g/hdllib.cfg
index 157235e48c95a9d9f3ca3f66aad5605dfaf2c733..c922483ad86242bafb51561600cc5021751d8df7 100644
--- a/libraries/technology/mac_10g/hdllib.cfg
+++ b/libraries/technology/mac_10g/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = tech_mac_10g
hdl_library_clause_name = tech_mac_10g_lib
hdl_lib_uses_synth = technology common dp ip_stratixiv_mac_10g
-hdl_lib_uses_ip = ip_arria10_mac_10g ip_arria10_e3sge3_mac_10g ip_arria10_e1sg_mac_10g
+hdl_lib_uses_ip = ip_arria10_mac_10g ip_arria10_e3sge3_mac_10g ip_arria10_e1sg_mac_10g ip_arria10_e2sg_mac_10g
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -9,6 +9,7 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_mac_10g ip_arria10_mac_10g_alt_em10g32_150
ip_arria10_e3sge3_mac_10g ip_arria10_e3sge3_mac_10g_alt_em10g32_151
ip_arria10_e1sg_mac_10g ip_arria10_e1sg_mac_10g_alt_em10g32_180
+ ip_arria10_e2sg_mac_10g ip_arria10_e2sg_mac_10g_alt_em10g32_180
synth_files =
tech_mac_10g_component_pkg.vhd
@@ -16,6 +17,7 @@ synth_files =
tech_mac_10g_arria10.vhd
tech_mac_10g_arria10_e3sge3.vhd
tech_mac_10g_arria10_e1sg.vhd
+ tech_mac_10g_arria10_e2sg.vhd
tech_mac_10g.vhd
test_bench_files =
diff --git a/libraries/technology/mac_10g/tech_mac_10g.vhd b/libraries/technology/mac_10g/tech_mac_10g.vhd
index 5937011b3ab82bf7fddb2d91f5b19581fb807468..8a5cf23b6863e9656130411d82c58ef09211c58c 100644
--- a/libraries/technology/mac_10g/tech_mac_10g.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g.vhd
@@ -118,8 +118,8 @@ END tech_mac_10g;
ARCHITECTURE str OF tech_mac_10g IS
-- Adapt ST ready latency 1 to IP ready latency
- CONSTANT c_ip_tx_ready_latency : NATURAL := sel_a_b(g_technology=c_tech_stratixiv OR g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg, 0, 1);
- CONSTANT c_ip_rx_ready_latency : NATURAL := sel_a_b(g_technology=c_tech_stratixiv OR g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg, 0, 1);
+ CONSTANT c_ip_tx_ready_latency : NATURAL := sel_a_b(g_technology=c_tech_stratixiv OR g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg, 0, 1);
+ CONSTANT c_ip_rx_ready_latency : NATURAL := sel_a_b(g_technology=c_tech_stratixiv OR g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg, 0, 1);
SIGNAL tx_mac_snk_in_data : STD_LOGIC_VECTOR(c_tech_mac_10g_data_w-1 DOWNTO 0); -- 64 bit
SIGNAL tx_mac_snk_in : t_dp_sosi;
@@ -176,6 +176,14 @@ BEGIN
rx_clk_312, rx_clk_156, rx_rst, rx_mac_src_out, rx_mac_src_in,
xgmii_link_status, xgmii_tx_data, xgmii_rx_data);
END GENERATE;
+
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ENTITY work.tech_mac_10g_arria10_e2sg
+ PORT MAP (mm_clk, mm_rst, csr_mosi, csr_miso,
+ tx_clk_312, tx_clk_156, tx_rst, tx_mac_snk_in, tx_mac_snk_out,
+ rx_clk_312, rx_clk_156, rx_rst, rx_mac_src_out, rx_mac_src_in,
+ xgmii_link_status, xgmii_tx_data, xgmii_rx_data);
+ END GENERATE;
-----------------------------------------------------------------------------
-- Debug signals to ease monitoring in wave window
diff --git a/libraries/technology/mac_10g/tech_mac_10g_arria10_e2sg.vhd b/libraries/technology/mac_10g/tech_mac_10g_arria10_e2sg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..91c26a3c02cb1ac7f7841271e4d2f9119326acb6
--- /dev/null
+++ b/libraries/technology/mac_10g/tech_mac_10g_arria10_e2sg.vhd
@@ -0,0 +1,145 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_arria10_e2sg_mac_10g_alt_em10g32_180;
+
+LIBRARY IEEE, technology_lib, common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE work.tech_mac_10g_component_pkg.ALL;
+
+ENTITY tech_mac_10g_arria10_e2sg IS
+ PORT (
+ -- MM
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+ csr_mosi : IN t_mem_mosi; -- CSR = control status register
+ csr_miso : OUT t_mem_miso;
+
+ -- ST
+ tx_clk_312 : IN STD_LOGIC;
+ tx_clk_156 : IN STD_LOGIC;
+ tx_rst : IN STD_LOGIC;
+ tx_snk_in : IN t_dp_sosi;
+ tx_snk_out : OUT t_dp_siso;
+
+ rx_clk_312 : IN STD_LOGIC;
+ rx_clk_156 : IN STD_LOGIC;
+ rx_rst : IN STD_LOGIC;
+ rx_src_out : OUT t_dp_sosi;
+ rx_src_in : IN t_dp_siso;
+
+ -- XGMII
+ xgmii_link_status : OUT STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0); -- 2 bit
+ xgmii_tx_data : OUT STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0); -- 72 bit
+ xgmii_rx_data : IN STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0) -- 72 bit
+ );
+END tech_mac_10g_arria10_e2sg;
+
+
+ARCHITECTURE str OF tech_mac_10g_arria10_e2sg IS
+
+ CONSTANT c_mac_10g_csr_addr_w : NATURAL := func_tech_mac_10g_csr_addr_w(c_tech_arria10); -- = 13
+
+ SIGNAL mm_rst_n : STD_LOGIC;
+ SIGNAL tx_rst_n : STD_LOGIC;
+ SIGNAL rx_rst_n : STD_LOGIC;
+
+ SIGNAL avalon_rx_src_out : t_dp_sosi := c_dp_sosi_rst;
+
+BEGIN
+
+ mm_rst_n <= NOT mm_rst;
+ tx_rst_n <= NOT tx_rst;
+ rx_rst_n <= NOT rx_rst;
+
+ -- Default frame level flow control
+ tx_snk_out.xon <= '1';
+
+ -- Force rx_src_out.sop = 0 when rx_src_out.valid = '0'
+ p_rx_src_out : PROCESS(avalon_rx_src_out)
+ BEGIN
+ rx_src_out <= avalon_rx_src_out;
+ rx_src_out.sop <= avalon_rx_src_out.sop AND avalon_rx_src_out.valid;
+ END PROCESS;
+
+ u_ip_arria10_e2sg_mac_10g : ip_arria10_e2sg_mac_10g
+ PORT MAP (
+ csr_clk => mm_clk,
+ csr_rst_n => mm_rst_n,
+
+ csr_address => csr_mosi.address(c_mac_10g_csr_addr_w-1 DOWNTO 0), -- 13 bit
+ csr_read => csr_mosi.rd,
+ csr_write => csr_mosi.wr,
+ csr_writedata => csr_mosi.wrdata(c_word_w-1 DOWNTO 0), -- 32 bit
+ csr_readdata => csr_miso.rddata(c_word_w-1 DOWNTO 0), -- 32 bit
+ csr_waitrequest => csr_miso.waitrequest,
+
+ tx_312_5_clk => tx_clk_312,
+ tx_156_25_clk => tx_clk_156,
+ tx_rst_n => tx_rst_n,
+
+ avalon_st_tx_ready => tx_snk_out.ready,
+ avalon_st_tx_startofpacket => tx_snk_in.sop,
+ avalon_st_tx_endofpacket => tx_snk_in.eop,
+ avalon_st_tx_valid => tx_snk_in.valid,
+ avalon_st_tx_data => tx_snk_in.data(c_xgmii_data_w-1 DOWNTO 0), -- 64 bit
+ avalon_st_tx_empty => tx_snk_in.empty(c_tech_mac_10g_empty_w-1 DOWNTO 0), -- 3 bit
+ avalon_st_tx_error => tx_snk_in.err(0), -- 1 bit std_logic = c_tech_mac_10g_tx_error_w
+ avalon_st_pause_data => (OTHERS=>'0'),
+
+ xgmii_tx => xgmii_tx_data, -- 72 bit
+
+ avalon_st_txstatus_valid => OPEN,
+ avalon_st_txstatus_data => OPEN,
+ avalon_st_txstatus_error => OPEN,
+
+ rx_312_5_clk => rx_clk_312,
+ rx_156_25_clk => rx_clk_156,
+ rx_rst_n => rx_rst_n,
+
+ xgmii_rx => xgmii_rx_data, -- 72 bit
+
+ avalon_st_rx_ready => rx_src_in.ready,
+ avalon_st_rx_startofpacket => avalon_rx_src_out.sop,
+ avalon_st_rx_endofpacket => avalon_rx_src_out.eop,
+ avalon_st_rx_valid => avalon_rx_src_out.valid,
+ avalon_st_rx_data => avalon_rx_src_out.data(c_xgmii_data_w-1 DOWNTO 0), -- 64 bit
+ avalon_st_rx_empty => avalon_rx_src_out.empty(c_tech_mac_10g_empty_w-1 DOWNTO 0), -- 3 bit
+ avalon_st_rx_error => avalon_rx_src_out.err(c_tech_mac_10g_rx_error_w-1 DOWNTO 0), -- 6 bit
+
+ avalon_st_rxstatus_valid => OPEN,
+ avalon_st_rxstatus_data => OPEN,
+ avalon_st_rxstatus_error => OPEN,
+
+ link_fault_status_xgmii_rx_data => xgmii_link_status, -- 0=ok, 1=local fault, 2=remote fault
+
+ unidirectional_en => OPEN,
+ unidirectional_remote_fault_dis => OPEN
+ );
+
+END str;
diff --git a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
index f88b2836c2344b2f226f9206d77fe4a5600ef8a1..fe4e87ff6f7bada17431e5bd4c1d056c42ec01da 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
@@ -242,6 +242,55 @@ PACKAGE tech_mac_10g_component_pkg IS
);
END COMPONENT;
+ ------------------------------------------------------------------------------
+ -- ip_arria10_e2sg
+ ------------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e2sg_mac_10g IS
+ PORT (
+ csr_read : in std_logic := '0'; -- csr.read
+ csr_write : in std_logic := '0'; -- .write
+ csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ csr_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ csr_waitrequest : out std_logic; -- .waitrequest
+ csr_address : in std_logic_vector(12 downto 0) := (others => '0'); -- .address
+ tx_312_5_clk : in std_logic := '0'; -- tx_312_5_clk.clk
+ tx_156_25_clk : in std_logic := '0'; -- tx_156_25_clk.clk
+ rx_312_5_clk : in std_logic := '0'; -- rx_312_5_clk.clk
+ rx_156_25_clk : in std_logic := '0'; -- rx_156_25_clk.clk
+ csr_clk : in std_logic := '0'; -- csr_clk.clk
+ csr_rst_n : in std_logic := '0'; -- csr_rst_n.reset_n
+ tx_rst_n : in std_logic := '0'; -- tx_rst_n.reset_n
+ rx_rst_n : in std_logic := '0'; -- rx_rst_n.reset_n
+ avalon_st_tx_startofpacket : in std_logic := '0'; -- avalon_st_tx.startofpacket
+ avalon_st_tx_endofpacket : in std_logic := '0'; -- .endofpacket
+ avalon_st_tx_valid : in std_logic := '0'; -- .valid
+ avalon_st_tx_data : in std_logic_vector(63 downto 0) := (others => '0'); -- .data
+ avalon_st_tx_empty : in std_logic_vector(2 downto 0) := (others => '0'); -- .empty
+ avalon_st_tx_error : in std_logic := '0'; -- .error
+ avalon_st_tx_ready : out std_logic; -- .ready
+ avalon_st_pause_data : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_st_pause.data
+ xgmii_tx : out std_logic_vector(71 downto 0); -- xgmii_tx.data
+ avalon_st_txstatus_valid : out std_logic; -- avalon_st_txstatus.valid
+ avalon_st_txstatus_data : out std_logic_vector(39 downto 0); -- .data
+ avalon_st_txstatus_error : out std_logic_vector(6 downto 0); -- .error
+ xgmii_rx : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_rx.data
+ link_fault_status_xgmii_rx_data : out std_logic_vector(1 downto 0); -- link_fault_status_xgmii_rx.data
+ avalon_st_rx_data : out std_logic_vector(63 downto 0); -- avalon_st_rx.data
+ avalon_st_rx_startofpacket : out std_logic; -- .startofpacket
+ avalon_st_rx_valid : out std_logic; -- .valid
+ avalon_st_rx_empty : out std_logic_vector(2 downto 0); -- .empty
+ avalon_st_rx_error : out std_logic_vector(5 downto 0); -- .error
+ avalon_st_rx_ready : in std_logic := '0'; -- .ready
+ avalon_st_rx_endofpacket : out std_logic; -- .endofpacket
+ avalon_st_rxstatus_valid : out std_logic; -- avalon_st_rxstatus.valid
+ avalon_st_rxstatus_data : out std_logic_vector(39 downto 0); -- .data
+ avalon_st_rxstatus_error : out std_logic_vector(6 downto 0); -- .error
+ unidirectional_en : out std_logic; -- unidirectional.en
+ unidirectional_remote_fault_dis : out std_logic -- .remote_fault_dis
+ );
+ END COMPONENT;
+
END tech_mac_10g_component_pkg;
PACKAGE BODY tech_mac_10g_component_pkg IS
@@ -254,6 +303,7 @@ PACKAGE BODY tech_mac_10g_component_pkg IS
WHEN c_tech_arria10 => v_csr_addr_w := 13; -- 13 with INSERT_CSR_ADAPTOR=1 in ip_arria10_mac_10g.qsys, 10 without
WHEN c_tech_arria10_e3sge3 => v_csr_addr_w := 13; -- 13 with INSERT_CSR_ADAPTOR=1 in ip_arria10_e3sge3_mac_10g.qsys, 10 without
WHEN c_tech_arria10_e1sg => v_csr_addr_w := 13; -- 13 with INSERT_CSR_ADAPTOR=1 in ip_arria10_e1sg_mac_10g.qsys, 10 without
+ WHEN c_tech_arria10_e2sg => v_csr_addr_w := 13; -- 13 with INSERT_CSR_ADAPTOR=1 in ip_arria10_e1sg_mac_10g.qsys, 10 without
WHEN OTHERS => v_csr_addr_w := 13; -- default to c_tech_stratixiv
END CASE;
RETURN v_csr_addr_w;
diff --git a/libraries/technology/memory/hdllib.cfg b/libraries/technology/memory/hdllib.cfg
index a2d022fb948a335770537c4f0637d76a68f18289..5aa87085c513250719d8033851aa05b327891ed3 100644
--- a/libraries/technology/memory/hdllib.cfg
+++ b/libraries/technology/memory/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = tech_memory
hdl_library_clause_name = tech_memory_lib
-hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram ip_arria10_e3sge3_ram ip_arria10_e1sg_ram
+hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram ip_arria10_e3sge3_ram ip_arria10_e1sg_ram ip_arria10_e2sg_ram
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -8,6 +8,7 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_ram ip_arria10_ram_lib
ip_arria10_e3sge3_ram ip_arria10_e3sge3_ram_lib
ip_arria10_e1sg_ram ip_arria10_e1sg_ram_lib
+ ip_arria10_e2sg_ram ip_arria10_e2sg_ram_lib
synth_files =
tech_memory_component_pkg.vhd
diff --git a/libraries/technology/memory/tech_memory_component_pkg.vhd b/libraries/technology/memory/tech_memory_component_pkg.vhd
index c3baad490670edfcb84fe1d70995e33024893f89..d0c4b1ebcd5ef4580e3e94a0661e92aad6afa539 100644
--- a/libraries/technology/memory/tech_memory_component_pkg.vhd
+++ b/libraries/technology/memory/tech_memory_component_pkg.vhd
@@ -422,4 +422,98 @@ PACKAGE tech_memory_component_pkg IS
);
END COMPONENT;
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e2sg
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e2sg_ram_crwk_crw IS
+ GENERIC (
+ g_adr_a_w : NATURAL := 5;
+ g_dat_a_w : NATURAL := 32;
+ g_adr_b_w : NATURAL := 4;
+ g_dat_b_w : NATURAL := 64;
+ g_nof_words_a : NATURAL := 2**5;
+ g_nof_words_b : NATURAL := 2**4;
+ g_rd_latency : NATURAL := 1; -- choose 1 or 2
+ g_init_file : STRING := "UNUSED"
+ );
+ PORT
+ (
+ address_a : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
+ address_b : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
+ clk_a : IN STD_LOGIC := '1';
+ clk_b : IN STD_LOGIC ;
+ data_a : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+ data_b : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
+ wren_a : IN STD_LOGIC := '0';
+ wren_b : IN STD_LOGIC := '0';
+ q_a : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+ q_b : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_ram_crw_crw IS
+ GENERIC (
+ g_inferred : BOOLEAN := FALSE;
+ g_adr_w : NATURAL := 5;
+ g_dat_w : NATURAL := 8;
+ g_nof_words : NATURAL := 2**5;
+ g_rd_latency : NATURAL := 1; -- choose 1 or 2
+ g_init_file : STRING := "UNUSED"
+ );
+ PORT
+ (
+ address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+ address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+ clk_a : IN STD_LOGIC := '1';
+ clk_b : IN STD_LOGIC ;
+ data_a : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ data_b : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ wren_a : IN STD_LOGIC := '0';
+ wren_b : IN STD_LOGIC := '0';
+ q_a : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ q_b : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_ram_cr_cw IS
+ GENERIC (
+ g_inferred : BOOLEAN := FALSE;
+ g_adr_w : NATURAL := 5;
+ g_dat_w : NATURAL := 8;
+ g_nof_words : NATURAL := 2**5;
+ g_rd_latency : NATURAL := 1; -- choose 1 or 2
+ g_init_file : STRING := "UNUSED"
+ );
+ PORT
+ (
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdaddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ wraddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+ wrclk : IN STD_LOGIC := '1';
+ wren : IN STD_LOGIC := '0';
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_ram_r_w IS
+ GENERIC (
+ g_inferred : BOOLEAN := FALSE;
+ g_adr_w : NATURAL := 5;
+ g_dat_w : NATURAL := 8;
+ g_nof_words : NATURAL := 2**5;
+ g_rd_latency : NATURAL := 1; -- choose 1 or 2
+ g_init_file : STRING := "UNUSED"
+ );
+ PORT (
+ clk : IN STD_LOGIC := '1';
+ data : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
+ rdaddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
+ wraddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
+ wren : IN STD_LOGIC := '0';
+ q : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
END tech_memory_component_pkg;
diff --git a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
index 412209602c24c27f2117369cba9311aec7612a56..342a964b8737673050135aec12b66cd544492667 100644
--- a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
@@ -30,6 +30,7 @@ LIBRARY ip_stratixiv_ram_lib;
LIBRARY ip_arria10_ram_lib;
LIBRARY ip_arria10_e3sge3_ram_lib;
LIBRARY ip_arria10_e1sg_ram_lib;
+LIBRARY ip_arria10_e2sg_ram_lib;
ENTITY tech_memory_ram_cr_cw IS
GENERIC (
@@ -80,5 +81,11 @@ BEGIN
GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
PORT MAP (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
END GENERATE;
+
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_ram_cr_cw
+ GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+ PORT MAP (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
+ END GENERATE;
END ARCHITECTURE;
diff --git a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
index 501da0de254848e0e6790f98daf4e880f5ee05fd..6e43a2d1284c055676f71c34f8dd053971c4f4c0 100644
--- a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
@@ -30,6 +30,7 @@ LIBRARY ip_stratixiv_ram_lib;
LIBRARY ip_arria10_ram_lib;
LIBRARY ip_arria10_e3sge3_ram_lib;
LIBRARY ip_arria10_e1sg_ram_lib;
+LIBRARY ip_arria10_e2sg_ram_lib;
ENTITY tech_memory_ram_crw_crw IS
GENERIC (
@@ -87,5 +88,11 @@ BEGIN
GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
END GENERATE;
-
+
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_ram_crw_crw
+ GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+ PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
index 78b4e5c68c6f630bd9cfa666a59dbf6f5138be74..802e6d8e8557b7920c24c7f406b60dbd1125823e 100644
--- a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
@@ -30,6 +30,7 @@ LIBRARY ip_stratixiv_ram_lib;
LIBRARY ip_arria10_ram_lib;
LIBRARY ip_arria10_e3sge3_ram_lib;
LIBRARY ip_arria10_e1sg_ram_lib;
+LIBRARY ip_arria10_e2sg_ram_lib;
ENTITY tech_memory_ram_crwk_crw IS -- support different port data widths and corresponding address ranges
GENERIC (
@@ -89,5 +90,11 @@ BEGIN
GENERIC MAP (g_adr_a_w, g_dat_a_w, g_adr_b_w, g_dat_b_w, g_nof_words_a, g_nof_words_b, g_rd_latency, g_init_file)
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
END GENERATE;
-
+
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_ram_crwk_crw
+ GENERIC MAP (g_adr_a_w, g_dat_a_w, g_adr_b_w, g_dat_b_w, g_nof_words_a, g_nof_words_b, g_rd_latency, g_init_file)
+ PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/memory/tech_memory_ram_r_w.vhd b/libraries/technology/memory/tech_memory_ram_r_w.vhd
index ca9222873dd9af1543f5a4c319eb3ffec9bf2b8b..54203fc4941920ac51f4e3008577d71c9578bc49 100644
--- a/libraries/technology/memory/tech_memory_ram_r_w.vhd
+++ b/libraries/technology/memory/tech_memory_ram_r_w.vhd
@@ -30,6 +30,7 @@ LIBRARY ip_stratixiv_ram_lib;
LIBRARY ip_arria10_ram_lib;
LIBRARY ip_arria10_e3sge3_ram_lib;
LIBRARY ip_arria10_e1sg_ram_lib;
+LIBRARY ip_arria10_e2sg_ram_lib;
ENTITY tech_memory_ram_r_w IS
GENERIC (
@@ -78,4 +79,10 @@ BEGIN
PORT MAP (clock, data, rdaddress, wraddress, wren, q);
END GENERATE;
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_ram_r_w
+ GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
+ PORT MAP (clock, data, rdaddress, wraddress, wren, q);
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/memory/tech_memory_rom_r.vhd b/libraries/technology/memory/tech_memory_rom_r.vhd
index 9f961d977bedb868fcf4f0d84cc2bc2112a27741..2fadf629885af98854f6bbc378b6b97df3ce9915 100644
--- a/libraries/technology/memory/tech_memory_rom_r.vhd
+++ b/libraries/technology/memory/tech_memory_rom_r.vhd
@@ -30,6 +30,7 @@ LIBRARY ip_stratixiv_ram_lib;
LIBRARY ip_arria10_ram_lib;
LIBRARY ip_arria10_e3sge3_ram_lib;
LIBRARY ip_arria10_e1sg_ram_lib;
+LIBRARY ip_arria10_e2sg_ram_lib;
ENTITY tech_memory_rom_r IS
GENERIC (
@@ -97,5 +98,19 @@ BEGIN
q => q
);
END GENERATE;
-
+
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ -- use ip_arria10_e1sg_ram_r_w as ROM
+ u0 : ip_arria10_e2sg_ram_r_w
+ GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
+ PORT MAP (
+ clk => clock,
+ --data => ,
+ rdaddress => address,
+ --wraddress => ,
+ --wren => ,
+ q => q
+ );
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/mult/hdllib.cfg b/libraries/technology/mult/hdllib.cfg
index 2b3f3f655d112e0fb00346756e14661765c577b1..5fbea82b38f96abd2a2e5925a89986fe90b01f0f 100644
--- a/libraries/technology/mult/hdllib.cfg
+++ b/libraries/technology/mult/hdllib.cfg
@@ -10,6 +10,9 @@ hdl_lib_uses_synth = common technology
ip_arria10_e3sge3_mult_add4
ip_arria10_e1sg_mult_add4
ip_arria10_e1sg_mult_add2
+ ip_arria10_e2sg_mult_add4
+ ip_arria10_e2sg_mult_add2
+ ip_arria10_e2sg_complex_mult
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -21,6 +24,9 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_mult_add4 ip_arria10_e3sge3_mult_add4_lib
ip_arria10_e1sg_mult_add4 ip_arria10_e1sg_mult_add4_lib
ip_arria10_e1sg_mult_add2 ip_arria10_e1sg_mult_add2_lib
+ ip_arria10_e2sg_mult_add4 ip_arria10_e2sg_mult_add4_lib
+ ip_arria10_e2sg_mult_add2 ip_arria10_e2sg_mult_add2_lib
+ ip_arria10_e2sg_complex_mult ip_arria10_e2sg_complex_mult_altmult_complex_194
synth_files =
diff --git a/libraries/technology/mult/tech_complex_mult.vhd b/libraries/technology/mult/tech_complex_mult.vhd
index 6432cf385e36cf90f7a7ee7e4911b6f6d039261f..680f89fb2ef4842278c785dd39318956bdbc8d57 100644
--- a/libraries/technology/mult/tech_complex_mult.vhd
+++ b/libraries/technology/mult/tech_complex_mult.vhd
@@ -32,6 +32,7 @@ LIBRARY ip_stratixiv_mult_lib;
--LIBRARY ip_arria10_mult_rtl_lib;
LIBRARY ip_arria10_complex_mult_altmult_complex_150;
LIBRARY ip_arria10_e1sg_complex_mult_altmult_complex_180;
+LIBRARY ip_arria10_e2sg_complex_mult_altmult_complex_194;
LIBRARY ip_arria10_complex_mult_rtl_lib;
LIBRARY ip_arria10_complex_mult_rtl_canonical_lib;
@@ -248,6 +249,34 @@ begin
END GENERATE;
+ gen_ip_arria10_e2sg_ip : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=c_tech_arria10_e2sg AND g_variant="IP") GENERATE
+
+ -- Adapt DSP input widths
+ ar <= RESIZE_SVEC(in_ar, c_dsp_dat_w);
+ ai <= RESIZE_SVEC(in_ai, c_dsp_dat_w);
+ br <= RESIZE_SVEC(in_br, c_dsp_dat_w);
+ bi <= RESIZE_SVEC(in_bi, c_dsp_dat_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_dat_w);
+
+
+ u0 : ip_arria10_e2sg_complex_mult
+ PORT MAP (
+ aclr => rst,
+ clock => clk,
+ dataa_imag => ai,
+ dataa_real => ar,
+ datab_imag => bi,
+ datab_real => br,
+ ena => clken,
+ result_imag => mult_im,
+ result_real => mult_re
+ );
+
+ -- Back to true input widths and then resize for output width
+ result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
+ result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
+
+ END GENERATE;
+
-------------------------------------------------------------------------------
-- Model: forward concatenated inputs to the 'result' output
--
diff --git a/libraries/technology/mult/tech_mult_add2.vhd b/libraries/technology/mult/tech_mult_add2.vhd
index 930dd258f22b743aeeea3c3f4280d8fbf579aadb..df55163ea2a967605ba6037e51a38574529409d1 100644
--- a/libraries/technology/mult/tech_mult_add2.vhd
+++ b/libraries/technology/mult/tech_mult_add2.vhd
@@ -29,6 +29,7 @@ USE work.tech_mult_component_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_mult_lib;
LIBRARY ip_arria10_e1sg_mult_add2_lib;
+LIBRARY ip_arria10_e2sg_mult_add2_lib;
ENTITY tech_mult_add2 IS
GENERIC (
@@ -107,5 +108,29 @@ begin
);
END GENERATE;
+ gen_ip_arria10_e2sg_rtl : IF (g_technology=c_tech_arria10_e2sg AND g_variant="RTL") GENERATE
+ u0 : ip_arria10_e2sg_mult_add2_rtl
+ GENERIC MAP(
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_res_w => g_res_w,
+ g_force_dsp => g_force_dsp,
+ g_add_sub => g_add_sub,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ PORT MAP(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ res => res
+ );
+ END GENERATE;
+
end str;
diff --git a/libraries/technology/mult/tech_mult_add4.vhd b/libraries/technology/mult/tech_mult_add4.vhd
index 434684633b40ecc2b474ad20ba3fab7501c2a7ed..b11d564997d1e60e65af881d56443c4d4f4cb81e 100644
--- a/libraries/technology/mult/tech_mult_add4.vhd
+++ b/libraries/technology/mult/tech_mult_add4.vhd
@@ -30,6 +30,7 @@ USE work.tech_mult_component_pkg.ALL;
LIBRARY ip_stratixiv_mult_lib;
LIBRARY ip_arria10_e3sge3_mult_add4_lib;
LIBRARY ip_arria10_e1sg_mult_add4_lib;
+LIBRARY ip_arria10_e2sg_mult_add4_lib;
ENTITY tech_mult_add4 IS
GENERIC (
@@ -140,5 +141,31 @@ begin
);
END GENERATE;
+ gen_ip_arria10_e2sg_rtl : IF (g_technology=c_tech_arria10_e2sg AND g_variant="RTL") GENERATE
+ u0 : ip_arria10_e2sg_mult_add4_rtl
+ GENERIC MAP(
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_res_w => g_res_w,
+ g_force_dsp => g_force_dsp,
+ g_add_sub0 => g_add_sub0,
+ g_add_sub1 => g_add_sub1,
+ g_add_sub => g_add_sub,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ PORT MAP(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ res => res
+ );
+ END GENERATE;
+
end str;
diff --git a/libraries/technology/mult/tech_mult_component_pkg.vhd b/libraries/technology/mult/tech_mult_component_pkg.vhd
index d04ed4e9e138205e731b9f5e027e95f88795f1b3..912d3ea189adbb09aa243f42717e6c01d2ebd9dc 100644
--- a/libraries/technology/mult/tech_mult_component_pkg.vhd
+++ b/libraries/technology/mult/tech_mult_component_pkg.vhd
@@ -360,4 +360,70 @@ PACKAGE tech_mult_component_pkg IS
result_imag : out std_logic_vector(35 downto 0) -- .result_imag
);
END COMPONENT;
+
+ -----------------------------------------------------------------------------
+ -- Arria 10 e2sg components
+ -----------------------------------------------------------------------------
+ COMPONENT ip_arria10_e2sg_mult_add2_rtl IS
+ GENERIC (
+ g_in_a_w : POSITIVE;
+ g_in_b_w : POSITIVE;
+ g_res_w : POSITIVE; -- g_in_a_w + g_in_b_w + log2(2)
+ g_force_dsp : BOOLEAN := TRUE; -- when TRUE resize input width to >= 18
+ g_add_sub : STRING := "ADD"; -- or "SUB"
+ g_nof_mult : INTEGER := 2; -- fixed
+ g_pipeline_input : NATURAL := 1; -- 0 or 1
+ g_pipeline_product : NATURAL := 0; -- 0 or 1
+ g_pipeline_adder : NATURAL := 1; -- 0 or 1
+ g_pipeline_output : NATURAL := 1 -- >= 0
+ );
+ PORT (
+ rst : IN STD_LOGIC := '0';
+ clk : IN STD_LOGIC;
+ clken : IN STD_LOGIC := '1';
+ in_a : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
+ in_b : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
+ res : OUT STD_LOGIC_VECTOR(g_res_w-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_mult_add4_rtl IS
+ GENERIC (
+ g_in_a_w : POSITIVE;
+ g_in_b_w : POSITIVE;
+ g_res_w : POSITIVE; -- g_in_a_w + g_in_b_w + log2(4)
+ g_force_dsp : BOOLEAN := TRUE; -- when TRUE resize input width to >= 18
+ g_add_sub0 : STRING := "ADD"; -- or "SUB"
+ g_add_sub1 : STRING := "ADD"; -- or "SUB"
+ g_add_sub : STRING := "ADD"; -- or "SUB" only available with rtl architecture
+ g_nof_mult : INTEGER := 4; -- fixed
+ g_pipeline_input : NATURAL := 1; -- 0 or 1
+ g_pipeline_product : NATURAL := 0; -- 0 or 1
+ g_pipeline_adder : NATURAL := 1; -- 0 or 1, first sum
+ g_pipeline_output : NATURAL := 1 -- >= 0, second sum and optional rounding
+ );
+ PORT (
+ rst : IN STD_LOGIC := '0';
+ clk : IN STD_LOGIC;
+ clken : IN STD_LOGIC := '1';
+ in_a : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
+ in_b : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
+ res : OUT STD_LOGIC_VECTOR(g_res_w-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_complex_mult is
+ PORT (
+ dataa_real : in std_logic_vector(17 downto 0) := (others => '0'); -- complex_input.dataa_real
+ dataa_imag : in std_logic_vector(17 downto 0) := (others => '0'); -- .dataa_imag
+ datab_real : in std_logic_vector(17 downto 0) := (others => '0'); -- .datab_real
+ datab_imag : in std_logic_vector(17 downto 0) := (others => '0'); -- .datab_imag
+ clock : in std_logic := '0'; -- .clk
+ aclr : in std_logic := '0'; -- .aclr
+ ena : in std_logic := '0'; -- .ena
+ result_real : out std_logic_vector(35 downto 0); -- complex_output.result_real
+ result_imag : out std_logic_vector(35 downto 0) -- .result_imag
+ );
+ END COMPONENT;
+
END tech_mult_component_pkg;
diff --git a/libraries/technology/pll/hdllib.cfg b/libraries/technology/pll/hdllib.cfg
index c7b3d55035279053a4c7be362f7ce4798e9d66c2..b91a8beeaf118fc6f33c72c989d68a9d09282543 100644
--- a/libraries/technology/pll/hdllib.cfg
+++ b/libraries/technology/pll/hdllib.cfg
@@ -5,6 +5,7 @@ hdl_lib_uses_ip = ip_stratixiv_pll ip_arria10_pll_clk200 ip_arri
ip_stratixiv_pll_clk25 ip_arria10_pll_clk25 ip_arria10_e3sge3_pll_clk25 ip_arria10_e1sg_pll_clk25
ip_arria10_pll_clk125 ip_arria10_e3sge3_pll_clk125 ip_arria10_e1sg_pll_clk125
ip_arria10_pll_xgmii_mac_clocks ip_arria10_e3sge3_pll_xgmii_mac_clocks ip_arria10_e1sg_pll_xgmii_mac_clocks
+ ip_arria10_e2sg_pll_clk200 ip_arria10_e2sg_pll_clk25 ip_arria10_e2sg_pll_clk125 ip_arria10_e2sg_pll_xgmii_mac_clocks
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -22,6 +23,10 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e1sg_pll_clk25 ip_arria10_e1sg_pll_clk25_altera_iopll_180
ip_arria10_e1sg_pll_clk125 ip_arria10_e1sg_pll_clk125_altera_iopll_180
ip_arria10_e1sg_pll_xgmii_mac_clocks ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_180
+ ip_arria10_e2sg_pll_clk200 ip_arria10_e2sg_pll_clk200_altera_iopll_194
+ ip_arria10_e2sg_pll_clk25 ip_arria10_e2sg_pll_clk25_altera_iopll_194
+ ip_arria10_e2sg_pll_clk125 ip_arria10_e2sg_pll_clk125_altera_iopll_194
+ ip_arria10_e2sg_pll_xgmii_mac_clocks ip_arria10_e2sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_194
synth_files =
tech_pll_component_pkg.vhd
diff --git a/libraries/technology/pll/tech_pll_clk125.vhd b/libraries/technology/pll/tech_pll_clk125.vhd
index df94261a8337360e01c8283d7079d38e92ef7c3d..fab5e6259a35cac787d14d1b21e7c94b843949e3 100644
--- a/libraries/technology/pll/tech_pll_clk125.vhd
+++ b/libraries/technology/pll/tech_pll_clk125.vhd
@@ -29,6 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
LIBRARY ip_arria10_pll_clk125_altera_iopll_150;
LIBRARY ip_arria10_e3sge3_pll_clk125_altera_iopll_151;
LIBRARY ip_arria10_e1sg_pll_clk125_altera_iopll_180;
+LIBRARY ip_arria10_e2sg_pll_clk125_altera_iopll_194;
ENTITY tech_pll_clk125 IS
GENERIC (
@@ -88,4 +89,17 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_pll_clk125
+ PORT MAP (
+ rst => areset,
+ refclk => inclk0,
+ outclk_0 => c0,
+ outclk_1 => c1,
+ outclk_2 => c2,
+ outclk_3 => c3,
+ locked => locked
+ );
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/pll/tech_pll_clk200.vhd b/libraries/technology/pll/tech_pll_clk200.vhd
index adf88609a918af520b4d93bea13a62c40d831313..1a38b8d778d7a3bb24e8ad623d293d95bbc45956 100644
--- a/libraries/technology/pll/tech_pll_clk200.vhd
+++ b/libraries/technology/pll/tech_pll_clk200.vhd
@@ -30,6 +30,7 @@ LIBRARY ip_stratixiv_pll_lib;
LIBRARY ip_arria10_pll_clk200_altera_iopll_150;
LIBRARY ip_arria10_e3sge3_pll_clk200_altera_iopll_151;
LIBRARY ip_arria10_e1sg_pll_clk200_altera_iopll_180;
+LIBRARY ip_arria10_e2sg_pll_clk200_altera_iopll_194;
ENTITY tech_pll_clk200 IS
GENERIC (
@@ -94,4 +95,16 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_pll_clk200
+ PORT MAP (
+ rst => areset,
+ refclk => inclk0,
+ outclk_0 => c0,
+ outclk_1 => c1,
+ outclk_2 => c2,
+ locked => locked
+ );
+ END GENERATE;
+
END ARCHITECTURE;
diff --git a/libraries/technology/pll/tech_pll_clk25.vhd b/libraries/technology/pll/tech_pll_clk25.vhd
index bfb242b469fe81c81b35920dc91ad24acb4aab02..68d5f876e3c6bd853e053a2abd63a9310f170455 100644
--- a/libraries/technology/pll/tech_pll_clk25.vhd
+++ b/libraries/technology/pll/tech_pll_clk25.vhd
@@ -30,6 +30,7 @@ LIBRARY ip_arria10_pll_clk25_altera_iopll_150;
LIBRARY ip_stratixiv_pll_clk25_lib;
LIBRARY ip_arria10_e3sge3_pll_clk25_altera_iopll_151;
LIBRARY ip_arria10_e1sg_pll_clk25_altera_iopll_180;
+LIBRARY ip_arria10_e2sg_pll_clk25_altera_iopll_194;
ENTITY tech_pll_clk25 IS
GENERIC (
@@ -90,6 +91,19 @@ BEGIN
);
END GENERATE;
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_pll_clk25
+ PORT MAP (
+ rst => areset,
+ refclk => inclk0,
+ outclk_0 => c0,
+ outclk_1 => c1,
+ outclk_2 => c2,
+ outclk_3 => c3,
+ locked => locked
+ );
+ END GENERATE;
+
gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
u0 : ip_stratixiv_pll_clk25
PORT MAP (
diff --git a/libraries/technology/pll/tech_pll_component_pkg.vhd b/libraries/technology/pll/tech_pll_component_pkg.vhd
index 99bc01b8029b24159d95c8a554f5602f9a354ab8..3eea0c5cc7ac2419fa8a4ab3bdfcdc0abdb5a607 100644
--- a/libraries/technology/pll/tech_pll_component_pkg.vhd
+++ b/libraries/technology/pll/tech_pll_component_pkg.vhd
@@ -283,6 +283,58 @@ PACKAGE tech_pll_component_pkg IS
);
END COMPONENT;
+ -----------------------------------------------------------------------------
+ -- ip_arria10_e2sg
+ -----------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e2sg_pll_xgmii_mac_clocks IS
+ PORT (
+ pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
+ pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
+ pll_locked : out std_logic; -- pll_locked.pll_locked
+ outclk0 : out std_logic; -- outclk0.clk
+ pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
+ outclk1 : out std_logic -- outclk1.clk
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_pll_clk200 IS
+ PORT
+ (
+ rst : IN STD_LOGIC := '0';
+ refclk : IN STD_LOGIC := '0';
+ outclk_0 : OUT STD_LOGIC ;
+ outclk_1 : OUT STD_LOGIC ;
+ outclk_2 : OUT STD_LOGIC ;
+ locked : OUT STD_LOGIC
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_pll_clk25 IS
+ PORT
+ (
+ rst : IN STD_LOGIC := '0';
+ refclk : IN STD_LOGIC := '0';
+ outclk_0 : OUT STD_LOGIC ;
+ outclk_1 : OUT STD_LOGIC ;
+ outclk_2 : OUT STD_LOGIC ;
+ outclk_3 : OUT STD_LOGIC ;
+ locked : OUT STD_LOGIC
+ );
+ END COMPONENT;
+
+ COMPONENT ip_arria10_e2sg_pll_clk125 IS
+ PORT
+ (
+ rst : IN STD_LOGIC := '0';
+ refclk : IN STD_LOGIC := '0';
+ outclk_0 : OUT STD_LOGIC ;
+ outclk_1 : OUT STD_LOGIC ;
+ outclk_2 : OUT STD_LOGIC ;
+ outclk_3 : OUT STD_LOGIC ;
+ locked : OUT STD_LOGIC
+ );
+ END COMPONENT;
END tech_pll_component_pkg;
diff --git a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
index ca3990942354cdc18be4a0cd19a240d9ea4239e8..674cb5379b1697ce7b32f48416e3947d8c4b8645 100644
--- a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
+++ b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
@@ -44,6 +44,7 @@ USE common_lib.common_pkg.ALL;
LIBRARY ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_150;
LIBRARY ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151;
LIBRARY ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_180;
+LIBRARY ip_arria10_e2sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_194;
ENTITY tech_pll_xgmii_mac_clocks IS
GENERIC (
@@ -104,6 +105,18 @@ BEGIN
outclk1 => i_clk_312
);
END GENERATE;
+
+ gen_ip_arria10_e2sg : IF g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ip_arria10_e2sg_pll_xgmii_mac_clocks
+ PORT MAP (
+ pll_refclk0 => refclk_644,
+ pll_powerdown => rst_in,
+ pll_locked => pll_locked,
+ outclk0 => i_clk_156,
+ pll_cal_busy => OPEN,
+ outclk1 => i_clk_312
+ );
+ END GENERATE;
pll_locked_n <= NOT pll_locked;
diff --git a/libraries/technology/tse/hdllib.cfg b/libraries/technology/tse/hdllib.cfg
index 56d098e9b3533ac82bf3ca1f5a8e95647d16d07a..72a5ce131ed6b2709cd31234ac31e6f8831a3181 100644
--- a/libraries/technology/tse/hdllib.cfg
+++ b/libraries/technology/tse/hdllib.cfg
@@ -5,6 +5,7 @@ hdl_lib_uses_ip = ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_gx
ip_arria10_tse_sgmii_lvds ip_arria10_tse_sgmii_gx
ip_arria10_e3sge3_tse_sgmii_lvds ip_arria10_e3sge3_tse_sgmii_gx
ip_arria10_e1sg_tse_sgmii_lvds ip_arria10_e1sg_tse_sgmii_gx
+ ip_arria10_e2sg_tse_sgmii_lvds ip_arria10_e2sg_tse_sgmii_gx
hdl_lib_uses_sim = tech_transceiver
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
@@ -16,6 +17,8 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_tse_sgmii_gx ip_arria10_e3sge3_tse_sgmii_gx_altera_eth_tse_151
ip_arria10_e1sg_tse_sgmii_lvds ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_180
ip_arria10_e1sg_tse_sgmii_gx ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_180
+ ip_arria10_e2sg_tse_sgmii_lvds ip_arria10_e2sg_tse_sgmii_lvds_altera_eth_tse_180
+ ip_arria10_e2sg_tse_sgmii_gx ip_arria10_e2sg_tse_sgmii_gx_altera_eth_tse_180
synth_files =
tech_tse_component_pkg.vhd
@@ -24,6 +27,7 @@ synth_files =
tech_tse_arria10.vhd
tech_tse_arria10_e3sge3.vhd
tech_tse_arria10_e1sg.vhd
+ tech_tse_arria10_e2sg.vhd
tech_tse.vhd
tb_tech_tse_pkg.vhd
diff --git a/libraries/technology/tse/tb_tech_tse_pkg.vhd b/libraries/technology/tse/tb_tech_tse_pkg.vhd
index 8cc33151b6020b5b72993a8941f413b83dfda008..801e1082466eed682da0c135674a34c1ab5c7d82 100644
--- a/libraries/technology/tse/tb_tech_tse_pkg.vhd
+++ b/libraries/technology/tse/tb_tech_tse_pkg.vhd
@@ -146,6 +146,7 @@ PACKAGE BODY tb_tech_tse_pkg IS
WHEN c_tech_arria10 => proc_tech_tse_setup_arria10(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi);
WHEN c_tech_arria10_e3sge3 => proc_tech_tse_setup_arria10(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi);
WHEN c_tech_arria10_e1sg => proc_tech_tse_setup_arria10(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi);
+ WHEN c_tech_arria10_e2sg => proc_tech_tse_setup_arria10(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi);
WHEN OTHERS => proc_tech_tse_setup_stratixiv(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi); -- default to c_tech_stratixiv
END CASE;
END proc_tech_tse_setup;
diff --git a/libraries/technology/tse/tech_tse.vhd b/libraries/technology/tse/tech_tse.vhd
index 49c6180925a05a56302b8eb6f9c970a6d4882b46..2afb13310bedc7f45b639377ae86dce758164165 100644
--- a/libraries/technology/tse/tech_tse.vhd
+++ b/libraries/technology/tse/tech_tse.vhd
@@ -176,6 +176,19 @@ BEGIN
tse_led);
END GENERATE;
+ gen_ip_arria10_e2sg : IF c_use_technology=TRUE AND g_technology=c_tech_arria10_e2sg GENERATE
+ u0 : ENTITY work.tech_tse_arria10_e2sg
+ GENERIC MAP (g_ETH_PHY)
+ PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk,
+ mm_sla_in, mm_sla_out,
+ tx_snk_in, tx_snk_out,
+ tx_mac_in, tx_mac_out,
+ rx_src_in, rx_src_out,
+ rx_mac_out,
+ eth_txp, eth_rxp,
+ tse_led);
+ END GENERATE;
+
gen_sim_tse : IF c_use_sim_model=TRUE GENERATE
u_sim_tse : sim_tse
GENERIC MAP (g_sim_tx, g_sim_rx)
diff --git a/libraries/technology/tse/tech_tse_arria10_e2sg.vhd b/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..33de3adfe220d659202f0342d301475c837610ca
--- /dev/null
+++ b/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
@@ -0,0 +1,256 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE work.tech_tse_component_pkg.ALL;
+USE work.tech_tse_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_arria10_e2sg_tse_sgmii_lvds_altera_eth_tse_180;
+LIBRARY ip_arria10_e2sg_tse_sgmii_gx_altera_eth_tse_180;
+
+ENTITY tech_tse_arria10_e2sg IS
+ GENERIC (
+ g_ETH_PHY : STRING := "LVDS" -- "LVDS" (default): uses LVDS IOs for ctrl_unb2_board, "XCVR": uses tranceiver PHY
+ );
+ PORT (
+ -- Clocks and reset
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ eth_clk : IN STD_LOGIC;
+ tx_snk_clk : IN STD_LOGIC;
+ rx_src_clk : IN STD_LOGIC;
+
+ -- Memory Mapped Slave
+ mm_sla_in : IN t_mem_mosi;
+ mm_sla_out : OUT t_mem_miso;
+
+ -- MAC transmit interface
+ -- . ST sink
+ tx_snk_in : IN t_dp_sosi;
+ tx_snk_out : OUT t_dp_siso;
+ -- . MAC specific
+ tx_mac_in : IN t_tech_tse_tx_mac;
+ tx_mac_out : OUT t_tech_tse_tx_mac;
+
+ -- MAC receive interface
+ -- . ST Source
+ rx_src_in : IN t_dp_siso;
+ rx_src_out : OUT t_dp_sosi;
+ -- . MAC specific
+ rx_mac_out : OUT t_tech_tse_rx_mac;
+
+ -- PHY interface
+ eth_txp : OUT STD_LOGIC;
+ eth_rxp : IN STD_LOGIC;
+
+ tse_led : OUT t_tech_tse_led
+ );
+END tech_tse_arria10_e2sg;
+
+ARCHITECTURE str OF tech_tse_arria10_e2sg IS
+
+ SIGNAL ff_tx_mod : STD_LOGIC_VECTOR(c_tech_tse_empty_w-1 DOWNTO 0);
+
+ SIGNAL ff_rx_out : t_dp_sosi := c_dp_sosi_rst;
+
+BEGIN
+
+ -- Default frame level flow control
+ tx_snk_out.xon <= '1';
+
+ -- Force empty = 0 when eop = '0' to avoid TSE MAC bug of missing two bytes when empty = 2 (observed with v9.1)
+ ff_tx_mod <= tx_snk_in.empty(c_tech_tse_empty_w-1 DOWNTO 0) WHEN tx_snk_in.eop='1' ELSE (OTHERS=>'0');
+
+ -- Force unused bits and fields in rx_src_out to c_dp_sosi_rst to avoid confusing 'X' in wave window
+ rx_src_out <= ff_rx_out;
+
+ u_LVDS_tse: IF g_ETH_PHY = "LVDS" GENERATE
+
+ u_tse : ip_arria10_e2sg_tse_sgmii_lvds
+ -- The tse_sgmii_lvds needs to be regenerated if its parameters are changed.
+ -- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
+ -- . ENABLE_SUP_ADDR = 0 : An extra MAC addresses can e.g. be used as service MAC for tests
+ -- . ENA_HASH = 0 : A multi cast hash table can be used to address all nodes at once
+ -- . STAT_CNT_ENA = 0 : PHY statistics counts are useful for monitoring, but not realy needed
+ -- . EG_FIFO = 256 : Tx FIFO depth in nof 32 bit words (256 --> 1 M9K)
+ -- . ING_FIFO = 256 : Rx FIFO depth in nof 32 bit words (256 --> 1 M9K)
+ -- . ENABLE_SGMII = 0 : PHY access 1000BASE-X
+ PORT MAP (
+ -- MAC transmit interface
+ -- . Avalon ST
+ ff_tx_clk => tx_snk_clk,
+ ff_tx_rdy => tx_snk_out.ready,
+ ff_tx_data => tx_snk_in.data(c_tech_tse_data_w-1 DOWNTO 0),
+ ff_tx_wren => tx_snk_in.valid,
+ ff_tx_sop => tx_snk_in.sop,
+ ff_tx_eop => tx_snk_in.eop,
+ ff_tx_mod => ff_tx_mod,
+ ff_tx_err => tx_snk_in.err(0),
+ -- . MAC specific
+ ff_tx_crc_fwd => tx_mac_in.crc_fwd, -- when '0' MAC inserts CRC32 after eop
+ ff_tx_septy => tx_mac_out.septy, -- when '0' then tx FIFO goes above section-empty threshold
+ ff_tx_a_full => tx_mac_out.a_full, -- when '1' then tx FIFO goes above almost-full threshold
+ ff_tx_a_empty => tx_mac_out.a_empty, -- when '1' then tx FIFO goes below almost-empty threshold
+ tx_ff_uflow => tx_mac_out.uflow, -- when '1' then tx FIFO underflow
+ -- MAC receive interface
+ -- . Avalon ST
+ ff_rx_clk => rx_src_clk,
+ ff_rx_rdy => rx_src_in.ready,
+ ff_rx_data => ff_rx_out.data(c_tech_tse_data_w-1 DOWNTO 0),
+ ff_rx_dval => ff_rx_out.valid,
+ ff_rx_sop => ff_rx_out.sop,
+ ff_rx_eop => ff_rx_out.eop,
+ ff_rx_mod => ff_rx_out.empty(c_tech_tse_empty_w-1 DOWNTO 0),
+ rx_err => ff_rx_out.err(c_tech_tse_error_w-1 DOWNTO 0), -- [5] collision error (can only occur in half duplex mode)
+ -- [4] PHY error on GMII
+ -- [3] receive frame truncated due to FIFO overflow
+ -- [2] CRC-32 error
+ -- [1] invalid length
+ -- [0] = OR of [1:5]
+ -- . MAC specific
+ rx_err_stat => rx_mac_out.ethertype, -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
+ rx_frm_type => rx_mac_out.frm_type, -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
+ ff_rx_dsav => rx_mac_out.dsav, -- rx frame available, but not necessarily a complete frame
+ ff_rx_a_full => rx_mac_out.a_full, -- when '1' then rx FIFO goes above almost-full threshold
+ ff_rx_a_empty => rx_mac_out.a_empty, -- when '1' then rx FIFO goes below almost-empty threshold
+ -- Reset
+ reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
+ -- MM control interface
+ clk => mm_clk,
+ reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+ reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
+ reg_rd => mm_sla_in.rd,
+ reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
+ reg_wr => mm_sla_in.wr,
+ reg_busy => mm_sla_out.waitrequest,
+ -- Status LEDs
+ led_an => tse_led.an, -- '1' = autonegation completed
+ led_link => tse_led.link, -- '1' = successful link synchronisation
+ led_disp_err => tse_led.disp_err, -- TBI character error
+ led_char_err => tse_led.char_err, -- TBI disparity error
+ -- crs and col are only available with the SGMII bridge
+ led_crs => tse_led.crs, -- carrier sense '1' when there is tx/rx activity on the line
+ led_col => tse_led.col, -- tx collision detected (always '0' for full duplex)
+ -- Serial 1.25 Gbps
+ rx_recovclkout => OPEN,
+ ref_clk => eth_clk,
+ txp => eth_txp,
+ rxp => eth_rxp
+ );
+
+ END GENERATE;
+
+ u_XCVR_tse: IF g_ETH_PHY = "XCVR" GENERATE
+
+ u_tse : ip_arria10_e2sg_tse_sgmii_gx
+ -- The tse_sgmii_xcvr needs to be regenerated if its parameters are changed.
+ -- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
+ -- . ENABLE_SUP_ADDR = 0 : An extra MAC addresses can e.g. be used as service MAC for tests
+ -- . ENA_HASH = 0 : A multi cast hash table can be used to address all nodes at once
+ -- . STAT_CNT_ENA = 0 : PHY statistics counts are useful for monitoring, but not realy needed
+ -- . EG_FIFO = 2048 : Tx FIFO depth in nof 32 bit words (2048 --> 4 M9K)
+ -- . ING_FIFO = 2048 : Rx FIFO depth in nof 32 bit words (2048 --> 4 M9K)
+ -- . ENABLE_SGMII = 0 : PHY access 1000BASE-X
+ PORT MAP (
+ -- MAC transmit interface
+ -- . Avalon ST
+ ff_tx_clk => tx_snk_clk,
+ ff_tx_rdy => tx_snk_out.ready,
+ ff_tx_data => tx_snk_in.data(c_tech_tse_data_w-1 DOWNTO 0),
+ ff_tx_wren => tx_snk_in.valid,
+ ff_tx_sop => tx_snk_in.sop,
+ ff_tx_eop => tx_snk_in.eop,
+ ff_tx_mod => ff_tx_mod,
+ ff_tx_err => tx_snk_in.err(0),
+ -- . MAC specific
+ ff_tx_crc_fwd => tx_mac_in.crc_fwd, -- when '0' MAC inserts CRC32 after eop
+ ff_tx_septy => tx_mac_out.septy, -- when '0' then tx FIFO goes above section-empty threshold
+ ff_tx_a_full => tx_mac_out.a_full, -- when '1' then tx FIFO goes above almost-full threshold
+ ff_tx_a_empty => tx_mac_out.a_empty, -- when '1' then tx FIFO goes below almost-empty threshold
+ tx_ff_uflow => tx_mac_out.uflow, -- when '1' then tx FIFO underflow
+ -- MAC receive interface
+ -- . Avalon ST
+ ff_rx_clk => rx_src_clk,
+ ff_rx_rdy => rx_src_in.ready,
+ ff_rx_data => ff_rx_out.data(c_tech_tse_data_w-1 DOWNTO 0),
+ ff_rx_dval => ff_rx_out.valid,
+ ff_rx_sop => ff_rx_out.sop,
+ ff_rx_eop => ff_rx_out.eop,
+ ff_rx_mod => ff_rx_out.empty(c_tech_tse_empty_w-1 DOWNTO 0),
+ rx_err => ff_rx_out.err(c_tech_tse_error_w-1 DOWNTO 0), -- [5] collision error (can only occur in half duplex mode)
+ -- [4] PHY error on GMII
+ -- [3] receive frame truncated due to FIFO overflow
+ -- [2] CRC-32 error
+ -- [1] invalid length
+ -- [0] = OR of [1:5]
+ -- . MAC specific
+ rx_err_stat => rx_mac_out.ethertype, -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
+ rx_frm_type => rx_mac_out.frm_type, -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
+ ff_rx_dsav => rx_mac_out.dsav, -- rx frame available, but not necessarily a complete frame
+ ff_rx_a_full => rx_mac_out.a_full, -- when '1' then rx FIFO goes above almost-full threshold
+ ff_rx_a_empty => rx_mac_out.a_empty, -- when '1' then rx FIFO goes below almost-empty threshold
+ -- Reset
+ reset => mm_rst, -- asynchronous reset (choose synchronous to mm_clk)
+ -- MM control interface
+ clk => mm_clk,
+ reg_addr => mm_sla_in.address(c_tech_tse_byte_addr_w-1 DOWNTO 2),
+ reg_data_out => mm_sla_out.rddata(c_tech_tse_data_w-1 DOWNTO 0),
+ reg_rd => mm_sla_in.rd,
+ reg_data_in => mm_sla_in.wrdata(c_tech_tse_data_w-1 DOWNTO 0),
+ reg_wr => mm_sla_in.wr,
+ reg_busy => mm_sla_out.waitrequest,
+ -- Status LEDs
+ led_an => tse_led.an, -- '1' = autonegation completed
+ led_link => tse_led.link, -- '1' = successful link synchronisation
+ led_disp_err => tse_led.disp_err, -- TBI character error
+ led_char_err => tse_led.char_err, -- TBI disparity error
+ -- crs and col are only available with the SGMII bridge
+ led_crs => tse_led.crs, -- carrier sense '1' when there is tx/rx activity on the line
+ led_col => tse_led.col, -- tx collision detected (always '0' for full duplex)
+ -- Serial 1.25 Gbps
+ rx_recovclkout => OPEN,
+ ref_clk => eth_clk,
+ txp => eth_txp,
+ rxp => eth_rxp,
+
+ -- GX connections ????
+ tx_serial_clk => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk.clk
+ rx_cdr_refclk => '0', -- : in std_logic := '0'; -- rx_cdr_refclk.clk
+ tx_analogreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_digitalreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ rx_analogreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_digitalreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ tx_cal_busy => OPEN, -- : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
+ rx_cal_busy => OPEN, -- : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_set_locktodata => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktodata.rx_set_locktodata
+ rx_set_locktoref => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktoref.rx_set_locktoref
+ rx_is_lockedtoref => OPEN, -- : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtodata => OPEN -- : out std_logic_vector(0 downto 0) -- rx_is_lockedtodata.rx_is_lockedtodata
+ );
+
+ END GENERATE;
+
+END str;
diff --git a/libraries/technology/tse/tech_tse_component_pkg.vhd b/libraries/technology/tse/tech_tse_component_pkg.vhd
index 64cac8c994213b141addda3a35238437cc8be30b..ec3f497a8e67769cbc0c51efbf08f6a2cabc4ae7 100644
--- a/libraries/technology/tse/tech_tse_component_pkg.vhd
+++ b/libraries/technology/tse/tech_tse_component_pkg.vhd
@@ -497,4 +497,120 @@ PACKAGE tech_tse_component_pkg IS
);
END COMPONENT;
+ ------------------------------------------------------------------------------
+ -- ip_arria10_e2sg
+ ------------------------------------------------------------------------------
+
+ COMPONENT ip_arria10_e2sg_tse_sgmii_lvds IS
+ PORT (
+ reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
+ reg_rd : in std_logic := '0'; -- .read
+ reg_data_in : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reg_wr : in std_logic := '0'; -- .write
+ reg_busy : out std_logic; -- .waitrequest
+ reg_addr : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
+ clk : in std_logic := '0'; -- control_port_clock_connection.clk
+ ff_tx_crc_fwd : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd
+ ff_tx_septy : out std_logic; -- .ff_tx_septy
+ tx_ff_uflow : out std_logic; -- .tx_ff_uflow
+ ff_tx_a_full : out std_logic; -- .ff_tx_a_full
+ ff_tx_a_empty : out std_logic; -- .ff_tx_a_empty
+ rx_err_stat : out std_logic_vector(17 downto 0); -- .rx_err_stat
+ rx_frm_type : out std_logic_vector(3 downto 0); -- .rx_frm_type
+ ff_rx_dsav : out std_logic; -- .ff_rx_dsav
+ ff_rx_a_full : out std_logic; -- .ff_rx_a_full
+ ff_rx_a_empty : out std_logic; -- .ff_rx_a_empty
+ ref_clk : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
+ ff_rx_data : out std_logic_vector(31 downto 0); -- receive.data
+ ff_rx_eop : out std_logic; -- .endofpacket
+ rx_err : out std_logic_vector(5 downto 0); -- .error
+ ff_rx_mod : out std_logic_vector(1 downto 0); -- .empty
+ ff_rx_rdy : in std_logic := '0'; -- .ready
+ ff_rx_sop : out std_logic; -- .startofpacket
+ ff_rx_dval : out std_logic; -- .valid
+ ff_rx_clk : in std_logic := '0'; -- receive_clock_connection.clk
+ reset : in std_logic := '0'; -- reset_connection.reset
+ rx_recovclkout : out std_logic; -- serdes_control_connection.export
+ rxp : in std_logic := '0'; -- serial_connection.rxp_0
+ txp : out std_logic; -- .txp_0
+ led_crs : out std_logic; -- status_led_connection.crs
+ led_link : out std_logic; -- .link
+ led_col : out std_logic; -- .col
+ led_an : out std_logic; -- .an
+ led_char_err : out std_logic; -- .char_err
+ led_disp_err : out std_logic; -- .disp_err
+ ff_tx_data : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
+ ff_tx_eop : in std_logic := '0'; -- .endofpacket
+ ff_tx_err : in std_logic := '0'; -- .error
+ ff_tx_mod : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
+ ff_tx_rdy : out std_logic; -- .ready
+ ff_tx_sop : in std_logic := '0'; -- .startofpacket
+ ff_tx_wren : in std_logic := '0'; -- .valid
+ ff_tx_clk : in std_logic := '0' -- transmit_clock_connection.clk
+ );
+ END COMPONENT;
+
+
+ COMPONENT ip_arria10_e2sg_tse_sgmii_gx IS
+ PORT (
+ reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
+ reg_rd : in std_logic := '0'; -- .read
+ reg_data_in : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reg_wr : in std_logic := '0'; -- .write
+ reg_busy : out std_logic; -- .waitrequest
+ reg_addr : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
+ clk : in std_logic := '0'; -- control_port_clock_connection.clk
+ ff_tx_crc_fwd : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd
+ ff_tx_septy : out std_logic; -- .ff_tx_septy
+ tx_ff_uflow : out std_logic; -- .tx_ff_uflow
+ ff_tx_a_full : out std_logic; -- .ff_tx_a_full
+ ff_tx_a_empty : out std_logic; -- .ff_tx_a_empty
+ rx_err_stat : out std_logic_vector(17 downto 0); -- .rx_err_stat
+ rx_frm_type : out std_logic_vector(3 downto 0); -- .rx_frm_type
+ ff_rx_dsav : out std_logic; -- .ff_rx_dsav
+ ff_rx_a_full : out std_logic; -- .ff_rx_a_full
+ ff_rx_a_empty : out std_logic; -- .ff_rx_a_empty
+ ref_clk : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
+ ff_rx_data : out std_logic_vector(31 downto 0); -- receive.data
+ ff_rx_eop : out std_logic; -- .endofpacket
+ rx_err : out std_logic_vector(5 downto 0); -- .error
+ ff_rx_mod : out std_logic_vector(1 downto 0); -- .empty
+ ff_rx_rdy : in std_logic := '0'; -- .ready
+ ff_rx_sop : out std_logic; -- .startofpacket
+ ff_rx_dval : out std_logic; -- .valid
+ ff_rx_clk : in std_logic := '0'; -- receive_clock_connection.clk
+ reset : in std_logic := '0'; -- reset_connection.reset
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cdr_refclk : in std_logic := '0'; -- rx_cdr_refclk.clk
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtoref : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_set_locktodata : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktodata.rx_set_locktodata
+ rx_set_locktoref : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktoref.rx_set_locktoref
+ rx_recovclkout : out std_logic; -- serdes_control_connection.export
+ rxp : in std_logic := '0'; -- serial_connection.rxp
+ txp : out std_logic; -- .txp
+ led_crs : out std_logic; -- status_led_connection.crs
+ led_link : out std_logic; -- .link
+ led_panel_link : out std_logic; -- .panel_link
+ led_col : out std_logic; -- .col
+ led_an : out std_logic; -- .an
+ led_char_err : out std_logic; -- .char_err
+ led_disp_err : out std_logic; -- .disp_err
+ ff_tx_data : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
+ ff_tx_eop : in std_logic := '0'; -- .endofpacket
+ ff_tx_err : in std_logic := '0'; -- .error
+ ff_tx_mod : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
+ ff_tx_rdy : out std_logic; -- .ready
+ ff_tx_sop : in std_logic := '0'; -- .startofpacket
+ ff_tx_wren : in std_logic := '0'; -- .valid
+ ff_tx_clk : in std_logic := '0'; -- transmit_clock_connection.clk
+ tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_serial_clk : in std_logic_vector(0 downto 0) := (others => '0') -- tx_serial_clk.clk
+ );
+ END COMPONENT;
+
END tech_tse_component_pkg;