diff --git a/applications/disturb2/designs/disturb2_unb2b_station/disturb2_unb2b_station.fpga.yaml b/applications/disturb2/designs/disturb2_unb2b_station/disturb2_unb2b_station.fpga.yaml
index 4c3d100037965c843061c117c765da482d11f2f6..3b87d372e2899767bff5cf243cbd0e18521dfada 100644
--- a/applications/disturb2/designs/disturb2_unb2b_station/disturb2_unb2b_station.fpga.yaml
+++ b/applications/disturb2/designs/disturb2_unb2b_station/disturb2_unb2b_station.fpga.yaml
@@ -21,6 +21,7 @@ parameters:
- { name: c_N_taps, value: 16 }
- { name: c_W_adc_jesd, value: 16 }
- { name: c_W_adc, value: 14 }
+ - { name: c_V_oversample, value: 2 }
- { name: c_V_sample_delay, value: 4096 }
- { name: c_V_si_db_large, value: 131072 }
- { name: c_V_si_db, value: 1024 }
@@ -204,7 +205,8 @@ peripherals:
- REG_SI
- peripheral_name: filter/fil_ppf_w
- number_of_peripherals: 2 # Disturb uses 2x oversample
+ number_of_peripherals: c_V_oversample # Disturb uses 2x oversample
+ peripheral_span: ceil_pow2(c_N_taps) * ceil_pow2(c_N_fft) * MM_BUS_SIZE # number_of_ports = ceil_pow2(c_N_taps), mm_port_span = ceil_pow2(c_N_fft) words
parameter_overrides:
- { name: g_fil_ppf.wb_factor, value: 1 } # process at sample rate (so no parallel wideband factor)
- { name: g_fil_ppf.nof_chan, value: 0 } # process at sample rate (so no serial time multiplexing)
@@ -217,7 +219,7 @@ peripherals:
- peripheral_name: sdp/sdp_subband_equalizer
parameter_overrides:
- - { name: P_pfb, value: 12} # DISTURB uses 2x oversample so 2 X P_pfb
+ - { name: P_pfb, value: c_V_oversample * c_P_pfb} # DISTURB uses 2x oversample so 2 X P_pfb
mm_port_names:
- RAM_EQUALIZER_GAINS
@@ -227,7 +229,7 @@ peripherals:
- peripheral_name: st/st_sst_for_sdp
parameter_overrides:
- - { name: g_nof_instances, value: 12} # DISTURB uses 2x oversample so 2 X P_pfb
+ - { name: g_nof_instances, value: c_V_oversample * c_P_pfb} # DISTURB uses 2x oversample so 2 X P_pfb
mm_port_names:
- RAM_ST_SST
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
index 26b558380e9ab0e708215833ce0cd40961af3a32..1124ffd4312c183c8e2b2d48dfb916ed410d027a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
@@ -21,6 +21,7 @@ parameters:
- { name: c_N_taps, value: 16 }
- { name: c_W_adc_jesd, value: 16 }
- { name: c_W_adc, value: 14 }
+ - { name: c_V_oversample, value: 2 }
- { name: c_V_sample_delay, value: 4096 }
- { name: c_V_si_db_large, value: 131072 }
- { name: c_V_si_db, value: 1024 }
@@ -202,6 +203,8 @@ peripherals:
- REG_SI
- peripheral_name: filter/fil_ppf_w
+ number_of_peripherals: c_V_oversample # Disturb uses 2x oversample
+ peripheral_span: ceil_pow2(c_N_taps) * ceil_pow2(c_N_fft) * MM_BUS_SIZE # number_of_ports = ceil_pow2(c_N_taps), mm_port_span = ceil_pow2(c_N_fft) words
parameter_overrides:
- { name: g_fil_ppf.wb_factor, value: 1 } # process at sample rate (so no parallel wideband factor)
- { name: g_fil_ppf.nof_chan, value: 0 } # process at sample rate (so no serial time multiplexing)
@@ -213,6 +216,8 @@ peripherals:
- RAM_FIL_COEFS
- peripheral_name: sdp/sdp_subband_equalizer
+ parameter_overrides:
+ - { name: P_pfb, value: c_V_oversample * c_P_pfb} # DISTURB uses 2x oversample so 2 X P_pfb
mm_port_names:
- RAM_EQUALIZER_GAINS
@@ -221,6 +226,8 @@ peripherals:
- REG_DP_SELECTOR # input_select = 0 for weighted subbands, input_select = 1 for raw subbands
- peripheral_name: st/st_sst_for_sdp
+ parameter_overrides:
+ - { name: g_nof_instances, value: c_V_oversample * c_P_pfb} # DISTURB uses 2x oversample so 2 X P_pfb
mm_port_names:
- RAM_ST_SST
@@ -402,7 +409,6 @@ peripherals:
peripheral_group: ring_rx_bf
number_of_peripherals: c_N_beamsets
peripheral_span: 8 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 8 words
-
parameter_overrides:
- { name: g_nof_streams, value: 1 }
mm_port_names:
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
index fbf1e8fd680cc4ff94fc06d857891e7fac4bb5bc..345943be8f39b4e11a090ec7faf4c248d54e1a9f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10C400' end='0x10C500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10C500' end='0x10C600' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C600' end='0x10C680' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C680' end='0x10C700' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C700' end='0x10C780' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C800' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C840' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C880' end='0x10C8C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C8C0' end='0x10C900' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C900' end='0x10C940' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C940' end='0x10C980' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C980' end='0x10C9C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C9C0' end='0x10CA00' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10CA00' end='0x10CA20' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10CA20' end='0x10CA40' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CA40' end='0x10CA60' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10CA60' end='0x10CA80' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10CA80' end='0x10CAA0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10CAA0' end='0x10CAC0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10CAC0' end='0x10CAE0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10CAE0' end='0x10CB00' datawidth='32' /><slave name='reg_epcs.mem' start='0x10CB00' end='0x10CB20' datawidth='32' /><slave name='reg_remu.mem' start='0x10CB20' end='0x10CB40' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10CB40' end='0x10CB50' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10CB50' end='0x10CB60' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10CB60' end='0x10CB70' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10CB70' end='0x10CB80' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10CB80' end='0x10CB90' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10CB90' end='0x10CBA0' datawidth='32' /><slave name='pio_pps.mem' start='0x10CBA0' end='0x10CBB0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10CBB0' end='0x10CBB8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10CBB8' end='0x10CBC0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10CBC0' end='0x10CBC8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10CBC8' end='0x10CBD0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10CBD0' end='0x10CBD8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10CBD8' end='0x10CBE0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10CBE0' end='0x10CBE8' datawidth='32' /><slave name='reg_si.mem' start='0x10CBE8' end='0x10CBF0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10CBF0' end='0x10CBF8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10CBF8' end='0x10CC00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CC00' end='0x10CC08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CC08' end='0x10CC10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CC10' end='0x10CC18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xE0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xE0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x110000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x110000' end='0x120000' datawidth='32' /><slave name='ram_wg.mem' start='0x120000' end='0x130000' datawidth='32' /><slave name='jesd204b.mem' start='0x130000' end='0x134000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x134000' end='0x134200' datawidth='32' /><slave name='reg_wg.mem' start='0x134200' end='0x134300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x134300' end='0x134400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x134400' end='0x134500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x134500' end='0x134600' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x134600' end='0x134680' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x134680' end='0x134700' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x134700' end='0x134780' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x134780' end='0x1347C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x1347C0' end='0x134800' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x134800' end='0x134840' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x134840' end='0x134880' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x134880' end='0x1348C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x1348C0' end='0x134900' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x134900' end='0x134940' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x134940' end='0x134980' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x134980' end='0x1349C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x1349C0' end='0x134A00' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x134A00' end='0x134A20' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x134A20' end='0x134A40' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x134A40' end='0x134A60' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x134A60' end='0x134A80' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x134A80' end='0x134AA0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x134AA0' end='0x134AC0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x134AC0' end='0x134AE0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x134AE0' end='0x134B00' datawidth='32' /><slave name='reg_epcs.mem' start='0x134B00' end='0x134B20' datawidth='32' /><slave name='reg_remu.mem' start='0x134B20' end='0x134B40' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x134B40' end='0x134B50' datawidth='32' /><slave name='reg_ring_info.mem' start='0x134B50' end='0x134B60' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x134B60' end='0x134B70' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x134B70' end='0x134B80' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x134B80' end='0x134B90' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x134B90' end='0x134BA0' datawidth='32' /><slave name='pio_pps.mem' start='0x134BA0' end='0x134BB0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x134BB0' end='0x134BB8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x134BB8' end='0x134BC0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x134BC0' end='0x134BC8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x134BC8' end='0x134BD0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x134BD0' end='0x134BD8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x134BD8' end='0x134BE0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x134BE0' end='0x134BE8' datawidth='32' /><slave name='reg_si.mem' start='0x134BE8' end='0x134BF0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x134BF0' end='0x134BF8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x134BF8' end='0x134C00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x134C00' end='0x134C08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x134C08' end='0x134C10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x134C10' end='0x134C18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10C400' end='0x10C500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10C500' end='0x10C600' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C600' end='0x10C680' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C680' end='0x10C700' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C700' end='0x10C780' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C800' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C840' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C880' end='0x10C8C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C8C0' end='0x10C900' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C900' end='0x10C940' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C940' end='0x10C980' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C980' end='0x10C9C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C9C0' end='0x10CA00' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10CA00' end='0x10CA20' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10CA20' end='0x10CA40' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CA40' end='0x10CA60' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10CA60' end='0x10CA80' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10CA80' end='0x10CAA0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10CAA0' end='0x10CAC0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10CAC0' end='0x10CAE0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10CAE0' end='0x10CB00' datawidth='32' /><slave name='reg_epcs.mem' start='0x10CB00' end='0x10CB20' datawidth='32' /><slave name='reg_remu.mem' start='0x10CB20' end='0x10CB40' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10CB40' end='0x10CB50' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10CB50' end='0x10CB60' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10CB60' end='0x10CB70' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10CB70' end='0x10CB80' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10CB80' end='0x10CB90' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10CB90' end='0x10CBA0' datawidth='32' /><slave name='pio_pps.mem' start='0x10CBA0' end='0x10CBB0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10CBB0' end='0x10CBB8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10CBB8' end='0x10CBC0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10CBC0' end='0x10CBC8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10CBC8' end='0x10CBD0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10CBD0' end='0x10CBD8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10CBD8' end='0x10CBE0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10CBE0' end='0x10CBE8' datawidth='32' /><slave name='reg_si.mem' start='0x10CBE8' end='0x10CBF0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10CBF0' end='0x10CBF8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10CBF8' end='0x10CC00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CC00' end='0x10CC08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CC08' end='0x10CC10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CC10' end='0x10CC18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xE0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xE0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x110000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x110000' end='0x120000' datawidth='32' /><slave name='ram_wg.mem' start='0x120000' end='0x130000' datawidth='32' /><slave name='jesd204b.mem' start='0x130000' end='0x134000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x134000' end='0x134200' datawidth='32' /><slave name='reg_wg.mem' start='0x134200' end='0x134300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x134300' end='0x134400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x134400' end='0x134500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x134500' end='0x134600' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x134600' end='0x134680' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x134680' end='0x134700' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x134700' end='0x134780' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x134780' end='0x1347C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x1347C0' end='0x134800' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x134800' end='0x134840' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x134840' end='0x134880' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x134880' end='0x1348C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x1348C0' end='0x134900' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x134900' end='0x134940' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x134940' end='0x134980' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x134980' end='0x1349C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x1349C0' end='0x134A00' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x134A00' end='0x134A20' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x134A20' end='0x134A40' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x134A40' end='0x134A60' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x134A60' end='0x134A80' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x134A80' end='0x134AA0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x134AA0' end='0x134AC0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x134AC0' end='0x134AE0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x134AE0' end='0x134B00' datawidth='32' /><slave name='reg_epcs.mem' start='0x134B00' end='0x134B20' datawidth='32' /><slave name='reg_remu.mem' start='0x134B20' end='0x134B40' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x134B40' end='0x134B50' datawidth='32' /><slave name='reg_ring_info.mem' start='0x134B50' end='0x134B60' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x134B60' end='0x134B70' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x134B70' end='0x134B80' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x134B80' end='0x134B90' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x134B90' end='0x134BA0' datawidth='32' /><slave name='pio_pps.mem' start='0x134BA0' end='0x134BB0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x134BB0' end='0x134BB8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x134BB8' end='0x134BC0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x134BC0' end='0x134BC8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x134BC8' end='0x134BD0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x134BD0' end='0x134BD8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x134BD8' end='0x134BE0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x134BE0' end='0x134BE8' datawidth='32' /><slave name='reg_si.mem' start='0x134BE8' end='0x134BF0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x134BF0' end='0x134BF8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x134BF8' end='0x134C00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x134C00' end='0x134C08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x134C08' end='0x134C10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x134C10' end='0x134C18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
index db6fc39074d58381ab89c6b31436537be13f1b2f..a41b1862532cae74669bc5796dd21eee27635333 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">32768</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">65536</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>12</spirit:right>
+ <spirit:right>13</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>12</spirit:right>
+ <spirit:right>13</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">13</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">14</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -846,7 +846,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -910,7 +910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -979,7 +979,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1374,11 +1374,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>16</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
index 84f4ab16fc3ab53e83d375f158d4588247ad4ecb..b738e91a46e6a43447119e6184a3fce6af59b067 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">65536</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">131072</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>13</spirit:right>
+ <spirit:right>14</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>13</spirit:right>
+ <spirit:right>14</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">14</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">15</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -846,7 +846,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -910,7 +910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -979,7 +979,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1374,11 +1374,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>17</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
index 26fa1a2d5968f125e4f8934794feb2e3cb144686..f1909a6dbac234a137fff0ef33501209b7d2f8eb 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">65536</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">131072</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>13</spirit:right>
+ <spirit:right>14</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>13</spirit:right>
+ <spirit:right>14</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">14</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">15</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -846,7 +846,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -910,7 +910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -979,7 +979,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1374,11 +1374,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>17</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
index 72ec443b74114af5a260e92fc2a8646a785144a0..2f785947ec6d087af7126a047e523df70e21d1f8 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
@@ -83,7 +83,7 @@
{
datum baseAddress
{
- value = "1081344";
+ value = "1245184";
type = "String";
}
}
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "1100816";
+ value = "1264656";
type = "String";
}
}
@@ -144,7 +144,7 @@
{
datum baseAddress
{
- value = "1100744";
+ value = "1264584";
type = "String";
}
}
@@ -165,7 +165,7 @@
{
datum baseAddress
{
- value = "1100704";
+ value = "1264544";
type = "String";
}
}
@@ -250,7 +250,7 @@
{
datum baseAddress
{
- value = "32768";
+ value = "1048576";
type = "String";
}
}
@@ -266,7 +266,7 @@
{
datum baseAddress
{
- value = "917504";
+ value = "786432";
type = "String";
}
}
@@ -298,7 +298,7 @@
{
datum baseAddress
{
- value = "786432";
+ value = "1114112";
type = "String";
}
}
@@ -330,7 +330,7 @@
{
datum baseAddress
{
- value = "98304";
+ value = "32768";
type = "String";
}
}
@@ -346,7 +346,7 @@
{
datum baseAddress
{
- value = "983040";
+ value = "917504";
type = "String";
}
}
@@ -378,7 +378,7 @@
{
datum baseAddress
{
- value = "851968";
+ value = "1179648";
type = "String";
}
}
@@ -394,7 +394,7 @@
{
datum baseAddress
{
- value = "1098496";
+ value = "1262336";
type = "String";
}
}
@@ -410,7 +410,7 @@
{
datum baseAddress
{
- value = "1100688";
+ value = "1264528";
type = "String";
}
}
@@ -426,7 +426,7 @@
{
datum baseAddress
{
- value = "1100320";
+ value = "1264160";
type = "String";
}
}
@@ -442,7 +442,7 @@
{
datum baseAddress
{
- value = "1099264";
+ value = "1263104";
type = "String";
}
}
@@ -474,7 +474,7 @@
{
datum baseAddress
{
- value = "1099776";
+ value = "1263616";
type = "String";
}
}
@@ -490,7 +490,7 @@
{
datum baseAddress
{
- value = "1100448";
+ value = "1264288";
type = "String";
}
}
@@ -506,7 +506,7 @@
{
datum baseAddress
{
- value = "1099840";
+ value = "1263680";
type = "String";
}
}
@@ -522,7 +522,7 @@
{
datum baseAddress
{
- value = "1099904";
+ value = "1263744";
type = "String";
}
}
@@ -538,7 +538,7 @@
{
datum baseAddress
{
- value = "1099712";
+ value = "1263552";
type = "String";
}
}
@@ -570,7 +570,7 @@
{
datum baseAddress
{
- value = "1099648";
+ value = "1263488";
type = "String";
}
}
@@ -634,7 +634,7 @@
{
datum baseAddress
{
- value = "1100352";
+ value = "1264192";
type = "String";
}
}
@@ -650,7 +650,7 @@
{
datum baseAddress
{
- value = "1100416";
+ value = "1264256";
type = "String";
}
}
@@ -666,7 +666,7 @@
{
datum baseAddress
{
- value = "1100768";
+ value = "1264608";
type = "String";
}
}
@@ -682,7 +682,7 @@
{
datum baseAddress
{
- value = "1100480";
+ value = "1264320";
type = "String";
}
}
@@ -698,7 +698,7 @@
{
datum baseAddress
{
- value = "1100032";
+ value = "1263872";
type = "String";
}
}
@@ -714,7 +714,7 @@
{
datum baseAddress
{
- value = "1100096";
+ value = "1263936";
type = "String";
}
}
@@ -730,7 +730,7 @@
{
datum baseAddress
{
- value = "1099392";
+ value = "1263232";
type = "String";
}
}
@@ -746,7 +746,7 @@
{
datum baseAddress
{
- value = "1100288";
+ value = "1264128";
type = "String";
}
}
@@ -770,7 +770,7 @@
{
datum baseAddress
{
- value = "1100640";
+ value = "1264480";
type = "String";
}
}
@@ -802,7 +802,7 @@
{
datum baseAddress
{
- value = "1099968";
+ value = "1263808";
type = "String";
}
}
@@ -818,7 +818,7 @@
{
datum baseAddress
{
- value = "1100760";
+ value = "1264600";
type = "String";
}
}
@@ -834,7 +834,7 @@
{
datum baseAddress
{
- value = "1099520";
+ value = "1263360";
type = "String";
}
}
@@ -850,7 +850,7 @@
{
datum baseAddress
{
- value = "1100672";
+ value = "1264512";
type = "String";
}
}
@@ -871,7 +871,7 @@
{
datum baseAddress
{
- value = "1100808";
+ value = "1264648";
type = "String";
}
}
@@ -892,7 +892,7 @@
{
datum baseAddress
{
- value = "1100800";
+ value = "1264640";
type = "String";
}
}
@@ -913,7 +913,7 @@
{
datum baseAddress
{
- value = "1100544";
+ value = "1264384";
type = "String";
}
}
@@ -929,7 +929,7 @@
{
datum baseAddress
{
- value = "1100512";
+ value = "1264352";
type = "String";
}
}
@@ -950,7 +950,7 @@
{
datum baseAddress
{
- value = "1100224";
+ value = "1264064";
type = "String";
}
}
@@ -966,7 +966,7 @@
{
datum baseAddress
{
- value = "1097728";
+ value = "1261568";
type = "String";
}
}
@@ -987,7 +987,7 @@
{
datum baseAddress
{
- value = "1100792";
+ value = "1264632";
type = "String";
}
}
@@ -1008,7 +1008,7 @@
{
datum baseAddress
{
- value = "1100784";
+ value = "1264624";
type = "String";
}
}
@@ -1024,7 +1024,7 @@
{
datum baseAddress
{
- value = "1100720";
+ value = "1264560";
type = "String";
}
}
@@ -1040,7 +1040,7 @@
{
datum baseAddress
{
- value = "1100752";
+ value = "1264592";
type = "String";
}
}
@@ -1056,7 +1056,7 @@
{
datum baseAddress
{
- value = "1048576";
+ value = "98304";
type = "String";
}
}
@@ -1077,7 +1077,7 @@
{
datum baseAddress
{
- value = "1100576";
+ value = "1264416";
type = "String";
}
}
@@ -1093,7 +1093,7 @@
{
datum baseAddress
{
- value = "1100624";
+ value = "1264464";
type = "String";
}
}
@@ -1109,7 +1109,7 @@
{
datum baseAddress
{
- value = "1100608";
+ value = "1264448";
type = "String";
}
}
@@ -1141,7 +1141,7 @@
{
datum baseAddress
{
- value = "1100160";
+ value = "1264000";
type = "String";
}
}
@@ -1157,7 +1157,7 @@
{
datum baseAddress
{
- value = "1100776";
+ value = "1264616";
type = "String";
}
}
@@ -1173,7 +1173,7 @@
{
datum baseAddress
{
- value = "1100656";
+ value = "1264496";
type = "String";
}
}
@@ -1189,7 +1189,7 @@
{
datum baseAddress
{
- value = "1100736";
+ value = "1264576";
type = "String";
}
}
@@ -1205,7 +1205,7 @@
{
datum baseAddress
{
- value = "1100728";
+ value = "1264568";
type = "String";
}
}
@@ -1269,7 +1269,7 @@
{
datum baseAddress
{
- value = "1100384";
+ value = "1264224";
type = "String";
}
}
@@ -1301,7 +1301,7 @@
{
datum baseAddress
{
- value = "1098752";
+ value = "1262592";
type = "String";
}
}
@@ -1317,7 +1317,7 @@
{
datum baseAddress
{
- value = "1099008";
+ value = "1262848";
type = "String";
}
}
@@ -1359,7 +1359,7 @@
{
datum baseAddress
{
- value = "1098240";
+ value = "1262080";
type = "String";
}
}
@@ -7037,7 +7037,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10C400' end='0x10C500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10C500' end='0x10C600' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C600' end='0x10C680' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C680' end='0x10C700' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C700' end='0x10C780' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C800' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C840' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C880' end='0x10C8C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C8C0' end='0x10C900' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C900' end='0x10C940' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C940' end='0x10C980' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C980' end='0x10C9C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C9C0' end='0x10CA00' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10CA00' end='0x10CA20' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10CA20' end='0x10CA40' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CA40' end='0x10CA60' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10CA60' end='0x10CA80' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10CA80' end='0x10CAA0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10CAA0' end='0x10CAC0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10CAC0' end='0x10CAE0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10CAE0' end='0x10CB00' datawidth='32' /><slave name='reg_epcs.mem' start='0x10CB00' end='0x10CB20' datawidth='32' /><slave name='reg_remu.mem' start='0x10CB20' end='0x10CB40' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10CB40' end='0x10CB50' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10CB50' end='0x10CB60' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10CB60' end='0x10CB70' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10CB70' end='0x10CB80' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10CB80' end='0x10CB90' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10CB90' end='0x10CBA0' datawidth='32' /><slave name='pio_pps.mem' start='0x10CBA0' end='0x10CBB0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10CBB0' end='0x10CBB8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10CBB8' end='0x10CBC0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10CBC0' end='0x10CBC8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10CBC8' end='0x10CBD0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10CBD0' end='0x10CBD8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10CBD8' end='0x10CBE0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10CBE0' end='0x10CBE8' datawidth='32' /><slave name='reg_si.mem' start='0x10CBE8' end='0x10CBF0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10CBF0' end='0x10CBF8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10CBF8' end='0x10CC00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CC00' end='0x10CC08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CC08' end='0x10CC10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CC10' end='0x10CC18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xE0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xE0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x110000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x110000' end='0x120000' datawidth='32' /><slave name='ram_wg.mem' start='0x120000' end='0x130000' datawidth='32' /><slave name='jesd204b.mem' start='0x130000' end='0x134000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x134000' end='0x134200' datawidth='32' /><slave name='reg_wg.mem' start='0x134200' end='0x134300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x134300' end='0x134400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x134400' end='0x134500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x134500' end='0x134600' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x134600' end='0x134680' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x134680' end='0x134700' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x134700' end='0x134780' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x134780' end='0x1347C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x1347C0' end='0x134800' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x134800' end='0x134840' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x134840' end='0x134880' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x134880' end='0x1348C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x1348C0' end='0x134900' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x134900' end='0x134940' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x134940' end='0x134980' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x134980' end='0x1349C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x1349C0' end='0x134A00' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x134A00' end='0x134A20' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x134A20' end='0x134A40' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x134A40' end='0x134A60' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x134A60' end='0x134A80' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x134A80' end='0x134AA0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x134AA0' end='0x134AC0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x134AC0' end='0x134AE0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x134AE0' end='0x134B00' datawidth='32' /><slave name='reg_epcs.mem' start='0x134B00' end='0x134B20' datawidth='32' /><slave name='reg_remu.mem' start='0x134B20' end='0x134B40' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x134B40' end='0x134B50' datawidth='32' /><slave name='reg_ring_info.mem' start='0x134B50' end='0x134B60' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x134B60' end='0x134B70' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x134B70' end='0x134B80' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x134B80' end='0x134B90' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x134B90' end='0x134BA0' datawidth='32' /><slave name='pio_pps.mem' start='0x134BA0' end='0x134BB0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x134BB0' end='0x134BB8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x134BB8' end='0x134BC0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x134BC0' end='0x134BC8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x134BC8' end='0x134BD0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x134BD0' end='0x134BD8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x134BD8' end='0x134BE0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x134BE0' end='0x134BE8' datawidth='32' /><slave name='reg_si.mem' start='0x134BE8' end='0x134BF0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x134BF0' end='0x134BF8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x134BF8' end='0x134C00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x134C00' end='0x134C08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x134C08' end='0x134C10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x134C10' end='0x134C18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -12772,7 +12772,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -12836,7 +12836,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -12905,7 +12905,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -13311,11 +13311,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>16</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -13388,7 +13388,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -13452,7 +13452,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -13521,7 +13521,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -13927,11 +13927,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>17</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -16468,7 +16468,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16532,7 +16532,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16601,7 +16601,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -17007,11 +17007,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>17</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -55372,7 +55372,7 @@
version="18.0"
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
- <parameter name="baseAddress" value="0x0010cc10" />
+ <parameter name="baseAddress" value="0x00134c10" />
</connection>
<connection
kind="avalon"
@@ -55386,7 +55386,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_unb_sens.mem">
- <parameter name="baseAddress" value="0x0010c500" />
+ <parameter name="baseAddress" value="0x00134500" />
</connection>
<connection
kind="avalon"
@@ -55407,7 +55407,7 @@
version="18.0"
start="cpu_0.data_master"
end="pio_pps.mem">
- <parameter name="baseAddress" value="0x0010cba0" />
+ <parameter name="baseAddress" value="0x00134ba0" />
</connection>
<connection
kind="avalon"
@@ -55421,84 +55421,84 @@
version="18.0"
start="cpu_0.data_master"
end="reg_remu.mem">
- <parameter name="baseAddress" value="0x0010cb20" />
+ <parameter name="baseAddress" value="0x00134b20" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_epcs.mem">
- <parameter name="baseAddress" value="0x0010cb00" />
+ <parameter name="baseAddress" value="0x00134b00" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
- <parameter name="baseAddress" value="0x0010cc08" />
+ <parameter name="baseAddress" value="0x00134c08" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
- <parameter name="baseAddress" value="0x0010cc00" />
+ <parameter name="baseAddress" value="0x00134c00" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
- <parameter name="baseAddress" value="0x0010cbf8" />
+ <parameter name="baseAddress" value="0x00134bf8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
- <parameter name="baseAddress" value="0x0010cbf0" />
+ <parameter name="baseAddress" value="0x00134bf0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
- <parameter name="baseAddress" value="0x0010cae0" />
+ <parameter name="baseAddress" value="0x00134ae0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_unb_pmbus.mem">
- <parameter name="baseAddress" value="0x0010c400" />
+ <parameter name="baseAddress" value="0x00134400" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
- <parameter name="baseAddress" value="0x0010c9c0" />
+ <parameter name="baseAddress" value="0x001349c0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_st_sst.mem">
- <parameter name="baseAddress" value="0x000f0000" />
+ <parameter name="baseAddress" value="0x000e0000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_si.mem">
- <parameter name="baseAddress" value="0x0010cbe8" />
+ <parameter name="baseAddress" value="0x00134be8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_fil_coefs.mem">
- <parameter name="baseAddress" value="0x000e0000" />
+ <parameter name="baseAddress" value="0x000c0000" />
</connection>
<connection
kind="avalon"
@@ -55512,42 +55512,42 @@
version="18.0"
start="cpu_0.data_master"
end="reg_aduh_monitor.mem">
- <parameter name="baseAddress" value="0x0010c300" />
+ <parameter name="baseAddress" value="0x00134300" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_wg.mem">
- <parameter name="baseAddress" value="0x000d0000" />
+ <parameter name="baseAddress" value="0x00120000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_shiftram.mem">
- <parameter name="baseAddress" value="0x0010c700" />
+ <parameter name="baseAddress" value="0x00134700" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
- <parameter name="baseAddress" value="0x0010cbe0" />
+ <parameter name="baseAddress" value="0x00134be0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_source_v2.mem">
- <parameter name="baseAddress" value="0x0010cac0" />
+ <parameter name="baseAddress" value="0x00134ac0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_wg.mem">
- <parameter name="baseAddress" value="0x0010c200" />
+ <parameter name="baseAddress" value="0x00134200" />
</connection>
<connection
kind="avalon"
@@ -55561,42 +55561,42 @@
version="18.0"
start="cpu_0.data_master"
end="jesd204b.mem">
- <parameter name="baseAddress" value="0x00108000" />
+ <parameter name="baseAddress" value="0x00130000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_selector.mem">
- <parameter name="baseAddress" value="0x0010cbd8" />
+ <parameter name="baseAddress" value="0x00134bd8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_ss_ss_wide.mem">
- <parameter name="baseAddress" value="0x000c0000" />
+ <parameter name="baseAddress" value="0x00110000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bf_scale.mem">
- <parameter name="baseAddress" value="0x0010cb90" />
+ <parameter name="baseAddress" value="0x00134b90" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_hdr_dat.mem">
- <parameter name="baseAddress" value="0x0010c000" />
+ <parameter name="baseAddress" value="0x00134000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_xonoff.mem">
- <parameter name="baseAddress" value="0x0010cb80" />
+ <parameter name="baseAddress" value="0x00134b80" />
</connection>
<connection
kind="avalon"
@@ -55610,28 +55610,28 @@
version="18.0"
start="cpu_0.data_master"
end="reg_sdp_info.mem">
- <parameter name="baseAddress" value="0x0010c980" />
+ <parameter name="baseAddress" value="0x00134980" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
- <parameter name="baseAddress" value="0x0010cbd0" />
+ <parameter name="baseAddress" value="0x00134bd0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_nw_10gbe_mac.mem">
- <parameter name="baseAddress" value="0x00100000" />
+ <parameter name="baseAddress" value="0x00018000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_diag_data_buffer_bsn.mem">
- <parameter name="baseAddress" value="0x0010c680" />
+ <parameter name="baseAddress" value="0x00134680" />
</connection>
<connection
kind="avalon"
@@ -55645,14 +55645,14 @@
version="18.0"
start="cpu_0.data_master"
end="pio_jesd_ctrl.mem">
- <parameter name="baseAddress" value="0x0010cbc8" />
+ <parameter name="baseAddress" value="0x00134bc8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_sst.mem">
- <parameter name="baseAddress" value="0x0010cbc0" />
+ <parameter name="baseAddress" value="0x00134bc0" />
</connection>
<connection
kind="avalon"
@@ -55666,7 +55666,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_bst.mem">
- <parameter name="baseAddress" value="0x0010cb70" />
+ <parameter name="baseAddress" value="0x00134b70" />
</connection>
<connection
kind="avalon"
@@ -55680,7 +55680,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_crosslets_info.mem">
- <parameter name="baseAddress" value="0x0010c940" />
+ <parameter name="baseAddress" value="0x00134940" />
</connection>
<connection
kind="avalon"
@@ -55694,7 +55694,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_xst.mem">
- <parameter name="baseAddress" value="0x0010cbb8" />
+ <parameter name="baseAddress" value="0x00134bb8" />
</connection>
<connection
kind="avalon"
@@ -55708,28 +55708,28 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_sync_scheduler_xsub.mem">
- <parameter name="baseAddress" value="0x0010c900" />
+ <parameter name="baseAddress" value="0x00134900" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_st_histogram.mem">
- <parameter name="baseAddress" value="0x00018000" />
+ <parameter name="baseAddress" value="0x8000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_nof_crosslets.mem">
- <parameter name="baseAddress" value="0x0010cbb0" />
+ <parameter name="baseAddress" value="0x00134bb0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_align_v2_xsub.mem">
- <parameter name="baseAddress" value="0x0010c600" />
+ <parameter name="baseAddress" value="0x00134600" />
</connection>
<connection
kind="avalon"
@@ -55743,14 +55743,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_aligned_xsub.mem">
- <parameter name="baseAddress" value="0x0010caa0" />
+ <parameter name="baseAddress" value="0x00134aa0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_xst_offload.mem">
- <parameter name="baseAddress" value="0x0010ca80" />
+ <parameter name="baseAddress" value="0x00134a80" />
</connection>
<connection
kind="avalon"
@@ -55778,28 +55778,28 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_block_validate_err_xst.mem">
- <parameter name="baseAddress" value="0x0010c8c0" />
+ <parameter name="baseAddress" value="0x001348c0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_block_validate_bsn_at_sync_xst.mem">
- <parameter name="baseAddress" value="0x0010cb60" />
+ <parameter name="baseAddress" value="0x00134b60" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_ring_info.mem">
- <parameter name="baseAddress" value="0x0010cb50" />
+ <parameter name="baseAddress" value="0x00134b50" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_tr_10gbe_eth10g.mem">
- <parameter name="baseAddress" value="0x0010ca60" />
+ <parameter name="baseAddress" value="0x00134a60" />
</connection>
<connection
kind="avalon"
@@ -55813,28 +55813,28 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_sst_offload.mem">
- <parameter name="baseAddress" value="0x0010ca40" />
+ <parameter name="baseAddress" value="0x00134a40" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_bst_offload.mem">
- <parameter name="baseAddress" value="0x0010c880" />
+ <parameter name="baseAddress" value="0x00134880" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_beamlet_output.mem">
- <parameter name="baseAddress" value="0x0010c840" />
+ <parameter name="baseAddress" value="0x00134840" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_align_v2_bf.mem">
- <parameter name="baseAddress" value="0x0010ca20" />
+ <parameter name="baseAddress" value="0x00134a20" />
</connection>
<connection
kind="avalon"
@@ -55848,28 +55848,28 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_aligned_bf.mem">
- <parameter name="baseAddress" value="0x0010c800" />
+ <parameter name="baseAddress" value="0x00134800" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_ring_lane_info_bf.mem">
- <parameter name="baseAddress" value="0x0010cb40" />
+ <parameter name="baseAddress" value="0x00134b40" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_ring_rx_bf.mem">
- <parameter name="baseAddress" value="0x0010c7c0" />
+ <parameter name="baseAddress" value="0x001347c0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_ring_tx_bf.mem">
- <parameter name="baseAddress" value="0x0010c780" />
+ <parameter name="baseAddress" value="0x00134780" />
</connection>
<connection
kind="avalon"
@@ -55883,7 +55883,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_block_validate_bsn_at_sync_bf.mem">
- <parameter name="baseAddress" value="0x0010ca00" />
+ <parameter name="baseAddress" value="0x00134a00" />
</connection>
<connection
kind="avalon"
@@ -55897,7 +55897,7 @@
version="18.0"
start="cpu_0.data_master"
end="ram_equalizer_gains.mem">
- <parameter name="baseAddress" value="0x8000" />
+ <parameter name="baseAddress" value="0x00100000" />
</connection>
<connection
kind="avalon"
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2cfff131262a66a8e1c7c65bd345791bd2835a43
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd
@@ -0,0 +1,194 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author : R. van der Walle
+-- Purpose:
+-- Wrapper for Disturb2 SDP Station full design, a revision of lofar2_sdp_station_full
+-- Description:
+-- Unb2b version for lab testing
+-- Contains complete SDP station design with AIT input stage with 12 ADC streams, oversampeld FSUB, XSUB, BF and RING
+
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY disturb2_unb2b_sdp_station_full IS
+ GENERIC (
+ g_design_name : STRING := "disturb2_unb2b_sdp_station_full";
+ g_design_note : STRING := "Disturb2 SDP station full design";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC := '0';
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+
+ -- Transceiver clocks
+ SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+ -- LEDs
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+
+ -- ring transceivers
+ RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS => '0'); -- Using qsfp bus width also for ring interfaces
+ RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+
+ -- back transceivers (note only 6 are used in unb2b)
+ BCK_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b-1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
+ BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
+
+ -- jesd204b syncronization signals (2 syncs)
+ JESD204B_SYSREF : IN STD_LOGIC;
+ JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) -- c_unb2b_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ );
+END disturb2_unb2b_sdp_station_full;
+
+ARCHITECTURE str OF disturb2_unb2b_sdp_station_full IS
+
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 downto 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC;
+
+
+BEGIN
+
+ -- Mapping between JESD signal names and UNB2B pin/schematic names
+ JESD204B_REFCLK <= BCK_REF_CLK;
+ JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
+ JESD204B_SERIAL_DATA(1) <= BCK_RX(43);
+ JESD204B_SERIAL_DATA(2) <= BCK_RX(44);
+ JESD204B_SERIAL_DATA(3) <= BCK_RX(45);
+ JESD204B_SERIAL_DATA(4) <= BCK_RX(46);
+ JESD204B_SERIAL_DATA(5) <= BCK_RX(47);
+ JESD204B_SERIAL_DATA(6) <= '0';
+ JESD204B_SERIAL_DATA(7) <= '0';
+ JESD204B_SERIAL_DATA(8) <= '0';
+ JESD204B_SERIAL_DATA(9) <= '0';
+ JESD204B_SERIAL_DATA(10) <= '0';
+ JESD204B_SERIAL_DATA(11) <= '0';
+ JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+
+
+ u_revision : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
+END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b85bc78b08035457af0eed4a6fae25007a1f4bef
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full_pins.tcl
@@ -0,0 +1,26 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..fc9f9b0be2067dec7d4a402040b2b2fc1bc90645
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/hdllib.cfg
@@ -0,0 +1,131 @@
+hdl_lib_name = disturb2_unb2b_sdp_station_full
+hdl_library_clause_name = disturb2_unb2b_sdp_station_full_lib
+hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_sdp_station
+hdl_lib_uses_sim = eth
+hdl_lib_technology = ip_arria10_e1sg
+
+ synth_files =
+ disturb2_unb2b_sdp_station_full.vhd
+
+test_bench_files =
+
+regression_test_vhdl =
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ # Overwrite bf weights with sim data
+ ../../tb/data data
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ ../../quartus .
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+# use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
+quartus_sdc_files =
+ ../../quartus/lofar2_unb2b_sdp_station.sdc
+ #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+ disturb2_unb2b_sdp_station_full_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/disturb2_unb2b_sdp_station_full/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4878d4fa2420751e1152ee92afdf35d650962a93
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
@@ -0,0 +1,157 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author : R. van der Walle
+-- Purpose:
+-- Wrapper for Disturb2 SDP Station full design.
+-- Description:
+-- Unb2b version for lab testing of SDP using the WG.
+-- Contains AIT input stage with WG, oversampled FSUB, XSUB, BF and RING, so without ADC JESD.
+
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY disturb2_unb2b_sdp_station_full_wg IS
+ GENERIC (
+ g_design_name : STRING := "Disturb2_unb2b_sdp_station_full_wg";
+ g_design_note : STRING := "Disturb2 SDP station full design WG";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC := '0';
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+
+ -- Transceiver clocks
+ SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+
+ -- front transceivers
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+
+ -- LEDs
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+
+ -- ring transceivers
+ RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS => '0'); -- Using qsfp bus width also for ring interfaces
+ RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0)
+ );
+END disturb2_unb2b_sdp_station_full_wg;
+
+ARCHITECTURE str OF disturb2_unb2b_sdp_station_full_wg IS
+
+BEGIN
+
+ u_revision : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX
+ );
+END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..689b010fb83a0f4df276dd070b6e8cc383755595
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg_pins.tcl
@@ -0,0 +1,25 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..c94035c6cff04e94efdb8bb8de049c37dd9465fd
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/hdllib.cfg
@@ -0,0 +1,131 @@
+hdl_lib_name = disturb2_unb2b_sdp_station_full_wg
+hdl_library_clause_name = disturb2_unb2b_sdp_station_full_wg_lib
+hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_sdp_station
+hdl_lib_uses_sim = eth
+hdl_lib_technology = ip_arria10_e1sg
+
+ synth_files =
+ disturb2_unb2b_sdp_station_full_wg.vhd
+
+test_bench_files =
+
+regression_test_vhdl =
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ # Overwrite bf weights with sim data
+ ../../tb/data data
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ ../../quartus .
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+# use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
+quartus_sdc_files =
+ ../../quartus/lofar2_unb2b_sdp_station.sdc
+ #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+ disturb2_unb2b_sdp_station_full_wg_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/disturb2_unb2b_sdp_station_full_wg/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index a5f605b3520af98c62aa61a552bad970cc807c3a..aebdb44fbc63e59491da5ef90addfce1354ed21d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -811,6 +811,7 @@ BEGIN
g_scope_selected_subband => g_scope_selected_subband,
g_no_jesd => c_revision_select.no_jesd,
g_use_fsub => c_revision_select.use_fsub,
+ g_use_oversample => c_revision_select.use_oversample,
g_use_xsub => c_revision_select.use_xsub,
g_use_bf => c_revision_select.use_bf,
g_use_ring => c_revision_select.use_ring,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
index f30f8846296984174033903e141b5d2d5c3f7877..ee9647cb426ff1aa1cac7bd3de7c502723b51201 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
@@ -34,20 +34,23 @@ PACKAGE lofar2_unb2b_sdp_station_pkg IS
TYPE t_lofar2_unb2b_sdp_station_config IS RECORD
no_jesd : BOOLEAN;
use_fsub : BOOLEAN;
+ use_oversample : BOOLEAN;
use_bf : BOOLEAN;
use_xsub : BOOLEAN;
use_ring : BOOLEAN;
P_sq : NATURAL;
END RECORD;
- CONSTANT c_ait : t_lofar2_unb2b_sdp_station_config := (FALSE, FALSE, FALSE, FALSE, FALSE, 0);
- CONSTANT c_fsub : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, FALSE, FALSE, FALSE, 0);
- CONSTANT c_bf : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, TRUE, FALSE, FALSE, 0);
- CONSTANT c_bf_ring : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, TRUE, FALSE, TRUE, 0);
- CONSTANT c_xsub_one : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, FALSE, TRUE, FALSE, 1);
- CONSTANT c_xsub_ring : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, FALSE, TRUE, TRUE, 9);
- CONSTANT c_full_wg : t_lofar2_unb2b_sdp_station_config := (TRUE, TRUE, TRUE, TRUE, TRUE, 9);
- CONSTANT c_full : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, TRUE, TRUE, TRUE, 9);
+ CONSTANT c_ait : t_lofar2_unb2b_sdp_station_config := (FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, 0);
+ CONSTANT c_fsub : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, 0);
+ CONSTANT c_bf : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, FALSE, TRUE, FALSE, FALSE, 0);
+ CONSTANT c_bf_ring : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, FALSE, TRUE, FALSE, TRUE, 0);
+ CONSTANT c_xsub_one : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, FALSE, FALSE, TRUE, FALSE, 1);
+ CONSTANT c_xsub_ring : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, FALSE, FALSE, TRUE, TRUE, 9);
+ CONSTANT c_full_wg : t_lofar2_unb2b_sdp_station_config := (TRUE, TRUE, FALSE, TRUE, TRUE, TRUE, 9);
+ CONSTANT c_full_os : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, TRUE, TRUE, TRUE, TRUE, 9);
+ CONSTANT c_full_wg_os : t_lofar2_unb2b_sdp_station_config := (TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 9);
+ CONSTANT c_full : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, FALSE, TRUE, TRUE, TRUE, 9);
-- Function to select the revision configuration.
FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_lofar2_unb2b_sdp_station_config;
@@ -67,6 +70,8 @@ PACKAGE BODY lofar2_unb2b_sdp_station_pkg IS
ELSIF g_design_name = "lofar2_unb2b_sdp_station_xsub_one" THEN RETURN c_xsub_one;
ELSIF g_design_name = "lofar2_unb2b_sdp_station_xsub_ring" THEN RETURN c_xsub_ring;
ELSIF g_design_name = "lofar2_unb2b_sdp_station_full_wg" THEN RETURN c_full_wg;
+ ELSIF g_design_name = "disturb2_unb2b_sdp_station_full" THEN RETURN c_full_os;
+ ELSIF g_design_name = "disturb2_unb2b_sdp_station_full_wg" THEN RETURN c_full_wg_os;
ELSE RETURN c_full;
END IF;
END;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index 9537b5c59308a8b7f8dc686e7be8a8fb6945c730..b156b4c6a05e253dd1b19676589277f604fa6b53 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -91,14 +91,14 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0); -- export
ram_equalizer_gains_clk_export : out std_logic; -- export
ram_equalizer_gains_read_export : out std_logic; -- export
ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
ram_equalizer_gains_reset_export : out std_logic; -- export
ram_equalizer_gains_write_export : out std_logic; -- export
ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
ram_fil_coefs_clk_export : out std_logic; -- export
ram_fil_coefs_read_export : out std_logic; -- export
ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
@@ -133,7 +133,7 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
ram_st_histogram_reset_export : out std_logic; -- export
ram_st_histogram_write_export : out std_logic; -- export
ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_st_sst_address_export : out std_logic_vector(14 downto 0); -- export
ram_st_sst_clk_export : out std_logic; -- export
ram_st_sst_read_export : out std_logic; -- export
ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
index 3155c2a507d4e80854ca7c45be46bb6215f91fe9..226536ab9f0f53b777950a8c08c5213ca04346dc 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
@@ -21,6 +21,7 @@ parameters:
- { name: c_N_taps, value: 16 }
- { name: c_W_adc_jesd, value: 16 }
- { name: c_W_adc, value: 14 }
+ - { name: c_V_oversample, value: 2 }
- { name: c_V_sample_delay, value: 4096 }
- { name: c_V_si_db_large, value: 131072 }
- { name: c_V_si_db, value: 1024 }
@@ -202,6 +203,8 @@ peripherals:
- REG_SI
- peripheral_name: filter/fil_ppf_w
+ number_of_peripherals: c_V_oversample # Disturb uses 2x oversample
+ peripheral_span: ceil_pow2(c_N_taps) * ceil_pow2(c_N_fft) * MM_BUS_SIZE # number_of_ports = ceil_pow2(c_N_taps), mm_port_span = ceil_pow2(c_N_fft) words
parameter_overrides:
- { name: g_fil_ppf.wb_factor, value: 1 } # process at sample rate (so no parallel wideband factor)
- { name: g_fil_ppf.nof_chan, value: 0 } # process at sample rate (so no serial time multiplexing)
@@ -213,6 +216,8 @@ peripherals:
- RAM_FIL_COEFS
- peripheral_name: sdp/sdp_subband_equalizer
+ parameter_overrides:
+ - { name: P_pfb, value: c_V_oversample * c_P_pfb} # DISTURB uses 2x oversample so 2 X P_pfb
mm_port_names:
- RAM_EQUALIZER_GAINS
@@ -221,6 +226,8 @@ peripherals:
- REG_DP_SELECTOR # input_select = 0 for weighted subbands, input_select = 1 for raw subbands
- peripheral_name: st/st_sst_for_sdp
+ parameter_overrides:
+ - { name: g_nof_instances, value: c_V_oversample * c_P_pfb} # DISTURB uses 2x oversample so 2 X P_pfb
mm_port_names:
- RAM_ST_SST
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
index fc2497605897ab8330046f4e49f409a0e1936c52..7b36d6200aacf1d634d610f1a7be86659bef960a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
@@ -2302,7 +2302,7 @@
<ipxact:parameter parameterId="dataSlaveMapParam" type="string">
<ipxact:name>dataSlaveMapParam</ipxact:name>
<ipxact:displayName>dataSlaveMapParam</ipxact:displayName>
- <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C400' end='0x10C480' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C480' end='0x10C500' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C500' end='0x10C580' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C580' end='0x10C5C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C5C0' end='0x10C600' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C600' end='0x10C640' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C640' end='0x10C680' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C680' end='0x10C6C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C6C0' end='0x10C700' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C700' end='0x10C740' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C740' end='0x10C780' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10C800' end='0x10C820' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10C820' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10C840' end='0x10C860' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10C860' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C880' end='0x10C8A0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10C8A0' end='0x10C8C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10C8C0' end='0x10C8E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10C8E0' end='0x10C900' datawidth='32' /><slave name='reg_epcs.mem' start='0x10C900' end='0x10C920' datawidth='32' /><slave name='reg_remu.mem' start='0x10C920' end='0x10C940' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10C940' end='0x10C950' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10C950' end='0x10C960' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C960' end='0x10C970' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10C970' end='0x10C980' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10C980' end='0x10C990' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10C990' end='0x10C9A0' datawidth='32' /><slave name='pio_pps.mem' start='0x10C9A0' end='0x10C9B0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10C9B0' end='0x10C9B8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10C9B8' end='0x10C9C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10C9C0' end='0x10C9C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10C9C8' end='0x10C9D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10C9D0' end='0x10C9D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10C9D8' end='0x10C9E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10C9E0' end='0x10C9E8' datawidth='32' /><slave name='reg_si.mem' start='0x10C9E8' end='0x10C9F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10C9F0' end='0x10C9F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10C9F8' end='0x10CA00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CA00' end='0x10CA08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CA08' end='0x10CA10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CA10' end='0x10CA18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
+ <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xE0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xE0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x110000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x110000' end='0x120000' datawidth='32' /><slave name='ram_wg.mem' start='0x120000' end='0x130000' datawidth='32' /><slave name='jesd204b.mem' start='0x130000' end='0x134000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x134000' end='0x134200' datawidth='32' /><slave name='reg_wg.mem' start='0x134200' end='0x134300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x134300' end='0x134400' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x134400' end='0x134480' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x134480' end='0x134500' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x134500' end='0x134580' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x134580' end='0x1345C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x1345C0' end='0x134600' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x134600' end='0x134640' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x134640' end='0x134680' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x134680' end='0x1346C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x1346C0' end='0x134700' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x134700' end='0x134740' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x134740' end='0x134780' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x134780' end='0x1347C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x1347C0' end='0x134800' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x134800' end='0x134820' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x134820' end='0x134840' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x134840' end='0x134860' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x134860' end='0x134880' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x134880' end='0x1348A0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x1348A0' end='0x1348C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x1348C0' end='0x1348E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x1348E0' end='0x134900' datawidth='32' /><slave name='reg_epcs.mem' start='0x134900' end='0x134920' datawidth='32' /><slave name='reg_remu.mem' start='0x134920' end='0x134940' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x134940' end='0x134950' datawidth='32' /><slave name='reg_ring_info.mem' start='0x134950' end='0x134960' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x134960' end='0x134970' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x134970' end='0x134980' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x134980' end='0x134990' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x134990' end='0x1349A0' datawidth='32' /><slave name='pio_pps.mem' start='0x1349A0' end='0x1349B0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x1349B0' end='0x1349B8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x1349B8' end='0x1349C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x1349C0' end='0x1349C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x1349C8' end='0x1349D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x1349D0' end='0x1349D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x1349D8' end='0x1349E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x1349E0' end='0x1349E8' datawidth='32' /><slave name='reg_si.mem' start='0x1349E8' end='0x1349F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x1349F0' end='0x1349F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x1349F8' end='0x134A00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x134A00' end='0x134A08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x134A08' end='0x134A10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x134A10' end='0x134A18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="tightlyCoupledDataMaster0MapParam" type="string">
<ipxact:name>tightlyCoupledDataMaster0MapParam</ipxact:name>
@@ -3589,7 +3589,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x100000' end='0x108000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_xsub.mem' start='0x10C400' end='0x10C480' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x10C480' end='0x10C500' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x10C500' end='0x10C580' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C580' end='0x10C5C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C5C0' end='0x10C600' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C600' end='0x10C640' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C640' end='0x10C680' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C680' end='0x10C6C0' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_xst.mem' start='0x10C6C0' end='0x10C700' datawidth='32' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C700' end='0x10C740' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x10C740' end='0x10C780' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10C800' end='0x10C820' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_bf.mem' start='0x10C820' end='0x10C840' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10C840' end='0x10C860' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_eth10g.mem' start='0x10C860' end='0x10C880' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C880' end='0x10C8A0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10C8A0' end='0x10C8C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x10C8C0' end='0x10C8E0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x10C8E0' end='0x10C900' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x10C900' end='0x10C920' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x10C920' end='0x10C940' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_bf.mem' start='0x10C940' end='0x10C950' datawidth='32' /&gt;&lt;slave name='reg_ring_info.mem' start='0x10C950' end='0x10C960' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C960' end='0x10C970' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x10C970' end='0x10C980' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x10C980' end='0x10C990' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x10C990' end='0x10C9A0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x10C9A0' end='0x10C9B0' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0x10C9B0' end='0x10C9B8' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x10C9B8' end='0x10C9C0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x10C9C0' end='0x10C9C8' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x10C9C8' end='0x10C9D0' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x10C9D0' end='0x10C9D8' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x10C9D8' end='0x10C9E0' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x10C9E0' end='0x10C9E8' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x10C9E8' end='0x10C9F0' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x10C9F0' end='0x10C9F8' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x10C9F8' end='0x10CA00' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x10CA00' end='0x10CA08' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x10CA08' end='0x10CA10' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CA10' end='0x10CA18' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0xC0000' end='0xE0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xE0000' end='0x100000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x100000' end='0x110000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0x110000' end='0x120000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0x120000' end='0x130000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x130000' end='0x134000' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x134000' end='0x134200' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x134200' end='0x134300' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x134300' end='0x134400' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_xsub.mem' start='0x134400' end='0x134480' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x134480' end='0x134500' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x134500' end='0x134580' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x134580' end='0x1345C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x1345C0' end='0x134600' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x134600' end='0x134640' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x134640' end='0x134680' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x134680' end='0x1346C0' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_xst.mem' start='0x1346C0' end='0x134700' datawidth='32' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x134700' end='0x134740' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x134740' end='0x134780' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x134780' end='0x1347C0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x1347C0' end='0x134800' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x134800' end='0x134820' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_bf.mem' start='0x134820' end='0x134840' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x134840' end='0x134860' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_eth10g.mem' start='0x134860' end='0x134880' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x134880' end='0x1348A0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x1348A0' end='0x1348C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x1348C0' end='0x1348E0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x1348E0' end='0x134900' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x134900' end='0x134920' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x134920' end='0x134940' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_bf.mem' start='0x134940' end='0x134950' datawidth='32' /&gt;&lt;slave name='reg_ring_info.mem' start='0x134950' end='0x134960' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x134960' end='0x134970' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x134970' end='0x134980' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x134980' end='0x134990' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x134990' end='0x1349A0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x1349A0' end='0x1349B0' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0x1349B0' end='0x1349B8' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x1349B8' end='0x1349C0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x1349C0' end='0x1349C8' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x1349C8' end='0x1349D0' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x1349D0' end='0x1349D8' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x1349D8' end='0x1349E0' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x1349E0' end='0x1349E8' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x1349E8' end='0x1349F0' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x1349F0' end='0x1349F8' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x1349F8' end='0x134A00' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x134A00' end='0x134A08' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x134A08' end='0x134A10' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x134A10' end='0x134A18' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
index 2d023f2008c88bf2c88f2ae07b9be0c815763243..25c86334f48878443a250dc2e74b39f4524727db 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
@@ -139,7 +139,7 @@
<ipxact:parameter parameterId="addressSpan" type="string">
<ipxact:name>addressSpan</ipxact:name>
<ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>32768</ipxact:value>
+ <ipxact:value>65536</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressUnits" type="string">
<ipxact:name>addressUnits</ipxact:name>
@@ -667,7 +667,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>12</ipxact:right>
+ <ipxact:right>13</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -773,7 +773,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>12</ipxact:right>
+ <ipxact:right>13</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -860,7 +860,7 @@
<ipxact:parameter parameterId="g_adr_w" type="int">
<ipxact:name>g_adr_w</ipxact:name>
<ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>13</ipxact:value>
+ <ipxact:value>14</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="g_dat_w" type="int">
<ipxact:name>g_dat_w</ipxact:name>
@@ -997,7 +997,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1066,7 +1066,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1295,7 +1295,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1462,11 +1462,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>16</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
index ea72955b322c7baf3566e7078987f6bddedd25d1..e40819858e4e1b18383b63f49cf2ba4ee88587ab 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
@@ -139,7 +139,7 @@
<ipxact:parameter parameterId="addressSpan" type="string">
<ipxact:name>addressSpan</ipxact:name>
<ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>65536</ipxact:value>
+ <ipxact:value>131072</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressUnits" type="string">
<ipxact:name>addressUnits</ipxact:name>
@@ -667,7 +667,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>13</ipxact:right>
+ <ipxact:right>14</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -773,7 +773,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>13</ipxact:right>
+ <ipxact:right>14</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -860,7 +860,7 @@
<ipxact:parameter parameterId="g_adr_w" type="int">
<ipxact:name>g_adr_w</ipxact:name>
<ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>14</ipxact:value>
+ <ipxact:value>15</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="g_dat_w" type="int">
<ipxact:name>g_dat_w</ipxact:name>
@@ -997,7 +997,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1066,7 +1066,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1295,7 +1295,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1462,11 +1462,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>17</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
index 6dd5191ee9830ecc9d1ac89dfb333a8dd724480f..533be46b78230b19d615dad5e0db35f81b4219b4 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
@@ -139,7 +139,7 @@
<ipxact:parameter parameterId="addressSpan" type="string">
<ipxact:name>addressSpan</ipxact:name>
<ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>65536</ipxact:value>
+ <ipxact:value>131072</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressUnits" type="string">
<ipxact:name>addressUnits</ipxact:name>
@@ -667,7 +667,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>13</ipxact:right>
+ <ipxact:right>14</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -773,7 +773,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>13</ipxact:right>
+ <ipxact:right>14</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -860,7 +860,7 @@
<ipxact:parameter parameterId="g_adr_w" type="int">
<ipxact:name>g_adr_w</ipxact:name>
<ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>14</ipxact:value>
+ <ipxact:value>15</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="g_dat_w" type="int">
<ipxact:name>g_dat_w</ipxact:name>
@@ -997,7 +997,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1066,7 +1066,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1295,7 +1295,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1462,11 +1462,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>17</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
index 2f380edef643f6f6d7f1fd27c48aead80a0a25e2..67b6afa9b53eba540562ccdec1c5d32642e1845d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
@@ -83,7 +83,7 @@
{
datum baseAddress
{
- value = "1081344";
+ value = "1245184";
type = "String";
}
}
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "1100304";
+ value = "1264144";
type = "String";
}
}
@@ -144,7 +144,7 @@
{
datum baseAddress
{
- value = "1100232";
+ value = "1264072";
type = "String";
}
}
@@ -165,7 +165,7 @@
{
datum baseAddress
{
- value = "1100192";
+ value = "1264032";
type = "String";
}
}
@@ -250,7 +250,7 @@
{
datum baseAddress
{
- value = "32768";
+ value = "1048576";
type = "String";
}
}
@@ -266,7 +266,7 @@
{
datum baseAddress
{
- value = "917504";
+ value = "786432";
type = "String";
}
}
@@ -298,7 +298,7 @@
{
datum baseAddress
{
- value = "786432";
+ value = "1114112";
type = "String";
}
}
@@ -330,7 +330,7 @@
{
datum baseAddress
{
- value = "98304";
+ value = "32768";
type = "String";
}
}
@@ -346,7 +346,7 @@
{
datum baseAddress
{
- value = "983040";
+ value = "917504";
type = "String";
}
}
@@ -378,7 +378,7 @@
{
datum baseAddress
{
- value = "851968";
+ value = "1179648";
type = "String";
}
}
@@ -394,7 +394,7 @@
{
datum baseAddress
{
- value = "1098496";
+ value = "1262336";
type = "String";
}
}
@@ -410,7 +410,7 @@
{
datum baseAddress
{
- value = "1100176";
+ value = "1264016";
type = "String";
}
}
@@ -426,7 +426,7 @@
{
datum baseAddress
{
- value = "1099808";
+ value = "1263648";
type = "String";
}
}
@@ -442,7 +442,7 @@
{
datum baseAddress
{
- value = "1098752";
+ value = "1262592";
type = "String";
}
}
@@ -474,7 +474,7 @@
{
datum baseAddress
{
- value = "1099264";
+ value = "1263104";
type = "String";
}
}
@@ -490,7 +490,7 @@
{
datum baseAddress
{
- value = "1099936";
+ value = "1263776";
type = "String";
}
}
@@ -506,7 +506,7 @@
{
datum baseAddress
{
- value = "1099328";
+ value = "1263168";
type = "String";
}
}
@@ -522,7 +522,7 @@
{
datum baseAddress
{
- value = "1099392";
+ value = "1263232";
type = "String";
}
}
@@ -538,7 +538,7 @@
{
datum baseAddress
{
- value = "1099200";
+ value = "1263040";
type = "String";
}
}
@@ -570,7 +570,7 @@
{
datum baseAddress
{
- value = "1099136";
+ value = "1262976";
type = "String";
}
}
@@ -634,7 +634,7 @@
{
datum baseAddress
{
- value = "1099840";
+ value = "1263680";
type = "String";
}
}
@@ -650,7 +650,7 @@
{
datum baseAddress
{
- value = "1099904";
+ value = "1263744";
type = "String";
}
}
@@ -666,7 +666,7 @@
{
datum baseAddress
{
- value = "1100256";
+ value = "1264096";
type = "String";
}
}
@@ -682,7 +682,7 @@
{
datum baseAddress
{
- value = "1099968";
+ value = "1263808";
type = "String";
}
}
@@ -698,7 +698,7 @@
{
datum baseAddress
{
- value = "1099520";
+ value = "1263360";
type = "String";
}
}
@@ -714,7 +714,7 @@
{
datum baseAddress
{
- value = "1099584";
+ value = "1263424";
type = "String";
}
}
@@ -730,7 +730,7 @@
{
datum baseAddress
{
- value = "1098880";
+ value = "1262720";
type = "String";
}
}
@@ -746,7 +746,7 @@
{
datum baseAddress
{
- value = "1099776";
+ value = "1263616";
type = "String";
}
}
@@ -762,7 +762,7 @@
{
datum baseAddress
{
- value = "1100128";
+ value = "1263968";
type = "String";
}
}
@@ -794,7 +794,7 @@
{
datum baseAddress
{
- value = "1099456";
+ value = "1263296";
type = "String";
}
}
@@ -810,7 +810,7 @@
{
datum baseAddress
{
- value = "1100248";
+ value = "1264088";
type = "String";
}
}
@@ -826,7 +826,7 @@
{
datum baseAddress
{
- value = "1099008";
+ value = "1262848";
type = "String";
}
}
@@ -842,7 +842,7 @@
{
datum baseAddress
{
- value = "1100160";
+ value = "1264000";
type = "String";
}
}
@@ -863,7 +863,7 @@
{
datum baseAddress
{
- value = "1100296";
+ value = "1264136";
type = "String";
}
}
@@ -884,7 +884,7 @@
{
datum baseAddress
{
- value = "1100288";
+ value = "1264128";
type = "String";
}
}
@@ -905,7 +905,7 @@
{
datum baseAddress
{
- value = "1100032";
+ value = "1263872";
type = "String";
}
}
@@ -921,7 +921,7 @@
{
datum baseAddress
{
- value = "1100000";
+ value = "1263840";
type = "String";
}
}
@@ -942,7 +942,7 @@
{
datum baseAddress
{
- value = "1099712";
+ value = "1263552";
type = "String";
}
}
@@ -958,7 +958,7 @@
{
datum baseAddress
{
- value = "1097728";
+ value = "1261568";
type = "String";
}
}
@@ -979,7 +979,7 @@
{
datum baseAddress
{
- value = "1100280";
+ value = "1264120";
type = "String";
}
}
@@ -1000,7 +1000,7 @@
{
datum baseAddress
{
- value = "1100272";
+ value = "1264112";
type = "String";
}
}
@@ -1016,7 +1016,7 @@
{
datum baseAddress
{
- value = "1100208";
+ value = "1264048";
type = "String";
}
}
@@ -1032,7 +1032,7 @@
{
datum baseAddress
{
- value = "1100240";
+ value = "1264080";
type = "String";
}
}
@@ -1048,7 +1048,7 @@
{
datum baseAddress
{
- value = "1048576";
+ value = "98304";
type = "String";
}
}
@@ -1069,7 +1069,7 @@
{
datum baseAddress
{
- value = "1100064";
+ value = "1263904";
type = "String";
}
}
@@ -1085,7 +1085,7 @@
{
datum baseAddress
{
- value = "1100112";
+ value = "1263952";
type = "String";
}
}
@@ -1101,7 +1101,7 @@
{
datum baseAddress
{
- value = "1100096";
+ value = "1263936";
type = "String";
}
}
@@ -1133,7 +1133,7 @@
{
datum baseAddress
{
- value = "1099648";
+ value = "1263488";
type = "String";
}
}
@@ -1149,7 +1149,7 @@
{
datum baseAddress
{
- value = "1100264";
+ value = "1264104";
type = "String";
}
}
@@ -1165,7 +1165,7 @@
{
datum baseAddress
{
- value = "1100144";
+ value = "1263984";
type = "String";
}
}
@@ -1181,7 +1181,7 @@
{
datum baseAddress
{
- value = "1100224";
+ value = "1264064";
type = "String";
}
}
@@ -1197,7 +1197,7 @@
{
datum baseAddress
{
- value = "1100216";
+ value = "1264056";
type = "String";
}
}
@@ -1261,7 +1261,7 @@
{
datum baseAddress
{
- value = "1099872";
+ value = "1263712";
type = "String";
}
}
@@ -1319,7 +1319,7 @@
{
datum baseAddress
{
- value = "1098240";
+ value = "1262080";
type = "String";
}
}
@@ -8497,7 +8497,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C400' end='0x10C480' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C480' end='0x10C500' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C500' end='0x10C580' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C580' end='0x10C5C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C5C0' end='0x10C600' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C600' end='0x10C640' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C640' end='0x10C680' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C680' end='0x10C6C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C6C0' end='0x10C700' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C700' end='0x10C740' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C740' end='0x10C780' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10C800' end='0x10C820' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10C820' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10C840' end='0x10C860' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10C860' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C880' end='0x10C8A0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10C8A0' end='0x10C8C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10C8C0' end='0x10C8E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10C8E0' end='0x10C900' datawidth='32' /><slave name='reg_epcs.mem' start='0x10C900' end='0x10C920' datawidth='32' /><slave name='reg_remu.mem' start='0x10C920' end='0x10C940' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10C940' end='0x10C950' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10C950' end='0x10C960' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C960' end='0x10C970' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10C970' end='0x10C980' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10C980' end='0x10C990' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10C990' end='0x10C9A0' datawidth='32' /><slave name='pio_pps.mem' start='0x10C9A0' end='0x10C9B0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10C9B0' end='0x10C9B8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10C9B8' end='0x10C9C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10C9C0' end='0x10C9C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10C9C8' end='0x10C9D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10C9D0' end='0x10C9D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10C9D8' end='0x10C9E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10C9E0' end='0x10C9E8' datawidth='32' /><slave name='reg_si.mem' start='0x10C9E8' end='0x10C9F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10C9F0' end='0x10C9F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10C9F8' end='0x10CA00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CA00' end='0x10CA08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CA08' end='0x10CA10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CA10' end='0x10CA18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xC0000' end='0xE0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xE0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x110000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x110000' end='0x120000' datawidth='32' /><slave name='ram_wg.mem' start='0x120000' end='0x130000' datawidth='32' /><slave name='jesd204b.mem' start='0x130000' end='0x134000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x134000' end='0x134200' datawidth='32' /><slave name='reg_wg.mem' start='0x134200' end='0x134300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x134300' end='0x134400' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x134400' end='0x134480' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x134480' end='0x134500' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x134500' end='0x134580' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x134580' end='0x1345C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x1345C0' end='0x134600' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x134600' end='0x134640' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x134640' end='0x134680' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x134680' end='0x1346C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x1346C0' end='0x134700' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x134700' end='0x134740' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x134740' end='0x134780' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x134780' end='0x1347C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x1347C0' end='0x134800' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x134800' end='0x134820' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x134820' end='0x134840' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x134840' end='0x134860' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x134860' end='0x134880' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x134880' end='0x1348A0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x1348A0' end='0x1348C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x1348C0' end='0x1348E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x1348E0' end='0x134900' datawidth='32' /><slave name='reg_epcs.mem' start='0x134900' end='0x134920' datawidth='32' /><slave name='reg_remu.mem' start='0x134920' end='0x134940' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x134940' end='0x134950' datawidth='32' /><slave name='reg_ring_info.mem' start='0x134950' end='0x134960' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x134960' end='0x134970' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x134970' end='0x134980' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x134980' end='0x134990' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x134990' end='0x1349A0' datawidth='32' /><slave name='pio_pps.mem' start='0x1349A0' end='0x1349B0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x1349B0' end='0x1349B8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x1349B8' end='0x1349C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x1349C0' end='0x1349C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x1349C8' end='0x1349D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x1349D0' end='0x1349D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x1349D8' end='0x1349E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x1349E0' end='0x1349E8' datawidth='32' /><slave name='reg_si.mem' start='0x1349E8' end='0x1349F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x1349F0' end='0x1349F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x1349F8' end='0x134A00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x134A00' end='0x134A08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x134A08' end='0x134A10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x134A10' end='0x134A18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -19557,7 +19557,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19626,7 +19626,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -19855,7 +19855,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20033,11 +20033,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>16</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -20137,7 +20137,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20206,7 +20206,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>65536</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -20435,7 +20435,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>14</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20635,7 +20635,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20699,7 +20699,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20768,7 +20768,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -21174,11 +21174,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>17</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -21215,7 +21215,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21279,7 +21279,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21348,7 +21348,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -26340,7 +26340,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26404,7 +26404,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26473,7 +26473,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -26879,11 +26879,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>17</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -26920,7 +26920,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26984,7 +26984,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27053,7 +27053,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -96093,7 +96093,7 @@
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010ca10" />
+ <parameter name="baseAddress" value="0x00134a10" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96173,7 +96173,7 @@
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c9a0" />
+ <parameter name="baseAddress" value="0x001349a0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96213,7 +96213,7 @@
start="cpu_0.data_master"
end="reg_remu.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c920" />
+ <parameter name="baseAddress" value="0x00134920" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96233,7 +96233,7 @@
start="cpu_0.data_master"
end="reg_epcs.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c900" />
+ <parameter name="baseAddress" value="0x00134900" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96253,7 +96253,7 @@
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010ca08" />
+ <parameter name="baseAddress" value="0x00134a08" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96273,7 +96273,7 @@
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010ca00" />
+ <parameter name="baseAddress" value="0x00134a00" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96293,7 +96293,7 @@
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c9f8" />
+ <parameter name="baseAddress" value="0x001349f8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96313,7 +96313,7 @@
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c9f0" />
+ <parameter name="baseAddress" value="0x001349f0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96333,7 +96333,7 @@
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c8e0" />
+ <parameter name="baseAddress" value="0x001348e0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96353,7 +96353,7 @@
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c7c0" />
+ <parameter name="baseAddress" value="0x001347c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96373,7 +96373,7 @@
start="cpu_0.data_master"
end="ram_st_sst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000f0000" />
+ <parameter name="baseAddress" value="0x000e0000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96393,7 +96393,7 @@
start="cpu_0.data_master"
end="reg_si.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c9e8" />
+ <parameter name="baseAddress" value="0x001349e8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96413,7 +96413,7 @@
start="cpu_0.data_master"
end="ram_fil_coefs.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000e0000" />
+ <parameter name="baseAddress" value="0x000c0000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96453,7 +96453,7 @@
start="cpu_0.data_master"
end="reg_aduh_monitor.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c300" />
+ <parameter name="baseAddress" value="0x00134300" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96473,7 +96473,7 @@
start="cpu_0.data_master"
end="ram_wg.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000d0000" />
+ <parameter name="baseAddress" value="0x00120000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96493,7 +96493,7 @@
start="cpu_0.data_master"
end="reg_dp_shiftram.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c500" />
+ <parameter name="baseAddress" value="0x00134500" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96513,7 +96513,7 @@
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c9e0" />
+ <parameter name="baseAddress" value="0x001349e0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96533,7 +96533,7 @@
start="cpu_0.data_master"
end="reg_bsn_source_v2.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c8c0" />
+ <parameter name="baseAddress" value="0x001348c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96553,7 +96553,7 @@
start="cpu_0.data_master"
end="reg_wg.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c200" />
+ <parameter name="baseAddress" value="0x00134200" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96593,7 +96593,7 @@
start="cpu_0.data_master"
end="jesd204b.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00108000" />
+ <parameter name="baseAddress" value="0x00130000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96613,7 +96613,7 @@
start="cpu_0.data_master"
end="reg_dp_selector.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c9d8" />
+ <parameter name="baseAddress" value="0x001349d8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96633,7 +96633,7 @@
start="cpu_0.data_master"
end="ram_ss_ss_wide.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x000c0000" />
+ <parameter name="baseAddress" value="0x00110000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96653,7 +96653,7 @@
start="cpu_0.data_master"
end="reg_bf_scale.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c990" />
+ <parameter name="baseAddress" value="0x00134990" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96673,7 +96673,7 @@
start="cpu_0.data_master"
end="reg_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c000" />
+ <parameter name="baseAddress" value="0x00134000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96693,7 +96693,7 @@
start="cpu_0.data_master"
end="reg_dp_xonoff.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c980" />
+ <parameter name="baseAddress" value="0x00134980" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96733,7 +96733,7 @@
start="cpu_0.data_master"
end="reg_sdp_info.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c780" />
+ <parameter name="baseAddress" value="0x00134780" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96753,7 +96753,7 @@
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c9d0" />
+ <parameter name="baseAddress" value="0x001349d0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96773,7 +96773,7 @@
start="cpu_0.data_master"
end="reg_nw_10gbe_mac.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00100000" />
+ <parameter name="baseAddress" value="0x00018000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96793,7 +96793,7 @@
start="cpu_0.data_master"
end="reg_diag_data_buffer_bsn.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c480" />
+ <parameter name="baseAddress" value="0x00134480" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96833,7 +96833,7 @@
start="cpu_0.data_master"
end="pio_jesd_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c9c8" />
+ <parameter name="baseAddress" value="0x001349c8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96853,7 +96853,7 @@
start="cpu_0.data_master"
end="reg_stat_enable_sst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c9c0" />
+ <parameter name="baseAddress" value="0x001349c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96893,7 +96893,7 @@
start="cpu_0.data_master"
end="reg_stat_enable_bst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c970" />
+ <parameter name="baseAddress" value="0x00134970" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96933,7 +96933,7 @@
start="cpu_0.data_master"
end="reg_crosslets_info.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c740" />
+ <parameter name="baseAddress" value="0x00134740" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -96973,7 +96973,7 @@
start="cpu_0.data_master"
end="reg_stat_enable_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c9b8" />
+ <parameter name="baseAddress" value="0x001349b8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97013,7 +97013,7 @@
start="cpu_0.data_master"
end="reg_bsn_sync_scheduler_xsub.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c700" />
+ <parameter name="baseAddress" value="0x00134700" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97033,7 +97033,7 @@
start="cpu_0.data_master"
end="ram_st_histogram.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00018000" />
+ <parameter name="baseAddress" value="0x8000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97053,7 +97053,7 @@
start="cpu_0.data_master"
end="reg_nof_crosslets.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c9b0" />
+ <parameter name="baseAddress" value="0x001349b0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97073,7 +97073,7 @@
start="cpu_0.data_master"
end="reg_bsn_align_v2_xsub.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c400" />
+ <parameter name="baseAddress" value="0x00134400" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97093,7 +97093,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_aligned_xsub.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c8a0" />
+ <parameter name="baseAddress" value="0x001348a0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97113,7 +97113,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_xst_offload.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c880" />
+ <parameter name="baseAddress" value="0x00134880" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97193,7 +97193,7 @@
start="cpu_0.data_master"
end="reg_dp_block_validate_err_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c6c0" />
+ <parameter name="baseAddress" value="0x001346c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97213,7 +97213,7 @@
start="cpu_0.data_master"
end="reg_dp_block_validate_bsn_at_sync_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c960" />
+ <parameter name="baseAddress" value="0x00134960" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97233,7 +97233,7 @@
start="cpu_0.data_master"
end="reg_ring_info.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c950" />
+ <parameter name="baseAddress" value="0x00134950" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97253,7 +97253,7 @@
start="cpu_0.data_master"
end="reg_tr_10gbe_eth10g.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c860" />
+ <parameter name="baseAddress" value="0x00134860" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97313,7 +97313,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_sst_offload.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c840" />
+ <parameter name="baseAddress" value="0x00134840" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97333,7 +97333,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_bst_offload.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c680" />
+ <parameter name="baseAddress" value="0x00134680" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97353,7 +97353,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_beamlet_output.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c640" />
+ <parameter name="baseAddress" value="0x00134640" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97373,7 +97373,7 @@
start="cpu_0.data_master"
end="reg_bsn_align_v2_bf.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c820" />
+ <parameter name="baseAddress" value="0x00134820" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97413,7 +97413,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_aligned_bf.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c600" />
+ <parameter name="baseAddress" value="0x00134600" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97433,7 +97433,7 @@
start="cpu_0.data_master"
end="reg_ring_lane_info_bf.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c940" />
+ <parameter name="baseAddress" value="0x00134940" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97453,7 +97453,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_ring_rx_bf.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c5c0" />
+ <parameter name="baseAddress" value="0x001345c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97473,7 +97473,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_ring_tx_bf.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c580" />
+ <parameter name="baseAddress" value="0x00134580" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97513,7 +97513,7 @@
start="cpu_0.data_master"
end="reg_dp_block_validate_bsn_at_sync_bf.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c800" />
+ <parameter name="baseAddress" value="0x00134800" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -97553,7 +97553,7 @@
start="cpu_0.data_master"
end="ram_equalizer_gains.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x8000" />
+ <parameter name="baseAddress" value="0x00100000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..dae5fadcbac5f0875667aa45de31828b4f53938c
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd
@@ -0,0 +1,165 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author : R. van der Walle
+-- Purpose:
+-- Wrapper for Lofar2 SDP Station full design
+-- Description:
+-- Unb2c version for lab testing
+-- Contains complete AIT input stage with 12 ADC streams, FSUB, XSUB, BF and RING
+
+
+LIBRARY IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb2c_board_lib.unb2c_board_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY disturb2_unb2c_sdp_station_full IS
+ GENERIC (
+ g_design_name : STRING := "disturb2_unb2c_sdp_station_full";
+ g_design_note : STRING := "Disturb2 SDP station full design";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2c_board_aux.testio_w-1 DOWNTO 0);
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+
+ -- Transceiver clocks
+ SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
+ -- LEDs
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+
+ -- ring transceivers
+ RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS => '0'); -- Using qsfp bus width also for ring interfaces
+ RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0);
+
+ -- back transceivers (note only 12 are used in unb2c)
+ BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b-1 DOWNTO 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
+ BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
+
+ -- jesd204b syncronization signals (4 syncs)
+ JESD204B_SYSREF : IN STD_LOGIC;
+ JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0) -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ );
+END disturb2_unb2c_sdp_station_full;
+
+ARCHITECTURE str OF disturb2_unb2c_sdp_station_full IS
+
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 DOWNTO 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC;
+
+BEGIN
+
+ -- Mapping between JESD signal names and UNB2B pin/schematic names
+ JESD204B_REFCLK <= BCK_REF_CLK;
+ JESD204B_SERIAL_DATA <= BCK_RX;
+ JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
+
+ u_revision : ENTITY lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
+END str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..273a627af9469a3f619164eee8ded453c302cb7f
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full_pins.tcl
@@ -0,0 +1,26 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..1b6f161754fd025476117c836247694ef5ff6491
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/hdllib.cfg
@@ -0,0 +1,129 @@
+hdl_lib_name = disturb2_unb2c_sdp_station_full
+hdl_library_clause_name = disturb2_unb2c_sdp_station_full_lib
+hdl_lib_uses_synth = common mm technology unb2c_board lofar2_unb2c_sdp_station
+hdl_lib_uses_sim = eth
+hdl_lib_technology = ip_arria10_e2sg
+
+ synth_files =
+ disturb2_unb2c_sdp_station_full.vhd
+
+test_bench_files =
+
+regression_test_vhdl =
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ # Overwrite bf weights with sim data
+ ../../tb/data data
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ ../../quartus .
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+
+# use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
+quartus_sdc_files =
+ ../../quartus/lofar2_unb2c_sdp_station.sdc
+ #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+
+quartus_tcl_files =
+ disturb2_unb2c_sdp_station_full_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/disturb2_unb2c_sdp_station_full/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5080e013c8db75e269d780ae0f8b2b41130ee47f
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd
@@ -0,0 +1,140 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author : R. van der Walle
+-- Purpose:
+-- Wrapper for Lofar2 SDP Station full wg design.
+-- Description:
+-- Unb2c version for lab testing of SDP using the WG.
+-- Contains AIT input stage with WG, FSUB, XSUB, BF and RING, so without ADC JESD.
+
+
+LIBRARY IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb2c_board_lib.unb2c_board_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY disturb2_unb2c_sdp_station_full_wg IS
+ GENERIC (
+ g_design_name : STRING := "disturb2_unb2c_sdp_station_full_wg";
+ g_design_note : STRING := "Disturb2 SDP station full design WG";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2c_board_aux.testio_w-1 DOWNTO 0);
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+
+ -- Transceiver clocks
+ SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
+ -- LEDs
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+
+ -- ring transceivers
+ RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS => '0'); -- Using qsfp bus width also for ring interfaces
+ RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0)
+ );
+END disturb2_unb2c_sdp_station_full_wg;
+
+ARCHITECTURE str OF disturb2_unb2c_sdp_station_full_wg IS
+
+BEGIN
+
+ u_revision : ENTITY lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX
+ );
+END str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4ceebdedad386e07a109627cae9cd0a15507fa48
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg_pins.tcl
@@ -0,0 +1,25 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..bc7d3a1b7e4959f22f31bbbd80ca7a282ee65b4e
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/hdllib.cfg
@@ -0,0 +1,129 @@
+hdl_lib_name = disturb2_unb2c_sdp_station_full_wg
+hdl_library_clause_name = disturb2_unb2c_sdp_station_full_wg_lib
+hdl_lib_uses_synth = common mm technology unb2c_board lofar2_unb2c_sdp_station
+hdl_lib_uses_sim = eth
+hdl_lib_technology = ip_arria10_e2sg
+
+ synth_files =
+ disturb2_unb2c_sdp_station_full_wg.vhd
+
+test_bench_files =
+
+regression_test_vhdl =
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ # Overwrite bf weights with sim data
+ ../../tb/data data
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ ../../quartus .
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+
+# use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
+quartus_sdc_files =
+ ../../quartus/lofar2_unb2c_sdp_station.sdc
+ #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+
+quartus_tcl_files =
+ disturb2_unb2c_sdp_station_full_wg_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/disturb2_unb2c_sdp_station_full_wg/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
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+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
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+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
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+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
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+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
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+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/freq_shift_half_subband_2048x16_im_re.hex b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/freq_shift_half_subband_2048x16_im_re.hex
new file mode 100644
index 0000000000000000000000000000000000000000..19547d8205c37b81f704cafae5ac8ba4fd17beaf
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/freq_shift_half_subband_2048x16_im_re.hex
@@ -0,0 +1,2049 @@
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diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/gains_1024_complex_16b13f_unit_10.hex b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/gains_1024_complex_16b13f_unit_10.hex
new file mode 100644
index 0000000000000000000000000000000000000000..f50bff279ae778401f565a9605229bc1206086bf
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/gains_1024_complex_16b13f_unit_10.hex
@@ -0,0 +1,1025 @@
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diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/gains_1024_complex_16b13f_unit_11.hex b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/gains_1024_complex_16b13f_unit_11.hex
new file mode 100644
index 0000000000000000000000000000000000000000..f50bff279ae778401f565a9605229bc1206086bf
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/gains_1024_complex_16b13f_unit_11.hex
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diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/gains_1024_complex_16b13f_unit_6.hex b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/gains_1024_complex_16b13f_unit_6.hex
new file mode 100644
index 0000000000000000000000000000000000000000..f50bff279ae778401f565a9605229bc1206086bf
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/gains_1024_complex_16b13f_unit_6.hex
@@ -0,0 +1,1025 @@
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diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/gains_1024_complex_16b13f_unit_7.hex b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/gains_1024_complex_16b13f_unit_7.hex
new file mode 100644
index 0000000000000000000000000000000000000000..f50bff279ae778401f565a9605229bc1206086bf
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/gains_1024_complex_16b13f_unit_7.hex
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diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/gains_1024_complex_16b13f_unit_8.hex b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/gains_1024_complex_16b13f_unit_8.hex
new file mode 100644
index 0000000000000000000000000000000000000000..f50bff279ae778401f565a9605229bc1206086bf
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/gains_1024_complex_16b13f_unit_8.hex
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diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/gains_1024_complex_16b13f_unit_9.hex b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/gains_1024_complex_16b13f_unit_9.hex
new file mode 100644
index 0000000000000000000000000000000000000000..f50bff279ae778401f565a9605229bc1206086bf
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/gains_1024_complex_16b13f_unit_9.hex
@@ -0,0 +1,1025 @@
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diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
index 1ef4c3b4ab9444431c638f49ef5a2d7289010c23..032a29e62fdffac0ad0b4bed69e0a9599d4aee7d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
@@ -777,6 +777,7 @@ BEGIN
g_scope_selected_subband => g_scope_selected_subband,
g_no_jesd => c_revision_select.no_jesd,
g_use_fsub => c_revision_select.use_fsub,
+ g_use_oversample => c_revision_select.use_oversample,
g_use_xsub => c_revision_select.use_xsub,
g_use_bf => c_revision_select.use_bf,
g_use_ring => c_revision_select.use_ring,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
index 903b88e1ec98003c2d99c329173ef30ccc424c9f..ce8ffd3ab09523951ff6db68a13ce0696c1ea3ec 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
@@ -34,20 +34,23 @@ PACKAGE lofar2_unb2c_sdp_station_pkg IS
TYPE t_lofar2_unb2c_sdp_station_config IS RECORD
no_jesd : BOOLEAN;
use_fsub : BOOLEAN;
+ use_oversample : BOOLEAN;
use_bf : BOOLEAN;
use_xsub : BOOLEAN;
use_ring : BOOLEAN;
P_sq : NATURAL;
END RECORD;
- CONSTANT c_ait : t_lofar2_unb2c_sdp_station_config := (FALSE, FALSE, FALSE, FALSE, FALSE, 0);
- CONSTANT c_fsub : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE, FALSE, FALSE, FALSE, 0);
- CONSTANT c_bf : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE, TRUE, FALSE, FALSE, 0);
- CONSTANT c_bf_ring : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE, TRUE, FALSE, TRUE, 0);
- CONSTANT c_xsub_one : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE, FALSE, TRUE, FALSE, 1);
- CONSTANT c_xsub_ring : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE, FALSE, TRUE, TRUE, 9);
- CONSTANT c_full_wg : t_lofar2_unb2c_sdp_station_config := (TRUE, TRUE, TRUE, TRUE, TRUE, 9);
- CONSTANT c_full : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE, TRUE, TRUE, TRUE, 9);
+ CONSTANT c_ait : t_lofar2_unb2c_sdp_station_config := (FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, 0);
+ CONSTANT c_fsub : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, 0);
+ CONSTANT c_bf : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE, FALSE, TRUE, FALSE, FALSE, 0);
+ CONSTANT c_bf_ring : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE, FALSE, TRUE, FALSE, TRUE, 0);
+ CONSTANT c_xsub_one : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE, FALSE, FALSE, TRUE, FALSE, 1);
+ CONSTANT c_xsub_ring : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE, FALSE, FALSE, TRUE, TRUE, 9);
+ CONSTANT c_full_wg : t_lofar2_unb2c_sdp_station_config := (TRUE, TRUE, FALSE, TRUE, TRUE, TRUE, 9);
+ CONSTANT c_full_os : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE, TRUE, TRUE, TRUE, TRUE, 9);
+ CONSTANT c_full_wg_os : t_lofar2_unb2c_sdp_station_config := (TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, 9);
+ CONSTANT c_full : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE, FALSE, TRUE, TRUE, TRUE, 9);
-- Function to select the revision configuration.
FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_lofar2_unb2c_sdp_station_config;
@@ -67,6 +70,8 @@ PACKAGE BODY lofar2_unb2c_sdp_station_pkg IS
ELSIF g_design_name = "lofar2_unb2c_sdp_station_xsub_one" THEN RETURN c_xsub_one;
ELSIF g_design_name = "lofar2_unb2c_sdp_station_xsub_ring" THEN RETURN c_xsub_ring;
ELSIF g_design_name = "lofar2_unb2c_sdp_station_full_wg" THEN RETURN c_full_wg;
+ ELSIF g_design_name = "disturb2_unb2c_sdp_station_full" THEN RETURN c_full_os;
+ ELSIF g_design_name = "disturb2_unb2c_sdp_station_full_wg" THEN RETURN c_full_wg_os;
ELSE RETURN c_full;
END IF;
END;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
index 12f93299f3749dd70aeada6cd42e001a944071d7..c8f7511c6e9e19f71e91ec67d526c2f11eecb18a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
@@ -92,14 +92,14 @@ PACKAGE qsys_lofar2_unb2c_sdp_station_pkg IS
ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0); -- export
ram_equalizer_gains_clk_export : out std_logic; -- export
ram_equalizer_gains_read_export : out std_logic; -- export
ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
ram_equalizer_gains_reset_export : out std_logic; -- export
ram_equalizer_gains_write_export : out std_logic; -- export
ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
ram_fil_coefs_clk_export : out std_logic; -- export
ram_fil_coefs_read_export : out std_logic; -- export
ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
@@ -134,7 +134,7 @@ PACKAGE qsys_lofar2_unb2c_sdp_station_pkg IS
ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_st_histogram_read_export : out std_logic; -- export
ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_st_sst_address_export : out std_logic_vector(14 downto 0); -- export
ram_st_sst_clk_export : out std_logic; -- export
ram_st_sst_read_export : out std_logic; -- export
ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
diff --git a/applications/lofar2/libraries/sdp/hdllib.cfg b/applications/lofar2/libraries/sdp/hdllib.cfg
index 380e327a6bc72885dc4b16121b43a70e32146aca..e351f1ec0688cb36d9f5ecd55cce061a3e9bd5d2 100644
--- a/applications/lofar2/libraries/sdp/hdllib.cfg
+++ b/applications/lofar2/libraries/sdp/hdllib.cfg
@@ -18,6 +18,7 @@ synth_files =
src/vhdl/sdp_crosslets_subband_select.vhd
src/vhdl/node_sdp_adc_input_and_timing.vhd
src/vhdl/node_sdp_filterbank.vhd
+ src/vhdl/node_sdp_oversampled_filterbank.vhd
src/vhdl/node_sdp_beamformer.vhd
src/vhdl/node_sdp_correlator.vhd
src/vhdl/sdp_station.vhd
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 09f12a015b8f26991a49d1988d549e696a72cf65..3b5d57a7f320031afaab78b9d63b4dc4e0dae874 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -177,9 +177,9 @@ PACKAGE sdp_pkg is
c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline); -- = c_wpfb_lofar2_subbands_dts_18b
CONSTANT c_sdp_wpfb_complex_subbands : t_wpfb :=
- (1, c_disturb_N_fft, 0, c_disturb_S_pn,
- c_disturb_N_taps, 1, c_disturb_W_adc, 23, c_disturb_W_fir_coef,
- true, false, false, 23, c_disturb_W_subband, 1, 24, 1, true, 54, c_disturb_W_statistic_sz, 195313,
+ (1, c_sdp_N_fft, 0, c_sdp_S_pn,
+ c_sdp_N_taps, 1, c_sdp_W_adc, 23, c_sdp_W_fir_coef,
+ true, false, false, 23, c_sdp_W_subband, 1, 24, 1, true, 54, c_sdp_W_statistic_sz, 195313,
c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline); -- = c_wpfb_lofar2_subbands_dts_18b
-- DC gain of WPFB FIR filter obtained from applications/lofar2/model/run_pfir_coef.m using application = 'lofar_subband'
@@ -735,7 +735,7 @@ PACKAGE BODY sdp_pkg IS
RETURN sel_a_b(g_statistics_type="BST", 1,
sel_a_b(g_statistics_type="XST", P_sq * N_crosslets,
sel_a_b(g_statistics_type="SST", S_pn,
- c_sdp_V_oversample * S_pn)); -- SST_OS
+ c_sdp_V_oversample * S_pn))); -- SST_OS
END func_sdp_get_stat_nof_packets;
FUNCTION func_sdp_get_stat_nof_packets(g_statistics_type : STRING) RETURN NATURAL IS
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index c33e0a5e37e01a4e1d0ef02d084b79b119df2e47..cdb5f276b171f38e27c45bab9847e2074fc92556 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -51,6 +51,7 @@ ENTITY sdp_station IS
g_scope_selected_subband : NATURAL := 0;
g_no_jesd : BOOLEAN := FALSE;
g_use_fsub : BOOLEAN := TRUE;
+ g_use_oversample : BOOLEAN := FALSE;
g_use_xsub : BOOLEAN := TRUE;
g_use_bf : BOOLEAN := TRUE;
g_use_ring : BOOLEAN := TRUE;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
index 05d222f417f158351779bbee469fc7b5543f3124..f337da198f9eb4334e72899c5bdf348db38ee59b 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
@@ -41,14 +41,15 @@ USE work.sdp_pkg.ALL;
ENTITY sdp_subband_equalizer IS
GENERIC (
- g_gains_file_name : STRING := "UNUSED"
+ g_gains_file_name : STRING := "UNUSED";
+ g_nof_streams : NATURAL := c_sdp_P_pfb
);
PORT (
dp_clk : IN STD_LOGIC;
dp_rst : IN STD_LOGIC;
- in_sosi_arr : IN t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
- out_sosi_arr : OUT t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
+ in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
@@ -65,7 +66,7 @@ ARCHITECTURE str OF sdp_subband_equalizer IS
SIGNAL cnt : NATURAL RANGE 0 TO c_sdp_Q_fft * c_sdp_N_sub-1;
SIGNAL gains_rd_address : STD_LOGIC_VECTOR(c_gain_addr_w-1 DOWNTO 0);
- SIGNAL dp_gain_serial_out_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
+ SIGNAL dp_gain_serial_out_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
BEGIN
---------------------------------------------------------------
@@ -113,7 +114,7 @@ BEGIN
---------------------------------------------------------------
u_mms_dp_gain_serial_arr : ENTITY dp_lib.mms_dp_gain_serial_arr
GENERIC MAP (
- g_nof_streams => c_sdp_P_pfb,
+ g_nof_streams => g_nof_streams,
g_nof_gains => c_sdp_Q_fft * c_sdp_N_sub,
g_complex_data => TRUE,
g_complex_gain => TRUE,
@@ -143,7 +144,7 @@ BEGIN
---------------------------------------------------------------
-- Requantize
---------------------------------------------------------------
- gen_dp_requantize : FOR I IN 0 TO c_sdp_P_pfb-1 GENERATE
+ gen_dp_requantize : FOR I IN 0 TO g_nof_streams-1 GENERATE
u_dp_requantize : ENTITY dp_lib.dp_requantize
GENERIC MAP (
g_complex => TRUE,