diff --git a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
index 03dc9bf28e4ef3fd0f52b32d9361e6b3f695562a..2da2fedde24cb011c55d1e739c71d1001169b752 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
@@ -24,13 +24,12 @@
# file msim_setup.tcl.
# The purpose of this file is to compile all files required for the XAUI IP -
# which is quite a list and tedious to have to add to the MPF (also in the
-# correct compile order). Bonus of this is also that there will be no errors
-# when making all_mod without having run the XAUI megawizard first.
+# correct compile order).
+# EK: The model files in phy_xaui_0_sim/ are suitable for all hard xaui IP variants.
-set IP_DIR "$env(UNB)/Firmware/modules/tr_xaui/src/ip/megawizard/generated/phy_xaui_0_sim"
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim"
-vlib ./work/
-#map work ./work/ --DS: requires MPF to be write enabled for some reason...
+#vlib ./work/ ;# EK: Assume library work already exists
vlog -sv "$IP_DIR/altera_xcvr_xaui/altera_xcvr_functions.sv" -work work
vlog -sv "$IP_DIR/altera_xcvr_xaui/mentor/altera_xcvr_functions.sv" -work work
@@ -100,11 +99,3 @@ vlog -sv "$IP_DIR/altera_xcvr_xaui/alt_xcvr_arbiter.sv"
vlog -sv "$IP_DIR/altera_xcvr_xaui/alt_xcvr_m2s.sv" -work work
vlog -sv "$IP_DIR/altera_xcvr_xaui/mentor/alt_xcvr_arbiter.sv" -work work
vlog -sv "$IP_DIR/altera_xcvr_xaui/mentor/alt_xcvr_m2s.sv" -work work
-vcom "$IP_DIR/phy_xaui_0.vhd"
-
-set IP_DIR "$env(UNB)/Firmware/modules/tr_xaui/src/ip/megawizard/generated/phy_xaui_1_sim"
-vcom "$IP_DIR/phy_xaui_1.vhd"
-
-set IP_DIR "$env(UNB)/Firmware/modules/tr_xaui/src/ip/megawizard/generated/phy_xaui_2_sim"
-vcom "$IP_DIR/phy_xaui_2.vhd"
-
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
index 4e3483b064d607e0b42f0b7e12a55173de5bf74c..42bd765382d23d53b49cc37e687053834ea95b73 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
@@ -27,10 +27,10 @@
# correct compile order). Bonus of this is also that there will be no errors
# when making all_mod without having run the XAUI megawizard first.
-set IP_DIR "$env(UNB)/Firmware/modules/tr_xaui/src/ip/megawizard/generated/phy_xaui_soft_sim"
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim"
+
+#vlib ./work/ ;# EK: Assume library work already exists
-vlib ./work/
-#map work ./work/ --DS: requires MPF to be write enabled for some reason...
vlog -sv "$IP_DIR/altera_xcvr_xaui/altera_xcvr_functions.sv" -work work
vlog -sv "$IP_DIR/altera_xcvr_xaui/mentor/altera_xcvr_functions.sv" -work work
@@ -127,6 +127,3 @@ vlog -sv "$IP_DIR/altera_xcvr_xaui/alt_xcvr_arbiter.sv"
vlog -sv "$IP_DIR/altera_xcvr_xaui/alt_xcvr_m2s.sv" -work work
vlog -sv "$IP_DIR/altera_xcvr_xaui/mentor/alt_xcvr_arbiter.sv" -work work
vlog -sv "$IP_DIR/altera_xcvr_xaui/mentor/alt_xcvr_m2s.sv" -work work
-vcom "$IP_DIR/phy_xaui_soft.vhd"
-
-
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generate_ip.sh b/libraries/technology/ip_stratixiv/phy_xaui/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..eba08183b5eb54e615333f135583a0726af01ec8
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generate_ip.sh
@@ -0,0 +1,57 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate phy_xaui IP with MegaWizard
+# Description:
+# Generate the phy_xaui IP in a separate generated/ subdirectory. Therefore first copy the MegaWizard variation file in the 'generated' output dir, because:
+# 1) setting the output dir is not an option in the MegaWizard
+# 2) The MegaWizard overwrites the variation file sometimes - we don't want that as it could be hand-modified with e.g. added generics
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+# The generated files for Quartus v11.1 that are needed for simulation and synthesis have been committed in SVN, so it is not necessary to run this
+# generate_ip.sh script again. Files that are not needed have not been committed in SVN.
+#
+# Remarks:
+# . This dedicated script is Derived from the generic script $UNB/Firmware/software/build/unb_mgw
+#
+if ! [ -d "generated" ]; then
+ mkdir generated
+fi
+cd generated
+cp ../ip_stratixiv_phy_xaui_0.vhd .
+cp ../ip_stratixiv_phy_xaui_1.vhd .
+cp ../ip_stratixiv_phy_xaui_2.vhd .
+cp ../ip_stratixiv_phy_xaui_soft.vhd .
+
+qmegawiz -silent -f:$UNB/Firmware/software/build/unb_mgw_params.txt ip_stratixiv_phy_xaui_0.vhd
+qmegawiz -silent -f:$UNB/Firmware/software/build/unb_mgw_params.txt ip_stratixiv_phy_xaui_1.vhd
+qmegawiz -silent -f:$UNB/Firmware/software/build/unb_mgw_params.txt ip_stratixiv_phy_xaui_2.vhd
+qmegawiz -silent -f:$UNB/Firmware/software/build/unb_mgw_params.txt ip_stratixiv_phy_xaui_soft.vhd
+
+rm ip_stratixiv_phy_xaui_0.vhd
+rm ip_stratixiv_phy_xaui_1.vhd
+rm ip_stratixiv_phy_xaui_2.vhd
+rm ip_stratixiv_phy_xaui_soft.vhd
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0.qip b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0.qip
new file mode 100644
index 0000000000000000000000000000000000000000..d682dbd902481399f0c4232eff93bdce767d2be3
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0.qip
@@ -0,0 +1,47 @@
+set_global_assignment -entity "ip_stratixiv_phy_xaui_0" -library "lib_ip_stratixiv_phy_xaui_0" -name IP_TOOL_NAME "altera_xcvr_xaui"
+set_global_assignment -entity "ip_stratixiv_phy_xaui_0" -library "lib_ip_stratixiv_phy_xaui_0" -name IP_TOOL_VERSION "11.1sp2"
+set_global_assignment -entity "ip_stratixiv_phy_xaui_0" -library "lib_ip_stratixiv_phy_xaui_0" -name IP_TOOL_ENV "mwpim"
+
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name VHDL_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0.vhd]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/altera_xcvr_functions.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/altera_xcvr_xaui.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/hxaui_csr_h.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/hxaui_csr.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xcvr_mgmt2dec_phyreconfig.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xcvr_mgmt2dec_xaui.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_pma_ch_controller_tgx.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_pma_controller_tgx.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_reset_ctrl_lego.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_reset_ctrl_tgx_cdrauto.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xcvr_resync.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xcvr_csr_common_h.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xcvr_csr_common.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xcvr_csr_pcs8g_h.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xcvr_csr_pcs8g.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xcvr_csr_selector.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xcvr_mgmt2dec.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/altera_wait_generate.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/hxaui_alt4gxb.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/hxaui.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/siv_xcvr_xaui.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name QIP_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xaui_phy_assignments.qip]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SDC_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xaui_phy_top.sdc]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_h.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_siv.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_analog.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_analog_tgx.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_offset_cancellation.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_offset_cancellation_tgx.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_eyemon_tgx.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_dfe_tgx.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_basic_tgx.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_mutex_acq.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_dprio.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xcvr_arbiter.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/alt_xcvr_m2s.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/plain_files.txt]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_0" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_0/qencrypt_files.txt]
+
+set_global_assignment -entity "altera_xcvr_xaui" -library "lib_ip_stratixiv_phy_xaui_0" -name IP_TOOL_NAME "altera_xcvr_xaui"
+set_global_assignment -entity "altera_xcvr_xaui" -library "lib_ip_stratixiv_phy_xaui_0" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_xcvr_xaui" -library "lib_ip_stratixiv_phy_xaui_0" -name IP_TOOL_ENV "mwpim"
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_dprio.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_dprio.v
new file mode 100644
index 0000000000000000000000000000000000000000..c8cb550d6c519e9fddf949f789fe95544e45690e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_dprio.v
@@ -0,0 +1,199 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"{-to addr_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to wr_out_data_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to rd_out_data_shift_reg[13]} DPRIO_INTERFACE_REG=ON;{-to in_data_shift_reg[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[1]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[2]} DPRIO_INTERFACE_REG=ON"} *)
+module alt_dprio (
+ input wire [15:0] address,
+ output wire busy,
+ input wire [15:0] datain,
+ output wire [15:0] dataout,
+ input wire dpclk,
+ output wire dpriodisable,
+ output wire dprioin,
+ output wire dprioload,
+ input wire dprioout,
+ input wire [6:0] quad_address,
+ input wire rden,
+ input wire wren,
+ input wire wren_data
+ );
+
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [31:0] addr_shift_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [15:0] in_data_shift_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [15:0] rd_out_data_shift_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [2:0] startup_cntr;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg [2:0] state_mc_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [31:0] wr_out_data_shift_reg;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg [5:0] state_mc_counter_q;
+
+ wire pre_amble_cmpr_agb;
+ wire [7:0] state_mc_decode_eq;
+ wire dprioin_mux_dataout;
+ wire busy_state;
+ wire idle_state;
+ wire rd_addr_done;
+ wire rd_addr_state;
+ wire rd_data_done;
+ wire rd_data_input_state;
+ wire rd_data_output_state;
+ wire rd_data_state;
+ wire rdinc;
+ wire read_state;
+ wire s0_to_0;
+ wire s0_to_1;
+ wire s1_to_0;
+ wire s1_to_1;
+ wire s2_to_0;
+ wire s2_to_1;
+ wire startup_done;
+ wire startup_idle;
+ wire wr_addr_done;
+ wire wr_addr_state;
+ wire wr_data_done;
+ wire wr_data_state;
+ wire write_state;
+ wire [2:0] startup_cntr_d;
+ wire [2:0] startup_cntr_ena;
+
+ // synopsys translate_off
+ initial
+ begin
+ addr_shift_reg = 0;
+ in_data_shift_reg = 0;
+ rd_out_data_shift_reg = 0;
+ startup_cntr[2:0] = 3'b0;
+ state_mc_reg = 0;
+ wr_out_data_shift_reg = 0;
+ state_mc_counter_q = 6'b0;
+ end
+ // synopsys translate_on
+
+ always @ (posedge dpclk)
+ begin
+ if (state_mc_counter_q == 6'b011111)
+ begin
+ addr_shift_reg <= {{2{{2{1'b0}}}}, {3{1'b0}}, quad_address, 2'b10, address};
+ rd_out_data_shift_reg <= {{2{1'b0}}, {2{1'b1}}, {3{1'b0}}, quad_address, 2'b10};
+ wr_out_data_shift_reg <= {{2{1'b0}}, 2'b01, {3{1'b0}}, quad_address, 2'b10, datain};
+ end
+ else begin
+ addr_shift_reg <= {addr_shift_reg[30:0], 1'b0};
+ rd_out_data_shift_reg <= {rd_out_data_shift_reg[14:0], 1'b0};
+ wr_out_data_shift_reg <= {wr_out_data_shift_reg[30:0], 1'b0};
+ end
+
+ if (rd_data_input_state == 1'b1)
+ in_data_shift_reg <= {in_data_shift_reg[14:0], dprioout};
+ end
+
+ always @ (posedge dpclk)
+ begin
+ if (startup_cntr_ena[0] == 1'b1)
+ startup_cntr[0] <= startup_cntr_d[0];
+ if (startup_cntr_ena[1:1] == 1'b1)
+ startup_cntr[1] <= startup_cntr_d[1];
+ if (startup_cntr_ena[2:2] == 1'b1)
+ startup_cntr[2] <= startup_cntr_d[2];
+ end
+
+ assign startup_cntr_d = {(startup_cntr[2] ^ (startup_cntr[1] & startup_cntr[0])), (startup_cntr[0] ^ startup_cntr[1]), (~ startup_cntr[0])};
+ assign startup_cntr_ena = {3{((((rden | wren) | rdinc) | (~ startup_idle)) & (~ startup_done))}};
+
+ always @ ( posedge dpclk)
+ begin
+ state_mc_reg <= {(s2_to_1 | (((~ s2_to_0) & (~ s2_to_1)) & state_mc_reg[2])), (s1_to_1 | (((~ s1_to_0) & (~ s1_to_1)) & state_mc_reg[1])), (s0_to_1 | (((~ s0_to_0) & (~ s0_to_1)) & state_mc_reg[0]))};
+ end
+
+ always @(posedge dpclk)
+ begin
+ if (write_state | read_state)
+ begin
+ if (state_mc_counter_q == 6'b111111)
+ state_mc_counter_q <= 6'b0;
+ else
+ state_mc_counter_q <= state_mc_counter_q[5:0] + 6'b1;
+ end
+ end
+
+ lpm_decode #(
+ .lpm_decodes (8),
+ .lpm_width (3),
+ .lpm_type ("lpm_decode"))
+ state_mc_decode(
+ .data(state_mc_reg),
+ .eq(state_mc_decode_eq)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .clken(1'b1),
+ .clock(1'b0),
+ .enable(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+
+ or(dprioin_mux_dataout, ((((((wr_addr_state | rd_addr_state) & addr_shift_reg[31]) & pre_amble_cmpr_agb) | ((~ pre_amble_cmpr_agb) & (wr_addr_state | rd_addr_state))) | (((wr_data_state & wr_out_data_shift_reg[31]) & pre_amble_cmpr_agb) | ((~ pre_amble_cmpr_agb) & wr_data_state))) | (((rd_data_output_state & rd_out_data_shift_reg[15]) & pre_amble_cmpr_agb) | ((~ pre_amble_cmpr_agb) & rd_data_output_state))), ~(((write_state | rd_addr_state) | rd_data_output_state)));
+
+ assign
+ pre_amble_cmpr_agb = (state_mc_counter_q > 6'b011111),
+ busy = busy_state,
+ busy_state = (write_state | read_state),
+ dataout = in_data_shift_reg,
+ dpriodisable = (~ (startup_cntr[2] & (startup_cntr[0] | startup_cntr[1]))),
+ dprioin = dprioin_mux_dataout,
+ dprioload = (~ ((startup_cntr[0] ^ startup_cntr[1]) & (~ startup_cntr[2]))),
+ idle_state = state_mc_decode_eq[0],
+
+ rd_addr_done = (rd_addr_state & (state_mc_counter_q == 6'b111111)),
+
+ rd_addr_state = (state_mc_decode_eq[5] & startup_done),
+ rd_data_done = (rd_data_state & (state_mc_counter_q == 6'b111111)),
+
+ rd_data_input_state = ((state_mc_counter_q >= 6'b110000) & rd_data_state),
+
+ rd_data_output_state = (state_mc_counter_q < 6'b110000 & rd_data_state),
+ rd_data_state = (state_mc_decode_eq[7] & startup_done),
+ rdinc = 1'b0,
+ read_state = (rd_addr_state | rd_data_state),
+ s0_to_0 = ((wr_data_state & wr_data_done) | (rd_data_state & rd_data_done)),
+ s0_to_1 = (((idle_state & (wren | ((~ wren) & ((rden | rdinc) | wren_data)))) | (wr_addr_state & wr_addr_done)) | (rd_addr_state & rd_addr_done)),
+ s1_to_0 = (((wr_data_state & wr_data_done) | (rd_data_state & rd_data_done)) | (idle_state & (wren | (((~ wren) & (~ wren_data)) & rden)))),
+ s1_to_1 = (((idle_state & ((~ wren) & (rdinc | wren_data))) | (wr_addr_state & wr_addr_done)) | (rd_addr_state & rd_addr_done)),
+ s2_to_0 = ((((wr_addr_state & wr_addr_done) | (wr_data_state & wr_data_done)) | (rd_data_state & rd_data_done)) | (idle_state & (wren | wren_data))),
+ s2_to_1 = ((idle_state & (((~ wren) & (~ wren_data)) & (rdinc | rden))) | (rd_addr_state & rd_addr_done)),
+ startup_done = ((startup_cntr[2] & (~ startup_cntr[0])) & startup_cntr[1]),
+ startup_idle = ((~ startup_cntr[0]) & (~ (startup_cntr[2] ^ startup_cntr[1]))),
+
+ wr_addr_done = (wr_addr_state & (state_mc_counter_q == 6'b111111)),
+
+ wr_addr_state = (state_mc_decode_eq[1] & startup_done),
+
+ wr_data_done = (wr_data_state & (state_mc_counter_q == 6'b111111)),
+
+ wr_data_state = (state_mc_decode_eq[3] & startup_done),
+ write_state = (wr_addr_state | wr_data_state);
+endmodule //alt_dprio
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_mutex_acq.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_mutex_acq.v
new file mode 100644
index 0000000000000000000000000000000000000000..c5d020f703904fbb94916ef75bd1fda144424ba9
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_mutex_acq.v
@@ -0,0 +1,221 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_mutex_acq #(
+ parameter mutex_wait_time = 101,
+ parameter mutex_wait_time_cntr_width = 7, // do we need this parameter?
+ parameter addr_width = 5,
+ parameter data_width = 32,
+ parameter read_mutex_addr_offset = 0 // address of the mutex word
+)
+(
+
+input wire clk, // this will be the reconfig clk
+input wire reset,
+
+// Internal interface for the bigger controlling module, like analog reconfig
+input wire [addr_width-1:0] address, // MM address
+input wire [data_width-1:0] writedata,
+input wire write,
+input wire read,
+output reg waitrequest, // can use to tell internal master to wait when auto-request+release
+output wire [data_width-1:0] readdata,
+
+
+// MM master external interface, that connects to mutex-slave, like the reconfig_basic block
+output wire [addr_width-1:0] master_address, // MM address
+output wire [data_width-1:0] master_writedata,
+output wire master_write,
+output wire master_read,
+input wire master_waitrequest, // needed for a valid master interface
+input wire [data_width-1:0] master_readdata, // from mutex-slave
+
+
+
+// request mutex access and should be held high as long as mutex is used
+input wire mutex_req,
+// output indicating whether mutex access was granted or not
+output reg mutex_grant
+
+);
+
+
+
+localparam IDLE = 2'b00;
+localparam GET_MUTEX = 2'b01;
+localparam RELEASE_MUTEX = 2'b10;
+
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [9:0] mutex_timeout_cntr;
+
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *) // should we make this variable
+reg [mutex_wait_time_cntr_width-1:0] mutex_wait_cntr;
+
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [addr_width-1:0] mutex_int_address; // MM address
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [data_width-1:0] mutex_int_writedata;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg mutex_int_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg mutex_int_read;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg do_base_readwrite;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
+reg mutex_mux_ctrl;
+
+// synopsys translate_off
+initial
+begin
+ mutex_grant = 0;
+ mutex_mux_ctrl = 1'b1;
+ mutex_timeout_cntr = 0;
+ mutex_wait_cntr = 0;
+ mutex_int_address = 0;
+ mutex_int_writedata = 0;
+ mutex_int_read = 0;
+ mutex_int_write = 0;
+ waitrequest = 0;
+ do_base_readwrite = 0;
+ state = 0;
+end
+// synopsys translate_on
+
+always @(posedge clk or posedge reset)
+begin
+ if (reset === 1'b1)
+ begin
+ mutex_grant <= 0;
+ mutex_mux_ctrl <= 1'b1;
+ mutex_timeout_cntr <= 0;
+ mutex_wait_cntr <= 0;
+ mutex_int_address <= 'b0;
+ mutex_int_writedata <= 'b0;
+ mutex_int_read <= 'b0;
+ mutex_int_write <= 'b0;
+ waitrequest <= 'b0;
+ do_base_readwrite <= 'b0;
+ state <= 'b0;
+ end
+ else begin
+ case (state)
+ IDLE:begin
+// fix SPR:343567 - Avalon slaves are permitted to keep waitrequest asserted during idle cycles.
+// The state machine will still work correctly by simply removing this condition.
+// The next state is GET_MUTEX, and it will wait there if waitrequest is legitimately asserted.
+// if (master_waitrequest == 1'b1)
+// state <= IDLE; // wait till the waitrequest goes low
+// else if (mutex_grant == 0 &&
+ if (mutex_grant == 0 &&
+ (mutex_req == 1'b1 || write == 1'b1 || read == 1'b1))
+ begin
+ state <= GET_MUTEX;
+ mutex_int_read <= 1'b1;
+ mutex_int_address <= read_mutex_addr_offset;
+ mutex_int_write <= 1'b0;
+ mutex_wait_cntr <= 0;
+ mutex_mux_ctrl <= 1'b1;
+ waitrequest <= 1'b1; // pull the waitrequest high
+ if (write == 1'b1 || read == 1'b1)
+ do_base_readwrite <= 1'b1;
+ else
+ do_base_readwrite <= 1'b0;
+ end
+ else if (mutex_grant == 1'b1)
+ begin
+ do_base_readwrite <= 1'b0;
+ if (mutex_req == 1'b1 || write == 1'b1 || read == 1'b1)
+ begin
+ mutex_mux_ctrl <= 1'b0; // relinquish control of the mux
+ if (write == 1'b1 || read == 1'b1)
+ waitrequest <= master_waitrequest;
+ else
+ waitrequest <= 1'b0;
+ if (read == 1'b1 || write == 1'b1)
+ mutex_timeout_cntr <= 0;
+ else if (mutex_timeout_cntr == 10'd1000)
+ state <= RELEASE_MUTEX;
+ else
+ mutex_timeout_cntr <= mutex_timeout_cntr[9:0] + 10'b1;
+ end
+ else
+ state <= RELEASE_MUTEX;
+ end
+ else
+ begin
+ mutex_mux_ctrl <= 1'b1; // choke the inputs going to basic as mux is not available
+ mutex_int_read <= 1'b0;
+ mutex_int_write <= 1'b0;
+ waitrequest <= 1'b0;
+ end
+ end
+ RELEASE_MUTEX: begin
+ // release the mutex
+ mutex_mux_ctrl <= 1'b1;
+ mutex_int_read <= 1'b0;
+ mutex_int_write <= 1'b1;
+ mutex_int_address <= read_mutex_addr_offset;
+ mutex_int_writedata <= 16'b0;
+ mutex_grant <= 1'b0;
+ state <= IDLE;
+ mutex_timeout_cntr <= 0;
+ waitrequest <= 1'b0;
+ end
+ GET_MUTEX: begin
+ if (master_waitrequest == 1'b1) // wait in this state itself
+ begin
+ state <= GET_MUTEX;
+ end
+ else if (mutex_int_read == 1'b1 && master_readdata[0] == 1'b0) // check mutex bit
+ begin
+ mutex_grant <= 1; // mutex is available
+ state <= IDLE;
+ mutex_int_read <= 1'b0; // reset the read and mux ctrl bits
+ mutex_mux_ctrl <= 0;
+ if (do_base_readwrite == 1'b1)
+ waitrequest <= master_waitrequest;
+ else
+ waitrequest <= 1'b0;
+ end
+ else if (mutex_wait_cntr != mutex_wait_time)
+ begin // continue waiting till the wait time is hit
+ mutex_wait_cntr <= mutex_wait_cntr[mutex_wait_time_cntr_width-1:0] + 1;
+ mutex_int_read <= 1'b0; // pull down the read
+ state <= GET_MUTEX;
+ end
+ else // try and read again
+ begin
+ mutex_wait_cntr <= 0; // reset the wait cntr and try and read again
+ mutex_int_read <= 1'b1;
+ state <= GET_MUTEX;
+ end
+ end
+ default: begin
+ state <= IDLE;
+ end
+ endcase
+ end
+
+end
+
+
+assign master_address = mutex_mux_ctrl ? mutex_int_address : address;
+assign master_writedata = mutex_mux_ctrl ? mutex_int_writedata : writedata;
+assign master_write = mutex_mux_ctrl ? mutex_int_write : write;
+assign master_read = mutex_mux_ctrl ? mutex_int_read : read;
+assign readdata = master_readdata; // pipe the readdata out
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_pma_ch_controller_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_pma_ch_controller_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..6347c1ae0190510fae1e3cec2d4c58e3c11c0d34
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_pma_ch_controller_tgx.v
@@ -0,0 +1,164 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ns/10ps
+module alt_pma_ch_controller_tgx #(
+ parameter
+ number_of_channels = 4,
+ sys_clk_in_mhz = 50, // used to calculate internal delays in terms of system clock cycles
+ manual_reset = "false",
+ sync_depth =2
+ )
+ (
+ //controller standard interface to user
+ input tri0 rst, // controller logic reset
+// input wire powerdown_all, // save power
+ input tri0 rx_rst_digital, // tx_digitalreset
+ input tri0 tx_rst_digital, // rx_digitalreset
+ output wire tx_pma_ready, // pma tx pll_locked
+ output wire rx_pma_ready, // pma rx pll is locked to data
+ input tri0 tx_cal_busy, // tx calibration in progress
+ input tri0 rx_cal_busy, // rx calibration in progress
+ input tri1 pll_locked, // tx pll_locked
+
+ // user data (avalon-MM formatted)
+ input wire clk,
+ input tri0 [5:0] ch_mgmt_address,
+ input tri1 ch_mgmt_read,
+ output wire [31:0] ch_mgmt_readdata,
+ input tri0 ch_mgmt_write,
+ input tri0 [31:0] ch_mgmt_writedata,
+ output wire ch_mgmt_waitrequest,
+
+ input tri1 [number_of_channels-1:0] rx_is_lockedtodata,
+ input tri1 [number_of_channels-1:0] rx_is_lockedtoref,
+
+ output wire [number_of_channels-1:0] rx_set_locktodata,
+ output wire [number_of_channels-1:0] rx_set_locktoref,
+ output wire [number_of_channels-1:0] rx_seriallpbken,
+
+ output wire [number_of_channels-1:0] rx_analog_rst,
+ output wire [number_of_channels-1:0] tx_digital_rst,
+ output wire [number_of_channels-1:0] rx_digital_rst,
+ output wire pll_powerdown
+);
+ // reset controller outputs
+ wire reset_controller_tx_ready;
+ wire reset_controller_rx_ready;
+ wire reset_controller_pll_powerdown;
+ wire reset_controller_tx_digitalreset;
+ wire reset_controller_rx_analogreset;
+ wire reset_controller_rx_digitalreset;
+ wire reset_controller_manual_mode;
+
+ // Control & status register map (CSR) outputs
+ wire csr_reset_tx_digital; // to reset controller
+ wire csr_reset_rx_digital; // to reset controller
+ wire csr_reset_all; // to reset controller
+ wire csr_pll_powerdown;
+ wire [number_of_channels - 1 : 0] csr_tx_digitalreset; // to xcvr instance
+ wire [number_of_channels - 1 : 0] csr_rx_analogreset; // to xcvr instance
+ wire [number_of_channels - 1 : 0] csr_rx_digitalreset; // to xcvr instance
+ wire [number_of_channels - 1 : 0] csr_phy_loopback_serial; // to xcvr instance
+ wire [number_of_channels - 1 : 0] csr_rx_set_locktoref; // to xcvr instance
+ wire [number_of_channels - 1 : 0] csr_rx_set_locktodata; // to xcvr instance
+
+
+ ///////////////////////////////////////////////////////////////////
+
+ // Implement waitrequest to match previous implementation
+ altera_wait_generate wait_gen(
+ .rst(rst),
+ .clk(clk),
+ .launch_signal(ch_mgmt_read),
+ .wait_req(ch_mgmt_waitrequest)
+ );
+ // Instantiate memory map logic for given number of lanes & PLL's
+ // Includes all except PCS
+ alt_xcvr_csr_common #(
+ .lanes(number_of_channels),
+ .plls(1)
+ ) csr (
+ .clk(clk),
+ .reset(rst),
+ .address(8'h40 | ch_mgmt_address), // map word 0 of this module to word 64 of alt_xcvr_csr_common
+ .read(ch_mgmt_read),
+ .write(ch_mgmt_write),
+ .writedata(ch_mgmt_writedata),
+ .pll_locked(pll_locked),
+ .rx_is_lockedtoref(rx_is_lockedtoref),
+ .rx_is_lockedtodata(rx_is_lockedtodata),
+ .rx_signaldetect({number_of_channels{1'b0}}),
+ .reset_controller_tx_ready(reset_controller_tx_ready),
+ .reset_controller_rx_ready(reset_controller_rx_ready),
+ .reset_controller_pll_powerdown(reset_controller_pll_powerdown),
+ .reset_controller_tx_digitalreset(reset_controller_tx_digitalreset),
+ .reset_controller_rx_analogreset(reset_controller_rx_analogreset),
+ .reset_controller_rx_digitalreset(reset_controller_rx_digitalreset),
+ .readdata(ch_mgmt_readdata),
+ .csr_reset_tx_digital(csr_reset_tx_digital),
+ .csr_reset_rx_digital(csr_reset_rx_digital),
+ .csr_reset_all(csr_reset_all),
+ .csr_pll_powerdown(csr_pll_powerdown),
+ .csr_tx_digitalreset(csr_tx_digitalreset),
+ .csr_rx_analogreset(csr_rx_analogreset),
+ .csr_rx_digitalreset(csr_rx_digitalreset),
+ .csr_phy_loopback_serial(csr_phy_loopback_serial),
+ .csr_rx_set_locktoref(csr_rx_set_locktoref),
+ .csr_rx_set_locktodata(csr_rx_set_locktodata)
+ );
+
+
+ // Instantiate reset controller for PMA channels
+ alt_reset_ctrl_tgx_cdrauto #(
+ .sys_clk_in_mhz(sys_clk_in_mhz)
+ ) rc (
+ .clock(clk),
+ .reset_all(csr_reset_all),
+ .reset_tx_digital(csr_reset_tx_digital | tx_rst_digital),
+ .reset_rx_digital(csr_reset_rx_digital | rx_rst_digital),
+ .powerdown_all(rst),
+ .tx_ready(reset_controller_tx_ready),
+ .rx_ready(reset_controller_rx_ready),
+ .pll_powerdown (reset_controller_pll_powerdown),
+ .tx_digitalreset(reset_controller_tx_digitalreset),
+ .rx_analogreset(reset_controller_rx_analogreset),
+ .rx_digitalreset(reset_controller_rx_digitalreset),
+ .gxb_powerdown(),
+ .pll_is_locked(pll_locked),
+ .tx_cal_busy(tx_cal_busy),
+ .rx_cal_busy(rx_cal_busy),
+ .rx_is_lockedtodata(&rx_is_lockedtodata),
+ .manual_mode(reset_controller_manual_mode)
+ );
+
+ // Assign outputs from reset controller
+ assign tx_pma_ready = reset_controller_tx_ready;
+ assign rx_pma_ready = reset_controller_rx_ready;
+
+ // Assign outputs from CSR to channel control bits
+ assign rx_set_locktodata = csr_rx_set_locktodata;
+ assign rx_set_locktoref = csr_rx_set_locktoref;
+ assign rx_seriallpbken = csr_phy_loopback_serial;
+
+ assign rx_analog_rst = csr_rx_analogreset;
+ assign tx_digital_rst = csr_tx_digitalreset;
+ assign rx_digital_rst = csr_rx_digitalreset;
+
+ assign reset_controller_manual_mode = (manual_reset == "true") ? 1'b1
+ : (csr_rx_set_locktoref || csr_rx_set_locktodata);
+
+ assign pll_powerdown = csr_pll_powerdown;
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_pma_controller_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_pma_controller_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..614ad6278ca4a3cbbfa013d414c4e6c8410c156e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_pma_controller_tgx.v
@@ -0,0 +1,198 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ns/10ps
+module alt_pma_controller_tgx #(
+ parameter number_of_plls = 1,// One controller only control the possible merged pll. If more pll is needed, user can use multiplier controller for none share plls.
+ parameter tx_pll_reset_hold_time = 0,// ignored - now calculated according to system clock
+ parameter sync_depth = 2,
+ parameter sys_clk_in_mhz = 50 // needed for 1us and 4us delay timers
+)
+(
+ input rst, // controller logic reset
+ output tx_pll_ready,
+
+ // user data (avalon-MM formatted)
+ input wire clk,
+ input wire [1:0] pma_mgmt_address,
+ input wire pma_mgmt_read,
+ output reg [31:0] pma_mgmt_readdata,
+ input wire pma_mgmt_write,
+ input wire [31:0] pma_mgmt_writedata,
+ output wire pma_mgmt_waitrequest,
+
+ // user data (avalon-clock formatted)
+ input wire cal_blk_clk,
+
+ // user data: pll control (avalon-ST formatted)
+ output wire cal_blk_pdn,//sync with cal_blk_clk
+ output wire gx_pdn,//sync with clk
+ output wire [number_of_plls-1:0] pll_pdn, //sync with clk
+ input wire [number_of_plls-1:0] pll_locked //
+);
+
+localparam clk_in_mhz =
+`ifdef QUARTUS__SIMGEN
+ 2; // simulation-only value
+`elsif ALTERA_RESERVED_QIS
+ sys_clk_in_mhz; // use real counter lengths for normal Quartus synthesis
+`else
+ 2; // simulation-only value
+`endif
+localparam t_pll_powerdown = clk_in_mhz; // 1 us minimum
+localparam t_ltd_auto = clk_in_mhz*4; // 4 us minimum
+
+wire [number_of_plls-1:0] pll_locked_sync;
+reg cal_blk_pdn_reg;
+reg read_delay;
+reg gx_pdn_reg;
+reg pll_pdn_resetall_avmm;
+wire pll_pdn_int;
+reg pll_pdn_reg;
+
+wire gx_pdn_int;
+wire gx_pdn_done;
+
+altera_wait_generate wait_gen(
+ .rst(rst),
+.clk(clk),
+.launch_signal(pma_mgmt_read),
+.wait_req(pma_mgmt_waitrequest)
+ );
+
+alt_reset_ctrl_lego
+#(
+.reset_hold_cycles (t_pll_powerdown) // reset pulse length in clock cycles
+) pll_pdn_rst
+(
+.clock(clk),
+.start(1'b1 ),
+.reset(pll_pdn_int),
+.rdone(pll_locked), // reset done signal
+.aclr(rst),
+.sdone(tx_pll_ready) // sequence done for this lego
+);
+
+alt_reset_ctrl_lego
+#(
+.reset_hold_cycles (2) // reset pulse length in clock cycles
+) gx_pdn_rst
+(
+.clock(clk),
+.start(1'b1 ),
+.reset(gx_pdn_int),
+.rdone(1'b1), // reset done signal
+.aclr(rst),
+.sdone(gx_pdn_done) // sequence done for this lego
+);
+
+assign pll_pdn= pll_pdn_reg | {number_of_plls{pll_pdn_int}} ;
+
+initial
+begin
+ pll_pdn_reg <= 0;
+end
+always @ (posedge clk, posedge rst)
+begin
+ if(rst) begin
+ pll_pdn_reg <= 1'b0;
+ end
+ else if (pma_mgmt_write==1'b1 & pma_mgmt_address==2'b00) begin
+ pll_pdn_reg <= pma_mgmt_writedata[number_of_plls -1 :0];
+ end
+end
+
+initial
+begin
+ pma_mgmt_readdata <= 0;
+end
+always @ (posedge clk, posedge rst)
+begin
+ if(rst) begin
+ pma_mgmt_readdata <= 0;
+ end
+ else if (pma_mgmt_read==1'b1 & pma_mgmt_address==2'b00) begin
+ pma_mgmt_readdata[number_of_plls -1 :0] <= pll_pdn;
+ end
+ else if (pma_mgmt_read==1'b1 & pma_mgmt_address==2'b01) begin
+ pma_mgmt_readdata[0] <= cal_blk_pdn_reg;
+ pma_mgmt_readdata[1] <= gx_pdn;
+ end
+ else if (pma_mgmt_read==1'b1 & pma_mgmt_address==2'b10) begin
+ pma_mgmt_readdata[number_of_plls -1 :0] <= pll_locked_sync;
+ end
+ else
+ pma_mgmt_readdata <= 0;
+end
+
+generate
+genvar i;
+for (i=0; i<number_of_plls; i=i+1)
+begin: lock_sync
+ altera_std_synchronizer
+ #(
+ .depth (sync_depth) // reset pulse length in clock cycles
+ )stdsync
+ (
+ .clk(clk),
+ .din(pll_locked[i]),
+ .dout(pll_locked_sync[i]),
+ .reset_n((~ rst))
+ );
+end
+endgenerate
+
+initial
+begin
+ cal_blk_pdn_reg <= 0;
+end
+always @ (posedge clk, posedge rst)
+begin
+ if(rst) begin
+ cal_blk_pdn_reg <= 0;
+ end
+ else if (pma_mgmt_write==1'b1 & pma_mgmt_address==2'b01) begin
+ cal_blk_pdn_reg <= pma_mgmt_writedata[0];
+ end
+end
+altera_std_synchronizer
+#(
+ .depth (sync_depth) // reset pulse length in clock cycles
+)stdsync
+(
+ .clk(cal_blk_clk),
+ .din(cal_blk_pdn_reg),
+ .dout(cal_blk_pdn),
+ .reset_n((~ rst))
+);
+
+assign gx_pdn = gx_pdn_reg | gx_pdn_int;
+initial
+begin
+ gx_pdn_reg <= 0;
+end
+always @ (posedge clk, posedge rst)
+begin
+ if(rst) begin
+ gx_pdn_reg <= 0;
+ end
+ else if (pma_mgmt_write==1'b1 & pma_mgmt_address==2'b01) begin
+ gx_pdn_reg <= pma_mgmt_writedata[1];
+ end
+ else begin
+ gx_pdn_reg <= gx_pdn_reg;
+ end
+
+end
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_reset_ctrl_lego.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_reset_ctrl_lego.sv
new file mode 100644
index 0000000000000000000000000000000000000000..38d99a0658aa5380a62046e68a3b66cb9158881b
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_reset_ctrl_lego.sv
@@ -0,0 +1,265 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Reset controller building block.
+//
+// Handles a single reset stage. Can be daisy-chained with other blocks for purely sequential resets.
+// Options include reset pulse length in clock cycles, and a counter for sdone stability checking.
+//
+// $Header$
+//
+
+`timescale 1 ns / 1 ns
+
+module alt_reset_ctrl_lego
+#(
+ parameter reset_hold_til_rdone = 0, // 1 means reset stays high until rdone arrives
+ // 0 means fixed pulse length, defined by reset_hold_cycles
+ parameter reset_hold_cycles = 1, // reset pulse length in clock cycles
+ parameter sdone_delay_cycles = 0, // optional delay from rdone received til sdone sent to next block
+ parameter rdone_is_edge_sensitive = 0 // default is level sensitive rdone
+)
+(
+ // clocks and PLLs
+ input wire clock,
+ input wire start,
+ input tri0 aclr, // active-high asynchronous reset
+ output wire reset,
+ input tri1 rdone, // reset done signal
+ output reg sdone // sequence done for this lego
+);
+ localparam max_precision = 32; // VCS requires this declaration outside the function
+ function integer ceil_log2;
+ input [max_precision-1:0] input_num;
+ integer i;
+ reg [max_precision-1:0] try_result;
+ begin
+ i = 0;
+ try_result = 1;
+ while ((try_result << i) < input_num && i < max_precision)
+ i = i + 1;
+ ceil_log2 = i;
+ end
+ endfunction
+
+ // How many bits are needed for 'reset_hold_cycles' counter?
+ localparam rhc_bits = ceil_log2(reset_hold_cycles);
+ localparam rhc_load_constant = (1 << rhc_bits) | (reset_hold_cycles-1);
+ // How many bits are needed for 'sdone_delay_cycles' counter?
+ localparam sdc_bits = ceil_log2(sdone_delay_cycles);
+ localparam sdc_load_constant = (1 << sdc_bits)
+ | ((rdone_is_edge_sensitive == 1 && sdone_delay_cycles > 1) ? sdone_delay_cycles-2 : sdone_delay_cycles-1);
+ localparam sdone_stable_cycles = (sdone_delay_cycles > 1 ? sdone_delay_cycles+1 : 0);
+
+ wire spulse; // synchronous detection of 'start' 0-to-1 transition
+ wire rhold;
+ wire timed_reset_in_progress;
+ wire rinit_next; // combinatorial input to rinit DFF
+ wire rdonei; // internal selector between rdone and rdsave (rdone_is_edge_sensitive==1)
+ wire rdpulse; // synchronous detection of 'rdone' 0-to-1 transition, when rdone_is_edge_sensitive==1
+
+ reg zstart = 0; // delayed value of 'start' input, used for detection of 0-to-1 transition
+ reg rinit = 0; // state bit that indicates sequence is in progress
+
+ initial begin
+ sdone = 0; // 1 indicates sequence is done
+ end
+
+
+ // 'start' input, detect 0-to-1 transition that triggers sequence
+ assign spulse = start & ~zstart;
+ always @(posedge clock or posedge aclr)
+ if (aclr == 1'b1)
+ zstart <= 0;
+ else
+ zstart <= start;
+
+ // rinit state bit, triggered by spulse, waits while rhold = 1
+ assign rinit_next = spulse | (rinit & (rhold | ~rdonei | rdpulse)) | timed_reset_in_progress;
+ always @(posedge clock or posedge aclr)
+ if (aclr == 1'b1)
+ rinit <= 0;
+ else
+ rinit <= rinit_next;
+
+ // optional internal 'rdone' generation logic, if rdone_is_edge_sensitive==1
+ generate
+ if (rdone_is_edge_sensitive == 0) begin
+ assign rdpulse = 0;
+ assign rdonei = rdone;
+ end
+ else begin
+ // instantiate synchronous edge-detection logic for rdone
+ reg zrdone = 0; // for edge-sensitive rdone, detect 0-to-1 transition synchronously
+ reg rdsave = 0; // for edge-sensitive rdone, use this as internal rdone
+ always @(posedge clock or posedge aclr) begin
+ if (aclr == 1'b1) begin
+ zrdone <= 0;
+ rdsave <= 0;
+ end
+ else begin
+ zrdone <= rdone; // previous value of rdone for synchronous edge detection
+ rdsave <= ~spulse & (rdpulse | rdsave);
+ end
+ end
+ assign rdpulse = rdone & ~zrdone;
+ assign rdonei = rdsave;
+ end
+ endgenerate
+
+ // rhold depends on sdone_delay_cycles and rdone_is_edge_sensitive
+ generate
+ if (sdone_delay_cycles == 0 || (sdone_delay_cycles == 1 && rdone_is_edge_sensitive == 1))
+ assign rhold = ~rdonei; // sdone_delay_cycles=0
+ else begin
+ // declare only when needed to avoid Quartus synthesis warnings
+ reg [sdc_bits:0] rhold_reg = 0; // for sdone_delay_cycles > 0
+ if (sdone_delay_cycles == 1) begin
+ always @(posedge clock or posedge aclr) begin
+ if (aclr == 1'b1)
+ rhold_reg <= 0;
+ else
+ rhold_reg <= ~(rinit & rdonei);
+ end
+ assign rhold = rhold_reg[0]; // sdone_delay_cycles=1
+ end
+ else begin
+ // need to count cycles to make sure rdone is stable
+ always @(posedge clock or posedge aclr)
+ begin
+ if (aclr == 1'b1)
+ rhold_reg <= 0;
+ else if ((rinit & rdonei & ~rdpulse) == 0)
+ // keep load value until rinit & rdone both high, and no new rdone pulses
+ rhold_reg <= sdc_load_constant[sdc_bits:0];
+ else
+ rhold_reg <= rhold_reg - 1'b1;
+ end
+ assign rhold = rhold_reg[sdc_bits]; // sdone_delay_cycles > 1
+ end
+ end
+ endgenerate
+
+ // sdone state bit indicates that reset sequence completed. Clear again on 'start'
+ always @(posedge clock or posedge aclr)
+ if (aclr == 1'b1)
+ sdone <= 0;
+ else
+ sdone <= ~spulse & (sdone | (rinit & ~rinit_next));
+
+ // reset pulse generation logic depends on 2 parameters
+ generate
+ if (reset_hold_til_rdone == 1) begin
+ assign reset = rinit;
+ assign timed_reset_in_progress = 0;
+ end
+ else if (reset_hold_cycles < 1) begin // 0 is legal, but catch negative (illegal) values too
+ assign reset = spulse;
+ assign timed_reset_in_progress = 0;
+ end
+ else begin
+ // declare only when needed to avoid Quartus synthesis warnings
+ reg [rhc_bits:0] zspulse = 0; // bits for reset pulse if fixed length
+ assign timed_reset_in_progress = zspulse[rhc_bits];
+ assign reset = zspulse[rhc_bits];
+
+ if (reset_hold_cycles == 1)
+ // a single-cycle reset pulse needs 1 register
+ always @(posedge clock or posedge aclr)
+ if (aclr == 1'b1)
+ zspulse <= 0;
+ else
+ zspulse <= spulse;
+ else begin
+ // multi-cycle reset pulse needs a counter
+ always @(posedge clock or posedge aclr)
+ begin
+ if (aclr == 1'b1)
+ zspulse <= 0;
+ else if (spulse == 1)
+ zspulse <= rhc_load_constant[rhc_bits:0];
+ else if (zspulse[rhc_bits] == 1)
+ zspulse <= zspulse - 1'b1;
+ end
+ end
+ end
+ endgenerate
+
+// generate
+// case (reset_hold_til_rdone)
+// 0 : m1 U1 (a, b, c);
+// 2 : m2 U1 (a, b, c);
+// default : m3 U1 (a, b, c);
+// endcase
+// endgenerate
+
+ // general assertions
+ //synopsys translate_off
+ // vlog/vcs/ncverilog: +define+ALTERA_XCVR_ASSERTIONS
+`ifdef ALTERA_XCVR_ASSERTIONS
+ // when rdone is edge sensitive, last rdone +ve edge triggers sdone +ve edge,
+ // 'sdone_delay_cycles' later. "##1 1" is an always-true cycle to match $rise(sdone)
+ sequence rdone_last_edge;
+ @(posedge clock) $rose(rdone) ##1 !$rose(rdone) [*sdone_delay_cycles] ##1 1;
+ endsequence
+
+ // when rdone is level sensitive, stable rdone for 'sdone_delay_cycles' consecutive cycles
+ // triggers sdone +ve edge. "##1 1" is an always-true cycle to match $rise(sdone)
+ sequence rdone_stable_level;
+ @(posedge clock) rdone [*(sdone_delay_cycles+1)] ##1 1;
+ endsequence
+
+// Most assertions aren't valid when 'aclr' is active
+//`define assert_awake(arg) assert property (disable iff (aclr) arg )
+ always @(aclr)
+ if (aclr) $assertkill;
+ else $asserton;
+
+ generate
+ always @(posedge clock) begin
+ // A rising edge on start will result in reset high within 1 clock cycle
+ assert property ($rose(start & ~aclr) |-> ##[0:1] reset);
+ // A rising edge on reset will result in sdone low within 1 clock cycle
+ assert property ($rose(reset) |-> ##[0:1] !sdone);
+
+ // assertions for optional behavior: reset pulse length options
+ if (reset_hold_til_rdone == 0 && reset_hold_cycles > 1)
+ // Verify fixed-length reset pulse option
+ assert property ($rose(reset) |-> reset [*reset_hold_cycles] ##1 !reset)
+ else $error("Reset pulse length should be %d", reset_hold_cycles);
+ if (reset_hold_til_rdone == 0 && reset_hold_cycles == 1)
+ // Verify fixed 1-length reset pulse option
+ assert property ($rose(reset) |=> !reset);
+ if (reset_hold_til_rdone == 0 && reset_hold_cycles == 0)
+ // Verify minimal-length reset pulse option, which mirrors 'start' edge detection
+ assert property ($rose(start & ~aclr) |-> reset ##1 !reset);
+ if (reset_hold_til_rdone == 1) begin
+ // with hold-til-rdone, reset should not deassert until after rdone asserts, then deassert immediately
+ assert property ($rose(reset) && !rdone |=> $stable(reset) [*0:$] ##1 (reset && rdone) ##1 !reset);
+ assert property ($rose(reset) && rdone ##1 rdone [*sdone_delay_cycles] |=> !reset); // rdone was already high
+ //assert property ($rose(reset) && !rdone |-> ##[0:$] rdone ##1 !reset);
+ end
+
+ // assertions for optional behavior: sdone delay options and rdone edge sensitive option
+ if (rdone_is_edge_sensitive == 1)
+ // rdone edge-sensitive option only has an effect when sdone_delay_cycles > 0
+ assert property ($rose(sdone) |-> rdone_last_edge.ended);
+ if (rdone_is_edge_sensitive == 0)
+ // rdone defaults to level-sensitive
+ assert property ($rose(sdone) |-> (rdone_stable_level.ended or $past($fell(reset),1)));
+ end
+ endgenerate
+`endif // ALTERA_XCVR_ASSERTIONS
+ //synopsys translate_on
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_reset_ctrl_tgx_cdrauto.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_reset_ctrl_tgx_cdrauto.sv
new file mode 100644
index 0000000000000000000000000000000000000000..d785de6ee8eb397584ea1833c7e8a7ddf5c3b045
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_reset_ctrl_tgx_cdrauto.sv
@@ -0,0 +1,201 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Reset controller for Stratix IV transceivers with RX CDR in auto-lock mode.
+//
+// Uses alt_reset_ctrl_lego to handle each reset stage, with 3 required for the overall sequence.
+// Parameter defaults for pll-powerdown and lock-to-data-auto timers assume 50 MHz system clock
+//
+// $Header$
+//
+
+`timescale 1 ns / 1 ns
+
+(* altera_attribute = "-name MERGE_TX_PLL_DRIVEN_BY_REGISTERS_WITH_SAME_CLEAR ON -to \"alt_reset_ctrl_lego:lego_pll_powerdown|zspulse\" " *)
+module alt_reset_ctrl_tgx_cdrauto
+#(
+ parameter sys_clk_in_mhz = 50 // needed for 1us and 4us delay timers
+)
+(
+ // User inputs and outputs
+ input wire clock,
+ input wire reset_all,
+ input tri0 reset_tx_digital,
+ input tri0 reset_rx_digital,
+ input wire powerdown_all,
+ output wire tx_ready,
+ output wire rx_ready,
+
+ // I/O to Stratix IV transceiver control & status
+ output wire pll_powerdown, // reset TX PLL
+ output wire tx_digitalreset, // reset TX PCS
+ output wire rx_analogreset, // reset RX PMA
+ output wire rx_digitalreset, // reset RX PCS
+ output wire gxb_powerdown, // powerdown whole quad
+ input wire pll_is_locked, // TX PLL is locked status
+ input tri0 tx_cal_busy, // TX channel calibration status
+ input tri0 rx_cal_busy, // RX channel calibration status
+ input tri1 rx_is_lockedtodata, // RX CDR PLL is locked to data status
+ input tri0 manual_mode // 0=Automatically reset RX after loss of rx_is_lockedtodata
+);
+
+localparam clk_in_mhz =
+`ifdef QUARTUS__SIMGEN
+ 2; // simulation-only value
+`elsif ALTERA_RESERVED_QIS
+ sys_clk_in_mhz; // use real counter lengths for normal Quartus synthesis
+`else
+ 2; // simulation-only value
+`endif
+localparam t_pll_powerdown = clk_in_mhz; // 1 us minimum
+localparam t_ltd_auto = clk_in_mhz*4; // 4 us minimum
+
+
+wire pll_is_locked_r; // pll_is_locked resynchronized
+wire tx_cal_busy_r; // tx_cal_busy resynchronized
+wire rx_cal_busy_r; // rx_cal_busy resynchronized
+wire rx_is_lockedtodata_r; // rx_is_lockedtodata resynchronized
+
+wire sdone_lego_pll_powerdown; // 'sequence done' output of pll_powerdown lego
+wire sdone_lego_tx_digitalreset;// 'sequence done' output of tx_digitalreset lego
+wire sdone_lego_rx_digitalreset;// 'sequence done' output of rx_digitalreset lego
+wire sdone_lego_rx_analogreset; // 'sequence done' output of rx_analogreset lego
+wire wire_tx_digital_only_reset;// reset output for TX digital-only
+wire wire_rx_digital_only_reset;// reset output for RX digital-only
+wire wire_tx_digitalreset; // TX digital full-reset source
+wire wire_rx_digitalreset; // RX digital full-reset source
+wire wire_rx_digital_retrigger; // Trigger new RX digital sequence after main sequence completes, and lose lock-to-data
+
+// Resynchronize input signals
+alt_xcvr_resync #(
+ .WIDTH(2)
+ ) alt_xcvr_resync_inst_0 (
+ .clk (clock),
+ .reset (1'b0),
+ .d ({pll_is_locked ,rx_is_lockedtodata }),
+ .q ({pll_is_locked_r,rx_is_lockedtodata_r})
+);
+
+alt_xcvr_resync #(
+ .WIDTH(2),
+ .INIT_VALUE(1)
+ ) alt_xcvr_resync_inst_1 (
+ .clk (clock),
+ .reset (1'b0),
+ .d ({rx_cal_busy,tx_cal_busy}),
+ .q ({rx_cal_busy_r,tx_cal_busy_r})
+);
+
+// First reset ctrl sequencer lego is for pll_powerdown generation
+alt_reset_ctrl_lego #(
+ .reset_hold_cycles(t_pll_powerdown) // hold pll_powerdown for 1us
+ ) lego_pll_powerdown ( .clock(clock),
+ .start(reset_all), // Do not use resynched version of reset_all here
+ .aclr(powerdown_all),
+ .reset(pll_powerdown),
+ .rdone(pll_is_locked_r),
+ .sdone(sdone_lego_pll_powerdown));
+
+// next reset ctrl sequencer lego is for tx_digitalreset generation
+alt_reset_ctrl_lego #(
+ .reset_hold_til_rdone(1) // hold until rdone arrives for this test case
+ ) lego_tx_digitalreset ( .clock(clock),
+ .start(reset_all),
+ .aclr(powerdown_all),
+ .reset(wire_tx_digitalreset),
+ .rdone(sdone_lego_pll_powerdown & ~tx_cal_busy_r),
+ .sdone(sdone_lego_tx_digitalreset));
+
+// next reset ctrl sequencer lego is for rx_analogreset generation
+alt_reset_ctrl_lego #(
+ .reset_hold_til_rdone(1), // hold until rdone arrives for this test case
+ .sdone_delay_cycles(2) // hold rx_analogreset 2 parallel_clock cycles after offset cancellation done
+ ) lego_rx_analogreset ( .clock(clock),
+ .start(reset_all),
+ .aclr(powerdown_all),
+ .reset(rx_analogreset),
+ .rdone(sdone_lego_tx_digitalreset & ~rx_cal_busy_r),
+ .sdone(sdone_lego_rx_analogreset));
+
+// last reset ctrl sequencer lego is for rx_digitalreset generation
+alt_reset_ctrl_lego #(
+ .reset_hold_til_rdone(1), // hold until rdone arrives for this test case
+ .sdone_delay_cycles(t_ltd_auto) // hold rx_digitalreset for 4us
+ ) lego_rx_digitalreset ( .clock(clock),
+ .start(~manual_mode & reset_all | wire_rx_digital_retrigger),
+ .aclr(powerdown_all),
+ .reset(wire_rx_digitalreset),
+ .rdone(sdone_lego_rx_analogreset & rx_is_lockedtodata_r),
+ .sdone(sdone_lego_rx_digitalreset));
+
+//////////// digital-only reset ////////////
+// separate reset ctrl sequencer lego for digital-only reset generation
+alt_reset_ctrl_lego #(
+ .reset_hold_cycles(3) // hold 2 parallel clock cycles (assumes sysclk slower or same freq as parallel clock)
+ ) lego_tx_digitalonly ( .clock(clock),
+ .start(reset_tx_digital | reset_all),
+ .aclr(powerdown_all),
+ .reset(wire_tx_digital_only_reset),
+ .rdone(sdone_lego_tx_digitalreset),
+ .sdone(tx_ready)); // TX status indicator for user
+
+alt_reset_ctrl_lego #(
+ .reset_hold_cycles(3) // hold 2 parallel clock cycles (assumes sysclk slower or same freq as parallel clock)
+ ) lego_rx_digitalonly ( .clock(clock),
+ .start(reset_rx_digital | (reset_all & ~manual_mode) | wire_rx_digital_retrigger),
+ .aclr(powerdown_all),
+ .reset(wire_rx_digital_only_reset),
+ .rdone(sdone_lego_rx_digitalreset),
+ .sdone(rx_ready)); // RX status indicator for user
+
+// digital resets have 2 possible sources: full-reset or digital-only
+assign tx_digitalreset = wire_tx_digitalreset | wire_tx_digital_only_reset;
+assign rx_digitalreset = wire_rx_digitalreset | wire_rx_digital_only_reset;
+
+// re-trigger RX digital sequence when main sequence is complete (indicated by sdone_lego_rx_digitalreset)
+// not manual mode, and lose lock-to-data
+assign wire_rx_digital_retrigger = ~manual_mode & sdone_lego_rx_digitalreset & ~rx_is_lockedtodata_r;
+
+// Quad power-down
+assign gxb_powerdown = powerdown_all;
+
+
+////////////////////////
+// general assertions
+//synopsys translate_off
+// vlog/vcs/ncverilog: +define+ALTERA_XCVR_ASSERTIONS
+`ifdef ALTERA_XCVR_ASSERTIONS
+always @(posedge clock) begin
+ // reset_all starts by triggering CMU PLL powerdown
+ assert property ($rose(reset_all) |=> $rose(pll_powerdown));
+ // While CMU PLL powerdown is asserted, all other resets must be asserted
+ assert property (pll_powerdown |-> (tx_digitalreset & rx_analogreset & rx_digitalreset));
+ // While rx_analogreset is asserted, rx_digitalreset must be asserted
+ assert property (rx_analogreset |-> rx_digitalreset);
+ // When pll_is_locked is asserted, tx_digitalreset must be deasserted
+ assert property ($rose(pll_is_locked_r) |-> ##[0:2] !tx_digitalreset);
+ // During a reset, rx_digitalreset should remain high for t_ltd_auto after rx_is_lockedtodata rising edge
+ assert property ($rose(rx_is_lockedtodata_r) & ~manual_mode|-> rx_digitalreset [*(t_ltd_auto+1)] ##1 !rx_digitalreset);
+ assert property ($rose(rx_is_lockedtodata_r) & manual_mode|->!rx_digitalreset);
+ // reset_tx_digital results in only a brief pulse on tx_digitalreset
+ assert property ($rose(reset_tx_digital) |=> tx_digitalreset [*3] );
+ assert property ($rose(reset_tx_digital) & tx_ready |=> tx_digitalreset [*3] ##1 ~tx_digitalreset ##1 $rose(tx_ready) );
+ // reset_rx_digital results in only a brief pulse on rx_digitalreset
+ assert property ($rose(reset_rx_digital) |=> rx_digitalreset [*3] );
+ assert property ($rose(reset_rx_digital) & rx_ready |=> rx_digitalreset [*3] ##1 ~rx_digitalreset ##1 $rose(rx_ready) );
+end
+`endif
+//synopsys translate_on
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xaui_phy_assignments.qip b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xaui_phy_assignments.qip
new file mode 100644
index 0000000000000000000000000000000000000000..6b854ad5bc76259e81a1220b8e3fb397d6826122
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xaui_phy_assignments.qip
@@ -0,0 +1,4 @@
+#comment: example of PLL TYPE assignment for TX PLL. This assignment is needed for every TX PLL that exist in the design
+
+# For Stratix V Soft XAUI:
+#set_instance_assignment -name PLL_TYPE ATX -to "*sv_xcvr_xaui:alt_xaui_phy*alt_pma_0*sv_xcvr_native_insts*pll*.tx_pll"
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xaui_phy_top.sdc b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xaui_phy_top.sdc
new file mode 100644
index 0000000000000000000000000000000000000000..3c125358eb82fe3f94dbea0afd1092f76ba3c68f
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xaui_phy_top.sdc
@@ -0,0 +1,43 @@
+# (C) 2001-2012 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and other
+# software and tools, and its AMPP partner logic functions, and any output
+# files any of the foregoing (including device programming or simulation
+# files), and any associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License Subscription
+# Agreement, Altera MegaCore Function License Agreement, or other applicable
+# license agreement, including, without limitation, that your use is for the
+# sole purpose of programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+
+#-----------------------------------------------------------------------------
+#
+# Description: SDC file for alt_xaui
+#
+# Authors: bauyeung
+#
+# Copyright (c) Altera Corporation 1997 - 2010
+# All rights reserved.
+#
+#
+#-----------------------------------------------------------------------------
+
+set_time_format -unit ns -decimal_places 3
+#derive_pll_clocks
+derive_clock_uncertainty
+
+#
+# input clocks
+#
+create_clock -name {xgmii_tx_clk} \
+ -period 6.400 -waveform {0.000 3.2} \
+ [ get_ports {xgmii_tx_clk} ]
+create_clock -name {phy_mgmt_clk} \
+ -period 20.000 -waveform {0.000 10.0} \
+ [ get_ports {phy_mgmt_clk} ]
+create_clock -name {refclk} \
+ -period 6.400 -waveform {0.000 3.2} \
+ [ get_ports {pll_ref_clk} ]
+
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_arbiter.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_arbiter.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5b0e914d4dea0be5e022a29a6df73240a4f4f29e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_arbiter.sv
@@ -0,0 +1,64 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Clocked priority encoder with state
+//
+// On each clock cycle, updates state to show which request is granted.
+// Most recent grant holder is always the highest priority.
+// If current grant holder is not making a request, while others are,
+// then new grant holder is always the requester with lowest bit number.
+// If no requests, current grant holder retains grant state
+
+// $Header$
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_arbiter #(
+ parameter width = 2
+) (
+ input wire clock,
+ input wire [width-1:0] req, // req[n] requests for this cycle
+ output reg [width-1:0] grant // grant[n] means requester n is grantee in this cycle
+);
+
+ wire idle; // idle when no requests
+ wire [width-1:0] keep; // keep[n] means requester n is requesting, and already has the grant
+ // Note: current grantee is always highest priority for next grant
+ wire [width-1:0] take; // take[n] means requester n is requesting, and there are no higher-priority requests
+
+ assign keep = req & grant; // current grantee is always highest priority for next grant
+ assign idle = ~| req; // idle when no requests
+
+ initial begin
+ grant = 0;
+ end
+
+ // grant next state depends on current grant and take priority
+ always @(posedge clock) begin
+ grant <= keep // if current grantee is requesting, gets to keep grant
+ | ({width{idle}} & grant) // if no requests, grant state remains unchanged
+ | take; // take applies only if current grantee is not requesting
+ end
+
+ // 'take' bus encodes priority. Request with lowest bit number wins when current grantee not requesting
+ assign take[0] = req[0]
+ & (~| (keep & ({width{1'b1}} << 1))); // no 'keep' from lower-priority inputs
+ genvar i;
+ generate
+ for (i=1; i < width; i = i + 1) begin : arb
+ assign take[i] = req[i]
+ & (~| (keep & ({width{1'b1}} << (i+1)))) // no 'keep' from lower-priority inputs
+ & (~| (req & {i{1'b1}})); // no 'req' from higher-priority inputs
+ end
+ endgenerate
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_csr_common.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_csr_common.sv
new file mode 100644
index 0000000000000000000000000000000000000000..dbe3e5a5fcf1db4a9ce64efc08efa2005e19cbe8
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_csr_common.sv
@@ -0,0 +1,209 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common control & status register map for transceiver PHY IP
+// Applies to Stratix V-generation basic PHY components
+//
+// $Header$
+//
+
+`timescale 1 ps / 1 ps
+
+module alt_xcvr_csr_common #(
+ parameter lanes = 1,
+ parameter plls = 1
+)
+(
+ // user data (avalon-MM formatted)
+ input wire clk,
+ input tri0 reset,
+ input wire [7:0] address,
+ input tri1 read,
+ output reg [31:0] readdata = 0,
+ input tri0 write,
+ input wire [31:0] writedata,
+
+ // transceiver status inputs to this CSR
+ input wire [plls - 1 : 0] pll_locked,
+ input wire [lanes - 1 : 0] rx_is_lockedtoref,
+ input wire [lanes - 1 : 0] rx_is_lockedtodata,
+ input wire [lanes - 1 : 0] rx_signaldetect,
+
+ // reset controller outputs
+ input wire reset_controller_tx_ready,
+ input wire reset_controller_rx_ready,
+ input wire reset_controller_pll_powerdown,
+ input wire reset_controller_tx_digitalreset,
+ input wire reset_controller_rx_analogreset,
+ input wire reset_controller_rx_digitalreset,
+
+ // read/write control registers
+ // to reset controller
+ output reg csr_reset_tx_digital = 0,
+ output reg csr_reset_rx_digital = 0,
+ output reg csr_reset_all = 1, // power-up to 1 to trigger auto-init sequence
+ // to PMA and PCS reset inputs
+ output wire csr_pll_powerdown, // reset controller or manual
+ output wire [lanes - 1 : 0] csr_tx_digitalreset, // reset controller or manual
+ output wire [lanes - 1 : 0] csr_rx_analogreset, // reset controller or manual
+ output wire [lanes - 1 : 0] csr_rx_digitalreset, // reset controller or manual
+ // common PMA controls
+ output reg [lanes - 1 : 0] csr_phy_loopback_serial = 0,
+ output reg [lanes - 1 : 0] csr_rx_set_locktoref = 0,
+ output reg [lanes - 1 : 0] csr_rx_set_locktodata = 0
+);
+ import alt_xcvr_csr_common_h::*;
+
+ localparam sync_stages = 2; // number of sync stages for transceiver status signals
+ localparam sync_stages_str = "2"; // number of sync stages specified as string (for timing constraints)
+ integer stage;
+
+ // Parameter strings for embedded timing constraints
+ localparam CSR_PLLLOCKED_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_common*csr_pll_locked*[",sync_stages_str,"]*]\""};
+ localparam CSR_RXISLOCKED_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_common*csr_rx_is_locked*[",sync_stages_str,"]*]\""};
+ localparam CSR_RXSIGNALDET_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_common*csr_rx_signaldetect*[",sync_stages_str,"]*]\""};
+ localparam SDC_CONSTRAINTS = {CSR_PLLLOCKED_CONSTRAINT,";",CSR_RXISLOCKED_CONSTRAINT,";",CSR_RXSIGNALDET_CONSTRAINT};
+
+ // internal control registers
+ reg [lanes - 1 : 0] csr_interrupt_ch_bitmask = {lanes{1'b1}};
+ // fine reset control. 'OR' with reset controller equivalent signals
+ reg csr_reset_or_pll_powerdown = 0; // fine reset control
+ reg csr_reset_or_reset_tx_digital = 0; // fine reset control
+ reg csr_reset_or_reset_rx_analog = 0; // fine reset control
+ reg csr_reset_or_reset_rx_digital = 0; // fine reset control
+ reg [lanes - 1 : 0] csr_reset_ch_bitmask = {lanes{1'b1}};
+
+ // read-only status registers
+ // These are synchronized forms of transceiver status signals
+ // async inputs go to reg [sync_stages], and come out synchronized at reg [1]
+ (* altera_attribute = SDC_CONSTRAINTS *) // Apply timing constraints (does not matter which node)
+ reg [plls - 1 : 0] csr_pll_locked [sync_stages:1];
+ reg [lanes - 1 : 0] csr_rx_is_lockedtoref [sync_stages:1];
+ reg [lanes - 1 : 0] csr_rx_is_lockedtodata [sync_stages:1];
+ reg [lanes - 1 : 0] csr_rx_signaldetect [sync_stages:1];
+
+ always @(posedge clk or posedge reset) begin
+ if (reset == 1) begin
+ readdata <= 0;
+ csr_interrupt_ch_bitmask <= {lanes{1'b1}};
+
+ csr_reset_tx_digital <= 0;
+ csr_reset_rx_digital <= 0;
+ csr_reset_all <= 1; // reset to 1 to trigger auto-init sequence
+ csr_reset_ch_bitmask <= {lanes{1'b1}};
+ csr_reset_or_pll_powerdown <= 0; // fine reset control
+ csr_reset_or_reset_tx_digital <= 0; // fine reset control
+ csr_reset_or_reset_rx_analog <= 0; // fine reset control
+ csr_reset_or_reset_rx_digital <= 0; // fine reset control
+
+ csr_phy_loopback_serial <= 0;
+ csr_rx_set_locktoref <= 0;
+ csr_rx_set_locktodata <= 0;
+ end
+ else begin
+ // decode read & write for each supported address
+ case (address)
+ // interrupt control
+ ADDR_INTERRUPT_CH_BITMASK: begin
+ readdata <= (32'd0 | csr_interrupt_ch_bitmask);
+ if (write) csr_interrupt_ch_bitmask <= writedata[lanes-1:0];
+ end
+
+ // reset control
+ ADDR_RESET_CONTROL: begin
+ // on read, returns two bits: bit0: TX ready, bit1: RX ready
+ readdata <= (32'd0 | {reset_controller_rx_ready, reset_controller_tx_ready});
+ // on write, bit0 is 'reset_tx_digital', bit1 is 'reset_rx_digital', bit2 is 'reset_all'
+ //if (write) begin
+ // reset_all write side-effect: when write a '1', force all reset_ch_bitmask bits to '1'
+ // csr_reset_ch_bitmask <= csr_reset_ch_bitmask | {(lanes){writedata[2]}};
+ //end
+ end
+ ADDR_RESET_CH_BITMASK: begin
+ readdata <= (32'd0 | csr_reset_ch_bitmask);
+ if (write) csr_reset_ch_bitmask <= writedata[lanes-1:0];
+ end
+
+ // loopback control
+ ADDR_PHY_LOOPBACK_SERIAL,
+ ADDR_PMA_LOOPBACK_SERIAL: begin
+ readdata <= (32'd0 | csr_phy_loopback_serial);
+ if (write) csr_phy_loopback_serial <= writedata[lanes-1:0];
+ end
+
+ // PMA control and status
+ ADDR_PMA_RX_SET_LOCKTOREF: begin
+ readdata <= (32'd0 | csr_rx_set_locktoref);
+ if (write) csr_rx_set_locktoref <= writedata[lanes-1:0];
+ end
+ ADDR_PMA_RX_SET_LOCKTODATA: begin
+ readdata <= (32'd0 | csr_rx_set_locktodata);
+ if (write) csr_rx_set_locktodata <= writedata[lanes-1:0];
+ end
+ // PMA status (read-only)
+ ADDR_PMA_PLL_IS_LOCKED: readdata <= (32'd0 | csr_pll_locked[1]);
+ ADDR_PMA_RX_IS_LOCKEDTOREF: readdata <= (32'd0 | csr_rx_is_lockedtoref[1]);
+ ADDR_PMA_RX_IS_LOCKEDTODATA: readdata <= (32'd0 | csr_rx_is_lockedtodata[1]);
+ ADDR_PMA_RX_SIGNALDETECT: readdata <= (32'd0 | csr_rx_signaldetect[1]);
+
+ // Fine reset control - device dependent
+ ADDR_RESET_FINE_CONTROL: begin
+ // bit 0: 'pll_powerdown', 1: 'reset_tx_digital', 2: 'reset_rx_analog', 3: 'reset_rx_digital'
+
+ readdata <= (32'd0 | {csr_reset_or_reset_rx_digital, csr_reset_or_reset_rx_analog,
+ csr_reset_or_reset_tx_digital, csr_reset_or_pll_powerdown});
+ if (write) begin
+ csr_reset_or_pll_powerdown <= writedata[0]; // fine reset control
+ csr_reset_or_reset_tx_digital <= writedata[1]; // fine reset control
+ csr_reset_or_reset_rx_analog <= writedata[2]; // fine reset control
+ csr_reset_or_reset_rx_digital <= writedata[3]; // fine reset control
+ end
+ end
+
+
+ default: readdata <= ~ 32'd0; // use too many LEs?
+ endcase
+
+ // special handling for registers that must auto-clear on cycle after a write
+ // reset control. on write, bit0 is 'reset_tx_digital', bit1 is 'reset_rx_digital', bit2 is 'reset_all'
+ csr_reset_tx_digital <= (address == ADDR_RESET_CONTROL) & write & writedata[0];
+ csr_reset_rx_digital <= (address == ADDR_RESET_CONTROL) & write & writedata[1];
+ csr_reset_all <= (address == ADDR_RESET_CONTROL) & write & writedata[2];
+
+ // synchronization registers for status signals from transceivers
+ csr_pll_locked[sync_stages] <= pll_locked; // input from transceiver
+ csr_rx_is_lockedtoref[sync_stages] <= rx_is_lockedtoref;
+ csr_rx_is_lockedtodata[sync_stages] <= rx_is_lockedtodata;
+ csr_rx_signaldetect[sync_stages] <= rx_signaldetect;
+ for (stage=2; stage <= sync_stages; stage = stage + 1) begin
+ // additional sync stages
+ csr_pll_locked[stage-1] <= csr_pll_locked[stage];
+ csr_rx_is_lockedtoref[stage-1] <= csr_rx_is_lockedtoref[stage];
+ csr_rx_is_lockedtodata[stage-1] <= csr_rx_is_lockedtodata[stage];
+ csr_rx_signaldetect[stage-1] <= csr_rx_signaldetect[stage];
+ end
+ end
+ end
+
+ // combine reset controller and CSR manual reset control settings
+ assign csr_pll_powerdown = reset_controller_pll_powerdown; // cut manual PLL reset path
+ // | csr_reset_or_pll_powerdown;
+ assign csr_tx_digitalreset = csr_reset_ch_bitmask & {(lanes)
+ {reset_controller_tx_digitalreset | csr_reset_or_reset_tx_digital}};
+ assign csr_rx_analogreset = csr_reset_ch_bitmask & {(lanes)
+ {reset_controller_rx_analogreset | csr_reset_or_reset_rx_analog}};
+ assign csr_rx_digitalreset = csr_reset_ch_bitmask & {(lanes)
+ {reset_controller_rx_digitalreset | csr_reset_or_reset_rx_digital}};
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_csr_common_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_csr_common_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..a323c0a2a16722d20880e2fd2d694fe5031fe780
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_csr_common_h.sv
@@ -0,0 +1,61 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common control & status register map for transceiver PHY IP
+// Applies to Stratix V-generation basic PHY components
+//
+// $Header$
+//
+// PACKAGE DECLARATION
+
+`timescale 1 ps / 1 ps
+
+package alt_xcvr_csr_common_h;
+
+ localparam alt_xcvr_csr_addr_width = 8;
+
+ // register bitmap ---------------------------------------------------------
+ // common blocks, interrupt control
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_INTERRUPT_CH_BITMASK = 1;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_INTERRUPT_ENABLE_BITMASK = 2;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_INTERRUPT_SOURCE = 3;
+
+ // common blocks, loopback control
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PHY_LOOPBACK_SERIAL = 6;
+
+ // common blocks, reset control
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_RESET_CONTROL_BASE = 64;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_RESET_CH_BITMASK = ADDR_RESET_CONTROL_BASE + 8'd1;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_RESET_CONTROL = ADDR_RESET_CONTROL_BASE + 8'd2;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_RESET_FINE_CONTROL = ADDR_RESET_CONTROL_BASE + 8'd4;
+
+ // common blocks, PMA common control & status
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_COMMON_BASE = 32;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_PLL_IS_LOCKED = ADDR_PMA_COMMON_BASE + 8'd2;
+ // common blocks, PMA channel control & status
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_CHANNEL_BASE = 96;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_LOOPBACK_SERIAL = ADDR_PMA_CHANNEL_BASE + 8'd1;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_RX_SIGNALDETECT = ADDR_PMA_CHANNEL_BASE + 8'd3;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_RX_SET_LOCKTODATA = ADDR_PMA_CHANNEL_BASE + 8'd4;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_RX_SET_LOCKTOREF = ADDR_PMA_CHANNEL_BASE + 8'd5;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_RX_IS_LOCKEDTODATA = ADDR_PMA_CHANNEL_BASE + 8'd6;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_RX_IS_LOCKEDTOREF = ADDR_PMA_CHANNEL_BASE + 8'd7;
+
+ // external block for PCS control & status
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS_BASE = 128; // 128-255
+
+ // First word in every PCS CSR is lane # (or lane group # as appropriate)
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS_LANE_GROUP = ADDR_PCS_BASE + 8'd0;
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_csr_pcs8g.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_csr_pcs8g.sv
new file mode 100644
index 0000000000000000000000000000000000000000..62ddfa2dce74f10cf83c30cd54f72573bbf216be
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_csr_pcs8g.sv
@@ -0,0 +1,350 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common control & status register map for transceiver PHY IP
+// Applies to Stratix V-generation basic PHY components
+//
+// $Header$
+//
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_csr_pcs8g #(
+ parameter lanes = 1,
+ parameter words = 2 // for status bits that are per-word, like 8B10B status
+)
+(
+ // user data (avalon-MM formatted)
+ input wire clk,
+ input tri0 reset,
+ input wire [7:0] address,
+ input tri1 read,
+ output reg [31:0] readdata = 0,
+ input tri0 write,
+ input wire [31:0] writedata,
+
+ input wire rx_clk, // to synchronize rx control outputs
+ input wire tx_clk, // to synchronize tx control outputs
+
+ // transceiver status inputs to this CSR
+ input wire [lanes*words - 1 : 0] rx_patterndetect,
+ input wire [lanes*words - 1 : 0] rx_syncstatus,
+ input wire [lanes*words - 1 : 0] rx_errdetect,
+ input wire [lanes*words - 1 : 0] rx_disperr,
+ input wire [lanes - 1 : 0] rx_phase_comp_fifo_error,
+ input wire [lanes - 1 : 0] tx_phase_comp_fifo_error,
+ input wire [lanes*5 - 1: 0] rx_bitslipboundaryselectout,
+ input wire [lanes - 1 : 0] rlv,
+ input wire [lanes*words - 1 : 0] rx_a1a2sizeout,
+
+ // read/write control outputs
+ // PCS controls
+ output wire [lanes - 1 : 0] csr_tx_invpolarity,
+ output wire [lanes*5 - 1 : 0] csr_tx_bitslipboundaryselect,
+ output wire [lanes - 1 : 0] csr_rx_invpolarity,
+ output wire [lanes - 1 : 0] csr_rx_enapatternalign,
+ output wire [lanes - 1 : 0] csr_rx_bitreversalenable,
+ output wire [lanes - 1 : 0] csr_rx_bytereversalenable,
+ output wire [lanes - 1 : 0] csr_rx_bitslip,
+ output wire [lanes - 1 : 0] csr_rx_a1a2size
+);
+ import alt_xcvr_csr_common_h::*;
+ import alt_xcvr_csr_pcs8g_h::*;
+
+ localparam sync_stages = 2; // number of sync stages for transceiver status signals
+ localparam sync_stages_str = "2"; // number of sync stages specified as string (for timing constraints)
+ localparam LANE_REGW = 5;
+
+ // Parameter strings for embedded timing constraints
+ localparam SYNC_RX_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_pcs8g*sync_rx_*[",sync_stages_str,"]*]\""};
+ localparam SYNC_TX_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_pcs8g*sync_tx_*[",sync_stages_str,"]*]\""};
+ localparam CSR_REG_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_pcs8g*csr_indexed_read_only_reg*sreg[",sync_stages_str,"]*]\""};
+ localparam SDC_CONSTRAINTS = {SYNC_RX_CONSTRAINT,";",SYNC_TX_CONSTRAINT,";",CSR_REG_CONSTRAINT};
+
+ // internal registers
+ reg [LANE_REGW-1:0] reg_lane_number = 0; // lane or group number for indirection
+
+ ////////////////////////////////////////////////////////
+ // Read/Write CSR registers with lane indirection
+ ////////////////////////////////////////////////////////
+ // Apply false path timing constraints to synchronization registers. (It does not matter as to which node these are applied).
+ (* altera_attribute = SDC_CONSTRAINTS *)
+ reg [lanes - 1 : 0] reg_tx_invpolarity = 0;
+ reg [lanes - 1 : 0] sync_tx_invpolarity [sync_stages:1]; // synchronize to tx_clk
+ wire [lanes - 1 : 0] write_tx_invpolarity; // indexed write group muxed in
+ wire [0 : 0] lane_tx_invpolarity; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_tx_invpolarity(.in_narrow(writedata[0]),
+ .in_wide(reg_tx_invpolarity), .sel(reg_lane_number),
+ .out_narrow(lane_tx_invpolarity), .out_wide(write_tx_invpolarity));
+
+ reg [lanes*5 - 1 : 0] reg_tx_bitslipboundaryselect = 0;
+ reg [lanes*5 - 1 : 0] sync_tx_bitslipboundaryselect [sync_stages:1]; //synchronize to tx_clk
+ wire [lanes*5 - 1 : 0] write_tx_bitslipboundaryselect; //indexed write group muxed in
+ wire [4:0] lane_tx_bitslipboundaryselect; //selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(5), .sel_size(LANE_REGW), .init_value(0))
+ wmux_tx_bitslipboundaryselect(.in_narrow(writedata[5:1]),
+ .in_wide(reg_tx_bitslipboundaryselect), .sel(reg_lane_number),
+ .out_narrow(lane_tx_bitslipboundaryselect), .out_wide(write_tx_bitslipboundaryselect));
+
+ reg [lanes - 1 : 0] reg_rx_invpolarity = 0;
+ reg [lanes - 1 : 0] sync_rx_invpolarity [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_invpolarity; // indexed write group muxed in
+ wire [0 : 0] lane_rx_invpolarity; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_invpolarity(.in_narrow(writedata[0]),
+ .in_wide(reg_rx_invpolarity), .sel(reg_lane_number),
+ .out_narrow(lane_rx_invpolarity), .out_wide(write_rx_invpolarity));
+
+ reg [lanes - 1 : 0] reg_rx_enapatternalign = 0;
+ reg [lanes - 1 : 0] sync_rx_enapatternalign [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_enapatternalign; // indexed write group muxed in
+ wire [0 : 0] lane_rx_enapatternalign; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_enapatternalign(.in_narrow(writedata[0]),
+ .in_wide(reg_rx_enapatternalign), .sel(reg_lane_number),
+ .out_narrow(lane_rx_enapatternalign), .out_wide(write_rx_enapatternalign));
+
+ reg [lanes - 1 : 0] reg_rx_bitreversalenable = 0;
+ reg [lanes - 1 : 0] sync_rx_bitreversalenable [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_bitreversalenable; // indexed write group muxed in
+ wire [0 : 0] lane_rx_bitreversalenable; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_bitreversalenable(.in_narrow(writedata[1]),
+ .in_wide(reg_rx_bitreversalenable), .sel(reg_lane_number),
+ .out_narrow(lane_rx_bitreversalenable), .out_wide(write_rx_bitreversalenable));
+
+ reg [lanes - 1 : 0] reg_rx_bytereversalenable = 0;
+ reg [lanes - 1 : 0] sync_rx_bytereversalenable [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_bytereversalenable; // indexed write group muxed in
+ wire [0 : 0] lane_rx_bytereversalenable; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_bytereversalenable(.in_narrow(writedata[2]),
+ .in_wide(reg_rx_bytereversalenable), .sel(reg_lane_number),
+ .out_narrow(lane_rx_bytereversalenable), .out_wide(write_rx_bytereversalenable));
+
+ reg [lanes - 1 : 0] reg_rx_bitslip = 0;
+ reg [lanes - 1 : 0] sync_rx_bitslip [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_bitslip; // indexed write group muxed in
+ wire [0 : 0] lane_rx_bitslip; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_bitslip(.in_narrow(writedata[3]),
+ .in_wide(reg_rx_bitslip), .sel(reg_lane_number),
+ .out_narrow(lane_rx_bitslip), .out_wide(write_rx_bitslip));
+
+ reg [lanes - 1 : 0] reg_rx_a1a2size = 0;
+ reg [lanes - 1 : 0] sync_rx_a1a2size [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_a1a2size; // indexed write group muxed in
+ wire [0 : 0] lane_rx_a1a2size; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_a1a2size(.in_narrow(writedata[3]),
+ .in_wide(reg_rx_a1a2size), .sel(reg_lane_number),
+ .out_narrow(lane_rx_a1a2size), .out_wide(write_rx_a1a2size));
+
+ ////////////////////////////////////////////////////////
+ // Read-only CSR registers with lane indirection
+ ////////////////////////////////////////////////////////
+ // read-only status registers are synchronized forms of transceiver status signals
+ // async inputs go to reg [sync_stages], and come out synchronized at reg [1]
+ ////////////////////////////////////////////////////////
+ // read selectors (muxes) that index using the indirect lane (group) number
+ wire [words-1 : 0] lane_rx_patterndetect;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(words), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_patterndetect(.clk(clk), .async_in_wide(rx_patterndetect),
+ .sel(reg_lane_number), .out_narrow(lane_rx_patterndetect));
+
+ wire [words-1 : 0] lane_rx_syncstatus;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(words), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_syncstatus(.clk(clk), .async_in_wide(rx_syncstatus),
+ .sel(reg_lane_number), .out_narrow(lane_rx_syncstatus));
+
+ wire [words-1 : 0] lane_rx_errdetect;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(words), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_errdetect(.clk(clk), .async_in_wide(rx_errdetect),
+ .sel(reg_lane_number), .out_narrow(lane_rx_errdetect));
+
+ wire [words-1 : 0] lane_rx_disperr;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(words), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_disperr(.clk(clk), .async_in_wide(rx_disperr),
+ .sel(reg_lane_number), .out_narrow(lane_rx_disperr));
+
+ wire [words-1 : 0] lane_rx_a1a2sizeout;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(words), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_a1a2sizeout(.clk(clk), .async_in_wide(rx_a1a2sizeout),
+ .sel(reg_lane_number), .out_narrow(lane_rx_a1a2sizeout));
+
+ wire [0 : 0] lane_rx_phase_comp_fifo_error;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_phase_comp_fifo_error(.clk(clk), .async_in_wide(rx_phase_comp_fifo_error),
+ .sel(reg_lane_number), .out_narrow(lane_rx_phase_comp_fifo_error));
+
+ wire [4 : 0] lane_rx_bitslipboundaryselectout;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(5), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_bitslipboundaryselectout(.clk(clk), .async_in_wide(rx_bitslipboundaryselectout),
+ .sel(reg_lane_number), .out_narrow(lane_rx_bitslipboundaryselectout));
+
+ wire [0 : 0] lane_tx_phase_comp_fifo_error;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_tx_phase_comp_fifo_error(.clk(clk), .async_in_wide(tx_phase_comp_fifo_error),
+ .sel(reg_lane_number), .out_narrow(lane_tx_phase_comp_fifo_error));
+
+ wire [0 : 0] lane_rlv;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rlv(.clk(clk), .async_in_wide(rlv),
+ .sel(reg_lane_number), .out_narrow(lane_rlv));
+
+
+ always @(posedge clk or posedge reset) begin
+ if (reset == 1) begin
+ readdata <= 0;
+ reg_lane_number <= 0;
+ reg_tx_invpolarity <= 0;
+ reg_tx_bitslipboundaryselect <= 0;
+ reg_rx_invpolarity <= 0;
+ reg_rx_enapatternalign <= 0;
+ reg_rx_bitreversalenable <= 0;
+ reg_rx_bytereversalenable <= 0;
+ reg_rx_bitslip <= 0;
+ reg_rx_a1a2size <= 0;
+
+ // no need to clear synchronization registers, since they do not store state
+ end
+ else begin
+ // decode read & write for each supported address
+ case (address)
+ // lane or group number for indirection
+ ADDR_PCS_LANE_GROUP: begin
+ readdata <= (32'd0 | reg_lane_number);
+ if (write) reg_lane_number <= writedata[LANE_REGW-1:0];
+ end
+
+ // offset + 1, read-only RX status bits
+ // bit 0, rx_phase_comp_fifo_error
+ // bit 5:1, rx_bitslipboundaryselectout
+ ADDR_PCS8G_RX_STATUS: begin
+ readdata <= (32'd0 |
+ {lane_rx_bitslipboundaryselectout, //bit 5-1
+ lane_rx_phase_comp_fifo_error}); // bit 0
+ end
+
+ // offset + 2, read-only TX status bits
+ // bit 0, tx_phase_comp_fifo_error
+ ADDR_PCS8G_TX_STATUS: begin
+ readdata <= (32'd0 | lane_tx_phase_comp_fifo_error); // bit 0
+ end
+
+ // offset + 3, read/write TX control bits
+ // bit 0, tx_invpolarity
+ // bit 5:1, tx_bitslipboundaryselect
+ ADDR_PCS8G_TX_CONTROL: begin
+ readdata <= (32'd0 | {lane_tx_bitslipboundaryselect, lane_tx_invpolarity});
+ if (write)
+ begin
+ reg_tx_invpolarity <= write_tx_invpolarity;
+ reg_tx_bitslipboundaryselect <= write_tx_bitslipboundaryselect;
+ end
+ end
+
+ // offset + 4, read/write RX control bits
+ // bit 0, rx_invpolarity
+ ADDR_PCS8G_RX_CONTROL: begin
+ readdata <= (32'd0 | lane_rx_invpolarity);
+ if (write) reg_rx_invpolarity <= write_rx_invpolarity;
+ end
+
+ // offset + 5, read/write RX WA control bits
+ // bit 0, rx_enapatternalign
+ // bit 1, rx_bitreversalenable
+ // bit 2, rx_bytereversalenable
+ // bit 3, rx_bitslip
+ // bit 4, rx_a1a2size
+ ADDR_PCS8G_RX_WA_CONTROL: begin
+ readdata <= (32'd0 | { lane_rx_a1a2size, // bit 4
+ lane_rx_bitslip, // bit 3
+ lane_rx_bytereversalenable, // bit 2
+ lane_rx_bitreversalenable, // bit 1
+ lane_rx_enapatternalign}); // bit 0
+ if (write)
+ begin
+ reg_rx_enapatternalign <= write_rx_enapatternalign;
+ reg_rx_bitreversalenable <= write_rx_bitreversalenable;
+ reg_rx_bytereversalenable <= write_rx_bytereversalenable;
+ reg_rx_bitslip <= write_rx_bitslip;
+ reg_rx_a1a2size <= write_rx_a1a2size;
+ end
+ end
+
+ // offset + 5, read RX WA status bits
+ // bit 3:0, rx_errdetect
+ // bit 7:4, rx_syncstatus
+ // bit 11:8, rx_disperr
+ // bit 15:12, rx_patterndetect
+ // bit 16, rlv
+ // bit 23:20, rx_a1a2sizeout
+ ADDR_PCS8G_RX_WA_STATUS: begin
+ readdata <= (32'd0 | {(4'b0 | lane_rx_a1a2sizeout), // bit 23:20
+ (4'b0 | lane_rlv), // bit 16
+ (4'b0 | lane_rx_patterndetect), // bit 15:12
+ (4'b0 | lane_rx_disperr), // bit 11:8
+ (4'b0 | lane_rx_syncstatus), // bit 7:4
+ (4'b0 | lane_rx_errdetect)}); // bit 3:0
+ end
+
+ default: readdata <= ~ 32'd0; // use too many LEs?
+ endcase
+ end
+ end
+
+ // synchronize TX controls to tx_clk before generating output
+ // sysclk-sync'ed input enters at [sync_stages], and tx_clk-sync'ed output exist at [1]
+ integer stage;
+ always @(posedge tx_clk) begin
+ sync_tx_invpolarity[sync_stages] <= reg_tx_invpolarity;
+ sync_tx_bitslipboundaryselect[sync_stages] <= reg_tx_bitslipboundaryselect;
+ for (stage=2; stage <= sync_stages; stage = stage + 1) begin
+ // additional sync stages
+ sync_tx_invpolarity[stage-1] <= sync_tx_invpolarity[stage];
+ sync_tx_bitslipboundaryselect[stage-1] <= sync_tx_bitslipboundaryselect[stage];
+ end
+ end
+ assign csr_tx_invpolarity = sync_tx_invpolarity[1];
+ assign csr_tx_bitslipboundaryselect = sync_tx_bitslipboundaryselect[1];
+
+ // synchronize RX controls to rx_clk before generating output
+ // sysclk-sync'ed input enters at [sync_stages], and rx_clk-sync'ed output exist at [1]
+ always @(posedge rx_clk) begin
+ sync_rx_invpolarity[sync_stages] <= reg_rx_invpolarity;
+ sync_rx_enapatternalign[sync_stages] <= reg_rx_enapatternalign;
+ sync_rx_bitreversalenable[sync_stages] <= reg_rx_bitreversalenable;
+ sync_rx_bytereversalenable[sync_stages] <= reg_rx_bytereversalenable;
+ sync_rx_bitslip[sync_stages] <= reg_rx_bitslip;
+ sync_rx_a1a2size[sync_stages] <= reg_rx_a1a2size;
+ for (stage=2; stage <= sync_stages; stage = stage + 1) begin
+ // additional sync stages
+ sync_rx_invpolarity[stage-1] <= sync_rx_invpolarity[stage];
+ sync_rx_enapatternalign[stage-1] <= sync_rx_enapatternalign[stage];
+ sync_rx_bitreversalenable[stage-1] <= sync_rx_bitreversalenable[stage];
+ sync_rx_bytereversalenable[stage-1] <= sync_rx_bytereversalenable[stage];
+ sync_rx_bitslip[stage-1] <= sync_rx_bitslip[stage];
+ sync_rx_a1a2size[stage-1] <= sync_rx_a1a2size[stage];
+ end
+ end
+ assign csr_rx_invpolarity = sync_rx_invpolarity[1];
+ assign csr_rx_enapatternalign = sync_rx_enapatternalign[1];
+ assign csr_rx_bitreversalenable = sync_rx_bitreversalenable[1];
+ assign csr_rx_bytereversalenable = sync_rx_bytereversalenable[1];
+ assign csr_rx_bitslip = sync_rx_bitslip[1];
+ assign csr_rx_a1a2size = sync_rx_a1a2size[1];
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_csr_pcs8g_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_csr_pcs8g_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..09f65ef3aee3227b1f9f9ba7d3359a300eb092ac
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_csr_pcs8g_h.sv
@@ -0,0 +1,33 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common control & status register map for transceiver PHY IP
+// Applies to Stratix V-generation basic PHY components
+//
+// $Header$
+//
+// PACKAGE DECLARATION
+package alt_xcvr_csr_pcs8g_h;
+
+ import alt_xcvr_csr_common_h::*;
+
+ // 8G PCS, a.k.a. "Standard PCS", control and status bits
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_RX_STATUS = ADDR_PCS_BASE + 8'd1;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_TX_STATUS = ADDR_PCS_BASE + 8'd2;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_TX_CONTROL = ADDR_PCS_BASE + 8'd3;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_RX_CONTROL = ADDR_PCS_BASE + 8'd4;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_RX_WA_CONTROL = ADDR_PCS_BASE + 8'd5;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_RX_WA_STATUS = ADDR_PCS_BASE + 8'd6;
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_csr_selector.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_csr_selector.sv
new file mode 100644
index 0000000000000000000000000000000000000000..2e843e4597c8292f41a2d244cf5bb2dae2d70abc
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_csr_selector.sv
@@ -0,0 +1,116 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Select a sub-group from a wide register
+// Useful for indirection indexing
+//
+// $Header$
+//
+
+`timescale 1 ns / 1 ns
+
+module csr_mux #(
+ parameter groups = 2,
+ parameter grp_size = 1,
+ parameter sel_size = 1
+)
+(
+ input wire [groups*grp_size-1:0] in_wide,
+ input tri0 [sel_size-1:0] sel,
+ output wire [grp_size-1:0] out_narrow
+);
+// lpm_mux #(.lpm_size(groups), .lpm_width(grp_size), .lpm_widths(sel_size))
+// mux (.data(in_wide), .sel(sel), .result(out_narrow));
+ wire [grp_size-1:0] in_groups [groups-1:0];
+
+ // a synthesizable mux, with a parameterized number of inputs
+ genvar i;
+ assign in_groups[0] = in_wide[grp_size-1:0] & {grp_size{sel == 0}};
+ generate for (i=1; i<groups; i = i+1) begin: mux
+ assign in_groups[i] = in_groups[i-1] | in_wide[i*grp_size +: grp_size] & {grp_size{sel == i}};
+ end
+ endgenerate
+ assign out_narrow = in_groups[groups-1];
+endmodule
+
+//
+// write to a sub-group of a wide register
+// Useful for indirection indexing on write
+//
+module csr_indexed_write_mux #(
+ parameter groups = 2,
+ parameter grp_size = 1,
+ parameter sel_size = 1,
+ parameter init_value = 0
+)
+(
+ input wire [grp_size-1:0] in_narrow,
+ input tri0 [sel_size-1:0] sel,
+ output wire [grp_size-1:0] out_narrow, // for read back to mgmt interface
+ input wire [groups*grp_size-1:0] in_wide, // full-width control reg state
+ output wire [groups*grp_size-1:0] out_wide // to write to full-width control reg
+);
+ wire [groups*grp_size-1:0] wire_wide [groups-1:0];
+
+ // in_narrow is output in the group position indicated by .sel() input
+ genvar i;
+ assign wire_wide[0] = (in_wide & {grp_size{sel != 0}}) | (in_narrow & {grp_size{sel == 0}});
+ generate for (i=1; i<groups; i = i+1) begin: mux
+ assign wire_wide[i] = wire_wide[i-1]
+ | (in_wide & {{grp_size{sel != i}}, {(grp_size*i){1'b0}}})
+ | ({in_narrow & {grp_size{sel == i}}, {(grp_size*i){1'b0}}});
+ end
+ endgenerate
+ assign out_wide = wire_wide[groups-1];
+
+ // generate out_narrow as ordinary mux of in_wide
+ csr_mux #(.groups(groups), .grp_size(grp_size), .sel_size(sel_size))
+ o_narrow(.in_wide(in_wide), .sel(sel), .out_narrow(out_narrow));
+
+endmodule
+
+//
+// read from a sub-group of a wide, async status input
+// Creates synchronization logic to sample in local clock domain
+// Useful for indirection indexing on read-only status bits
+//
+module csr_indexed_read_only_reg #(
+ parameter groups = 2,
+ parameter grp_size = 1,
+ parameter sel_size = 1,
+ parameter sync_stages = 2
+)
+(
+ input wire clk,
+ input tri0 [sel_size-1:0] sel,
+ output wire [grp_size-1:0] out_narrow, // for read back to mgmt interface
+ input wire [groups*grp_size-1:0] async_in_wide // full-width async status inputs
+);
+ // read-only status registers are synchronized forms of async status signals
+ // async inputs go to sreg [sync_stages], and come out synchronized at sreg [1]
+ reg [groups*grp_size-1:0] sreg [sync_stages:1];
+ integer stage;
+ always @(posedge clk) begin
+ sreg[sync_stages] <= async_in_wide;
+ for (stage=2; stage <= sync_stages; stage = stage + 1) begin
+ // additional sync stages
+ sreg[stage-1] <= sreg[stage];
+ end
+ end
+
+ // generate out_narrow as ordinary mux of out_wide
+ csr_mux #(.groups(groups), .grp_size(grp_size), .sel_size(sel_size))
+ o_narrow(.in_wide(sreg[1]), .sel(sel), .out_narrow(out_narrow));
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_m2s.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_m2s.sv
new file mode 100644
index 0000000000000000000000000000000000000000..143f8260ab27069cf2eb8fd54be2d08f84f018ec
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_m2s.sv
@@ -0,0 +1,61 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Master-to-slave access fabric
+//
+// Combined with external multi-master arbitration, this block gates
+// master read, write, address, and writedata outputs, and generates
+// a waitrequest when arbiter indicates access is not granted
+
+// $Header$
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_m2s #(
+ parameter width_addr = 3,
+ parameter width_data = 32
+) (
+ input wire clock,
+ output wire req, // request to arbiter for slave access
+ input wire grant,
+
+ // signals from/to master
+ input wire m_read,
+ input wire m_write,
+ input wire [width_addr-1:0] m_address,
+ input wire [width_data-1:0] m_writedata,
+ output wire [width_data-1:0] m_readdata,
+ output wire m_waitrequest,
+
+ // signals from/to slave
+ output wire s_read,
+ output wire s_write,
+ output wire [width_addr-1:0] s_address,
+ output wire [width_data-1:0] s_writedata,
+ input wire [width_data-1:0] s_readdata,
+ input wire s_waitrequest
+);
+
+ // If master is requesting access, generate waitreq until granted
+ assign req = m_read | m_write; // master access requests
+ assign m_waitrequest = grant ? s_waitrequest : req;
+
+ // gate outputs to slave with grant signal
+ assign s_read = m_read & grant;
+ assign s_write = m_write & grant;
+ assign s_address = m_address & {width_addr{grant}};
+ assign s_writedata = m_writedata & {width_data{grant}};
+
+ // slave data outputs pass through directly
+ assign m_readdata = s_readdata;
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_mgmt2dec.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_mgmt2dec.sv
new file mode 100644
index 0000000000000000000000000000000000000000..93ce24e6bb50518c47c242026699fb45dcee975a
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_mgmt2dec.sv
@@ -0,0 +1,90 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Management interface address decoder for Altera Transceiver PHY
+//
+// Addresses common case of 2 modules to be stitched together:
+// - 'top' PHY channel blocks (includes reset control, CSR, ...)
+// - dynamic reconfiguration block
+
+// $Header$
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_mgmt2dec (
+
+ // user-visible external management interface
+ input wire mgmt_clk_reset,
+ input wire mgmt_clk,
+
+ input wire [8:0] mgmt_address,
+ input wire mgmt_read,
+ output reg [31:0] mgmt_readdata = ~32'd0,
+ output reg mgmt_waitrequest = 0,
+ input wire mgmt_write,
+
+ // internal interface to 'top' csr block
+ output wire [7:0] topcsr_address,
+ output wire topcsr_read,
+ input wire [31:0] topcsr_readdata,
+ input wire topcsr_waitrequest,
+ output wire topcsr_write,
+
+ // internal interface to 'top' csr block
+ output wire [7:0] reconf_address,
+ output wire reconf_read,
+ input wire [31:0] reconf_readdata,
+ input wire reconf_waitrequest,
+ output wire reconf_write
+);
+ localparam width_swa = 7; // word address width of interface to slaves (2 for top.CSR and 1 for reconfig)
+ localparam dec_count = 2; // count of the total number of sub-components that can act
+ // as slaves to the mgmt interface
+ localparam dec_topcsr = 0; // uses 2 128-word address blocks
+ localparam dec_reconf = 1; // uses 1 128-word address block
+
+
+ ///////////////////////////////////////////////////////////////////////
+ // Decoder for multiple slaves of reconfig_mgmt interface
+ ///////////////////////////////////////////////////////////////////////
+ wire [dec_count-1:0] r_decode;
+ assign r_decode =
+ (mgmt_address[8:width_swa+1] == dec_topcsr) ? (({dec_count-dec_topcsr{1'b0}} | 1'b1) << dec_topcsr)
+ : (mgmt_address[8:width_swa] == 2'd2) ? (({dec_count-dec_reconf{1'b0}} | 1'b1) << dec_reconf)
+ : {dec_count{1'b0}};
+
+ // reconfig_mgmt output generation is muxing of decoded slave output
+ always @(*) begin
+ if (r_decode[dec_topcsr] == 1'b1) begin
+ mgmt_readdata = topcsr_readdata;
+ mgmt_waitrequest = topcsr_waitrequest;
+ end else if (r_decode[dec_reconf] == 1'b1) begin
+ mgmt_readdata = reconf_readdata;
+ mgmt_waitrequest = reconf_waitrequest;
+ end else begin
+ mgmt_readdata = -1;
+ mgmt_waitrequest = 1'b0;
+ end
+ end
+
+ // internal interface to 'top' csr block
+ assign topcsr_address = mgmt_address[width_swa:0]; // top.csr uses 2 128-word blocks
+ assign topcsr_read = mgmt_read & r_decode[dec_topcsr];
+ assign topcsr_write = mgmt_write & r_decode[dec_topcsr];
+
+ // internal interface to 'top' csr block
+ assign reconf_address = mgmt_address[width_swa-1:0]; // reconfig uses 1 128-word block
+ assign reconf_read = mgmt_read & r_decode[dec_reconf];
+ assign reconf_write = mgmt_write & r_decode[dec_reconf];
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_mgmt2dec_phyreconfig.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_mgmt2dec_phyreconfig.sv
new file mode 100644
index 0000000000000000000000000000000000000000..3993651a7280e45e8ed8823d62ce37b8836861c2
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_mgmt2dec_phyreconfig.sv
@@ -0,0 +1,110 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//-----------------------------------------------------------------------------
+//
+// Description: Custom management interface address decoder for Altera
+// transciever PHY. Addresses common case of 2 modules to be stitched together:
+// - 'top' PHY channel blocks (includes reset control, CSR, ...)
+// - dynamic reconfiguration block
+//
+// Authors: dunnikri 19-Aug-2010
+//
+// Copyright (c) Altera Corporation 1997 - 2010
+// All rights reserved.
+//
+//
+//-----------------------------------------------------------------------------
+
+//`timescale 1 ns / 1 ns
+
+module alt_xcvr_mgmt2dec_phyreconfig (
+
+ // user-visible external management interface
+ input wire mgmt_clk_reset,
+ input wire mgmt_clk,
+
+ input wire [8:0] mgmt_address,
+ input wire mgmt_read,
+ output reg [31:0] mgmt_readdata = ~32'd0,
+ output reg mgmt_waitrequest = 0,
+ input wire mgmt_write,
+
+ // internal interface to xaui phy block
+ output wire [7:0] sc_phy_address,
+ output wire sc_phy_read,
+ input wire [31:0] sc_phy_readdata,
+ input wire sc_phy_waitrequest,
+ output wire sc_phy_write,
+
+ // internal interface to reconfig block
+ output wire [6:0] sc_reconf_address,
+ output wire sc_reconf_read,
+ input wire [31:0] sc_reconf_readdata,
+ input wire sc_reconf_waitrequest,
+ output wire sc_reconf_write
+);
+ localparam width_swa = 7; // word address width of interface to slaves (2 for phy and 1 for reconfig)
+ localparam dec_count = 2; // count of the total number of sub-components that can act
+ // as slaves to the mgmt interface
+ localparam dec_sc_phy = 0; //
+ localparam dec_reconf = 1; //
+
+ ///////////////////////////////////////////////////////////////////////
+ // Decoder for multiple slaves of reconfig_mgmt interface
+ ///////////////////////////////////////////////////////////////////////
+ wire [dec_count-1:0] r_decode; //1-hot encoding
+
+ //-----------------------Memory Map Reference-------------------------
+ //--------------------------------------------------------------------
+ //Block | Word Address | Byte Address |
+ //-------------------------------------------------------------------
+ //PHY Common | 0x0 | 0x0 |
+ //PMA Controller | 0x20 | 0x80 |
+ //Reset Controller | 0x40 | 0x100 |
+ //PMA Channel Controller | 0x60 | 0x180 |
+ //PCS | 0x80 | 0x200 |
+ //XCVR Reconfig | 0x100 | 0x400 |
+ //--------------------------------------------------------------------
+
+ //Decoding is based on memory map word address
+ assign r_decode =
+ (mgmt_address[8:width_swa+1] == dec_sc_phy) ? (({dec_count-dec_sc_phy{1'b0}} | 1'b1) << dec_sc_phy)
+ : (mgmt_address[8:width_swa] == 2'd2) ? (({dec_count-dec_reconf{1'b0}} | 1'b1) << dec_reconf)
+ : {dec_count{1'b0}};
+
+ // reconfig_mgmt output generation is muxing of decoded slave output
+ always @(*) begin
+ if (r_decode[dec_sc_phy] == 1'b1) begin
+ mgmt_readdata = sc_phy_readdata;
+ mgmt_waitrequest = sc_phy_waitrequest;
+ end else if (r_decode[dec_reconf] == 1'b1) begin
+ mgmt_readdata = sc_reconf_readdata;
+ mgmt_waitrequest = sc_reconf_waitrequest;
+ end else begin
+ mgmt_readdata = -1;
+ mgmt_waitrequest = 1'b0;
+ end
+ end
+
+ // internal interface to 'top' phy block
+ assign sc_phy_address = mgmt_address[width_swa:0];
+ assign sc_phy_read = mgmt_read & r_decode[dec_sc_phy];
+ assign sc_phy_write = mgmt_write & r_decode[dec_sc_phy];
+
+ // internal interface to 'top' reconfig block
+ assign sc_reconf_address = mgmt_address[width_swa-1:0];
+ assign sc_reconf_read = mgmt_read & r_decode[dec_reconf];
+ assign sc_reconf_write = mgmt_write & r_decode[dec_reconf];
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_mgmt2dec_xaui.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_mgmt2dec_xaui.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5720dddc8ee64986827d0db95c96c90eec94cdf3
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_mgmt2dec_xaui.sv
@@ -0,0 +1,134 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//-----------------------------------------------------------------------------
+//
+// Description: Custom management interface address decoder for Altera
+// transciever PHY. Addresses common case of 3 modules to be stitched together:
+// - CSR, Alt_PMA controller, Alt_PMA_Channel controller
+//
+// Authors: dunnikri 19-Aug-2010
+//
+// Copyright (c) Altera Corporation 1997 - 2010
+// All rights reserved.
+//
+//
+//-----------------------------------------------------------------------------
+
+`timescale 1 ps / 1 ps
+
+module alt_xcvr_mgmt2dec_xaui (
+
+ // user-visible external management interface
+ input wire mgmt_clk_reset,
+ input wire mgmt_clk,
+
+ input wire [7:0] mgmt_address,
+ input wire mgmt_read,
+ output reg [31:0] mgmt_readdata = ~32'd0,
+ output reg mgmt_waitrequest = 0,
+ input wire mgmt_write,
+
+ // internal interface to xaui pma channel controller
+ output wire [5:0] sc_pma_ch_controller_address,
+ output wire sc_pma_ch_controller_read,
+ input wire [31:0] sc_pma_ch_controller_readdata,
+ input wire sc_pma_ch_controller_waitrequest,
+ output wire sc_pma_ch_controller_write,
+
+ // internal interface to pma controller block
+ output wire [1:0] sc_pma_controller_address,
+ output wire sc_pma_controller_read,
+ input wire [31:0] sc_pma_controller_readdata,
+ input wire sc_pma_controller_waitrequest,
+ output wire sc_pma_controller_write,
+
+ // internal interface to hxaui csr block
+ output wire [4:0] sc_csr_address,
+ output wire sc_csr_read,
+ input wire [31:0] sc_csr_readdata,
+ input wire sc_csr_waitrequest,
+ output wire sc_csr_write
+);
+ localparam width_swa = 7; // word address width of interface to slaves (2 for phy and 1 for reconfig)
+ localparam dec_count = 3; // count of the total number of sub-components that can act
+ // as slaves to the mgmt interface
+
+ localparam dec_pma_control = 0;
+ localparam dec_csr = 1;
+ localparam dec_pma_ch_control = 2;
+
+ //--------------------------------------------------------------------
+ //Block | Word Address | Byte Address |
+ //-------------------------------------------------------------------
+ //PHY Common | 0x0 | 0x0 |
+ //PMA Controller | 0x20 | 0x80 |
+ //Reset Controller | 0x40 | 0x100 |
+ //PMA Channel Controller | 0x60 | 0x180 |
+ //PCS | 0x80 | 0x200 |
+ //XCVR Reconfig | 0x100 | 0x400 |
+ //-------------------------------------------------------------------
+
+
+ ///////////////////////////////////////////////////////////////////////
+ // Decoder for multiple slaves of reconfig_mgmt interface
+ ///////////////////////////////////////////////////////////////////////
+ wire [dec_count-1:0] r_decode; //1-hot encoding
+
+ //PMA Controller - 0x20 (0010 0000)
+ //Reset Controller - 0x40 (0100 0000)
+ //Channel Controller - 0x60 (0110 0000)
+ //PCS - 0x80 (1000 0000)
+ //Consider first 3 MSBs for decoding
+ /*assign r_decode =
+ (mgmt_address[7:5] == 3'd1) ? (({dec_count-dec_pma_control{1'b0}} | 1'b1) << dec_pma_control)
+ : (mgmt_address[7:5] == 3'd4) ? (({dec_count-dec_csr{1'b0}} | 1'b1) << dec_csr)
+ : (mgmt_address[7:5] == 3'd3) ? (({dec_count-dec_pma_ch_control{1'b0}} | 1'b1) << dec_pma_ch_control)
+ : {dec_count{1'b0}};*/
+
+ assign r_decode[0] = (!mgmt_address[7]) & (!mgmt_address[6]) & (mgmt_address[5]);
+ assign r_decode[1] = (mgmt_address[7]) & (!mgmt_address[6]) & (!mgmt_address[5]);
+ assign r_decode[2] = (!mgmt_address[7]) & (mgmt_address[6]);
+
+
+ always @(*) begin
+ if (r_decode[dec_pma_ch_control] == 1'b1) begin
+ mgmt_readdata = sc_pma_ch_controller_readdata;
+ mgmt_waitrequest = sc_pma_ch_controller_waitrequest;
+ end else if (r_decode[dec_pma_control] == 1'b1) begin
+ mgmt_readdata = sc_pma_controller_readdata;
+ mgmt_waitrequest = sc_pma_controller_waitrequest;
+ end else if (r_decode[dec_csr] == 1'b1) begin
+ mgmt_readdata = sc_csr_readdata;
+ mgmt_waitrequest = sc_csr_waitrequest;
+ end else begin
+ mgmt_readdata = -1;
+ mgmt_waitrequest = 1'b0;
+ end
+ end
+
+ // internal interface to alt_pma_ch_control block
+ assign sc_pma_ch_controller_address = mgmt_address[5:0]; //6 bit address
+ assign sc_pma_ch_controller_read = mgmt_read & r_decode[dec_pma_ch_control];
+ assign sc_pma_ch_controller_write = mgmt_write & r_decode[dec_pma_ch_control];
+
+ // internal interface to pma_control block
+ assign sc_pma_controller_address = mgmt_address[1:0]; // 2 bit address
+ assign sc_pma_controller_read = mgmt_read & r_decode[dec_pma_control];
+ assign sc_pma_controller_write = mgmt_write & r_decode[dec_pma_control];
+
+ // internal interface to csr block
+ assign sc_csr_address = mgmt_address[4:0]; // 5 bit address
+ assign sc_csr_read = mgmt_read & r_decode[dec_csr];
+ assign sc_csr_write = mgmt_write & r_decode[dec_csr];
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_analog.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_analog.sv
new file mode 100644
index 0000000000000000000000000000000000000000..c11f7aa371601873a1d6fc77d0c67623f66bff56
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_analog.sv
@@ -0,0 +1,146 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_analog #(
+ parameter device_family = "Stratix V"
+)
+(
+
+input wire reconfig_clk, // this will be the reconfig clk
+input wire reset,
+
+//avalon MM slave
+input wire [2:0] analog_reconfig_address, // MM address
+input wire [31:0] analog_reconfig_writedata,
+input wire analog_reconfig_write,
+input wire analog_reconfig_read,
+
+//output MM slave
+output wire [31:0] analog_reconfig_readdata, // from MM
+output wire analog_reconfig_waitrequest,
+//output wire analog_reconfig_error,
+output wire analog_reconfig_done,
+
+// input from base_reconfig
+input wire analog_reconfig_irq_from_base,
+input wire analog_reconfig_waitrequest_from_base,
+
+
+// output to base_reconfig
+// Avalon MM Master
+output wire [2:0] analog_reconfig_address_base, // 3 bit MM
+output wire [31:0] analog_reconfig_writedata_base,
+output wire analog_reconfig_write_base, // start write to GXB
+output wire analog_reconfig_read_base, // start read from GXB
+
+// input from base reconfig
+input wire [31:0] analog_reconfig_readdata_base, // data from read command
+ output wire arb_req,
+ input wire arb_grant
+);
+
+//parameter device_family = "StratixIV"; // or ArriaII
+
+
+generate
+ //Deepak - added namespace support for CIVGX and AII GX
+ if((device_family == "Stratix IV") || (device_family == "Arria II") || (device_family == "Cyclone IV GX") || (device_family == "Arria II GX") || (device_family == "Arria II GZ") || (device_family == "HardCopy IV"))
+ begin
+ wire [4:0] w_tgx_analog_reconfig_address_base;
+ alt_xcvr_reconfig_analog_tgx reconfig_analog_tgx(
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .analog_reconfig_address(analog_reconfig_address),
+ .analog_reconfig_writedata(analog_reconfig_writedata),
+ .analog_reconfig_write(analog_reconfig_write),
+ .analog_reconfig_read(analog_reconfig_read),
+ .analog_reconfig_readdata(analog_reconfig_readdata),
+ .analog_reconfig_waitrequest(analog_reconfig_waitrequest),
+ .analog_reconfig_done(analog_reconfig_done),
+ .analog_reconfig_irq_from_base(analog_reconfig_irq_from_base),
+ .analog_reconfig_waitrequest_from_base(analog_reconfig_waitrequest_from_base),
+ .analog_reconfig_address_base(analog_reconfig_address_base),
+ .analog_reconfig_writedata_base(analog_reconfig_writedata_base),
+ .analog_reconfig_write_base(analog_reconfig_write_base),
+ .analog_reconfig_read_base(analog_reconfig_read_base),
+ .analog_reconfig_readdata_base(analog_reconfig_readdata_base)
+ );
+ assign analog_reconfig_address_base = w_tgx_analog_reconfig_address_base[4:2];
+ assign arb_req = 1'b0 & arb_grant; // not currently used in S4 architecture
+ end
+ else if(device_family == "Stratix V")
+ begin
+ alt_xcvr_reconfig_analog_sv reconfig_analog_sv(
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .analog_reconfig_address(analog_reconfig_address),
+ .analog_reconfig_writedata(analog_reconfig_writedata),
+ .analog_reconfig_write(analog_reconfig_write),
+ .analog_reconfig_read(analog_reconfig_read),
+ .analog_reconfig_readdata(analog_reconfig_readdata),
+ .analog_reconfig_waitrequest(analog_reconfig_waitrequest),
+ .analog_reconfig_done(analog_reconfig_done),
+ .analog_reconfig_irq_from_base(analog_reconfig_irq_from_base),
+ .analog_reconfig_waitrequest_from_base(analog_reconfig_waitrequest_from_base),
+ .analog_reconfig_address_base(analog_reconfig_address_base),
+ .analog_reconfig_writedata_base(analog_reconfig_writedata_base),
+ .analog_reconfig_write_base(analog_reconfig_write_base),
+ .analog_reconfig_read_base(analog_reconfig_read_base),
+ .analog_reconfig_readdata_base(analog_reconfig_readdata_base),
+ .arb_req(arb_req),
+ .arb_grant(arb_grant)
+
+ );
+ end
+ else if(device_family == "Arria V")
+ begin
+ alt_xcvr_reconfig_analog_av reconfig_analog_av(
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .analog_reconfig_address(analog_reconfig_address),
+ .analog_reconfig_writedata(analog_reconfig_writedata),
+ .analog_reconfig_write(analog_reconfig_write),
+ .analog_reconfig_read(analog_reconfig_read),
+ .analog_reconfig_readdata(analog_reconfig_readdata),
+ .analog_reconfig_waitrequest(analog_reconfig_waitrequest),
+ .analog_reconfig_done(analog_reconfig_done),
+ .analog_reconfig_irq_from_base(analog_reconfig_irq_from_base),
+ .analog_reconfig_waitrequest_from_base(analog_reconfig_waitrequest_from_base),
+ .analog_reconfig_address_base(analog_reconfig_address_base),
+ .analog_reconfig_writedata_base(analog_reconfig_writedata_base),
+ .analog_reconfig_write_base(analog_reconfig_write_base),
+ .analog_reconfig_read_base(analog_reconfig_read_base),
+ .analog_reconfig_readdata_base(analog_reconfig_readdata_base),
+ .arb_req(arb_req),
+ .arb_grant(arb_grant)
+
+ );
+ end
+ else
+ begin
+ assign analog_reconfig_readdata = 32'd0;
+ assign analog_reconfig_waitrequest = 1'd0;
+ assign analog_reconfig_done = 1'd1;
+ assign analog_reconfig_address_base = 3'd0;
+ assign analog_reconfig_writedata_base = 32'd0;
+ assign analog_reconfig_write_base = 1'd0;
+ assign analog_reconfig_read_base = 1'd0;
+ assign arb_req = 1'd0;
+ end
+
+endgenerate
+
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_analog_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_analog_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..b124cab8495ba45a26198a9b5ab25318441e6f01
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_analog_tgx.v
@@ -0,0 +1,763 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_analog_tgx (
+
+input wire reconfig_clk, // this will be the reconfig clk
+input wire reset,
+
+//avalon MM slave
+input wire [2:0] analog_reconfig_address, // MM address
+input wire [31:0] analog_reconfig_writedata,
+input wire analog_reconfig_write,
+input wire analog_reconfig_read,
+
+//output MM slave
+output reg [31:0] analog_reconfig_readdata, // from MM
+output wire analog_reconfig_waitrequest,
+//output wire analog_reconfig_error,
+output reg analog_reconfig_done,
+
+// input from base_reconfig
+ input wire analog_reconfig_irq_from_base,
+ input wire analog_reconfig_waitrequest_from_base,
+
+
+// output to base_reconfig
+// Avalon MM Master
+output wire [4:0] analog_reconfig_address_base, // 3 bit MM
+output wire [31:0] analog_reconfig_writedata_base,
+output wire analog_reconfig_write_base, // start write to GXB
+output wire analog_reconfig_read_base, // start read from GXB
+
+// input from base reconfig
+input wire [31:0] analog_reconfig_readdata_base // data from read command
+);
+
+parameter device_family = "Stratix IV"; // or ArriaII
+
+// new memory map -- register indirection
+//----------------------------------------------
+// address data[15:0]
+// 0 wr/rd logical_channel_address
+// 1 rd physical_chnl
+// 2 wr/rd control (write, read) / status (error, datavalid, busy)
+// 3 wr/rd addr_offset
+// 4 wr/rd data
+//
+// addr_offset ( upto 16 bits)
+// 0-15 TX parameters : vod, preemph_0t, preemph_1t, preemph_2t
+// 16-31 RX parameters : dcgain, eqctrl
+
+//local parameters
+localparam ADDR_WIDTH = 3;
+
+localparam IDLE = 4'b0000;
+localparam READ_FROM_GXB = 4'b0001;
+localparam WRITE_TO_GXB = 4'b0010;
+localparam SET_INFO_ON_BASIC = 4'b0011;
+localparam WRITE_DONE = 4'b0100;
+localparam READ_FROM_BASIC = 4'b0101;
+localparam READ_FROM_BASIC_DONE = 4'b0110;
+localparam READ_IDLE = 4'b0111;
+localparam GET_MUTEX = 4'b1000;
+localparam WRITE_CHL_ADDR = 4'b1001;
+localparam READ_OR_SET_INFO = 4'b1010;
+
+localparam ILLEGAL_PHYSICAL_CHNL = 12'b111111111111;
+
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [3:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+//reg [3:0] prev_state;
+genvar i;
+integer j;
+wire [(2**ADDR_WIDTH)-1:0] address_decode;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [4:0] master_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_read;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [31:0] master_writedata;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] chnl_addr_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [11:0] phys_chnl_addr_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg logical_chnl_addr_updated;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] status_reg;
+reg [1:0] control_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] data_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg needs_second_access;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [4:0] addr_offset;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg needs_second_write_access;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg do_read_before_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg set_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg have_mutex;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg req_and_use_mutex;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg do_read_phys_chnl;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg do_write_chnl_addr;
+
+wire mutex_grant;
+wire mutex_acq_waitrequest;
+wire [31:0] mutex_acq_readdata;
+wire accessing_rxeqctrl;
+wire accessing_rxdcgain;
+wire accessing_vod;
+wire accessing_preemph1t;
+wire accessing_preemph0t;
+wire accessing_preemph2t;
+
+// Implement waitrequest to match previous implementation
+altera_wait_generate wait_gen(
+ .rst(reset),
+ .clk(reconfig_clk),
+ .launch_signal(analog_reconfig_read),
+ .wait_req(analog_reconfig_waitrequest)
+);
+
+// synopsys translate_off
+initial begin
+ state <= 3'b000;
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ master_writedata <= 16'b0;
+ master_addr <= 5'b0;
+ status_reg <= 2'b0;
+ control_reg <= 2'b0;
+ data_reg <= 16'b0;
+ needs_second_access <= 1'b0;
+ do_read_before_write <= 1'b0;
+ addr_offset <= 5'b0;
+ set_addr <= 1'b0;
+ needs_second_write_access <= 1'b0;
+ have_mutex <= 0;
+ req_and_use_mutex <= 0;
+ do_read_phys_chnl <= 0;
+ do_write_chnl_addr <= 0;
+ logical_chnl_addr_updated <= 0;
+end
+// synopsys translate_on
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset)
+ begin
+ state <= IDLE;
+ analog_reconfig_readdata[31:0] <= 32'b0;
+ analog_reconfig_done <= 1'b0;
+ status_reg <= 2'b0;
+ control_reg <= 2'b0;
+ needs_second_access <= 1'b0;
+ needs_second_write_access <= 1'b0;
+ set_addr <= 1'b0;
+ do_read_before_write <= 1'b0;
+ data_reg <= 16'b0;
+ have_mutex <= 0;
+ req_and_use_mutex <= 0;
+ do_read_phys_chnl <= 0;
+ do_write_chnl_addr <= 0;
+ logical_chnl_addr_updated <= 0;
+ end
+ else begin
+ have_mutex <= mutex_grant;
+ if (analog_reconfig_read == 1'b1) // allow status read during GX read
+ begin
+ if (analog_reconfig_address == 3'b000) // logical channel address
+ analog_reconfig_readdata <= {{16{1'b0}}, chnl_addr_reg};
+ else if (analog_reconfig_address == 3'b001) // physical channel address
+ analog_reconfig_readdata <= {{20{1'b0}}, phys_chnl_addr_reg};
+ else if (analog_reconfig_address == 3'b010) // status
+ analog_reconfig_readdata <= {{22{1'b0}}, status_reg[1:0], {8{1'b0}}};
+ else if (analog_reconfig_address == 3'b011) // TX/RX offset
+ analog_reconfig_readdata <= {{16{1'b0}}, addr_offset};
+ else if (analog_reconfig_address == 3'b100) // previously read data
+ analog_reconfig_readdata <= {{16{1'b0}}, data_reg};
+ else
+ analog_reconfig_readdata <= {32{1'b0}};
+ end
+ case (state)
+ IDLE: begin
+ needs_second_access <= 1'b0;
+ if (analog_reconfig_address == 3'b0)
+ begin
+ if (analog_reconfig_write == 1'b1)
+ begin
+ chnl_addr_reg <= {{4{1'b0}},analog_reconfig_writedata[11:0]}; // write logical_ch_addr
+ logical_chnl_addr_updated <= 1'b1;
+ end
+ end
+ else if (analog_reconfig_write == 1'b1 && analog_reconfig_address == 3'b011) // addr_offset
+ begin
+ addr_offset <= analog_reconfig_writedata[4:0];
+ end
+ else if (analog_reconfig_address == 3'b100) // DPRIO write data
+ begin
+ if (analog_reconfig_write == 1'b1)
+ data_reg[15:0] <= analog_reconfig_writedata[15:0];
+ end
+ else if (analog_reconfig_read == 1'b1 && analog_reconfig_address == 3'b001) // physical chnl
+ begin
+ if (logical_chnl_addr_updated == 1'b1) // if logical chnl addr was updated from the last time we read the phys addr, go do the read again
+ begin
+ status_reg <= {1'b0, 1'b1}; //set busy bit
+ if (have_mutex)
+ begin
+ state <= WRITE_CHL_ADDR;
+ do_read_phys_chnl <= 1;
+ end
+ else begin
+ state <= READ_IDLE;
+ req_and_use_mutex <= 1'b1;
+ do_write_chnl_addr <= 1'b1;
+ do_read_phys_chnl <= 1;
+ end
+ logical_chnl_addr_updated <= 1'b0;
+ end
+ end
+ else if (analog_reconfig_address == 3'b010 && analog_reconfig_write == 1'b1) // control reg bit 1 rd, bit 0 wr
+ begin
+ status_reg <= {1'b0, 1'b1}; // set busy bit
+ control_reg <= analog_reconfig_writedata[1:0];
+ if (analog_reconfig_writedata[0] == 1'b1)
+ do_read_before_write <= 1'b1;
+ if (have_mutex)
+ begin
+ state <= WRITE_CHL_ADDR;
+ end
+ else begin
+ state <= READ_IDLE;
+ req_and_use_mutex <= 1'b1;
+ do_write_chnl_addr <= 1'b1;
+ status_reg <= {1'b0, 1'b1}; // set busy bit
+ end
+ end
+ else if (analog_reconfig_address > 3'b100 && analog_reconfig_write == 1'b1) //
+ begin
+ // synopsys translate_off
+ $display ("Illegal operation to reserved address %h", analog_reconfig_address);
+ $display ("Time: %0t Instance: %m", $time);
+ // synopsys translate_on
+ end
+ else if (have_mutex == 1'b1)
+ begin
+ // holding the mutex in idle state, release it
+ req_and_use_mutex <= 1'b0;
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ end
+ end
+ WRITE_CHL_ADDR: begin
+ master_addr <= 5'b00100;
+ master_write <= 1'b1;
+ master_writedata <= chnl_addr_reg;
+ state <= READ_OR_SET_INFO;
+ end
+ READ_OR_SET_INFO: begin
+ if (analog_reconfig_waitrequest_from_base == 1'b1)
+ state <= READ_OR_SET_INFO;
+ else
+ begin
+ master_write <= 1'b0;
+ if (do_read_phys_chnl)
+ begin
+ state <= READ_FROM_BASIC;
+ // do_read_phys_chnl = 0;
+ end
+ else begin
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ master_read <= 0;
+ end
+ end
+ end
+ GET_MUTEX:
+ begin
+ if (have_mutex == 1'b1)
+ begin
+ if (do_write_chnl_addr == 1'b1)
+ state <= WRITE_CHL_ADDR;
+ else
+ state <= READ_OR_SET_INFO;
+ end
+ else
+ begin
+ state <= GET_MUTEX;
+ end
+ end
+ READ_FROM_BASIC: begin
+ if (analog_reconfig_waitrequest == 1'b0)
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ if (analog_reconfig_irq_from_base == 1'b1) // start read access to data reg. of base_reconfig
+ begin
+ master_addr <= 5'b10100;
+ end
+ else begin
+ master_addr <= 5'b01000;
+ end
+ state <= READ_IDLE;
+ end
+ else
+ begin
+ state <= READ_FROM_BASIC;
+ end
+ end
+ READ_IDLE: begin
+ if (analog_reconfig_waitrequest == 1'b0)
+ begin
+ if (have_mutex)
+ state <= READ_FROM_BASIC_DONE;
+ else
+ begin
+ state <= GET_MUTEX;
+ end
+ end
+ else
+ begin
+ state <= READ_IDLE;
+ end
+ end
+ READ_FROM_BASIC_DONE: begin
+ if (analog_reconfig_waitrequest == 1'b0)
+ begin
+ master_read <= 1'b0;
+ if (do_read_phys_chnl)
+ begin
+ do_read_phys_chnl <= 0;
+ phys_chnl_addr_reg <= mutex_acq_readdata[11:0];
+ if (mutex_acq_readdata[11:0] == ILLEGAL_PHYSICAL_CHNL)
+ begin
+ //set error bit
+ status_reg <= {1'b1, 1'b0};
+ // error message for sim
+ //$display();
+ //$display();
+ end
+ else begin
+ // unset busy bit
+ status_reg <= 2'b0;
+ end
+ state <= IDLE;
+ end
+ else if (accessing_vod)
+ begin
+
+ // This is for Stratix IV only
+ //////////////////////////////////////////////////
+ //Port | DPRIO CRAM bit value
+ //2..0 | 2..0
+ //////////////////////////////////////////////////
+ //000 | 000
+ //001 | 001
+ //010 | 010
+ //011 | 110
+ //100 | 011
+ //101 | 111
+ //110 | 100
+ //111 | 101
+ /////////////////////////////////////////////////
+ if (control_reg[0] == 1'b1) // this was a write cycle to begin with
+ begin
+ master_writedata[31:16] <= {16{1'b0}};
+ master_writedata[15:13] <= {(data_reg[2] & data_reg[1]) | (data_reg[2] & data_reg[0]) | (data_reg[1] & data_reg[0]), data_reg[2] ^ data_reg[1], (~data_reg[1] & data_reg[0]) | (data_reg[2] & data_reg[0]) | (data_reg[2] & ~data_reg[1])};
+ master_writedata[12:0] <= mutex_acq_readdata[12:0];
+ master_addr <= 5'b10100;
+ master_write <= 1'b1;
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ end
+ else begin
+ data_reg <= {{13{1'b0}}, (mutex_acq_readdata[15] & ~mutex_acq_readdata[14]) | (mutex_acq_readdata[14] & mutex_acq_readdata[13]), (mutex_acq_readdata[15] & ~mutex_acq_readdata[14]) | (mutex_acq_readdata[14] & ~mutex_acq_readdata[13]), (~mutex_acq_readdata[14] & mutex_acq_readdata[13]) | (mutex_acq_readdata[15] & mutex_acq_readdata[14])};
+ // unset busy bit
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ else if (accessing_rxdcgain)
+ begin
+ // This is for Stratix IV only
+ //////////////////////////////////////////////////
+ //Port | DRIO CRAM bit value
+ //2..0 | 10..7
+ //////////////////////////////////////////////////
+ //000 | 0000
+ //001 | 0001
+ //010 | 0011
+ //011 | 0111
+ //100 | 1111
+ //Others | Assume to be 1's
+ /////////////////////////////////////////////////
+
+ // This is for Arria II only
+ //////////////////////////////////////////////////
+ //Port | DRIO CRAM bit value
+ //1..0 | 10..7
+ //////////////////////////////////////////////////
+ //00 | 0000
+ //01 | 0001
+ //10 | 0011
+ //Others | Assume to be 1's
+ /////////////////////////////////////////////////
+ if (control_reg[0] == 1'b1)
+ begin
+ if ((device_family == "Stratix IV") || (device_family == "HardCopy IV"))
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:11], data_reg[2], data_reg[1] & data_reg[0] | data_reg[2], data_reg[2] | data_reg[1], data_reg[2] | data_reg[1] | data_reg[0], mutex_acq_readdata[6:0]};
+ else
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:11], 1'b0, 1'b0, data_reg[1], data_reg[1] | data_reg[0], mutex_acq_readdata[6:0]};
+ master_addr <= 5'b10100;
+ master_write <= 1'b1;
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ end
+ else begin
+ if ((device_family == "Stratix IV") || (device_family == "HardCopy IV"))
+ data_reg <= {{13{1'b0}}, mutex_acq_readdata[10], ~mutex_acq_readdata[10] & mutex_acq_readdata[8], mutex_acq_readdata[10] ^ mutex_acq_readdata[9] ^ mutex_acq_readdata[8] ^ mutex_acq_readdata[7]};
+ else
+ data_reg <= {{14{1'b0}}, mutex_acq_readdata[8], mutex_acq_readdata[7] ^ mutex_acq_readdata[8]};
+ // unset busy bit
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ else if (accessing_rxeqctrl) // encode/decode rx_eqctrl
+ begin
+ ////////////////////////////////////////
+ // Wiz A B C D V
+ // 3210 EDC BA9 876 543 210
+ // 0000 000 000 000 000 000
+ // L0 0001 011 000 000 000 111
+ // L1 0010 100 000 000 000 000
+ // L2 0011 111 000 000 000 000
+ // L3 0100 111 000 000 000 111
+ // L4 0101 101 101 000 000 000
+ // M0 0110 111 111 000 000 000
+ // M1 0111 111 111 000 000 100
+ // M2 1000 111 111 000 000 111
+ // M3 1001 111 111 111 000 001
+ // M4 1010 111 111 111 000 100
+ // H0 1011 111 111 111 111 000
+ // H1 1100 111 111 111 111 001
+ // H2 1101 111 111 111 111 100
+ // H3 1110 111 111 111 111 110
+ // H4 1111 111 111 111 111 111
+ ////////////////////////////////////////
+ if (control_reg[0] == 1'b1)
+ begin
+ master_writedata[31:16] <= 0;
+ master_writedata[15] <= mutex_acq_readdata[15];
+ if (data_reg[3:0] > 4'b1010)
+ master_writedata[14:3] <= {12{1'b1}};
+ else if (data_reg[3:0] > 4'b0110)
+ master_writedata[14:3] <= {{3{1'b0}}, {9{1'b1}}};
+ else if (data_reg[3:0] > 4'b0011)
+ master_writedata[14:3] <= {{6{1'b0}}, {6{1'b1}}};
+ else if (data_reg[3:0] > 4'b0)
+ master_writedata[14:3] <= {{9{1'b0}}, {3{1'b1}}};
+ else
+ master_writedata[14:3] <= {12{1'b0}};
+ master_writedata[2] <= (data_reg[1] & ~data_reg[0]) | (~data_reg[3] & ~data_reg[2] & data_reg[1]) | (data_reg[2] & ~data_reg[1] & data_reg[0] | (data_reg[3] & data_reg[2] & data_reg[0]) | (data_reg[3] & ~data_reg[2] & ~data_reg[1]));
+ master_writedata[1] <= ( data_reg[1] & (data_reg[0] ^ (data_reg[2] ^ data_reg[3]))) | (data_reg[3] & data_reg[2] & ~data_reg[1] & ~data_reg[0]);
+ master_writedata[0] <= (~(data_reg[3] ^ data_reg[2]) & data_reg[1] & data_reg[0]) | (data_reg[2] & data_reg[1] & ~data_reg[0]) | (data_reg[3] & data_reg[1] & ~data_reg[0]) | (data_reg[3] & data_reg[2] & ~data_reg[0]) | (data_reg[3] & ~data_reg[2] & ~data_reg[1] & data_reg[0]);
+
+ master_addr <= 5'b10100;
+ master_write <= 1'b1;
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ end
+ else begin
+ if (mutex_acq_readdata[14:12] == 3'b111) // > 10
+ data_reg <= {{12{1'b0}}, 1'b1, (mutex_acq_readdata[1] & mutex_acq_readdata[0]) | (mutex_acq_readdata[2] & ~mutex_acq_readdata[1]), (mutex_acq_readdata[2] & mutex_acq_readdata[0]) | (~mutex_acq_readdata[0] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[2]), (~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]) | (mutex_acq_readdata[2] & mutex_acq_readdata[1] & mutex_acq_readdata[0])};
+ else if (mutex_acq_readdata[11:9] == 3'b111) // > 6 only
+ data_reg <= {{12{1'b0}}, mutex_acq_readdata[2], ~mutex_acq_readdata[2], (mutex_acq_readdata[2] & mutex_acq_readdata[1] & mutex_acq_readdata[0]) | (~mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]), (~mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]) | (mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & mutex_acq_readdata[0])};
+ else if (mutex_acq_readdata[8:6] == 3'b111) // > 3 only
+ data_reg <= {{12{1'b0}}, 1'b0, 1'b1, mutex_acq_readdata[2] & mutex_acq_readdata[1] & mutex_acq_readdata[0], mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]};
+ else if (mutex_acq_readdata[5:3] == 3'b111) // > 0 only
+ data_reg <= {{12{1'b0}}, {2{1'b0}}, (mutex_acq_readdata[2] & mutex_acq_readdata[1] & mutex_acq_readdata[0]) | (mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]), (mutex_acq_readdata[2] & mutex_acq_readdata[1] & mutex_acq_readdata[0]) | (~mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]) };
+ else
+ data_reg <= {16{1'b0}};
+
+ // unset busy bit
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ else if (accessing_preemph1t)
+ begin
+ // This is for Arria II only
+ //////////////////////////////////////////////////
+ //Port | DRIO CRAM bit value
+ //4..0 | 15..11
+ //////////////////////////////////////////////////
+ //00000 | 00000
+ //00001 | 00001
+ //00010 | 00101
+ //00011 | 01001
+ //00100 | 01101
+ //00101 | 10001
+ //00110 | 10101
+ //Others | Assume to be 1's
+ /////////////////////////////////////////////////
+ if (control_reg[0] == 1'b1)
+ begin
+ if (device_family == "Stratix IV")
+ master_writedata <= {{16{1'b0}}, data_reg[4:0], mutex_acq_readdata[10:0]};
+ else
+ master_writedata <= {{16{1'b0}}, data_reg[2] & data_reg[1] ^ data_reg[0], data_reg[2] & ~data_reg[1] & ~data_reg[0] | (data_reg[1] & data_reg[0]), (data_reg[2] | data_reg[1]) & ~data_reg[0], 1'b0, (data_reg[2] | data_reg[1] | data_reg[0]), mutex_acq_readdata[10:0]};
+ master_addr <= 5'b10100;
+ master_write <= 1'b1;
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ end
+ else begin
+ if (device_family == "Stratix IV")
+ data_reg <= {{11{1'b0}}, mutex_acq_readdata[15:11]};
+ else
+ data_reg <= {{11{1'b0}}, 1'b0, 1'b0, mutex_acq_readdata[15] | (mutex_acq_readdata[14] & mutex_acq_readdata[13]), mutex_acq_readdata[14] ^ mutex_acq_readdata[13], mutex_acq_readdata[13] ^ mutex_acq_readdata[11]};
+ // unset busy bit
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ else if (accessing_preemph0t || accessing_preemph2t)
+ begin
+ if (control_reg[0] == 1'b1)
+ begin
+ if (accessing_preemph0t)
+ begin
+ if (needs_second_write_access)
+ begin
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:5], ~data_reg[4], mutex_acq_readdata[3:0]};
+ end
+ else begin
+ if (data_reg[4] == 1'b0)
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:4], 4'b0000 - data_reg[3:0]};
+ else
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:4], data_reg[3:0]};
+ end
+ end
+ else if (accessing_preemph2t)
+ begin
+ if (needs_second_write_access)
+ begin
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:4], ~data_reg[4], mutex_acq_readdata[2:0]};
+ end
+ else begin
+ if (data_reg[4] == 1'b0)
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:8], 4'b0000 - data_reg[3:0], mutex_acq_readdata[3:0]};
+ else
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:8], data_reg[3:0], mutex_acq_readdata[3:0]};
+ end
+ end
+ master_addr <= 5'b10100;
+ master_write <= 1'b1;
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ end
+ else begin
+ if (needs_second_access)
+ begin
+ data_reg <= mutex_acq_readdata[15:0];
+ master_write <= 1'b1; // start access for INV bit
+ master_addr <= 5'b10000;
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {8{1'b0}}, 2'b11}; // DPRIO register address
+ state <= SET_INFO_ON_BASIC;
+ needs_second_access <= 1'b0;
+ end
+ else begin
+ if (accessing_preemph0t)
+ begin
+ if (mutex_acq_readdata[4] == 1'b1)
+ data_reg <= {{11{1'b0}}, 1'b0, 4'b0000 - data_reg[3:0]};
+ else
+ data_reg <= {{11{1'b0}}, 1'b1, data_reg[3:0]};
+ end
+ else begin
+ if (mutex_acq_readdata[3] == 1'b1)
+ data_reg <= {{11{1'b0}}, 1'b0, 4'b0000 - data_reg[7:4]};
+ else
+ data_reg <= {{11{1'b0}}, 1'b1, data_reg[7:4]};
+ end
+ // unset busy
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ end
+ else begin // dont know what the operation is
+ analog_reconfig_readdata <= mutex_acq_readdata;
+ // unset busy bit
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ else
+ begin
+ state <= READ_FROM_BASIC_DONE;
+ end
+ end
+ SET_INFO_ON_BASIC: begin
+ if (set_addr)
+ begin
+ master_addr <= 5'b10000;
+ master_write <= 1'b1;
+ if (accessing_vod)
+ begin
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {10{1'b0}}};
+ end
+ else if (accessing_preemph1t)
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {8{1'b0}}, 2'b01};
+ else if (accessing_rxdcgain)
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b11, 10'b0};
+ else if (accessing_rxeqctrl)
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b11, 10'b0000001011};
+ else if (accessing_preemph0t || accessing_preemph2t)
+ begin
+ if (needs_second_write_access)
+ begin
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {8{1'b0}}, 2'b11};
+ end
+ else
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {8{1'b0}}, 2'b10};
+ if (control_reg[1] == 1'b1) // pure read cycle
+ needs_second_access <= 1'b1;
+ end
+ set_addr <= 1'b0;
+ end
+ else if (control_reg[1] == 1'b1 || (control_reg[0] == 1'b1 & do_read_before_write)) // read
+ begin
+ master_addr <= 5'b01100;
+ master_write <= 1'b1;
+ master_writedata <= {{16{1'b0}}, {14{1'b0}}, 2'b10}; // initiate read first
+ state <= READ_FROM_GXB;
+ do_read_before_write <= 1'b0;
+ end
+ else if (control_reg[0] == 1'b1) // actual write
+ begin
+ master_write <= 1'b1;
+ master_addr <= 5'b01100;
+ master_writedata <= {{16{1'b0}}, {14{1'b0}}, 2'b01}; // issue write to basic's control_reg to start WRITE
+ state <= WRITE_TO_GXB;
+ end
+ end
+ READ_FROM_GXB: begin
+ master_write <= 1'b0;
+ if (analog_reconfig_irq_from_base == 1'b1)
+ state <= READ_FROM_BASIC;
+ end
+ WRITE_TO_GXB: begin
+ master_write <= 1'b0;
+ if (analog_reconfig_irq_from_base == 1'b1)
+ begin
+ //start access to clear interrupt control reg. on slave
+ master_addr <= 5'b01100;
+ master_write <= 1'b1;
+ master_writedata <= {{16{1'b0}}, {13{1'b0}}, 3'b000};
+ state <= WRITE_DONE;
+ end
+ end
+ WRITE_DONE: begin
+ master_write <= 1'b0;
+ if (analog_reconfig_irq_from_base == 1'b1)
+ begin
+ if ((accessing_preemph0t || accessing_preemph2t) & (!needs_second_write_access))
+ begin
+ needs_second_write_access <= 1'b1;
+ do_read_before_write <= 1'b1;
+ master_write <= 1'b1;
+ master_addr <= 5'b10000;
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {8{1'b0}}, 2'b11}; // DPRIO register address for INV
+ state <= SET_INFO_ON_BASIC;
+ end
+ else begin
+ needs_second_write_access <= 1'b0;
+ status_reg <= {1'b0, 1'b0}; // unset busy
+ analog_reconfig_done <= 1'b1; // send INTERRUPT
+ state <= IDLE;
+ end
+ end
+ end
+ default:begin
+ state <= IDLE;
+ end
+ endcase
+ end
+// prev_state <= state;
+end
+
+assign accessing_vod = (addr_offset[4:0] == 5'b0);
+assign accessing_preemph0t = (addr_offset[4:0] == 5'b00001);
+assign accessing_preemph1t = (addr_offset[4:0] == 5'b00010);
+assign accessing_preemph2t = (addr_offset[4:0] == 5'b00011);
+assign accessing_rxdcgain = (addr_offset[4] == 1'b1 && addr_offset[3:0] == 4'b0000);
+assign accessing_rxeqctrl = (addr_offset[4] == 1'b1 && addr_offset[3:0] == 4'b0001);
+
+//assign analog_reconfig_address_base = master_addr;
+//assign analog_reconfig_write_base = master_write;
+//assign analog_reconfig_read_base = master_read;
+//assign analog_reconfig_writedata_base = master_writedata;
+
+
+ alt_mutex_acq #(
+ .mutex_wait_time(101),
+ .addr_width(5),
+ .data_width(32)
+ )
+ mutex_inst (
+ .clk(reconfig_clk),
+ .reset(reset),
+ // inputs to the base that should be routed through the mutex
+ .address(master_addr),
+ .writedata(master_writedata),
+ .write(master_write),
+ .read(master_read),
+ // output from the mutex which is processed form of output from base
+ .waitrequest(mutex_acq_waitrequest),
+ .readdata(mutex_acq_readdata),
+
+
+ // outputs from mutex to be routed to the base
+ .master_address(analog_reconfig_address_base),
+ .master_writedata(analog_reconfig_writedata_base),
+ .master_write(analog_reconfig_write_base),
+ .master_read(analog_reconfig_read_base),
+
+ // these ports are from the base routed to the mutex
+ .master_waitrequest(analog_reconfig_waitrequest_from_base),
+ .master_readdata(analog_reconfig_readdata_base), // from MM
+
+ //request signal to the mutex should be kept high as long as the mutex is being used
+ .mutex_req(req_and_use_mutex),
+ // output from mutex indicates whether you have mutex or not
+ .mutex_grant(mutex_grant)
+ );
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_basic_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_basic_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..2c4f79b384db04a1ab6911dc33951886c61d0f08
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_basic_tgx.v
@@ -0,0 +1,367 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+(* ALTERA_ATTRIBUTE = {"{-to address_pres_reg[11]} DPRIO_CHANNEL_NUM=11;{-to address_pres_reg[10]} DPRIO_CHANNEL_NUM=10;{-to address_pres_reg[9]} DPRIO_CHANNEL_NUM=9;{-to address_pres_reg[8]} DPRIO_CHANNEL_NUM=8;{-to address_pres_reg[7]} DPRIO_CHANNEL_NUM=7;{-to address_pres_reg[6]} DPRIO_CHANNEL_NUM=6;{-to address_pres_reg[5]} DPRIO_CHANNEL_NUM=5;{-to address_pres_reg[4]} DPRIO_CHANNEL_NUM=4;{-to address_pres_reg[3]} DPRIO_CHANNEL_NUM=3;{-to address_pres_reg[2]} DPRIO_CHANNEL_NUM=2;{-to address_pres_reg[1]} DPRIO_CHANNEL_NUM=1;{-to address_pres_reg[0]} DPRIO_CHANNEL_NUM=0; disable_da_rule=\"S102,R102\""} *)
+module alt_xcvr_reconfig_basic_tgx
+#( parameter number_of_reconfig_interfaces = 1
+ )
+(
+ // avalon clock interface
+ input wire reconfig_clk,
+ input wire reset,
+
+ // avalon MM
+ input wire basic_reconfig_write,
+ input wire basic_reconfig_read,
+ input wire [31:0] basic_reconfig_writedata,
+ input wire [2:0] basic_reconfig_address, // address to MM described below
+
+ output reg [31:0] basic_reconfig_readdata, // reconfig_fromgxb_data
+ output wire basic_reconfig_waitrequest,
+
+ // avalon MM
+// output wire reconfig_write_base,
+// output wire reconfig_read_base,
+// output wire [31:0] reconfig_writedata_base,
+// output wire [4:0] reconfig_address_base, // address to MM described below
+
+// input wire [31:0] reconfig_readdata_base, // reconfig_fromgxb_data
+// input wire reconfig_waitrequest_from_base,
+
+
+ // avalon ST interface
+ input wire [number_of_reconfig_interfaces*17 - 1 : 0] basic_reconfig_fromgxb_data, // dprioout, testbus from altgx : (17+4 bits/quad)
+ input wire [number_of_reconfig_interfaces*8 - 1 : 0] aeq_fromgxb_data, // for ADCE dprio
+ output wire [3:0] basic_reconfig_togxb_data, // busy, dprioin, dprioload, dpriodisable and aeq to altgx
+ output reg [number_of_reconfig_interfaces*24 - 1 : 0] aeq_togxb_data, // for ADCE
+ output reg [number_of_reconfig_interfaces*16 - 1 : 0] testbus_data,
+
+ output reg basic_reconfig_irq // interrupt to Master
+);
+
+//assign reconfig_write_base = 1'b0;
+//assign reconfig_read_base = 1'b0;
+//assign reconfig_writedata_base = 32'd0;
+//assign reconfig_address_base = 5'd0;
+
+
+// Memeory Map for register indirection
+// addr wr/rd description
+// ------------------------------------------------------
+// 0 wr/rd mutex : bit[0]
+// 1 wr/rd logical_ch_addr (10 bits)
+// 2 rd physical_chnl_map
+// 3 rd/wr status/control -- bit 0 busy/bit 1 read, bit 0 write, bit 3 = absolute addressing
+// 4 wr/rd DPRIO addr_offset
+// 5 wr/rd DPRIO data
+// 6 rd/wr adce_standby, adce_capture, testbussel : bit 7 -- adcedone, bit 6 -- adcetestbus, bits 5,4 -- adce, 3 to 0 -- bussel
+// 7 rd/wr offset cancellation busy output to GX bit 0
+
+//local parameters
+localparam quad_address_width = 9;
+localparam IDLE_STATE = 2'b00;
+localparam WRITE_STATE = 2'b01;
+localparam READ_STATE = 2'b10;
+
+
+(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON"} *)
+reg [11:0] address_pres_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [11:0] logical_channel_addr_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [14:0] dprio_table_addr_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] pma_pcs_id_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg dprio_busy_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] data_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [5:0] testbussel;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] adce_testdata;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] control_reg;
+// mutex
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg mutex_value;
+//reg [15:0] mutex_owner;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [10:0] mutex_timeout_cntr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg offset_cancellation_busy;
+
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg basic_reconfig_absolute_addressing;
+
+
+wire [quad_address_width-1:0] quad_address;
+wire [quad_address_width-1:0] dprio_quad_address;
+
+wire busy_state;
+wire [15:0] dprio_address;
+wire dprio_busy;
+wire [15:0] dprio_datain;
+wire [15:0] dprio_dataout;
+wire dprio_dprioout;
+wire dprio_rden;
+wire dprio_pulse;
+wire rd_pulse;
+wire read_done;
+wire read_word_done;
+wire reset_system;
+wire dprio_wren;
+wire write_done;
+wire wr_pulse;
+wire read_data_valid;
+wire write_word_done;
+
+integer i,j;
+
+
+assign basic_reconfig_waitrequest = 1'b0;
+
+// synopsys translate_off
+initial
+begin
+ state = 2'b00;
+ basic_reconfig_irq = 1'b0;
+ logical_channel_addr_reg = 12'b0;
+ testbussel = 0;
+ control_reg = 0;
+ mutex_value = 0;
+ mutex_timeout_cntr = 0;
+ offset_cancellation_busy = 0;
+ data_reg = 16'h0000;
+ dprio_table_addr_reg = 15'h0000;
+ pma_pcs_id_reg = 2'b00;
+
+end
+// synopsys translate_on
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset === 1'b1)
+ adce_testdata <= 0;
+ else begin
+ for (i=0; i<=1; i=i+1)
+ begin
+ adce_testdata[i] <= aeq_fromgxb_data[(logical_channel_addr_reg) + i];
+ end
+ end
+end
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset === 1'b1)
+ begin
+ state <= IDLE_STATE;
+ basic_reconfig_readdata <= 16'b0;
+ basic_reconfig_irq <= 1'b0;
+ testbussel <= 0;
+ control_reg <= 0;
+ // mutex registers
+ mutex_value <= 0;
+ mutex_timeout_cntr <= 0;
+ end
+ else begin
+ // mutex
+ if (basic_reconfig_address == 3'b0)
+ begin
+ //read first only update the mutex_value
+ if (basic_reconfig_read == 1'b1)
+ begin
+ basic_reconfig_readdata <= {{31{1'b0}}, mutex_value};
+ // if (basic_reconfig_waitrequest == 1'b0)
+ if (mutex_value == 1'b0) // mutex is free, so grant access
+ mutex_value <= 1'b1;
+ end
+ else if (basic_reconfig_write == 1'b1)
+ begin
+ mutex_value <= 0;
+ end
+ end
+
+ case (state)
+ IDLE_STATE: begin
+ if (basic_reconfig_write == 1'b1)
+ begin
+ mutex_timeout_cntr <= 0; // reset the mutex_timeout counter
+ if (basic_reconfig_address == 3'b001)
+ begin
+ logical_channel_addr_reg <= basic_reconfig_writedata[11:0];
+ address_pres_reg <= {basic_reconfig_writedata[10:2], 1'b0, basic_reconfig_writedata[1:0]}; //chestan
+ end
+ else if (basic_reconfig_address == 3'b100)
+ begin
+ dprio_table_addr_reg <= basic_reconfig_writedata[14:0];
+ pma_pcs_id_reg <= basic_reconfig_writedata[11:10];
+ end
+ else if (basic_reconfig_address == 3'b011) // control reg
+ begin
+ if (basic_reconfig_writedata[0] == 1'b1) // write
+ begin
+ state <= WRITE_STATE;
+ control_reg <= 2'b01;
+ end
+ else if (basic_reconfig_writedata[1] == 1'b1) // read
+ begin
+ state <= READ_STATE;
+ control_reg <= 2'b10;
+ end
+ if (basic_reconfig_writedata[2] == 1'b0) begin
+ basic_reconfig_irq <= 1'b0; // clear WRITE interrupt
+ end
+ basic_reconfig_absolute_addressing <= basic_reconfig_writedata[3]; // use the full address from dprio_addr, not the derived address
+ end
+ else if (basic_reconfig_address == 3'b101) // data
+ begin
+ data_reg <= basic_reconfig_writedata[15:0];
+ end
+ else if (basic_reconfig_address == 3'b110) // testbussel
+ testbussel <= basic_reconfig_writedata[5:0];
+ else if (basic_reconfig_address == 3'b111)
+ offset_cancellation_busy <= basic_reconfig_writedata[0];
+ begin
+ end
+ end
+ else if (basic_reconfig_read == 1'b1)
+ begin
+ if (basic_reconfig_address == 3'b001)
+ basic_reconfig_readdata <= {{20{1'b0}}, logical_channel_addr_reg};
+ else if (basic_reconfig_address == 3'b010) // physical chnl
+ basic_reconfig_readdata <= {{21{1'b0}}, address_pres_reg[11:3], address_pres_reg[1:0]}; // check this
+ else if (basic_reconfig_address == 3'b011) // status
+ basic_reconfig_readdata <= {{23{1'b0}}, busy_state, {5{1'b0}}, basic_reconfig_irq, control_reg};
+ else if (basic_reconfig_address == 3'b100)
+ basic_reconfig_readdata <= {{20{1'b0}}, pma_pcs_id_reg, dprio_table_addr_reg};
+ else if (basic_reconfig_address == 3'b101) // DPRIO readdata
+ begin
+ basic_reconfig_readdata <= {{16{1'b0}}, data_reg};
+ basic_reconfig_irq <= 1'b0; // clear READ interrupt
+ end
+ else if (basic_reconfig_address == 3'b110)
+ basic_reconfig_readdata <= {{24{1'b0}}, adce_testdata, testbussel};
+ else if (basic_reconfig_address == 3'b111) // testbusdata
+ basic_reconfig_readdata <= {{31{1'b0}}, offset_cancellation_busy};
+ if (basic_reconfig_address != 3'b0) // if not reading the mutex val
+ mutex_timeout_cntr <= 0; // reset the mutex counter
+ end
+ else if (mutex_value == 1'b1) // if mutex was granted to someone
+ if (mutex_timeout_cntr == 10'd1000) // and they didnt do anything for 1000 cycles
+ begin
+ mutex_value <= 1'b0; // reset the mutex and give it to the next person
+ mutex_timeout_cntr <= 0;
+ end
+ else
+ mutex_timeout_cntr <= mutex_timeout_cntr[9:0] + 10'b1; // count up the timer from the last access
+ end
+ WRITE_STATE: begin
+ if (write_done)
+ begin
+ state <= IDLE_STATE;
+ basic_reconfig_irq <= 1'b1; // send interrupt to master
+ end
+ // allow status_register read here
+ if (basic_reconfig_read == 1'b1 && basic_reconfig_address == 3'b011)
+ basic_reconfig_readdata <= {{23{1'b0}}, busy_state, {5{1'b0}}, basic_reconfig_irq, control_reg};
+ end
+ READ_STATE: begin
+ if (read_word_done == 1'b1)
+ begin
+ data_reg <= dprio_dataout;
+ basic_reconfig_irq <= 1'b1; // send interrupt
+ state <= IDLE_STATE;
+ end
+ // allow status_register read here
+ if (basic_reconfig_read == 1'b1 && basic_reconfig_address == 3'b011)
+ basic_reconfig_readdata <= {{23{1'b0}}, busy_state, {5{1'b0}}, basic_reconfig_irq, control_reg};
+ end
+ default: begin
+ state <= IDLE_STATE;
+ end
+ endcase
+ end
+end
+
+// synopsys translate_off
+initial address_pres_reg = 0;
+// synopsys translate_on
+
+assign quad_address = logical_channel_addr_reg[10:2];
+assign dprio_address[15:0] = basic_reconfig_absolute_addressing ? {1'b0, dprio_table_addr_reg[14:0]} : {1'b0, address_pres_reg[2], address_pres_reg[1:0], pma_pcs_id_reg[1:0], dprio_table_addr_reg[9:0]};
+assign dprio_quad_address = address_pres_reg[11:3];
+assign dprio_dprioout = basic_reconfig_fromgxb_data[quad_address * 17];
+assign dprio_datain = data_reg;
+assign dprio_rden = rd_pulse;
+assign rd_pulse = (state == READ_STATE) & ~dprio_pulse & ~read_done;
+assign read_done = read_word_done | reset_system;
+assign read_word_done = (state == READ_STATE) & read_data_valid;
+assign read_data_valid = (state == READ_STATE) & dprio_pulse;
+assign dprio_wren = wr_pulse;
+assign wr_pulse = (state == WRITE_STATE) & ~dprio_pulse & ~write_done;
+assign write_done = write_word_done | reset_system;
+assign write_word_done = (state == WRITE_STATE) & dprio_pulse;
+assign reset_system = reset;
+assign busy_state = (state == READ_STATE) | (state == WRITE_STATE);
+
+// synopsys translate_off
+initial dprio_busy_reg = 0;
+// synopsys translate_on
+
+always @(posedge reconfig_clk) dprio_busy_reg <= dprio_busy;
+assign dprio_pulse = (dprio_busy_reg ^ dprio_busy) & (~dprio_busy);
+
+alt_dprio inst_alt_dprio (.dpclk(reconfig_clk),
+ .datain(dprio_datain),
+ .address(dprio_address),
+ .wren(dprio_wren),
+ .rden(dprio_rden),
+// .rdinc(),
+ .wren_data(1'b0),
+ .dprioout(dprio_dprioout), // reconfig_fromgxb_data[0]
+ .quad_address(dprio_quad_address),
+ // outputs
+ .dprioin(basic_reconfig_togxb_data[0]),
+ .dpriodisable(basic_reconfig_togxb_data[1]),
+ .dprioload(basic_reconfig_togxb_data[2]),
+ .dataout(dprio_dataout),
+ .busy(dprio_busy)
+ );
+
+//assign testbus_data = (testbussel == 3'b110) ? basic_reconfig_fromgxb_data : 'b0;
+
+assign basic_reconfig_togxb_data[3] = offset_cancellation_busy;
+
+always @(basic_reconfig_fromgxb_data)
+begin
+ for (i=0; i<number_of_reconfig_interfaces; i=i+1)
+ begin
+ for (j=0; j<= 15; j=j+1)
+ begin
+ testbus_data[(i*16) + j] = basic_reconfig_fromgxb_data[(i*17) + j+1];
+ end
+ end
+end
+
+always @(logical_channel_addr_reg or testbussel)
+begin
+ aeq_togxb_data = {number_of_reconfig_interfaces*24{1'b0}};
+ for (i=0; i<=5; i=i+1)
+ begin
+ aeq_togxb_data[(logical_channel_addr_reg*6) + i] = testbussel[i];
+ end
+end
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_dfe_tgx.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_dfe_tgx.sv
new file mode 100644
index 0000000000000000000000000000000000000000..107fa27aa9d4e7684eaf3ff65891450a40db21ac
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_dfe_tgx.sv
@@ -0,0 +1,502 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_dfe_tgx
+#(
+ parameter device_family = "StratixIV",
+ parameter number_of_reconfig_interfaces = 1
+)
+(
+ input wire reconfig_clk, // this will be the reconfig clk
+ input wire reset,
+
+ //avalon MM slave
+ input wire [2:0] dfe_address, // Check this! fix me!
+ input wire [31:0] dfe_writedata,
+ input wire dfe_write,
+ input wire dfe_read,
+
+ //output MM slave
+ output wire [31:0] dfe_readdata, // from MM
+ output wire dfe_waitrequest, // from MM
+
+ output reg dfe_irq,
+
+ // input from base_reconfig
+ input wire dfe_irq_from_base,
+ input wire dfe_waitrequest_from_base,
+
+ // output to base_reconfig
+ // Avalon MM Master
+ output wire [2:0] dfe_address_base, // 3 bit MM
+ output wire [31:0] dfe_writedata_base,
+ output wire dfe_write_base, // start write to GXB
+ output wire dfe_read_base, // start read from GXB
+
+ // input from base reconfig
+ input wire [31:0] dfe_readdata_base // data from read command
+
+);
+
+//local parameters
+//state
+localparam IDLE_STATE = 4'b0000;
+localparam LOGICAL_ADDRESS_STATE = 4'b0001;
+localparam WRITE_DATA_STATE = 4'b0010;
+localparam CONTROL_STATE = 4'b0011;
+localparam BUSY_STATE = 4'b0100;
+localparam READ_PHY_ADDR_STATE = 4'b0101;
+localparam CHECK_PHY_ADDR_STATE = 4'b0110;
+localparam ADDRESS_OFFSET_STATE = 4'b0111;
+localparam BASE_BUSY_STATE = 4'b1000;
+localparam READ_DATA_STATE = 4'b1001;
+localparam WRITE_DONE_STATE = 4'b1010;
+
+localparam ILLEGAL_PHYSICAL_CHNL = 10'b1111111111;
+wire [4:0] dfe_addr_all; // 5 bit MM
+
+wire mutex_grant;
+wire [31:0] master_read_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [3:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg write_read_control;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_read;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [31:0] master_write_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [2:0] master_address;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg req_and_use_mutex;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg set_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg wait_phy_addr_ready;
+
+wire [4:0] master_address_shifted;
+
+//alt_dfe instantiation
+wire alt_dfe_busy;
+wire [15:0] alt_dfe_dprio_dataout;
+wire alt_dfe_dprio_wren;
+wire alt_dfe_dprio_rden;
+wire [(number_of_reconfig_interfaces*4-1) : 0] alt_dfe_error;
+
+wire [15:0] alt_dfe_dprio_addr;
+wire [8:0] alt_dfe_quad_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [11:0] alt_dfe_remap_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_dfe_dprio_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_dfe_dprio_busy_int;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] alt_dfe_dprio_datain;
+
+function integer CLogB2;
+input integer Depth;
+integer i;
+begin
+i = Depth;
+for(CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1)
+i = i >> 1;
+end
+endfunction
+
+// synopsys translate_off
+initial begin
+ state = 3'b000;
+ alt_dfe_remap_addr = 12'h000;
+ req_and_use_mutex = 1'b0;
+ wait_phy_addr_ready = 1'b0;
+ alt_dfe_dprio_datain = 16'h0000;
+ alt_dfe_dprio_busy = 1'b0;
+ alt_dfe_dprio_busy_int = 1'b0;
+
+ master_write = 1'b0;
+ master_read = 1'b0;
+ master_write_data = {32{1'b0}};
+ master_address = 3'h0;
+
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy = 1'b0; // 1 for assert busy, 0 for deassert busy
+
+ dfe_irq = 1'b0;
+
+end
+// synopsys translate_on
+
+integer count;
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset)
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ master_write_data <= {32{1'b0}};
+ master_address <= 3'h0;
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ req_and_use_mutex <= 1'b0;
+ wait_phy_addr_ready <= 1'b0;
+ alt_dfe_dprio_busy_int<= 1'b0;
+ dfe_irq <= 1'b0;
+ end
+ else begin
+ if(alt_dfe_busy == 1'b0)
+ req_and_use_mutex <= 1'b0;
+ else
+ req_and_use_mutex <= 1'b1;
+
+ case (state)
+ IDLE_STATE:
+ begin
+ dfe_irq <= 1'b0; // reset write/read done flag
+ //reset the signal
+ set_busy <= 1'b0;
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ alt_dfe_remap_addr <= 12'h000;
+
+ //alt_dfe will not assert wren and rden at the same time
+ if((alt_dfe_dprio_wren == 1'b1) || (alt_dfe_dprio_rden == 1'b1))
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(alt_dfe_dprio_wren == 1'b1)
+ write_read_control <= 1'b1; // 1 for write
+ else
+ write_read_control <= 1'b0; // 0 for read
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ else
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ state <= IDLE_STATE;
+ end
+ end
+ LOGICAL_ADDRESS_STATE: //sending channel and quad address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h1;
+ master_write_data <= {{21{1'b0}}, alt_dfe_quad_addr, alt_dfe_dprio_addr[13:12]};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= READ_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ end
+ READ_PHY_ADDR_STATE: //read phsical address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h2;
+ master_read <= 1'b1;
+ master_write <= 1'b0;
+ if (wait_phy_addr_ready == 1'b1)
+ begin
+ wait_phy_addr_ready <= 1'b0;
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ wait_phy_addr_ready <= 1'b1;
+ state <= READ_PHY_ADDR_STATE;
+ //state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_PHY_ADDR_STATE;
+ end
+ end
+ CHECK_PHY_ADDR_STATE: //check physical address correct or not
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ if (master_read_data[9:0] == ILLEGAL_PHYSICAL_CHNL)
+ begin
+ // synopsys translate_off
+ $display ("Illegal physical address: 10'h%h", master_read_data);
+ $display ("Time: %0t Instance: %m", $time);
+ // synopsys translate_on
+ alt_dfe_remap_addr <= 12'hfff;
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ alt_dfe_remap_addr <= master_read_data[11:0];
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ else
+ begin
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ ADDRESS_OFFSET_STATE: // send address offset to alt_dprio
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h4;
+ master_write_data <= {{20{1'b0}}, alt_dfe_dprio_addr[11:0]};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(write_read_control == 1'b1)
+ state <= WRITE_DATA_STATE;
+ else
+ state <= CONTROL_STATE;
+ end
+ else
+ begin
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ WRITE_DATA_STATE:
+ begin
+ master_address <= 3'h5;
+ master_write_data = {{16{1'b0}}, alt_dfe_dprio_dataout};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= CONTROL_STATE;
+ end
+ CONTROL_STATE: // sending write/read command
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h3; // get ready to send control command to alt_dprio
+ master_write_data <= {{29{1'b0}}, (~write_read_control), write_read_control};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ state <= BASE_BUSY_STATE;
+ end
+ else
+ begin
+ state <= CONTROL_STATE;
+ end
+ end
+ BASE_BUSY_STATE: // send busy to reconfig_togxb
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h7; // set offset cancellation busy to reconfig_togxb
+ master_write_data <= {{30{1'b0}}, alt_dfe_busy};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(set_busy == 1'b0)
+ begin
+ set_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ else
+ begin
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= BASE_BUSY_STATE;
+ end
+ end
+ BUSY_STATE: // wait for write done
+ begin
+ if(dfe_irq_from_base == 1'b1)
+ begin
+ alt_dfe_dprio_busy <= 1'b1;
+ if(write_read_control == 1'b0) //read
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_dfe_dprio_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ end
+ WRITE_DONE_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(dfe_irq_from_base == 1'b1)
+ begin
+ if(alt_dfe_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_dfe_dprio_busy_int <= master_read_data[8];
+ alt_dfe_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ else
+ begin
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ master_address <= 3'h3;
+ master_write_data <= {{16{1'b0}}, {16'h0000}}; //acknowledge write operation
+ alt_dfe_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_dfe_dprio_busy <= 1'b0;
+ dfe_irq <= 1'b1; // write done
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ READ_DATA_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(dfe_irq_from_base == 1'b1)
+ begin
+ if(alt_dfe_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_dfe_dprio_busy_int <= master_read_data[8];
+ alt_dfe_dprio_busy <= 1'b1;
+ end
+ else
+ begin
+ master_address <= 3'h5;
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ alt_dfe_dprio_busy <= 1'b1;
+ end
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ dfe_irq <= 1'b1; // read done
+ alt_dfe_dprio_datain <= master_read_data[15:0];
+ alt_dfe_dprio_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_DATA_STATE;
+ end
+ end
+ default:
+ begin
+ state <= IDLE_STATE;
+ end
+ endcase
+ end
+end
+
+alt_dfe #(
+ .channel_address_width (CLogB2(number_of_reconfig_interfaces*4)),
+ .avmm_slave_addr_width (3),
+ .avmm_slave_rdata_width ( 32),
+ .avmm_slave_wdata_width (32)
+)alt_dfe_inst(
+ .i_resetn (~reset),
+ .i_avmm_clk (reconfig_clk),
+ .i_avmm_saddress (dfe_address),
+ .i_avmm_sread (dfe_read),
+ .i_avmm_swrite (dfe_write),
+ .i_avmm_swritedata (dfe_writedata),
+//. i_avmm_sbegintransfer,
+ .o_avmm_sreaddata (dfe_readdata),
+ .o_avmm_swaitrequest (dfe_waitrequest),
+
+ .i_remap_address (alt_dfe_remap_addr),
+ .o_quad_address (alt_dfe_quad_addr),
+ .o_reconfig_busy (alt_dfe_busy),
+
+ .i_dprio_busy (alt_dfe_dprio_busy),
+ .i_dprio_in (alt_dfe_dprio_datain),
+ .o_dprio_wren (alt_dfe_dprio_wren),
+ .o_dprio_rden (alt_dfe_dprio_rden),
+ .o_dprio_addr (alt_dfe_dprio_addr),
+ .o_dprio_data (alt_dfe_dprio_dataout)
+);
+alt_mutex_acq #(
+ .mutex_wait_time(103), //analog uses 101, offset cancellation uses 102
+ .addr_width(5),
+ .data_width(32)
+)
+mutex_inst (
+ .clk(reconfig_clk),
+ .reset(reset),
+// inputs to the base that should be routed through the mutex
+ .address(master_address_shifted),
+ .writedata(master_write_data),
+ .write(master_write),
+ .read(master_read),
+// output from the mutex which is processed form of output from base
+ .waitrequest(),
+ .readdata(master_read_data),
+
+// outputs from mutex to be routed to the base
+ .master_address(dfe_addr_all),
+ .master_writedata(dfe_writedata_base),
+ .master_write(dfe_write_base),
+ .master_read(dfe_read_base),
+
+// these ports are from the base routed to the mutex
+ .master_waitrequest(dfe_waitrequest_from_base),
+ .master_readdata(dfe_readdata_base), // from MM
+
+//request signal to the mutex should be kept high as long as the mutex is being used
+ .mutex_req(req_and_use_mutex),
+// output from mutex indicates whether you have mutex or not
+ .mutex_grant(mutex_grant)
+);
+assign dfe_address_base = dfe_addr_all[ 4:2];
+//wire assignment
+assign master_address_shifted = {master_address, {2'b00}};
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_eyemon_tgx.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_eyemon_tgx.sv
new file mode 100644
index 0000000000000000000000000000000000000000..cb0a8d147058a8522ece5c1f9b7c0eb17b8ec6bc
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_eyemon_tgx.sv
@@ -0,0 +1,504 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_eyemon_tgx
+#(
+ parameter device_family = "StratixIV",
+ parameter number_of_reconfig_interfaces = 1
+)
+(
+ input wire reconfig_clk, // this will be the reconfig clk
+ input wire reset,
+
+ //avalon MM slave
+ input wire [2:0] eyemon_address, // Check this! fix me!
+ input wire [31:0] eyemon_writedata,
+ input wire eyemon_write,
+ input wire eyemon_read,
+
+ //output MM slave
+ output wire [31:0] eyemon_readdata, // from MM
+ output wire eyemon_waitrequest, // from MM
+
+ output reg eyemon_irq,
+
+ // input from base_reconfig
+ input wire eyemon_irq_from_base,
+ input wire eyemon_waitrequest_from_base,
+
+ // output to base_reconfig
+ // Avalon MM Master
+ output wire [2:0] eyemon_address_base, // 3 bit MM
+ output wire [31:0] eyemon_writedata_base,
+ output wire eyemon_write_base, // start write to GXB
+ output wire eyemon_read_base, // start read from GXB
+
+ // input from base reconfig
+ input wire [31:0] eyemon_readdata_base // data from read command
+
+);
+
+//local parameters
+//state
+localparam IDLE_STATE = 4'b0000;
+localparam LOGICAL_ADDRESS_STATE = 4'b0001;
+localparam WRITE_DATA_STATE = 4'b0010;
+localparam CONTROL_STATE = 4'b0011;
+localparam BUSY_STATE = 4'b0100;
+localparam READ_PHY_ADDR_STATE = 4'b0101;
+localparam CHECK_PHY_ADDR_STATE = 4'b0110;
+localparam ADDRESS_OFFSET_STATE = 4'b0111;
+localparam BASE_BUSY_STATE = 4'b1000;
+localparam READ_DATA_STATE = 4'b1001;
+localparam WRITE_DONE_STATE = 4'b1010;
+
+localparam ILLEGAL_PHYSICAL_CHNL = 10'b1111111111;
+
+wire [4:0] eyemon_address_all; // 5 bit MM
+wire mutex_grant;
+wire [31:0] master_read_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [3:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg write_read_control;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_read;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [31:0] master_write_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [2:0] master_address;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg req_and_use_mutex;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg set_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg wait_phy_addr_ready;
+
+wire [4:0] master_address_shifted;
+
+//alt_eyemon instantiation
+wire alt_eyemon_busy;
+wire [15:0] alt_eyemon_dprio_dataout;
+wire alt_eyemon_dprio_wren;
+wire alt_eyemon_dprio_rden;
+wire [(number_of_reconfig_interfaces*4-1) : 0] alt_eyemon_error;
+
+wire [15:0] alt_eyemon_dprio_addr;
+wire [8:0] alt_eyemon_quad_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [11:0] alt_eyemon_remap_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_eyemon_dprio_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_eyemon_dprio_busy_int;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] alt_eyemon_dprio_datain;
+
+function integer CLogB2;
+input integer Depth;
+integer i;
+begin
+i = Depth;
+for(CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1)
+i = i >> 1;
+end
+endfunction
+
+// synopsys translate_off
+initial begin
+ state = 3'b000;
+ alt_eyemon_remap_addr = 12'h000;
+ req_and_use_mutex = 1'b0;
+ wait_phy_addr_ready = 1'b0;
+ alt_eyemon_dprio_datain = 16'h0000;
+ alt_eyemon_dprio_busy = 1'b0;
+ alt_eyemon_dprio_busy_int = 1'b0;
+
+ master_write = 1'b0;
+ master_read = 1'b0;
+ master_write_data = {32{1'b0}};
+ master_address = 3'h0;
+
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy = 1'b0; // 1 for assert busy, 0 for deassert busy
+
+ eyemon_irq = 1'b0;
+
+end
+// synopsys translate_on
+
+integer count;
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset)
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ master_write_data <= {32{1'b0}};
+ master_address <= 3'h0;
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ req_and_use_mutex <= 1'b0;
+ wait_phy_addr_ready <= 1'b0;
+ alt_eyemon_dprio_busy_int<= 1'b0;
+ eyemon_irq <= 1'b0;
+ end
+ else begin
+ if(alt_eyemon_busy == 1'b0)
+ req_and_use_mutex <= 1'b0;
+ else
+ req_and_use_mutex <= 1'b1;
+
+ case (state)
+ IDLE_STATE:
+ begin
+ eyemon_irq <= 1'b0; // reset write/read done flag
+ //reset the signal
+ set_busy <= 1'b0;
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ alt_eyemon_remap_addr <= 12'h000;
+
+ //alt_eyemon will not assert wren and rden at the same time
+ if((alt_eyemon_dprio_wren == 1'b1) || (alt_eyemon_dprio_rden == 1'b1))
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(alt_eyemon_dprio_wren == 1'b1)
+ write_read_control <= 1'b1; // 1 for write
+ else
+ write_read_control <= 1'b0; // 0 for read
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ else
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ state <= IDLE_STATE;
+ end
+ end
+ LOGICAL_ADDRESS_STATE: //sending channel and quad address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h1;
+ master_write_data <= {{21{1'b0}}, alt_eyemon_quad_addr, alt_eyemon_dprio_addr[13:12]};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= READ_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ end
+ READ_PHY_ADDR_STATE: //read phsical address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h2;
+ master_read <= 1'b1;
+ master_write <= 1'b0;
+ if (wait_phy_addr_ready == 1'b1)
+ begin
+ wait_phy_addr_ready <= 1'b0;
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ wait_phy_addr_ready <= 1'b1;
+ state <= READ_PHY_ADDR_STATE;
+ //state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_PHY_ADDR_STATE;
+ end
+ end
+ CHECK_PHY_ADDR_STATE: //check physical address correct or not
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ if (master_read_data[9:0] == ILLEGAL_PHYSICAL_CHNL)
+ begin
+ // synopsys translate_off
+ $display ("Illegal physical address: 10'h%h", master_read_data);
+ $display ("Time: %0t Instance: %m", $time);
+ // synopsys translate_on
+ alt_eyemon_remap_addr <= 12'hfff;
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ alt_eyemon_remap_addr <= master_read_data[11:0];
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ else
+ begin
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ ADDRESS_OFFSET_STATE: // send address offset to alt_dprio
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h4;
+ master_write_data <= {{20{1'b0}}, alt_eyemon_dprio_addr[11:0]};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(write_read_control == 1'b1)
+ state <= WRITE_DATA_STATE;
+ else
+ state <= CONTROL_STATE;
+ end
+ else
+ begin
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ WRITE_DATA_STATE:
+ begin
+ master_address <= 3'h5;
+ master_write_data = {{16{1'b0}}, alt_eyemon_dprio_dataout};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= CONTROL_STATE;
+ end
+ CONTROL_STATE: // sending write/read command
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h3; // get ready to send control command to alt_dprio
+ master_write_data <= {{29{1'b0}}, (~write_read_control), write_read_control};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ state <= BASE_BUSY_STATE;
+ end
+ else
+ begin
+ state <= CONTROL_STATE;
+ end
+ end
+ BASE_BUSY_STATE: // send busy to reconfig_togxb
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h7; // set offset cancellation busy to reconfig_togxb
+ master_write_data <= {{30{1'b0}}, alt_eyemon_busy};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(set_busy == 1'b0)
+ begin
+ set_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ else
+ begin
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= BASE_BUSY_STATE;
+ end
+ end
+ BUSY_STATE: // wait for write done
+ begin
+ if(eyemon_irq_from_base == 1'b1)
+ begin
+ alt_eyemon_dprio_busy <= 1'b1;
+ if(write_read_control == 1'b0) //read
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_eyemon_dprio_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ end
+ WRITE_DONE_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(eyemon_irq_from_base == 1'b1)
+ begin
+ if(alt_eyemon_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_eyemon_dprio_busy_int <= master_read_data[8];
+ alt_eyemon_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ else
+ begin
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ master_address <= 3'h3;
+ master_write_data <= {{16{1'b0}}, {16'h0000}}; //acknowledge write operation
+ alt_eyemon_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_eyemon_dprio_busy <= 1'b0;
+ eyemon_irq <= 1'b1; // write done
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ READ_DATA_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(eyemon_irq_from_base == 1'b1)
+ begin
+ if(alt_eyemon_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_eyemon_dprio_busy_int <= master_read_data[8];
+ alt_eyemon_dprio_busy <= 1'b1;
+ end
+ else
+ begin
+ master_address <= 3'h5;
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ alt_eyemon_dprio_busy <= 1'b1;
+ end
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ eyemon_irq <= 1'b1; // read done
+ alt_eyemon_dprio_datain <= master_read_data[15:0];
+ alt_eyemon_dprio_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_DATA_STATE;
+ end
+ end
+ default:
+ begin
+ state <= IDLE_STATE;
+ end
+ endcase
+ end
+end
+
+alt_eyemon #(
+ .channel_address_width (CLogB2(number_of_reconfig_interfaces*4)),
+ .avmm_slave_addr_width (3),
+ .avmm_slave_rdata_width ( 32),
+ .avmm_slave_wdata_width (32)
+)alt_eyemon_inst(
+ .i_resetn (~reset),
+ .i_avmm_clk (reconfig_clk),
+ .i_avmm_saddress (eyemon_address),
+ .i_avmm_sread (eyemon_read),
+ .i_avmm_swrite (eyemon_write),
+ .i_avmm_swritedata (eyemon_writedata),
+//. i_avmm_sbegintransfer,
+ .o_avmm_sreaddata (eyemon_readdata),
+ .o_avmm_swaitrequest (eyemon_waitrequest),
+
+ .i_remap_phase (1'b1), // need to figure out best way to control this - for now, always remap - fix me!
+ .i_remap_address (alt_eyemon_remap_addr),
+ .o_quad_address (alt_eyemon_quad_addr),
+ .o_reconfig_busy (alt_eyemon_busy),
+
+ .i_dprio_busy (alt_eyemon_dprio_busy),
+ .i_dprio_in (alt_eyemon_dprio_datain),
+ .o_dprio_wren (alt_eyemon_dprio_wren),
+ .o_dprio_rden (alt_eyemon_dprio_rden),
+ .o_dprio_addr (alt_eyemon_dprio_addr),
+ .o_dprio_data (alt_eyemon_dprio_dataout)
+);
+alt_mutex_acq #(
+ .mutex_wait_time(103), //analog uses 101, offset cancellation uses 102
+ .addr_width(5),
+ .data_width(32)
+)
+mutex_inst (
+ .clk(reconfig_clk),
+ .reset(reset),
+// inputs to the base that should be routed through the mutex
+ .address(master_address_shifted),
+ .writedata(master_write_data),
+ .write(master_write),
+ .read(master_read),
+// output from the mutex which is processed form of output from base
+ .waitrequest(),
+ .readdata(master_read_data),
+
+// outputs from mutex to be routed to the base
+ .master_address({eyemon_address_all}),
+ .master_writedata(eyemon_writedata_base),
+ .master_write(eyemon_write_base),
+ .master_read(eyemon_read_base),
+
+// these ports are from the base routed to the mutex
+ .master_waitrequest(eyemon_waitrequest_from_base),
+ .master_readdata(eyemon_readdata_base), // from MM
+
+//request signal to the mutex should be kept high as long as the mutex is being used
+ .mutex_req(req_and_use_mutex),
+// output from mutex indicates whether you have mutex or not
+ .mutex_grant(mutex_grant)
+);
+
+//wire assignment
+assign eyemon_address_base = eyemon_address_all[4:2];
+assign master_address_shifted = {master_address, {2'b00}};
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..102856f4162133620df696f7e6ccb75bc2dca7f4
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_h.sv
@@ -0,0 +1,266 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Top-level definitions for transceiver reconfig IP
+//
+// $Header$
+//
+// PACKAGE DECLARATION
+package alt_xcvr_reconfig_h;
+
+ ////////////////////////////////////////////////////////
+ // Top-level register map for transceiver reconfig IP
+ ////////////////////////////////////////////////////////
+ localparam W_XR_ADDR = 7; // address width on mgmt interface
+ localparam W_XR_FEATURE_LADDR = 3; // address width of standard feature block, and basic logical interface
+ typedef bit [W_XR_ADDR -1:0] t_xreconf_addr;
+ typedef bit [W_XR_FEATURE_LADDR-1:0] t_xr_feature_addr;
+
+ // Feature block indices (used for address decoding for each block)
+ localparam INDEX_XR_OFFSET = 0;
+ localparam INDEX_XR_ANALOG = 1;
+ localparam INDEX_XR_EYEMON = 2;
+ localparam INDEX_XR_DFE = 3;
+ localparam INDEX_XR_DIRECT = 4;
+ localparam INDEX_XR_ADCE = 5;
+ localparam INDEX_XR_LC = 6;
+ localparam INDEX_XR_MIF = 7;
+ localparam INDEX_XR_PLL = 8;
+ localparam INDEX_XR_DCD = 9;
+ localparam INDEX_XR_END = 10; // must always mark end of address space
+
+ // Each feature block is allocated an 8-word address range
+ localparam [W_XR_ADDR-1:0] ADDR_XR_OFFSET_BASE = t_xreconf_addr'(INDEX_XR_OFFSET << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_BASE = t_xreconf_addr'(INDEX_XR_ANALOG << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_BASE = t_xreconf_addr'(INDEX_XR_EYEMON << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_BASE = t_xreconf_addr'(INDEX_XR_DFE << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_BASE = t_xreconf_addr'(INDEX_XR_DIRECT << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_BASE = t_xreconf_addr'(INDEX_XR_ADCE << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_LC_BASE = t_xreconf_addr'(INDEX_XR_LC << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_BASE = t_xreconf_addr'(INDEX_XR_MIF << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_BASE = t_xreconf_addr'(INDEX_XR_PLL << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_BASE = t_xreconf_addr'(INDEX_XR_DCD << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_END_BASE = t_xreconf_addr'(INDEX_XR_END << W_XR_FEATURE_LADDR); // must always mark end of address space
+
+ localparam [W_XR_FEATURE_LADDR-1:0] XR_STATUS_OFST = t_xr_feature_addr'(2);
+ localparam XR_STATUS_OFST_COMB_BUSY = 8;
+
+ ////////////////////////////////////////////////////////
+ // Offset Cancellation block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_OFFSET_STATUS = t_xreconf_addr'(ADDR_XR_OFFSET_BASE + 2);
+
+
+ ////////////////////////////////////////////////////////
+ // Analog block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_LCH = t_xreconf_addr'(ADDR_XR_ANALOG_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_PCH = t_xreconf_addr'(ADDR_XR_ANALOG_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_STATUS = t_xreconf_addr'(ADDR_XR_ANALOG_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_OFFSET = t_xreconf_addr'(ADDR_XR_ANALOG_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_DATA = t_xreconf_addr'(ADDR_XR_ANALOG_BASE + 4);
+
+ // Analog internal register offsets
+ // These are to be written to the analog offset address register, ADDR_XR_ANALOG_OFFSET
+ localparam XR_ANALOG_OFFSET_VOD = 0;
+ localparam XR_ANALOG_OFFSET_PREEMPH0T = 1;
+ localparam XR_ANALOG_OFFSET_PREEMPH1T = 2;
+ localparam XR_ANALOG_OFFSET_PREEMPH2T = 3;
+ localparam XR_ANALOG_OFFSET_RXDCGAIN = 16;
+ localparam XR_ANALOG_OFFSET_RXEQCTRL = 17;
+ localparam XR_ANALOG_OFFSET_PRECDRLPBK = 32;
+ localparam XR_ANALOG_OFFSET_POSTCDRLPBK = 33;
+
+ ////////////////////////////////////////////////////////
+ // DFE block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_LCH = t_xreconf_addr'(ADDR_XR_DFE_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_PCH = t_xreconf_addr'(ADDR_XR_DFE_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_STATUS = t_xreconf_addr'(ADDR_XR_DFE_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_OFFSET = t_xreconf_addr'(ADDR_XR_DFE_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_DATA = t_xreconf_addr'(ADDR_XR_DFE_BASE + 4);
+
+ // DFE internal register offsets
+ // These are to be written to the DFE offset address register, ADDR_XR_DFE_OFFSET
+ localparam XR_DFE_OFFSET_CTRL = 0;
+ localparam XR_DFE_OFFSET_TAP1 = 1;
+ localparam XR_DFE_OFFSET_TAP2 = 2;
+ localparam XR_DFE_OFFSET_TAP3 = 3;
+ localparam XR_DFE_OFFSET_TAP4 = 4;
+ localparam XR_DFE_OFFSET_TAP5 = 5;
+ localparam XR_DFE_OFFSET_REF = 6;
+ localparam XR_DFE_OFFSET_STEP = 7;
+ localparam XR_DFE_OFFSET_DFE12 = 18;
+ localparam XR_DFE_OFFSET_DFE13 = 19;
+ localparam XR_DFE_OFFSET_DFE14 = 20;
+ localparam XR_DFE_OFFSET_DFE15 = 21;
+ localparam XR_DFE_OFFSET_CAL_PLL = 22;
+ localparam XR_DFE_OFFSET_CAL_TBUS = 23;
+ localparam XR_DFE_OFFSET_CAL_SAMPL = 24;
+ ////////////////////////////////////////////////////////
+ // Eyemon block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_LCH = t_xreconf_addr'(ADDR_XR_EYEMON_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_PCH = t_xreconf_addr'(ADDR_XR_EYEMON_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_STATUS = t_xreconf_addr'(ADDR_XR_EYEMON_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_OFFSET = t_xreconf_addr'(ADDR_XR_EYEMON_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_DATA = t_xreconf_addr'(ADDR_XR_EYEMON_BASE + 4);
+
+ // EYEMON internal register offsets
+ // These are to be written to the EYEMON offset address register, ADDR_XR_EYEMON_OFFSET
+ localparam XR_EYEMON_OFFSET_CTRL = 0;
+ localparam XR_EYEMON_OFFSET_HPHASE = 1;
+ localparam XR_EYEMON_OFFSET_VHEIGHT = 2;
+ localparam XR_EYEMON_OFFSET_EYEMON16 = 3;
+ localparam XR_EYEMON_OFFSET_EYEMON17 = 4;
+
+ ////////////////////////////////////////////////////////
+ // ADCE block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_LCH = t_xreconf_addr'(ADDR_XR_ADCE_BASE + 0); // Logical channel number
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_PCH = t_xreconf_addr'(ADDR_XR_ADCE_BASE + 1); // Physical channel number
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_STATUS = t_xreconf_addr'(ADDR_XR_ADCE_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_OFFSET = t_xreconf_addr'(ADDR_XR_ADCE_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_DATA = t_xreconf_addr'(ADDR_XR_ADCE_BASE + 4);
+
+ // ADCE internal register offsets
+ // These are to be written to the ADCE offset address register, ADDR_XR_ADCE_OFFSET
+ localparam XR_ADCE_OFFSET_CTRL = 0;
+ localparam XR_ADCE_OFFSET_RESULTS = 1; // Manual setting equivalent to ADCE results
+ localparam XR_ADCE_OFFSET_RADCE_ATT_0 = 9; // radce_att[15: 0]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_1 = 10; // radce_att[31:15]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_2 = 11; // radce_att[47:32]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_3 = 12; // radce_att[63:48]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_4 = 13; // radce_att[79:64]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_5 = 14; // radce_att[95:80]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_6 = 15; // radce_att[111:96]
+
+ ////////////////////////////////////////////////////////
+ // DCD block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_LCH = t_xreconf_addr'(ADDR_XR_DCD_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_PCH = t_xreconf_addr'(ADDR_XR_DCD_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_STATUS = t_xreconf_addr'(ADDR_XR_DCD_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_OFFSET = t_xreconf_addr'(ADDR_XR_DCD_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_DATA = t_xreconf_addr'(ADDR_XR_DCD_BASE + 4);
+
+ // DCD internal register offsets
+ // These are to be written to the DFE offset address register, ADDR_XR_DCD_OFFSET
+ localparam XR_DCD_OFFSET_CTRL = 0;
+
+ ////////////////////////////////////////////////////////
+ // MIF block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_LCH = t_xreconf_addr'(ADDR_XR_MIF_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_PCH = t_xreconf_addr'(ADDR_XR_MIF_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_STATUS = t_xreconf_addr'(ADDR_XR_MIF_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_OFFSET = t_xreconf_addr'(ADDR_XR_MIF_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_DATA = t_xreconf_addr'(ADDR_XR_MIF_BASE + 4);
+
+ ////////////////////////////////////////////////////////
+ // PLL block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_LCH = t_xreconf_addr'(ADDR_XR_PLL_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_PCH = t_xreconf_addr'(ADDR_XR_PLL_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_STATUS = t_xreconf_addr'(ADDR_XR_PLL_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_OFFSET = t_xreconf_addr'(ADDR_XR_PLL_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_DATA = t_xreconf_addr'(ADDR_XR_PLL_BASE + 4);
+
+
+
+
+ ////////////////////////////////////////////////////////
+ // Basic block addresses (internal, private addresses)
+ ////////////////////////////////////////////////////////
+ // The 'basic' interface block is the switch that routes requests to
+ // an appropriate physical reconfiguration interface. A logical channel
+ // number acts as a channel ID, which allows the basic block to find
+ // the corresponding physical reconfiguration interface, and a physical
+ // channel index within a physical interface.
+ //
+ // The Basic (B) block features are also available via the direct access block.
+ // All users of the basic block, including the direct access block, must
+ // acquire appropriate semaphores before using an interface, and release
+ // the semaphores when done, to avoid locking out other feature blocks.
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_MUTEX = t_xr_feature_addr'(0);
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_LOGICAL_CHANNEL = t_xr_feature_addr'(1);
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_PHYSICAL_CHANNEL = t_xr_feature_addr'(2);
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_CONTROL = t_xr_feature_addr'(3);
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_OFFSET_ADDR = t_xr_feature_addr'(4);
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_DATA = t_xr_feature_addr'(5);
+
+
+ ////////////////////////////////////////////////////////
+ // Direct Access & Basic block addresses
+ ////////////////////////////////////////////////////////
+ //
+ // The minimum steps to read & write a reconfiguration word are the following:
+ // Step 1 - acquire basic arbiter lock (write 1 to ADDR_XR_DIRECT_ARB_ACQ)
+ // Step 2 - write logical channel number to ADDR_XR_DIRECT_LCH
+ // Step 3 - acquire channel lock
+ // 3a - request channel lock (write XR_DIRECT_CONTROL_PHYS_LOCK_SET to ADDR_XR_DIRECT_CONTROL)
+ // 3b - confirm channel lock (read ADDR_XR_DIRECT_CONTROL, mask with XR_DIRECT_STATUS_BITMASK_PHYS_LOCK_GRANTED)
+ // -- repeat step 3b until result after applying mask is != 0
+ // Step 4 - write channel offset address to ADDR_XR_DIRECT_OFFSET
+ // Step 5 - read existing value from reconfig space, modify, then write back
+ // 5a (read cycle part 1) - write XR_DIRECT_CONTROL_RECONF_READ to ADDR_XR_DIRECT_CONTROL
+ // 5b (read cycle part 2) - read data from ADDR_XR_DIRECT_DATA
+ // 5c (write cycle part 1) - write modified value to ADDR_XR_DIRECT_DATA
+ // 5d (write cycle part 2) - write XR_DIRECT_CONTROL_RECONF_WRITE to ADDR_XR_DIRECT_CONTROL
+ // -- addtional read-modify-write cycles, repeat from step 2 or 4 (can skip step 3a)
+ // Step 6 - release channel lock (write XR_DIRECT_CONTROL_PHYS_LOCK_CLEAR to ADDR_XR_DIRECT_CONTROL)
+ // Step 7 - release basic arbiter lock (write 0 to ADDR_XR_DIRECT_ARB_ACQ)
+ //
+ // Direct/Basic register bitmap ---------------------------------------------------------
+ // word addr wr/rd description
+ // ------------------------------------------------------
+ // 0 wr basic arbiter, 1 to request access, 0 to release lock
+ // 1 wr/rd logical channel number
+ // 2 rd physical channel number. When lower 3 bits are 3'b111, means ch is not present
+ // 3 wr/rd status/control -- see XR_DIRECT_CONTROL_* opcodes and XR_DIRECT_STATUS_* bitfield definitions
+ // 4 wr/rd offset_addr -- for opcode-based reads & writes
+ // 5 wr/rd data -- for opcode-based reads & writes
+ // 6 -- reserved
+ // 7 -- reserved
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_ARB_ACQ = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + 0); // write 1 to request B access, 0 to release
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_LCH = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + ADDR_XCVR_RECONFIG_BASIC_LOGICAL_CHANNEL);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_PCH = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + ADDR_XCVR_RECONFIG_BASIC_PHYSICAL_CHANNEL);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_CONTROL = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + ADDR_XCVR_RECONFIG_BASIC_CONTROL);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_OFFSET = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + ADDR_XCVR_RECONFIG_BASIC_OFFSET_ADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_DATA = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + ADDR_XCVR_RECONFIG_BASIC_DATA);
+
+ // Opcode values for writes to control word, ADDR_XR_DIRECT_CONTROL
+ localparam XR_DIRECT_CONTROL_RECONF_WRITE = 32'b0000; // reconfig space: write current DATA to OFFSET addr (as physical addr or ch offset addr)
+ localparam XR_DIRECT_CONTROL_RECONF_READ = 32'b0001; // reconfig space: read from OFFSET_ADDR, save result in DATA
+ localparam XR_DIRECT_CONTROL_LADDR_SET = 32'b0010; // interpret OFFSET_ADDR as logical addr, with automatic ch addr offset
+ localparam XR_DIRECT_CONTROL_PADDR_SET = 32'b0011; // interpret OFFSET_ADDR as physical addr, with no automatic addr offset
+ localparam XR_DIRECT_CONTROL_PHYS_LOCK_CLEAR = 32'b0100; // clear lock request for current channel
+ localparam XR_DIRECT_CONTROL_PHYS_LOCK_SET = 32'b0101; // set lock request for current channel
+ localparam XR_DIRECT_CONTROL_ADDR_AUTO_INCR_CLEAR = 32'b0110; // clear auto-write-and-address-increment mode for data writes
+ localparam XR_DIRECT_CONTROL_ADDR_AUTO_INCR_SET = 32'b0111; // set auto-write-and-address-increment mode for data writes
+ localparam XR_DIRECT_CONTROL_INTERNAL_WRITE = 32'b1000; // Internal registers, mainly testbus control
+ //localparam XR_DIRECT_CONTROL_INTERNAL_READ = 32'b1001; // internal reg space: read from OFFSET_ADDR, save result in DATA
+ localparam XR_DIRECT_CONTROL_TABLE_READ = 32'b1011; // ROM table lookup, especially for PLL and clock mux remapping
+
+ // Read of control/status reg returns this bitfield data
+ localparam XR_DIRECT_STATUS_BITMASK_PHYS_LOCK_GRANTED = 32'b0001; // on read, bit 0 is grant status
+ localparam XR_DIRECT_STATUS_BITMASK_PHYS_LOCK_REQUESTED = 32'b0010; // on read, bit 1 is physical lock request flag
+ localparam XR_DIRECT_STATUS_BITMASK_USING_PHYS_ADDR = 32'b0100; // on read, bit 2 is physical addr mode indicator (0 mean logical addr)
+ localparam XR_DIRECT_STATUS_BITMASK_USING_ADDR_AUTO_INCR = 32'b1000; // on read, bit 3 is auto-write-and-addr-incr mode indicator
+
+ // Internal register addresses, for read/write via these opcodes: XR_DIRECT_CONTROL_INTERNAL_*
+ localparam XR_DIRECT_OFFSET_TESTBUS_SEL = 2'd0; // internal register for testbus sel
+
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_offset_cancellation.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_offset_cancellation.sv
new file mode 100644
index 0000000000000000000000000000000000000000..0dd5517bb661acbd542861fa584fe89ae3aa336c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_offset_cancellation.sv
@@ -0,0 +1,174 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_offset_cancellation
+#(
+ parameter device_family = "StratixV",
+ parameter number_of_reconfig_interfaces = 1
+)
+(
+ input wire reconfig_clk, // this will be the reconfig clk
+ input wire reset,
+
+ //avalon MM slave
+ input wire [2:0] offset_cancellation_address, // MM address
+ input wire [31:0] offset_cancellation_writedata,
+ input wire offset_cancellation_write,
+ input wire offset_cancellation_read,
+
+ //output MM slave
+ output wire [31:0] offset_cancellation_readdata, // from MM
+
+ output wire offset_cancellation_done,
+
+ // input from base_reconfig
+ input wire offset_cancellation_irq_from_base,
+ input wire offset_cancellation_waitrequest_from_base,
+ output wire offset_cancellation_waitrequest,
+
+ // output to base_reconfig
+ // Avalon MM Master
+ output wire [2:0] offset_cancellation_address_base, // 3 bit MM
+ output wire [31:0] offset_cancellation_writedata_base,
+ output wire offset_cancellation_write_base, // start write to GXB
+ output wire offset_cancellation_read_base, // start read from GXB
+
+ // input from base reconfig
+ input wire [31:0] offset_cancellation_readdata_base, // data from read command
+
+ // Avalon ST
+ input wire [number_of_reconfig_interfaces*16 - 1 : 0] testbus_data,
+
+ // external connect to switch fabric: request basic access from arbiter
+ output wire arb_req,
+ input wire arb_grant
+
+);
+
+import altera_xcvr_functions::*;
+localparam is_s4 = has_s4_style_hssi(device_family);
+localparam is_s5 = has_s5_style_hssi(device_family);
+localparam is_a5 = has_a5_style_hssi(device_family);
+
+
+generate
+ //Deepak - Namespace support for AII GX and CIVGX
+ if(is_s4)
+ begin
+ wire [4:0] w_tgx_offset_cancellation_address_base;
+ alt_xcvr_reconfig_offset_cancellation_tgx
+ #(
+ .device_family(device_family),
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces)
+ ) offset_cancellation_tgx
+ (
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .offset_cancellation_address(offset_cancellation_address),
+ .offset_cancellation_writedata(offset_cancellation_writedata),
+ .offset_cancellation_write(offset_cancellation_write),
+ .offset_cancellation_read(offset_cancellation_read),
+ .offset_cancellation_readdata(offset_cancellation_readdata),
+ .offset_cancellation_done(offset_cancellation_done),
+ .offset_cancellation_irq_from_base(offset_cancellation_irq_from_base),
+ .offset_cancellation_waitrequest_from_base(offset_cancellation_waitrequest_from_base),
+ .offset_cancellation_waitrequest(offset_cancellation_waitrequest),
+ .offset_cancellation_address_base(w_tgx_offset_cancellation_address_base),
+ .offset_cancellation_writedata_base(offset_cancellation_writedata_base),
+ .offset_cancellation_write_base(offset_cancellation_write_base),
+ .offset_cancellation_read_base(offset_cancellation_read_base),
+ .offset_cancellation_readdata_base(offset_cancellation_readdata_base),
+ .testbus_data(testbus_data)
+ );
+ assign offset_cancellation_address_base = w_tgx_offset_cancellation_address_base[4:2];
+ assign arb_req = 1'b0 & arb_grant; // not currently used in S4 architecture
+ end
+ else if (is_s5)
+ begin
+ alt_xcvr_reconfig_offset_cancellation_sv
+ #(
+ .device_family(device_family),
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces)
+ ) offset_cancellation_sv
+ (
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .offset_cancellation_address(offset_cancellation_address),
+ .offset_cancellation_writedata(offset_cancellation_writedata),
+ .offset_cancellation_write(offset_cancellation_write),
+ .offset_cancellation_read(offset_cancellation_read),
+ .offset_cancellation_readdata(offset_cancellation_readdata),
+ .offset_cancellation_done(offset_cancellation_done),
+ .offset_cancellation_irq_from_base(offset_cancellation_irq_from_base),
+ .offset_cancellation_waitrequest_from_base(offset_cancellation_waitrequest_from_base),
+ .offset_cancellation_waitrequest(offset_cancellation_waitrequest),
+ .offset_cancellation_address_base(offset_cancellation_address_base),
+ .offset_cancellation_writedata_base(offset_cancellation_writedata_base),
+ .offset_cancellation_write_base(offset_cancellation_write_base),
+ .offset_cancellation_read_base(offset_cancellation_read_base),
+ .offset_cancellation_readdata_base(offset_cancellation_readdata_base),
+ .testbus_data(testbus_data[7:0]), // testbus data is now provided on a per-channel basis from the 'B' - only need the lower 8 bits
+ .arb_req(arb_req),
+ .arb_grant(arb_grant)
+ );
+ end
+ else if (is_a5)
+ begin
+ alt_xcvr_reconfig_offset_cancellation_av
+ #(
+ .device_family(device_family),
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces)
+ ) offset_cancellation_av
+ (
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .offset_cancellation_address(offset_cancellation_address),
+ .offset_cancellation_writedata(offset_cancellation_writedata),
+ .offset_cancellation_write(offset_cancellation_write),
+ .offset_cancellation_read(offset_cancellation_read),
+ .offset_cancellation_readdata(offset_cancellation_readdata),
+ .offset_cancellation_done(offset_cancellation_done),
+ .offset_cancellation_irq_from_base(offset_cancellation_irq_from_base),
+ .offset_cancellation_waitrequest_from_base(offset_cancellation_waitrequest_from_base),
+ .offset_cancellation_waitrequest(offset_cancellation_waitrequest),
+ .offset_cancellation_address_base(offset_cancellation_address_base),
+ .offset_cancellation_writedata_base(offset_cancellation_writedata_base),
+ .offset_cancellation_write_base(offset_cancellation_write_base),
+ .offset_cancellation_read_base(offset_cancellation_read_base),
+ .offset_cancellation_readdata_base(offset_cancellation_readdata_base),
+ .testbus_data(testbus_data[7:0]), // testbus data is now provided on a per-channel basis from the 'B' - only need the lower 8 bits
+ .arb_req(arb_req),
+ .arb_grant(arb_grant)
+ );
+ end
+ else
+ begin
+ assign offset_cancellation_readdata = 32'd0;
+ assign offset_cancellation_done = 1'd0;
+ assign offset_cancellation_waitrequest = 1'd0;
+ assign offset_cancellation_address_base = 3'd0;
+ assign offset_cancellation_writedata_base = 32'd0;
+ assign offset_cancellation_write_base = 1'd0;
+ assign offset_cancellation_read_base = 1'd0;
+ assign arb_req = 1'd0;
+ end
+
+
+
+endgenerate
+
+endmodule
+
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_offset_cancellation_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_offset_cancellation_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..01ee1edc16393c8b5f525ce12734b754321f57b7
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_offset_cancellation_tgx.v
@@ -0,0 +1,581 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_offset_cancellation_tgx
+#(
+ parameter device_family = "StratixIV",
+ parameter number_of_reconfig_interfaces = 1
+)
+(
+ input wire reconfig_clk, // this will be the reconfig clk
+ input wire reset,
+
+ //avalon MM slave
+ input wire offset_cancellation_address, // MM address
+ input wire [31:0] offset_cancellation_writedata,
+ input wire offset_cancellation_write,
+ input wire offset_cancellation_read,
+
+ //output MM slave
+ output reg [31:0] offset_cancellation_readdata, // from MM
+
+ output reg offset_cancellation_done,
+
+ // input from base_reconfig
+ input wire offset_cancellation_irq_from_base,
+ input wire offset_cancellation_waitrequest_from_base,
+
+ output wire offset_cancellation_waitrequest,
+
+ // output to base_reconfig
+ // Avalon MM Master
+ output wire [4:0] offset_cancellation_address_base, // 3 bit MM
+ output wire [31:0] offset_cancellation_writedata_base,
+ output wire offset_cancellation_write_base, // start write to GXB
+ output wire offset_cancellation_read_base, // start read from GXB
+
+ // input from base reconfig
+ input wire [31:0] offset_cancellation_readdata_base, // data from read command
+
+ // Avalon ST
+ input wire [number_of_reconfig_interfaces*16 - 1 : 0] testbus_data
+);
+
+///////////////////////////////////////////////////////////////////
+// Memory map | wr/rd | Description
+//----------------------------------------------------------------
+// 0 | wr/rd | [31:10] Reserved
+// | | [9] Error
+// | | [8] Busy
+// | | [7:1] Reserved
+// | | [0] Start (hidden for QII 9.1)
+///////////////////////////////////////////////////////////////////
+
+//local parameters
+//state
+localparam IDLE_STATE = 4'b0000;
+localparam LOGICAL_ADDRESS_STATE = 4'b0001;
+localparam WRITE_DATA_STATE = 4'b0010;
+localparam CONTROL_STATE = 4'b0011;
+localparam BUSY_STATE = 4'b0100;
+localparam READ_PHY_ADDR_STATE = 4'b0101;
+localparam CHECK_PHY_ADDR_STATE = 4'b0110;
+localparam ADDRESS_OFFSET_STATE = 4'b0111;
+localparam BASE_BUSY_STATE = 4'b1000;
+localparam READ_DATA_STATE = 4'b1001;
+localparam WRITE_DONE_STATE = 4'b1010;
+
+localparam ILLEGAL_PHYSICAL_CHNL = 10'b1111111111;
+
+wire mutex_grant;
+wire [31:0] master_read_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [3:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg write_read_control;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_read;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [31:0] master_write_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [2:0] master_address;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg req_and_use_mutex;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg set_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_cal_error_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg wait_phy_addr_ready;
+
+wire [4:0] master_address_shifted;
+
+//alt_cal instantiation
+wire alt_cal_busy;
+wire [15:0] alt_cal_dprio_dataout;
+wire alt_cal_dprio_wren;
+wire alt_cal_dprio_rden;
+wire alt_cal_retain_addr;
+wire [(number_of_reconfig_interfaces*4-1) : 0] alt_cal_error;
+
+wire [number_of_reconfig_interfaces*16 - 1 : 0] alt_cal_testbuses;
+wire [15:0] alt_cal_dprio_addr;
+wire [8:0] alt_cal_quad_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [11:0] alt_cal_remap_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_cal_dprio_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_cal_dprio_busy_int;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] alt_cal_dprio_datain;
+
+function integer CLogB2;
+input integer Depth;
+integer i;
+begin
+i = Depth;
+for(CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1)
+i = i >> 1;
+end
+endfunction
+
+// Implement waitrequest to match previous implementation
+altera_wait_generate wait_gen(
+ .rst(reset),
+ .clk(reconfig_clk),
+ .launch_signal(offset_cancellation_read),
+ .wait_req(offset_cancellation_waitrequest)
+);
+
+// synopsys translate_off
+initial begin
+ state = 3'b000;
+ alt_cal_remap_addr = 12'h000;
+ req_and_use_mutex = 1'b0;
+ wait_phy_addr_ready = 1'b0;
+ // alt_cal_testbuses = 0;
+ alt_cal_dprio_datain = 16'h0000;
+ alt_cal_dprio_busy = 1'b0;
+ alt_cal_dprio_busy_int = 1'b0;
+
+ master_write = 1'b0;
+ master_read = 1'b0;
+ master_write_data = {32{1'b0}};
+ master_address = 3'h0;
+
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy = 1'b0; // 1 for assert busy, 0 for deassert busy
+
+ alt_cal_error_reg = 1'b0;
+ offset_cancellation_done = 1'b0;
+
+end
+// synopsys translate_on
+
+integer count;
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset)
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ master_write_data <= {32{1'b0}};
+ master_address <= 3'h0;
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ offset_cancellation_readdata[31:0] <= {32{1'b0}};
+ alt_cal_error_reg <= 1'b0;
+ req_and_use_mutex <= 1'b0;
+ wait_phy_addr_ready <= 1'b0;
+ alt_cal_dprio_busy_int<= 1'b0;
+ offset_cancellation_done <= 1'b0;
+ end
+ else begin
+ if(offset_cancellation_read == 1'b1)
+ begin
+ if(offset_cancellation_address == 1'b0)
+ begin
+ offset_cancellation_readdata <= {{22{1'b0}}, alt_cal_error_reg, alt_cal_busy , {8{1'b0}}};
+ end
+ end
+
+ for(count=0; count < (number_of_reconfig_interfaces*4); count=count+1)
+ begin
+ alt_cal_error_reg = alt_cal_error[count] | alt_cal_error_reg;
+ end
+
+ if(alt_cal_busy == 1'b0)
+ req_and_use_mutex <= 1'b0;
+ else
+ req_and_use_mutex <= 1'b1;
+
+ case (state)
+ IDLE_STATE:
+ begin
+ offset_cancellation_done <= 1'b0; // reset write/read done flag
+ //reset the signal
+ set_busy <= 1'b0;
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ alt_cal_remap_addr <= 12'h000;
+
+ //al_cal will not assert wren and rden at the same time
+ if((alt_cal_dprio_wren == 1'b1) || (alt_cal_dprio_rden == 1'b1))
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(alt_cal_dprio_wren == 1'b1)
+ write_read_control <= 1'b1; // 1 for write
+ else
+ write_read_control <= 1'b0; // 0 for read
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ else
+ state <= IDLE_STATE;
+ end
+ else if(alt_cal_retain_addr == 1'b1)
+ begin
+ if(mutex_grant == 1'b1)
+ state <= WRITE_DATA_STATE;
+ else
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ state <= IDLE_STATE;
+ end
+ end
+ LOGICAL_ADDRESS_STATE: //sending channel and quad address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h1;
+ master_write_data <= {{21{1'b0}}, alt_cal_quad_addr, alt_cal_dprio_addr[13:12]};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= READ_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ end
+ READ_PHY_ADDR_STATE: //read phsical address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h2;
+ master_read <= 1'b1;
+ master_write <= 1'b0;
+ if (wait_phy_addr_ready == 1'b1)
+ begin
+ wait_phy_addr_ready <= 1'b0;
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ wait_phy_addr_ready <= 1'b1;
+ state <= READ_PHY_ADDR_STATE;
+ //state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_PHY_ADDR_STATE;
+ end
+ end
+ CHECK_PHY_ADDR_STATE: //check physical address correct or not
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ if (master_read_data[9:0] == ILLEGAL_PHYSICAL_CHNL)
+ begin
+ // synopsys translate_off
+ $display ("Illegal physical address: 10'h%h", master_read_data);
+ $display ("Time: %0t Instance: %m", $time);
+ // synopsys translate_on
+ alt_cal_remap_addr <= 12'hfff;
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ alt_cal_remap_addr <= master_read_data[11:0];
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ else
+ begin
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ ADDRESS_OFFSET_STATE: // send address offset to alt_dprio
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h4;
+ master_write_data <= {{17{1'b0}}, alt_cal_dprio_addr[14:0]};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(write_read_control == 1'b1)
+ state <= WRITE_DATA_STATE;
+ else
+ state <= CONTROL_STATE;
+ end
+ else
+ begin
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ WRITE_DATA_STATE:
+ begin
+ master_address <= 3'h5;
+ master_write_data = {{16{1'b0}}, alt_cal_dprio_dataout};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= CONTROL_STATE;
+ end
+ CONTROL_STATE: // sending write/read command
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h3; // get ready to send control command to alt_dprio
+// master_write_data <= {{29{1'b0}}, (~write_read_control), write_read_control};
+ master_write_data <= {{27{1'b0}}, 1'b1, 1'b0, (~write_read_control), write_read_control}; // use absolute addressing
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ state <= BASE_BUSY_STATE;
+ end
+ else
+ begin
+ state <= CONTROL_STATE;
+ end
+ end
+ BASE_BUSY_STATE: // send busy to reconfig_togxb
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h7; // set offset cancellation busy to reconfig_togxb
+ master_write_data <= {{30{1'b0}}, alt_cal_busy};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(set_busy == 1'b0)
+ begin
+ set_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ else
+ begin
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= BASE_BUSY_STATE;
+ end
+ end
+ BUSY_STATE: // wait for write done
+ begin
+ if(offset_cancellation_irq_from_base == 1'b1)
+ begin
+ alt_cal_dprio_busy <= 1'b1;
+ if(write_read_control == 1'b0) //read
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_cal_dprio_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ end
+ WRITE_DONE_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(offset_cancellation_irq_from_base == 1'b1)
+ begin
+ if(alt_cal_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_cal_dprio_busy_int <= master_read_data[8];
+ alt_cal_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ else
+ begin
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ master_address <= 3'h3;
+ master_write_data <= {{16{1'b0}}, {16'h0000}}; //acknowledge write operation
+ alt_cal_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_cal_dprio_busy <= 1'b0;
+ offset_cancellation_done <= 1'b1; // write done
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ READ_DATA_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(offset_cancellation_irq_from_base == 1'b1)
+ begin
+ if(alt_cal_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_cal_dprio_busy_int <= master_read_data[8];
+ alt_cal_dprio_busy <= 1'b1;
+ end
+ else
+ begin
+ master_address <= 3'h5;
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ alt_cal_dprio_busy <= 1'b1;
+ end
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ offset_cancellation_done <= 1'b1; // read done
+ alt_cal_dprio_datain <= master_read_data[15:0];
+ alt_cal_dprio_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_DATA_STATE;
+ end
+ end
+ default:
+ begin
+ state <= IDLE_STATE;
+ end
+ endcase
+ end
+end
+
+
+
+generate
+
+//Deepak Use alt_cal_mm for SIV and AIIGX
+if((device_family=="Stratix IV") || (device_family=="Arria II GX") || (device_family=="Arria II GZ") || (device_family=="HardCopy IV"))
+begin
+ alt_cal_mm #(
+ .number_of_channels (number_of_reconfig_interfaces*4),
+ .channel_address_width (CLogB2(number_of_reconfig_interfaces*4))
+ )alt_cal_inst
+ (
+ .clock(reconfig_clk),
+ .reset(reset),
+ .start(),
+ .busy(alt_cal_busy),
+ .dprio_addr(alt_cal_dprio_addr), // only extract the logical channel address
+ .quad_addr(alt_cal_quad_addr),
+ .dprio_dataout(alt_cal_dprio_dataout),
+ .dprio_datain(alt_cal_dprio_datain),
+ .dprio_wren(alt_cal_dprio_wren),
+ .dprio_rden(alt_cal_dprio_rden),
+ .dprio_busy(alt_cal_dprio_busy),
+ .retain_addr(alt_cal_retain_addr),
+ .remap_addr(alt_cal_remap_addr),
+ .testbuses(alt_cal_testbuses),
+ .cal_error(alt_cal_error)
+ );
+end
+//Deepak: Use alt_cal_c3gxb for Cyclone IV GX
+if(device_family=="Cyclone IV GX")
+begin
+ alt_cal_c3gxb alt_cal_inst
+ (
+ .clock(reconfig_clk),
+ .reset(reset),
+ .start(),
+ .busy(alt_cal_busy),
+ .dprio_addr(alt_cal_dprio_addr), // only extract the logical channel address
+ .quad_addr(alt_cal_quad_addr),
+ .dprio_dataout(alt_cal_dprio_dataout),
+ .dprio_datain(alt_cal_dprio_datain),
+ .dprio_wren(alt_cal_dprio_wren),
+ .dprio_rden(alt_cal_dprio_rden),
+ .dprio_busy(alt_cal_dprio_busy),
+ .retain_addr(alt_cal_retain_addr),
+ .remap_addr(alt_cal_remap_addr),
+ .testbuses(alt_cal_testbuses),
+ .cal_error(alt_cal_error)
+ );
+defparam
+ alt_cal_inst.number_of_channels = number_of_reconfig_interfaces*4,
+ alt_cal_inst.channel_address_width = CLogB2(number_of_reconfig_interfaces*4);
+end
+endgenerate
+
+alt_mutex_acq #(
+ .mutex_wait_time(102), ///Thia: pick a different mutex wait time to avoid collision. Say 102. (since analog is already using 101)
+ .addr_width(5),
+ .data_width(32)
+)
+mutex_inst (
+ .clk(reconfig_clk),
+ .reset(reset),
+// inputs to the base that should be routed through the mutex
+ .address(master_address_shifted),
+ .writedata(master_write_data),
+ .write(master_write),
+ .read(master_read),
+// output from the mutex which is processed form of output from base
+ .waitrequest(),
+ .readdata(master_read_data),
+
+// outputs from mutex to be routed to the base
+ .master_address(offset_cancellation_address_base),
+ .master_writedata(offset_cancellation_writedata_base),
+ .master_write(offset_cancellation_write_base),
+ .master_read(offset_cancellation_read_base),
+
+// these ports are from the base routed to the mutex
+ .master_waitrequest(offset_cancellation_waitrequest_from_base),
+ .master_readdata(offset_cancellation_readdata_base), // from MM
+
+//request signal to the mutex should be kept high as long as the mutex is being used
+ .mutex_req(req_and_use_mutex),
+// output from mutex indicates whether you have mutex or not
+ .mutex_grant(mutex_grant)
+);
+
+//wire assignment
+assign alt_cal_testbuses = testbus_data;
+assign master_address_shifted = {master_address, {2'b00}};
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_siv.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_siv.sv
new file mode 100644
index 0000000000000000000000000000000000000000..727be748a008f29b2f9649fef902f9787b9b1f47
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_reconfig_siv.sv
@@ -0,0 +1,441 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Transceiver Reconfiguration Module for Stratix IV architectures
+//
+// Includes many function-specific sub-modules, such as:
+// - analog reconfig (alt_xcvr_reconfig_analog)
+// - offset cancellation (alt_xcvr_reconfig_offset_cancellation)
+// - ...
+
+// $Header$
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_reconfig_siv #(
+ parameter number_of_reconfig_interfaces = 1
+) (
+ input wire mgmt_clk_clk, // mgmt_clk.clk
+ input wire mgmt_rst_reset, // mgmt_rst.reset
+
+ // user reconfiguration management interface
+ input wire [6:0] reconfig_mgmt_address, // reconfig_mgmt.address
+ output reg reconfig_mgmt_waitrequest = 0, // .waitrequest
+ input wire reconfig_mgmt_read, // .read
+ output reg [31:0] reconfig_mgmt_readdata = ~0, // .readdata
+ input wire reconfig_mgmt_write, // .write
+ input wire [31:0] reconfig_mgmt_writedata, // .writedata
+ output wire reconfig_done, // reconfig_done.export
+
+ output wire [3:0] reconfig_togxb, // reconfig_togxb_data.data
+ input wire [number_of_reconfig_interfaces*17 - 1 : 0] reconfig_fromgxb // dprioout, testbus from altgx : (17+4 bits/quad)
+);
+
+ // master interface to basic reconfiguration block that interfaces to the transceiver channel
+ wire [2:0] basic_address; // basic.address // master interface must include 2 lower addr bits
+ wire basic_waitrequest; // .waitrequest
+ wire basic_irq; // .irq
+ wire basic_read; // .read
+ wire [31:0] basic_readdata; // .readdata
+ wire basic_write; // .write
+ wire [31:0] basic_writedata; // .writedata
+
+ // native testbus input
+ wire [15:0] testbus_data;
+
+ localparam l_dev_family = "Stratix IV";
+ localparam width_awa = 3; // word address width of interface to analog reconfig block
+ localparam width_bwa = 3; // word address width of interface to basic reconfig block
+ localparam arb_count = 4; // count of the total number of sub-components that can act
+ // as slaves to the mgmt interface, and masters to the 'basic' block
+ localparam arb_offset = 0;
+ localparam arb_analog = 1;
+ localparam arb_eyemon = 2;
+ localparam arb_dfe = 3;
+
+ // Analog controls output ports, mgmt facing
+ wire [31:0] sc_analog_readdata;
+ wire sc_analog_waitrequest;
+
+ // Offset cancellation output ports, mgmt facing
+ wire [31:0] sc_offset_readdata;
+ wire sc_offset_waitrequest;
+
+ // Eyemon output ports, mgmt facing
+ wire [31:0] sc_eyemon_readdata;
+ wire sc_eyemon_waitrequest;
+
+ // DFE output ports, mgmt facing
+ wire [31:0] sc_dfe_readdata;
+ wire sc_dfe_waitrequest;
+
+ ///////////////////////////////////////////////////////////////////////
+ // Decoder for multiple slaves of reconfig_mgmt interface
+ ///////////////////////////////////////////////////////////////////////
+ wire [arb_count-1:0] r_decode;
+ assign r_decode =
+ (reconfig_mgmt_address[6:width_awa] == arb_offset) ? (({arb_count-arb_offset{1'b0}} | 1'b1) << arb_offset)
+ : (reconfig_mgmt_address[6:width_awa] == arb_analog) ? (({arb_count-arb_analog{1'b0}} | 1'b1) << arb_analog)
+ : (reconfig_mgmt_address[6:width_awa] == arb_eyemon) ? (({arb_count-arb_eyemon{1'b0}} | 1'b1) << arb_eyemon)
+ : (reconfig_mgmt_address[6:width_awa] == arb_dfe) ? (({arb_count-arb_dfe{1'b0}} | 1'b1) << arb_dfe)
+ : {arb_count{1'b0}};
+
+ // reconfig_mgmt output generation is muxing of decoded slave output
+ always @(*) begin
+ case (reconfig_mgmt_address[6:width_awa])
+ arb_offset: begin
+ reconfig_mgmt_readdata = sc_offset_readdata;
+ reconfig_mgmt_waitrequest = sc_offset_waitrequest;
+ end
+ arb_analog: begin
+ reconfig_mgmt_readdata = sc_analog_readdata;
+ reconfig_mgmt_waitrequest = sc_analog_waitrequest;
+ end
+ arb_eyemon: begin
+ reconfig_mgmt_readdata = sc_eyemon_readdata;
+ reconfig_mgmt_waitrequest = sc_eyemon_waitrequest;
+ end
+ arb_dfe: begin
+ reconfig_mgmt_readdata = sc_dfe_readdata;
+ reconfig_mgmt_waitrequest = sc_dfe_waitrequest;
+ end
+ default: begin
+ reconfig_mgmt_readdata = -1;
+ reconfig_mgmt_waitrequest = 1'b0;
+ end
+ endcase
+ end
+
+ ///////////////////////////////////////////////////////////////////////
+ // Arbiter for multiple masters accessing 'basic' reconfig slave port
+ ///////////////////////////////////////////////////////////////////////
+ wire [arb_count-1:0] req; // req[0] is highest priority when current grantee is done
+ wire [arb_count-1:0] grant;
+
+ alt_xcvr_arbiter #(
+ .width(arb_count) // count total number of sub-components that act as masters to 'basic'
+ ) arbiter (
+ .clock(mgmt_clk_clk),
+ .req(req),
+ .grant(grant)
+ );
+
+ ////////////////////////////////////
+ // Sub-component: analog controls
+ // word address offset: +0
+ ////////////////////////////////////
+
+ // Analog controls output ports, mgmt facing
+ wire analog_reconfig_done;
+ // Analog controls output ports, basic slave facing
+ wire [width_bwa+1:0] scs_analog_address;
+ wire [31:0] scs_analog_writedata;
+ wire scs_analog_write;
+ wire scs_analog_read;
+
+ // Analog controls master-to-slave access fabric outputs
+ tri0 m2s_analog_read;
+ tri0 m2s_analog_write;
+ tri0 [width_bwa-1:0] m2s_analog_address;
+ tri0 [31:0] m2s_analog_writedata;
+ wire [31:0] m2s_analog_readdata;
+ wire m2s_analog_waitrequest;
+
+ alt_xcvr_reconfig_analog_tgx sc_analog (
+ .reconfig_clk(mgmt_clk_clk),
+ .reset(mgmt_rst_reset),
+ // external mgmt interface facing
+ .analog_reconfig_address(reconfig_mgmt_address[width_awa-1:0]),
+ .analog_reconfig_writedata(reconfig_mgmt_writedata),
+ .analog_reconfig_write(reconfig_mgmt_write & r_decode[arb_analog]),
+ .analog_reconfig_read(reconfig_mgmt_read & r_decode[arb_analog]),
+ .analog_reconfig_readdata(sc_analog_readdata),
+ .analog_reconfig_waitrequest(sc_analog_waitrequest),
+ .analog_reconfig_done(analog_reconfig_done),
+ // master-to-slave fabric facing, to basic reconfig
+ .analog_reconfig_irq_from_base(basic_irq),
+ .analog_reconfig_waitrequest_from_base(m2s_analog_waitrequest),
+ .analog_reconfig_readdata_base(m2s_analog_readdata),
+ .analog_reconfig_address_base(scs_analog_address),
+ .analog_reconfig_writedata_base(scs_analog_writedata),
+ .analog_reconfig_write_base(scs_analog_write),
+ .analog_reconfig_read_base(scs_analog_read)
+ );
+
+ // master-to-slave access module
+ alt_xcvr_m2s #(
+ .width_addr(width_bwa),
+ .width_data(32)
+ ) m2s_analog (
+ .clock(mgmt_clk_clk),
+ .req(req[arb_analog]),
+ .grant(grant[arb_analog]),
+ // master ports, facing basic reconfig block
+ .m_read(scs_analog_read),
+ .m_write(scs_analog_write),
+ .m_address(scs_analog_address[2 +: width_bwa]), // drop 2 lower addr bits
+ .m_writedata(scs_analog_writedata),
+ .m_readdata(m2s_analog_readdata),
+ .m_waitrequest(m2s_analog_waitrequest),
+ // slave-side ports, from basic reconfig block
+ .s_readdata(basic_readdata),
+ .s_waitrequest(basic_waitrequest),
+ .s_read(m2s_analog_read),
+ .s_write(m2s_analog_write),
+ .s_address(m2s_analog_address),
+ .s_writedata(m2s_analog_writedata)
+ );
+
+ ///////////////////////////////////////////
+ // Sub-component: offset cancellation
+ // word address offset: +8 (0x20 in bytes)
+ ///////////////////////////////////////////
+
+ // Offset cancellation output ports:
+ wire offset_cancellation_done;
+ wire [width_bwa-1:0] scs_offset_address;
+ wire [31:0] scs_offset_writedata;
+ wire scs_offset_write;
+ wire scs_offset_read;
+
+ // Offset cancellation master-to-slave access fabric outputs
+ tri0 m2s_offset_read;
+ tri0 m2s_offset_write;
+ tri0 [width_bwa-1:0] m2s_offset_address;
+ tri0 [31:0] m2s_offset_writedata;
+ wire [31:0] m2s_offset_readdata;
+ wire m2s_offset_waitrequest;
+
+ alt_xcvr_reconfig_offset_cancellation #(
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces),
+ .device_family(l_dev_family)
+ ) sc_offset (
+ .reconfig_clk(mgmt_clk_clk),
+ .reset(mgmt_rst_reset),
+ // external mgmt interface facing
+ .offset_cancellation_address(reconfig_mgmt_address[0]), // slave uses a single address bit
+ .offset_cancellation_writedata(reconfig_mgmt_writedata),
+ .offset_cancellation_write(reconfig_mgmt_write & r_decode[arb_offset]),
+ .offset_cancellation_read(reconfig_mgmt_read & r_decode[arb_offset]),
+ .offset_cancellation_readdata(sc_offset_readdata),
+ .offset_cancellation_waitrequest(sc_offset_waitrequest),
+ // master-to-slave fabric facing, to basic reconfig
+ .offset_cancellation_irq_from_base(basic_irq),
+ .offset_cancellation_waitrequest_from_base(m2s_offset_waitrequest),
+ .offset_cancellation_readdata_base(m2s_offset_readdata),
+ .testbus_data(testbus_data),
+ .offset_cancellation_done(offset_cancellation_done),
+ .offset_cancellation_address_base(scs_offset_address),
+ .offset_cancellation_writedata_base(scs_offset_writedata),
+ .offset_cancellation_write_base(scs_offset_write),
+ .offset_cancellation_read_base(scs_offset_read)
+ );
+
+ // master-to-slave access module
+ alt_xcvr_m2s #(
+ .width_addr(width_bwa),
+ .width_data(32)
+ ) m2s_offset (
+ .clock(mgmt_clk_clk),
+ .req(req[arb_offset]),
+ .grant(grant[arb_offset]),
+ // master ports, facing basic reconfig block
+ .m_read(scs_offset_read),
+ .m_write(scs_offset_write),
+ .m_address(scs_offset_address), // drop 2 lower addr bits
+ .m_writedata(scs_offset_writedata),
+ .m_readdata(m2s_offset_readdata),
+ .m_waitrequest(m2s_offset_waitrequest),
+ // slave-side ports, from basic reconfig block
+ .s_readdata(basic_readdata),
+ .s_waitrequest(basic_waitrequest),
+ .s_read(m2s_offset_read),
+ .s_write(m2s_offset_write),
+ .s_address(m2s_offset_address),
+ .s_writedata(m2s_offset_writedata)
+ );
+
+ ///////////////////////////////////////////
+ // Sub-component: "EyeQ" eye monitor
+ // word address offset: +16 (0x40 in bytes)
+ ///////////////////////////////////////////
+
+ // Eyemon output ports:
+ wire eyemon_done;
+ wire [width_bwa+1:0] scs_eyemon_address;
+ wire [31:0] scs_eyemon_writedata;
+ wire scs_eyemon_write;
+ wire scs_eyemon_read;
+
+ // eyemon master-to-slave access fabric outputs
+ tri0 m2s_eyemon_read;
+ tri0 m2s_eyemon_write;
+ tri0 [width_bwa-1:0] m2s_eyemon_address;
+ tri0 [31:0] m2s_eyemon_writedata;
+ wire [31:0] m2s_eyemon_readdata;
+ wire m2s_eyemon_waitrequest;
+
+ alt_xcvr_reconfig_eyemon_tgx #(
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces),
+ .device_family(l_dev_family)
+ ) sc_eyemon (
+ .reconfig_clk(mgmt_clk_clk),
+ .reset(mgmt_rst_reset),
+ // external mgmt interface facing
+ .eyemon_address(reconfig_mgmt_address[width_awa-1:0]), // slave uses a 3-bit address
+ .eyemon_writedata(reconfig_mgmt_writedata),
+ .eyemon_write(reconfig_mgmt_write & r_decode[arb_eyemon]),
+ .eyemon_read(reconfig_mgmt_read & r_decode[arb_eyemon]),
+ .eyemon_readdata(sc_eyemon_readdata),
+ .eyemon_waitrequest(sc_eyemon_waitrequest),
+ // master-to-slave fabric facing, to basic reconfig
+ .eyemon_irq_from_base(basic_irq),
+ .eyemon_waitrequest_from_base(m2s_eyemon_waitrequest),
+ .eyemon_readdata_base(m2s_eyemon_readdata),
+ .eyemon_irq(eyemon_done),
+ .eyemon_address_base(scs_eyemon_address),
+ .eyemon_writedata_base(scs_eyemon_writedata),
+ .eyemon_write_base(scs_eyemon_write),
+ .eyemon_read_base(scs_eyemon_read)
+ );
+
+ // master-to-slave access module
+ alt_xcvr_m2s #(
+ .width_addr(width_bwa),
+ .width_data(32)
+ ) m2s_eyemon (
+ .clock(mgmt_clk_clk),
+ .req(req[arb_eyemon]),
+ .grant(grant[arb_eyemon]),
+ // master ports, facing basic reconfig block
+ .m_read(scs_eyemon_read),
+ .m_write(scs_eyemon_write),
+ .m_address(scs_eyemon_address[2 +: width_bwa]), // drop 2 lower addr bits
+ .m_writedata(scs_eyemon_writedata),
+ .m_readdata(m2s_eyemon_readdata),
+ .m_waitrequest(m2s_eyemon_waitrequest),
+ // slave-side ports, from basic reconfig block
+ .s_readdata(basic_readdata),
+ .s_waitrequest(basic_waitrequest),
+ .s_read(m2s_eyemon_read),
+ .s_write(m2s_eyemon_write),
+ .s_address(m2s_eyemon_address),
+ .s_writedata(m2s_eyemon_writedata)
+ );
+
+ ///////////////////////////////////////////
+ // Sub-component: DFE
+ // word address offset: +24 (0x60 in bytes)
+ ///////////////////////////////////////////
+
+ // DFE output ports:
+ wire dfe_done;
+ wire [width_bwa-1:0] scs_dfe_address;
+ wire [31:0] scs_dfe_writedata;
+ wire scs_dfe_write;
+ wire scs_dfe_read;
+
+ // dfe master-to-slave access fabric outputs
+ tri0 m2s_dfe_read;
+ tri0 m2s_dfe_write;
+ tri0 [width_bwa-1:0] m2s_dfe_address;
+ tri0 [31:0] m2s_dfe_writedata;
+ wire [31:0] m2s_dfe_readdata;
+ wire m2s_dfe_waitrequest;
+
+ alt_xcvr_reconfig_dfe_tgx #(
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces),
+ .device_family(l_dev_family)
+ ) sc_dfe (
+ .reconfig_clk(mgmt_clk_clk),
+ .reset(mgmt_rst_reset),
+ // external mgmt interface facing
+ .dfe_address(reconfig_mgmt_address[width_awa-1:0]), // slave uses a 3-bit address
+ .dfe_writedata(reconfig_mgmt_writedata),
+ .dfe_write(reconfig_mgmt_write & r_decode[arb_dfe]),
+ .dfe_read(reconfig_mgmt_read & r_decode[arb_dfe]),
+ .dfe_readdata(sc_dfe_readdata),
+ .dfe_waitrequest(sc_dfe_waitrequest),
+ // master-to-slave fabric facing, to basic reconfig
+ .dfe_irq_from_base(basic_irq),
+ .dfe_waitrequest_from_base(m2s_dfe_waitrequest),
+ .dfe_readdata_base(m2s_dfe_readdata),
+ .dfe_irq(dfe_done),
+ .dfe_address_base(scs_dfe_address),
+ .dfe_writedata_base(scs_dfe_writedata),
+ .dfe_write_base(scs_dfe_write),
+ .dfe_read_base(scs_dfe_read)
+ );
+
+ // master-to-slave access module
+ alt_xcvr_m2s #(
+ .width_addr(width_bwa),
+ .width_data(32)
+ ) m2s_dfe (
+ .clock(mgmt_clk_clk),
+ .req(req[arb_dfe]),
+ .grant(grant[arb_dfe]),
+ // master ports, facing basic reconfig block
+ .m_read(scs_dfe_read),
+ .m_write(scs_dfe_write),
+ .m_address(scs_dfe_address),
+ .m_writedata(scs_dfe_writedata),
+ .m_readdata(m2s_dfe_readdata),
+ .m_waitrequest(m2s_dfe_waitrequest),
+ // slave-side ports, from basic reconfig block
+ .s_readdata(basic_readdata),
+ .s_waitrequest(basic_waitrequest),
+ .s_read(m2s_dfe_read),
+ .s_write(m2s_dfe_write),
+ .s_address(m2s_dfe_address),
+ .s_writedata(m2s_dfe_writedata)
+ );
+
+
+ ///////////////////////////////////////////
+ // Outputs to basic block
+ ///////////////////////////////////////////
+ assign basic_address = m2s_analog_address | m2s_offset_address | m2s_eyemon_address | m2s_dfe_address;
+ assign basic_read = m2s_analog_read | m2s_offset_read | m2s_eyemon_read | m2s_dfe_read;
+ assign basic_write = m2s_analog_write | m2s_offset_write | m2s_eyemon_write | m2s_dfe_write;
+ assign basic_writedata = m2s_analog_writedata | m2s_offset_writedata | m2s_eyemon_writedata | m2s_dfe_writedata;
+
+ wire [number_of_reconfig_interfaces*8 - 1 : 0] aeq_fromgxb_data=0;
+ wire [number_of_reconfig_interfaces*24 - 1 : 0] aeq_togxb_data;
+
+ alt_xcvr_reconfig_basic_tgx #(
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces)
+ ) sc_basic (
+ .reconfig_clk(mgmt_clk_clk),
+ .reset(mgmt_rst_reset),
+ .basic_reconfig_write(basic_write),
+ .basic_reconfig_read(basic_read),
+ .basic_reconfig_writedata(basic_writedata),
+ .basic_reconfig_address(basic_address),
+ .basic_reconfig_fromgxb_data(reconfig_fromgxb),
+ .aeq_fromgxb_data(aeq_fromgxb_data),
+ .basic_reconfig_readdata(basic_readdata),
+ .basic_reconfig_waitrequest(basic_waitrequest),
+ .basic_reconfig_togxb_data(reconfig_togxb),
+ .aeq_togxb_data(aeq_togxb_data),
+ .testbus_data(testbus_data),
+ .basic_reconfig_irq(basic_irq)
+ );
+
+
+ ///////////////////////////////////////////
+ // Status to external mgmt interface
+ ///////////////////////////////////////////
+ assign reconfig_done = analog_reconfig_done | offset_cancellation_done | eyemon_done | dfe_done;
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_resync.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_resync.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5c723372b22da2640f7283962c5acdd598a91dfa
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/alt_xcvr_resync.sv
@@ -0,0 +1,98 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Module: alt_xcvr_resync
+//
+// Description:
+// A general purpose resynchronization module.
+//
+// Parameters:
+// SYNC_CHAIN_LENGTH
+// - Specifies the length of the synchronizer chain for metastability
+// retiming.
+// WIDTH
+// - Specifies the number of bits you want to synchronize. Controls the width of the
+// d and q ports.
+// SLOW_CLOCK - USE WITH CAUTION.
+// - Leaving this setting at its default will create a standard resynch circuit that
+// merely passes the input data through a chain of flip-flops. This setting assumes
+// that the input data has a pulse width longer than one clock cycle sufficient to
+// satisfy setup and hold requirements on at least one clock edge.
+// - By setting this to 1 (USE CAUTION) you are creating an asynchronous
+// circuit that will capture the input data regardless of the pulse width and
+// its relationship to the clock. However it is more difficult to apply static
+// timing constraints as it ties the data input to the clock input of the flop.
+// This implementation assumes the data rate is slow enough
+// INIT_VALUE
+// - Specifies the initial values of the synchronization registers.
+//
+// Apply embedded false path timing constraint
+(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_resync*sync_r[0]]\"" *)
+
+`timescale 1ps/1ps
+
+module alt_xcvr_resync #(
+ parameter SYNC_CHAIN_LENGTH = 2, // Number of flip-flops for retiming
+ parameter WIDTH = 1, // Number of bits to resync
+ parameter SLOW_CLOCK = 0, // See description above
+ parameter INIT_VALUE = 0
+ ) (
+ input wire clk,
+ input wire reset,
+ input wire [WIDTH-1:0] d,
+ output wire [WIDTH-1:0] q
+ );
+
+localparam INT_LEN = (SYNC_CHAIN_LENGTH > 0) ? SYNC_CHAIN_LENGTH : 1;
+localparam [INT_LEN-1:0] L_INIT_VALUE = (INIT_VALUE == 1) ? {INT_LEN{1'b1}} : {INT_LEN{1'b0}};
+
+genvar ig;
+
+// Generate a synchronizer chain for each bit
+generate begin
+ for(ig=0;ig<WIDTH;ig=ig+1) begin : resync_chains
+ wire d_in; // Input to sychronization chain.
+ reg [INT_LEN-1:0] sync_r = L_INIT_VALUE;
+ wire [INT_LEN :0] next_r; // One larger than real chain
+
+ assign q[ig] = sync_r[INT_LEN-1]; // Output signal
+ assign next_r = {sync_r,d_in};
+
+ always @(posedge clk or posedge reset)
+ if(reset)
+ sync_r <= L_INIT_VALUE;
+ else
+ sync_r <= next_r[INT_LEN-1:0];
+
+ // Generate asynchronous capture circuit if specified.
+ if(SLOW_CLOCK == 0) begin
+ assign d_in = d[ig];
+ end else begin
+ wire d_clk;
+ reg d_r = L_INIT_VALUE[0];
+ wire clr_n;
+
+ assign d_clk = d[ig];
+ assign d_in = d_r;
+ assign clr_n = ~q[ig] | d_clk; // Clear when output is logic 1 and input is logic 0
+
+ // Asynchronously latch the input signal.
+ always @(posedge d_clk or negedge clr_n)
+ if(!clr_n) d_r <= 1'b0;
+ else if(d_clk) d_r <= 1'b1;
+ end // SLOW_CLOCK
+ end // for loop
+end // generate
+endgenerate
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/altera_wait_generate.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/altera_wait_generate.v
new file mode 100644
index 0000000000000000000000000000000000000000..d11ec7e154387185d9a1d14b39c0410608a6c6ed
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/altera_wait_generate.v
@@ -0,0 +1,38 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module altera_wait_generate
+//#(
+//This code only works when wait_cycle =1, if need other case, you need to modify this code.
+//please set wait_cycle default value as 1 to keep old design works.
+// parameter wait_cycle =1
+// )
+(
+ input wire rst,
+ input wire clk,
+ input wire launch_signal,
+ output wire wait_req
+ );
+reg launch_reg = 0;
+reg wait_reg = 0;
+always @ (posedge clk, posedge rst) begin
+ if(rst) launch_reg <= 1'b0;
+ else launch_reg <= launch_signal;
+end
+always @ (posedge clk, posedge rst) begin
+ if(rst) wait_reg <= 1'b0;
+ else wait_reg <= launch_signal & launch_reg & (! wait_reg & !wait_req);
+end
+assign wait_req = (launch_signal & ~launch_reg) | (wait_reg & launch_signal ) ;
+endmodule
\ No newline at end of file
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/altera_xcvr_functions.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/altera_xcvr_functions.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5ef175a54cc3ce30e9dded8e494731600eb6ffda
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/altera_xcvr_functions.sv
@@ -0,0 +1,746 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common functions for transceiver PHY IP
+//
+// $Header$
+//
+// PACKAGE DECLARATION
+package altera_xcvr_functions;
+ localparam integer MAX_CHARS = 32;
+ localparam integer MAX_STRS = 16;
+ localparam integer MAX_XCVR_CHANNELS = 64;
+
+ // Reconfiguration bundle widths per family
+ localparam integer W_S5_RECONFIG_BUNDLE_TO_XCVR = 70;
+ localparam integer W_S5_RECONFIG_BUNDLE_FROM_XCVR = 46;
+ localparam integer W_A5_RECONFIG_BUNDLE_TO_XCVR = 70;
+ localparam integer W_A5_RECONFIG_BUNDLE_FROM_XCVR = 46;
+ localparam integer W_S4_RECONFIG_BUNDLE_TO_XCVR = 4;
+ localparam integer W_S4_RECONFIG_BUNDLE_FROM_XCVR = 17;
+ localparam integer W_C4_RECONFIG_BUNDLE_TO_XCVR = 4;
+ localparam integer W_C4_RECONFIG_BUNDLE_FROM_XCVR = 17;
+
+ // Reconfiguration bundle widths per family
+ localparam integer W_S5_RECONFIG_BUNDLE_TO_GXB = W_S5_RECONFIG_BUNDLE_TO_XCVR;
+ localparam integer W_S5_RECONFIG_BUNDLE_FROM_GXB = W_S5_RECONFIG_BUNDLE_FROM_XCVR;
+ localparam integer W_A5_RECONFIG_BUNDLE_TO_GXB = W_A5_RECONFIG_BUNDLE_TO_XCVR;
+ localparam integer W_A5_RECONFIG_BUNDLE_FROM_GXB = W_A5_RECONFIG_BUNDLE_FROM_XCVR;
+ localparam integer W_S4_RECONFIG_BUNDLE_TO_GXB = W_S4_RECONFIG_BUNDLE_TO_XCVR;
+ localparam integer W_S4_RECONFIG_BUNDLE_FROM_GXB = W_S4_RECONFIG_BUNDLE_FROM_XCVR;
+ localparam integer W_C4_RECONFIG_BUNDLE_TO_GXB = W_C4_RECONFIG_BUNDLE_TO_XCVR;
+ localparam integer W_C4_RECONFIG_BUNDLE_FROM_GXB = W_C4_RECONFIG_BUNDLE_FROM_XCVR;
+
+ // convert frequency string into integer Hz. Fractional Hz are truncated
+ // Must remain a constant function - can't use string.atoi().
+ function time str2hz (
+ input [8*MAX_CHARS:1] s
+ );
+
+ integer i;
+ integer c; // temp char storage for frequency conversion
+ integer unit_tens; // assume already Hz
+ integer is_numeric;
+ integer saw_dot;
+
+ reg [8:1] c_dot; // = ".";
+ reg [8:1] c_space; // = " ";
+ reg [8:1] c_a; // = 8'h61; //"a";
+ reg [8:1] c_z; // = 8'h7a; //"z";
+ reg [8*4:1] s_unit;
+ reg [8*MAX_CHARS:1] s_shift;
+
+ begin
+ // frequency ratio calculations
+ str2hz = 0;
+ unit_tens = 0; // assume already Hz
+ is_numeric = 1;
+ saw_dot = 0;
+ s_unit = "";
+
+ // Modelsim optimizer bug forces us to initialize these non-statically
+ c_dot = ".";
+ c_space = " ";
+ c_a = "a";
+ c_z = "z";
+ for (i=(MAX_CHARS-1); i>=0; i=i-1) begin
+ s_shift = (s >> (i*8));
+ c = s_shift[8:1] & 8'hff;
+ if (c > 0) begin
+ //$display("[%d] => '%1s',", i, c);
+ if (c >= 8'h30 && c <= 8'h39 && is_numeric) begin
+ str2hz = (str2hz * 10) + (c & 8'h0f);
+ if (saw_dot) unit_tens = unit_tens - 1; // count digits after decimal point
+ end else if (c == c_dot) saw_dot = 1;
+ else if (c != c_space) begin
+ is_numeric = 0; // stop accepting new numeric digits in value
+ // if it's a-z, convert to upper case A-Z
+ if (c >= c_a && c <= c_z) c = (c & 8'h5f); // convert a-z (lower) to A-Z (upper)
+ s_unit = (s_unit << 8) | c;
+ end
+ end
+ end
+ //$display("numeric = %d x 10**(%2d), unit = '%0s'", str2hz, unit_tens, s_unit);
+
+ // account for frequency unit
+ if (s_unit == "GHZ" || s_unit == "GBPS") unit_tens = unit_tens + 9; // 10**9
+ else if (s_unit == "MHZ" || s_unit == "MBPS") unit_tens = unit_tens + 6; // 10**6
+ else if (s_unit == "KHZ" || s_unit == "KBPS") unit_tens = unit_tens + 3; // 10**3
+ else if (s_unit != "HZ" && s_unit != "BPS") begin
+ $display("Invalid frequency unit '%0s', assuming %d x 10**(%2d) 'Hz'", s_unit, str2hz, unit_tens);
+ end
+ //$display("numeric in Hz = %d x 10**(%2d)", str2hz, unit_tens);
+
+ // align numeric to Hz
+ if (unit_tens < 0) begin
+ //str2hz = str2hz / (10**(-unit_tens));
+ for (i=0; i>unit_tens; i=i-1) begin
+ str2hz = str2hz / 10;
+ end
+ end else begin
+ //str2hz = str2hz * (10**unit_tens);
+ for (i=0; i<unit_tens; i=i+1) begin
+ str2hz = str2hz * 10;
+ end
+ end
+ //$display("%d Hz", str2hz);
+ end
+ endfunction
+
+ // convert integer Hz to a frequency string
+ // integer Hz as type time, and the frequency string will use MHz units
+ // Must remain a constant function - can't use $sformat or string.itoa().
+ function [MAX_CHARS*8-1:0] hz2str (
+ input time hz
+ );
+ integer pos;
+ integer f_unit; // 10**f_unit is offset from Hz for larger unit
+ time hz_mod_10;
+ begin
+ hz2str = "0.000000 MHz"; // minimum string value
+ f_unit = 6; // MHz offsets Hz value by 6 decimal digits
+
+ // convert time back to string with frequency units
+ // char positions 3 to 0 are used by " MHz", so start with digits at pos 4
+ for (pos = 4; pos < MAX_CHARS && hz > 0; pos = pos + 1) begin
+ if (f_unit == 0) begin
+ hz2str[pos*8 +: 8] = 8'h2e; // add "." character
+ pos = pos + 1;
+ end
+ f_unit = f_unit - 1;
+ hz_mod_10 = (hz % 10);
+ hz2str[pos*8 +: 8] = hz_mod_10[7:0] | 8'h30;
+ hz = hz / 10;
+ //$display("hz2str() => so far '%s', pos (%d), f_unit(%d) ", hz2str, pos, f_unit);
+ end
+ //$display("hz2str() returns '%s'", hz2str);
+ end
+ endfunction
+
+ // Convert a string to an integer
+ // Uses pre-existing str2hz function
+ function integer str2int(
+ input [MAX_CHARS*8-1:0] instring
+ );
+ time temp;
+ temp = str2hz({instring,"Hz"});
+ str2int = temp[31:0];
+ endfunction
+
+
+ // Convert an integer to a string
+ function [MAX_CHARS*8-1:0] int2str(
+ input integer in_int
+ );
+ integer i;
+ integer this_char;
+ i = 0;
+ int2str = "";
+ do
+ begin
+ this_char = (in_int % 10) + 48;
+ int2str[i*8+:8] = this_char[7:0];
+ i=i+1;
+ in_int = in_int / 10;
+ end
+ while(in_int > 0);
+ endfunction
+
+ // function to convert at most 40-bit long string to binary
+ function [39 : 0] m_str_to_bin;
+ input [40*8 : 1] s;
+ reg [40*8 : 1] reg_s;
+ reg [40:1] res;
+
+ integer m;
+ begin
+
+ reg_s = s;
+ for (m = 40; m > 0; m = m-1 )
+ begin
+ res[m] = reg_s[313];
+ reg_s = reg_s << 8;
+ end
+
+ m_str_to_bin = res;
+ end
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Verify that the string value is contained in the legal set.
+ //
+ // The 'set' can consist of a single string with no delimiters, e.g. "individual",
+ // or multiple values, separated by commas, and surrounded by parens, e.g. "(one,two,three,four,five)"
+ //
+ // Returns 1 if the value is in the set, and 0 otherwise
+ function integer is_in_legal_set(
+ input [MAX_CHARS*8-1:0] value,
+ input [MAX_STRS*MAX_CHARS*8-1:0] set
+ );
+ if (value == "<auto_any>")
+ is_in_legal_set = 1;
+ else if (value == "<auto_single>")
+ is_in_legal_set = (set[7:0] == 8'h29) ? 0 : 1; // 8'h29 is closing parenthesis char
+ else if (value == set)
+ is_in_legal_set = 1; // value matches single value in set
+ else begin
+ // check value against each in set
+ integer close_pos; // end of string marker can be comma or closing paren
+ integer open_pos; // open paren is start of set, if appropriate
+ reg [MAX_STRS*MAX_CHARS*8-1:0] legalstr;
+
+ is_in_legal_set = 0;
+ open_pos = MAX_STRS*MAX_CHARS-1;
+ // Remove closing parenthesis if exists
+ if(set[7:0] == 8'h29) begin
+ set = (set >> 8);
+ set[(MAX_STRS*MAX_CHARS*8-1)-:8] = 8'h00;
+ end
+ // look for first non-null and non open paren character
+ while (open_pos > 0 && (set[open_pos*8 +: 8] == 8'h00 || set[open_pos*8 +: 8] == 8'h28)) // look for first non-null
+ open_pos = open_pos - 1;
+
+ while (is_in_legal_set == 0 && open_pos >= 0) begin
+ close_pos = open_pos;
+ while (close_pos > 0
+ && set[close_pos*8 +: 8] != 8'h2c) // look for comma (8'h2c)
+ close_pos = close_pos - 1;
+ if (close_pos >= 0) begin
+ close_pos = close_pos == 0 ? 0 : close_pos + 1;
+ legalstr = ((set & ((1'b1 << open_pos*8+8)-1)) >> close_pos*8);
+ if (value == legalstr)
+ is_in_legal_set = 1;
+ end
+ open_pos = close_pos-2; // prepare to look for next legal string
+ end
+ end
+ //$display("is_in_legal_set(): returns %d", is_in_legal_set);
+ endfunction
+
+
+ // Accepts a string list of comma seperated numbers and returns a binary
+ // field where each bit indicates whether the index corresponding to that bit
+ // was found in the legal set.
+ //
+ // @param count - The number of integer indexes to check for in the set
+ // or the highest integer minus 1.
+ // @param set - The list containing the integer values to search for
+ // @return - A bitfield where each bit indicates whether the corresponding
+ // integer was found in the legal set.
+ function [MAX_XCVR_CHANNELS-1:0] map_numerical_is_in_legal_set(
+ input integer count,
+ input [MAX_STRS*MAX_CHARS*8-1:0] set
+ );
+ integer index;
+ reg [MAX_XCVR_CHANNELS-1:0] retval;
+
+ // Validate count parameter
+ if(count > MAX_XCVR_CHANNELS)
+ $display("Error: [map_numerical_is_in_legal_set]: Invalid value for count: %0d",count);
+
+ map_numerical_is_in_legal_set = {MAX_XCVR_CHANNELS{1'b0}};
+ retval = {MAX_XCVR_CHANNELS{1'b0}};
+ for(index = 0; index < count; index = index + 1) begin
+ if(is_in_legal_set(int2str(index),set))
+ retval = retval | (({MAX_XCVR_CHANNELS{1'b0}} | 1'b1) << index);
+ end
+ map_numerical_is_in_legal_set = retval;
+ endfunction
+
+
+ // Accepts a string list of comma seperated numbers and returns a binary
+ // field where each byte contains the corresponding number found in the
+ // list.
+ //
+ // @param count - The number of elements in the list.
+ // @param set - The list containing the integer values.
+ // @return - A bitfield where each byte contains the corresponding number found
+ // at that location in the list.
+ function [MAX_XCVR_CHANNELS*8-1:0] map_numerical_legal_set(
+ input integer count,
+ input [MAX_STRS*MAX_CHARS*8-1:0] set
+ );
+ integer index;
+ reg [MAX_XCVR_CHANNELS-1:0] retval;
+ reg [MAX_CHARS*8-1:0] str_val;
+ reg [7:0] int_val;
+
+ // Validate count parameter
+ if(count > MAX_XCVR_CHANNELS || count > 256)
+ $display("Error: [map_numerical_legal_set]: Invalid value for count: %0d",count);
+
+ map_numerical_legal_set = {MAX_XCVR_CHANNELS{8'd0}};
+ retval = {MAX_XCVR_CHANNELS{8'd0}};
+ for(index = 0; index < count; index = index + 1) begin
+ str_val = get_value_at_index(index,set);
+ if(str_val != "NA") begin
+ int_val = str2int(str_val);
+ if(int_val > 255)
+ $display("Error: [map_numerical_legal_set]: Invalid string contains non-numerical item or value:%0d",int_val);
+ else begin
+ retval = retval | ( ( {MAX_XCVR_CHANNELS{8'd0}} | int_val ) << (index * 8));
+ end
+ end
+ end
+ map_numerical_legal_set = retval;
+ endfunction
+
+
+ // Accepts a comma separated list of string values and returns the element
+ // found at the specified index. If the index is invalid, "NA" is returned
+ //
+ // @param index - The index of the value to return within "set"
+ // @param set - A comma separated list of string values. The entire list may
+ // be surrounded by parenthesis("(item0,item1,item2)")
+ function [MAX_CHARS*8-1:0] get_value_at_index(
+ input integer index,
+ input [MAX_STRS*MAX_CHARS*8-1:0] set
+ );
+ // check value against each in set
+ integer close_pos; // end of string marker can be comma or closing paren
+ integer open_pos; // open paren is start of set, if appropriate
+ reg [MAX_STRS*MAX_CHARS*8-1:0] legalstr;
+ integer cur_index = 0;
+
+ get_value_at_index = "";
+ legalstr = "NA";
+ cur_index = 0;
+ open_pos = MAX_STRS*MAX_CHARS-1;
+ // Remove closing parenthesis if exists
+ if(set[7:0] == 8'h29) begin
+ set = (set >> 8);
+ set[(MAX_STRS*MAX_CHARS*8-1)-:8] = 8'h00;
+ end
+ // Find the start of the string
+ while (open_pos >= 1 && (set[open_pos*8 +: 8] == 8'h00 || set[open_pos*8 +: 8] == 8'h28)) // look for first non-null
+ open_pos = open_pos - 1;
+
+ // Iterate through list until the string is found or we've reached the end of the list
+ while (legalstr == "NA" && open_pos >= 0 && cur_index <= index) begin
+ close_pos = open_pos;
+ // Move the close iterator to the end of the current value (or end of string)
+ while (close_pos > 0
+ && set[close_pos*8 +: 8] != 8'h2c) // look for comma (8'h2c)
+ close_pos = close_pos - 1;
+ if (close_pos >= 0) begin
+ close_pos = close_pos == 0 ? 0 : close_pos + 1;
+ if(index == cur_index) begin
+ legalstr = ((set & ((1'b1 << open_pos*8+8)-1)) >> close_pos*8);
+ end
+ open_pos = close_pos-2; // prepare to look for next legal string
+ end
+ cur_index = cur_index + 1;
+ end
+
+ cur_index = 0;
+ while(legalstr[cur_index*8+:8] != 0) begin
+ get_value_at_index[cur_index*8+:8] = legalstr[cur_index*8+:8];
+ cur_index = cur_index + 1;
+ end
+
+ //$display("is_in_legal_set(): returns %d", is_in_legal_set);
+ endfunction
+
+
+ ////////////////////////////////////////////////////////////////////////
+ // Calculate the minimum number of bits needed to hold an integer value
+ //
+ // Returns ceil_log2() value
+ localparam integer MAX_PRECISION = 32; // VCS requires this declaration outside the function
+ function integer ceil_log2;
+ input [MAX_PRECISION-1:0] input_num;
+ integer i;
+ reg [MAX_PRECISION-1:0] try_result;
+ begin
+ i = 0;
+ try_result = 1;
+ while ((try_result << i) < input_num && i < MAX_PRECISION)
+ i = i + 1;
+ ceil_log2 = i;
+ end
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Return current device family string for display purposes
+ `ifndef XCVR_DEV_FAM
+ `ifdef ALTERA_RESERVED_QIS_FAMILY
+ `define XCVR_DEV_FAM `ALTERA_RESERVED_QIS_FAMILY // synthesis: use QIS-defined value
+ `else
+ `define XCVR_DEV_FAM device_family // simulation: use passed-in value
+ `endif
+ `endif
+ function [MAX_CHARS*8-1:0] current_device_family (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ current_device_family = `XCVR_DEV_FAM;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Match device family against standard family name strings
+ //
+ // Returns 1 if the names feature is present in the given device family
+ function integer has_s4_style_hssi (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ has_s4_style_hssi = ( (`XCVR_DEV_FAM == "Stratix IV")
+ || (`XCVR_DEV_FAM == "Arria II")
+ || (`XCVR_DEV_FAM == "Cyclone IV GX") // not exact, but close enough
+ || (`XCVR_DEV_FAM == "Arria II GX")
+ || (`XCVR_DEV_FAM == "Arria II GZ")
+ || (`XCVR_DEV_FAM == "HardCopy IV")
+ ) ? 1 : 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Match device family against standard family name strings
+ //
+ // Returns 1 if the names feature is present in the given device family
+ function integer has_s5_style_hssi (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ has_s5_style_hssi = ( (`XCVR_DEV_FAM == "Stratix V")
+ ) ? 1 : 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Match device family against standard family name strings
+ //
+ // Returns 1 if the names feature is present in the given device family
+ function integer has_a5_style_hssi (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ has_a5_style_hssi = ( (`XCVR_DEV_FAM == "Arria V")
+ ) ? 1 : 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Match device family against standard family name strings
+ //
+ // Returns 1 if the names feature is present in the given device family
+ function integer has_c5_style_hssi (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ has_c5_style_hssi = ( (`XCVR_DEV_FAM == "Cyclone V")
+ ) ? 1 : 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Match device family against standard family name strings
+ //
+ // Returns 1 if the names feature is present in the given device family
+ function integer has_c4_style_hssi (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ has_c4_style_hssi = ( (`XCVR_DEV_FAM == "Cyclone IV GX")
+ ) ? 1 : 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_to_gxb bundle width for specified device family
+ //
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_to_gxb bundle for that family
+ function integer get_reconfig_to_gxb_width (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family))
+ get_reconfig_to_gxb_width = W_S5_RECONFIG_BUNDLE_TO_XCVR;
+ else if (has_s4_style_hssi(device_family))
+ get_reconfig_to_gxb_width = W_S4_RECONFIG_BUNDLE_TO_XCVR;
+ else if (has_c4_style_hssi(device_family))
+ get_reconfig_to_gxb_width = W_C4_RECONFIG_BUNDLE_TO_XCVR;
+ else
+ get_reconfig_to_gxb_width = 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_from_gxb bundle width for specified device family
+ //
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_gxb bundle for that family
+ function integer get_reconfig_from_gxb_width (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family))
+ get_reconfig_from_gxb_width = W_S5_RECONFIG_BUNDLE_FROM_XCVR;
+ else if (has_s4_style_hssi(device_family))
+ get_reconfig_from_gxb_width = W_S4_RECONFIG_BUNDLE_FROM_XCVR;
+ else if (has_c4_style_hssi(device_family))
+ get_reconfig_from_gxb_width = W_C4_RECONFIG_BUNDLE_FROM_XCVR;
+ else
+ get_reconfig_from_gxb_width = 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_to_xcvr total port width for specified device family
+ //
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_to_xcvr port for that family
+ function integer get_reconfig_to_width (
+ input [MAX_CHARS*8-1:0] device_family,
+ input integer reconfig_interfaces
+ );
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family))
+ get_reconfig_to_width = get_s5_reconfig_to_width(reconfig_interfaces);
+ else if (has_s4_style_hssi(device_family))
+ get_reconfig_to_width = W_S4_RECONFIG_BUNDLE_TO_XCVR;
+ else if (has_c4_style_hssi(device_family))
+ get_reconfig_to_width = W_C4_RECONFIG_BUNDLE_TO_XCVR;
+ else
+ get_reconfig_to_width = 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_to_xcvr total port width for Stratix V device family
+ //
+ function integer get_s5_reconfig_to_width (
+ input integer reconfig_interfaces
+ );
+ get_s5_reconfig_to_width = reconfig_interfaces * get_reconfig_to_gxb_width("Stratix V");
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_from_xcvr total port width for specified device family
+ //
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_reconfig_from_width (
+ input [MAX_CHARS*8-1:0] device_family,
+ input integer reconfig_interfaces
+ );
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family))
+ get_reconfig_from_width = reconfig_interfaces * get_reconfig_from_gxb_width(device_family);
+ else if (has_s4_style_hssi(device_family))
+ get_reconfig_from_width = reconfig_interfaces * get_reconfig_from_gxb_width(device_family);
+ else if (has_c4_style_hssi(device_family))
+ get_reconfig_from_width = reconfig_interfaces * get_reconfig_from_gxb_width(device_family);
+ else
+ get_reconfig_from_width = 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_from_xcvr total port width for Stratix V device family
+ //
+ function integer get_s5_reconfig_from_width (
+ input integer reconfig_interfaces
+ );
+ get_s5_reconfig_from_width = reconfig_interfaces * get_reconfig_from_gxb_width("Stratix V");
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get number of reconfig interfaces for Custom PHY
+ // NOTE - !!Has since been used by other PHY IP!!
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // @param lanes - Number of channels
+ // @param plls - Number of TX plls (per channel)
+ // @param bonded_group_size - Size of bonded group (1 or lanes)
+ // @param data_path_type - Abuse of function by overloading for ATT support
+ // - Carry on the abuse
+ //
+ // @return 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_custom_reconfig_interfaces(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer lanes,
+ input integer plls,
+ input integer bonded_group_size,
+ input [MAX_CHARS*8-1:0] data_path_type = "",
+ input [MAX_CHARS*8-1:0] bonded_mode = "xN"
+ );
+ integer reconfig_interfaces;
+ reconfig_interfaces = 0;
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family)) begin
+ // ATT specific calculations
+ if( data_path_type == "ATT" ) begin
+ if((operation_mode == "RX_ONLY") || (operation_mode == "rx_only") || (operation_mode == "Rx") || (operation_mode == "RX") || (operation_mode == "rx")) begin
+ reconfig_interfaces = lanes;
+ end else if((operation_mode == "TX_ONLY") || (operation_mode == "tx_only") || (operation_mode == "Tx") || (operation_mode == "TX") || (operation_mode == "tx")) begin
+ reconfig_interfaces = 2*lanes;
+ end else begin
+ reconfig_interfaces = 3*lanes;
+ end
+ end else begin
+ // Custom PHY calculations
+ if((operation_mode == "RX") || (operation_mode == "Rx") || (operation_mode == "rx_only"))
+ reconfig_interfaces = lanes;
+ else begin
+ bonded_group_size = (bonded_mode == "fb_compensation") ? 1 : bonded_group_size;
+ reconfig_interfaces = lanes+(plls*(lanes/bonded_group_size));
+ end
+ end
+ end
+ get_custom_reconfig_interfaces = reconfig_interfaces;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_to_xcvr total port width for Custom PHY
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // @param lanes - Number of transceiver channels
+ // @param plls - Number of plls per bonded group
+ // @param bonded_group_size - Size of bonded group (1 or lanes)
+ // @param data_path_type - Abuse of function to support ATT
+ //
+ // @return - 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_custom_reconfig_to_width(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer lanes,
+ input integer plls,
+ input integer bonded_group_size,
+ input [MAX_CHARS*8-1:0] data_path_type = "",
+ input [MAX_CHARS*8-1:0] bonded_mode = "xN"
+ );
+ integer reconfig_interfaces;
+ reconfig_interfaces = get_custom_reconfig_interfaces(device_family,operation_mode,lanes,plls,bonded_group_size, data_path_type, bonded_mode );
+ get_custom_reconfig_to_width = get_s5_reconfig_to_width(reconfig_interfaces);
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_from_xcvr total port width for Custom PHY
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // @param lanes - Number of transceiver channels
+ // @param plls - Number of plls per bonded group
+ // @param bonded_group_size - Size of bonded group (1 or lanes)
+ // @param data_path_type - Abuse of function to support ATT
+ //
+ // @return - 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_custom_reconfig_from_width(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer lanes,
+ input integer plls,
+ input integer bonded_group_size,
+ input [MAX_CHARS*8-1:0] data_path_type = "",
+ input [MAX_CHARS*8-1:0] bonded_mode = "xN"
+ );
+ integer reconfig_interfaces;
+ reconfig_interfaces = get_custom_reconfig_interfaces(device_family,operation_mode,lanes,plls,bonded_group_size, data_path_type, bonded_mode);
+ get_custom_reconfig_from_width = get_s5_reconfig_from_width(reconfig_interfaces);
+ endfunction
+
+
+ ////////////////////////////////////////////////////////////////////
+ // Start Interlaken Specific functions for calculating reconfig interfaces
+ // and reconfig_to_gxb, reconfig_from_gxb widths
+
+ ////////////////////////////////////////////////////////////////////
+ // Get number of reconfig interfaces for Interlaken PHY
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_interlaken_reconfig_interfaces(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer bonded_group_size,
+ input integer lanes
+ );
+ integer reconfig_interfaces;
+ integer xslices;
+ integer xremain;
+ integer totalplls;
+
+ reconfig_interfaces = 0;
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family)) begin
+ if((operation_mode == "RX") || (operation_mode == "Rx") || (operation_mode == "rx_only"))
+ reconfig_interfaces = lanes;
+ else begin
+ xslices = lanes/bonded_group_size;
+ xremain = lanes % bonded_group_size;
+
+ if (xremain >0)
+ totalplls = xslices +1;
+ else
+ totalplls = xslices;
+ reconfig_interfaces = lanes+totalplls;
+ end // else: !if((operation_mode == "RX") || (operation_mode == "Rx") || (operation_mode == "rx_only"))
+ end // if (has_s5_style_hssi(device_family))
+ get_interlaken_reconfig_interfaces = reconfig_interfaces;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_to_xcvr total port width for Interlaken PHY
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // @param lanes - Number of transceiver channels
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_interlaken_reconfig_to_width(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer bonded_group_size,
+ input integer lanes
+ );
+ integer reconfig_interfaces;
+ reconfig_interfaces = get_interlaken_reconfig_interfaces(device_family,operation_mode,bonded_group_size,lanes);
+ get_interlaken_reconfig_to_width = get_s5_reconfig_to_width(reconfig_interfaces);
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_from_xcvr total port width for Custom PHY
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_interlaken_reconfig_from_width(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer bonded_group_size,
+ input integer lanes
+ );
+ integer reconfig_interfaces;
+ reconfig_interfaces = get_interlaken_reconfig_interfaces(device_family,operation_mode,bonded_group_size,lanes);
+ get_interlaken_reconfig_from_width = get_s5_reconfig_from_width(reconfig_interfaces);
+ endfunction
+
+ // End Interlaken specific functions
+ ////////////////////////////////////////////////////////////////////
+
+
+
+
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/altera_xcvr_xaui.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/altera_xcvr_xaui.sv
new file mode 100644
index 0000000000000000000000000000000000000000..f5731672ef25f5db829bfa5138a5ea5bee0aec5c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/altera_xcvr_xaui.sv
@@ -0,0 +1,510 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//-----------------------------------------------------------------------------
+//
+// Description: alt_xaui static verilog top level
+//
+// Authors: bauyeung 7-Sep-2010
+// Modified: ishimony 13-Dec-2010
+//
+// Copyright (c) Altera Corporation 1997 - 2010
+// All rights reserved.
+//
+//
+//-----------------------------------------------------------------------------
+
+// have separate generate statements for each component
+
+`timescale 1 ps / 1 ps
+import altera_xcvr_functions::*;
+(* altera_attribute = "-name IP_TOOL_NAME __ACDS_IP_CORE_NAME__; -name IP_TOOL_VERSION __ACDS_VERSION_SHORT__" *)
+module altera_xcvr_xaui #(
+ parameter device_family = "Stratix IV", // default Stratix IV
+ parameter starting_channel_number = 0, // only applies to SIV
+ parameter interface_type = "Hard XAUI",
+ parameter data_rate = "3125 Mbps",
+ parameter xaui_pll_type = "CMU",
+ parameter BASE_DATA_RATE = "3125 Mbps",
+ parameter use_control_and_status_ports = 0,
+ parameter external_pma_ctrl_reconf = 0,
+ parameter recovered_clk_out = 0,
+ parameter number_of_interfaces = 1,
+ parameter reconfig_interfaces = 1,
+ parameter use_rx_rate_match = 0,
+ parameter tx_termination = "OCT_150_OHMS",
+ parameter tx_vod_selection = 1,
+ parameter tx_preemp_pretap = 0,
+ parameter tx_preemp_pretap_inv = 0,
+ parameter tx_preemp_tap_1 = 5,
+ parameter tx_preemp_tap_2 = 0,
+ parameter tx_preemp_tap_2_inv = 0,
+ parameter rx_common_mode = "0.82v",
+ parameter rx_termination = "OCT_150_OHMS",
+ parameter rx_eq_dc_gain = 0,
+ parameter rx_eq_ctrl = 14,
+ parameter mgmt_clk_in_mhz = 50
+) (
+ input wire pll_ref_clk,
+ input wire xgmii_tx_clk,
+ output wire xgmii_rx_clk,
+ output wire tx_clk312_5, // dxaui: pma tx out clock, 312.5Mhz
+ input wire phy_mgmt_clk,
+ input wire phy_mgmt_clk_reset,
+ input wire [8:0] phy_mgmt_address,
+ output wire phy_mgmt_waitrequest,
+ input wire phy_mgmt_read,
+ output wire [31:0] phy_mgmt_readdata,
+ input wire phy_mgmt_write,
+ input wire [31:0] phy_mgmt_writedata,
+ input wire [71:0] xgmii_tx_dc,
+ output wire [71:0] xgmii_rx_dc,
+ output wire [3:0] xaui_tx_serial_data,
+ input wire [3:0] xaui_rx_serial_data,
+ output wire rx_ready,
+ output wire tx_ready,
+ output wire [3:0] rx_recovered_clk, // rx recovered clock from cdr
+
+// only used if use_control_and_status_ports is set
+ input tri0 rx_analogreset,
+ input tri0 rx_digitalreset,
+ input tri0 tx_digitalreset,
+ output tri0 rx_channelaligned,
+ input tri0 [3:0] rx_invpolarity,
+ input tri0 [3:0] rx_set_locktodata,
+ input tri0 [3:0] rx_set_locktoref,
+ input tri0 [3:0] rx_seriallpbken,
+ input tri0 [3:0] tx_invpolarity,
+ output tri1 [3:0] rx_is_lockedtodata,
+ output tri0 [3:0] rx_phase_comp_fifo_error,
+ output tri1 [3:0] rx_is_lockedtoref,
+ output tri0 [3:0] rx_rlv,
+ output tri0 [3:0] rx_rmfifoempty,
+ output tri0 [3:0] rx_rmfifofull,
+ output tri0 [3:0] tx_phase_comp_fifo_error,
+ output tri0 [7:0] rx_disperr,
+ output tri0 [7:0] rx_errdetect,
+ output tri0 [7:0] rx_patterndetect,
+ output tri0 [7:0] rx_rmfifodatadeleted,
+ output tri0 [7:0] rx_rmfifodatainserted,
+ output tri0 [7:0] rx_runningdisp,
+ output tri0 [7:0] rx_syncstatus,
+
+
+// only used if external_pma_ctrl_reconf is set
+ output tri0 [altera_xcvr_functions::get_reconfig_from_width(device_family,reconfig_interfaces)-1:0] reconfig_from_xcvr,
+ input tri0 [altera_xcvr_functions::get_reconfig_to_width(device_family,reconfig_interfaces) -1:0] reconfig_to_xcvr,
+ output tri0 pll_locked,
+ input tri0 cal_blk_powerdown,
+ input tri0 gxb_powerdown,
+ input tri0 pll_powerdown
+// need to add all possible port/param combinations
+// these should be set to tri0/1 where possible, so unused ports don't need to be terminated by the user
+);
+
+import altera_xcvr_functions::*;
+
+localparam reconfig_out_width = altera_xcvr_functions::get_reconfig_from_width(device_family,reconfig_interfaces);
+localparam reconfig_in_width = altera_xcvr_functions::get_reconfig_to_width(device_family,reconfig_interfaces);
+
+ wire [reconfig_out_width -1:0] l_reconfig_from_xcvr; // local reconfig_from_xcvr
+ wire [reconfig_in_width -1:0] l_reconfig_to_xcvr; // local reconfig_to_xcvr
+
+ wire [7:0] sc_phy_address; // mgmt.address
+ wire sc_phy_waitrequest; // .waitrequest
+ wire sc_phy_read; // .read
+ wire [31:0] sc_phy_readdata; // .readdata
+ wire sc_phy_write; // .write
+
+ wire [6:0] sc_reconf_address; // mgmt.address
+ wire sc_reconf_waitrequest; // .waitrequest
+ wire sc_reconf_read; // .read
+ wire [31:0] sc_reconf_readdata; // .readdata
+ wire sc_reconf_write; // .write
+
+///////////////////////////////////////////////////////////////////////
+// Custom decoder for multiple slaves of phy-reconfig interface
+///////////////////////////////////////////////////////////////////////
+// should be consistent across all device families
+ alt_xcvr_mgmt2dec_phyreconfig mgmtdec_phyreconfig (
+ .mgmt_clk_reset (phy_mgmt_clk_reset),
+ .mgmt_clk (phy_mgmt_clk),
+
+ .mgmt_address (phy_mgmt_address),
+ .mgmt_read (phy_mgmt_read),
+ .mgmt_write (phy_mgmt_write),
+ .mgmt_readdata (phy_mgmt_readdata),
+ .mgmt_waitrequest (phy_mgmt_waitrequest),
+
+ // internal interface to 'top' phy block
+ .sc_phy_readdata (sc_phy_readdata),
+ .sc_phy_waitrequest (sc_phy_waitrequest),
+ .sc_phy_address (sc_phy_address),
+ .sc_phy_read (sc_phy_read),
+ .sc_phy_write (sc_phy_write),
+
+ // internal interface to 'top' reconfig block
+ .sc_reconf_readdata (sc_reconf_readdata),
+ .sc_reconf_waitrequest (sc_reconf_waitrequest),
+ .sc_reconf_address (sc_reconf_address),
+ .sc_reconf_read (sc_reconf_read),
+ .sc_reconf_write (sc_reconf_write)
+ );
+
+
+///////////////////////////////////////////////////////////////////////
+// alt_xcvr_reconfig
+///////////////////////////////////////////////////////////////////////
+// add generate statement for this
+// need to account for external pma reconfig
+ generate
+ if (external_pma_ctrl_reconf == 1) begin
+ assign l_reconfig_to_xcvr = reconfig_to_xcvr;
+ assign reconfig_from_xcvr = l_reconfig_from_xcvr;
+ end else if ((interface_type == "Hard XAUI") && ((device_family == "Stratix IV") || (device_family == "HardCopy IV") || (device_family == "Arria II GX") || (device_family == "Arria II GX") || (device_family == "Arria II GZ"))) begin
+ alt_xcvr_reconfig_siv #(
+ .number_of_reconfig_interfaces (1)
+ ) alt_xcvr_reconfig_0 (
+ .mgmt_clk_clk (phy_mgmt_clk),
+ .mgmt_rst_reset (phy_mgmt_clk_reset),
+ .reconfig_mgmt_address (sc_reconf_address),
+ .reconfig_mgmt_waitrequest (sc_reconf_waitrequest),
+ .reconfig_mgmt_read (sc_reconf_read),
+ .reconfig_mgmt_readdata (sc_reconf_readdata),
+ .reconfig_mgmt_write (sc_reconf_write),
+ .reconfig_mgmt_writedata (phy_mgmt_writedata),
+ .reconfig_togxb (l_reconfig_to_xcvr),
+ .reconfig_fromgxb (l_reconfig_from_xcvr[16:0])
+ );
+ end else if ((interface_type == "Soft XAUI") && ((device_family == "Stratix IV") || (device_family == "HardCopy IV"))) begin // Arria II GX/GZ don't support soft xaui
+ alt_xcvr_reconfig_siv #(
+ .number_of_reconfig_interfaces (4)
+ ) alt_xcvr_reconfig_0 (
+ .mgmt_clk_clk (phy_mgmt_clk),
+ .mgmt_rst_reset (phy_mgmt_clk_reset),
+ .reconfig_mgmt_address (sc_reconf_address),
+ .reconfig_mgmt_waitrequest (sc_reconf_waitrequest),
+ .reconfig_mgmt_read (sc_reconf_read),
+ .reconfig_mgmt_readdata (sc_reconf_readdata),
+ .reconfig_mgmt_write (sc_reconf_write),
+ .reconfig_mgmt_writedata (phy_mgmt_writedata),
+ .reconfig_togxb (l_reconfig_to_xcvr),
+ .reconfig_fromgxb (l_reconfig_from_xcvr)
+ );
+ end else if ((interface_type == "DDR XAUI") && (device_family == "Stratix IV")) begin
+ // stub for now - nothing here
+ end else if (device_family == "Stratix V") begin
+ // stub for now - nothing here
+ assign l_reconfig_to_xcvr = reconfig_to_xcvr;
+ assign reconfig_from_xcvr = l_reconfig_from_xcvr;
+ end else if (device_family == "Cyclone IV GX") begin
+ alt_xcvr_reconfig_civ #(
+ .number_of_reconfig_interfaces (1)
+ ) alt_xcvr_reconfig_0 (
+ .reconfig_mgmt_clk_clk (phy_mgmt_clk),
+ .reconfig_mgmt_rst_reset (phy_mgmt_clk_reset),
+ .reconfig_mgmt_address (sc_reconf_address),
+ .reconfig_mgmt_waitrequest (sc_reconf_waitrequest),
+ .reconfig_mgmt_read (sc_reconf_read),
+ .reconfig_mgmt_readdata (sc_reconf_readdata),
+ .reconfig_mgmt_write (sc_reconf_write),
+ .reconfig_mgmt_writedata (phy_mgmt_writedata),
+ .reconfig_togxb (l_reconfig_to_xcvr),
+ .reconfig_fromgxb (l_reconfig_from_xcvr[16:0])
+ );
+ end
+ endgenerate
+
+///////////////////////////////////////////////////////////////////////
+// alt_xaui_phy - Integrates hxaui (i/f to hxaui_alt_c3gxb), csr, pma
+// controller and pma channel controller
+///////////////////////////////////////////////////////////////////////
+ generate
+ if (device_family == "Stratix V") begin
+ sv_xcvr_xaui #(
+ .device_family (device_family),
+ .starting_channel_number (starting_channel_number),
+ .interface_type (interface_type),
+ .reconfig_interfaces (reconfig_interfaces),
+ .sys_clk_in_mhz (mgmt_clk_in_mhz),
+ .data_rate (data_rate),
+ .xaui_pll_type (xaui_pll_type),
+ .BASE_DATA_RATE (BASE_DATA_RATE),
+ .use_control_and_status_ports (use_control_and_status_ports),
+ .tx_termination (tx_termination),
+ .rx_termination (rx_termination),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv (tx_preemp_pretap_inv),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv (tx_preemp_tap_2_inv),
+ .tx_vod_selection (tx_vod_selection),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .rx_common_mode (rx_common_mode),
+ .bonded_group_size (4), /// allowed values 1=> non-bonded 4=> bonded
+ .bonded_mode ("xN") /// allowed values "xN" and "fb_compensation"
+ ) alt_xaui_phy (
+ .pll_ref_clk (pll_ref_clk), // refclk.clk
+ .xgmii_tx_clk (xgmii_tx_clk), // xgmii_tx_clk.clk
+ .xgmii_rx_clk (xgmii_rx_clk), // xgmii_rx_clk.clk
+ .phy_mgmt_clk (phy_mgmt_clk), // mgmt_clk.clk
+ .phy_mgmt_clk_reset (phy_mgmt_clk_reset), // mgmt_clk_rst.reset_n
+ .phy_mgmt_address (sc_phy_address), // phy_mgmt.address
+ .phy_mgmt_waitrequest (sc_phy_waitrequest), // .waitrequest
+ .phy_mgmt_read (sc_phy_read), // .read
+ .phy_mgmt_readdata (sc_phy_readdata), // .readdata
+ .phy_mgmt_write (sc_phy_write), // .write
+ .phy_mgmt_writedata (phy_mgmt_writedata), // .writedata
+ .xgmii_tx_dc (xgmii_tx_dc), // xgmii_tx_dc.data
+ .xgmii_rx_dc (xgmii_rx_dc), // xgmii_rx_dc.data
+ .xaui_tx_serial_data (xaui_tx_serial_data), // xaui_tx_serial.export
+ .xaui_rx_serial_data (xaui_rx_serial_data), // xaui_rx_serial.export
+ .rx_digitalreset (rx_digitalreset), // rx_digitalreset.data
+ .tx_digitalreset (tx_digitalreset), // tx_digitalreset.data
+ .rx_channelaligned (rx_channelaligned), // rx_channelaligned.data
+ .rx_syncstatus (rx_syncstatus), // rx_syncstatus.data
+ .rx_disperr (rx_disperr), // rx_disperr.data
+ .rx_errdetect (rx_errdetect), // rx_errdetect.data
+ .rx_ready (rx_ready), // rx_pma_ready.data
+ .tx_ready (tx_ready), // tx_pma_ready.data
+ .reconfig_to_xcvr (l_reconfig_to_xcvr),
+ .reconfig_from_xcvr (l_reconfig_from_xcvr),
+ .rx_recovered_clk (rx_recovered_clk)
+ );
+ end else if ((interface_type == "DDR XAUI") && (device_family == "Stratix IV")) begin
+ dxaui_siv #(
+ .device_family (device_family),
+ .starting_channel_number (starting_channel_number),
+ .interface_type (interface_type),
+ .number_of_interfaces (1),
+ .reconfig_interfaces (reconfig_interfaces),
+ .sys_clk_in_mhz (mgmt_clk_in_mhz),
+ .xaui_pll_type (xaui_pll_type),
+ .use_control_and_status_ports (use_control_and_status_ports),
+ .external_pma_ctrl_reconf (external_pma_ctrl_reconf),
+ .tx_termination (tx_termination),
+ .tx_vod_selection (tx_vod_selection),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv (tx_preemp_pretap_inv),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv (tx_preemp_tap_2_inv),
+ .rx_common_mode (rx_common_mode),
+ .rx_termination (rx_termination),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .use_rx_rate_match (use_rx_rate_match)
+) dxaui_siv (
+ .pll_ref_clk (pll_ref_clk), // i
+ .xgmii_tx_clk (xgmii_tx_clk), // i
+ .xgmii_rx_clk (xgmii_rx_clk), // o
+ .tx_clk312_5 (tx_clk312_5), // o
+ .phy_mgmt_clk (phy_mgmt_clk), // i
+ .phy_mgmt_clk_reset (phy_mgmt_clk_reset), // i
+ .phy_mgmt_address (sc_phy_address), // i
+ .phy_mgmt_waitrequest (sc_phy_waitrequest), // o
+ .phy_mgmt_read (sc_phy_read), // i
+ .phy_mgmt_readdata (sc_phy_readdata), // o
+ .phy_mgmt_write (sc_phy_write), // i
+ .phy_mgmt_writedata (phy_mgmt_writedata), // i
+ .xgmii_tx_dc (xgmii_tx_dc), // i
+ .xgmii_rx_dc (xgmii_rx_dc), // o
+ .xaui_tx_serial_data (xaui_tx_serial_data), // o
+ .xaui_rx_serial_data (xaui_rx_serial_data), // i
+ .rx_ready (rx_ready), // o
+ .tx_ready (tx_ready), // o
+ .rx_recovered_clk (rx_recovered_clk), // o
+ .reconfig_from_xcvr (l_reconfig_from_xcvr), // o
+ .reconfig_to_xcvr (l_reconfig_to_xcvr), // i
+ .rx_analogreset (rx_analogreset), // i
+ .rx_digitalreset (rx_digitalreset), // i
+ .tx_digitalreset (tx_digitalreset), // i
+ .rx_channelaligned (rx_channelaligned), // o
+ .rx_invpolarity (rx_invpolarity), // i
+ .rx_set_locktodata (rx_set_locktodata), // i
+ .rx_set_locktoref (rx_set_locktoref), // i
+ .rx_seriallpbken (rx_seriallpbken), // i
+ .tx_invpolarity (tx_invpolarity), // i
+ .rx_is_lockedtodata (rx_is_lockedtodata), // o
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error), // o
+ .rx_is_lockedtoref (rx_is_lockedtoref), // o
+ .rx_rlv (rx_rlv), // o
+ .rx_rmfifoempty (rx_rmfifoempty), // o
+ .rx_rmfifofull (rx_rmfifofull), // o
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error), // o
+ .rx_disperr (rx_disperr), // o
+ .rx_errdetect (rx_errdetect), // o
+ .rx_patterndetect (rx_patterndetect), // o
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted), // o
+ .rx_rmfifodatainserted (rx_rmfifodatainserted), // o
+ .rx_runningdisp (rx_runningdisp), // o
+ .rx_syncstatus (rx_syncstatus), // o
+ .pll_locked (pll_locked), // o
+ .cal_blk_powerdown (cal_blk_powerdown), // i
+ .gxb_powerdown (gxb_powerdown), // i
+ .pll_powerdown (pll_powerdown) // i
+); // module dxaui_siv
+ end else if ((device_family == "Stratix IV") || (device_family == "HardCopy IV") ||(device_family == "Arria II GX") || (device_family == "Arria II GZ")) begin
+ siv_xcvr_xaui #(
+ .device_family (device_family),
+ .starting_channel_number (starting_channel_number),
+ .interface_type (interface_type),
+ .number_of_interfaces (1),
+ .reconfig_interfaces (reconfig_interfaces),
+ .sys_clk_in_mhz (mgmt_clk_in_mhz),
+ .xaui_pll_type (xaui_pll_type),
+ .use_control_and_status_ports (use_control_and_status_ports),
+ .external_pma_ctrl_reconf (external_pma_ctrl_reconf),
+ .tx_termination (tx_termination),
+ .rx_termination (rx_termination),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv (tx_preemp_pretap_inv),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv (tx_preemp_tap_2_inv),
+ .tx_vod_selection (tx_vod_selection),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .rx_common_mode (rx_common_mode)
+ ) xaui_phy (
+ .pll_ref_clk (pll_ref_clk),
+ .xgmii_rx_clk (xgmii_rx_clk),
+ .xgmii_tx_clk (xgmii_tx_clk),
+ .phy_mgmt_clk (phy_mgmt_clk),
+ .phy_mgmt_clk_reset (phy_mgmt_clk_reset),
+ .phy_mgmt_address (sc_phy_address),
+ .phy_mgmt_read (sc_phy_read),
+ .phy_mgmt_readdata (sc_phy_readdata),
+ .phy_mgmt_waitrequest (sc_phy_waitrequest),
+ .phy_mgmt_write (sc_phy_write),
+ .phy_mgmt_writedata (phy_mgmt_writedata),
+ .xaui_rx_serial_data (xaui_rx_serial_data),
+ .xaui_tx_serial_data (xaui_tx_serial_data),
+ .xgmii_rx_dc (xgmii_rx_dc),
+ .xgmii_tx_dc (xgmii_tx_dc),
+ .rx_ready (rx_ready),
+ .tx_ready (tx_ready),
+ .rx_recovered_clk (rx_recovered_clk), //o
+ .reconfig_from_xcvr (l_reconfig_from_xcvr),
+ .reconfig_to_xcvr (l_reconfig_to_xcvr),
+
+// optional control and status ports - will be terminated by tri0 if unconnected
+ .rx_analogreset (rx_analogreset), // input wire
+ .rx_digitalreset (rx_digitalreset), // input wire [3:0]
+ .tx_digitalreset (tx_digitalreset), // input wire [3:0]
+ .rx_channelaligned (rx_channelaligned), // output wire
+ .rx_invpolarity (rx_invpolarity), // input wire [3:0]
+ .rx_set_locktodata (rx_set_locktodata), // input wire [3:0]
+ .rx_set_locktoref (rx_set_locktoref), // input wire [3:0]
+ .rx_seriallpbken (rx_seriallpbken), // input wire [3:0]
+ .tx_invpolarity (tx_invpolarity), // input wire [3:0]
+ .rx_is_lockedtodata (rx_is_lockedtodata), // output wire [3:0]
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error), // output wire [3:0]
+ .rx_is_lockedtoref (rx_is_lockedtoref), // output wire [3:0]
+ .rx_rlv (rx_rlv), // output wire [3:0]
+ .rx_rmfifoempty (rx_rmfifoempty), // output wire [3:0]
+ .rx_rmfifofull (rx_rmfifofull), // output wire [3:0]
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error), // output wire [3:0]
+ .rx_disperr (rx_disperr), // output wire [7:0]
+ .rx_errdetect (rx_errdetect), // output wire [7:0]
+ .rx_patterndetect (rx_patterndetect), // output wire [7:0]
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted), // output wire [7:0]
+ .rx_rmfifodatainserted (rx_rmfifodatainserted), // output wire [7:0]
+ .rx_runningdisp (rx_runningdisp), // output wire [7:0]
+ .rx_syncstatus (rx_syncstatus), // output wire [7:0]
+
+// external_pma_ctrl_reconf
+ .pll_locked (pll_locked), // output wire
+ .cal_blk_powerdown (cal_blk_powerdown), // input wire
+ .gxb_powerdown (gxb_powerdown), // input wire
+ .pll_powerdown (pll_powerdown) // input wire
+ );
+ end else if (device_family == "Cyclone IV GX") begin
+// need to add the extra optional ports for c&s and ext_pma
+ civ_xcvr_xaui #(
+ .device_family (device_family),
+ .starting_channel_number (starting_channel_number),
+ .interface_type (interface_type),
+ .number_of_interfaces (1),
+ .sys_clk_in_mhz (mgmt_clk_in_mhz),
+ .xaui_pll_type (xaui_pll_type),
+ .use_control_and_status_ports (use_control_and_status_ports),
+ .tx_termination (tx_termination),
+ .rx_termination (rx_termination),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv (tx_preemp_pretap_inv),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv (tx_preemp_tap_2_inv),
+ .tx_vod_selection (tx_vod_selection),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .rx_common_mode (rx_common_mode)
+ ) xaui_phy (
+ .pll_ref_clk (pll_ref_clk),
+ .xgmii_rx_clk (xgmii_rx_clk),
+ .xgmii_tx_clk (xgmii_tx_clk),
+ .phy_mgmt_clk (phy_mgmt_clk),
+ .phy_mgmt_clk_reset (phy_mgmt_clk_reset),
+ .phy_mgmt_address (sc_phy_address),
+ .phy_mgmt_read (sc_phy_read),
+ .phy_mgmt_readdata (sc_phy_readdata),
+ .phy_mgmt_waitrequest (sc_phy_waitrequest),
+ .phy_mgmt_write (sc_phy_write),
+ .phy_mgmt_writedata (phy_mgmt_writedata),
+ .xaui_rx_serial_data (xaui_rx_serial_data),
+ .xaui_tx_serial_data (xaui_tx_serial_data),
+ .xgmii_rx_dc (xgmii_rx_dc),
+ .xgmii_tx_dc (xgmii_tx_dc),
+ .rx_ready (rx_ready),
+ .tx_ready (tx_ready),
+ .rx_recovered_clk (rx_recovered_clk), //o
+ .reconfig_from_xcvr (l_reconfig_from_xcvr[16:0]),
+ .reconfig_to_xcvr (l_reconfig_to_xcvr),
+
+// optional control and status ports - will be terminated by tri0 if unconnected
+ .rx_analogreset (rx_analogreset), // input wire
+ .rx_digitalreset (rx_digitalreset), // input wire [3:0]
+ .tx_digitalreset (tx_digitalreset), // input wire [3:0]
+ .rx_channelaligned (rx_channelaligned), // output wire
+ .rx_invpolarity (rx_invpolarity), // input wire [3:0]
+ .rx_set_locktodata (rx_set_locktodata), // input wire [3:0]
+ .rx_set_locktoref (rx_set_locktoref), // input wire [3:0]
+ .rx_seriallpbken (rx_seriallpbken), // input wire [3:0]
+ .tx_invpolarity (tx_invpolarity), // input wire [3:0]
+ .rx_is_lockedtodata (rx_is_lockedtodata), // output wire [3:0]
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error), // output wire [3:0]
+ .rx_is_lockedtoref (rx_is_lockedtoref), // output wire [3:0]
+ .rx_rlv (rx_rlv), // output wire [3:0]
+ .rx_rmfifoempty (rx_rmfifoempty), // output wire [3:0]
+ .rx_rmfifofull (rx_rmfifofull), // output wire [3:0]
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error), // output wire [3:0]
+ .rx_disperr (rx_disperr), // output wire [7:0]
+ .rx_errdetect (rx_errdetect), // output wire [7:0]
+ .rx_patterndetect (rx_patterndetect), // output wire [7:0]
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted), // output wire [7:0]
+ .rx_rmfifodatainserted (rx_rmfifodatainserted), // output wire [7:0]
+ .rx_runningdisp (rx_runningdisp), // output wire [7:0]
+ .rx_syncstatus (rx_syncstatus), // output wire [7:0]
+
+// external_pma_ctrl_reconf
+ .pll_locked (pll_locked), // output wire
+ .cal_blk_powerdown (cal_blk_powerdown), // input wire
+ .gxb_powerdown (gxb_powerdown), // input wire
+ .pll_powerdown (pll_powerdown) // input wire
+ );
+ end
+ endgenerate
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/hxaui.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/hxaui.v
new file mode 100644
index 0000000000000000000000000000000000000000..de12fe1dceb673e679f042133e3e4c48d0c3e778
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/hxaui.v
@@ -0,0 +1,499 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//-----------------------------------------------------------------------------
+//
+// Description: hxaui - instantiates hard xaui and shim layer
+//
+// Authors: ishimony 14-Jan-2009
+//
+// Copyright (c) Altera Corporation 1997 - 2009
+// All rights reserved.
+//
+// //
+//-----------------------------------------------------------------------------
+
+`timescale 1 ps / 1 ps
+
+module hxaui(
+ xgmii_tx_clk, refclk, xgmii_tx_dc, xgmii_rx_clk, xgmii_rx_dc, xaui_rx_serial,
+ xaui_tx_serial, rx_analogreset, rx_digitalreset,
+ tx_digitalreset, rx_channelaligned, rx_invpolarity, rx_set_locktodata,
+ rx_set_locktoref, rx_seriallpbken, tx_invpolarity, rx_is_lockedtodata,
+ rx_phase_comp_fifo_error, rx_is_lockedtoref, rx_rlv, rx_rmfifoempty,
+ rx_rmfifofull, tx_phase_comp_fifo_error, rx_disperr, rx_errdetect,
+ rx_patterndetect, rx_rmfifodatadeleted, rx_rmfifodatainserted, rx_recovered_clk,
+ rx_runningdisp, rx_syncstatus, reconfig_togxb, reconfig_fromgxb,
+ reconfig_clk, cal_blk_clk, cal_blk_powerdown,
+ gxb_powerdown, pll_powerdown, pll_locked, r_cal_blk_powerdown,
+ r_gxb_powerdown, r_pll_powerdown, r_rx_set_locktodata, r_rx_set_locktoref,
+ r_rx_seriallpbken, r_rx_analogreset, r_rx_digitalreset, r_tx_digitalreset,
+ r_rx_invpolarity, r_tx_invpolarity
+); // module hxaui
+
+// parameters --------------------------------------------------------------
+parameter starting_channel_number = 0;
+parameter xaui_pll_type = "CMU"; // values: CMU/LCTANK
+parameter use_control_and_status_ports = "true";
+parameter device_family = "Stratix IV";
+parameter external_pma_ctrl_reconf = "true";
+
+ //analog parameters
+parameter tx_termination = "OCT_100_OHMS"; //Valid values for SIV/AII - OCT_85_OHMS,OCT_100_OHMS,OCT_120_OHMS,OCT_150_OHMS
+ //Valid values for CIV - OCT_100_OHMS,OCT_150_OHMS
+parameter rx_termination = "OCT_100_OHMS"; //Valid values for SIV/AII - OCT_85_OHMS,OCT_100_OHMS,OCT_120_OHMS,OCT_150_OHMS
+ //Valid values for CIV - OCT_100_OHMS,OCT_150_OHMS
+parameter rx_common_mode = "0.82v";
+
+parameter tx_preemp_pretap = 0;//0-7
+parameter tx_preemp_pretap_inv = "FALSE";//TRUE or FALSE.
+parameter tx_preemp_tap_1 = 5; //Valid values for SIV/AII - 0-15
+ //Valid values for CIV - 0-31
+parameter tx_preemp_tap_2 = 0; //0-7
+parameter tx_preemp_tap_2_inv = "FALSE";//TRUE or FALSE.
+parameter tx_vod_selection = 1;//0-7
+
+parameter rx_eq_dc_gain = 0; //Valid values for SIV/AII - 0-4
+ //Valid values for CIV - 0-3
+parameter rx_eq_ctrl = 14;//0-16
+
+
+localparam rx_term = ((rx_termination == "OCT_85_OHMS") ? "OCT 85 OHMS" : ((rx_termination == "OCT_100_OHMS") ? "OCT 100 OHMS" :
+ ((rx_termination == "OCT_120_OHMS") ? "OCT 120 OHMS" : ((rx_termination == "OCT_150_OHMS") ? "OCT 150 OHMS" : "NONE"))));
+localparam tx_term = ((tx_termination == "OCT_85_OHMS") ? "OCT 85 OHMS" : ((tx_termination == "OCT_100_OHMS") ? "OCT 100 OHMS" :
+ ((tx_termination == "OCT_120_OHMS") ? "OCT 120 OHMS" : ((tx_termination == "OCT_150_OHMS") ? "OCT 150 OHMS" : "NONE"))));
+localparam tx_preemp_ptinv = (tx_preemp_pretap_inv == 1) ? "TRUE" : "FALSE";
+localparam tx_preemp_t2inv = (tx_preemp_tap_2_inv == 1) ? "TRUE" : "FALSE";
+
+/*Equalization settings*/
+/*Deepak - Found an SPR (287703) that says there is a difference in legality check between SIV and AII. Arria II has a restricted equalization and preemphasis setting. In the case of equalization, EQA, B,C, D and V can all be 0 or 1 whereas on TGX they can all be 0 to 7. Recheck with Brian on whether the following code is the correct way to change it*/
+
+// Arria II GZ uses SIV EQ settings, so don't add it to this if statement
+localparam rx_eqa_ctrl = (device_family=="Arria II GX") ? ((rx_eq_ctrl >10)? 1 :0) : ((rx_eq_ctrl >10)? 7 :0);
+localparam rx_eqb_ctrl = (device_family=="Arria II GX") ? ((rx_eq_ctrl >6) ? 1 :0) : ((rx_eq_ctrl >6) ? 7 :0);
+localparam rx_eqc_ctrl = (device_family=="Arria II GX") ? ((rx_eq_ctrl >3) ? 1 :0) : ((rx_eq_ctrl >3) ? 7 :0);
+localparam rx_eqd_ctrl = (device_family=="Arria II GX") ? ((rx_eq_ctrl >0) ? 1 :0) : ((rx_eq_ctrl >0) ? 7 :0);
+localparam rx_eqv_ctrl = (device_family=="Arria II GX") ? (((rx_eq_ctrl==2 | rx_eq_ctrl==5 | rx_eq_ctrl==8 | rx_eq_ctrl==13)? 1 :
+ ((rx_eq_ctrl==3 | rx_eq_ctrl==6 | rx_eq_ctrl==10 | rx_eq_ctrl==15)? 1 :
+ ((rx_eq_ctrl==9 | rx_eq_ctrl==14 )? 1 :
+ (rx_eq_ctrl==12)? 1 : 0)))):
+ (((rx_eq_ctrl==2 | rx_eq_ctrl==5 | rx_eq_ctrl==8 | rx_eq_ctrl==13)? 4 :
+ ((rx_eq_ctrl==3 | rx_eq_ctrl==6 | rx_eq_ctrl==10 | rx_eq_ctrl==15)? 7 :
+ ((rx_eq_ctrl==9 | rx_eq_ctrl==14 )? 5 :
+ (rx_eq_ctrl==12)? 3 : 0))));
+
+//Deepak:Cyclone IV GX reconfig_fromgxb_width = 4. But we keep it as 16 for backward compatibility with Stratix IV
+localparam RECONFIG_FROMGXB_WIDTH = 16;
+
+// ports -------------------------------------------------------------------
+
+// xgmii
+input xgmii_tx_clk;
+input refclk;
+input [71:0] xgmii_tx_dc;
+output xgmii_rx_clk;
+output [71:0] xgmii_rx_dc;
+
+// xaui
+input [3:0] xaui_rx_serial;
+output [3:0] xaui_tx_serial;
+
+// clock_reset
+input rx_analogreset;
+input [3:0] rx_digitalreset; //SPR 346070
+input [3:0] tx_digitalreset; //SPR 346070
+
+// ctrl_stat: control and status
+output rx_channelaligned;
+input [3:0] rx_invpolarity;
+input [3:0] rx_set_locktodata; // should be [3:0]
+input [3:0] rx_set_locktoref; // should be [3:0]
+input [3:0] rx_seriallpbken; // should be [3:0]
+input [3:0] tx_invpolarity;
+output [3:0] rx_is_lockedtodata; // should be [3:0]
+output [3:0] rx_phase_comp_fifo_error;
+output [3:0] rx_is_lockedtoref; // should be [3:0]
+output [3:0] rx_rlv;
+output [3:0] rx_rmfifoempty;
+output [3:0] rx_rmfifofull;
+output [3:0] tx_phase_comp_fifo_error;
+output [7:0] rx_disperr;
+output [7:0] rx_errdetect;
+output [7:0] rx_patterndetect;
+output [7:0] rx_rmfifodatadeleted;
+output [7:0] rx_rmfifodatainserted;
+output [7:0] rx_runningdisp;
+output [7:0] rx_syncstatus;
+output [3:0] rx_recovered_clk;
+
+// reconfig
+input [3:0] reconfig_togxb;
+output [RECONFIG_FROMGXB_WIDTH:0] reconfig_fromgxb;
+input reconfig_clk;
+
+// pma control
+input cal_blk_clk;
+input gxb_powerdown;
+input cal_blk_powerdown;
+input pll_powerdown;
+output pll_locked;
+
+input r_gxb_powerdown;
+input r_cal_blk_powerdown;
+input r_pll_powerdown;
+input [3:0] r_rx_set_locktodata; // should be [3:0]
+input [3:0] r_rx_set_locktoref; // should be [3:0]
+input [3:0] r_rx_seriallpbken; // should be [3:0]
+input [3:0] r_rx_analogreset; // should be width 1
+input r_rx_digitalreset;
+input r_tx_digitalreset;
+input [3:0] r_rx_invpolarity;
+input [3:0] r_tx_invpolarity;
+
+
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+
+// ports -------------------------------------------------------------------
+
+wire xgmii_tx_clk;
+wire [71:0] xgmii_tx_dc;
+wire xgmii_rx_clk;
+wire [71:0] xgmii_rx_dc;
+wire [3:0] xaui_rx_serial;
+wire [3:0] xaui_tx_serial;
+wire [3:0] rx_cruclk;
+wire rx_analogreset;
+wire [3:0] rx_digitalreset; //SPR 346070
+wire [3:0] tx_digitalreset; //SPR 346070
+wire rx_channelaligned;
+wire [3:0] rx_invpolarity;
+wire [3:0] rx_set_locktodata;
+wire [3:0] rx_set_locktoref;
+wire [3:0] rx_seriallpbken;
+wire [3:0] tx_invpolarity;
+wire [3:0] rx_is_lockedtodata;
+wire [3:0] rx_phase_comp_fifo_error;
+wire [3:0] rx_is_lockedtoref;
+wire [3:0] rx_rlv;
+wire [3:0] rx_rmfifoempty;
+wire [3:0] rx_rmfifofull;
+wire [3:0] tx_phase_comp_fifo_error;
+wire [7:0] rx_disperr;
+wire [7:0] rx_errdetect;
+wire [7:0] rx_patterndetect;
+wire [7:0] rx_rmfifodatadeleted;
+wire [7:0] rx_rmfifodatainserted;
+wire [7:0] rx_runningdisp;
+wire [7:0] rx_syncstatus;
+wire [3:0] reconfig_togxb;
+wire [RECONFIG_FROMGXB_WIDTH:0] reconfig_fromgxb;
+wire reconfig_clk;
+wire cal_blk_clk;
+wire cal_blk_powerdown;
+wire gxb_powerdown;
+wire pll_powerdown;
+wire pll_locked;
+
+
+// locals ------------------------------------------------------------------
+wire [7:0] xgmii_tx_c;
+wire [63:0] xgmii_tx_d;
+wire [7:0] xgmii_rx_c;
+wire [63:0] xgmii_rx_d;
+
+// local version
+wire l_cal_blk_powerdown;
+wire l_gxb_powerdown;
+wire l_rx_analogreset;
+wire l_rx_digitalreset;
+wire l_tx_digitalreset;
+wire l_pll_powerdown;
+wire [3:0] l_rx_invpolarity;
+wire [3:0] l_rx_set_locktodata;
+wire [3:0] l_rx_set_locktoref;
+wire [3:0] l_rx_seriallpbken;
+wire [3:0] l_tx_invpolarity;
+
+// register file version
+wire r_gxb_powerdown;
+wire r_cal_blk_powerdown;
+wire [3:0] r_rx_analogreset;
+wire r_rx_digitalreset;
+wire r_tx_digitalreset;
+wire r_pll_powerdown;
+wire [3:0] r_rx_invpolarity;
+wire [3:0] r_rx_set_locktodata;
+wire [3:0] r_rx_set_locktoref;
+wire [3:0] r_rx_seriallpbken;
+wire [3:0] r_tx_invpolarity;
+
+
+// hard xaui signals -------------------------------------------------------
+wire coreclkout;
+wire pll_inclk;
+wire [7:0] tx_ctrlenable;
+wire [63:0] tx_datain;
+wire [7:0] rx_ctrldetect;
+wire [63:0] rx_dataout;
+wire [3:0] rx_datain;
+wire [3:0] tx_dataout;
+wire [3:0] tx_coreclk;
+
+// body --------------------------------------------------------------------
+
+// Convert to/from Avalon Streaming Interface single bus to data + control
+genvar g;
+generate
+ for (g = 0; g < 8; g = g + 1) begin : st_to_dc_b
+ assign xgmii_tx_d [g*8 +: 8] = xgmii_tx_dc[g*9 +: 8];
+ assign xgmii_tx_c [g] = xgmii_tx_dc[g*9 + 8];
+ assign xgmii_rx_dc[g*9 +: 8] = xgmii_rx_d [g*8 +: 8];
+ assign xgmii_rx_dc[g*9 + 8] = xgmii_rx_c [g];
+ end
+endgenerate
+
+// Default values in case ports are not and without control/status registers
+generate
+ if (use_control_and_status_ports == "true" & external_pma_ctrl_reconf == "false" ) begin: use_cs_ports_true
+ assign l_cal_blk_powerdown = cal_blk_powerdown | r_cal_blk_powerdown;
+ assign l_gxb_powerdown = gxb_powerdown | r_gxb_powerdown;
+ assign l_pll_powerdown = pll_powerdown | r_pll_powerdown;
+ assign l_rx_analogreset = rx_analogreset | r_rx_analogreset[0];
+ assign l_rx_digitalreset = |rx_digitalreset | r_rx_digitalreset; //SPR 346070
+ assign l_rx_invpolarity = rx_invpolarity | r_rx_invpolarity;
+ assign l_rx_set_locktodata = rx_set_locktodata[3:0] |
+ r_rx_set_locktodata[3:0];
+ assign l_rx_set_locktoref = rx_set_locktoref[3:0] |
+ r_rx_set_locktoref[3:0];
+ assign l_rx_seriallpbken = rx_seriallpbken[3:0] |
+ r_rx_seriallpbken[3:0];
+ assign l_tx_digitalreset = |tx_digitalreset | r_tx_digitalreset; //SPR 346070
+ assign l_tx_invpolarity = tx_invpolarity | r_tx_invpolarity;
+ end
+ else if (external_pma_ctrl_reconf == "true" ) begin: use_extern_ctrl_true
+ assign l_cal_blk_powerdown = cal_blk_powerdown ;
+ assign l_gxb_powerdown = gxb_powerdown ;
+ assign l_pll_powerdown = pll_powerdown ;
+ assign l_rx_analogreset = rx_analogreset | r_rx_analogreset[0];
+ assign l_rx_digitalreset = |rx_digitalreset | r_rx_digitalreset; //SPR 346070
+ assign l_rx_invpolarity = rx_invpolarity | r_rx_invpolarity;
+ assign l_rx_set_locktodata = rx_set_locktodata[3:0] |
+ r_rx_set_locktodata[3:0];
+ assign l_rx_set_locktoref = rx_set_locktoref[3:0] |
+ r_rx_set_locktoref[3:0];
+ assign l_rx_seriallpbken = rx_seriallpbken[3:0] |
+ r_rx_seriallpbken[3:0];
+ assign l_tx_digitalreset = |tx_digitalreset | r_tx_digitalreset; //SPR 346070
+ assign l_tx_invpolarity = tx_invpolarity | r_tx_invpolarity;
+ end
+ else begin: use_cs_ports_false
+ assign l_cal_blk_powerdown = r_cal_blk_powerdown;
+ assign l_gxb_powerdown = r_gxb_powerdown;
+ assign l_pll_powerdown = r_pll_powerdown;
+ assign l_rx_analogreset = r_rx_analogreset[0];
+ assign l_rx_digitalreset = r_rx_digitalreset | |rx_digitalreset;
+ assign l_rx_invpolarity = r_rx_invpolarity;
+ assign l_rx_set_locktodata = r_rx_set_locktodata[3:0];
+ assign l_rx_set_locktoref = r_rx_set_locktoref[3:0];
+ assign l_rx_seriallpbken = r_rx_seriallpbken[3:0];
+ assign l_tx_digitalreset = r_tx_digitalreset | |tx_digitalreset;
+ assign l_tx_invpolarity = r_tx_invpolarity;
+ end
+endgenerate
+
+// hard xaui --------------------------------------------------------------
+
+// interleave shim
+assign tx_datain[ 0 +: 8] = xgmii_tx_d[ 0 +: 8];
+assign tx_datain[ 8 +: 8] = xgmii_tx_d[32 +: 8];
+assign tx_datain[16 +: 8] = xgmii_tx_d[ 8 +: 8];
+assign tx_datain[24 +: 8] = xgmii_tx_d[40 +: 8];
+assign tx_datain[32 +: 8] = xgmii_tx_d[16 +: 8];
+assign tx_datain[40 +: 8] = xgmii_tx_d[48 +: 8];
+assign tx_datain[48 +: 8] = xgmii_tx_d[24 +: 8];
+assign tx_datain[56 +: 8] = xgmii_tx_d[56 +: 8];
+
+assign tx_ctrlenable[0] = xgmii_tx_c[0];
+assign tx_ctrlenable[1] = xgmii_tx_c[4];
+assign tx_ctrlenable[2] = xgmii_tx_c[1];
+assign tx_ctrlenable[3] = xgmii_tx_c[5];
+assign tx_ctrlenable[4] = xgmii_tx_c[2];
+assign tx_ctrlenable[5] = xgmii_tx_c[6];
+assign tx_ctrlenable[6] = xgmii_tx_c[3];
+assign tx_ctrlenable[7] = xgmii_tx_c[7];
+
+assign xgmii_rx_d[ 0 +: 8] = rx_dataout[ 0 +: 8];
+assign xgmii_rx_d[ 8 +: 8] = rx_dataout[16 +: 8];
+assign xgmii_rx_d[16 +: 8] = rx_dataout[32 +: 8];
+assign xgmii_rx_d[24 +: 8] = rx_dataout[48 +: 8];
+assign xgmii_rx_d[32 +: 8] = rx_dataout[ 8 +: 8];
+assign xgmii_rx_d[40 +: 8] = rx_dataout[24 +: 8];
+assign xgmii_rx_d[48 +: 8] = rx_dataout[40 +: 8];
+assign xgmii_rx_d[56 +: 8] = rx_dataout[56 +: 8];
+
+assign xgmii_rx_c[0] = rx_ctrldetect[0];
+assign xgmii_rx_c[1] = rx_ctrldetect[2];
+assign xgmii_rx_c[2] = rx_ctrldetect[4];
+assign xgmii_rx_c[3] = rx_ctrldetect[6];
+assign xgmii_rx_c[4] = rx_ctrldetect[1];
+assign xgmii_rx_c[5] = rx_ctrldetect[3];
+assign xgmii_rx_c[6] = rx_ctrldetect[5];
+assign xgmii_rx_c[7] = rx_ctrldetect[7];
+
+// translate signal names
+assign pll_inclk = refclk;
+assign xgmii_rx_clk = coreclkout;
+assign rx_datain = xaui_rx_serial;
+assign xaui_tx_serial = tx_dataout;
+assign rx_cruclk = {4{refclk}};
+assign tx_coreclk = {4{xgmii_tx_clk}};
+
+// hard pcs instantiation
+generate
+if((device_family=="Stratix IV") || (device_family=="HardCopy IV") || (device_family=="Arria II GX") || (device_family=="Arria II GZ")) begin: use_device_family_siv_sv
+hxaui_alt4gxb #(
+ .starting_channel_number(starting_channel_number),
+ .receiver_termination(rx_term),
+ .transmitter_termination(tx_term),
+ .preemphasis_ctrl_pretap_setting(tx_preemp_pretap),
+ .preemphasis_ctrl_pretap_inv_setting(tx_preemp_ptinv),
+ .preemphasis_ctrl_1stposttap_setting(tx_preemp_tap_1),
+ .preemphasis_ctrl_2ndposttap_setting(tx_preemp_tap_2),
+ .preemphasis_ctrl_2ndposttap_inv_setting(tx_preemp_t2inv),
+ .vod_ctrl_setting(tx_vod_selection),
+ .rx_common_mode(rx_common_mode),
+ .equalizer_ctrl_a_setting(rx_eqa_ctrl),
+ .equalizer_ctrl_b_setting(rx_eqb_ctrl),
+ .equalizer_ctrl_c_setting(rx_eqc_ctrl),
+ .equalizer_ctrl_d_setting(rx_eqd_ctrl),
+ .equalizer_ctrl_v_setting(rx_eqv_ctrl),
+ .equalizer_dcgain_setting(rx_eq_dc_gain)
+)hxaui_alt4gxb(
+ .cal_blk_clk (cal_blk_clk), // i
+ .cal_blk_powerdown (l_cal_blk_powerdown), // i
+ .gxb_powerdown (l_gxb_powerdown), // i
+ .pll_inclk (pll_inclk), // i
+ .pll_powerdown (l_pll_powerdown), // i
+ .reconfig_clk (reconfig_clk), // i
+ .reconfig_togxb (reconfig_togxb), // i
+ .rx_analogreset (l_rx_analogreset), // i
+ .rx_cruclk (rx_cruclk),
+ .rx_datain (rx_datain), // i
+ .rx_digitalreset (l_rx_digitalreset), // i
+ .rx_invpolarity (l_rx_invpolarity), // i
+ .rx_locktodata (l_rx_set_locktodata), // i
+ .rx_locktorefclk (l_rx_set_locktoref), // i
+ .rx_seriallpbken (l_rx_seriallpbken), // i
+ .tx_coreclk (tx_coreclk), // i - user should tie this to xgmii_rx_clk at top level, if not used
+ .tx_ctrlenable (tx_ctrlenable),
+ .tx_datain (tx_datain), // i
+ .tx_digitalreset (l_tx_digitalreset), // i
+ .tx_invpolarity (l_tx_invpolarity), // i
+ .coreclkout (coreclkout), // o
+ .pll_locked (pll_locked), // o
+ .reconfig_fromgxb (reconfig_fromgxb), // o
+ .rx_channelaligned (rx_channelaligned), // o
+ .rx_ctrldetect (rx_ctrldetect), // o
+ .rx_dataout (rx_dataout), // o
+ .rx_disperr (rx_disperr), // o
+ .rx_errdetect (rx_errdetect), // o
+ .rx_freqlocked (rx_is_lockedtodata[3:0]), // o
+ .rx_patterndetect (rx_patterndetect), // o
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error), // o
+ .rx_pll_locked (rx_is_lockedtoref[3:0]), // o
+ .rx_rlv (rx_rlv), // o
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted), // o
+ .rx_rmfifodatainserted (rx_rmfifodatainserted), // o
+ .rx_rmfifoempty (rx_rmfifoempty), // o
+ .rx_rmfifofull (rx_rmfifofull), // o
+ .rx_runningdisp (rx_runningdisp), // o
+ .rx_recovered_clk (rx_recovered_clk), // o
+ .rx_syncstatus (rx_syncstatus), // o
+ .tx_dataout (tx_dataout), // o
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error) // o
+);
+defparam
+ hxaui_alt4gxb.starting_channel_number = starting_channel_number;
+end
+
+if((device_family=="Cyclone IV GX")) begin: use_device_family_civ
+
+//Deepak : from Mei Yin Tan, PN
+//Cyclone IV GX:
+//if you are using duplex design, both the tx and rx is sharing the same ALTPLL, so the pll_locked will determine whether the pll is locked.
+//assign rx_is_lockedtoref[3:0] = {4{pll_locked}};
+assign rx_is_lockedtoref[3:0] = rx_is_lockedtodata[3:0];
+
+
+hxaui_alt_c3gxb #(
+ .starting_channel_number(starting_channel_number),
+ .receiver_termination(rx_term),
+ .transmitter_termination(tx_term),
+ .preemphasis_ctrl_1stposttap_setting(tx_preemp_tap_1),
+ .vod_ctrl_setting(tx_vod_selection),
+ .rx_common_mode(rx_common_mode),
+ .equalizer_dcgain_setting(rx_eq_dc_gain)
+)hxaui_alt_c3gxb (
+
+ .cal_blk_clk (cal_blk_clk), // i
+ .cal_blk_powerdown (l_cal_blk_powerdown), // i
+ .gxb_powerdown (l_gxb_powerdown), // i
+ .pll_inclk (pll_inclk), // i
+ .pll_powerdown (l_pll_powerdown), // i
+ .reconfig_clk (reconfig_clk), // i
+ .reconfig_togxb (reconfig_togxb), // i
+ .rx_analogreset (l_rx_analogreset), // i
+ .rx_datain (rx_datain), // i
+ .rx_digitalreset (l_rx_digitalreset), // i
+ .rx_invpolarity (l_rx_invpolarity), // i
+ .rx_locktodata (l_rx_set_locktodata), // i
+ .rx_locktorefclk (l_rx_set_locktoref), // i
+
+ .tx_coreclk (tx_coreclk), // i - user should tie this to xgmii_rx_clk at top level, if not used
+ .tx_ctrlenable (tx_ctrlenable),
+ .tx_datain (tx_datain), // i
+ .tx_digitalreset (l_tx_digitalreset), // i
+ .tx_invpolarity (l_tx_invpolarity), // i
+ .coreclkout (coreclkout), // o
+ .pll_locked (pll_locked), // o
+ .reconfig_fromgxb (reconfig_fromgxb[4:0]), // o - alt3gxb uses only lower 5 bits of 17 bits from Stratix IV
+ .rx_channelaligned (rx_channelaligned), // o
+ .rx_ctrldetect (rx_ctrldetect), // o
+ .rx_dataout (rx_dataout), // o
+ .rx_disperr (rx_disperr), // o
+ .rx_errdetect (rx_errdetect), // o
+ .rx_freqlocked (rx_is_lockedtodata[3:0]), // o
+ .rx_patterndetect (rx_patterndetect), // o
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error), // o
+ .rx_rlv (rx_rlv), // o
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted), // o
+ .rx_rmfifodatainserted (rx_rmfifodatainserted), // o
+ .rx_rmfifoempty (rx_rmfifoempty), // o
+ .rx_rmfifofull (rx_rmfifofull), // o
+ .rx_recovered_clk (rx_recovered_clk), // o
+ .rx_runningdisp (rx_runningdisp), // o
+ .rx_syncstatus (rx_syncstatus), // o
+ .tx_dataout (tx_dataout), // o
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error) // o
+);
+defparam
+ hxaui_alt_c3gxb.starting_channel_number = starting_channel_number;
+
+assign reconfig_fromgxb[16:5] = 12'b0;
+end
+endgenerate
+
+endmodule // alt_xaui
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/hxaui_alt4gxb.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/hxaui_alt4gxb.v
new file mode 100644
index 0000000000000000000000000000000000000000..3c73ae92cf771e2eb4711d03be66a8166501ab4d
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/hxaui_alt4gxb.v
@@ -0,0 +1,4048 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt4gxb
+
+// ============================================================
+// File Name: hxaui_alt4gxb.v
+// Megafunction Name(s):
+// alt4gxb
+//
+// Simulation Library Files(s):
+// stratixiv_hssi
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.1 Build 301 01/06/2010 SP 1 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt4gxb CBX_AUTO_BLACKBOX="ALL" coreclkout_control_width=1 device_family="Stratix IV" effective_data_rate="3125 Mbps" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=0 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="AUTO" gxb_powerdown_width=1 input_clock_frequency="156.25 MHz" intended_device_speed_grade="2" intended_device_variant="GX" loopback_mode="slb" number_of_channels=4 number_of_quads=1 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="xaui" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_fromgxb_port_width=17 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="true" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_bonding="x4" rx_channel_width=16 rx_common_mode="0.82v" rx_cru_bandwidth_type="auto" rx_cru_inclock0_period=6400 rx_cru_m_divider=10 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=2 rx_data_rate=3125 rx_data_rate_remainder=0 rx_datapath_protocol="xaui" rx_digitalreset_port_width=1 rx_dwidth_factor=2 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="true" rx_enable_lock_to_refclk_sig="true" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="1101000011" rx_rate_match_pattern2="0010111100" rx_rate_match_pattern_size=10 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=2 rx_signal_detect_valid_threshold=1 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="true" rx_use_double_data_mode="true" rx_use_external_termination="false" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="true" tx_analog_power="AUTO" tx_channel_bonding="x4" tx_channel_width=16 tx_clkout_width=4 tx_common_mode="0.65v" tx_data_rate=3125 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=2 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="auto" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=6400 tx_pll_m_divider=10 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=2 tx_slew_rate="low" tx_transmit_protocol="xaui" tx_use_coreclk="true" tx_use_double_data_mode="true" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk cal_blk_powerdown coreclkout gxb_powerdown pll_inclk pll_locked pll_powerdown reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_channelaligned rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_freqlocked rx_invpolarity rx_locktodata rx_locktorefclk rx_patterndetect rx_phase_comp_fifo_error rx_pll_locked rx_rlv rx_rmfifodatadeleted rx_rmfifodatainserted rx_rmfifoempty rx_rmfifofull rx_runningdisp rx_seriallpbken rx_syncstatus tx_coreclk tx_ctrlenable tx_datain tx_dataout tx_digitalreset tx_invpolarity tx_phase_comp_fifo_error
+//VERSION_BEGIN 9.1SP1 cbx_alt4gxb 2010:01:06:21:12:59:SJ cbx_mgl 2010:01:06:21:19:19:SJ cbx_tgx 2010:01:06:21:12:59:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = reg 6 stratixiv_hssi_calibration_block 1 stratixiv_hssi_clock_divider 1 stratixiv_hssi_cmu 1 stratixiv_hssi_pll 5 stratixiv_hssi_rx_pcs 4 stratixiv_hssi_rx_pma 4 stratixiv_hssi_tx_pcs 4 stratixiv_hssi_tx_pma 4
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module hxaui_alt4gxb_alt4gxb_dksa
+ (
+ cal_blk_clk,
+ cal_blk_powerdown,
+ coreclkout,
+ gxb_powerdown,
+ pll_inclk,
+ pll_locked,
+ pll_powerdown,
+ reconfig_clk,
+ reconfig_fromgxb,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_channelaligned,
+ rx_coreclk,
+ rx_cruclk,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_disperr,
+ rx_errdetect,
+ rx_freqlocked,
+ rx_invpolarity,
+ rx_locktodata,
+ rx_locktorefclk,
+ rx_patterndetect,
+ rx_phase_comp_fifo_error,
+ rx_pll_locked,
+ rx_rlv,
+ rx_rmfifodatadeleted,
+ rx_rmfifodatainserted,
+ rx_rmfifoempty,
+ rx_rmfifofull,
+ rx_runningdisp,
+ rx_seriallpbken,
+ rx_syncstatus,
+ rx_recovered_clk,
+ tx_coreclk,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_digitalreset,
+ tx_invpolarity,
+ tx_phase_comp_fifo_error) ;
+ input cal_blk_clk;
+ input cal_blk_powerdown;
+ output [0:0] coreclkout;
+ input [0:0] gxb_powerdown;
+ input pll_inclk;
+ output [0:0] pll_locked;
+ input [0:0] pll_powerdown;
+ input reconfig_clk;
+ output [16:0] reconfig_fromgxb;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ output [0:0] rx_channelaligned;
+ input [3:0] rx_coreclk;
+ input [3:0] rx_cruclk;
+ output [7:0] rx_ctrldetect;
+ input [3:0] rx_datain;
+ output [63:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [7:0] rx_disperr;
+ output [7:0] rx_errdetect;
+ output [3:0] rx_freqlocked;
+ input [3:0] rx_invpolarity;
+ input [3:0] rx_locktodata;
+ input [3:0] rx_locktorefclk;
+ output [7:0] rx_patterndetect;
+ output [3:0] rx_phase_comp_fifo_error;
+ output [3:0] rx_pll_locked;
+ output [3:0] rx_rlv;
+ output [7:0] rx_rmfifodatadeleted;
+ output [7:0] rx_rmfifodatainserted;
+ output [3:0] rx_rmfifoempty;
+ output [3:0] rx_rmfifofull;
+ output [7:0] rx_runningdisp;
+ input [3:0] rx_seriallpbken;
+ output [7:0] rx_syncstatus;
+ input [3:0] tx_coreclk;
+ input [7:0] tx_ctrlenable;
+ input [63:0] tx_datain;
+ output [3:0] tx_dataout;
+ input [0:0] tx_digitalreset;
+ input [3:0] tx_invpolarity;
+ output [3:0] tx_phase_comp_fifo_error;
+ output [3:0] rx_recovered_clk;
+
+ wire wire_receive_pcs0_clkout;
+ wire wire_receive_pcs1_clkout;
+ wire wire_receive_pcs2_clkout;
+ wire wire_receive_pcs3_clkout;
+ assign rx_recovered_clk = {wire_receive_pcs0_clkout,wire_receive_pcs1_clkout,wire_receive_pcs2_clkout,wire_receive_pcs3_clkout};
+
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 cal_blk_clk;
+ tri0 cal_blk_powerdown;
+ tri0 [0:0] gxb_powerdown;
+ tri0 pll_inclk;
+ tri0 [0:0] pll_powerdown;
+ tri0 reconfig_clk;
+ tri0 [0:0] rx_analogreset;
+ tri0 [3:0] rx_coreclk;
+ tri0 [3:0] rx_cruclk;
+ tri0 [0:0] rx_digitalreset;
+ tri0 [3:0] rx_invpolarity;
+ tri0 [3:0] rx_locktodata;
+ tri0 [3:0] rx_locktorefclk;
+ tri0 [3:0] rx_seriallpbken;
+ tri0 [3:0] tx_coreclk;
+ tri0 [7:0] tx_ctrlenable;
+ tri0 [63:0] tx_datain;
+ tri0 [0:0] tx_digitalreset;
+ tri0 [3:0] tx_invpolarity;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+
+ parameter starting_channel_number = 0;
+ parameter transmitter_termination = "OCT 100 OHMS";//OCT_85_OHMS,OCT_100_OHMS,OCT_120_OHMS,OCT_150_OHMS
+ parameter receiver_termination = "OCT 100 OHMS"; //OCT_85_OHMS,OCT_100_OHMS,OCT_120_OHMS,OCT_150_OHMS
+ parameter rx_common_mode = "0.82v";
+
+ parameter preemphasis_ctrl_pretap_setting = 0;//0-7
+ parameter preemphasis_ctrl_pretap_inv_setting = "FALSE";//TRUE or FALSE.
+ parameter preemphasis_ctrl_1stposttap_setting = 5;//0-15
+ parameter preemphasis_ctrl_2ndposttap_setting = 0;//0-7
+ parameter preemphasis_ctrl_2ndposttap_inv_setting = "FALSE";//TRUE or FALSE.
+ parameter vod_ctrl_setting = 1;//0-7
+
+ parameter equalizer_dcgain_setting = 0; //0-4
+ parameter equalizer_ctrl_a_setting = 0;
+ parameter equalizer_ctrl_b_setting = 0;
+ parameter equalizer_ctrl_c_setting = 0;
+ parameter equalizer_ctrl_d_setting = 0;
+ parameter equalizer_ctrl_v_setting = 0;
+
+
+ wire [2:0] wire_rx_digitalreset_reg0c_d;
+ reg [2:0] rx_digitalreset_reg0c;
+ wire [2:0] wire_rx_digitalreset_reg0c_clk;
+ wire [2:0] wire_tx_digitalreset_reg0c_d;
+ reg [2:0] tx_digitalreset_reg0c;
+ wire [2:0] wire_tx_digitalreset_reg0c_clk;
+ wire wire_cal_blk0_nonusertocmu;
+ wire [1:0] wire_central_clk_div0_analogfastrefclkout;
+ wire [1:0] wire_central_clk_div0_analogrefclkout;
+ wire wire_central_clk_div0_analogrefclkpulse;
+ wire wire_central_clk_div0_coreclkout;
+ wire [99:0] wire_central_clk_div0_dprioout;
+ wire wire_central_clk_div0_rateswitchdone;
+ wire wire_central_clk_div0_refclkout;
+ wire wire_cent_unit0_alignstatus;
+ wire [1:0] wire_cent_unit0_clkdivpowerdn;
+ wire [599:0] wire_cent_unit0_cmudividerdprioout;
+ wire [1799:0] wire_cent_unit0_cmuplldprioout;
+ wire wire_cent_unit0_dpriodisableout;
+ wire wire_cent_unit0_dprioout;
+ wire wire_cent_unit0_enabledeskew;
+ wire wire_cent_unit0_fiforesetrd;
+ wire [1:0] wire_cent_unit0_pllpowerdn;
+ wire [1:0] wire_cent_unit0_pllresetout;
+ wire wire_cent_unit0_quadresetout;
+ wire [5:0] wire_cent_unit0_rxanalogresetout;
+ wire [5:0] wire_cent_unit0_rxcrupowerdown;
+ wire [5:0] wire_cent_unit0_rxcruresetout;
+ wire [3:0] wire_cent_unit0_rxctrlout;
+ wire [31:0] wire_cent_unit0_rxdataout;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [5:0] wire_cent_unit0_rxibpowerdown;
+ wire [1599:0] wire_cent_unit0_rxpcsdprioout;
+ wire wire_cent_unit0_rxphfifox4byteselout;
+ wire wire_cent_unit0_rxphfifox4rdenableout;
+ wire wire_cent_unit0_rxphfifox4wrclkout;
+ wire wire_cent_unit0_rxphfifox4wrenableout;
+ wire [1799:0] wire_cent_unit0_rxpmadprioout;
+ wire [5:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txctrlout;
+ wire [31:0] wire_cent_unit0_txdataout;
+ wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [5:0] wire_cent_unit0_txobpowerdown;
+ wire [599:0] wire_cent_unit0_txpcsdprioout;
+ wire wire_cent_unit0_txphfifox4byteselout;
+ wire wire_cent_unit0_txphfifox4rdclkout;
+ wire wire_cent_unit0_txphfifox4rdenableout;
+ wire wire_cent_unit0_txphfifox4wrenableout;
+ wire [1799:0] wire_cent_unit0_txpmadprioout;
+ wire [3:0] wire_rx_cdr_pll0_clk;
+ wire [1:0] wire_rx_cdr_pll0_dataout;
+ wire [299:0] wire_rx_cdr_pll0_dprioout;
+ wire wire_rx_cdr_pll0_freqlocked;
+ wire wire_rx_cdr_pll0_locked;
+ wire wire_rx_cdr_pll0_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll1_clk;
+ wire [1:0] wire_rx_cdr_pll1_dataout;
+ wire [299:0] wire_rx_cdr_pll1_dprioout;
+ wire wire_rx_cdr_pll1_freqlocked;
+ wire wire_rx_cdr_pll1_locked;
+ wire wire_rx_cdr_pll1_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll2_clk;
+ wire [1:0] wire_rx_cdr_pll2_dataout;
+ wire [299:0] wire_rx_cdr_pll2_dprioout;
+ wire wire_rx_cdr_pll2_freqlocked;
+ wire wire_rx_cdr_pll2_locked;
+ wire wire_rx_cdr_pll2_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll3_clk;
+ wire [1:0] wire_rx_cdr_pll3_dataout;
+ wire [299:0] wire_rx_cdr_pll3_dprioout;
+ wire wire_rx_cdr_pll3_freqlocked;
+ wire wire_rx_cdr_pll3_locked;
+ wire wire_rx_cdr_pll3_pfdrefclkout;
+ wire [3:0] wire_tx_pll0_clk;
+ wire [299:0] wire_tx_pll0_dprioout;
+ wire wire_tx_pll0_locked;
+ wire wire_receive_pcs0_adetectdeskew;
+ wire wire_receive_pcs0_alignstatussyncout;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire wire_receive_pcs0_coreclkout;
+ wire [3:0] wire_receive_pcs0_ctrldetect;
+ wire [39:0] wire_receive_pcs0_dataout;
+ wire wire_receive_pcs0_disablefifordout;
+ wire wire_receive_pcs0_disablefifowrout;
+ wire [3:0] wire_receive_pcs0_disperr;
+ wire [399:0] wire_receive_pcs0_dprioout;
+ wire [3:0] wire_receive_pcs0_errdetect;
+ wire wire_receive_pcs0_fifordout;
+ wire [3:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_phfifobyteserdisableout;
+ wire wire_receive_pcs0_phfifooverflow;
+ wire wire_receive_pcs0_phfifoptrsresetout;
+ wire wire_receive_pcs0_phfifordenableout;
+ wire wire_receive_pcs0_phfiforesetout;
+ wire wire_receive_pcs0_phfifounderflow;
+ wire wire_receive_pcs0_phfifowrdisableout;
+ wire wire_receive_pcs0_rateswitchout;
+ wire wire_receive_pcs0_rdalign;
+ wire wire_receive_pcs0_rlv;
+ wire [3:0] wire_receive_pcs0_rmfifodatadeleted;
+ wire [3:0] wire_receive_pcs0_rmfifodatainserted;
+ wire wire_receive_pcs0_rmfifoempty;
+ wire wire_receive_pcs0_rmfifofull;
+ wire [3:0] wire_receive_pcs0_runningdisp;
+ wire [3:0] wire_receive_pcs0_syncstatus;
+ wire wire_receive_pcs0_syncstatusdeskew;
+ wire wire_receive_pcs0_xgmctrldet;
+ wire [7:0] wire_receive_pcs0_xgmdataout;
+ wire wire_receive_pcs0_xgmdatavalid;
+ wire wire_receive_pcs0_xgmrunningdisp;
+ wire wire_receive_pcs1_adetectdeskew;
+ wire wire_receive_pcs1_alignstatussyncout;
+ wire wire_receive_pcs1_cdrctrllocktorefclkout;
+ wire wire_receive_pcs1_coreclkout;
+ wire [3:0] wire_receive_pcs1_ctrldetect;
+ wire [39:0] wire_receive_pcs1_dataout;
+ wire wire_receive_pcs1_disablefifordout;
+ wire wire_receive_pcs1_disablefifowrout;
+ wire [3:0] wire_receive_pcs1_disperr;
+ wire [399:0] wire_receive_pcs1_dprioout;
+ wire [3:0] wire_receive_pcs1_errdetect;
+ wire wire_receive_pcs1_fifordout;
+ wire [3:0] wire_receive_pcs1_patterndetect;
+ wire wire_receive_pcs1_phfifobyteserdisableout;
+ wire wire_receive_pcs1_phfifooverflow;
+ wire wire_receive_pcs1_phfifoptrsresetout;
+ wire wire_receive_pcs1_phfifordenableout;
+ wire wire_receive_pcs1_phfiforesetout;
+ wire wire_receive_pcs1_phfifounderflow;
+ wire wire_receive_pcs1_phfifowrdisableout;
+ wire wire_receive_pcs1_rateswitchout;
+ wire wire_receive_pcs1_rdalign;
+ wire wire_receive_pcs1_rlv;
+ wire [3:0] wire_receive_pcs1_rmfifodatadeleted;
+ wire [3:0] wire_receive_pcs1_rmfifodatainserted;
+ wire wire_receive_pcs1_rmfifoempty;
+ wire wire_receive_pcs1_rmfifofull;
+ wire [3:0] wire_receive_pcs1_runningdisp;
+ wire [3:0] wire_receive_pcs1_syncstatus;
+ wire wire_receive_pcs1_syncstatusdeskew;
+ wire wire_receive_pcs1_xgmctrldet;
+ wire [7:0] wire_receive_pcs1_xgmdataout;
+ wire wire_receive_pcs1_xgmdatavalid;
+ wire wire_receive_pcs1_xgmrunningdisp;
+ wire wire_receive_pcs2_adetectdeskew;
+ wire wire_receive_pcs2_alignstatussyncout;
+ wire wire_receive_pcs2_cdrctrllocktorefclkout;
+ wire wire_receive_pcs2_coreclkout;
+ wire [3:0] wire_receive_pcs2_ctrldetect;
+ wire [39:0] wire_receive_pcs2_dataout;
+ wire wire_receive_pcs2_disablefifordout;
+ wire wire_receive_pcs2_disablefifowrout;
+ wire [3:0] wire_receive_pcs2_disperr;
+ wire [399:0] wire_receive_pcs2_dprioout;
+ wire [3:0] wire_receive_pcs2_errdetect;
+ wire wire_receive_pcs2_fifordout;
+ wire [3:0] wire_receive_pcs2_patterndetect;
+ wire wire_receive_pcs2_phfifobyteserdisableout;
+ wire wire_receive_pcs2_phfifooverflow;
+ wire wire_receive_pcs2_phfifoptrsresetout;
+ wire wire_receive_pcs2_phfifordenableout;
+ wire wire_receive_pcs2_phfiforesetout;
+ wire wire_receive_pcs2_phfifounderflow;
+ wire wire_receive_pcs2_phfifowrdisableout;
+ wire wire_receive_pcs2_rateswitchout;
+ wire wire_receive_pcs2_rdalign;
+ wire wire_receive_pcs2_rlv;
+ wire [3:0] wire_receive_pcs2_rmfifodatadeleted;
+ wire [3:0] wire_receive_pcs2_rmfifodatainserted;
+ wire wire_receive_pcs2_rmfifoempty;
+ wire wire_receive_pcs2_rmfifofull;
+ wire [3:0] wire_receive_pcs2_runningdisp;
+ wire [3:0] wire_receive_pcs2_syncstatus;
+ wire wire_receive_pcs2_syncstatusdeskew;
+ wire wire_receive_pcs2_xgmctrldet;
+ wire [7:0] wire_receive_pcs2_xgmdataout;
+ wire wire_receive_pcs2_xgmdatavalid;
+ wire wire_receive_pcs2_xgmrunningdisp;
+ wire wire_receive_pcs3_adetectdeskew;
+ wire wire_receive_pcs3_alignstatussyncout;
+ wire wire_receive_pcs3_cdrctrllocktorefclkout;
+ wire wire_receive_pcs3_coreclkout;
+ wire [3:0] wire_receive_pcs3_ctrldetect;
+ wire [39:0] wire_receive_pcs3_dataout;
+ wire wire_receive_pcs3_disablefifordout;
+ wire wire_receive_pcs3_disablefifowrout;
+ wire [3:0] wire_receive_pcs3_disperr;
+ wire [399:0] wire_receive_pcs3_dprioout;
+ wire [3:0] wire_receive_pcs3_errdetect;
+ wire wire_receive_pcs3_fifordout;
+ wire [3:0] wire_receive_pcs3_patterndetect;
+ wire wire_receive_pcs3_phfifobyteserdisableout;
+ wire wire_receive_pcs3_phfifooverflow;
+ wire wire_receive_pcs3_phfifoptrsresetout;
+ wire wire_receive_pcs3_phfifordenableout;
+ wire wire_receive_pcs3_phfiforesetout;
+ wire wire_receive_pcs3_phfifounderflow;
+ wire wire_receive_pcs3_phfifowrdisableout;
+ wire wire_receive_pcs3_rateswitchout;
+ wire wire_receive_pcs3_rdalign;
+ wire wire_receive_pcs3_rlv;
+ wire [3:0] wire_receive_pcs3_rmfifodatadeleted;
+ wire [3:0] wire_receive_pcs3_rmfifodatainserted;
+ wire wire_receive_pcs3_rmfifoempty;
+ wire wire_receive_pcs3_rmfifofull;
+ wire [3:0] wire_receive_pcs3_runningdisp;
+ wire [3:0] wire_receive_pcs3_syncstatus;
+ wire wire_receive_pcs3_syncstatusdeskew;
+ wire wire_receive_pcs3_xgmctrldet;
+ wire [7:0] wire_receive_pcs3_xgmdataout;
+ wire wire_receive_pcs3_xgmdatavalid;
+ wire wire_receive_pcs3_xgmrunningdisp;
+ wire [7:0] wire_receive_pma0_analogtestbus;
+ wire wire_receive_pma0_clockout;
+ wire wire_receive_pma0_dataout;
+ wire [299:0] wire_receive_pma0_dprioout;
+ wire wire_receive_pma0_locktorefout;
+ wire [63:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire [7:0] wire_receive_pma1_analogtestbus;
+ wire wire_receive_pma1_clockout;
+ wire wire_receive_pma1_dataout;
+ wire [299:0] wire_receive_pma1_dprioout;
+ wire wire_receive_pma1_locktorefout;
+ wire [63:0] wire_receive_pma1_recoverdataout;
+ wire wire_receive_pma1_signaldetect;
+ wire [7:0] wire_receive_pma2_analogtestbus;
+ wire wire_receive_pma2_clockout;
+ wire wire_receive_pma2_dataout;
+ wire [299:0] wire_receive_pma2_dprioout;
+ wire wire_receive_pma2_locktorefout;
+ wire [63:0] wire_receive_pma2_recoverdataout;
+ wire wire_receive_pma2_signaldetect;
+ wire [7:0] wire_receive_pma3_analogtestbus;
+ wire wire_receive_pma3_clockout;
+ wire wire_receive_pma3_dataout;
+ wire [299:0] wire_receive_pma3_dprioout;
+ wire wire_receive_pma3_locktorefout;
+ wire [63:0] wire_receive_pma3_recoverdataout;
+ wire wire_receive_pma3_signaldetect;
+ wire wire_transmit_pcs0_coreclkout;
+ wire [19:0] wire_transmit_pcs0_dataout;
+ wire [149:0] wire_transmit_pcs0_dprioout;
+ wire wire_transmit_pcs0_forceelecidleout;
+ wire wire_transmit_pcs0_phfifooverflow;
+ wire wire_transmit_pcs0_phfiforddisableout;
+ wire wire_transmit_pcs0_phfiforesetout;
+ wire wire_transmit_pcs0_phfifounderflow;
+ wire wire_transmit_pcs0_phfifowrenableout;
+ wire wire_transmit_pcs0_rdenablesync;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pcs0_xgmctrlenable;
+ wire [7:0] wire_transmit_pcs0_xgmdataout;
+ wire wire_transmit_pcs1_coreclkout;
+ wire [19:0] wire_transmit_pcs1_dataout;
+ wire [149:0] wire_transmit_pcs1_dprioout;
+ wire wire_transmit_pcs1_forceelecidleout;
+ wire wire_transmit_pcs1_phfifooverflow;
+ wire wire_transmit_pcs1_phfiforddisableout;
+ wire wire_transmit_pcs1_phfiforesetout;
+ wire wire_transmit_pcs1_phfifounderflow;
+ wire wire_transmit_pcs1_phfifowrenableout;
+ wire wire_transmit_pcs1_rdenablesync;
+ wire wire_transmit_pcs1_txdetectrx;
+ wire wire_transmit_pcs1_xgmctrlenable;
+ wire [7:0] wire_transmit_pcs1_xgmdataout;
+ wire wire_transmit_pcs2_coreclkout;
+ wire [19:0] wire_transmit_pcs2_dataout;
+ wire [149:0] wire_transmit_pcs2_dprioout;
+ wire wire_transmit_pcs2_forceelecidleout;
+ wire wire_transmit_pcs2_phfifooverflow;
+ wire wire_transmit_pcs2_phfiforddisableout;
+ wire wire_transmit_pcs2_phfiforesetout;
+ wire wire_transmit_pcs2_phfifounderflow;
+ wire wire_transmit_pcs2_phfifowrenableout;
+ wire wire_transmit_pcs2_rdenablesync;
+ wire wire_transmit_pcs2_txdetectrx;
+ wire wire_transmit_pcs2_xgmctrlenable;
+ wire [7:0] wire_transmit_pcs2_xgmdataout;
+ wire wire_transmit_pcs3_coreclkout;
+ wire [19:0] wire_transmit_pcs3_dataout;
+ wire [149:0] wire_transmit_pcs3_dprioout;
+ wire wire_transmit_pcs3_forceelecidleout;
+ wire wire_transmit_pcs3_phfifooverflow;
+ wire wire_transmit_pcs3_phfiforddisableout;
+ wire wire_transmit_pcs3_phfiforesetout;
+ wire wire_transmit_pcs3_phfifounderflow;
+ wire wire_transmit_pcs3_phfifowrenableout;
+ wire wire_transmit_pcs3_rdenablesync;
+ wire wire_transmit_pcs3_txdetectrx;
+ wire wire_transmit_pcs3_xgmctrlenable;
+ wire [7:0] wire_transmit_pcs3_xgmdataout;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire [299:0] wire_transmit_pma0_dprioout;
+ wire wire_transmit_pma0_seriallpbkout;
+ wire wire_transmit_pma1_clockout;
+ wire wire_transmit_pma1_dataout;
+ wire [299:0] wire_transmit_pma1_dprioout;
+ wire wire_transmit_pma1_seriallpbkout;
+ wire wire_transmit_pma2_clockout;
+ wire wire_transmit_pma2_dataout;
+ wire [299:0] wire_transmit_pma2_dprioout;
+ wire wire_transmit_pma2_seriallpbkout;
+ wire wire_transmit_pma3_clockout;
+ wire wire_transmit_pma3_dataout;
+ wire [299:0] wire_transmit_pma3_dprioout;
+ wire wire_transmit_pma3_seriallpbkout;
+ wire [0:0] cent_unit_clkdivpowerdn;
+ wire [599:0] cent_unit_cmudividerdprioout;
+ wire [1799:0] cent_unit_cmuplldprioout;
+ wire [1:0] cent_unit_pllpowerdn;
+ wire [1:0] cent_unit_pllresetout;
+ wire [0:0] cent_unit_quadresetout;
+ wire [0:0] cent_unit_rdenablesync;
+ wire [3:0] cent_unit_rx_ctrl;
+ wire [31:0] cent_unit_rx_xgmdataout;
+ wire [5:0] cent_unit_rxcrupowerdn;
+ wire [5:0] cent_unit_rxibpowerdn;
+ wire [1599:0] cent_unit_rxpcsdprioin;
+ wire [1599:0] cent_unit_rxpcsdprioout;
+ wire [1799:0] cent_unit_rxpmadprioin;
+ wire [1799:0] cent_unit_rxpmadprioout;
+ wire [1199:0] cent_unit_tx_dprioin;
+ wire [31:0] cent_unit_tx_xgmdataout;
+ wire [3:0] cent_unit_txctrlout;
+ wire [5:0] cent_unit_txdetectrxpowerdn;
+ wire [599:0] cent_unit_txdprioout;
+ wire [5:0] cent_unit_txobpowerdn;
+ wire [1799:0] cent_unit_txpmadprioin;
+ wire [1799:0] cent_unit_txpmadprioout;
+ wire [3:0] clk_div_clk0in;
+ wire [599:0] clk_div_cmudividerdprioin;
+ wire [1:0] cmu_analogfastrefclkout;
+ wire [1:0] cmu_analogrefclkout;
+ wire [0:0] cmu_analogrefclkpulse;
+ wire [0:0] coreclkout_wire;
+ wire [0:0] enabledeskew;
+ wire [5:0] fixedclk_to_cmu;
+ wire [0:0] int_hiprateswtichdone;
+ wire [3:0] int_rx_coreclkout;
+ wire [0:0] int_rx_digitalreset_reg;
+ wire [3:0] int_rx_phfifobyteserdisable;
+ wire [3:0] int_rx_phfifoptrsresetout;
+ wire [3:0] int_rx_phfifordenableout;
+ wire [3:0] int_rx_phfiforesetout;
+ wire [3:0] int_rx_phfifowrdisableout;
+ wire [11:0] int_rx_phfifoxnbytesel;
+ wire [11:0] int_rx_phfifoxnrdenable;
+ wire [11:0] int_rx_phfifoxnwrclk;
+ wire [11:0] int_rx_phfifoxnwrenable;
+ wire [0:0] int_rxcoreclk;
+ wire [0:0] int_rxphfifordenable;
+ wire [0:0] int_rxphfiforeset;
+ wire [0:0] int_rxphfifox4byteselout;
+ wire [0:0] int_rxphfifox4rdenableout;
+ wire [0:0] int_rxphfifox4wrclkout;
+ wire [0:0] int_rxphfifox4wrenableout;
+ wire [3:0] int_tx_coreclkout;
+ wire [0:0] int_tx_digitalreset_reg;
+ wire [3:0] int_tx_phfiforddisableout;
+ wire [3:0] int_tx_phfiforesetout;
+ wire [3:0] int_tx_phfifowrenableout;
+ wire [11:0] int_tx_phfifoxnbytesel;
+ wire [11:0] int_tx_phfifoxnrdclk;
+ wire [11:0] int_tx_phfifoxnrdenable;
+ wire [11:0] int_tx_phfifoxnwrenable;
+ wire [0:0] int_txcoreclk;
+ wire [0:0] int_txphfiforddisable;
+ wire [0:0] int_txphfiforeset;
+ wire [0:0] int_txphfifowrenable;
+ wire [0:0] int_txphfifox4byteselout;
+ wire [0:0] int_txphfifox4rdclkout;
+ wire [0:0] int_txphfifox4rdenableout;
+ wire [0:0] int_txphfifox4wrenableout;
+ wire [0:0] nonusertocmu_out;
+ wire [9:0] pll0_clkin;
+ wire [299:0] pll0_dprioin;
+ wire [299:0] pll0_dprioout;
+ wire [3:0] pll0_out;
+ wire [7:0] pll_ch_dataout_wire;
+ wire [1199:0] pll_ch_dprioout;
+ wire [1799:0] pll_cmuplldprioout;
+ wire [0:0] pll_inclk_wire;
+ wire [0:0] pll_locked_out;
+ wire [1:0] pllpowerdn_in;
+ wire [1:0] pllreset_in;
+ wire [0:0] reconfig_togxb_busy;
+ wire [0:0] reconfig_togxb_disable;
+ wire [0:0] reconfig_togxb_in;
+ wire [0:0] reconfig_togxb_load;
+ wire [0:0] refclk_pma;
+ wire [3:0] rx_adetectdeskew;
+ wire [0:0] rx_alignstatussync;
+ wire [3:0] rx_alignstatussyncout;
+ wire [5:0] rx_analogreset_in;
+ wire [5:0] rx_analogreset_out;
+ wire [0:0] rx_channelaligned_in;
+ wire [3:0] rx_coreclk_in;
+ wire [39:0] rx_cruclk_in;
+ wire [15:0] rx_deserclock_in;
+ wire [3:0] rx_digitalreset_in;
+ wire [3:0] rx_digitalreset_out;
+ wire [0:0] rx_disablefifordin_in;
+ wire [3:0] rx_disablefifordout_wire;
+ wire [0:0] rx_disablefifowrin_in;
+ wire [3:0] rx_disablefifowrout_wire;
+ wire [3:0] rx_enapatternalign;
+ wire [0:0] rx_fifordin_in;
+ wire [3:0] rx_fifordout_wire;
+ wire [0:0] rx_fiforesetrd;
+ wire [3:0] rx_freqlocked_wire;
+ wire [3:0] rx_locktodata_wire;
+ wire [3:0] rx_locktorefclk_wire;
+ wire [0:0] rx_masterclk;
+ wire [63:0] rx_out_wire;
+ wire [1599:0] rx_pcsdprioin_wire;
+ wire [1599:0] rx_pcsdprioout;
+ wire [3:0] rx_phfifooverflowout;
+ wire [3:0] rx_phfifordenable;
+ wire [3:0] rx_phfiforeset;
+ wire [3:0] rx_phfifounderflowout;
+ wire [3:0] rx_phfifowrdisable;
+ wire [3:0] rx_pldcruclk_in;
+ wire [15:0] rx_pll_clkout;
+ wire [3:0] rx_pll_pfdrefclkout_wire;
+ wire [3:0] rx_plllocked_wire;
+ wire [67:0] rx_pma_analogtestbus;
+ wire [3:0] rx_pma_clockout;
+ wire [3:0] rx_pma_dataout;
+ wire [3:0] rx_pma_locktorefout;
+ wire [79:0] rx_pma_recoverdataout_wire;
+ wire [1799:0] rx_pmadprioin_wire;
+ wire [1799:0] rx_pmadprioout;
+ wire [3:0] rx_powerdown;
+ wire [5:0] rx_powerdown_in;
+ wire [3:0] rx_prbscidenable;
+ wire [3:0] rx_rdalign;
+ wire [3:0] rx_rmfiforeset;
+ wire [5:0] rx_rxcruresetout;
+ wire [3:0] rx_syncstatusdeskew;
+ wire [3:0] rx_xgmctrlin;
+ wire [31:0] rx_xgmdataout;
+ wire [3:0] rx_xgmdatavalid;
+ wire [3:0] rx_xgmrunningdisp;
+ wire [0:0] rxphfifowrdisable;
+ wire [1799:0] rxpll_dprioin;
+ wire [5:0] tx_analogreset_out;
+ wire [3:0] tx_clkout_int_wire;
+ wire [3:0] tx_coreclk_in;
+ wire [63:0] tx_datain_wire;
+ wire [79:0] tx_dataout_pcs_to_pma;
+ wire [3:0] tx_digitalreset_in;
+ wire [3:0] tx_digitalreset_out;
+ wire [1199:0] tx_dprioin_wire;
+ wire [7:0] tx_forcedisp_wire;
+ wire [3:0] tx_localrefclk;
+ wire [3:0] tx_phfifooverflowout;
+ wire [3:0] tx_phfiforeset;
+ wire [3:0] tx_phfifounderflowout;
+ wire [1799:0] tx_pmadprioin_wire;
+ wire [1799:0] tx_pmadprioout;
+ wire [3:0] tx_rdenablesync;
+ wire [3:0] tx_serialloopbackout;
+ wire [599:0] tx_txdprioout;
+ wire [3:0] tx_xgmctrlenable;
+ wire [31:0] tx_xgmdataout;
+ wire [3:0] txdetectrxout;
+ wire [0:0] w_cent_unit_dpriodisableout1w;
+
+ // These are synchronized forms digital reset
+ // async inputs go to *digitalreset_reg0c, synced with data path clock
+ // synopsys translate_off
+ initial
+ rx_digitalreset_reg0c[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_rx_digitalreset_reg0c_clk[0:0])
+ rx_digitalreset_reg0c[0:0] <= wire_rx_digitalreset_reg0c_d[0:0];
+ // synopsys translate_off
+ initial
+ rx_digitalreset_reg0c[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_rx_digitalreset_reg0c_clk[1:1])
+ rx_digitalreset_reg0c[1:1] <= wire_rx_digitalreset_reg0c_d[1:1];
+ // synopsys translate_off
+ initial
+ rx_digitalreset_reg0c[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_rx_digitalreset_reg0c_clk[2:2])
+ rx_digitalreset_reg0c[2:2] <= wire_rx_digitalreset_reg0c_d[2:2];
+ assign
+ wire_rx_digitalreset_reg0c_d = {rx_digitalreset_reg0c[1:0], rx_digitalreset[0]};
+ assign
+ wire_rx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
+ // synopsys translate_off
+ initial
+ tx_digitalreset_reg0c[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_tx_digitalreset_reg0c_clk[0:0])
+ tx_digitalreset_reg0c[0:0] <= wire_tx_digitalreset_reg0c_d[0:0];
+ // synopsys translate_off
+ initial
+ tx_digitalreset_reg0c[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_tx_digitalreset_reg0c_clk[1:1])
+ tx_digitalreset_reg0c[1:1] <= wire_tx_digitalreset_reg0c_d[1:1];
+ // synopsys translate_off
+ initial
+ tx_digitalreset_reg0c[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_tx_digitalreset_reg0c_clk[2:2])
+ tx_digitalreset_reg0c[2:2] <= wire_tx_digitalreset_reg0c_d[2:2];
+ assign
+ wire_tx_digitalreset_reg0c_d = {tx_digitalreset_reg0c[1:0], tx_digitalreset[0]};
+ assign
+ wire_tx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
+
+ // Parameter strings for embedded timing constraints
+ localparam TX_DIGITALRESET_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to {*xaui_phy*tx_digitalreset_reg0c[0]};\""};
+ localparam RX_DIGITALRESET_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to {*xaui_phy*rx_digitalreset_reg0c[0]};\""};
+ localparam SDC_CONSTRAINTS = {TX_DIGITALRESET_CONSTRAINT,";",RX_DIGITALRESET_CONSTRAINT};
+ (* altera_attribute = SDC_CONSTRAINTS *) // Apply timing constraints (does not matter which node)
+
+ stratixiv_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .enabletestbus(1'b1),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ stratixiv_hssi_clock_divider central_clk_div0
+ (
+ .analogfastrefclkout(wire_central_clk_div0_analogfastrefclkout),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(wire_central_clk_div0_analogrefclkout),
+ .analogrefclkoutshifted(),
+ .analogrefclkpulse(wire_central_clk_div0_analogrefclkpulse),
+ .analogrefclkpulseshifted(),
+ .clk0in(clk_div_clk0in[3:0]),
+ .coreclkout(wire_central_clk_div0_coreclkout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(cent_unit_cmudividerdprioout[499:400]),
+ .dprioout(wire_central_clk_div0_dprioout),
+ .powerdn(cent_unit_clkdivpowerdn[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchbaseclock(),
+ .rateswitchdone(wire_central_clk_div0_rateswitchdone),
+ .rateswitchout(),
+ .refclkout(wire_central_clk_div0_refclkout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .clk1in({4{1'b0}}),
+ .rateswitch(1'b0),
+ .rateswitchbaseclkin({2{1'b0}}),
+ .rateswitchdonein({2{1'b0}}),
+ .refclkdig(1'b0),
+ .refclkin({2{1'b0}}),
+ .vcobypassin(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ central_clk_div0.divide_by = 5,
+ central_clk_div0.divider_type = "CENTRAL_ENHANCED",
+ central_clk_div0.effective_data_rate = "3125 Mbps",
+ central_clk_div0.enable_dynamic_divider = "false",
+ central_clk_div0.enable_refclk_out = "true",
+ central_clk_div0.inclk_select = 0,
+ central_clk_div0.logical_channel_address = 0,
+ central_clk_div0.pre_divide_by = 1,
+ central_clk_div0.refclkin_select = 0,
+ central_clk_div0.select_local_rate_switch_base_clock = "true",
+ central_clk_div0.select_local_refclk = "true",
+ central_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
+ central_clk_div0.sim_analogrefclkout_phase_shift = 0,
+ central_clk_div0.sim_coreclkout_phase_shift = 0,
+ central_clk_div0.sim_refclkout_phase_shift = 0,
+ central_clk_div0.use_coreclk_out_post_divider = "true",
+ central_clk_div0.use_refclk_post_divider = "false",
+ central_clk_div0.use_vco_bypass = "false",
+ central_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
+ stratixiv_hssi_cmu cent_unit0
+ (
+ .adet(rx_adetectdeskew[3:0]),
+ .alignstatus(wire_cent_unit0_alignstatus),
+ .autospdx4configsel(),
+ .autospdx4rateswitchout(),
+ .autospdx4spdchg(),
+ .clkdivpowerdn(wire_cent_unit0_clkdivpowerdn),
+ .cmudividerdprioin({clk_div_cmudividerdprioin[599:0]}),
+ .cmudividerdprioout(wire_cent_unit0_cmudividerdprioout),
+ .cmuplldprioin(pll_cmuplldprioout[1799:0]),
+ .cmuplldprioout(wire_cent_unit0_cmuplldprioout),
+ .digitaltestout(),
+ .dpclk(reconfig_clk),
+ .dpriodisable(reconfig_togxb_disable),
+ .dpriodisableout(wire_cent_unit0_dpriodisableout),
+ .dprioin(reconfig_togxb_in),
+ .dprioload(reconfig_togxb_load),
+ .dpriooe(),
+ .dprioout(wire_cent_unit0_dprioout),
+ .enabledeskew(wire_cent_unit0_enabledeskew),
+ .extra10gout(),
+ .fiforesetrd(wire_cent_unit0_fiforesetrd),
+ .fixedclk({{2{1'b0}}, fixedclk_to_cmu[3:0]}),
+ .lccmutestbus(),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .phfifiox4ptrsreset(),
+ .pllpowerdn(wire_cent_unit0_pllpowerdn),
+ .pllresetout(wire_cent_unit0_pllresetout),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .rateswitchdonein(int_hiprateswtichdone[0]),
+ .rdalign(rx_rdalign[3:0]),
+ .rdenablesync(cent_unit_rdenablesync[0]),
+ .recovclk(rx_masterclk[0]),
+ .refclkdividerdprioin({2{1'b0}}),
+ .refclkdividerdprioout(),
+ .rxadcepowerdown(),
+ .rxadceresetout(),
+ .rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxclk(refclk_pma[0]),
+ .rxcoreclk(int_rxcoreclk[0]),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxcruresetout(wire_cent_unit0_rxcruresetout),
+ .rxctrl(cent_unit_rx_ctrl[3:0]),
+ .rxctrlout(wire_cent_unit0_rxctrlout),
+ .rxdatain(rx_xgmdataout[31:0]),
+ .rxdataout(wire_cent_unit0_rxdataout),
+ .rxdatavalid(rx_xgmdatavalid[3:0]),
+ .rxdigitalreset({rx_digitalreset_in[3:0]}),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
+ .rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
+ .rxphfifordenable(int_rxphfifordenable[0]),
+ .rxphfiforeset(int_rxphfiforeset[0]),
+ .rxphfifowrdisable(rxphfifowrdisable[0]),
+ .rxphfifox4byteselout(wire_cent_unit0_rxphfifox4byteselout),
+ .rxphfifox4rdenableout(wire_cent_unit0_rxphfifox4rdenableout),
+ .rxphfifox4wrclkout(wire_cent_unit0_rxphfifox4wrclkout),
+ .rxphfifox4wrenableout(wire_cent_unit0_rxphfifox4wrenableout),
+ .rxpmadprioin({cent_unit_rxpmadprioin[1799:0]}),
+ .rxpmadprioout(wire_cent_unit0_rxpmadprioout),
+ .rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
+ .rxrunningdisp(rx_xgmrunningdisp[3:0]),
+ .scanout(),
+ .syncstatus(rx_syncstatusdeskew[3:0]),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txclk(refclk_pma[0]),
+ .txcoreclk(int_txcoreclk[0]),
+ .txctrl(tx_xgmctrlenable[3:0]),
+ .txctrlout(wire_cent_unit0_txctrlout),
+ .txdatain(tx_xgmdataout[31:0]),
+ .txdataout(wire_cent_unit0_txdataout),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset({tx_digitalreset_in[3:0]}),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
+ .txpcsdprioout(wire_cent_unit0_txpcsdprioout),
+ .txphfiforddisable(int_txphfiforddisable[0]),
+ .txphfiforeset(int_txphfiforeset[0]),
+ .txphfifowrenable(int_txphfifowrenable[0]),
+ .txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
+ .txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
+ .txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
+ .txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout),
+ .txpllreset({{1{1'b0}}, pll_powerdown[0]}),
+ .txpmadprioin({cent_unit_txpmadprioin[1799:0]}),
+ .txpmadprioout(wire_cent_unit0_txpmadprioout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({7{1'b0}}),
+ .lccmurtestbussel({3{1'b0}}),
+ .pmacramtest(1'b0),
+ .rateswitch(1'b0),
+ .scanclk(1'b0),
+ .scanin({23{1'b0}}),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({10000{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit0.auto_spd_phystatus_notify_count = 0,
+ cent_unit0.bonded_quad_mode = "none",
+ cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
+ cent_unit0.in_xaui_mode = "true",
+ cent_unit0.offset_all_errors_align = "false",
+ cent_unit0.pipe_auto_speed_nego_enable = "false",
+ cent_unit0.pipe_freq_scale_mode = "Frequency",
+ cent_unit0.pma_done_count = 249950,
+ cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
+ cent_unit0.rx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.rx0_channel_bonding = "x4",
+ cent_unit0.rx0_clk1_mux_select = "master clock",
+ cent_unit0.rx0_clk2_mux_select = "digital reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "true",
+ cent_unit0.tx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.tx0_channel_bonding = "x4",
+ cent_unit0.tx0_ph_fifo_reg_mode = "false",
+ cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
+ cent_unit0.tx0_use_double_data_mode = "true",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_deskew_fifo = "true",
+ cent_unit0.vcceh_voltage = "Auto",
+ cent_unit0.lpm_type = "stratixiv_hssi_cmu";
+ stratixiv_hssi_pll rx_cdr_pll0
+ (
+ .areset(rx_rxcruresetout[0]),
+ .clk(wire_rx_cdr_pll0_clk),
+ .datain(rx_pma_dataout[0]),
+ .dataout(wire_rx_cdr_pll0_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[299:0]),
+ .dprioout(wire_rx_cdr_pll0_dprioout),
+ .freqlocked(wire_rx_cdr_pll0_freqlocked),
+ .inclk({rx_cruclk_in[9:0]}),
+ .locked(wire_rx_cdr_pll0_locked),
+ .locktorefclk(rx_pma_locktorefout[0]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll0.bandwidth_type = "Auto",
+ rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
+ rx_cdr_pll0.dprio_config_mode = 6'h00,
+ rx_cdr_pll0.effective_data_rate = "3125 Mbps",
+ rx_cdr_pll0.enable_dynamic_divider = "false",
+ rx_cdr_pll0.fast_lock_control = "false",
+ rx_cdr_pll0.inclk0_input_period = 6400,
+ rx_cdr_pll0.input_clock_frequency = "156.25 MHz",
+ rx_cdr_pll0.m = 10,
+ rx_cdr_pll0.n = 1,
+ rx_cdr_pll0.pfd_clk_select = 0,
+ rx_cdr_pll0.pll_type = "RX CDR",
+ rx_cdr_pll0.use_refclk_pin = "false",
+ rx_cdr_pll0.vco_post_scale = 2,
+ rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll1
+ (
+ .areset(rx_rxcruresetout[1]),
+ .clk(wire_rx_cdr_pll1_clk),
+ .datain(rx_pma_dataout[1]),
+ .dataout(wire_rx_cdr_pll1_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[599:300]),
+ .dprioout(wire_rx_cdr_pll1_dprioout),
+ .freqlocked(wire_rx_cdr_pll1_freqlocked),
+ .inclk({rx_cruclk_in[19:10]}),
+ .locked(wire_rx_cdr_pll1_locked),
+ .locktorefclk(rx_pma_locktorefout[1]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll1_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[1]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll1.bandwidth_type = "Auto",
+ rx_cdr_pll1.channel_num = ((starting_channel_number + 1) % 4),
+ rx_cdr_pll1.dprio_config_mode = 6'h00,
+ rx_cdr_pll1.effective_data_rate = "3125 Mbps",
+ rx_cdr_pll1.enable_dynamic_divider = "false",
+ rx_cdr_pll1.fast_lock_control = "false",
+ rx_cdr_pll1.inclk0_input_period = 6400,
+ rx_cdr_pll1.input_clock_frequency = "156.25 MHz",
+ rx_cdr_pll1.m = 10,
+ rx_cdr_pll1.n = 1,
+ rx_cdr_pll1.pfd_clk_select = 0,
+ rx_cdr_pll1.pll_type = "RX CDR",
+ rx_cdr_pll1.use_refclk_pin = "false",
+ rx_cdr_pll1.vco_post_scale = 2,
+ rx_cdr_pll1.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll2
+ (
+ .areset(rx_rxcruresetout[2]),
+ .clk(wire_rx_cdr_pll2_clk),
+ .datain(rx_pma_dataout[2]),
+ .dataout(wire_rx_cdr_pll2_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[899:600]),
+ .dprioout(wire_rx_cdr_pll2_dprioout),
+ .freqlocked(wire_rx_cdr_pll2_freqlocked),
+ .inclk({rx_cruclk_in[29:20]}),
+ .locked(wire_rx_cdr_pll2_locked),
+ .locktorefclk(rx_pma_locktorefout[2]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll2_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[2]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll2.bandwidth_type = "Auto",
+ rx_cdr_pll2.channel_num = ((starting_channel_number + 2) % 4),
+ rx_cdr_pll2.dprio_config_mode = 6'h00,
+ rx_cdr_pll2.effective_data_rate = "3125 Mbps",
+ rx_cdr_pll2.enable_dynamic_divider = "false",
+ rx_cdr_pll2.fast_lock_control = "false",
+ rx_cdr_pll2.inclk0_input_period = 6400,
+ rx_cdr_pll2.input_clock_frequency = "156.25 MHz",
+ rx_cdr_pll2.m = 10,
+ rx_cdr_pll2.n = 1,
+ rx_cdr_pll2.pfd_clk_select = 0,
+ rx_cdr_pll2.pll_type = "RX CDR",
+ rx_cdr_pll2.use_refclk_pin = "false",
+ rx_cdr_pll2.vco_post_scale = 2,
+ rx_cdr_pll2.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll3
+ (
+ .areset(rx_rxcruresetout[3]),
+ .clk(wire_rx_cdr_pll3_clk),
+ .datain(rx_pma_dataout[3]),
+ .dataout(wire_rx_cdr_pll3_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[1199:900]),
+ .dprioout(wire_rx_cdr_pll3_dprioout),
+ .freqlocked(wire_rx_cdr_pll3_freqlocked),
+ .inclk({rx_cruclk_in[39:30]}),
+ .locked(wire_rx_cdr_pll3_locked),
+ .locktorefclk(rx_pma_locktorefout[3]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll3_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[3]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll3.bandwidth_type = "Auto",
+ rx_cdr_pll3.channel_num = ((starting_channel_number + 3) % 4),
+ rx_cdr_pll3.dprio_config_mode = 6'h00,
+ rx_cdr_pll3.effective_data_rate = "3125 Mbps",
+ rx_cdr_pll3.enable_dynamic_divider = "false",
+ rx_cdr_pll3.fast_lock_control = "false",
+ rx_cdr_pll3.inclk0_input_period = 6400,
+ rx_cdr_pll3.input_clock_frequency = "156.25 MHz",
+ rx_cdr_pll3.m = 10,
+ rx_cdr_pll3.n = 1,
+ rx_cdr_pll3.pfd_clk_select = 0,
+ rx_cdr_pll3.pll_type = "RX CDR",
+ rx_cdr_pll3.use_refclk_pin = "false",
+ rx_cdr_pll3.vco_post_scale = 2,
+ rx_cdr_pll3.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll tx_pll0
+ (
+ .areset(pllreset_in[0]),
+ .clk(wire_tx_pll0_clk),
+ .dataout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(pll0_dprioin[299:0]),
+ .dprioout(wire_tx_pll0_dprioout),
+ .freqlocked(),
+ .inclk({pll0_clkin[9:0]}),
+ .locked(wire_tx_pll0_locked),
+ .pfdfbclkout(),
+ .pfdrefclkout(),
+ .powerdown(pllpowerdn_in[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datain(1'b0),
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .locktorefclk(1'b1),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ tx_pll0.bandwidth_type = "Auto",
+ tx_pll0.channel_num = 4,
+ tx_pll0.dprio_config_mode = 6'h00,
+ tx_pll0.inclk0_input_period = 6400,
+ tx_pll0.input_clock_frequency = "156.25 MHz",
+ tx_pll0.logical_tx_pll_number = 0,
+ tx_pll0.m = 10,
+ tx_pll0.n = 1,
+ tx_pll0.pfd_clk_select = 0,
+ tx_pll0.pfd_fb_select = "internal",
+ tx_pll0.pll_type = "CMU",
+ tx_pll0.use_refclk_pin = "false",
+ tx_pll0.vco_post_scale = 2,
+ tx_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(wire_receive_pcs0_adetectdeskew),
+ .alignstatus(rx_channelaligned_in[0]),
+ .alignstatussync(rx_alignstatussync[0]),
+ .alignstatussyncout(wire_receive_pcs0_alignstatussyncout),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefcl((reconfig_togxb_busy | rx_locktorefclk[0])),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(wire_receive_pcs0_clkout),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(wire_receive_pcs0_coreclkout),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[19:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .digitaltestout(),
+ .disablefifordin(rx_disablefifordin_in[0]),
+ .disablefifordout(wire_receive_pcs0_disablefifordout),
+ .disablefifowrin(rx_disablefifowrin_in[0]),
+ .disablefifowrout(wire_receive_pcs0_disablefifowrout),
+ .disperr(wire_receive_pcs0_disperr),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[399:0]),
+ .dprioout(wire_receive_pcs0_dprioout),
+ .enabledeskew(enabledeskew[0]),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(wire_receive_pcs0_errdetect),
+ .fifordin(rx_fifordin_in[0]),
+ .fifordout(wire_receive_pcs0_fifordout),
+ .fiforesetrd(rx_fiforesetrd[0]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(rx_invpolarity[0]),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(rx_masterclk[0]),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs0_phfifobyteserdisableout),
+ .phfifooverflow(wire_receive_pcs0_phfifooverflow),
+ .phfifoptrsresetout(wire_receive_pcs0_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(wire_receive_pcs0_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(wire_receive_pcs0_phfiforesetout),
+ .phfifounderflow(wire_receive_pcs0_phfifounderflow),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(wire_receive_pcs0_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[2:0]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[2:0]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[2:0]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[2:0]),
+ .pipebufferstat(),
+ .pipedatavalid(),
+ .pipeelecidle(),
+ .pipephydonestatus(),
+ .pipepowerdown({2{1'b0}}),
+ .pipepowerstate({4{1'b0}}),
+ .pipestatetransdoneout(),
+ .pipestatus(),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs0_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(wire_receive_pcs0_rdalign),
+ .recoveredclk(rx_pma_clockout[0]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(),
+ .rlv(wire_receive_pcs0_rlv),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(wire_receive_pcs0_rmfifodatadeleted),
+ .rmfifodatainserted(wire_receive_pcs0_rmfifodatainserted),
+ .rmfifoempty(wire_receive_pcs0_rmfifoempty),
+ .rmfifofull(wire_receive_pcs0_rmfifofull),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(wire_receive_pcs0_runningdisp),
+ .rxdetectvalid(1'b0),
+ .rxfound({2{1'b0}}),
+ .signaldetect(),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .syncstatusdeskew(wire_receive_pcs0_syncstatusdeskew),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(wire_receive_pcs0_xgmctrldet),
+ .xgmctrlin(rx_xgmctrlin[0]),
+ .xgmdatain(cent_unit_rx_xgmdataout[7:0]),
+ .xgmdataout(wire_receive_pcs0_xgmdataout),
+ .xgmdatavalid(wire_receive_pcs0_xgmdatavalid),
+ .xgmrunningdisp(wire_receive_pcs0_xgmrunningdisp)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .elecidleinfersel({3{1'b0}}),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipe8b10binvpolarity(1'b0),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .powerdn({2{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .signaldetected(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs0.allow_align_polarity_inversion = "true",
+ receive_pcs0.allow_pipe_polarity_inversion = "false",
+ receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs0.auto_spd_phystatus_notify_count = 0,
+ receive_pcs0.auto_spd_self_switch_enable = "false",
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_enable = "false",
+ receive_pcs0.cdrctrl_mask_cycle = 800,
+ receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs0.cdrctrl_rxvalid_mask = "false",
+ receive_pcs0.channel_bonding = "x4",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pcs0.channel_width = 16,
+ receive_pcs0.clk1_mux_select = "master clock",
+ receive_pcs0.clk2_mux_select = "digital reference clock",
+ receive_pcs0.core_clock_0ppm = "true",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "xaui",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.dec_8b_10b_polarity_inv_enable = "false",
+ receive_pcs0.deskew_pattern = "0011000011",
+ receive_pcs0.disable_auto_idle_insertion = "true",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.dprio_config_mode = 6'h01,
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_deep_align = "false",
+ receive_pcs0.enable_deep_align_byte_swap = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.enable_true_complement_match_in_word_align = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.logical_channel_address = (starting_channel_number + 0),
+ receive_pcs0.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs0.num_align_cons_good_data = 4,
+ receive_pcs0.num_align_cons_pat = 4,
+ receive_pcs0.num_align_loss_sync_error = 4,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.ph_fifo_xn_mapping0 = "none",
+ receive_pcs0.ph_fifo_xn_mapping1 = "none",
+ receive_pcs0.ph_fifo_xn_mapping2 = "central",
+ receive_pcs0.ph_fifo_xn_select = 2,
+ receive_pcs0.pipe_auto_speed_nego_enable = "false",
+ receive_pcs0.pipe_freq_scale_mode = "Frequency",
+ receive_pcs0.pma_done_count = 249950,
+ receive_pcs0.protocol_hint = "xaui",
+ receive_pcs0.rate_match_almost_empty_threshold = 11,
+ receive_pcs0.rate_match_almost_full_threshold = 13,
+ receive_pcs0.rate_match_back_to_back = "true",
+ receive_pcs0.rate_match_delete_threshold = 13,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 11,
+ receive_pcs0.rate_match_ordered_set_based = "false",
+ receive_pcs0.rate_match_pattern1 = "1101000011",
+ receive_pcs0.rate_match_pattern2 = "0010111100",
+ receive_pcs0.rate_match_pattern_size = 10,
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "false",
+ receive_pcs0.rate_match_start_threshold = 7,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 40,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rx_phfifo_wait_cnt = 15,
+ receive_pcs0.rxstatus_error_report_mode = 0,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_deserializer_double_data_mode = "false",
+ receive_pcs0.use_deskew_fifo = "true",
+ receive_pcs0.use_double_data_mode = "true",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs1
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(wire_receive_pcs1_adetectdeskew),
+ .alignstatus(rx_channelaligned_in[0]),
+ .alignstatussync(rx_alignstatussync[0]),
+ .alignstatussyncout(wire_receive_pcs1_alignstatussyncout),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefcl((reconfig_togxb_busy | rx_locktorefclk[1])),
+ .cdrctrllocktorefclkout(wire_receive_pcs1_cdrctrllocktorefclkout),
+ .clkout(wire_receive_pcs1_clkout),
+ .coreclk(rx_coreclk_in[1]),
+ .coreclkout(wire_receive_pcs1_coreclkout),
+ .ctrldetect(wire_receive_pcs1_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[39:20]),
+ .dataout(wire_receive_pcs1_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[1]),
+ .digitaltestout(),
+ .disablefifordin(rx_disablefifordin_in[0]),
+ .disablefifordout(wire_receive_pcs1_disablefifordout),
+ .disablefifowrin(rx_disablefifowrin_in[0]),
+ .disablefifowrout(wire_receive_pcs1_disablefifowrout),
+ .disperr(wire_receive_pcs1_disperr),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[799:400]),
+ .dprioout(wire_receive_pcs1_dprioout),
+ .enabledeskew(enabledeskew[0]),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[1]),
+ .errdetect(wire_receive_pcs1_errdetect),
+ .fifordin(rx_fifordin_in[0]),
+ .fifordout(wire_receive_pcs1_fifordout),
+ .fiforesetrd(rx_fiforesetrd[0]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(rx_invpolarity[1]),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(rx_masterclk[0]),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs1_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs1_phfifobyteserdisableout),
+ .phfifooverflow(wire_receive_pcs1_phfifooverflow),
+ .phfifoptrsresetout(wire_receive_pcs1_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[1]),
+ .phfifordenableout(wire_receive_pcs1_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[1]),
+ .phfiforesetout(wire_receive_pcs1_phfiforesetout),
+ .phfifounderflow(wire_receive_pcs1_phfifounderflow),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[1]),
+ .phfifowrdisableout(wire_receive_pcs1_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[5:3]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[5:3]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[5:3]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[5:3]),
+ .pipebufferstat(),
+ .pipedatavalid(),
+ .pipeelecidle(),
+ .pipephydonestatus(),
+ .pipepowerdown({2{1'b0}}),
+ .pipepowerstate({4{1'b0}}),
+ .pipestatetransdoneout(),
+ .pipestatus(),
+ .prbscidenable(rx_prbscidenable[1]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs1_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(wire_receive_pcs1_rdalign),
+ .recoveredclk(rx_pma_clockout[1]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(),
+ .rlv(wire_receive_pcs1_rlv),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(wire_receive_pcs1_rmfifodatadeleted),
+ .rmfifodatainserted(wire_receive_pcs1_rmfifodatainserted),
+ .rmfifoempty(wire_receive_pcs1_rmfifoempty),
+ .rmfifofull(wire_receive_pcs1_rmfifofull),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[1]),
+ .rmfifowrena(1'b0),
+ .runningdisp(wire_receive_pcs1_runningdisp),
+ .rxdetectvalid(1'b0),
+ .rxfound({2{1'b0}}),
+ .signaldetect(),
+ .syncstatus(wire_receive_pcs1_syncstatus),
+ .syncstatusdeskew(wire_receive_pcs1_syncstatusdeskew),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(wire_receive_pcs1_xgmctrldet),
+ .xgmctrlin(rx_xgmctrlin[1]),
+ .xgmdatain(cent_unit_rx_xgmdataout[15:8]),
+ .xgmdataout(wire_receive_pcs1_xgmdataout),
+ .xgmdatavalid(wire_receive_pcs1_xgmdatavalid),
+ .xgmrunningdisp(wire_receive_pcs1_xgmrunningdisp)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .elecidleinfersel({3{1'b0}}),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipe8b10binvpolarity(1'b0),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .powerdn({2{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .signaldetected(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs1.align_pattern = "0101111100",
+ receive_pcs1.align_pattern_length = 10,
+ receive_pcs1.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs1.allow_align_polarity_inversion = "true",
+ receive_pcs1.allow_pipe_polarity_inversion = "false",
+ receive_pcs1.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs1.auto_spd_phystatus_notify_count = 0,
+ receive_pcs1.auto_spd_self_switch_enable = "false",
+ receive_pcs1.bit_slip_enable = "false",
+ receive_pcs1.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs1.byte_order_mode = "none",
+ receive_pcs1.byte_order_pad_pattern = "0",
+ receive_pcs1.byte_order_pattern = "0",
+ receive_pcs1.byte_order_pld_ctrl_enable = "false",
+ receive_pcs1.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs1.cdrctrl_enable = "false",
+ receive_pcs1.cdrctrl_mask_cycle = 800,
+ receive_pcs1.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs1.cdrctrl_rxvalid_mask = "false",
+ receive_pcs1.channel_bonding = "x4",
+ receive_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pcs1.channel_width = 16,
+ receive_pcs1.clk1_mux_select = "master clock",
+ receive_pcs1.clk2_mux_select = "digital reference clock",
+ receive_pcs1.core_clock_0ppm = "true",
+ receive_pcs1.datapath_low_latency_mode = "false",
+ receive_pcs1.datapath_protocol = "xaui",
+ receive_pcs1.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs1.dec_8b_10b_mode = "normal",
+ receive_pcs1.dec_8b_10b_polarity_inv_enable = "false",
+ receive_pcs1.deskew_pattern = "0011000011",
+ receive_pcs1.disable_auto_idle_insertion = "true",
+ receive_pcs1.disable_running_disp_in_word_align = "false",
+ receive_pcs1.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs1.dprio_config_mode = 6'h01,
+ receive_pcs1.elec_idle_infer_enable = "false",
+ receive_pcs1.elec_idle_num_com_detect = 3,
+ receive_pcs1.enable_bit_reversal = "false",
+ receive_pcs1.enable_deep_align = "false",
+ receive_pcs1.enable_deep_align_byte_swap = "false",
+ receive_pcs1.enable_self_test_mode = "false",
+ receive_pcs1.enable_true_complement_match_in_word_align = "false",
+ receive_pcs1.force_signal_detect_dig = "true",
+ receive_pcs1.hip_enable = "false",
+ receive_pcs1.infiniband_invalid_code = 0,
+ receive_pcs1.insert_pad_on_underflow = "false",
+ receive_pcs1.logical_channel_address = (starting_channel_number + 1),
+ receive_pcs1.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs1.num_align_cons_good_data = 4,
+ receive_pcs1.num_align_cons_pat = 4,
+ receive_pcs1.num_align_loss_sync_error = 4,
+ receive_pcs1.ph_fifo_low_latency_enable = "true",
+ receive_pcs1.ph_fifo_reg_mode = "false",
+ receive_pcs1.ph_fifo_xn_mapping0 = "none",
+ receive_pcs1.ph_fifo_xn_mapping1 = "none",
+ receive_pcs1.ph_fifo_xn_mapping2 = "central",
+ receive_pcs1.ph_fifo_xn_select = 2,
+ receive_pcs1.pipe_auto_speed_nego_enable = "false",
+ receive_pcs1.pipe_freq_scale_mode = "Frequency",
+ receive_pcs1.pma_done_count = 249950,
+ receive_pcs1.protocol_hint = "xaui",
+ receive_pcs1.rate_match_almost_empty_threshold = 11,
+ receive_pcs1.rate_match_almost_full_threshold = 13,
+ receive_pcs1.rate_match_back_to_back = "true",
+ receive_pcs1.rate_match_delete_threshold = 13,
+ receive_pcs1.rate_match_empty_threshold = 5,
+ receive_pcs1.rate_match_fifo_mode = "true",
+ receive_pcs1.rate_match_full_threshold = 20,
+ receive_pcs1.rate_match_insert_threshold = 11,
+ receive_pcs1.rate_match_ordered_set_based = "false",
+ receive_pcs1.rate_match_pattern1 = "1101000011",
+ receive_pcs1.rate_match_pattern2 = "0010111100",
+ receive_pcs1.rate_match_pattern_size = 10,
+ receive_pcs1.rate_match_reset_enable = "false",
+ receive_pcs1.rate_match_skip_set_based = "false",
+ receive_pcs1.rate_match_start_threshold = 7,
+ receive_pcs1.rd_clk_mux_select = "core clock",
+ receive_pcs1.recovered_clk_mux_select = "recovered clock",
+ receive_pcs1.run_length = 40,
+ receive_pcs1.run_length_enable = "true",
+ receive_pcs1.rx_detect_bypass = "false",
+ receive_pcs1.rx_phfifo_wait_cnt = 15,
+ receive_pcs1.rxstatus_error_report_mode = 0,
+ receive_pcs1.self_test_mode = "incremental",
+ receive_pcs1.use_alignment_state_machine = "true",
+ receive_pcs1.use_deserializer_double_data_mode = "false",
+ receive_pcs1.use_deskew_fifo = "true",
+ receive_pcs1.use_double_data_mode = "true",
+ receive_pcs1.use_parallel_loopback = "false",
+ receive_pcs1.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs1.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs2
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(wire_receive_pcs2_adetectdeskew),
+ .alignstatus(rx_channelaligned_in[0]),
+ .alignstatussync(rx_alignstatussync[0]),
+ .alignstatussyncout(wire_receive_pcs2_alignstatussyncout),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefcl((reconfig_togxb_busy | rx_locktorefclk[2])),
+ .cdrctrllocktorefclkout(wire_receive_pcs2_cdrctrllocktorefclkout),
+ .clkout(wire_receive_pcs2_clkout),
+ .coreclk(rx_coreclk_in[2]),
+ .coreclkout(wire_receive_pcs2_coreclkout),
+ .ctrldetect(wire_receive_pcs2_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[59:40]),
+ .dataout(wire_receive_pcs2_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[2]),
+ .digitaltestout(),
+ .disablefifordin(rx_disablefifordin_in[0]),
+ .disablefifordout(wire_receive_pcs2_disablefifordout),
+ .disablefifowrin(rx_disablefifowrin_in[0]),
+ .disablefifowrout(wire_receive_pcs2_disablefifowrout),
+ .disperr(wire_receive_pcs2_disperr),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[1199:800]),
+ .dprioout(wire_receive_pcs2_dprioout),
+ .enabledeskew(enabledeskew[0]),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[2]),
+ .errdetect(wire_receive_pcs2_errdetect),
+ .fifordin(rx_fifordin_in[0]),
+ .fifordout(wire_receive_pcs2_fifordout),
+ .fiforesetrd(rx_fiforesetrd[0]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(rx_invpolarity[2]),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(rx_masterclk[0]),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs2_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs2_phfifobyteserdisableout),
+ .phfifooverflow(wire_receive_pcs2_phfifooverflow),
+ .phfifoptrsresetout(wire_receive_pcs2_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[2]),
+ .phfifordenableout(wire_receive_pcs2_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[2]),
+ .phfiforesetout(wire_receive_pcs2_phfiforesetout),
+ .phfifounderflow(wire_receive_pcs2_phfifounderflow),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[2]),
+ .phfifowrdisableout(wire_receive_pcs2_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[8:6]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[8:6]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[8:6]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[8:6]),
+ .pipebufferstat(),
+ .pipedatavalid(),
+ .pipeelecidle(),
+ .pipephydonestatus(),
+ .pipepowerdown({2{1'b0}}),
+ .pipepowerstate({4{1'b0}}),
+ .pipestatetransdoneout(),
+ .pipestatus(),
+ .prbscidenable(rx_prbscidenable[2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs2_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(wire_receive_pcs2_rdalign),
+ .recoveredclk(rx_pma_clockout[2]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(),
+ .rlv(wire_receive_pcs2_rlv),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(wire_receive_pcs2_rmfifodatadeleted),
+ .rmfifodatainserted(wire_receive_pcs2_rmfifodatainserted),
+ .rmfifoempty(wire_receive_pcs2_rmfifoempty),
+ .rmfifofull(wire_receive_pcs2_rmfifofull),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[2]),
+ .rmfifowrena(1'b0),
+ .runningdisp(wire_receive_pcs2_runningdisp),
+ .rxdetectvalid(1'b0),
+ .rxfound({2{1'b0}}),
+ .signaldetect(),
+ .syncstatus(wire_receive_pcs2_syncstatus),
+ .syncstatusdeskew(wire_receive_pcs2_syncstatusdeskew),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(wire_receive_pcs2_xgmctrldet),
+ .xgmctrlin(rx_xgmctrlin[2]),
+ .xgmdatain(cent_unit_rx_xgmdataout[23:16]),
+ .xgmdataout(wire_receive_pcs2_xgmdataout),
+ .xgmdatavalid(wire_receive_pcs2_xgmdatavalid),
+ .xgmrunningdisp(wire_receive_pcs2_xgmrunningdisp)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .elecidleinfersel({3{1'b0}}),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipe8b10binvpolarity(1'b0),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .powerdn({2{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .signaldetected(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs2.align_pattern = "0101111100",
+ receive_pcs2.align_pattern_length = 10,
+ receive_pcs2.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs2.allow_align_polarity_inversion = "true",
+ receive_pcs2.allow_pipe_polarity_inversion = "false",
+ receive_pcs2.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs2.auto_spd_phystatus_notify_count = 0,
+ receive_pcs2.auto_spd_self_switch_enable = "false",
+ receive_pcs2.bit_slip_enable = "false",
+ receive_pcs2.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs2.byte_order_mode = "none",
+ receive_pcs2.byte_order_pad_pattern = "0",
+ receive_pcs2.byte_order_pattern = "0",
+ receive_pcs2.byte_order_pld_ctrl_enable = "false",
+ receive_pcs2.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs2.cdrctrl_enable = "false",
+ receive_pcs2.cdrctrl_mask_cycle = 800,
+ receive_pcs2.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs2.cdrctrl_rxvalid_mask = "false",
+ receive_pcs2.channel_bonding = "x4",
+ receive_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pcs2.channel_width = 16,
+ receive_pcs2.clk1_mux_select = "master clock",
+ receive_pcs2.clk2_mux_select = "digital reference clock",
+ receive_pcs2.core_clock_0ppm = "true",
+ receive_pcs2.datapath_low_latency_mode = "false",
+ receive_pcs2.datapath_protocol = "xaui",
+ receive_pcs2.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs2.dec_8b_10b_mode = "normal",
+ receive_pcs2.dec_8b_10b_polarity_inv_enable = "false",
+ receive_pcs2.deskew_pattern = "0011000011",
+ receive_pcs2.disable_auto_idle_insertion = "true",
+ receive_pcs2.disable_running_disp_in_word_align = "false",
+ receive_pcs2.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs2.dprio_config_mode = 6'h01,
+ receive_pcs2.elec_idle_infer_enable = "false",
+ receive_pcs2.elec_idle_num_com_detect = 3,
+ receive_pcs2.enable_bit_reversal = "false",
+ receive_pcs2.enable_deep_align = "false",
+ receive_pcs2.enable_deep_align_byte_swap = "false",
+ receive_pcs2.enable_self_test_mode = "false",
+ receive_pcs2.enable_true_complement_match_in_word_align = "false",
+ receive_pcs2.force_signal_detect_dig = "true",
+ receive_pcs2.hip_enable = "false",
+ receive_pcs2.infiniband_invalid_code = 0,
+ receive_pcs2.insert_pad_on_underflow = "false",
+ receive_pcs2.logical_channel_address = (starting_channel_number + 2),
+ receive_pcs2.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs2.num_align_cons_good_data = 4,
+ receive_pcs2.num_align_cons_pat = 4,
+ receive_pcs2.num_align_loss_sync_error = 4,
+ receive_pcs2.ph_fifo_low_latency_enable = "true",
+ receive_pcs2.ph_fifo_reg_mode = "false",
+ receive_pcs2.ph_fifo_xn_mapping0 = "none",
+ receive_pcs2.ph_fifo_xn_mapping1 = "none",
+ receive_pcs2.ph_fifo_xn_mapping2 = "central",
+ receive_pcs2.ph_fifo_xn_select = 2,
+ receive_pcs2.pipe_auto_speed_nego_enable = "false",
+ receive_pcs2.pipe_freq_scale_mode = "Frequency",
+ receive_pcs2.pma_done_count = 249950,
+ receive_pcs2.protocol_hint = "xaui",
+ receive_pcs2.rate_match_almost_empty_threshold = 11,
+ receive_pcs2.rate_match_almost_full_threshold = 13,
+ receive_pcs2.rate_match_back_to_back = "true",
+ receive_pcs2.rate_match_delete_threshold = 13,
+ receive_pcs2.rate_match_empty_threshold = 5,
+ receive_pcs2.rate_match_fifo_mode = "true",
+ receive_pcs2.rate_match_full_threshold = 20,
+ receive_pcs2.rate_match_insert_threshold = 11,
+ receive_pcs2.rate_match_ordered_set_based = "false",
+ receive_pcs2.rate_match_pattern1 = "1101000011",
+ receive_pcs2.rate_match_pattern2 = "0010111100",
+ receive_pcs2.rate_match_pattern_size = 10,
+ receive_pcs2.rate_match_reset_enable = "false",
+ receive_pcs2.rate_match_skip_set_based = "false",
+ receive_pcs2.rate_match_start_threshold = 7,
+ receive_pcs2.rd_clk_mux_select = "core clock",
+ receive_pcs2.recovered_clk_mux_select = "recovered clock",
+ receive_pcs2.run_length = 40,
+ receive_pcs2.run_length_enable = "true",
+ receive_pcs2.rx_detect_bypass = "false",
+ receive_pcs2.rx_phfifo_wait_cnt = 15,
+ receive_pcs2.rxstatus_error_report_mode = 0,
+ receive_pcs2.self_test_mode = "incremental",
+ receive_pcs2.use_alignment_state_machine = "true",
+ receive_pcs2.use_deserializer_double_data_mode = "false",
+ receive_pcs2.use_deskew_fifo = "true",
+ receive_pcs2.use_double_data_mode = "true",
+ receive_pcs2.use_parallel_loopback = "false",
+ receive_pcs2.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs2.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs3
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(wire_receive_pcs3_adetectdeskew),
+ .alignstatus(rx_channelaligned_in[0]),
+ .alignstatussync(rx_alignstatussync[0]),
+ .alignstatussyncout(wire_receive_pcs3_alignstatussyncout),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefcl((reconfig_togxb_busy | rx_locktorefclk[3])),
+ .cdrctrllocktorefclkout(wire_receive_pcs3_cdrctrllocktorefclkout),
+ .clkout(wire_receive_pcs3_clkout),
+ .coreclk(rx_coreclk_in[3]),
+ .coreclkout(wire_receive_pcs3_coreclkout),
+ .ctrldetect(wire_receive_pcs3_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[79:60]),
+ .dataout(wire_receive_pcs3_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[3]),
+ .digitaltestout(),
+ .disablefifordin(rx_disablefifordin_in[0]),
+ .disablefifordout(wire_receive_pcs3_disablefifordout),
+ .disablefifowrin(rx_disablefifowrin_in[0]),
+ .disablefifowrout(wire_receive_pcs3_disablefifowrout),
+ .disperr(wire_receive_pcs3_disperr),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[1599:1200]),
+ .dprioout(wire_receive_pcs3_dprioout),
+ .enabledeskew(enabledeskew[0]),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[3]),
+ .errdetect(wire_receive_pcs3_errdetect),
+ .fifordin(rx_fifordin_in[0]),
+ .fifordout(wire_receive_pcs3_fifordout),
+ .fiforesetrd(rx_fiforesetrd[0]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(rx_invpolarity[3]),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(rx_masterclk[0]),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs3_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs3_phfifobyteserdisableout),
+ .phfifooverflow(wire_receive_pcs3_phfifooverflow),
+ .phfifoptrsresetout(wire_receive_pcs3_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[3]),
+ .phfifordenableout(wire_receive_pcs3_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[3]),
+ .phfiforesetout(wire_receive_pcs3_phfiforesetout),
+ .phfifounderflow(wire_receive_pcs3_phfifounderflow),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[3]),
+ .phfifowrdisableout(wire_receive_pcs3_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[11:9]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[11:9]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[11:9]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[11:9]),
+ .pipebufferstat(),
+ .pipedatavalid(),
+ .pipeelecidle(),
+ .pipephydonestatus(),
+ .pipepowerdown({2{1'b0}}),
+ .pipepowerstate({4{1'b0}}),
+ .pipestatetransdoneout(),
+ .pipestatus(),
+ .prbscidenable(rx_prbscidenable[3]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs3_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(wire_receive_pcs3_rdalign),
+ .recoveredclk(rx_pma_clockout[3]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(),
+ .rlv(wire_receive_pcs3_rlv),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(wire_receive_pcs3_rmfifodatadeleted),
+ .rmfifodatainserted(wire_receive_pcs3_rmfifodatainserted),
+ .rmfifoempty(wire_receive_pcs3_rmfifoempty),
+ .rmfifofull(wire_receive_pcs3_rmfifofull),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[3]),
+ .rmfifowrena(1'b0),
+ .runningdisp(wire_receive_pcs3_runningdisp),
+ .rxdetectvalid(1'b0),
+ .rxfound({2{1'b0}}),
+ .signaldetect(),
+ .syncstatus(wire_receive_pcs3_syncstatus),
+ .syncstatusdeskew(wire_receive_pcs3_syncstatusdeskew),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(wire_receive_pcs3_xgmctrldet),
+ .xgmctrlin(rx_xgmctrlin[3]),
+ .xgmdatain(cent_unit_rx_xgmdataout[31:24]),
+ .xgmdataout(wire_receive_pcs3_xgmdataout),
+ .xgmdatavalid(wire_receive_pcs3_xgmdatavalid),
+ .xgmrunningdisp(wire_receive_pcs3_xgmrunningdisp)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .elecidleinfersel({3{1'b0}}),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipe8b10binvpolarity(1'b0),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .powerdn({2{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .signaldetected(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs3.align_pattern = "0101111100",
+ receive_pcs3.align_pattern_length = 10,
+ receive_pcs3.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs3.allow_align_polarity_inversion = "true",
+ receive_pcs3.allow_pipe_polarity_inversion = "false",
+ receive_pcs3.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs3.auto_spd_phystatus_notify_count = 0,
+ receive_pcs3.auto_spd_self_switch_enable = "false",
+ receive_pcs3.bit_slip_enable = "false",
+ receive_pcs3.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs3.byte_order_mode = "none",
+ receive_pcs3.byte_order_pad_pattern = "0",
+ receive_pcs3.byte_order_pattern = "0",
+ receive_pcs3.byte_order_pld_ctrl_enable = "false",
+ receive_pcs3.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs3.cdrctrl_enable = "false",
+ receive_pcs3.cdrctrl_mask_cycle = 800,
+ receive_pcs3.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs3.cdrctrl_rxvalid_mask = "false",
+ receive_pcs3.channel_bonding = "x4",
+ receive_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pcs3.channel_width = 16,
+ receive_pcs3.clk1_mux_select = "master clock",
+ receive_pcs3.clk2_mux_select = "digital reference clock",
+ receive_pcs3.core_clock_0ppm = "true",
+ receive_pcs3.datapath_low_latency_mode = "false",
+ receive_pcs3.datapath_protocol = "xaui",
+ receive_pcs3.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs3.dec_8b_10b_mode = "normal",
+ receive_pcs3.dec_8b_10b_polarity_inv_enable = "false",
+ receive_pcs3.deskew_pattern = "0011000011",
+ receive_pcs3.disable_auto_idle_insertion = "true",
+ receive_pcs3.disable_running_disp_in_word_align = "false",
+ receive_pcs3.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs3.dprio_config_mode = 6'h01,
+ receive_pcs3.elec_idle_infer_enable = "false",
+ receive_pcs3.elec_idle_num_com_detect = 3,
+ receive_pcs3.enable_bit_reversal = "false",
+ receive_pcs3.enable_deep_align = "false",
+ receive_pcs3.enable_deep_align_byte_swap = "false",
+ receive_pcs3.enable_self_test_mode = "false",
+ receive_pcs3.enable_true_complement_match_in_word_align = "false",
+ receive_pcs3.force_signal_detect_dig = "true",
+ receive_pcs3.hip_enable = "false",
+ receive_pcs3.infiniband_invalid_code = 0,
+ receive_pcs3.insert_pad_on_underflow = "false",
+ receive_pcs3.logical_channel_address = (starting_channel_number + 3),
+ receive_pcs3.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs3.num_align_cons_good_data = 4,
+ receive_pcs3.num_align_cons_pat = 4,
+ receive_pcs3.num_align_loss_sync_error = 4,
+ receive_pcs3.ph_fifo_low_latency_enable = "true",
+ receive_pcs3.ph_fifo_reg_mode = "false",
+ receive_pcs3.ph_fifo_xn_mapping0 = "none",
+ receive_pcs3.ph_fifo_xn_mapping1 = "none",
+ receive_pcs3.ph_fifo_xn_mapping2 = "central",
+ receive_pcs3.ph_fifo_xn_select = 2,
+ receive_pcs3.pipe_auto_speed_nego_enable = "false",
+ receive_pcs3.pipe_freq_scale_mode = "Frequency",
+ receive_pcs3.pma_done_count = 249950,
+ receive_pcs3.protocol_hint = "xaui",
+ receive_pcs3.rate_match_almost_empty_threshold = 11,
+ receive_pcs3.rate_match_almost_full_threshold = 13,
+ receive_pcs3.rate_match_back_to_back = "true",
+ receive_pcs3.rate_match_delete_threshold = 13,
+ receive_pcs3.rate_match_empty_threshold = 5,
+ receive_pcs3.rate_match_fifo_mode = "true",
+ receive_pcs3.rate_match_full_threshold = 20,
+ receive_pcs3.rate_match_insert_threshold = 11,
+ receive_pcs3.rate_match_ordered_set_based = "false",
+ receive_pcs3.rate_match_pattern1 = "1101000011",
+ receive_pcs3.rate_match_pattern2 = "0010111100",
+ receive_pcs3.rate_match_pattern_size = 10,
+ receive_pcs3.rate_match_reset_enable = "false",
+ receive_pcs3.rate_match_skip_set_based = "false",
+ receive_pcs3.rate_match_start_threshold = 7,
+ receive_pcs3.rd_clk_mux_select = "core clock",
+ receive_pcs3.recovered_clk_mux_select = "recovered clock",
+ receive_pcs3.run_length = 40,
+ receive_pcs3.run_length_enable = "true",
+ receive_pcs3.rx_detect_bypass = "false",
+ receive_pcs3.rx_phfifo_wait_cnt = 15,
+ receive_pcs3.rxstatus_error_report_mode = 0,
+ receive_pcs3.self_test_mode = "incremental",
+ receive_pcs3.use_alignment_state_machine = "true",
+ receive_pcs3.use_deserializer_double_data_mode = "false",
+ receive_pcs3.use_deskew_fifo = "true",
+ receive_pcs3.use_double_data_mode = "true",
+ receive_pcs3.use_parallel_loopback = "false",
+ receive_pcs3.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs3.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pma receive_pma0
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma0_analogtestbus),
+ .clockout(wire_receive_pma0_clockout),
+ .datain(rx_datain[0]),
+ .dataout(wire_receive_pma0_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[3:0]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[299:0]),
+ .dprioout(wire_receive_pma0_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[0]),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[0]),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdatain(pll_ch_dataout_wire[1:0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbken(rx_seriallpbken[0]),
+ .seriallpbkin(tx_serialloopbackout[0]),
+ .signaldetect(wire_receive_pma0_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.adaptive_equalization_mode = "none",
+ receive_pma0.allow_serial_loopback = "true",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pma0.channel_type = "auto",
+ receive_pma0.common_mode = rx_common_mode,
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.dprio_config_mode = 6'h01,
+ receive_pma0.enable_ltd = "true",
+ receive_pma0.enable_ltr = "true",
+ receive_pma0.eq_dc_gain = equalizer_dcgain_setting,
+ receive_pma0.eqa_ctrl = equalizer_ctrl_a_setting,
+ receive_pma0.eqb_ctrl = equalizer_ctrl_b_setting,
+ receive_pma0.eqc_ctrl = equalizer_ctrl_c_setting,
+ receive_pma0.eqd_ctrl = equalizer_ctrl_d_setting,
+ receive_pma0.eqv_ctrl = equalizer_ctrl_v_setting,
+ receive_pma0.eyemon_bandwidth = 0,
+ receive_pma0.force_signal_detect = "true",
+ receive_pma0.logical_channel_address = (starting_channel_number + 0),
+ receive_pma0.low_speed_test_select = 0,
+ receive_pma0.offset_cancellation = 1,
+ receive_pma0.ppmselect = 32,
+ receive_pma0.protocol_hint = "xaui",
+ receive_pma0.send_direct_reverse_serial_loopback = "None",
+ receive_pma0.signal_detect_hysteresis = 2,
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 1,
+ receive_pma0.signal_detect_loss_threshold = 1,
+ receive_pma0.termination = receiver_termination,
+ receive_pma0.use_deser_double_data_width = "false",
+ receive_pma0.use_external_termination = "false",
+ receive_pma0.use_pma_direct = "false",
+ receive_pma0.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma1
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma1_analogtestbus),
+ .clockout(wire_receive_pma1_clockout),
+ .datain(rx_datain[1]),
+ .dataout(wire_receive_pma1_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[7:4]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[599:300]),
+ .dprioout(wire_receive_pma1_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[1]),
+ .locktoref(rx_locktorefclk_wire[1]),
+ .locktorefout(wire_receive_pma1_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[1]),
+ .powerdn(cent_unit_rxibpowerdn[1]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[1]),
+ .recoverdatain(pll_ch_dataout_wire[3:2]),
+ .recoverdataout(wire_receive_pma1_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[1]),
+ .seriallpbken(rx_seriallpbken[1]),
+ .seriallpbkin(tx_serialloopbackout[1]),
+ .signaldetect(wire_receive_pma1_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma1.adaptive_equalization_mode = "none",
+ receive_pma1.allow_serial_loopback = "true",
+ receive_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pma1.channel_type = "auto",
+ receive_pma1.common_mode = rx_common_mode,
+ receive_pma1.deserialization_factor = 10,
+ receive_pma1.dprio_config_mode = 6'h01,
+ receive_pma1.enable_ltd = "true",
+ receive_pma1.enable_ltr = "true",
+ receive_pma1.eq_dc_gain = equalizer_dcgain_setting,
+ receive_pma1.eqa_ctrl = equalizer_ctrl_a_setting,
+ receive_pma1.eqb_ctrl = equalizer_ctrl_b_setting,
+ receive_pma1.eqc_ctrl = equalizer_ctrl_c_setting,
+ receive_pma1.eqd_ctrl = equalizer_ctrl_d_setting,
+ receive_pma1.eqv_ctrl = equalizer_ctrl_v_setting,
+ receive_pma1.eyemon_bandwidth = 0,
+ receive_pma1.force_signal_detect = "true",
+ receive_pma1.logical_channel_address = (starting_channel_number + 1),
+ receive_pma1.low_speed_test_select = 0,
+ receive_pma1.offset_cancellation = 1,
+ receive_pma1.ppmselect = 32,
+ receive_pma1.protocol_hint = "xaui",
+ receive_pma1.send_direct_reverse_serial_loopback = "None",
+ receive_pma1.signal_detect_hysteresis = 2,
+ receive_pma1.signal_detect_hysteresis_valid_threshold = 1,
+ receive_pma1.signal_detect_loss_threshold = 1,
+ receive_pma1.termination = receiver_termination,
+ receive_pma1.use_deser_double_data_width = "false",
+ receive_pma1.use_external_termination = "false",
+ receive_pma1.use_pma_direct = "false",
+ receive_pma1.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma2
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma2_analogtestbus),
+ .clockout(wire_receive_pma2_clockout),
+ .datain(rx_datain[2]),
+ .dataout(wire_receive_pma2_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[11:8]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[899:600]),
+ .dprioout(wire_receive_pma2_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[2]),
+ .locktoref(rx_locktorefclk_wire[2]),
+ .locktorefout(wire_receive_pma2_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[2]),
+ .powerdn(cent_unit_rxibpowerdn[2]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[2]),
+ .recoverdatain(pll_ch_dataout_wire[5:4]),
+ .recoverdataout(wire_receive_pma2_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[2]),
+ .seriallpbken(rx_seriallpbken[2]),
+ .seriallpbkin(tx_serialloopbackout[2]),
+ .signaldetect(wire_receive_pma2_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma2.adaptive_equalization_mode = "none",
+ receive_pma2.allow_serial_loopback = "true",
+ receive_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pma2.channel_type = "auto",
+ receive_pma2.common_mode = rx_common_mode,
+ receive_pma2.deserialization_factor = 10,
+ receive_pma2.dprio_config_mode = 6'h01,
+ receive_pma2.enable_ltd = "true",
+ receive_pma2.enable_ltr = "true",
+ receive_pma2.eq_dc_gain = equalizer_dcgain_setting,
+ receive_pma2.eqa_ctrl = equalizer_ctrl_a_setting,
+ receive_pma2.eqb_ctrl = equalizer_ctrl_b_setting,
+ receive_pma2.eqc_ctrl = equalizer_ctrl_c_setting,
+ receive_pma2.eqd_ctrl = equalizer_ctrl_d_setting,
+ receive_pma2.eqv_ctrl = equalizer_ctrl_v_setting,
+ receive_pma2.eyemon_bandwidth = 0,
+ receive_pma2.force_signal_detect = "true",
+ receive_pma2.logical_channel_address = (starting_channel_number + 2),
+ receive_pma2.low_speed_test_select = 0,
+ receive_pma2.offset_cancellation = 1,
+ receive_pma2.ppmselect = 32,
+ receive_pma2.protocol_hint = "xaui",
+ receive_pma2.send_direct_reverse_serial_loopback = "None",
+ receive_pma2.signal_detect_hysteresis = 2,
+ receive_pma2.signal_detect_hysteresis_valid_threshold = 1,
+ receive_pma2.signal_detect_loss_threshold = 1,
+ receive_pma2.termination = receiver_termination,
+ receive_pma2.use_deser_double_data_width = "false",
+ receive_pma2.use_external_termination = "false",
+ receive_pma2.use_pma_direct = "false",
+ receive_pma2.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma3
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma3_analogtestbus),
+ .clockout(wire_receive_pma3_clockout),
+ .datain(rx_datain[3]),
+ .dataout(wire_receive_pma3_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[15:12]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[1199:900]),
+ .dprioout(wire_receive_pma3_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[3]),
+ .locktoref(rx_locktorefclk_wire[3]),
+ .locktorefout(wire_receive_pma3_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[3]),
+ .powerdn(cent_unit_rxibpowerdn[3]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[3]),
+ .recoverdatain(pll_ch_dataout_wire[7:6]),
+ .recoverdataout(wire_receive_pma3_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[3]),
+ .seriallpbken(rx_seriallpbken[3]),
+ .seriallpbkin(tx_serialloopbackout[3]),
+ .signaldetect(wire_receive_pma3_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma3.adaptive_equalization_mode = "none",
+ receive_pma3.allow_serial_loopback = "true",
+ receive_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pma3.channel_type = "auto",
+ receive_pma3.common_mode = rx_common_mode,
+ receive_pma3.deserialization_factor = 10,
+ receive_pma3.dprio_config_mode = 6'h01,
+ receive_pma3.enable_ltd = "true",
+ receive_pma3.enable_ltr = "true",
+ receive_pma3.eq_dc_gain = equalizer_dcgain_setting,
+ receive_pma3.eqa_ctrl = equalizer_ctrl_a_setting,
+ receive_pma3.eqb_ctrl = equalizer_ctrl_b_setting,
+ receive_pma3.eqc_ctrl = equalizer_ctrl_c_setting,
+ receive_pma3.eqd_ctrl = equalizer_ctrl_d_setting,
+ receive_pma3.eqv_ctrl = equalizer_ctrl_v_setting,
+ receive_pma3.eyemon_bandwidth = 0,
+ receive_pma3.force_signal_detect = "true",
+ receive_pma3.logical_channel_address = (starting_channel_number + 3),
+ receive_pma3.low_speed_test_select = 0,
+ receive_pma3.offset_cancellation = 1,
+ receive_pma3.ppmselect = 32,
+ receive_pma3.protocol_hint = "xaui",
+ receive_pma3.send_direct_reverse_serial_loopback = "None",
+ receive_pma3.signal_detect_hysteresis = 2,
+ receive_pma3.signal_detect_hysteresis_valid_threshold = 1,
+ receive_pma3.signal_detect_loss_threshold = 1,
+ receive_pma3.termination = receiver_termination,
+ receive_pma3.use_deser_double_data_width = "false",
+ receive_pma3.use_external_termination = "false",
+ receive_pma3.use_pma_direct = "false",
+ receive_pma3.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(wire_transmit_pcs0_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[1:0]}),
+ .datain({{24{1'b0}}, tx_datain_wire[15:0]}),
+ .datainfull({44{1'b0}}),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(1'b0),
+ .digitalreset(tx_digitalreset_out[0]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[149:0]),
+ .dprioout(wire_transmit_pcs0_dprioout),
+ .enrevparallellpbk(1'b0),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[1:0]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidleout(wire_transmit_pcs0_forceelecidleout),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[0]),
+ .phfifooverflow(wire_transmit_pcs0_phfifooverflow),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[0]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(wire_transmit_pcs0_phfiforesetout),
+ .phfifounderflow(wire_transmit_pcs0_phfifounderflow),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[2:0]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[2:0]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[2:0]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[2:0]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(),
+ .pipepowerstateout(),
+ .pipestatetransdone(1'b0),
+ .powerdn({2{1'b0}}),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(wire_transmit_pcs0_rdenablesync),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk({20{1'b0}}),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[0]),
+ .xgmctrlenable(wire_transmit_pcs0_xgmctrlenable),
+ .xgmdatain(cent_unit_tx_xgmdataout[7:0]),
+ .xgmdataout(wire_transmit_pcs0_xgmdataout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .dispval({4{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .forceelecidle(1'b0),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .pipetxdeemph(1'b0),
+ .pipetxmargin({3{1'b0}}),
+ .pipetxswing(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "true",
+ transmit_pcs0.auto_spd_self_switch_enable = "false",
+ transmit_pcs0.bitslip_enable = "false",
+ transmit_pcs0.channel_bonding = "x4",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pcs0.channel_width = 16,
+ transmit_pcs0.core_clock_0ppm = "true",
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "xaui",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "none",
+ transmit_pcs0.dprio_config_mode = 6'h01,
+ transmit_pcs0.elec_idle_delay = 6,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "false",
+ transmit_pcs0.enable_reverse_parallel_loopback = "false",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enable_symbol_swap = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.force_echar = "false",
+ transmit_pcs0.force_kchar = "false",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs0.ph_fifo_xn_select = 2,
+ transmit_pcs0.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs0.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "xaui",
+ transmit_pcs0.refclk_select = "cmu_clock_divider",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "true",
+ transmit_pcs0.use_serializer_double_data_mode = "false",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs1
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[1]),
+ .coreclkout(wire_transmit_pcs1_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[3:2]}),
+ .datain({{24{1'b0}}, tx_datain_wire[31:16]}),
+ .datainfull({44{1'b0}}),
+ .dataout(wire_transmit_pcs1_dataout),
+ .detectrxloop(1'b0),
+ .digitalreset(tx_digitalreset_out[1]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[299:150]),
+ .dprioout(wire_transmit_pcs1_dprioout),
+ .enrevparallellpbk(1'b0),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[3:2]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidleout(wire_transmit_pcs1_forceelecidleout),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[1]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[1]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[1]),
+ .phfifooverflow(wire_transmit_pcs1_phfifooverflow),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[1]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[1]),
+ .phfiforesetout(wire_transmit_pcs1_phfiforesetout),
+ .phfifounderflow(wire_transmit_pcs1_phfifounderflow),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[5:3]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[5:3]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[5:3]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[5:3]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(),
+ .pipepowerstateout(),
+ .pipestatetransdone(1'b0),
+ .powerdn({2{1'b0}}),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(wire_transmit_pcs1_rdenablesync),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk({20{1'b0}}),
+ .txdetectrx(wire_transmit_pcs1_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[1]),
+ .xgmctrlenable(wire_transmit_pcs1_xgmctrlenable),
+ .xgmdatain(cent_unit_tx_xgmdataout[15:8]),
+ .xgmdataout(wire_transmit_pcs1_xgmdataout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .dispval({4{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .forceelecidle(1'b0),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .pipetxdeemph(1'b0),
+ .pipetxmargin({3{1'b0}}),
+ .pipetxswing(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs1.allow_polarity_inversion = "true",
+ transmit_pcs1.auto_spd_self_switch_enable = "false",
+ transmit_pcs1.bitslip_enable = "false",
+ transmit_pcs1.channel_bonding = "x4",
+ transmit_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pcs1.channel_width = 16,
+ transmit_pcs1.core_clock_0ppm = "true",
+ transmit_pcs1.datapath_low_latency_mode = "false",
+ transmit_pcs1.datapath_protocol = "xaui",
+ transmit_pcs1.disable_ph_low_latency_mode = "false",
+ transmit_pcs1.disparity_mode = "none",
+ transmit_pcs1.dprio_config_mode = 6'h01,
+ transmit_pcs1.elec_idle_delay = 6,
+ transmit_pcs1.enable_bit_reversal = "false",
+ transmit_pcs1.enable_idle_selection = "false",
+ transmit_pcs1.enable_reverse_parallel_loopback = "false",
+ transmit_pcs1.enable_self_test_mode = "false",
+ transmit_pcs1.enable_symbol_swap = "false",
+ transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs1.enc_8b_10b_mode = "normal",
+ transmit_pcs1.force_echar = "false",
+ transmit_pcs1.force_kchar = "false",
+ transmit_pcs1.hip_enable = "false",
+ transmit_pcs1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pcs1.ph_fifo_reg_mode = "false",
+ transmit_pcs1.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs1.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs1.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs1.ph_fifo_xn_select = 2,
+ transmit_pcs1.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs1.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs1.prbs_cid_pattern = "false",
+ transmit_pcs1.protocol_hint = "xaui",
+ transmit_pcs1.refclk_select = "cmu_clock_divider",
+ transmit_pcs1.self_test_mode = "incremental",
+ transmit_pcs1.use_double_data_mode = "true",
+ transmit_pcs1.use_serializer_double_data_mode = "false",
+ transmit_pcs1.wr_clk_mux_select = "core_clk",
+ transmit_pcs1.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs2
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[2]),
+ .coreclkout(wire_transmit_pcs2_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[5:4]}),
+ .datain({{24{1'b0}}, tx_datain_wire[47:32]}),
+ .datainfull({44{1'b0}}),
+ .dataout(wire_transmit_pcs2_dataout),
+ .detectrxloop(1'b0),
+ .digitalreset(tx_digitalreset_out[2]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[449:300]),
+ .dprioout(wire_transmit_pcs2_dprioout),
+ .enrevparallellpbk(1'b0),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[5:4]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidleout(wire_transmit_pcs2_forceelecidleout),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[2]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[2]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[2]),
+ .phfifooverflow(wire_transmit_pcs2_phfifooverflow),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[2]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs2_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[2]),
+ .phfiforesetout(wire_transmit_pcs2_phfiforesetout),
+ .phfifounderflow(wire_transmit_pcs2_phfifounderflow),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs2_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[8:6]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[8:6]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[8:6]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[8:6]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(),
+ .pipepowerstateout(),
+ .pipestatetransdone(1'b0),
+ .powerdn({2{1'b0}}),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(wire_transmit_pcs2_rdenablesync),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk({20{1'b0}}),
+ .txdetectrx(wire_transmit_pcs2_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[2]),
+ .xgmctrlenable(wire_transmit_pcs2_xgmctrlenable),
+ .xgmdatain(cent_unit_tx_xgmdataout[23:16]),
+ .xgmdataout(wire_transmit_pcs2_xgmdataout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .dispval({4{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .forceelecidle(1'b0),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .pipetxdeemph(1'b0),
+ .pipetxmargin({3{1'b0}}),
+ .pipetxswing(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs2.allow_polarity_inversion = "true",
+ transmit_pcs2.auto_spd_self_switch_enable = "false",
+ transmit_pcs2.bitslip_enable = "false",
+ transmit_pcs2.channel_bonding = "x4",
+ transmit_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pcs2.channel_width = 16,
+ transmit_pcs2.core_clock_0ppm = "true",
+ transmit_pcs2.datapath_low_latency_mode = "false",
+ transmit_pcs2.datapath_protocol = "xaui",
+ transmit_pcs2.disable_ph_low_latency_mode = "false",
+ transmit_pcs2.disparity_mode = "none",
+ transmit_pcs2.dprio_config_mode = 6'h01,
+ transmit_pcs2.elec_idle_delay = 6,
+ transmit_pcs2.enable_bit_reversal = "false",
+ transmit_pcs2.enable_idle_selection = "false",
+ transmit_pcs2.enable_reverse_parallel_loopback = "false",
+ transmit_pcs2.enable_self_test_mode = "false",
+ transmit_pcs2.enable_symbol_swap = "false",
+ transmit_pcs2.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs2.enc_8b_10b_mode = "normal",
+ transmit_pcs2.force_echar = "false",
+ transmit_pcs2.force_kchar = "false",
+ transmit_pcs2.hip_enable = "false",
+ transmit_pcs2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pcs2.ph_fifo_reg_mode = "false",
+ transmit_pcs2.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs2.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs2.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs2.ph_fifo_xn_select = 2,
+ transmit_pcs2.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs2.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs2.prbs_cid_pattern = "false",
+ transmit_pcs2.protocol_hint = "xaui",
+ transmit_pcs2.refclk_select = "cmu_clock_divider",
+ transmit_pcs2.self_test_mode = "incremental",
+ transmit_pcs2.use_double_data_mode = "true",
+ transmit_pcs2.use_serializer_double_data_mode = "false",
+ transmit_pcs2.wr_clk_mux_select = "core_clk",
+ transmit_pcs2.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs3
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[3]),
+ .coreclkout(wire_transmit_pcs3_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[7:6]}),
+ .datain({{24{1'b0}}, tx_datain_wire[63:48]}),
+ .datainfull({44{1'b0}}),
+ .dataout(wire_transmit_pcs3_dataout),
+ .detectrxloop(1'b0),
+ .digitalreset(tx_digitalreset_out[3]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[599:450]),
+ .dprioout(wire_transmit_pcs3_dprioout),
+ .enrevparallellpbk(1'b0),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[7:6]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidleout(wire_transmit_pcs3_forceelecidleout),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[3]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[3]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[3]),
+ .phfifooverflow(wire_transmit_pcs3_phfifooverflow),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[3]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs3_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[3]),
+ .phfiforesetout(wire_transmit_pcs3_phfiforesetout),
+ .phfifounderflow(wire_transmit_pcs3_phfifounderflow),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs3_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[11:9]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[11:9]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[11:9]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[11:9]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(),
+ .pipepowerstateout(),
+ .pipestatetransdone(1'b0),
+ .powerdn({2{1'b0}}),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(wire_transmit_pcs3_rdenablesync),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk({20{1'b0}}),
+ .txdetectrx(wire_transmit_pcs3_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[3]),
+ .xgmctrlenable(wire_transmit_pcs3_xgmctrlenable),
+ .xgmdatain(cent_unit_tx_xgmdataout[31:24]),
+ .xgmdataout(wire_transmit_pcs3_xgmdataout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .dispval({4{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .forceelecidle(1'b0),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .pipetxdeemph(1'b0),
+ .pipetxmargin({3{1'b0}}),
+ .pipetxswing(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs3.allow_polarity_inversion = "true",
+ transmit_pcs3.auto_spd_self_switch_enable = "false",
+ transmit_pcs3.bitslip_enable = "false",
+ transmit_pcs3.channel_bonding = "x4",
+ transmit_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pcs3.channel_width = 16,
+ transmit_pcs3.core_clock_0ppm = "true",
+ transmit_pcs3.datapath_low_latency_mode = "false",
+ transmit_pcs3.datapath_protocol = "xaui",
+ transmit_pcs3.disable_ph_low_latency_mode = "false",
+ transmit_pcs3.disparity_mode = "none",
+ transmit_pcs3.dprio_config_mode = 6'h01,
+ transmit_pcs3.elec_idle_delay = 6,
+ transmit_pcs3.enable_bit_reversal = "false",
+ transmit_pcs3.enable_idle_selection = "false",
+ transmit_pcs3.enable_reverse_parallel_loopback = "false",
+ transmit_pcs3.enable_self_test_mode = "false",
+ transmit_pcs3.enable_symbol_swap = "false",
+ transmit_pcs3.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs3.enc_8b_10b_mode = "normal",
+ transmit_pcs3.force_echar = "false",
+ transmit_pcs3.force_kchar = "false",
+ transmit_pcs3.hip_enable = "false",
+ transmit_pcs3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pcs3.ph_fifo_reg_mode = "false",
+ transmit_pcs3.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs3.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs3.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs3.ph_fifo_xn_select = 2,
+ transmit_pcs3.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs3.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs3.prbs_cid_pattern = "false",
+ transmit_pcs3.protocol_hint = "xaui",
+ transmit_pcs3.refclk_select = "cmu_clock_divider",
+ transmit_pcs3.self_test_mode = "incremental",
+ transmit_pcs3.use_double_data_mode = "true",
+ transmit_pcs3.use_serializer_double_data_mode = "false",
+ transmit_pcs3.wr_clk_mux_select = "core_clk",
+ transmit_pcs3.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pma transmit_pma0
+ (
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[19:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[299:0]),
+ .dprioout(wire_transmit_pma0_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(1'b0),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(),
+ .rxfoundout(),
+ .seriallpbkout(wire_transmit_pma0_seriallpbkout),
+ .txpmareset(tx_analogreset_out[0])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.analog_power = "auto",
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pma0.channel_type = "auto",
+ transmit_pma0.clkin_select = 1,
+ transmit_pma0.clkmux_delay = "false",
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.dprio_config_mode = 6'h01,
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pma0.logical_protocol_hint_0 = "xaui",
+ transmit_pma0.low_speed_test_select = 0,
+ transmit_pma0.physical_clkin1_mapping = "x4",
+ transmit_pma0.preemp_pretap = preemphasis_ctrl_pretap_setting,
+ transmit_pma0.preemp_pretap_inv = preemphasis_ctrl_pretap_inv_setting,
+ transmit_pma0.preemp_tap_1 = preemphasis_ctrl_1stposttap_setting,
+ transmit_pma0.preemp_tap_2 = preemphasis_ctrl_2ndposttap_setting,
+ transmit_pma0.preemp_tap_2_inv = preemphasis_ctrl_2ndposttap_inv_setting,
+ transmit_pma0.protocol_hint = "xaui",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "low",
+ transmit_pma0.termination = transmitter_termination,
+ transmit_pma0.use_external_termination = "false",
+ transmit_pma0.use_pma_direct = "false",
+ transmit_pma0.use_ser_double_data_mode = "false",
+ transmit_pma0.vod_selection = vod_ctrl_setting,
+ transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma1
+ (
+ .clockout(wire_transmit_pma1_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[39:20]}),
+ .dataout(wire_transmit_pma1_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[599:300]),
+ .dprioout(wire_transmit_pma1_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(1'b0),
+ .powerdn(cent_unit_txobpowerdn[1]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[1]),
+ .rxdetectvalidout(),
+ .rxfoundout(),
+ .seriallpbkout(wire_transmit_pma1_seriallpbkout),
+ .txpmareset(tx_analogreset_out[1])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma1.analog_power = "auto",
+ transmit_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pma1.channel_type = "auto",
+ transmit_pma1.clkin_select = 1,
+ transmit_pma1.clkmux_delay = "false",
+ transmit_pma1.common_mode = "0.65V",
+ transmit_pma1.dprio_config_mode = 6'h01,
+ transmit_pma1.enable_reverse_serial_loopback = "false",
+ transmit_pma1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pma1.logical_protocol_hint_0 = "xaui",
+ transmit_pma1.low_speed_test_select = 0,
+ transmit_pma1.physical_clkin1_mapping = "x4",
+ transmit_pma1.preemp_pretap = preemphasis_ctrl_pretap_setting,
+ transmit_pma1.preemp_pretap_inv = preemphasis_ctrl_pretap_inv_setting,
+ transmit_pma1.preemp_tap_1 = preemphasis_ctrl_1stposttap_setting,
+ transmit_pma1.preemp_tap_2 = preemphasis_ctrl_2ndposttap_setting,
+ transmit_pma1.preemp_tap_2_inv = preemphasis_ctrl_2ndposttap_inv_setting,
+ transmit_pma1.protocol_hint = "xaui",
+ transmit_pma1.rx_detect = 0,
+ transmit_pma1.serialization_factor = 10,
+ transmit_pma1.slew_rate = "low",
+ transmit_pma1.termination = transmitter_termination,
+ transmit_pma1.use_external_termination = "false",
+ transmit_pma1.use_pma_direct = "false",
+ transmit_pma1.use_ser_double_data_mode = "false",
+ transmit_pma1.vod_selection = vod_ctrl_setting,
+ transmit_pma1.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma2
+ (
+ .clockout(wire_transmit_pma2_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[59:40]}),
+ .dataout(wire_transmit_pma2_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[2]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[899:600]),
+ .dprioout(wire_transmit_pma2_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(1'b0),
+ .powerdn(cent_unit_txobpowerdn[2]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[2]),
+ .rxdetectvalidout(),
+ .rxfoundout(),
+ .seriallpbkout(wire_transmit_pma2_seriallpbkout),
+ .txpmareset(tx_analogreset_out[2])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma2.analog_power = "auto",
+ transmit_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pma2.channel_type = "auto",
+ transmit_pma2.clkin_select = 1,
+ transmit_pma2.clkmux_delay = "false",
+ transmit_pma2.common_mode = "0.65V",
+ transmit_pma2.dprio_config_mode = 6'h01,
+ transmit_pma2.enable_reverse_serial_loopback = "false",
+ transmit_pma2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pma2.logical_protocol_hint_0 = "xaui",
+ transmit_pma2.low_speed_test_select = 0,
+ transmit_pma2.physical_clkin1_mapping = "x4",
+ transmit_pma2.preemp_pretap = preemphasis_ctrl_pretap_setting,
+ transmit_pma2.preemp_pretap_inv = preemphasis_ctrl_pretap_inv_setting,
+ transmit_pma2.preemp_tap_1 = preemphasis_ctrl_1stposttap_setting,
+ transmit_pma2.preemp_tap_2 = preemphasis_ctrl_2ndposttap_setting,
+ transmit_pma2.preemp_tap_2_inv = preemphasis_ctrl_2ndposttap_inv_setting,
+ transmit_pma2.protocol_hint = "xaui",
+ transmit_pma2.rx_detect = 0,
+ transmit_pma2.serialization_factor = 10,
+ transmit_pma2.slew_rate = "low",
+ transmit_pma2.termination = transmitter_termination,
+ transmit_pma2.use_external_termination = "false",
+ transmit_pma2.use_pma_direct = "false",
+ transmit_pma2.use_ser_double_data_mode = "false",
+ transmit_pma2.vod_selection = vod_ctrl_setting,
+ transmit_pma2.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma3
+ (
+ .clockout(wire_transmit_pma3_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[79:60]}),
+ .dataout(wire_transmit_pma3_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[3]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[1199:900]),
+ .dprioout(wire_transmit_pma3_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(1'b0),
+ .powerdn(cent_unit_txobpowerdn[3]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[3]),
+ .rxdetectvalidout(),
+ .rxfoundout(),
+ .seriallpbkout(wire_transmit_pma3_seriallpbkout),
+ .txpmareset(tx_analogreset_out[3])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma3.analog_power = "auto",
+ transmit_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pma3.channel_type = "auto",
+ transmit_pma3.clkin_select = 1,
+ transmit_pma3.clkmux_delay = "false",
+ transmit_pma3.common_mode = "0.65V",
+ transmit_pma3.dprio_config_mode = 6'h01,
+ transmit_pma3.enable_reverse_serial_loopback = "false",
+ transmit_pma3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pma3.logical_protocol_hint_0 = "xaui",
+ transmit_pma3.low_speed_test_select = 0,
+ transmit_pma3.physical_clkin1_mapping = "x4",
+ transmit_pma3.preemp_pretap = preemphasis_ctrl_pretap_setting,
+ transmit_pma3.preemp_pretap_inv = preemphasis_ctrl_pretap_inv_setting,
+ transmit_pma3.preemp_tap_1 = preemphasis_ctrl_1stposttap_setting,
+ transmit_pma3.preemp_tap_2 = preemphasis_ctrl_2ndposttap_setting,
+ transmit_pma3.preemp_tap_2_inv = preemphasis_ctrl_2ndposttap_inv_setting,
+ transmit_pma3.protocol_hint = "xaui",
+ transmit_pma3.rx_detect = 0,
+ transmit_pma3.serialization_factor = 10,
+ transmit_pma3.slew_rate = "low",
+ transmit_pma3.termination = transmitter_termination,
+ transmit_pma3.use_external_termination = "false",
+ transmit_pma3.use_pma_direct = "false",
+ transmit_pma3.use_ser_double_data_mode = "false",
+ transmit_pma3.vod_selection = vod_ctrl_setting,
+ transmit_pma3.lpm_type = "stratixiv_hssi_tx_pma";
+ assign
+ cent_unit_clkdivpowerdn = {wire_cent_unit0_clkdivpowerdn[0]},
+ cent_unit_cmudividerdprioout = {wire_cent_unit0_cmudividerdprioout},
+ cent_unit_cmuplldprioout = {wire_cent_unit0_cmuplldprioout},
+ cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]},
+ cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]},
+ cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
+ cent_unit_rdenablesync = {tx_rdenablesync[0]},
+ cent_unit_rx_ctrl = {wire_receive_pcs3_xgmctrldet, wire_receive_pcs2_xgmctrldet, wire_receive_pcs1_xgmctrldet, wire_receive_pcs0_xgmctrldet},
+ cent_unit_rx_xgmdataout = {wire_cent_unit0_rxdataout},
+ cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]},
+ cent_unit_rxpcsdprioin = {rx_pcsdprioout[1599:0]},
+ cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout[1599:0]},
+ cent_unit_rxpmadprioin = {{2{{300{1'b0}}}}, rx_pmadprioout[1199:0]},
+ cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout[1799:0]},
+ cent_unit_tx_dprioin = {{600{1'b0}}, tx_txdprioout[599:0]},
+ cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout[31:0]},
+ cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[5:0]},
+ cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout[599:0]},
+ cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
+ cent_unit_txpmadprioin = {{2{{300{1'b0}}}}, tx_pmadprioout[1199:0]},
+ cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout[1799:0]},
+ clk_div_clk0in = {pll0_out[3:0]},
+ clk_div_cmudividerdprioin = {{100{1'b0}}, wire_central_clk_div0_dprioout, {400{1'b0}}},
+ cmu_analogfastrefclkout = {wire_central_clk_div0_analogfastrefclkout},
+ cmu_analogrefclkout = {wire_central_clk_div0_analogrefclkout},
+ cmu_analogrefclkpulse = {wire_central_clk_div0_analogrefclkpulse},
+ coreclkout = {coreclkout_wire[0]},
+ coreclkout_wire = {wire_central_clk_div0_coreclkout},
+ enabledeskew = {wire_cent_unit0_enabledeskew},
+ fixedclk_to_cmu = {6{reconfig_clk}},
+ int_hiprateswtichdone = {wire_central_clk_div0_rateswitchdone},
+ int_rx_coreclkout = {wire_receive_pcs3_coreclkout, wire_receive_pcs2_coreclkout, wire_receive_pcs1_coreclkout, wire_receive_pcs0_coreclkout},
+ int_rx_digitalreset_reg = {rx_digitalreset_reg0c[2]},
+ int_rx_phfifobyteserdisable = {wire_receive_pcs3_phfifobyteserdisableout, wire_receive_pcs2_phfifobyteserdisableout, wire_receive_pcs1_phfifobyteserdisableout, wire_receive_pcs0_phfifobyteserdisableout},
+ int_rx_phfifoptrsresetout = {wire_receive_pcs3_phfifoptrsresetout, wire_receive_pcs2_phfifoptrsresetout, wire_receive_pcs1_phfifoptrsresetout, wire_receive_pcs0_phfifoptrsresetout},
+ int_rx_phfifordenableout = {wire_receive_pcs3_phfifordenableout, wire_receive_pcs2_phfifordenableout, wire_receive_pcs1_phfifordenableout, wire_receive_pcs0_phfifordenableout},
+ int_rx_phfiforesetout = {wire_receive_pcs3_phfiforesetout, wire_receive_pcs2_phfiforesetout, wire_receive_pcs1_phfiforesetout, wire_receive_pcs0_phfiforesetout},
+ int_rx_phfifowrdisableout = {wire_receive_pcs3_phfifowrdisableout, wire_receive_pcs2_phfifowrdisableout, wire_receive_pcs1_phfifowrdisableout, wire_receive_pcs0_phfifowrdisableout},
+ int_rx_phfifoxnbytesel = {int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}},
+ int_rx_phfifoxnrdenable = {int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}},
+ int_rx_phfifoxnwrclk = {int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}},
+ int_rx_phfifoxnwrenable = {int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}},
+ int_rxcoreclk = {int_rx_coreclkout[0]},
+ int_rxphfifordenable = {int_rx_phfifordenableout[0]},
+ int_rxphfiforeset = {int_rx_phfiforesetout[0]},
+ int_rxphfifox4byteselout = {wire_cent_unit0_rxphfifox4byteselout},
+ int_rxphfifox4rdenableout = {wire_cent_unit0_rxphfifox4rdenableout},
+ int_rxphfifox4wrclkout = {wire_cent_unit0_rxphfifox4wrclkout},
+ int_rxphfifox4wrenableout = {wire_cent_unit0_rxphfifox4wrenableout},
+ int_tx_coreclkout = {wire_transmit_pcs3_coreclkout, wire_transmit_pcs2_coreclkout, wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
+ int_tx_digitalreset_reg = {tx_digitalreset_reg0c[2]},
+ int_tx_phfiforddisableout = {wire_transmit_pcs3_phfiforddisableout, wire_transmit_pcs2_phfiforddisableout, wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
+ int_tx_phfiforesetout = {wire_transmit_pcs3_phfiforesetout, wire_transmit_pcs2_phfiforesetout, wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
+ int_tx_phfifowrenableout = {wire_transmit_pcs3_phfifowrenableout, wire_transmit_pcs2_phfifowrenableout, wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
+ int_tx_phfifoxnbytesel = {int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}},
+ int_tx_phfifoxnrdclk = {int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}},
+ int_tx_phfifoxnrdenable = {int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}},
+ int_tx_phfifoxnwrenable = {int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}},
+ int_txcoreclk = {int_tx_coreclkout[0]},
+ int_txphfiforddisable = {int_tx_phfiforddisableout[0]},
+ int_txphfiforeset = {int_tx_phfiforesetout[0]},
+ int_txphfifowrenable = {int_tx_phfifowrenableout[0]},
+ int_txphfifox4byteselout = {wire_cent_unit0_txphfifox4byteselout},
+ int_txphfifox4rdclkout = {wire_cent_unit0_txphfifox4rdclkout},
+ int_txphfifox4rdenableout = {wire_cent_unit0_txphfifox4rdenableout},
+ int_txphfifox4wrenableout = {wire_cent_unit0_txphfifox4wrenableout},
+ nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
+ pll0_clkin = {{9{1'b0}}, pll_inclk_wire[0]},
+ pll0_dprioin = {cent_unit_cmuplldprioout[1499:1200]},
+ pll0_dprioout = {wire_tx_pll0_dprioout},
+ pll0_out = {wire_tx_pll0_clk[3:0]},
+ pll_ch_dataout_wire = {wire_rx_cdr_pll3_dataout, wire_rx_cdr_pll2_dataout, wire_rx_cdr_pll1_dataout, wire_rx_cdr_pll0_dataout},
+ pll_ch_dprioout = {wire_rx_cdr_pll3_dprioout, wire_rx_cdr_pll2_dprioout, wire_rx_cdr_pll1_dprioout, wire_rx_cdr_pll0_dprioout},
+ pll_cmuplldprioout = {{300{1'b0}}, pll0_dprioout[299:0], pll_ch_dprioout[1199:0]},
+ pll_inclk_wire = {pll_inclk},
+ pll_locked = {pll_locked_out[0]},
+ pll_locked_out = {wire_tx_pll0_locked},
+ pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]},
+ pllreset_in = {1'b0, cent_unit_pllresetout[0]},
+ reconfig_fromgxb = {rx_pma_analogtestbus[16:1], wire_cent_unit0_dprioout},
+ reconfig_togxb_busy = reconfig_togxb[3],
+ reconfig_togxb_disable = reconfig_togxb[1],
+ reconfig_togxb_in = reconfig_togxb[0],
+ reconfig_togxb_load = reconfig_togxb[2],
+ refclk_pma = {wire_central_clk_div0_refclkout},
+ rx_adetectdeskew = {wire_receive_pcs3_adetectdeskew, wire_receive_pcs2_adetectdeskew, wire_receive_pcs1_adetectdeskew, wire_receive_pcs0_adetectdeskew},
+ rx_alignstatussync = {rx_alignstatussyncout[0]},
+ rx_alignstatussyncout = {wire_receive_pcs3_alignstatussyncout, wire_receive_pcs2_alignstatussyncout, wire_receive_pcs1_alignstatussyncout, wire_receive_pcs0_alignstatussyncout},
+ rx_analogreset_in = {{2{1'b0}}, {4{((~ reconfig_togxb_busy) & rx_analogreset[0])}}},
+ rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]},
+ rx_channelaligned = {rx_channelaligned_in[0]},
+ rx_channelaligned_in = {wire_cent_unit0_alignstatus},
+ rx_coreclk_in = {rx_coreclk[3:0]},
+ rx_cruclk_in = {{9{1'b0}}, rx_pldcruclk_in[3], {9{1'b0}}, rx_pldcruclk_in[2], {9{1'b0}}, rx_pldcruclk_in[1], {9{1'b0}}, rx_pldcruclk_in[0]},
+ rx_ctrldetect = {wire_receive_pcs3_ctrldetect[1:0], wire_receive_pcs2_ctrldetect[1:0], wire_receive_pcs1_ctrldetect[1:0], wire_receive_pcs0_ctrldetect[1:0]},
+ rx_dataout = {rx_out_wire[63:0]},
+ rx_deserclock_in = {rx_pll_clkout[15:0]},
+ rx_digitalreset_in = {4{int_rx_digitalreset_reg[0]}},
+ rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]},
+ rx_disablefifordin_in = {rx_disablefifordout_wire[0]},
+ rx_disablefifordout_wire = {wire_receive_pcs3_disablefifordout, wire_receive_pcs2_disablefifordout, wire_receive_pcs1_disablefifordout, wire_receive_pcs0_disablefifordout},
+ rx_disablefifowrin_in = {rx_disablefifowrout_wire[0]},
+ rx_disablefifowrout_wire = {wire_receive_pcs3_disablefifowrout, wire_receive_pcs2_disablefifowrout, wire_receive_pcs1_disablefifowrout, wire_receive_pcs0_disablefifowrout},
+ rx_disperr = {wire_receive_pcs3_disperr[1:0], wire_receive_pcs2_disperr[1:0], wire_receive_pcs1_disperr[1:0], wire_receive_pcs0_disperr[1:0]},
+ rx_enapatternalign = {4{1'b0}},
+ rx_errdetect = {wire_receive_pcs3_errdetect[1:0], wire_receive_pcs2_errdetect[1:0], wire_receive_pcs1_errdetect[1:0], wire_receive_pcs0_errdetect[1:0]},
+ rx_fifordin_in = {rx_fifordout_wire[0]},
+ rx_fifordout_wire = {wire_receive_pcs3_fifordout, wire_receive_pcs2_fifordout, wire_receive_pcs1_fifordout, wire_receive_pcs0_fifordout},
+ rx_fiforesetrd = {wire_cent_unit0_fiforesetrd},
+ rx_freqlocked = {(rx_freqlocked_wire[3] & (~ rx_analogreset[0])), (rx_freqlocked_wire[2] & (~ rx_analogreset[0])), (rx_freqlocked_wire[1] & (~ rx_analogreset[0])), (rx_freqlocked_wire[0] & (~ rx_analogreset[0]))},
+ rx_freqlocked_wire = {wire_rx_cdr_pll3_freqlocked, wire_rx_cdr_pll2_freqlocked, wire_rx_cdr_pll1_freqlocked, wire_rx_cdr_pll0_freqlocked},
+ rx_locktodata_wire = {((~ reconfig_togxb_busy) & rx_locktodata[3]), ((~ reconfig_togxb_busy) & rx_locktodata[2]), ((~ reconfig_togxb_busy) & rx_locktodata[1]), ((~ reconfig_togxb_busy) & rx_locktodata[0])},
+ rx_locktorefclk_wire = {wire_receive_pcs3_cdrctrllocktorefclkout, wire_receive_pcs2_cdrctrllocktorefclkout, wire_receive_pcs1_cdrctrllocktorefclkout, wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_masterclk = {rx_pma_clockout[0]},
+ rx_out_wire = {wire_receive_pcs3_dataout[15:0], wire_receive_pcs2_dataout[15:0], wire_receive_pcs1_dataout[15:0], wire_receive_pcs0_dataout[15:0]},
+ rx_patterndetect = {wire_receive_pcs3_patterndetect[1:0], wire_receive_pcs2_patterndetect[1:0], wire_receive_pcs1_patterndetect[1:0], wire_receive_pcs0_patterndetect[1:0]},
+ rx_pcsdprioin_wire = {cent_unit_rxpcsdprioout[1599:0]},
+ rx_pcsdprioout = {wire_receive_pcs3_dprioout, wire_receive_pcs2_dprioout, wire_receive_pcs1_dprioout, wire_receive_pcs0_dprioout},
+ rx_phase_comp_fifo_error = {(rx_phfifooverflowout[3] | rx_phfifounderflowout[3]), (rx_phfifooverflowout[2] | rx_phfifounderflowout[2]), (rx_phfifooverflowout[1] | rx_phfifounderflowout[1]), (rx_phfifooverflowout[0] | rx_phfifounderflowout[0])},
+ rx_phfifooverflowout = {wire_receive_pcs3_phfifooverflow, wire_receive_pcs2_phfifooverflow, wire_receive_pcs1_phfifooverflow, wire_receive_pcs0_phfifooverflow},
+ rx_phfifordenable = {4{1'b1}},
+ rx_phfiforeset = {4{1'b0}},
+ rx_phfifounderflowout = {wire_receive_pcs3_phfifounderflow, wire_receive_pcs2_phfifounderflow, wire_receive_pcs1_phfifounderflow, wire_receive_pcs0_phfifounderflow},
+ rx_phfifowrdisable = {4{1'b0}},
+ rx_pldcruclk_in = {rx_cruclk[3:0]},
+ rx_pll_clkout = {wire_rx_cdr_pll3_clk, wire_rx_cdr_pll2_clk, wire_rx_cdr_pll1_clk, wire_rx_cdr_pll0_clk},
+ rx_pll_locked = {(rx_plllocked_wire[3] & (~ rx_analogreset[0])), (rx_plllocked_wire[2] & (~ rx_analogreset[0])), (rx_plllocked_wire[1] & (~ rx_analogreset[0])), (rx_plllocked_wire[0] & (~ rx_analogreset[0]))},
+ rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll3_pfdrefclkout, wire_rx_cdr_pll2_pfdrefclkout, wire_rx_cdr_pll1_pfdrefclkout, wire_rx_cdr_pll0_pfdrefclkout},
+ rx_plllocked_wire = {wire_rx_cdr_pll3_locked, wire_rx_cdr_pll2_locked, wire_rx_cdr_pll1_locked, wire_rx_cdr_pll0_locked},
+ rx_pma_analogtestbus = {{51{1'b0}}, wire_receive_pma3_analogtestbus[5:2], wire_receive_pma2_analogtestbus[5:2], wire_receive_pma1_analogtestbus[5:2], wire_receive_pma0_analogtestbus[5:2], 1'b0},
+ rx_pma_clockout = {wire_receive_pma3_clockout, wire_receive_pma2_clockout, wire_receive_pma1_clockout, wire_receive_pma0_clockout},
+ rx_pma_dataout = {wire_receive_pma3_dataout, wire_receive_pma2_dataout, wire_receive_pma1_dataout, wire_receive_pma0_dataout},
+ rx_pma_locktorefout = {wire_receive_pma3_locktorefout, wire_receive_pma2_locktorefout, wire_receive_pma1_locktorefout, wire_receive_pma0_locktorefout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma3_recoverdataout[19:0], wire_receive_pma2_recoverdataout[19:0], wire_receive_pma1_recoverdataout[19:0], wire_receive_pma0_recoverdataout[19:0]},
+ rx_pmadprioin_wire = {{2{{300{1'b0}}}}, cent_unit_rxpmadprioout[1199:0]},
+ rx_pmadprioout = {{2{{300{1'b0}}}}, wire_receive_pma3_dprioout, wire_receive_pma2_dprioout, wire_receive_pma1_dprioout, wire_receive_pma0_dprioout},
+ rx_powerdown = {4{1'b0}},
+ rx_powerdown_in = {{2{1'b0}}, rx_powerdown[3:0]},
+ rx_prbscidenable = {4{1'b0}},
+ rx_rdalign = {wire_receive_pcs3_rdalign, wire_receive_pcs2_rdalign, wire_receive_pcs1_rdalign, wire_receive_pcs0_rdalign},
+ rx_rlv = {wire_receive_pcs3_rlv, wire_receive_pcs2_rlv, wire_receive_pcs1_rlv, wire_receive_pcs0_rlv},
+ rx_rmfifodatadeleted = {wire_receive_pcs3_rmfifodatadeleted[1:0], wire_receive_pcs2_rmfifodatadeleted[1:0], wire_receive_pcs1_rmfifodatadeleted[1:0], wire_receive_pcs0_rmfifodatadeleted[1:0]},
+ rx_rmfifodatainserted = {wire_receive_pcs3_rmfifodatainserted[1:0], wire_receive_pcs2_rmfifodatainserted[1:0], wire_receive_pcs1_rmfifodatainserted[1:0], wire_receive_pcs0_rmfifodatainserted[1:0]},
+ rx_rmfifoempty = {wire_receive_pcs3_rmfifoempty, wire_receive_pcs2_rmfifoempty, wire_receive_pcs1_rmfifoempty, wire_receive_pcs0_rmfifoempty},
+ rx_rmfifofull = {wire_receive_pcs3_rmfifofull, wire_receive_pcs2_rmfifofull, wire_receive_pcs1_rmfifofull, wire_receive_pcs0_rmfifofull},
+ rx_rmfiforeset = {4{1'b0}},
+ rx_runningdisp = {wire_receive_pcs3_runningdisp[1:0], wire_receive_pcs2_runningdisp[1:0], wire_receive_pcs1_runningdisp[1:0], wire_receive_pcs0_runningdisp[1:0]},
+ rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]},
+ rx_syncstatus = {wire_receive_pcs3_syncstatus[1:0], wire_receive_pcs2_syncstatus[1:0], wire_receive_pcs1_syncstatus[1:0], wire_receive_pcs0_syncstatus[1:0]},
+ rx_syncstatusdeskew = {wire_receive_pcs3_syncstatusdeskew, wire_receive_pcs2_syncstatusdeskew, wire_receive_pcs1_syncstatusdeskew, wire_receive_pcs0_syncstatusdeskew},
+ rx_xgmctrlin = {wire_cent_unit0_rxctrlout},
+ rx_xgmdataout = {wire_receive_pcs3_xgmdataout, wire_receive_pcs2_xgmdataout, wire_receive_pcs1_xgmdataout, wire_receive_pcs0_xgmdataout},
+ rx_xgmdatavalid = {wire_receive_pcs3_xgmdatavalid, wire_receive_pcs2_xgmdatavalid, wire_receive_pcs1_xgmdatavalid, wire_receive_pcs0_xgmdatavalid},
+ rx_xgmrunningdisp = {wire_receive_pcs3_xgmrunningdisp, wire_receive_pcs2_xgmrunningdisp, wire_receive_pcs1_xgmrunningdisp, wire_receive_pcs0_xgmrunningdisp},
+ rxphfifowrdisable = {int_rx_phfifowrdisableout[0]},
+ rxpll_dprioin = {{2{{300{1'b0}}}}, cent_unit_cmuplldprioout[1199:0]},
+ tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
+ tx_coreclk_in = {tx_coreclk[3:0]},
+ tx_datain_wire = {tx_datain[63:0]},
+ tx_dataout = {wire_transmit_pma3_dataout, wire_transmit_pma2_dataout, wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs3_dataout, wire_transmit_pcs2_dataout, wire_transmit_pcs1_dataout, wire_transmit_pcs0_dataout},
+ tx_digitalreset_in = {4{int_tx_digitalreset_reg[0]}},
+ tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]},
+ tx_dprioin_wire = {{600{1'b0}}, cent_unit_txdprioout[599:0]},
+ tx_forcedisp_wire = {4{{2{1'b0}}}},
+ tx_localrefclk = {wire_transmit_pma3_clockout, wire_transmit_pma2_clockout, wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
+ tx_phase_comp_fifo_error = {(tx_phfifooverflowout[3] | tx_phfifounderflowout[3]), (tx_phfifooverflowout[2] | tx_phfifounderflowout[2]), (tx_phfifooverflowout[1] | tx_phfifounderflowout[1]), (tx_phfifooverflowout[0] | tx_phfifounderflowout[0])},
+ tx_phfifooverflowout = {wire_transmit_pcs3_phfifooverflow, wire_transmit_pcs2_phfifooverflow, wire_transmit_pcs1_phfifooverflow, wire_transmit_pcs0_phfifooverflow},
+ tx_phfiforeset = {4{1'b0}},
+ tx_phfifounderflowout = {wire_transmit_pcs3_phfifounderflow, wire_transmit_pcs2_phfifounderflow, wire_transmit_pcs1_phfifounderflow, wire_transmit_pcs0_phfifounderflow},
+ tx_pmadprioin_wire = {{2{{300{1'b0}}}}, cent_unit_txpmadprioout[1199:0]},
+ tx_pmadprioout = {{2{{300{1'b0}}}}, wire_transmit_pma3_dprioout, wire_transmit_pma2_dprioout, wire_transmit_pma1_dprioout, wire_transmit_pma0_dprioout},
+ tx_rdenablesync = {wire_transmit_pcs3_rdenablesync, wire_transmit_pcs2_rdenablesync, wire_transmit_pcs1_rdenablesync, wire_transmit_pcs0_rdenablesync},
+ tx_serialloopbackout = {wire_transmit_pma3_seriallpbkout, wire_transmit_pma2_seriallpbkout, wire_transmit_pma1_seriallpbkout, wire_transmit_pma0_seriallpbkout},
+ tx_txdprioout = {wire_transmit_pcs3_dprioout, wire_transmit_pcs2_dprioout, wire_transmit_pcs1_dprioout, wire_transmit_pcs0_dprioout},
+ tx_xgmctrlenable = {wire_transmit_pcs3_xgmctrlenable, wire_transmit_pcs2_xgmctrlenable, wire_transmit_pcs1_xgmctrlenable, wire_transmit_pcs0_xgmctrlenable},
+ tx_xgmdataout = {wire_transmit_pcs3_xgmdataout, wire_transmit_pcs2_xgmdataout, wire_transmit_pcs1_xgmdataout, wire_transmit_pcs0_xgmdataout},
+ txdetectrxout = {wire_transmit_pcs3_txdetectrx, wire_transmit_pcs2_txdetectrx, wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx},
+ w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
+endmodule //hxaui_alt4gxb_alt4gxb_dksa
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+//(* ALTERA_ATTRIBUTE = {"-name SDC_STATEMENT \"set_false_path -from [get_registers *hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component*fifo*flow] -to [get_registers *xaui_phy*hxaui_csr*tx_phase_comp_fifo_error_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers *hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component*] -to [get_registers *xaui_phy*hxaui_csr*rx*_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*siv_xcvr_xaui*hxaui_csr*hxaui_csr_reset0q[*]}] -to [get_registers {*xaui_phy*hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component|*digitalreset*}]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*siv_xcvr_xaui*alt_pma_ch_controller_0*rc*}] -to [get_registers {*xaui_phy*hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component|*digitalreset*}]\""} *)
+module hxaui_alt4gxb (
+ cal_blk_clk,
+ cal_blk_powerdown,
+ gxb_powerdown,
+ pll_inclk,
+ pll_powerdown,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ rx_invpolarity,
+ rx_locktodata,
+ rx_locktorefclk,
+ rx_seriallpbken,
+ tx_coreclk,
+ tx_ctrlenable,
+ tx_datain,
+ tx_digitalreset,
+ tx_invpolarity,
+ coreclkout,
+ pll_locked,
+ reconfig_fromgxb,
+ rx_channelaligned,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_disperr,
+ rx_errdetect,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_phase_comp_fifo_error,
+ rx_pll_locked,
+ rx_rlv,
+ rx_rmfifodatadeleted,
+ rx_rmfifodatainserted,
+ rx_rmfifoempty,
+ rx_rmfifofull,
+ rx_runningdisp,
+ rx_syncstatus,
+ rx_recovered_clk,
+ tx_dataout,
+ tx_phase_comp_fifo_error);
+
+ input cal_blk_clk;
+ input cal_blk_powerdown;
+ input [0:0] gxb_powerdown;
+ input pll_inclk;
+ input [0:0] pll_powerdown;
+ input reconfig_clk;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ wire [3:0] rx_coreclk;
+ input [3:0] rx_cruclk;
+ input [3:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [3:0] rx_invpolarity;
+ input [3:0] rx_locktodata;
+ input [3:0] rx_locktorefclk;
+ input [3:0] rx_seriallpbken;
+ input [3:0] tx_coreclk;
+ input [7:0] tx_ctrlenable;
+ input [63:0] tx_datain;
+ input [0:0] tx_digitalreset;
+ input [3:0] tx_invpolarity;
+ output [0:0] coreclkout;
+ output [0:0] pll_locked;
+ output [16:0] reconfig_fromgxb;
+ output [0:0] rx_channelaligned;
+ output [7:0] rx_ctrldetect;
+ output [63:0] rx_dataout;
+ output [7:0] rx_disperr;
+ output [7:0] rx_errdetect;
+ output [3:0] rx_freqlocked;
+ output [3:0] rx_recovered_clk;
+ output [7:0] rx_patterndetect;
+ output [3:0] rx_phase_comp_fifo_error;
+ output [3:0] rx_pll_locked;
+ output [3:0] rx_rlv;
+ output [7:0] rx_rmfifodatadeleted;
+ output [7:0] rx_rmfifodatainserted;
+ output [3:0] rx_rmfifoempty;
+ output [3:0] rx_rmfifofull;
+ output [7:0] rx_runningdisp;
+ output [7:0] rx_syncstatus;
+ output [3:0] tx_dataout;
+ output [3:0] tx_phase_comp_fifo_error;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 [3:0] rx_cruclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ parameter starting_channel_number = 0;
+ parameter transmitter_termination = "OCT 100 OHMS";//OCT_85_OHMS,OCT_100_OHMS,OCT_120_OHMS,OCT_150_OHMS
+ parameter receiver_termination = "OCT 100 OHMS"; //OCT_85_OHMS,OCT_100_OHMS,OCT_120_OHMS,OCT_150_OHMS
+ parameter rx_common_mode = "0.82v";
+
+ parameter preemphasis_ctrl_pretap_setting = 0;//0-7
+ parameter preemphasis_ctrl_pretap_inv_setting = "FALSE";//TRUE or FALSE.
+ parameter preemphasis_ctrl_1stposttap_setting = 5;//0-15
+ parameter preemphasis_ctrl_2ndposttap_setting = 0;//0-7
+ parameter preemphasis_ctrl_2ndposttap_inv_setting = "FALSE";//TRUE or FALSE.
+ parameter vod_ctrl_setting = 1;//0-7
+
+ parameter equalizer_dcgain_setting = 0; //0-4
+ parameter equalizer_ctrl_a_setting = 0;
+ parameter equalizer_ctrl_b_setting = 0;
+ parameter equalizer_ctrl_c_setting = 0;
+ parameter equalizer_ctrl_d_setting = 0;
+ parameter equalizer_ctrl_v_setting = 0;
+
+
+ wire [7:0] sub_wire0;
+ wire [3:0] sub_wire1;
+ wire [3:0] sub_wire2;
+ wire [7:0] sub_wire3;
+ wire [0:0] sub_wire4;
+ wire [7:0] sub_wire5;
+ wire [7:0] sub_wire6;
+ wire [7:0] sub_wire7;
+ wire [3:0] sub_wire8;
+ wire [3:0] sub_wire9;
+ wire [7:0] sub_wire10;
+ wire [3:0] sub_wire11;
+ wire [3:0] sub_wire12;
+ wire [7:0] sub_wire13;
+ wire [3:0] sub_wire14;
+ wire [0:0] sub_wire15;
+ wire [3:0] sub_wire16;
+ wire [7:0] sub_wire17;
+ wire [16:0] sub_wire18;
+ wire [0:0] sub_wire19;
+ wire [63:0] sub_wire20;
+ wire [7:0] rx_disperr = sub_wire0[7:0];
+ wire [3:0] rx_rmfifoempty = sub_wire1[3:0];
+ wire [3:0] rx_rlv = sub_wire2[3:0];
+ wire [7:0] rx_patterndetect = sub_wire3[7:0];
+ wire [0:0] coreclkout = sub_wire4[0:0];
+ wire [7:0] rx_ctrldetect = sub_wire5[7:0];
+ wire [7:0] rx_errdetect = sub_wire6[7:0];
+ wire [7:0] rx_rmfifodatadeleted = sub_wire7[7:0];
+ wire [3:0] rx_pll_locked = sub_wire8[3:0];
+ wire [3:0] rx_freqlocked = sub_wire9[3:0];
+ wire [7:0] rx_runningdisp = sub_wire10[7:0];
+ wire [3:0] tx_phase_comp_fifo_error = sub_wire11[3:0];
+ wire [3:0] tx_dataout = sub_wire12[3:0];
+ wire [7:0] rx_rmfifodatainserted = sub_wire13[7:0];
+ wire [3:0] rx_phase_comp_fifo_error = sub_wire14[3:0];
+ wire [0:0] rx_channelaligned = sub_wire15[0:0];
+ wire [3:0] rx_rmfifofull = sub_wire16[3:0];
+ wire [7:0] rx_syncstatus = sub_wire17[7:0];
+ wire [16:0] reconfig_fromgxb = sub_wire18[16:0];
+ wire [0:0] pll_locked = sub_wire19[0:0];
+ wire [63:0] rx_dataout = sub_wire20[63:0];
+ wire coreclkout_global;
+ // Start - Manually instantiate the clock control block without requiring the MegaWizard generated file
+ stratixiv_clkena sd1
+ (
+ .ena(1'b1),
+ .enaout(),
+ .inclk(sub_wire4),
+ .outclk(coreclkout_global)
+ // synopsys translate_off
+ ,
+ .devclrn(1'b1),
+ .devpor(1'b1)
+ // synopsys translate_on
+ );
+ defparam
+ //sd1.clock_type = "Global Clock",
+ sd1.ena_register_mode = "falling edge",
+ sd1.lpm_type = "stratixiv_clkena";
+ // End
+ assign rx_coreclk = {4{coreclkout_global}};
+
+ hxaui_alt4gxb_alt4gxb_dksa hxaui_alt4gxb_alt4gxb_dksa_component (
+ .rx_locktorefclk (rx_locktorefclk),
+ .rx_invpolarity (rx_invpolarity),
+ .pll_inclk (pll_inclk),
+ .tx_invpolarity (tx_invpolarity),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_datain (tx_datain),
+ .rx_cruclk (rx_cruclk),
+ .cal_blk_clk (cal_blk_clk),
+ .pll_powerdown (pll_powerdown),
+ .reconfig_clk (reconfig_clk),
+ .rx_seriallpbken (rx_seriallpbken),
+ .rx_locktodata (rx_locktodata),
+ .rx_datain (rx_datain),
+ .cal_blk_powerdown (cal_blk_powerdown),
+ .reconfig_togxb (reconfig_togxb),
+ .tx_coreclk (tx_coreclk),
+ .tx_ctrlenable (tx_ctrlenable),
+ .rx_analogreset (rx_analogreset),
+ .rx_digitalreset (rx_digitalreset),
+ .tx_digitalreset (tx_digitalreset),
+ .rx_disperr (sub_wire0),
+ .rx_rmfifoempty (sub_wire1),
+ .rx_rlv (sub_wire2),
+ .rx_patterndetect (sub_wire3),
+ .coreclkout (sub_wire4),
+ .rx_ctrldetect (sub_wire5),
+ .rx_errdetect (sub_wire6),
+ .rx_rmfifodatadeleted (sub_wire7),
+ .rx_pll_locked (sub_wire8),
+ .rx_freqlocked (sub_wire9),
+ .rx_runningdisp (sub_wire10),
+ .tx_phase_comp_fifo_error (sub_wire11),
+ .tx_dataout (sub_wire12),
+ .rx_rmfifodatainserted (sub_wire13),
+ .rx_phase_comp_fifo_error (sub_wire14),
+ .rx_channelaligned (sub_wire15),
+ .rx_rmfifofull (sub_wire16),
+ .rx_coreclk (rx_coreclk),
+ .rx_syncstatus (sub_wire17),
+ .rx_recovered_clk(rx_recovered_clk), // o
+ .reconfig_fromgxb (sub_wire18),
+ .pll_locked (sub_wire19),
+ .rx_dataout (sub_wire20));
+ defparam
+ hxaui_alt4gxb_alt4gxb_dksa_component.starting_channel_number = starting_channel_number,
+ hxaui_alt4gxb_alt4gxb_dksa_component.receiver_termination = receiver_termination,
+ hxaui_alt4gxb_alt4gxb_dksa_component.transmitter_termination = transmitter_termination,
+ hxaui_alt4gxb_alt4gxb_dksa_component.preemphasis_ctrl_pretap_setting = preemphasis_ctrl_pretap_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.preemphasis_ctrl_pretap_inv_setting = preemphasis_ctrl_pretap_inv_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.preemphasis_ctrl_1stposttap_setting = preemphasis_ctrl_1stposttap_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.preemphasis_ctrl_2ndposttap_setting = preemphasis_ctrl_2ndposttap_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.preemphasis_ctrl_2ndposttap_inv_setting = preemphasis_ctrl_2ndposttap_inv_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.vod_ctrl_setting = vod_ctrl_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.rx_common_mode = rx_common_mode,
+ hxaui_alt4gxb_alt4gxb_dksa_component.equalizer_ctrl_a_setting = equalizer_ctrl_a_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.equalizer_ctrl_b_setting = equalizer_ctrl_b_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.equalizer_ctrl_c_setting = equalizer_ctrl_c_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.equalizer_ctrl_d_setting = equalizer_ctrl_d_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.equalizer_ctrl_v_setting = equalizer_ctrl_v_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.equalizer_dcgain_setting = equalizer_dcgain_setting;
+
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "3125.0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "3125"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "50.0 "
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "50.0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "250.0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "XAUI"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "1"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "156.25"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "156.25"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "3125"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "156.25"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "XAUI"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "None"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "3125 Mbps"
+// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
+// Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "AUTO"
+// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "156.25 MHz"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "2"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "GX"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "slb"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "4"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "xaui"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x4"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Auto"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "6400"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "xaui"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "3125"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "true"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "true"
+// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "1101000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "0010111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "10"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "2"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "AUTO"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x4"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "4"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "3125"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "Auto"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "6400"
+// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
+// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "low"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "xaui"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "true"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
+// Retrieval info: CONSTANT: coreclkout_control_width NUMERIC "1"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
+// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
+// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "17"
+// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
+// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "10"
+// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "1"
+// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "2"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "1"
+// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "1"
+// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "10"
+// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "2"
+// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: cal_blk_powerdown 0 0 0 0 INPUT NODEFVAL "cal_blk_powerdown"
+// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: pll_powerdown 0 0 1 0 INPUT NODEFVAL "pll_powerdown[0..0]"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 OUTPUT NODEFVAL "reconfig_fromgxb[16..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_channelaligned 0 0 1 0 OUTPUT NODEFVAL "rx_channelaligned[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 4 0 INPUT GND "rx_cruclk[3..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 8 0 OUTPUT NODEFVAL "rx_ctrldetect[7..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 4 0 INPUT NODEFVAL "rx_datain[3..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 64 0 OUTPUT NODEFVAL "rx_dataout[63..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_disperr 0 0 8 0 OUTPUT NODEFVAL "rx_disperr[7..0]"
+// Retrieval info: USED_PORT: rx_errdetect 0 0 8 0 OUTPUT NODEFVAL "rx_errdetect[7..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 4 0 OUTPUT NODEFVAL "rx_freqlocked[3..0]"
+// Retrieval info: USED_PORT: rx_invpolarity 0 0 4 0 INPUT NODEFVAL "rx_invpolarity[3..0]"
+// Retrieval info: USED_PORT: rx_locktodata 0 0 4 0 INPUT NODEFVAL "rx_locktodata[3..0]"
+// Retrieval info: USED_PORT: rx_locktorefclk 0 0 4 0 INPUT NODEFVAL "rx_locktorefclk[3..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 8 0 OUTPUT NODEFVAL "rx_patterndetect[7..0]"
+// Retrieval info: USED_PORT: rx_phase_comp_fifo_error 0 0 4 0 OUTPUT NODEFVAL "rx_phase_comp_fifo_error[3..0]"
+// Retrieval info: USED_PORT: rx_pll_locked 0 0 4 0 OUTPUT NODEFVAL "rx_pll_locked[3..0]"
+// Retrieval info: USED_PORT: rx_rlv 0 0 4 0 OUTPUT NODEFVAL "rx_rlv[3..0]"
+// Retrieval info: USED_PORT: rx_rmfifodatadeleted 0 0 8 0 OUTPUT NODEFVAL "rx_rmfifodatadeleted[7..0]"
+// Retrieval info: USED_PORT: rx_rmfifodatainserted 0 0 8 0 OUTPUT NODEFVAL "rx_rmfifodatainserted[7..0]"
+// Retrieval info: USED_PORT: rx_rmfifoempty 0 0 4 0 OUTPUT NODEFVAL "rx_rmfifoempty[3..0]"
+// Retrieval info: USED_PORT: rx_rmfifofull 0 0 4 0 OUTPUT NODEFVAL "rx_rmfifofull[3..0]"
+// Retrieval info: USED_PORT: rx_runningdisp 0 0 8 0 OUTPUT NODEFVAL "rx_runningdisp[7..0]"
+// Retrieval info: USED_PORT: rx_seriallpbken 0 0 4 0 INPUT NODEFVAL "rx_seriallpbken[3..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 8 0 OUTPUT NODEFVAL "rx_syncstatus[7..0]"
+// Retrieval info: USED_PORT: tx_coreclk 0 0 4 0 INPUT NODEFVAL "tx_coreclk[3..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 8 0 INPUT NODEFVAL "tx_ctrlenable[7..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 64 0 INPUT NODEFVAL "tx_datain[63..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 4 0 OUTPUT NODEFVAL "tx_dataout[3..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_invpolarity 0 0 4 0 INPUT NODEFVAL "tx_invpolarity[3..0]"
+// Retrieval info: USED_PORT: tx_phase_comp_fifo_error 0 0 4 0 OUTPUT NODEFVAL "tx_phase_comp_fifo_error[3..0]"
+// Retrieval info: CONNECT: rx_patterndetect 0 0 8 0 @rx_patterndetect 0 0 8 0
+// Retrieval info: CONNECT: @rx_invpolarity 0 0 4 0 rx_invpolarity 0 0 4 0
+// Retrieval info: CONNECT: @rx_locktorefclk 0 0 4 0 rx_locktorefclk 0 0 4 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 8 0 @rx_ctrldetect 0 0 8 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: rx_dataout 0 0 64 0 @rx_dataout 0 0 64 0
+// Retrieval info: CONNECT: rx_runningdisp 0 0 8 0 @rx_runningdisp 0 0 8 0
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: rx_phase_comp_fifo_error 0 0 4 0 @rx_phase_comp_fifo_error 0 0 4 0
+// Retrieval info: CONNECT: rx_rmfifofull 0 0 4 0 @rx_rmfifofull 0 0 4 0
+// Retrieval info: CONNECT: rx_errdetect 0 0 8 0 @rx_errdetect 0 0 8 0
+// Retrieval info: CONNECT: rx_channelaligned 0 0 1 0 @rx_channelaligned 0 0 1 0
+// Retrieval info: CONNECT: @tx_coreclk 0 0 4 0 tx_coreclk 0 0 4 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: rx_pll_locked 0 0 4 0 @rx_pll_locked 0 0 4 0
+// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 8 0 @rx_syncstatus 0 0 8 0
+// Retrieval info: CONNECT: @rx_seriallpbken 0 0 4 0 rx_seriallpbken 0 0 4 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: tx_phase_comp_fifo_error 0 0 4 0 @tx_phase_comp_fifo_error 0 0 4 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 4 0 rx_cruclk 0 0 4 0
+// Retrieval info: CONNECT: @tx_invpolarity 0 0 4 0 tx_invpolarity 0 0 4 0
+// Retrieval info: CONNECT: rx_rlv 0 0 4 0 @rx_rlv 0 0 4 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 8 0 tx_ctrlenable 0 0 8 0
+// Retrieval info: CONNECT: tx_dataout 0 0 4 0 @tx_dataout 0 0 4 0
+// Retrieval info: CONNECT: @tx_datain 0 0 64 0 tx_datain 0 0 64 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 17 0 @reconfig_fromgxb 0 0 17 0
+// Retrieval info: CONNECT: rx_rmfifoempty 0 0 4 0 @rx_rmfifoempty 0 0 4 0
+// Retrieval info: CONNECT: @cal_blk_powerdown 0 0 0 0 cal_blk_powerdown 0 0 0 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 4 0 @rx_freqlocked 0 0 4 0
+// Retrieval info: CONNECT: @rx_locktodata 0 0 4 0 rx_locktodata 0 0 4 0
+// Retrieval info: CONNECT: @rx_datain 0 0 4 0 rx_datain 0 0 4 0
+// Retrieval info: CONNECT: rx_rmfifodatainserted 0 0 8 0 @rx_rmfifodatainserted 0 0 8 0
+// Retrieval info: CONNECT: rx_rmfifodatadeleted 0 0 8 0 @rx_rmfifodatadeleted 0 0 8 0
+// Retrieval info: CONNECT: rx_disperr 0 0 8 0 @rx_disperr 0 0 8 0
+// Retrieval info: CONNECT: @pll_powerdown 0 0 1 0 pll_powerdown 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL hxaui_alt4gxb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL hxaui_alt4gxb.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL hxaui_alt4gxb.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL hxaui_alt4gxb.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL hxaui_alt4gxb.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL hxaui_alt4gxb_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL hxaui_alt4gxb_bb.v TRUE
+// Retrieval info: LIB_FILE: stratixiv_hssi
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/hxaui_csr.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/hxaui_csr.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5ad633285f019d30350c678e518974f6621093e3
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/hxaui_csr.sv
@@ -0,0 +1,415 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// (C) 2001-2010 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+///////////////////////////////////////////////////////////////////////////////
+//
+//
+// Description: Hard xaui control and status registers
+//
+// Authors: ishimony 12-Jun-2009
+//
+// Copyright (c) Altera Corporation 1997 - 2009
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+//
+// TBD: unless synthesis is smart enough all synchronization flops will have
+// to be manually instantiated (altera_std_synchronizer)
+//
+
+`timescale 1 ps / 1 ps
+
+module hxaui_csr(
+ clk, reset, address, byteenable, read, readdata, write, writedata,
+ rx_patterndetect, rx_syncstatus, rx_runningdisp, rx_errdetect,
+ rx_disperr, rx_phase_comp_fifo_error, rx_rlv, rx_rmfifodatadeleted,
+ rx_rmfifodatainserted, rx_rmfifoempty, rx_rmfifofull,
+ tx_phase_comp_fifo_error, r_rx_invpolarity, r_tx_invpolarity,
+ r_rx_digitalreset, r_tx_digitalreset, simulation_flag
+); // module hxaui_csr
+import hxaui_csr_h::*;
+
+// ports -------------------------------------------------------------------
+
+// Avalon MM slave
+input clk;
+input reset;
+
+input [4:0] address;
+input [3:0] byteenable;
+
+input read;
+output [31:0] readdata;
+
+input write;
+input [31:0] writedata;
+
+// hard xaui control/status
+input [7:0] rx_patterndetect;
+input [7:0] rx_syncstatus;
+input [7:0] rx_runningdisp; // nc
+
+input [7:0] rx_errdetect;
+input [7:0] rx_disperr;
+
+input [3:0] rx_phase_comp_fifo_error;
+input [3:0] rx_rlv;
+
+input [7:0] rx_rmfifodatadeleted;
+input [7:0] rx_rmfifodatainserted;
+input [3:0] rx_rmfifoempty;
+input [3:0] rx_rmfifofull;
+
+input [3:0] tx_phase_comp_fifo_error;
+
+output [3:0] r_rx_invpolarity;
+output [3:0] r_tx_invpolarity;
+output r_rx_digitalreset;
+output r_tx_digitalreset;
+
+output simulation_flag; // '1' shortens reset and loss_timer length
+
+// ports -------------------------------------------------------------------
+wire clk;
+wire reset;
+wire [4:0] address;
+wire [6:0] addr;
+wire [3:0] byteenable;
+wire read;
+reg [31:0] readdata;
+wire write;
+wire [31:0] writedata;
+wire [3:0] rx_phase_comp_fifo_error;
+wire [3:0] rx_rlv;
+wire [3:0] rx_rmfifoempty;
+wire [3:0] rx_rmfifofull;
+wire [3:0] tx_phase_comp_fifo_error;
+wire [7:0] rx_disperr;
+wire [7:0] rx_errdetect;
+wire [7:0] rx_patterndetect;
+wire [7:0] rx_rmfifodatadeleted;
+wire [7:0] rx_rmfifodatainserted;
+wire [7:0] rx_runningdisp;
+wire [7:0] rx_syncstatus;
+wire [3:0] r_rx_invpolarity;
+wire [3:0] r_tx_invpolarity;
+wire r_rx_digitalreset;
+wire r_tx_digitalreset;
+wire simulation_flag;
+
+// locals ------------------------------------------------------------------
+reg [1:0] hxaui_csr_reset, hxaui_csr_reset0q;
+reg [3:0] hxaui_csr_rx_cntrl, hxaui_csr_rx_cntrl0q;
+reg [3:0] hxaui_csr_tx_cntrl, hxaui_csr_tx_cntrl0q;
+wire [31:0] hxaui_csr_rx_status_0;
+wire [31:0] hxaui_csr_rx_status_1;
+wire [31:0] hxaui_csr_rx_status_2;
+wire [31:0] hxaui_csr_rx_status_3;
+wire [31:0] hxaui_csr_rx_status_4;
+wire [31:0] hxaui_csr_tx_status_0;
+reg hxaui_csr_simulation_flag, hxaui_csr_simulation_flag0q;
+
+
+reg [7:0] rx_patterndetect_c; // rx_patterndetect synced to clk
+reg [7:0] rx_syncstatus_c; // rx_syncstatus synced to clk
+reg [7:0] rx_patterndetect_sr; // rx_patterndetect sr ff
+reg [7:0] rx_syncstatus_sr; // rx_syncstatus sr ff
+wire read_rx_status_0;
+
+reg [7:0] rx_errdetect_c; // rx_errdetect synced to clk
+reg [7:0] rx_disperr_c; // rx_disperr synced to clk
+reg [7:0] rx_errdetect_sr; // rx_errdetect sr ff
+reg [7:0] rx_disperr_sr; // rx_disperr sr ff
+wire read_rx_status_1;
+
+reg [3:0] rx_phase_comp_fifo_error_c; // rx_phase_comp_fifo_error synced
+reg [3:0] rx_rlv_c; // rx_rlv synced to clk
+reg [3:0] rx_phase_comp_fifo_error_sr; // rx_phase_comp_fifo_error sr ff
+reg [3:0] rx_rlv_sr; // rx_rlv sr ff
+wire read_rx_status_2;
+
+reg [7:0] rx_rmfifodatainserted_c; // rx_rmfifodatainserted synced to clk
+reg [7:0] rx_rmfifodatadeleted_c; // rx_rmfifodatadeleted synced to clk
+reg [7:0] rx_rmfifodatainserted_sr;// rx_rmfifodatainserted sr ff
+reg [7:0] rx_rmfifodatadeleted_sr; // rx_rmfifodatadeleted sr ff
+wire read_rx_status_3;
+
+reg [3:0] rx_rmfifofull_c; // rx_rmfifo_full synced
+reg [3:0] rx_rmfifoempty_c; // rx_rmfifoempty synced to clk
+reg [3:0] rx_rmfifofull_sr; // rx_rmfifo_full sr ff
+reg [3:0] rx_rmfifoempty_sr; // rx_rmfifoempty sr ff
+wire read_rx_status_4;
+
+wire read_rx_status_5;
+
+reg [3:0] tx_phase_comp_fifo_error_c; // tx_phase_comp_fifo_error synced
+reg [3:0] tx_phase_comp_fifo_error_sr; // tx_phase_comp_fifo_error sr ff
+wire read_tx_status_0;
+
+// body --------------------------------------------------------------------
+
+//--- readdata output latch ---
+// For easier address debug shift back 2 bits
+assign addr = {address[4:0], 2'b00};
+
+always @(*) begin
+ case (addr)
+ HXAUI_CSR_RESET_ADDR:
+ readdata <= hxaui_csr_reset0q;
+ HXAUI_CSR_RX_CNTRL_ADDR:
+ readdata <= hxaui_csr_rx_cntrl0q;
+ HXAUI_CSR_TX_CNTRL_ADDR:
+ readdata <= hxaui_csr_tx_cntrl0q;
+ HXAUI_CSR_RX_STATUS_0_ADDR:
+ readdata <= hxaui_csr_rx_status_0;
+ HXAUI_CSR_RX_STATUS_1_ADDR:
+ readdata <= hxaui_csr_rx_status_1;
+ HXAUI_CSR_RX_STATUS_2_ADDR:
+ readdata <= hxaui_csr_rx_status_2;
+ HXAUI_CSR_RX_STATUS_3_ADDR:
+ readdata <= hxaui_csr_rx_status_3;
+ HXAUI_CSR_RX_STATUS_4_ADDR:
+ readdata <= hxaui_csr_rx_status_4;
+ HXAUI_CSR_TX_STATUS_0_ADDR:
+ readdata <= hxaui_csr_tx_status_0;
+ HXAUI_CSR_SIMULATION_FLAG_ADDR:
+ readdata <= hxaui_csr_simulation_flag0q;
+ default:
+ readdata <= 32'h0;
+ endcase // case (addr)
+end
+
+always @ (posedge clk or posedge reset) begin
+ if (reset) begin
+ hxaui_csr_reset0q <= 2'b0;
+ hxaui_csr_rx_cntrl0q <= 4'b0;
+ hxaui_csr_tx_cntrl0q <= 4'b0;
+ hxaui_csr_simulation_flag0q <= 1'b0;
+ end else begin
+ hxaui_csr_reset0q <= hxaui_csr_reset;
+ hxaui_csr_rx_cntrl0q <= hxaui_csr_rx_cntrl;
+ hxaui_csr_tx_cntrl0q <= hxaui_csr_tx_cntrl;
+ hxaui_csr_simulation_flag0q <= hxaui_csr_simulation_flag;
+ end
+end
+
+
+always @ (*) begin
+ hxaui_csr_reset = hxaui_csr_reset0q;
+ hxaui_csr_rx_cntrl = hxaui_csr_rx_cntrl0q;
+ hxaui_csr_tx_cntrl = hxaui_csr_tx_cntrl0q;
+ hxaui_csr_simulation_flag = hxaui_csr_simulation_flag0q;
+ if (write) begin
+ case (addr)
+ HXAUI_CSR_RESET_ADDR:
+ hxaui_csr_reset = writedata[1:0];
+ HXAUI_CSR_RX_CNTRL_ADDR:
+ hxaui_csr_rx_cntrl = writedata[3:0];
+ HXAUI_CSR_TX_CNTRL_ADDR:
+ hxaui_csr_tx_cntrl = writedata[3:0];
+ HXAUI_CSR_SIMULATION_FLAG_ADDR:
+ hxaui_csr_simulation_flag = writedata[0];
+ default:;
+ endcase // case (addr)
+ end
+end
+
+assign {r_rx_digitalreset, r_tx_digitalreset} = hxaui_csr_reset0q[1:0];
+assign r_rx_invpolarity[3:0] = hxaui_csr_rx_cntrl0q[3:0];
+assign r_tx_invpolarity[3:0] = hxaui_csr_tx_cntrl0q[3:0];
+assign simulation_flag = hxaui_csr_simulation_flag0q;
+
+//--- rx_status_0 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ rx_patterndetect_c <= rx_patterndetect;
+ rx_syncstatus_c <= rx_syncstatus;
+end
+
+assign read_rx_status_0 = read && (addr == HXAUI_CSR_RX_STATUS_0_ADDR);
+
+// sticky bits implementation -
+// set: status signal
+// reset: read from register
+// Set has precedence over reset
+//
+// s r q nq
+// ------------
+// 0 0 x q
+// 0 1 x 0
+// 1 x x 1
+//
+// nq <= s + qr'
+//
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ rx_patterndetect_sr <= 8'h0;
+ rx_syncstatus_sr <= 8'h0;
+ end else begin
+ rx_patterndetect_sr <= rx_patterndetect_c |
+ (rx_patterndetect_sr & {8{read_rx_status_0}});
+ rx_syncstatus_sr <= rx_syncstatus_c |
+ (rx_syncstatus_sr & {8{read_rx_status_0}});
+ end
+end
+
+assign hxaui_csr_rx_status_0 = {rx_patterndetect_sr, rx_syncstatus_sr};
+
+//--- rx_status_1 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ rx_errdetect_c <= rx_errdetect;
+ rx_disperr_c <= rx_disperr;
+end
+
+assign read_rx_status_1 = read && (addr == HXAUI_CSR_RX_STATUS_1_ADDR);
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ rx_errdetect_sr <= 8'h0;
+ rx_disperr_sr <= 8'h0;
+ end else begin
+ rx_errdetect_sr <= rx_errdetect_c |
+ (rx_errdetect_sr & {8{read_rx_status_1}});
+ rx_disperr_sr <= rx_disperr_c |
+ (rx_disperr_sr & {8{read_rx_status_1}});
+ end
+end
+
+assign hxaui_csr_rx_status_1 = {rx_errdetect_sr, rx_disperr_sr};
+
+//--- rx_status_2 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ rx_phase_comp_fifo_error_c <= rx_phase_comp_fifo_error;
+ rx_rlv_c <= rx_rlv;
+end
+
+assign read_rx_status_2 = read && (addr == HXAUI_CSR_RX_STATUS_2_ADDR);
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ rx_phase_comp_fifo_error_sr <= 4'h0;
+ rx_rlv_sr <= 4'h0;
+ end else begin
+ rx_phase_comp_fifo_error_sr <= rx_phase_comp_fifo_error_c |
+ (rx_phase_comp_fifo_error_sr & {4{read_rx_status_2}});
+ rx_rlv_sr <= rx_rlv_c |
+ (rx_rlv_sr & {4{read_rx_status_2}});
+ end
+end
+
+assign hxaui_csr_rx_status_2 = {rx_phase_comp_fifo_error_sr, rx_rlv_sr};
+
+//--- rx_status_3 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ rx_rmfifodatainserted_c <= rx_rmfifodatainserted;
+ rx_rmfifodatadeleted_c <= rx_rmfifodatadeleted;
+end
+
+assign read_rx_status_3 = read && (addr == HXAUI_CSR_RX_STATUS_3_ADDR);
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ rx_rmfifodatainserted_sr <= 8'h0;
+ rx_rmfifodatadeleted_sr <= 8'h0;
+ end else begin
+ rx_rmfifodatainserted_sr <= rx_rmfifodatainserted_c |
+ (rx_rmfifodatainserted_sr & {8{read_rx_status_3}});
+ rx_rmfifodatadeleted_sr <= rx_rmfifodatadeleted_c |
+ (rx_rmfifodatadeleted_sr & {8{read_rx_status_3}});
+ end
+end
+
+assign hxaui_csr_rx_status_3 = {rx_rmfifodatainserted_sr,
+ rx_rmfifodatadeleted_sr};
+
+//--- rx_status_4 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ rx_rmfifoempty_c <= rx_rmfifoempty;
+ rx_rmfifofull_c <= rx_rmfifofull;
+end
+
+assign read_rx_status_4 = read && (addr == HXAUI_CSR_RX_STATUS_4_ADDR);
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ rx_rmfifoempty_sr <= 4'h0;
+ rx_rmfifofull_sr <= 4'h0;
+ end else begin
+ rx_rmfifoempty_sr <= rx_rmfifoempty_c |
+ (rx_rmfifoempty_sr & {4{read_rx_status_4}});
+ rx_rmfifofull_sr <= rx_rmfifofull_c |
+ (rx_rmfifofull_sr & {4{read_rx_status_4}});
+ end
+end
+
+assign hxaui_csr_rx_status_4 = {rx_rmfifoempty_sr, rx_rmfifofull_sr};
+
+//--- tx_status_0 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ tx_phase_comp_fifo_error_c <= tx_phase_comp_fifo_error;
+end
+
+assign read_tx_status_0 = read && (addr == HXAUI_CSR_TX_STATUS_0_ADDR);
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ tx_phase_comp_fifo_error_sr <= 4'h0;
+ end else begin
+ tx_phase_comp_fifo_error_sr <= tx_phase_comp_fifo_error_c |
+ (tx_phase_comp_fifo_error_sr & {4{read_tx_status_0}});
+ end
+end
+
+assign hxaui_csr_tx_status_0 = tx_phase_comp_fifo_error_sr;
+
+
+endmodule // hxaui_csr
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/hxaui_csr_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/hxaui_csr_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..b4856c0cf54dc1a394a545937fa14fa28b03a1ce
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/hxaui_csr_h.sv
@@ -0,0 +1,155 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// (C) 2001-2011 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+///////////////////////////////////////////////////////////////////////////////
+//
+//
+// Description: Hard xaui control and status registers header file
+//
+// Authors: ishimony 12-Jun-2009
+//
+// Copyright (c) Altera Corporation 1997 - 2009
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+`timescale 1 ps / 1 ps
+
+package hxaui_csr_h;
+
+
+// address map
+localparam [11:0]ALT_PMA_CONTROLLER_ADDR =12'h080;
+localparam [11:0]ALT_PMA_CH_CONTROLLER_ADDR =12'h180;
+//localparam ALT_PMA_ADDR 12'h080
+localparam [11:0]ALT_RECONFIG_ANALOG_ADDR =12'h400;
+localparam [11:0]ALT_RECONFIG_OC_ADDR =12'h408;
+localparam [11:0]HXAUI_CSR_ADDR =12'h200;
+
+
+// registers address -------------------------------------------------------
+// preserve 7'h00 for indirection register (future implementation)
+localparam [6:0]HXAUI_CSR_RESET_ADDR =7'h04;
+localparam [6:0]HXAUI_CSR_RX_CNTRL_ADDR =7'h08;
+localparam [6:0]HXAUI_CSR_TX_CNTRL_ADDR =7'h0C;
+localparam [6:0]HXAUI_CSR_RX_STATUS_0_ADDR =7'h10;
+localparam [6:0]HXAUI_CSR_RX_STATUS_1_ADDR =7'h14;
+localparam [6:0]HXAUI_CSR_RX_STATUS_2_ADDR =7'h18;
+localparam [6:0]HXAUI_CSR_RX_STATUS_3_ADDR =7'h1C;
+localparam [6:0]HXAUI_CSR_RX_STATUS_4_ADDR =7'h20;
+localparam [6:0]HXAUI_CSR_TX_STATUS_0_ADDR =7'h24;
+localparam [6:0]HXAUI_CSR_SIMULATION_FLAG_ADDR =7'h28;
+
+// register bitmap ---------------------------------------------------------
+localparam [32:0]HXAUI_CSR_RESET_RX_DIGITAL =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RESET_TX_DIGITAL =32'h0000_0002;
+
+localparam [32:0]HXAUI_CSR_RX_CNTRL_INVPOLARITY_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_CNTRL_INVPOLARITY_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_CNTRL_INVPOLARITY_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_CNTRL_INVPOLARITY_3 =32'h0000_0008;
+
+localparam [32:0]HXAUI_CSR_TX_CNTRL_INVPOLARITY_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_TX_CNTRL_INVPOLARITY_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_TX_CNTRL_INVPOLARITY_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_TX_CNTRL_INVPOLARITY_3 =32'h0000_0008;
+
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_3 =32'h0000_0008;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_4 =32'h0000_0010;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_5 =32'h0000_0020;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_6 =32'h0000_0040;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_7 =32'h0000_0080;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_0 =32'h0000_0100;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_1 =32'h0000_0200;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_2 =32'h0000_0400;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_3 =32'h0000_0800;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_4 =32'h0000_1000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_5 =32'h0000_2000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_6 =32'h0000_4000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_7 =32'h0000_8000;
+
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_3 =32'h0000_0008;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_4 =32'h0000_0010;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_5 =32'h0000_0020;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_6 =32'h0000_0040;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_7 =32'h0000_0080;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_0 =32'h0000_0100;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_1 =32'h0000_0200;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_2 =32'h0000_0400;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_3 =32'h0000_0800;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_4 =32'h0000_1000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_5 =32'h0000_2000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_6 =32'h0000_4000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_7 =32'h0000_8000;
+
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_RLV_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_RLV_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_RLV_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_RLV_3 =32'h0000_0008;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_PHASE_COMP_FIFO_ERROR_0 =32'h0000_0010;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_PHASE_COMP_FIFO_ERROR_1 =32'h0000_0020;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_PHASE_COMP_FIFO_ERROR_2 =32'h0000_0040;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_PHASE_COMP_FIFO_ERROR_3 =32'h0000_0080;
+
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_3 =32'h0000_0008;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_4 =32'h0000_0010;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_5 =32'h0000_0020;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_6 =32'h0000_0040;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_7 =32'h0000_0080;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_0 =32'h0000_0100;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_1 =32'h0000_0200;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_2 =32'h0000_0400;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_3 =32'h0000_0800;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_4 =32'h0000_1000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_5 =32'h0000_2000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_6 =32'h0000_4000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_7 =32'h0000_8000;
+
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOFULL_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOFULL_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOFULL_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOFULL_3 =32'h0000_0008;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOEMPTY_0 =32'h0000_0010;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOEMPTY_1 =32'h0000_0020;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOEMPTY_2 =32'h0000_0040;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOEMPTY_3 =32'h0000_0080;
+
+localparam [32:0]HXAUI_CSR_TX_STATUS_0_PHASE_COMP_FIFO_ERROR_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_TX_STATUS_0_PHASE_COMP_FIFO_ERROR_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_TX_STATUS_0_PHASE_COMP_FIFO_ERROR_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_TX_STATUS_0_PHASE_COMP_FIFO_ERROR_3 =32'h0000_0008;
+
+localparam [32:0]HXAUI_CSR_SIMULATION_FLAG =32'h0000_0001;
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/plain_files.txt b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/plain_files.txt
new file mode 100644
index 0000000000000000000000000000000000000000..96175539fe10e847160e3bb13c7980081beae5b3
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/plain_files.txt
@@ -0,0 +1,34 @@
+./altera_xcvr_functions.sv
+./altera_xcvr_xaui.sv
+./hxaui_csr_h.sv
+./hxaui_csr.sv
+./alt_xcvr_mgmt2dec_phyreconfig.sv
+./alt_xcvr_mgmt2dec_xaui.sv
+./alt_pma_ch_controller_tgx.v
+./alt_pma_controller_tgx.v
+./alt_reset_ctrl_lego.sv
+./alt_reset_ctrl_tgx_cdrauto.sv
+./alt_xcvr_resync.sv
+./alt_xcvr_csr_common_h.sv
+./alt_xcvr_csr_common.sv
+./alt_xcvr_csr_pcs8g_h.sv
+./alt_xcvr_csr_pcs8g.sv
+./alt_xcvr_csr_selector.sv
+./alt_xcvr_mgmt2dec.sv
+./altera_wait_generate.v
+./hxaui_alt4gxb.v
+./hxaui.v
+./siv_xcvr_xaui.sv
+./alt_xcvr_reconfig_h.sv
+./alt_xcvr_reconfig_siv.sv
+./alt_xcvr_reconfig_analog.sv
+./alt_xcvr_reconfig_analog_tgx.v
+./alt_xcvr_reconfig_offset_cancellation.sv
+./alt_xcvr_reconfig_offset_cancellation_tgx.v
+./alt_xcvr_reconfig_eyemon_tgx.sv
+./alt_xcvr_reconfig_dfe_tgx.sv
+./alt_xcvr_reconfig_basic_tgx.v
+./alt_mutex_acq.v
+./alt_dprio.v
+./alt_xcvr_arbiter.sv
+./alt_xcvr_m2s.sv
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/qencrypt_files.txt b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/qencrypt_files.txt
new file mode 100644
index 0000000000000000000000000000000000000000..96175539fe10e847160e3bb13c7980081beae5b3
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/qencrypt_files.txt
@@ -0,0 +1,34 @@
+./altera_xcvr_functions.sv
+./altera_xcvr_xaui.sv
+./hxaui_csr_h.sv
+./hxaui_csr.sv
+./alt_xcvr_mgmt2dec_phyreconfig.sv
+./alt_xcvr_mgmt2dec_xaui.sv
+./alt_pma_ch_controller_tgx.v
+./alt_pma_controller_tgx.v
+./alt_reset_ctrl_lego.sv
+./alt_reset_ctrl_tgx_cdrauto.sv
+./alt_xcvr_resync.sv
+./alt_xcvr_csr_common_h.sv
+./alt_xcvr_csr_common.sv
+./alt_xcvr_csr_pcs8g_h.sv
+./alt_xcvr_csr_pcs8g.sv
+./alt_xcvr_csr_selector.sv
+./alt_xcvr_mgmt2dec.sv
+./altera_wait_generate.v
+./hxaui_alt4gxb.v
+./hxaui.v
+./siv_xcvr_xaui.sv
+./alt_xcvr_reconfig_h.sv
+./alt_xcvr_reconfig_siv.sv
+./alt_xcvr_reconfig_analog.sv
+./alt_xcvr_reconfig_analog_tgx.v
+./alt_xcvr_reconfig_offset_cancellation.sv
+./alt_xcvr_reconfig_offset_cancellation_tgx.v
+./alt_xcvr_reconfig_eyemon_tgx.sv
+./alt_xcvr_reconfig_dfe_tgx.sv
+./alt_xcvr_reconfig_basic_tgx.v
+./alt_mutex_acq.v
+./alt_dprio.v
+./alt_xcvr_arbiter.sv
+./alt_xcvr_m2s.sv
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/siv_xcvr_xaui.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/siv_xcvr_xaui.sv
new file mode 100644
index 0000000000000000000000000000000000000000..16ad2c9b0c247529918db040a9c41da5f8639e0c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0/siv_xcvr_xaui.sv
@@ -0,0 +1,539 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//-----------------------------------------------------------------------------
+//
+// Description: hxaui static verilog for Stratix IV
+//
+// Authors: bauyeung 7-Sep-2010
+//
+// Copyright (c) Altera Corporation 1997 - 2010
+// All rights reserved.
+//
+//-----------------------------------------------------------------------------
+ /*ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"set_false_path -from [get_registers *hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component*] -to [get_registers *xaui_phy*hxaui_csr*tx_phase_comp_fifo_error_c[*]]\" " */
+
+module siv_xcvr_xaui #(
+ parameter device_family = "Stratix IV",
+ parameter starting_channel_number = 0,
+ parameter interface_type = "Hard XAUI",
+ parameter number_of_interfaces = 1,
+ parameter sys_clk_in_mhz = 50,
+ parameter xaui_pll_type = "CMU",
+ parameter reconfig_interfaces = 1,
+ parameter use_control_and_status_ports = 0,
+ parameter external_pma_ctrl_reconf = 0,
+ parameter tx_termination = "OCT_150_OHMS",
+ parameter tx_vod_selection = 1,
+ parameter tx_preemp_pretap = 0,
+ parameter tx_preemp_pretap_inv = 0,
+ parameter tx_preemp_tap_1 = 5,
+ parameter tx_preemp_tap_2 = 0,
+ parameter tx_preemp_tap_2_inv = 0,
+ parameter rx_common_mode = "0.82v",
+ parameter rx_termination = "OCT_150_OHMS",
+ parameter rx_eq_dc_gain = 0,
+ parameter rx_eq_ctrl = 14
+) (
+ input wire pll_ref_clk, // refclk.clk
+ input wire xgmii_tx_clk, // xgmii_tx_clk.clk
+ output wire xgmii_rx_clk, // xgmii_rx_clk.clk
+ input wire phy_mgmt_clk, // mgmt_clk.clk
+ input wire phy_mgmt_clk_reset, // mgmt_clk_rst.reset_n
+ input wire [7:0] phy_mgmt_address, // phy_mgmt.address
+ output wire phy_mgmt_waitrequest, // .waitrequest
+ input wire phy_mgmt_read, // .read
+ output wire [31:0] phy_mgmt_readdata, // .readdata
+ input wire phy_mgmt_write, // .write
+ input wire [31:0] phy_mgmt_writedata, // .writedata
+ input wire [71:0] xgmii_tx_dc, // xgmii_tx_dc.data
+ output wire [71:0] xgmii_rx_dc, // xgmii_rx_dc.data
+ output wire [3:0] xaui_tx_serial_data, // xaui_tx_serial.export
+ input wire [3:0] xaui_rx_serial_data, // xaui_rx_serial.export
+ output wire rx_ready, // rx_pma_ready.data
+ output wire tx_ready, // tx_pma_ready.data
+ output tri0 [altera_xcvr_functions::get_reconfig_from_width(device_family,reconfig_interfaces)-1:0] reconfig_from_xcvr,
+ input tri0 [altera_xcvr_functions::get_reconfig_to_width(device_family,reconfig_interfaces) -1:0] reconfig_to_xcvr,
+
+ output wire [3:0] rx_recovered_clk, // rx recovered clock from cdr
+// optional control and status ports
+ input wire rx_analogreset,
+ input wire rx_digitalreset,
+ input wire tx_digitalreset,
+ output wire rx_channelaligned,
+ input wire [3:0] rx_invpolarity,
+ input wire [3:0] rx_set_locktodata,
+ input wire [3:0] rx_set_locktoref,
+ input wire [3:0] rx_seriallpbken,
+ input wire [3:0] tx_invpolarity,
+ output wire [3:0] rx_is_lockedtodata,
+ output wire [3:0] rx_phase_comp_fifo_error,
+ output wire [3:0] rx_is_lockedtoref,
+ output wire [3:0] rx_rlv,
+ output wire [3:0] rx_rmfifoempty,
+ output wire [3:0] rx_rmfifofull,
+ output wire [3:0] tx_phase_comp_fifo_error,
+ output wire [7:0] rx_disperr,
+ output wire [7:0] rx_errdetect,
+ output wire [7:0] rx_patterndetect,
+ output wire [7:0] rx_rmfifodatadeleted,
+ output wire [7:0] rx_rmfifodatainserted,
+ output wire [7:0] rx_runningdisp,
+ output wire [7:0] rx_syncstatus,
+
+// external_pma_ctrl_reconf
+ output wire pll_locked,
+ input wire cal_blk_powerdown,
+ input wire gxb_powerdown,
+ input wire pll_powerdown
+);
+
+import altera_xcvr_functions::*;
+
+ wire alt_pma_controller_0_cal_blk_pdn_data;
+ wire alt_pma_controller_0_pll_pdn0_data;
+ wire alt_pma_controller_0_gx_pdn_data;
+ wire pll_locked_data;
+ wire [7:0] rx_disperr_data;
+ wire [7:0] rx_errdetect_data;
+ wire [7:0] rx_patterndetect_data;
+ wire [3:0] rx_phase_comp_fifo_error_data;
+ wire [3:0] rx_rlv_data;
+ wire [7:0] rx_rmfifodatadeleted_data;
+ wire [7:0] rx_rmfifodatainserted_data;
+ wire [3:0] rx_rmfifoempty_data;
+ wire [3:0] rx_rmfifofull_data;
+ wire [7:0] rx_runningdisp_data;
+ wire [7:0] rx_syncstatus_data;
+ wire [3:0] tx_phase_comp_fifo_error_data;
+ wire [3:0] alt_pma_ch_controller_0_rx_set_locktodata_data;
+ wire [3:0] alt_pma_ch_controller_0_rx_set_locktoref_data;
+ wire [3:0] alt_pma_ch_controller_0_rx_seriallpbken_data;
+ wire [3:0] alt_pma_ch_controller_0_rx_analog_rst_data;
+ wire [3:0] rx_is_lockedtodata_data;
+ wire [3:0] rx_is_lockedtoref_data;
+ wire [3:0] alt_pma_ch_controller_0_tx_digital_rst_data;
+ wire [3:0] alt_pma_ch_controller_0_rx_digital_rst_data;
+ wire hxaui_csr_r_rx_digitalreset_data;
+ wire [3:0] hxaui_csr_r_rx_invpolarity_data;
+ wire hxaui_csr_r_tx_digitalreset_data;
+ wire [3:0] hxaui_csr_r_tx_invpolarity_data;
+ wire hxaui_csr_simulation_flag_data;
+ wire alt_pma_controller_0_pll_pdn;
+ wire [3:0] alt_pma_0_tx_out_clk_clk;
+ wire [3:0] alt_pma_0_rx_recovered_clk_clk;
+ wire [79:0] sxaui_0_tx_parallel_data_data;
+ wire [79:0] alt_pma_0_rx_parallel_data_data;
+ wire [3:0] alt_pma_0_rx_is_lockedtodata_data;
+ wire rx_pma_ready;
+ wire sxaui_rst_done;
+
+
+ wire [5:0] sc_pma_ch_controller_address;
+ wire sc_pma_ch_controller_read;
+ wire [31:0] sc_pma_ch_controller_readdata;
+ wire sc_pma_ch_controller_waitrequest;
+ wire sc_pma_ch_controller_write;
+
+
+ wire [1:0] sc_pma_controller_address;
+ wire sc_pma_controller_read;
+ wire [31:0] sc_pma_controller_readdata;
+ wire sc_pma_controller_waitrequest;
+ wire sc_pma_controller_write;
+
+ wire [4:0] sc_csr_address;
+ wire sc_csr_read;
+ wire [31:0] sc_csr_readdata;
+ wire sc_csr_write;
+
+// assign output wires for status ports - whether or not they are used will be decided by the top level
+ assign rx_is_lockedtodata = rx_is_lockedtodata_data;
+ assign rx_phase_comp_fifo_error = rx_phase_comp_fifo_error_data;
+ assign rx_is_lockedtoref = rx_is_lockedtoref_data;
+ assign rx_rlv = rx_rlv_data;
+ assign rx_rmfifoempty = rx_rmfifoempty_data;
+ assign rx_rmfifofull = rx_rmfifofull_data;
+ assign tx_phase_comp_fifo_error = tx_phase_comp_fifo_error_data;
+ assign rx_disperr = rx_disperr_data;
+ assign rx_errdetect = rx_errdetect_data;
+ assign rx_patterndetect = rx_patterndetect_data;
+ assign rx_rmfifodatadeleted = rx_rmfifodatadeleted_data;
+ assign rx_rmfifodatainserted = rx_rmfifodatainserted_data;
+ assign rx_runningdisp = rx_runningdisp_data;
+ assign rx_syncstatus = rx_syncstatus_data;
+ assign rx_recovered_clk = alt_pma_0_rx_recovered_clk_clk;
+
+ // assign output wires for external pma_ctrl - whether or not they are used will be decided by the top level
+ assign pll_locked = pll_locked_data;
+ assign rx_ready = rx_pma_ready & sxaui_rst_done; // pma and PCS must be both ready
+
+ ///////////////////////////////////////////////////////////////////////
+ // Decoder for multiple slaves of pma_ch_control,pma_control,hxaui i/f
+ ///////////////////////////////////////////////////////////////////////
+ alt_xcvr_mgmt2dec_xaui mgmtdec_xaui (
+ .mgmt_clk_reset (phy_mgmt_clk_reset),
+ .mgmt_clk (phy_mgmt_clk),
+ .mgmt_address (phy_mgmt_address),
+ .mgmt_read (phy_mgmt_read),
+ .mgmt_write (phy_mgmt_write),
+ .mgmt_readdata (phy_mgmt_readdata),
+ .mgmt_waitrequest (phy_mgmt_waitrequest),
+
+ // internal interface to 'top' pma ch controller block
+ .sc_pma_ch_controller_readdata (sc_pma_ch_controller_readdata),
+ .sc_pma_ch_controller_waitrequest (sc_pma_ch_controller_waitrequest),
+ .sc_pma_ch_controller_address (sc_pma_ch_controller_address), //6 bit wide
+ .sc_pma_ch_controller_read (sc_pma_ch_controller_read),
+ .sc_pma_ch_controller_write (sc_pma_ch_controller_write),
+
+ // internal interface to 'top' pma controller block
+ .sc_pma_controller_readdata (sc_pma_controller_readdata),
+ .sc_pma_controller_waitrequest (sc_pma_controller_waitrequest),
+ .sc_pma_controller_address (sc_pma_controller_address), //2 bit wide
+ .sc_pma_controller_read (sc_pma_controller_read),
+ .sc_pma_controller_write (sc_pma_controller_write),
+
+ // internal interface to 'top' hxaui csr block
+ .sc_csr_readdata (sc_csr_readdata),
+ .sc_csr_waitrequest (1'b0), // PCS CSR is always ready
+ .sc_csr_address (sc_csr_address), //5 bit wide
+ .sc_csr_read (sc_csr_read),
+ .sc_csr_write (sc_csr_write)
+ );
+
+ ///////////////////////////////////////////////////////////////////////
+ // PMA Channel Controller - only for HXAUI
+ ///////////////////////////////////////////////////////////////////////
+// add generate for hxaui/sxaui - only use ch_controller for hxaui
+ generate
+ if (interface_type == "Hard XAUI") begin
+ alt_pma_ch_controller_tgx #(
+ .number_of_channels (4),
+ .sync_depth (2),
+ .sys_clk_in_mhz (sys_clk_in_mhz)
+ ) alt_pma_ch_controller_0 (
+ .clk (phy_mgmt_clk),
+ .rst (phy_mgmt_clk_reset),
+ .ch_mgmt_address (sc_pma_ch_controller_address),
+ .ch_mgmt_read (sc_pma_ch_controller_read),
+ .ch_mgmt_readdata (sc_pma_ch_controller_readdata),
+ .ch_mgmt_write (sc_pma_ch_controller_write),
+ .ch_mgmt_writedata (phy_mgmt_writedata),
+ .ch_mgmt_waitrequest (sc_pma_ch_controller_waitrequest),
+ .rx_pma_ready (rx_pma_ready),
+ .tx_pma_ready (tx_ready),
+ .rx_is_lockedtodata (rx_is_lockedtodata_data),
+ .rx_is_lockedtoref (rx_is_lockedtoref_data),
+ .rx_set_locktodata (alt_pma_ch_controller_0_rx_set_locktodata_data),
+ .rx_set_locktoref (alt_pma_ch_controller_0_rx_set_locktoref_data),
+ .rx_seriallpbken (alt_pma_ch_controller_0_rx_seriallpbken_data),
+ .rx_analog_rst (alt_pma_ch_controller_0_rx_analog_rst_data),
+ .tx_digital_rst (alt_pma_ch_controller_0_tx_digital_rst_data),
+ .rx_digital_rst (alt_pma_ch_controller_0_rx_digital_rst_data),
+ .rx_rst_digital (rx_digitalreset), // optional user triggered rx_digitalreset
+ .tx_rst_digital (tx_digitalreset), // optional user triggered tx_digitalreset
+ //reconfig_to_xcvr bit configuration
+ //Bit | Value
+ //-------------------------------------------
+ //3 | offset_cancellation_is_busy |
+ //2 | dprio_load |
+ //1 | dprio_disable |
+ //0 | dprio_in |
+ //-------------------------------------------
+ // .rx_oc_busy (reconfig_to_xcvr[3]), // rx_oc_busy.data
+ .rx_cal_busy (reconfig_to_xcvr[3]), // rx_oc_busy.data
+ .tx_cal_busy (1'b0), // rx_oc_busy.data
+ .pll_locked (pll_locked_data)
+ );
+ end else if (interface_type == "Soft XAUI") begin
+ siv_xcvr_low_latency_phy_nr #(
+ .device_family (device_family),
+ .intended_device_variant ("ANY"),
+ .number_of_channels (4),
+ .number_of_reconfig_interface (reconfig_interfaces),
+ .operation_mode ("DUPLEX"),
+ .phase_comp_fifo_mode ("NONE"),
+ .serialization_factor (20),
+ .data_rate ("3125 Mbps"),
+ .pll_input_frequency ("156.25 MHz"),
+ .number_pll_inclks (1),
+ .pll_inclk_select (0),
+ .pll_type (xaui_pll_type),
+ .starting_channel_number (starting_channel_number),
+ .bonded_mode ("TRUE"),
+ .sys_clk_in_mhz (sys_clk_in_mhz),
+ //.rx_bitslip_en (0),
+ //.tx_bitslip_en (0),
+ //.select_10g_pcs (0),
+ //.tx_use_coreclk (0),
+ //.rx_use_coreclk (0),
+ .gx_analog_power ("AUTO"),
+ .pll_lock_speed ("AUTO"),
+ .tx_analog_power ("AUTO"),
+ .tx_slew_rate ("OFF"),
+ .tx_termination (tx_termination),
+ .tx_common_mode ("0.65V"),
+ .rx_pll_lock_speed ("AUTO"),
+ .rx_common_mode (rx_common_mode),
+ .rx_signal_detect_threshold (2),
+ .rx_ppmselect (32),
+ .rx_termination (rx_termination),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv ((tx_preemp_pretap_inv==1)? "TRUE" : "FALSE"),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv ((tx_preemp_tap_2_inv==1)? "TRUE" : "FALSE"),
+ .tx_vod_selection (tx_vod_selection),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .rx_use_cruclk ("FALSE"),
+ .loopback_mode ("SLB")
+ ) alt_pma_0 (
+ .clk (phy_mgmt_clk),
+ .rst (phy_mgmt_clk_reset),
+ .gx_pdn (alt_pma_controller_0_gx_pdn_data),
+ .ch_mgmt_address (sc_pma_ch_controller_address),
+ .ch_mgmt_read (sc_pma_ch_controller_read),
+ .ch_mgmt_readdata (sc_pma_ch_controller_readdata),
+ .ch_mgmt_write (sc_pma_ch_controller_write),
+ .ch_mgmt_writedata (phy_mgmt_writedata),
+ .ch_mgmt_waitrequest (sc_pma_ch_controller_waitrequest),
+ .cal_blk_clk (phy_mgmt_clk),
+ .cal_blk_pdn (alt_pma_controller_0_cal_blk_pdn_data),
+ .pll_ref_clk (pll_ref_clk),
+ .tx_out_clk (alt_pma_0_tx_out_clk_clk),
+ .tx_parallel_data (sxaui_0_tx_parallel_data_data),
+ .tx_serial_data (xaui_tx_serial_data),
+ .tx_pma_ready (tx_ready),
+ .pll_pdn (alt_pma_controller_0_pll_pdn0_data),
+ .pll_locked (pll_locked_data),
+ .rx_is_lockedtodata (alt_pma_0_rx_is_lockedtodata_data),
+ .rx_is_lockedtoref (),
+ .rx_recovered_clk (alt_pma_0_rx_recovered_clk_clk),
+ .rx_serial_data (xaui_rx_serial_data),
+ .rx_parallel_data (alt_pma_0_rx_parallel_data_data),
+ .rx_cdr_ref_clk (),
+ .rx_pma_ready (rx_pma_ready),
+ .reconfig_clk (phy_mgmt_clk),
+ .reconfig_to_gxb (reconfig_to_xcvr),
+ .reconfig_from_gxb (reconfig_from_xcvr),
+ .rx_rst_digital (rx_digitalreset), //optional user triggered rx_digitalreset
+ .tx_rst_digital (tx_digitalreset), //optional user triggered tx_digitalreset
+ //.tx_bitslip (28'b0),
+ //.tx_coreclk (4'b0),
+ //.rx_offset_cancellation_done (1'b1),
+ //.rx_bitslip (4'b0),
+ //.rx_parallel_data_read (4'b0),
+ //.rx_coreclk (4'b0),
+ //.aeq_to_gxb (96'b0),
+ //.aeq_from_gxb (),
+ .tx_digital_rst (alt_pma_ch_controller_0_tx_digital_rst_data),
+ .rx_digital_rst (alt_pma_ch_controller_0_rx_digital_rst_data)
+ );
+ end
+ // don't instantiate anything if the interface type is invalid
+ endgenerate
+
+ ///////////////////////////////////////////////////////////////////////
+ // PMA Controller
+ ///////////////////////////////////////////////////////////////////////
+ generate
+ if (external_pma_ctrl_reconf == 0) begin
+ alt_pma_controller_tgx #(
+ .number_of_plls (1),
+ .sync_depth (2),
+ .tx_pll_reset_hold_time (20)
+ ) alt_pma_controller_0 (
+ .clk (phy_mgmt_clk),
+ .rst (phy_mgmt_clk_reset),
+ .pma_mgmt_address (sc_pma_controller_address),
+ .pma_mgmt_read (sc_pma_controller_read),
+ .pma_mgmt_readdata (sc_pma_controller_readdata),
+ .pma_mgmt_write (sc_pma_controller_write),
+ .pma_mgmt_writedata (phy_mgmt_writedata),
+ .pma_mgmt_waitrequest (sc_pma_controller_waitrequest),
+ .cal_blk_clk (phy_mgmt_clk),
+ .cal_blk_pdn (alt_pma_controller_0_cal_blk_pdn_data),
+ .tx_pll_ready (),
+ .gx_pdn (alt_pma_controller_0_gx_pdn_data),
+ .pll_pdn (alt_pma_controller_0_pll_pdn0_data),
+ .pll_locked (pll_locked_data)
+ );
+ end else begin
+ assign alt_pma_controller_0_cal_blk_pdn_data = cal_blk_powerdown;
+ assign alt_pma_controller_0_gx_pdn_data = gxb_powerdown;
+ assign alt_pma_controller_0_pll_pdn0_data = pll_powerdown;
+ end
+ endgenerate
+
+
+ ///////////////////////////////////////////////////////////////////////
+ // HXAUI CSR
+ ///////////////////////////////////////////////////////////////////////
+// should be consistent across all device families and interface types
+// -might need a generate statement for some of the connections that don't exist between hxaui/sxaui
+ hxaui_csr hxaui_csr (
+ .clk (phy_mgmt_clk),
+ .reset (phy_mgmt_clk_reset),
+ .address (sc_csr_address),
+ .byteenable (4'b1111), // .byteenable (Tie byteenable to all 1s)
+ .read (sc_csr_read),
+ .readdata (sc_csr_readdata),
+ .write (sc_csr_write),
+ .writedata (phy_mgmt_writedata),
+ .rx_patterndetect (rx_patterndetect_data),
+ .rx_syncstatus (rx_syncstatus_data),
+ .rx_runningdisp (rx_runningdisp_data),
+ .rx_errdetect (rx_errdetect_data),
+ .rx_disperr (rx_disperr_data),
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error_data),
+ .rx_rlv (rx_rlv_data),
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted_data),
+ .rx_rmfifodatainserted (rx_rmfifodatainserted_data),
+ .rx_rmfifoempty (rx_rmfifoempty_data),
+ .rx_rmfifofull (rx_rmfifofull_data),
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error_data),
+ .r_rx_invpolarity (hxaui_csr_r_rx_invpolarity_data),
+ .r_tx_invpolarity (hxaui_csr_r_tx_invpolarity_data),
+ .r_rx_digitalreset (hxaui_csr_r_rx_digitalreset_data),
+ .r_tx_digitalreset (hxaui_csr_r_tx_digitalreset_data),
+ .simulation_flag (hxaui_csr_simulation_flag_data) // only for soft_xaui
+ );
+
+
+ ///////////////////////////////////////////////////////////////////////
+ // HXAUI - Interface to alt4gxb megafunction block
+ ///////////////////////////////////////////////////////////////////////
+// need to add generate to pick between sxaui and hxaui
+ generate
+ if (interface_type == "Hard XAUI") begin
+ (* ALTERA_ATTRIBUTE = {"-name SDC_STATEMENT \"set_false_path -from [get_registers *hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component*fifo*flow] -to [get_registers *xaui_phy*hxaui_csr*tx_phase_comp_fifo_error_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers *hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component*] -to [get_registers *xaui_phy*hxaui_csr*rx*_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*siv_xcvr_xaui*hxaui_csr*hxaui_csr_reset0q[*]}] -to [get_registers {*xaui_phy*hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component|*digitalreset*}]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*siv_xcvr_xaui*alt_pma_ch_controller_0*rc*}] -to [get_registers {*xaui_phy*hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component|*digitalreset*}]\""} *)
+ hxaui #(
+ .device_family (device_family),
+ .starting_channel_number (starting_channel_number),
+ .xaui_pll_type (xaui_pll_type),
+ .use_control_and_status_ports (use_control_and_status_ports),
+ .external_pma_ctrl_reconf (external_pma_ctrl_reconf),
+ .tx_termination (tx_termination),
+ .rx_termination (rx_termination),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv (tx_preemp_pretap_inv),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv (tx_preemp_tap_2_inv),
+ .tx_vod_selection (tx_vod_selection),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .rx_common_mode (rx_common_mode)
+ ) hxaui_0 (
+ .xgmii_tx_clk (xgmii_tx_clk),
+ .xgmii_tx_dc (xgmii_tx_dc),
+ .xgmii_rx_clk (xgmii_rx_clk),
+ .xgmii_rx_dc (xgmii_rx_dc),
+ .refclk (pll_ref_clk),
+ .xaui_tx_serial (xaui_tx_serial_data),
+ .xaui_rx_serial (xaui_rx_serial_data),
+ .rx_analogreset (rx_analogreset), // use_cs_ports, input
+ .rx_digitalreset (alt_pma_ch_controller_0_rx_digital_rst_data),
+ .tx_digitalreset (alt_pma_ch_controller_0_tx_digital_rst_data),
+ .rx_channelaligned (rx_channelaligned), // use_cs_ports, output
+ .rx_invpolarity (rx_invpolarity), // use_cs_ports, input
+ .rx_set_locktodata (rx_set_locktodata), // use_cs_ports, input
+ .rx_set_locktoref (rx_set_locktoref), // use_cs_ports, input
+ .rx_seriallpbken (rx_seriallpbken), // use_cs_ports, input
+ .tx_invpolarity (tx_invpolarity), // use_cs_ports, input
+ .rx_is_lockedtodata (rx_is_lockedtodata_data), // use_cs_ports, output
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error_data), // use_cs_ports, output
+ .rx_is_lockedtoref (rx_is_lockedtoref_data), // use_cs_ports, output
+ .rx_rlv (rx_rlv_data), // use_cs_ports, output
+ .rx_rmfifoempty (rx_rmfifoempty_data), // use_cs_ports, output
+ .rx_rmfifofull (rx_rmfifofull_data), // use_cs_ports, output
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error_data), // use_cs_ports, output
+ .rx_disperr (rx_disperr_data), // use_cs_ports, output
+ .rx_errdetect (rx_errdetect_data), // use_cs_ports, output
+ .rx_patterndetect (rx_patterndetect_data), // use_cs_ports, output
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted_data), // use_cs_ports, output
+ .rx_rmfifodatainserted (rx_rmfifodatainserted_data), // use_cs_ports, output
+ .rx_runningdisp (rx_runningdisp_data), // use_cs_ports, output
+ .rx_syncstatus (rx_syncstatus_data), // use_cs_ports, output
+ .reconfig_clk (phy_mgmt_clk),
+ .reconfig_togxb (reconfig_to_xcvr), // external_pma_ctrl_reconf
+ .reconfig_fromgxb (reconfig_from_xcvr[16:0]), // external_pma_ctrl_reconf
+ .rx_recovered_clk (alt_pma_0_rx_recovered_clk_clk),
+ .cal_blk_clk (phy_mgmt_clk),
+ .cal_blk_powerdown (1'b0), // not used, should remove
+ .gxb_powerdown (1'b0), // not used, should remove
+ .pll_powerdown (1'b0), // not used, should remove
+ .pll_locked (pll_locked_data),
+ .r_cal_blk_powerdown (alt_pma_controller_0_cal_blk_pdn_data),
+ .r_gxb_powerdown (alt_pma_controller_0_gx_pdn_data),
+ .r_pll_powerdown (alt_pma_controller_0_pll_pdn0_data),
+ .r_rx_set_locktodata (alt_pma_ch_controller_0_rx_set_locktodata_data),
+ .r_rx_set_locktoref (alt_pma_ch_controller_0_rx_set_locktoref_data),
+ .r_rx_seriallpbken (alt_pma_ch_controller_0_rx_seriallpbken_data),
+ .r_rx_analogreset (alt_pma_ch_controller_0_rx_analog_rst_data),
+ .r_rx_digitalreset (hxaui_csr_r_rx_digitalreset_data),
+ .r_tx_digitalreset (hxaui_csr_r_tx_digitalreset_data),
+ .r_rx_invpolarity (hxaui_csr_r_rx_invpolarity_data),
+ .r_tx_invpolarity (hxaui_csr_r_tx_invpolarity_data)
+ );
+ assign sxaui_rst_done = 1'b1; // if using hard xaui, assign this to 1 to always be ready
+ end else if (interface_type == "Soft XAUI") begin
+ (* ALTERA_ATTRIBUTE = {" -name SDC_STATEMENT \"set_false_path -from [get_registers {*sxaui_0*alt_soft_xaui_pcs*xaui_rx*disp_err_delay[*]}] -to [get_registers *xaui_phy*hxaui_csr*rx*_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*sxaui_0*alt_soft_xaui_pcs*xaui_rx*pcs_rx_syncstatus[*]}] -to [get_registers *xaui_phy*hxaui_csr*rx*_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*sxaui_0*alt_soft_xaui_pcs*xaui_rx*channel_align_synchclk[*]}] -to [get_registers *xaui_phy*hxaui_csr*rx*_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*siv_xcvr_xaui*hxaui_csr*hxaui_csr_reset0q[1]}] -to [get_registers *sxaui_0*alt_soft_xaui_pcs*tx_reset*] \" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*siv_xcvr_xaui*hxaui_csr*hxaui_csr_reset0q[1]}] -to [get_registers *sxaui_0*alt_soft_xaui_pcs*rx_reset*] \" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*sxaui_0*alt_soft_xaui_pcs*xaui_rx*rd_ptr_latched_del[*]}] -to [get_registers *sxaui_0*alt_soft_xaui_pcs*xaui_rx*rd_ptr_wr[*]]\""} *)
+ sxaui #(
+ .starting_channel_number (starting_channel_number),
+ .xaui_pll_type (xaui_pll_type),
+ .use_control_and_status_ports (use_control_and_status_ports)
+ ) sxaui_0 (
+ .xgmii_tx_clk (xgmii_tx_clk), // xgmii_tx_clk.clk
+ .xgmii_tx_dc (xgmii_tx_dc), // xgmii_tx_dc.data
+ .xgmii_rx_clk (xgmii_rx_clk), // xgmii_rx_clk.clk
+ .xgmii_rx_dc (xgmii_rx_dc), // xgmii_rx_dc.data
+ .refclk (pll_ref_clk), // refclk.clk
+ .mgmt_clk (phy_mgmt_clk), // mgmt_clk.clk
+ .tx_out_clk (alt_pma_0_tx_out_clk_clk), // tx_out_clk.clk
+ .rx_recovered_clk (alt_pma_0_rx_recovered_clk_clk), // rx_recovered_clk.clk
+ .tx_parallel_data (sxaui_0_tx_parallel_data_data), // tx_parallel_data.data
+ .rx_parallel_data (alt_pma_0_rx_parallel_data_data), // rx_parallel_data.data
+ .rx_is_lockedtodata (alt_pma_0_rx_is_lockedtodata_data), // rx_is_lockedtodata.data
+ .rx_digitalreset (alt_pma_ch_controller_0_rx_digital_rst_data[0] ), // rx_digitalreset from cahnnel controller in alt_pma
+ .tx_digitalreset (alt_pma_ch_controller_0_tx_digital_rst_data[0] ), // tx_digitalreset from cahnnel controller in alt_pma
+ .pll_locked (pll_locked_data), // pll_locked.data
+ .rx_syncstatus (rx_syncstatus_data), // rx_syncstatus.data
+ .rx_channelaligned (rx_channelaligned), // rx_channelaligned.data
+ .rx_disperr (rx_disperr_data), // rx_disperr.data
+ .rx_errdetect (rx_errdetect_data), // rx_errdetect.data
+ .r_rx_digitalreset (hxaui_csr_r_rx_digitalreset_data), // r_rx_digitalreset.data
+ .r_tx_digitalreset (hxaui_csr_r_tx_digitalreset_data), // r_tx_digitalreset.data
+ .pma_stat_rst_done (sxaui_rst_done), // soft reset done
+ .simulation_flag (hxaui_csr_simulation_flag_data) // simulation_flag.data
+ );
+ assign rx_patterndetect_data = 8'b0; // not supported by soft PCS
+ assign rx_runningdisp_data = 8'b0; // not supported by soft PCS
+ assign rx_phase_comp_fifo_error_data = 4'b0; // not supported by soft PCS
+ assign rx_rlv_data = 4'b0; // not supported by soft PCS
+ assign rx_rmfifodatadeleted_data = 8'b0; // not supported by soft PCS
+ assign rx_rmfifodatainserted_data = 8'b0; // not supported by soft PCS
+ assign rx_rmfifoempty_data = 4'b0; // not supported by soft PCS
+ assign rx_rmfifofull_data = 4'b0; // not supported by soft PCS
+ assign tx_phase_comp_fifo_error_data = 4'b0; // not supported by soft PCS
+ assign hxaui_csr_r_rx_invpolarity_data = 4'b0; // not supported by soft PCS
+ assign hxaui_csr_r_tx_invpolarity_data = 4'b0; // not supported by soft PCS
+ assign rx_is_lockedtodata_data = 4'b0; // not supported by soft PCS
+ assign rx_is_lockedtoref_data = 4'b0; // not supported by soft PCS
+ end
+ // don't instantiate anything if the interface type is invalid
+ endgenerate
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/aldec_files.txt b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/aldec_files.txt
new file mode 100644
index 0000000000000000000000000000000000000000..96175539fe10e847160e3bb13c7980081beae5b3
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/aldec_files.txt
@@ -0,0 +1,34 @@
+./altera_xcvr_functions.sv
+./altera_xcvr_xaui.sv
+./hxaui_csr_h.sv
+./hxaui_csr.sv
+./alt_xcvr_mgmt2dec_phyreconfig.sv
+./alt_xcvr_mgmt2dec_xaui.sv
+./alt_pma_ch_controller_tgx.v
+./alt_pma_controller_tgx.v
+./alt_reset_ctrl_lego.sv
+./alt_reset_ctrl_tgx_cdrauto.sv
+./alt_xcvr_resync.sv
+./alt_xcvr_csr_common_h.sv
+./alt_xcvr_csr_common.sv
+./alt_xcvr_csr_pcs8g_h.sv
+./alt_xcvr_csr_pcs8g.sv
+./alt_xcvr_csr_selector.sv
+./alt_xcvr_mgmt2dec.sv
+./altera_wait_generate.v
+./hxaui_alt4gxb.v
+./hxaui.v
+./siv_xcvr_xaui.sv
+./alt_xcvr_reconfig_h.sv
+./alt_xcvr_reconfig_siv.sv
+./alt_xcvr_reconfig_analog.sv
+./alt_xcvr_reconfig_analog_tgx.v
+./alt_xcvr_reconfig_offset_cancellation.sv
+./alt_xcvr_reconfig_offset_cancellation_tgx.v
+./alt_xcvr_reconfig_eyemon_tgx.sv
+./alt_xcvr_reconfig_dfe_tgx.sv
+./alt_xcvr_reconfig_basic_tgx.v
+./alt_mutex_acq.v
+./alt_dprio.v
+./alt_xcvr_arbiter.sv
+./alt_xcvr_m2s.sv
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_dprio.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_dprio.v
new file mode 100644
index 0000000000000000000000000000000000000000..c8cb550d6c519e9fddf949f789fe95544e45690e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_dprio.v
@@ -0,0 +1,199 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"{-to addr_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to wr_out_data_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to rd_out_data_shift_reg[13]} DPRIO_INTERFACE_REG=ON;{-to in_data_shift_reg[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[1]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[2]} DPRIO_INTERFACE_REG=ON"} *)
+module alt_dprio (
+ input wire [15:0] address,
+ output wire busy,
+ input wire [15:0] datain,
+ output wire [15:0] dataout,
+ input wire dpclk,
+ output wire dpriodisable,
+ output wire dprioin,
+ output wire dprioload,
+ input wire dprioout,
+ input wire [6:0] quad_address,
+ input wire rden,
+ input wire wren,
+ input wire wren_data
+ );
+
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [31:0] addr_shift_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [15:0] in_data_shift_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [15:0] rd_out_data_shift_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [2:0] startup_cntr;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg [2:0] state_mc_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [31:0] wr_out_data_shift_reg;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg [5:0] state_mc_counter_q;
+
+ wire pre_amble_cmpr_agb;
+ wire [7:0] state_mc_decode_eq;
+ wire dprioin_mux_dataout;
+ wire busy_state;
+ wire idle_state;
+ wire rd_addr_done;
+ wire rd_addr_state;
+ wire rd_data_done;
+ wire rd_data_input_state;
+ wire rd_data_output_state;
+ wire rd_data_state;
+ wire rdinc;
+ wire read_state;
+ wire s0_to_0;
+ wire s0_to_1;
+ wire s1_to_0;
+ wire s1_to_1;
+ wire s2_to_0;
+ wire s2_to_1;
+ wire startup_done;
+ wire startup_idle;
+ wire wr_addr_done;
+ wire wr_addr_state;
+ wire wr_data_done;
+ wire wr_data_state;
+ wire write_state;
+ wire [2:0] startup_cntr_d;
+ wire [2:0] startup_cntr_ena;
+
+ // synopsys translate_off
+ initial
+ begin
+ addr_shift_reg = 0;
+ in_data_shift_reg = 0;
+ rd_out_data_shift_reg = 0;
+ startup_cntr[2:0] = 3'b0;
+ state_mc_reg = 0;
+ wr_out_data_shift_reg = 0;
+ state_mc_counter_q = 6'b0;
+ end
+ // synopsys translate_on
+
+ always @ (posedge dpclk)
+ begin
+ if (state_mc_counter_q == 6'b011111)
+ begin
+ addr_shift_reg <= {{2{{2{1'b0}}}}, {3{1'b0}}, quad_address, 2'b10, address};
+ rd_out_data_shift_reg <= {{2{1'b0}}, {2{1'b1}}, {3{1'b0}}, quad_address, 2'b10};
+ wr_out_data_shift_reg <= {{2{1'b0}}, 2'b01, {3{1'b0}}, quad_address, 2'b10, datain};
+ end
+ else begin
+ addr_shift_reg <= {addr_shift_reg[30:0], 1'b0};
+ rd_out_data_shift_reg <= {rd_out_data_shift_reg[14:0], 1'b0};
+ wr_out_data_shift_reg <= {wr_out_data_shift_reg[30:0], 1'b0};
+ end
+
+ if (rd_data_input_state == 1'b1)
+ in_data_shift_reg <= {in_data_shift_reg[14:0], dprioout};
+ end
+
+ always @ (posedge dpclk)
+ begin
+ if (startup_cntr_ena[0] == 1'b1)
+ startup_cntr[0] <= startup_cntr_d[0];
+ if (startup_cntr_ena[1:1] == 1'b1)
+ startup_cntr[1] <= startup_cntr_d[1];
+ if (startup_cntr_ena[2:2] == 1'b1)
+ startup_cntr[2] <= startup_cntr_d[2];
+ end
+
+ assign startup_cntr_d = {(startup_cntr[2] ^ (startup_cntr[1] & startup_cntr[0])), (startup_cntr[0] ^ startup_cntr[1]), (~ startup_cntr[0])};
+ assign startup_cntr_ena = {3{((((rden | wren) | rdinc) | (~ startup_idle)) & (~ startup_done))}};
+
+ always @ ( posedge dpclk)
+ begin
+ state_mc_reg <= {(s2_to_1 | (((~ s2_to_0) & (~ s2_to_1)) & state_mc_reg[2])), (s1_to_1 | (((~ s1_to_0) & (~ s1_to_1)) & state_mc_reg[1])), (s0_to_1 | (((~ s0_to_0) & (~ s0_to_1)) & state_mc_reg[0]))};
+ end
+
+ always @(posedge dpclk)
+ begin
+ if (write_state | read_state)
+ begin
+ if (state_mc_counter_q == 6'b111111)
+ state_mc_counter_q <= 6'b0;
+ else
+ state_mc_counter_q <= state_mc_counter_q[5:0] + 6'b1;
+ end
+ end
+
+ lpm_decode #(
+ .lpm_decodes (8),
+ .lpm_width (3),
+ .lpm_type ("lpm_decode"))
+ state_mc_decode(
+ .data(state_mc_reg),
+ .eq(state_mc_decode_eq)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .clken(1'b1),
+ .clock(1'b0),
+ .enable(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+
+ or(dprioin_mux_dataout, ((((((wr_addr_state | rd_addr_state) & addr_shift_reg[31]) & pre_amble_cmpr_agb) | ((~ pre_amble_cmpr_agb) & (wr_addr_state | rd_addr_state))) | (((wr_data_state & wr_out_data_shift_reg[31]) & pre_amble_cmpr_agb) | ((~ pre_amble_cmpr_agb) & wr_data_state))) | (((rd_data_output_state & rd_out_data_shift_reg[15]) & pre_amble_cmpr_agb) | ((~ pre_amble_cmpr_agb) & rd_data_output_state))), ~(((write_state | rd_addr_state) | rd_data_output_state)));
+
+ assign
+ pre_amble_cmpr_agb = (state_mc_counter_q > 6'b011111),
+ busy = busy_state,
+ busy_state = (write_state | read_state),
+ dataout = in_data_shift_reg,
+ dpriodisable = (~ (startup_cntr[2] & (startup_cntr[0] | startup_cntr[1]))),
+ dprioin = dprioin_mux_dataout,
+ dprioload = (~ ((startup_cntr[0] ^ startup_cntr[1]) & (~ startup_cntr[2]))),
+ idle_state = state_mc_decode_eq[0],
+
+ rd_addr_done = (rd_addr_state & (state_mc_counter_q == 6'b111111)),
+
+ rd_addr_state = (state_mc_decode_eq[5] & startup_done),
+ rd_data_done = (rd_data_state & (state_mc_counter_q == 6'b111111)),
+
+ rd_data_input_state = ((state_mc_counter_q >= 6'b110000) & rd_data_state),
+
+ rd_data_output_state = (state_mc_counter_q < 6'b110000 & rd_data_state),
+ rd_data_state = (state_mc_decode_eq[7] & startup_done),
+ rdinc = 1'b0,
+ read_state = (rd_addr_state | rd_data_state),
+ s0_to_0 = ((wr_data_state & wr_data_done) | (rd_data_state & rd_data_done)),
+ s0_to_1 = (((idle_state & (wren | ((~ wren) & ((rden | rdinc) | wren_data)))) | (wr_addr_state & wr_addr_done)) | (rd_addr_state & rd_addr_done)),
+ s1_to_0 = (((wr_data_state & wr_data_done) | (rd_data_state & rd_data_done)) | (idle_state & (wren | (((~ wren) & (~ wren_data)) & rden)))),
+ s1_to_1 = (((idle_state & ((~ wren) & (rdinc | wren_data))) | (wr_addr_state & wr_addr_done)) | (rd_addr_state & rd_addr_done)),
+ s2_to_0 = ((((wr_addr_state & wr_addr_done) | (wr_data_state & wr_data_done)) | (rd_data_state & rd_data_done)) | (idle_state & (wren | wren_data))),
+ s2_to_1 = ((idle_state & (((~ wren) & (~ wren_data)) & (rdinc | rden))) | (rd_addr_state & rd_addr_done)),
+ startup_done = ((startup_cntr[2] & (~ startup_cntr[0])) & startup_cntr[1]),
+ startup_idle = ((~ startup_cntr[0]) & (~ (startup_cntr[2] ^ startup_cntr[1]))),
+
+ wr_addr_done = (wr_addr_state & (state_mc_counter_q == 6'b111111)),
+
+ wr_addr_state = (state_mc_decode_eq[1] & startup_done),
+
+ wr_data_done = (wr_data_state & (state_mc_counter_q == 6'b111111)),
+
+ wr_data_state = (state_mc_decode_eq[3] & startup_done),
+ write_state = (wr_addr_state | wr_data_state);
+endmodule //alt_dprio
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_mutex_acq.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_mutex_acq.v
new file mode 100644
index 0000000000000000000000000000000000000000..c5d020f703904fbb94916ef75bd1fda144424ba9
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_mutex_acq.v
@@ -0,0 +1,221 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_mutex_acq #(
+ parameter mutex_wait_time = 101,
+ parameter mutex_wait_time_cntr_width = 7, // do we need this parameter?
+ parameter addr_width = 5,
+ parameter data_width = 32,
+ parameter read_mutex_addr_offset = 0 // address of the mutex word
+)
+(
+
+input wire clk, // this will be the reconfig clk
+input wire reset,
+
+// Internal interface for the bigger controlling module, like analog reconfig
+input wire [addr_width-1:0] address, // MM address
+input wire [data_width-1:0] writedata,
+input wire write,
+input wire read,
+output reg waitrequest, // can use to tell internal master to wait when auto-request+release
+output wire [data_width-1:0] readdata,
+
+
+// MM master external interface, that connects to mutex-slave, like the reconfig_basic block
+output wire [addr_width-1:0] master_address, // MM address
+output wire [data_width-1:0] master_writedata,
+output wire master_write,
+output wire master_read,
+input wire master_waitrequest, // needed for a valid master interface
+input wire [data_width-1:0] master_readdata, // from mutex-slave
+
+
+
+// request mutex access and should be held high as long as mutex is used
+input wire mutex_req,
+// output indicating whether mutex access was granted or not
+output reg mutex_grant
+
+);
+
+
+
+localparam IDLE = 2'b00;
+localparam GET_MUTEX = 2'b01;
+localparam RELEASE_MUTEX = 2'b10;
+
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [9:0] mutex_timeout_cntr;
+
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *) // should we make this variable
+reg [mutex_wait_time_cntr_width-1:0] mutex_wait_cntr;
+
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [addr_width-1:0] mutex_int_address; // MM address
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [data_width-1:0] mutex_int_writedata;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg mutex_int_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg mutex_int_read;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg do_base_readwrite;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
+reg mutex_mux_ctrl;
+
+// synopsys translate_off
+initial
+begin
+ mutex_grant = 0;
+ mutex_mux_ctrl = 1'b1;
+ mutex_timeout_cntr = 0;
+ mutex_wait_cntr = 0;
+ mutex_int_address = 0;
+ mutex_int_writedata = 0;
+ mutex_int_read = 0;
+ mutex_int_write = 0;
+ waitrequest = 0;
+ do_base_readwrite = 0;
+ state = 0;
+end
+// synopsys translate_on
+
+always @(posedge clk or posedge reset)
+begin
+ if (reset === 1'b1)
+ begin
+ mutex_grant <= 0;
+ mutex_mux_ctrl <= 1'b1;
+ mutex_timeout_cntr <= 0;
+ mutex_wait_cntr <= 0;
+ mutex_int_address <= 'b0;
+ mutex_int_writedata <= 'b0;
+ mutex_int_read <= 'b0;
+ mutex_int_write <= 'b0;
+ waitrequest <= 'b0;
+ do_base_readwrite <= 'b0;
+ state <= 'b0;
+ end
+ else begin
+ case (state)
+ IDLE:begin
+// fix SPR:343567 - Avalon slaves are permitted to keep waitrequest asserted during idle cycles.
+// The state machine will still work correctly by simply removing this condition.
+// The next state is GET_MUTEX, and it will wait there if waitrequest is legitimately asserted.
+// if (master_waitrequest == 1'b1)
+// state <= IDLE; // wait till the waitrequest goes low
+// else if (mutex_grant == 0 &&
+ if (mutex_grant == 0 &&
+ (mutex_req == 1'b1 || write == 1'b1 || read == 1'b1))
+ begin
+ state <= GET_MUTEX;
+ mutex_int_read <= 1'b1;
+ mutex_int_address <= read_mutex_addr_offset;
+ mutex_int_write <= 1'b0;
+ mutex_wait_cntr <= 0;
+ mutex_mux_ctrl <= 1'b1;
+ waitrequest <= 1'b1; // pull the waitrequest high
+ if (write == 1'b1 || read == 1'b1)
+ do_base_readwrite <= 1'b1;
+ else
+ do_base_readwrite <= 1'b0;
+ end
+ else if (mutex_grant == 1'b1)
+ begin
+ do_base_readwrite <= 1'b0;
+ if (mutex_req == 1'b1 || write == 1'b1 || read == 1'b1)
+ begin
+ mutex_mux_ctrl <= 1'b0; // relinquish control of the mux
+ if (write == 1'b1 || read == 1'b1)
+ waitrequest <= master_waitrequest;
+ else
+ waitrequest <= 1'b0;
+ if (read == 1'b1 || write == 1'b1)
+ mutex_timeout_cntr <= 0;
+ else if (mutex_timeout_cntr == 10'd1000)
+ state <= RELEASE_MUTEX;
+ else
+ mutex_timeout_cntr <= mutex_timeout_cntr[9:0] + 10'b1;
+ end
+ else
+ state <= RELEASE_MUTEX;
+ end
+ else
+ begin
+ mutex_mux_ctrl <= 1'b1; // choke the inputs going to basic as mux is not available
+ mutex_int_read <= 1'b0;
+ mutex_int_write <= 1'b0;
+ waitrequest <= 1'b0;
+ end
+ end
+ RELEASE_MUTEX: begin
+ // release the mutex
+ mutex_mux_ctrl <= 1'b1;
+ mutex_int_read <= 1'b0;
+ mutex_int_write <= 1'b1;
+ mutex_int_address <= read_mutex_addr_offset;
+ mutex_int_writedata <= 16'b0;
+ mutex_grant <= 1'b0;
+ state <= IDLE;
+ mutex_timeout_cntr <= 0;
+ waitrequest <= 1'b0;
+ end
+ GET_MUTEX: begin
+ if (master_waitrequest == 1'b1) // wait in this state itself
+ begin
+ state <= GET_MUTEX;
+ end
+ else if (mutex_int_read == 1'b1 && master_readdata[0] == 1'b0) // check mutex bit
+ begin
+ mutex_grant <= 1; // mutex is available
+ state <= IDLE;
+ mutex_int_read <= 1'b0; // reset the read and mux ctrl bits
+ mutex_mux_ctrl <= 0;
+ if (do_base_readwrite == 1'b1)
+ waitrequest <= master_waitrequest;
+ else
+ waitrequest <= 1'b0;
+ end
+ else if (mutex_wait_cntr != mutex_wait_time)
+ begin // continue waiting till the wait time is hit
+ mutex_wait_cntr <= mutex_wait_cntr[mutex_wait_time_cntr_width-1:0] + 1;
+ mutex_int_read <= 1'b0; // pull down the read
+ state <= GET_MUTEX;
+ end
+ else // try and read again
+ begin
+ mutex_wait_cntr <= 0; // reset the wait cntr and try and read again
+ mutex_int_read <= 1'b1;
+ state <= GET_MUTEX;
+ end
+ end
+ default: begin
+ state <= IDLE;
+ end
+ endcase
+ end
+
+end
+
+
+assign master_address = mutex_mux_ctrl ? mutex_int_address : address;
+assign master_writedata = mutex_mux_ctrl ? mutex_int_writedata : writedata;
+assign master_write = mutex_mux_ctrl ? mutex_int_write : write;
+assign master_read = mutex_mux_ctrl ? mutex_int_read : read;
+assign readdata = master_readdata; // pipe the readdata out
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_pma_ch_controller_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_pma_ch_controller_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..6347c1ae0190510fae1e3cec2d4c58e3c11c0d34
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_pma_ch_controller_tgx.v
@@ -0,0 +1,164 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ns/10ps
+module alt_pma_ch_controller_tgx #(
+ parameter
+ number_of_channels = 4,
+ sys_clk_in_mhz = 50, // used to calculate internal delays in terms of system clock cycles
+ manual_reset = "false",
+ sync_depth =2
+ )
+ (
+ //controller standard interface to user
+ input tri0 rst, // controller logic reset
+// input wire powerdown_all, // save power
+ input tri0 rx_rst_digital, // tx_digitalreset
+ input tri0 tx_rst_digital, // rx_digitalreset
+ output wire tx_pma_ready, // pma tx pll_locked
+ output wire rx_pma_ready, // pma rx pll is locked to data
+ input tri0 tx_cal_busy, // tx calibration in progress
+ input tri0 rx_cal_busy, // rx calibration in progress
+ input tri1 pll_locked, // tx pll_locked
+
+ // user data (avalon-MM formatted)
+ input wire clk,
+ input tri0 [5:0] ch_mgmt_address,
+ input tri1 ch_mgmt_read,
+ output wire [31:0] ch_mgmt_readdata,
+ input tri0 ch_mgmt_write,
+ input tri0 [31:0] ch_mgmt_writedata,
+ output wire ch_mgmt_waitrequest,
+
+ input tri1 [number_of_channels-1:0] rx_is_lockedtodata,
+ input tri1 [number_of_channels-1:0] rx_is_lockedtoref,
+
+ output wire [number_of_channels-1:0] rx_set_locktodata,
+ output wire [number_of_channels-1:0] rx_set_locktoref,
+ output wire [number_of_channels-1:0] rx_seriallpbken,
+
+ output wire [number_of_channels-1:0] rx_analog_rst,
+ output wire [number_of_channels-1:0] tx_digital_rst,
+ output wire [number_of_channels-1:0] rx_digital_rst,
+ output wire pll_powerdown
+);
+ // reset controller outputs
+ wire reset_controller_tx_ready;
+ wire reset_controller_rx_ready;
+ wire reset_controller_pll_powerdown;
+ wire reset_controller_tx_digitalreset;
+ wire reset_controller_rx_analogreset;
+ wire reset_controller_rx_digitalreset;
+ wire reset_controller_manual_mode;
+
+ // Control & status register map (CSR) outputs
+ wire csr_reset_tx_digital; // to reset controller
+ wire csr_reset_rx_digital; // to reset controller
+ wire csr_reset_all; // to reset controller
+ wire csr_pll_powerdown;
+ wire [number_of_channels - 1 : 0] csr_tx_digitalreset; // to xcvr instance
+ wire [number_of_channels - 1 : 0] csr_rx_analogreset; // to xcvr instance
+ wire [number_of_channels - 1 : 0] csr_rx_digitalreset; // to xcvr instance
+ wire [number_of_channels - 1 : 0] csr_phy_loopback_serial; // to xcvr instance
+ wire [number_of_channels - 1 : 0] csr_rx_set_locktoref; // to xcvr instance
+ wire [number_of_channels - 1 : 0] csr_rx_set_locktodata; // to xcvr instance
+
+
+ ///////////////////////////////////////////////////////////////////
+
+ // Implement waitrequest to match previous implementation
+ altera_wait_generate wait_gen(
+ .rst(rst),
+ .clk(clk),
+ .launch_signal(ch_mgmt_read),
+ .wait_req(ch_mgmt_waitrequest)
+ );
+ // Instantiate memory map logic for given number of lanes & PLL's
+ // Includes all except PCS
+ alt_xcvr_csr_common #(
+ .lanes(number_of_channels),
+ .plls(1)
+ ) csr (
+ .clk(clk),
+ .reset(rst),
+ .address(8'h40 | ch_mgmt_address), // map word 0 of this module to word 64 of alt_xcvr_csr_common
+ .read(ch_mgmt_read),
+ .write(ch_mgmt_write),
+ .writedata(ch_mgmt_writedata),
+ .pll_locked(pll_locked),
+ .rx_is_lockedtoref(rx_is_lockedtoref),
+ .rx_is_lockedtodata(rx_is_lockedtodata),
+ .rx_signaldetect({number_of_channels{1'b0}}),
+ .reset_controller_tx_ready(reset_controller_tx_ready),
+ .reset_controller_rx_ready(reset_controller_rx_ready),
+ .reset_controller_pll_powerdown(reset_controller_pll_powerdown),
+ .reset_controller_tx_digitalreset(reset_controller_tx_digitalreset),
+ .reset_controller_rx_analogreset(reset_controller_rx_analogreset),
+ .reset_controller_rx_digitalreset(reset_controller_rx_digitalreset),
+ .readdata(ch_mgmt_readdata),
+ .csr_reset_tx_digital(csr_reset_tx_digital),
+ .csr_reset_rx_digital(csr_reset_rx_digital),
+ .csr_reset_all(csr_reset_all),
+ .csr_pll_powerdown(csr_pll_powerdown),
+ .csr_tx_digitalreset(csr_tx_digitalreset),
+ .csr_rx_analogreset(csr_rx_analogreset),
+ .csr_rx_digitalreset(csr_rx_digitalreset),
+ .csr_phy_loopback_serial(csr_phy_loopback_serial),
+ .csr_rx_set_locktoref(csr_rx_set_locktoref),
+ .csr_rx_set_locktodata(csr_rx_set_locktodata)
+ );
+
+
+ // Instantiate reset controller for PMA channels
+ alt_reset_ctrl_tgx_cdrauto #(
+ .sys_clk_in_mhz(sys_clk_in_mhz)
+ ) rc (
+ .clock(clk),
+ .reset_all(csr_reset_all),
+ .reset_tx_digital(csr_reset_tx_digital | tx_rst_digital),
+ .reset_rx_digital(csr_reset_rx_digital | rx_rst_digital),
+ .powerdown_all(rst),
+ .tx_ready(reset_controller_tx_ready),
+ .rx_ready(reset_controller_rx_ready),
+ .pll_powerdown (reset_controller_pll_powerdown),
+ .tx_digitalreset(reset_controller_tx_digitalreset),
+ .rx_analogreset(reset_controller_rx_analogreset),
+ .rx_digitalreset(reset_controller_rx_digitalreset),
+ .gxb_powerdown(),
+ .pll_is_locked(pll_locked),
+ .tx_cal_busy(tx_cal_busy),
+ .rx_cal_busy(rx_cal_busy),
+ .rx_is_lockedtodata(&rx_is_lockedtodata),
+ .manual_mode(reset_controller_manual_mode)
+ );
+
+ // Assign outputs from reset controller
+ assign tx_pma_ready = reset_controller_tx_ready;
+ assign rx_pma_ready = reset_controller_rx_ready;
+
+ // Assign outputs from CSR to channel control bits
+ assign rx_set_locktodata = csr_rx_set_locktodata;
+ assign rx_set_locktoref = csr_rx_set_locktoref;
+ assign rx_seriallpbken = csr_phy_loopback_serial;
+
+ assign rx_analog_rst = csr_rx_analogreset;
+ assign tx_digital_rst = csr_tx_digitalreset;
+ assign rx_digital_rst = csr_rx_digitalreset;
+
+ assign reset_controller_manual_mode = (manual_reset == "true") ? 1'b1
+ : (csr_rx_set_locktoref || csr_rx_set_locktodata);
+
+ assign pll_powerdown = csr_pll_powerdown;
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_pma_controller_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_pma_controller_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..614ad6278ca4a3cbbfa013d414c4e6c8410c156e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_pma_controller_tgx.v
@@ -0,0 +1,198 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ns/10ps
+module alt_pma_controller_tgx #(
+ parameter number_of_plls = 1,// One controller only control the possible merged pll. If more pll is needed, user can use multiplier controller for none share plls.
+ parameter tx_pll_reset_hold_time = 0,// ignored - now calculated according to system clock
+ parameter sync_depth = 2,
+ parameter sys_clk_in_mhz = 50 // needed for 1us and 4us delay timers
+)
+(
+ input rst, // controller logic reset
+ output tx_pll_ready,
+
+ // user data (avalon-MM formatted)
+ input wire clk,
+ input wire [1:0] pma_mgmt_address,
+ input wire pma_mgmt_read,
+ output reg [31:0] pma_mgmt_readdata,
+ input wire pma_mgmt_write,
+ input wire [31:0] pma_mgmt_writedata,
+ output wire pma_mgmt_waitrequest,
+
+ // user data (avalon-clock formatted)
+ input wire cal_blk_clk,
+
+ // user data: pll control (avalon-ST formatted)
+ output wire cal_blk_pdn,//sync with cal_blk_clk
+ output wire gx_pdn,//sync with clk
+ output wire [number_of_plls-1:0] pll_pdn, //sync with clk
+ input wire [number_of_plls-1:0] pll_locked //
+);
+
+localparam clk_in_mhz =
+`ifdef QUARTUS__SIMGEN
+ 2; // simulation-only value
+`elsif ALTERA_RESERVED_QIS
+ sys_clk_in_mhz; // use real counter lengths for normal Quartus synthesis
+`else
+ 2; // simulation-only value
+`endif
+localparam t_pll_powerdown = clk_in_mhz; // 1 us minimum
+localparam t_ltd_auto = clk_in_mhz*4; // 4 us minimum
+
+wire [number_of_plls-1:0] pll_locked_sync;
+reg cal_blk_pdn_reg;
+reg read_delay;
+reg gx_pdn_reg;
+reg pll_pdn_resetall_avmm;
+wire pll_pdn_int;
+reg pll_pdn_reg;
+
+wire gx_pdn_int;
+wire gx_pdn_done;
+
+altera_wait_generate wait_gen(
+ .rst(rst),
+.clk(clk),
+.launch_signal(pma_mgmt_read),
+.wait_req(pma_mgmt_waitrequest)
+ );
+
+alt_reset_ctrl_lego
+#(
+.reset_hold_cycles (t_pll_powerdown) // reset pulse length in clock cycles
+) pll_pdn_rst
+(
+.clock(clk),
+.start(1'b1 ),
+.reset(pll_pdn_int),
+.rdone(pll_locked), // reset done signal
+.aclr(rst),
+.sdone(tx_pll_ready) // sequence done for this lego
+);
+
+alt_reset_ctrl_lego
+#(
+.reset_hold_cycles (2) // reset pulse length in clock cycles
+) gx_pdn_rst
+(
+.clock(clk),
+.start(1'b1 ),
+.reset(gx_pdn_int),
+.rdone(1'b1), // reset done signal
+.aclr(rst),
+.sdone(gx_pdn_done) // sequence done for this lego
+);
+
+assign pll_pdn= pll_pdn_reg | {number_of_plls{pll_pdn_int}} ;
+
+initial
+begin
+ pll_pdn_reg <= 0;
+end
+always @ (posedge clk, posedge rst)
+begin
+ if(rst) begin
+ pll_pdn_reg <= 1'b0;
+ end
+ else if (pma_mgmt_write==1'b1 & pma_mgmt_address==2'b00) begin
+ pll_pdn_reg <= pma_mgmt_writedata[number_of_plls -1 :0];
+ end
+end
+
+initial
+begin
+ pma_mgmt_readdata <= 0;
+end
+always @ (posedge clk, posedge rst)
+begin
+ if(rst) begin
+ pma_mgmt_readdata <= 0;
+ end
+ else if (pma_mgmt_read==1'b1 & pma_mgmt_address==2'b00) begin
+ pma_mgmt_readdata[number_of_plls -1 :0] <= pll_pdn;
+ end
+ else if (pma_mgmt_read==1'b1 & pma_mgmt_address==2'b01) begin
+ pma_mgmt_readdata[0] <= cal_blk_pdn_reg;
+ pma_mgmt_readdata[1] <= gx_pdn;
+ end
+ else if (pma_mgmt_read==1'b1 & pma_mgmt_address==2'b10) begin
+ pma_mgmt_readdata[number_of_plls -1 :0] <= pll_locked_sync;
+ end
+ else
+ pma_mgmt_readdata <= 0;
+end
+
+generate
+genvar i;
+for (i=0; i<number_of_plls; i=i+1)
+begin: lock_sync
+ altera_std_synchronizer
+ #(
+ .depth (sync_depth) // reset pulse length in clock cycles
+ )stdsync
+ (
+ .clk(clk),
+ .din(pll_locked[i]),
+ .dout(pll_locked_sync[i]),
+ .reset_n((~ rst))
+ );
+end
+endgenerate
+
+initial
+begin
+ cal_blk_pdn_reg <= 0;
+end
+always @ (posedge clk, posedge rst)
+begin
+ if(rst) begin
+ cal_blk_pdn_reg <= 0;
+ end
+ else if (pma_mgmt_write==1'b1 & pma_mgmt_address==2'b01) begin
+ cal_blk_pdn_reg <= pma_mgmt_writedata[0];
+ end
+end
+altera_std_synchronizer
+#(
+ .depth (sync_depth) // reset pulse length in clock cycles
+)stdsync
+(
+ .clk(cal_blk_clk),
+ .din(cal_blk_pdn_reg),
+ .dout(cal_blk_pdn),
+ .reset_n((~ rst))
+);
+
+assign gx_pdn = gx_pdn_reg | gx_pdn_int;
+initial
+begin
+ gx_pdn_reg <= 0;
+end
+always @ (posedge clk, posedge rst)
+begin
+ if(rst) begin
+ gx_pdn_reg <= 0;
+ end
+ else if (pma_mgmt_write==1'b1 & pma_mgmt_address==2'b01) begin
+ gx_pdn_reg <= pma_mgmt_writedata[1];
+ end
+ else begin
+ gx_pdn_reg <= gx_pdn_reg;
+ end
+
+end
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_reset_ctrl_lego.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_reset_ctrl_lego.sv
new file mode 100644
index 0000000000000000000000000000000000000000..38d99a0658aa5380a62046e68a3b66cb9158881b
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_reset_ctrl_lego.sv
@@ -0,0 +1,265 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Reset controller building block.
+//
+// Handles a single reset stage. Can be daisy-chained with other blocks for purely sequential resets.
+// Options include reset pulse length in clock cycles, and a counter for sdone stability checking.
+//
+// $Header$
+//
+
+`timescale 1 ns / 1 ns
+
+module alt_reset_ctrl_lego
+#(
+ parameter reset_hold_til_rdone = 0, // 1 means reset stays high until rdone arrives
+ // 0 means fixed pulse length, defined by reset_hold_cycles
+ parameter reset_hold_cycles = 1, // reset pulse length in clock cycles
+ parameter sdone_delay_cycles = 0, // optional delay from rdone received til sdone sent to next block
+ parameter rdone_is_edge_sensitive = 0 // default is level sensitive rdone
+)
+(
+ // clocks and PLLs
+ input wire clock,
+ input wire start,
+ input tri0 aclr, // active-high asynchronous reset
+ output wire reset,
+ input tri1 rdone, // reset done signal
+ output reg sdone // sequence done for this lego
+);
+ localparam max_precision = 32; // VCS requires this declaration outside the function
+ function integer ceil_log2;
+ input [max_precision-1:0] input_num;
+ integer i;
+ reg [max_precision-1:0] try_result;
+ begin
+ i = 0;
+ try_result = 1;
+ while ((try_result << i) < input_num && i < max_precision)
+ i = i + 1;
+ ceil_log2 = i;
+ end
+ endfunction
+
+ // How many bits are needed for 'reset_hold_cycles' counter?
+ localparam rhc_bits = ceil_log2(reset_hold_cycles);
+ localparam rhc_load_constant = (1 << rhc_bits) | (reset_hold_cycles-1);
+ // How many bits are needed for 'sdone_delay_cycles' counter?
+ localparam sdc_bits = ceil_log2(sdone_delay_cycles);
+ localparam sdc_load_constant = (1 << sdc_bits)
+ | ((rdone_is_edge_sensitive == 1 && sdone_delay_cycles > 1) ? sdone_delay_cycles-2 : sdone_delay_cycles-1);
+ localparam sdone_stable_cycles = (sdone_delay_cycles > 1 ? sdone_delay_cycles+1 : 0);
+
+ wire spulse; // synchronous detection of 'start' 0-to-1 transition
+ wire rhold;
+ wire timed_reset_in_progress;
+ wire rinit_next; // combinatorial input to rinit DFF
+ wire rdonei; // internal selector between rdone and rdsave (rdone_is_edge_sensitive==1)
+ wire rdpulse; // synchronous detection of 'rdone' 0-to-1 transition, when rdone_is_edge_sensitive==1
+
+ reg zstart = 0; // delayed value of 'start' input, used for detection of 0-to-1 transition
+ reg rinit = 0; // state bit that indicates sequence is in progress
+
+ initial begin
+ sdone = 0; // 1 indicates sequence is done
+ end
+
+
+ // 'start' input, detect 0-to-1 transition that triggers sequence
+ assign spulse = start & ~zstart;
+ always @(posedge clock or posedge aclr)
+ if (aclr == 1'b1)
+ zstart <= 0;
+ else
+ zstart <= start;
+
+ // rinit state bit, triggered by spulse, waits while rhold = 1
+ assign rinit_next = spulse | (rinit & (rhold | ~rdonei | rdpulse)) | timed_reset_in_progress;
+ always @(posedge clock or posedge aclr)
+ if (aclr == 1'b1)
+ rinit <= 0;
+ else
+ rinit <= rinit_next;
+
+ // optional internal 'rdone' generation logic, if rdone_is_edge_sensitive==1
+ generate
+ if (rdone_is_edge_sensitive == 0) begin
+ assign rdpulse = 0;
+ assign rdonei = rdone;
+ end
+ else begin
+ // instantiate synchronous edge-detection logic for rdone
+ reg zrdone = 0; // for edge-sensitive rdone, detect 0-to-1 transition synchronously
+ reg rdsave = 0; // for edge-sensitive rdone, use this as internal rdone
+ always @(posedge clock or posedge aclr) begin
+ if (aclr == 1'b1) begin
+ zrdone <= 0;
+ rdsave <= 0;
+ end
+ else begin
+ zrdone <= rdone; // previous value of rdone for synchronous edge detection
+ rdsave <= ~spulse & (rdpulse | rdsave);
+ end
+ end
+ assign rdpulse = rdone & ~zrdone;
+ assign rdonei = rdsave;
+ end
+ endgenerate
+
+ // rhold depends on sdone_delay_cycles and rdone_is_edge_sensitive
+ generate
+ if (sdone_delay_cycles == 0 || (sdone_delay_cycles == 1 && rdone_is_edge_sensitive == 1))
+ assign rhold = ~rdonei; // sdone_delay_cycles=0
+ else begin
+ // declare only when needed to avoid Quartus synthesis warnings
+ reg [sdc_bits:0] rhold_reg = 0; // for sdone_delay_cycles > 0
+ if (sdone_delay_cycles == 1) begin
+ always @(posedge clock or posedge aclr) begin
+ if (aclr == 1'b1)
+ rhold_reg <= 0;
+ else
+ rhold_reg <= ~(rinit & rdonei);
+ end
+ assign rhold = rhold_reg[0]; // sdone_delay_cycles=1
+ end
+ else begin
+ // need to count cycles to make sure rdone is stable
+ always @(posedge clock or posedge aclr)
+ begin
+ if (aclr == 1'b1)
+ rhold_reg <= 0;
+ else if ((rinit & rdonei & ~rdpulse) == 0)
+ // keep load value until rinit & rdone both high, and no new rdone pulses
+ rhold_reg <= sdc_load_constant[sdc_bits:0];
+ else
+ rhold_reg <= rhold_reg - 1'b1;
+ end
+ assign rhold = rhold_reg[sdc_bits]; // sdone_delay_cycles > 1
+ end
+ end
+ endgenerate
+
+ // sdone state bit indicates that reset sequence completed. Clear again on 'start'
+ always @(posedge clock or posedge aclr)
+ if (aclr == 1'b1)
+ sdone <= 0;
+ else
+ sdone <= ~spulse & (sdone | (rinit & ~rinit_next));
+
+ // reset pulse generation logic depends on 2 parameters
+ generate
+ if (reset_hold_til_rdone == 1) begin
+ assign reset = rinit;
+ assign timed_reset_in_progress = 0;
+ end
+ else if (reset_hold_cycles < 1) begin // 0 is legal, but catch negative (illegal) values too
+ assign reset = spulse;
+ assign timed_reset_in_progress = 0;
+ end
+ else begin
+ // declare only when needed to avoid Quartus synthesis warnings
+ reg [rhc_bits:0] zspulse = 0; // bits for reset pulse if fixed length
+ assign timed_reset_in_progress = zspulse[rhc_bits];
+ assign reset = zspulse[rhc_bits];
+
+ if (reset_hold_cycles == 1)
+ // a single-cycle reset pulse needs 1 register
+ always @(posedge clock or posedge aclr)
+ if (aclr == 1'b1)
+ zspulse <= 0;
+ else
+ zspulse <= spulse;
+ else begin
+ // multi-cycle reset pulse needs a counter
+ always @(posedge clock or posedge aclr)
+ begin
+ if (aclr == 1'b1)
+ zspulse <= 0;
+ else if (spulse == 1)
+ zspulse <= rhc_load_constant[rhc_bits:0];
+ else if (zspulse[rhc_bits] == 1)
+ zspulse <= zspulse - 1'b1;
+ end
+ end
+ end
+ endgenerate
+
+// generate
+// case (reset_hold_til_rdone)
+// 0 : m1 U1 (a, b, c);
+// 2 : m2 U1 (a, b, c);
+// default : m3 U1 (a, b, c);
+// endcase
+// endgenerate
+
+ // general assertions
+ //synopsys translate_off
+ // vlog/vcs/ncverilog: +define+ALTERA_XCVR_ASSERTIONS
+`ifdef ALTERA_XCVR_ASSERTIONS
+ // when rdone is edge sensitive, last rdone +ve edge triggers sdone +ve edge,
+ // 'sdone_delay_cycles' later. "##1 1" is an always-true cycle to match $rise(sdone)
+ sequence rdone_last_edge;
+ @(posedge clock) $rose(rdone) ##1 !$rose(rdone) [*sdone_delay_cycles] ##1 1;
+ endsequence
+
+ // when rdone is level sensitive, stable rdone for 'sdone_delay_cycles' consecutive cycles
+ // triggers sdone +ve edge. "##1 1" is an always-true cycle to match $rise(sdone)
+ sequence rdone_stable_level;
+ @(posedge clock) rdone [*(sdone_delay_cycles+1)] ##1 1;
+ endsequence
+
+// Most assertions aren't valid when 'aclr' is active
+//`define assert_awake(arg) assert property (disable iff (aclr) arg )
+ always @(aclr)
+ if (aclr) $assertkill;
+ else $asserton;
+
+ generate
+ always @(posedge clock) begin
+ // A rising edge on start will result in reset high within 1 clock cycle
+ assert property ($rose(start & ~aclr) |-> ##[0:1] reset);
+ // A rising edge on reset will result in sdone low within 1 clock cycle
+ assert property ($rose(reset) |-> ##[0:1] !sdone);
+
+ // assertions for optional behavior: reset pulse length options
+ if (reset_hold_til_rdone == 0 && reset_hold_cycles > 1)
+ // Verify fixed-length reset pulse option
+ assert property ($rose(reset) |-> reset [*reset_hold_cycles] ##1 !reset)
+ else $error("Reset pulse length should be %d", reset_hold_cycles);
+ if (reset_hold_til_rdone == 0 && reset_hold_cycles == 1)
+ // Verify fixed 1-length reset pulse option
+ assert property ($rose(reset) |=> !reset);
+ if (reset_hold_til_rdone == 0 && reset_hold_cycles == 0)
+ // Verify minimal-length reset pulse option, which mirrors 'start' edge detection
+ assert property ($rose(start & ~aclr) |-> reset ##1 !reset);
+ if (reset_hold_til_rdone == 1) begin
+ // with hold-til-rdone, reset should not deassert until after rdone asserts, then deassert immediately
+ assert property ($rose(reset) && !rdone |=> $stable(reset) [*0:$] ##1 (reset && rdone) ##1 !reset);
+ assert property ($rose(reset) && rdone ##1 rdone [*sdone_delay_cycles] |=> !reset); // rdone was already high
+ //assert property ($rose(reset) && !rdone |-> ##[0:$] rdone ##1 !reset);
+ end
+
+ // assertions for optional behavior: sdone delay options and rdone edge sensitive option
+ if (rdone_is_edge_sensitive == 1)
+ // rdone edge-sensitive option only has an effect when sdone_delay_cycles > 0
+ assert property ($rose(sdone) |-> rdone_last_edge.ended);
+ if (rdone_is_edge_sensitive == 0)
+ // rdone defaults to level-sensitive
+ assert property ($rose(sdone) |-> (rdone_stable_level.ended or $past($fell(reset),1)));
+ end
+ endgenerate
+`endif // ALTERA_XCVR_ASSERTIONS
+ //synopsys translate_on
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_reset_ctrl_tgx_cdrauto.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_reset_ctrl_tgx_cdrauto.sv
new file mode 100644
index 0000000000000000000000000000000000000000..d785de6ee8eb397584ea1833c7e8a7ddf5c3b045
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_reset_ctrl_tgx_cdrauto.sv
@@ -0,0 +1,201 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Reset controller for Stratix IV transceivers with RX CDR in auto-lock mode.
+//
+// Uses alt_reset_ctrl_lego to handle each reset stage, with 3 required for the overall sequence.
+// Parameter defaults for pll-powerdown and lock-to-data-auto timers assume 50 MHz system clock
+//
+// $Header$
+//
+
+`timescale 1 ns / 1 ns
+
+(* altera_attribute = "-name MERGE_TX_PLL_DRIVEN_BY_REGISTERS_WITH_SAME_CLEAR ON -to \"alt_reset_ctrl_lego:lego_pll_powerdown|zspulse\" " *)
+module alt_reset_ctrl_tgx_cdrauto
+#(
+ parameter sys_clk_in_mhz = 50 // needed for 1us and 4us delay timers
+)
+(
+ // User inputs and outputs
+ input wire clock,
+ input wire reset_all,
+ input tri0 reset_tx_digital,
+ input tri0 reset_rx_digital,
+ input wire powerdown_all,
+ output wire tx_ready,
+ output wire rx_ready,
+
+ // I/O to Stratix IV transceiver control & status
+ output wire pll_powerdown, // reset TX PLL
+ output wire tx_digitalreset, // reset TX PCS
+ output wire rx_analogreset, // reset RX PMA
+ output wire rx_digitalreset, // reset RX PCS
+ output wire gxb_powerdown, // powerdown whole quad
+ input wire pll_is_locked, // TX PLL is locked status
+ input tri0 tx_cal_busy, // TX channel calibration status
+ input tri0 rx_cal_busy, // RX channel calibration status
+ input tri1 rx_is_lockedtodata, // RX CDR PLL is locked to data status
+ input tri0 manual_mode // 0=Automatically reset RX after loss of rx_is_lockedtodata
+);
+
+localparam clk_in_mhz =
+`ifdef QUARTUS__SIMGEN
+ 2; // simulation-only value
+`elsif ALTERA_RESERVED_QIS
+ sys_clk_in_mhz; // use real counter lengths for normal Quartus synthesis
+`else
+ 2; // simulation-only value
+`endif
+localparam t_pll_powerdown = clk_in_mhz; // 1 us minimum
+localparam t_ltd_auto = clk_in_mhz*4; // 4 us minimum
+
+
+wire pll_is_locked_r; // pll_is_locked resynchronized
+wire tx_cal_busy_r; // tx_cal_busy resynchronized
+wire rx_cal_busy_r; // rx_cal_busy resynchronized
+wire rx_is_lockedtodata_r; // rx_is_lockedtodata resynchronized
+
+wire sdone_lego_pll_powerdown; // 'sequence done' output of pll_powerdown lego
+wire sdone_lego_tx_digitalreset;// 'sequence done' output of tx_digitalreset lego
+wire sdone_lego_rx_digitalreset;// 'sequence done' output of rx_digitalreset lego
+wire sdone_lego_rx_analogreset; // 'sequence done' output of rx_analogreset lego
+wire wire_tx_digital_only_reset;// reset output for TX digital-only
+wire wire_rx_digital_only_reset;// reset output for RX digital-only
+wire wire_tx_digitalreset; // TX digital full-reset source
+wire wire_rx_digitalreset; // RX digital full-reset source
+wire wire_rx_digital_retrigger; // Trigger new RX digital sequence after main sequence completes, and lose lock-to-data
+
+// Resynchronize input signals
+alt_xcvr_resync #(
+ .WIDTH(2)
+ ) alt_xcvr_resync_inst_0 (
+ .clk (clock),
+ .reset (1'b0),
+ .d ({pll_is_locked ,rx_is_lockedtodata }),
+ .q ({pll_is_locked_r,rx_is_lockedtodata_r})
+);
+
+alt_xcvr_resync #(
+ .WIDTH(2),
+ .INIT_VALUE(1)
+ ) alt_xcvr_resync_inst_1 (
+ .clk (clock),
+ .reset (1'b0),
+ .d ({rx_cal_busy,tx_cal_busy}),
+ .q ({rx_cal_busy_r,tx_cal_busy_r})
+);
+
+// First reset ctrl sequencer lego is for pll_powerdown generation
+alt_reset_ctrl_lego #(
+ .reset_hold_cycles(t_pll_powerdown) // hold pll_powerdown for 1us
+ ) lego_pll_powerdown ( .clock(clock),
+ .start(reset_all), // Do not use resynched version of reset_all here
+ .aclr(powerdown_all),
+ .reset(pll_powerdown),
+ .rdone(pll_is_locked_r),
+ .sdone(sdone_lego_pll_powerdown));
+
+// next reset ctrl sequencer lego is for tx_digitalreset generation
+alt_reset_ctrl_lego #(
+ .reset_hold_til_rdone(1) // hold until rdone arrives for this test case
+ ) lego_tx_digitalreset ( .clock(clock),
+ .start(reset_all),
+ .aclr(powerdown_all),
+ .reset(wire_tx_digitalreset),
+ .rdone(sdone_lego_pll_powerdown & ~tx_cal_busy_r),
+ .sdone(sdone_lego_tx_digitalreset));
+
+// next reset ctrl sequencer lego is for rx_analogreset generation
+alt_reset_ctrl_lego #(
+ .reset_hold_til_rdone(1), // hold until rdone arrives for this test case
+ .sdone_delay_cycles(2) // hold rx_analogreset 2 parallel_clock cycles after offset cancellation done
+ ) lego_rx_analogreset ( .clock(clock),
+ .start(reset_all),
+ .aclr(powerdown_all),
+ .reset(rx_analogreset),
+ .rdone(sdone_lego_tx_digitalreset & ~rx_cal_busy_r),
+ .sdone(sdone_lego_rx_analogreset));
+
+// last reset ctrl sequencer lego is for rx_digitalreset generation
+alt_reset_ctrl_lego #(
+ .reset_hold_til_rdone(1), // hold until rdone arrives for this test case
+ .sdone_delay_cycles(t_ltd_auto) // hold rx_digitalreset for 4us
+ ) lego_rx_digitalreset ( .clock(clock),
+ .start(~manual_mode & reset_all | wire_rx_digital_retrigger),
+ .aclr(powerdown_all),
+ .reset(wire_rx_digitalreset),
+ .rdone(sdone_lego_rx_analogreset & rx_is_lockedtodata_r),
+ .sdone(sdone_lego_rx_digitalreset));
+
+//////////// digital-only reset ////////////
+// separate reset ctrl sequencer lego for digital-only reset generation
+alt_reset_ctrl_lego #(
+ .reset_hold_cycles(3) // hold 2 parallel clock cycles (assumes sysclk slower or same freq as parallel clock)
+ ) lego_tx_digitalonly ( .clock(clock),
+ .start(reset_tx_digital | reset_all),
+ .aclr(powerdown_all),
+ .reset(wire_tx_digital_only_reset),
+ .rdone(sdone_lego_tx_digitalreset),
+ .sdone(tx_ready)); // TX status indicator for user
+
+alt_reset_ctrl_lego #(
+ .reset_hold_cycles(3) // hold 2 parallel clock cycles (assumes sysclk slower or same freq as parallel clock)
+ ) lego_rx_digitalonly ( .clock(clock),
+ .start(reset_rx_digital | (reset_all & ~manual_mode) | wire_rx_digital_retrigger),
+ .aclr(powerdown_all),
+ .reset(wire_rx_digital_only_reset),
+ .rdone(sdone_lego_rx_digitalreset),
+ .sdone(rx_ready)); // RX status indicator for user
+
+// digital resets have 2 possible sources: full-reset or digital-only
+assign tx_digitalreset = wire_tx_digitalreset | wire_tx_digital_only_reset;
+assign rx_digitalreset = wire_rx_digitalreset | wire_rx_digital_only_reset;
+
+// re-trigger RX digital sequence when main sequence is complete (indicated by sdone_lego_rx_digitalreset)
+// not manual mode, and lose lock-to-data
+assign wire_rx_digital_retrigger = ~manual_mode & sdone_lego_rx_digitalreset & ~rx_is_lockedtodata_r;
+
+// Quad power-down
+assign gxb_powerdown = powerdown_all;
+
+
+////////////////////////
+// general assertions
+//synopsys translate_off
+// vlog/vcs/ncverilog: +define+ALTERA_XCVR_ASSERTIONS
+`ifdef ALTERA_XCVR_ASSERTIONS
+always @(posedge clock) begin
+ // reset_all starts by triggering CMU PLL powerdown
+ assert property ($rose(reset_all) |=> $rose(pll_powerdown));
+ // While CMU PLL powerdown is asserted, all other resets must be asserted
+ assert property (pll_powerdown |-> (tx_digitalreset & rx_analogreset & rx_digitalreset));
+ // While rx_analogreset is asserted, rx_digitalreset must be asserted
+ assert property (rx_analogreset |-> rx_digitalreset);
+ // When pll_is_locked is asserted, tx_digitalreset must be deasserted
+ assert property ($rose(pll_is_locked_r) |-> ##[0:2] !tx_digitalreset);
+ // During a reset, rx_digitalreset should remain high for t_ltd_auto after rx_is_lockedtodata rising edge
+ assert property ($rose(rx_is_lockedtodata_r) & ~manual_mode|-> rx_digitalreset [*(t_ltd_auto+1)] ##1 !rx_digitalreset);
+ assert property ($rose(rx_is_lockedtodata_r) & manual_mode|->!rx_digitalreset);
+ // reset_tx_digital results in only a brief pulse on tx_digitalreset
+ assert property ($rose(reset_tx_digital) |=> tx_digitalreset [*3] );
+ assert property ($rose(reset_tx_digital) & tx_ready |=> tx_digitalreset [*3] ##1 ~tx_digitalreset ##1 $rose(tx_ready) );
+ // reset_rx_digital results in only a brief pulse on rx_digitalreset
+ assert property ($rose(reset_rx_digital) |=> rx_digitalreset [*3] );
+ assert property ($rose(reset_rx_digital) & rx_ready |=> rx_digitalreset [*3] ##1 ~rx_digitalreset ##1 $rose(rx_ready) );
+end
+`endif
+//synopsys translate_on
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_arbiter.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_arbiter.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5b0e914d4dea0be5e022a29a6df73240a4f4f29e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_arbiter.sv
@@ -0,0 +1,64 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Clocked priority encoder with state
+//
+// On each clock cycle, updates state to show which request is granted.
+// Most recent grant holder is always the highest priority.
+// If current grant holder is not making a request, while others are,
+// then new grant holder is always the requester with lowest bit number.
+// If no requests, current grant holder retains grant state
+
+// $Header$
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_arbiter #(
+ parameter width = 2
+) (
+ input wire clock,
+ input wire [width-1:0] req, // req[n] requests for this cycle
+ output reg [width-1:0] grant // grant[n] means requester n is grantee in this cycle
+);
+
+ wire idle; // idle when no requests
+ wire [width-1:0] keep; // keep[n] means requester n is requesting, and already has the grant
+ // Note: current grantee is always highest priority for next grant
+ wire [width-1:0] take; // take[n] means requester n is requesting, and there are no higher-priority requests
+
+ assign keep = req & grant; // current grantee is always highest priority for next grant
+ assign idle = ~| req; // idle when no requests
+
+ initial begin
+ grant = 0;
+ end
+
+ // grant next state depends on current grant and take priority
+ always @(posedge clock) begin
+ grant <= keep // if current grantee is requesting, gets to keep grant
+ | ({width{idle}} & grant) // if no requests, grant state remains unchanged
+ | take; // take applies only if current grantee is not requesting
+ end
+
+ // 'take' bus encodes priority. Request with lowest bit number wins when current grantee not requesting
+ assign take[0] = req[0]
+ & (~| (keep & ({width{1'b1}} << 1))); // no 'keep' from lower-priority inputs
+ genvar i;
+ generate
+ for (i=1; i < width; i = i + 1) begin : arb
+ assign take[i] = req[i]
+ & (~| (keep & ({width{1'b1}} << (i+1)))) // no 'keep' from lower-priority inputs
+ & (~| (req & {i{1'b1}})); // no 'req' from higher-priority inputs
+ end
+ endgenerate
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_csr_common.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_csr_common.sv
new file mode 100644
index 0000000000000000000000000000000000000000..dbe3e5a5fcf1db4a9ce64efc08efa2005e19cbe8
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_csr_common.sv
@@ -0,0 +1,209 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common control & status register map for transceiver PHY IP
+// Applies to Stratix V-generation basic PHY components
+//
+// $Header$
+//
+
+`timescale 1 ps / 1 ps
+
+module alt_xcvr_csr_common #(
+ parameter lanes = 1,
+ parameter plls = 1
+)
+(
+ // user data (avalon-MM formatted)
+ input wire clk,
+ input tri0 reset,
+ input wire [7:0] address,
+ input tri1 read,
+ output reg [31:0] readdata = 0,
+ input tri0 write,
+ input wire [31:0] writedata,
+
+ // transceiver status inputs to this CSR
+ input wire [plls - 1 : 0] pll_locked,
+ input wire [lanes - 1 : 0] rx_is_lockedtoref,
+ input wire [lanes - 1 : 0] rx_is_lockedtodata,
+ input wire [lanes - 1 : 0] rx_signaldetect,
+
+ // reset controller outputs
+ input wire reset_controller_tx_ready,
+ input wire reset_controller_rx_ready,
+ input wire reset_controller_pll_powerdown,
+ input wire reset_controller_tx_digitalreset,
+ input wire reset_controller_rx_analogreset,
+ input wire reset_controller_rx_digitalreset,
+
+ // read/write control registers
+ // to reset controller
+ output reg csr_reset_tx_digital = 0,
+ output reg csr_reset_rx_digital = 0,
+ output reg csr_reset_all = 1, // power-up to 1 to trigger auto-init sequence
+ // to PMA and PCS reset inputs
+ output wire csr_pll_powerdown, // reset controller or manual
+ output wire [lanes - 1 : 0] csr_tx_digitalreset, // reset controller or manual
+ output wire [lanes - 1 : 0] csr_rx_analogreset, // reset controller or manual
+ output wire [lanes - 1 : 0] csr_rx_digitalreset, // reset controller or manual
+ // common PMA controls
+ output reg [lanes - 1 : 0] csr_phy_loopback_serial = 0,
+ output reg [lanes - 1 : 0] csr_rx_set_locktoref = 0,
+ output reg [lanes - 1 : 0] csr_rx_set_locktodata = 0
+);
+ import alt_xcvr_csr_common_h::*;
+
+ localparam sync_stages = 2; // number of sync stages for transceiver status signals
+ localparam sync_stages_str = "2"; // number of sync stages specified as string (for timing constraints)
+ integer stage;
+
+ // Parameter strings for embedded timing constraints
+ localparam CSR_PLLLOCKED_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_common*csr_pll_locked*[",sync_stages_str,"]*]\""};
+ localparam CSR_RXISLOCKED_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_common*csr_rx_is_locked*[",sync_stages_str,"]*]\""};
+ localparam CSR_RXSIGNALDET_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_common*csr_rx_signaldetect*[",sync_stages_str,"]*]\""};
+ localparam SDC_CONSTRAINTS = {CSR_PLLLOCKED_CONSTRAINT,";",CSR_RXISLOCKED_CONSTRAINT,";",CSR_RXSIGNALDET_CONSTRAINT};
+
+ // internal control registers
+ reg [lanes - 1 : 0] csr_interrupt_ch_bitmask = {lanes{1'b1}};
+ // fine reset control. 'OR' with reset controller equivalent signals
+ reg csr_reset_or_pll_powerdown = 0; // fine reset control
+ reg csr_reset_or_reset_tx_digital = 0; // fine reset control
+ reg csr_reset_or_reset_rx_analog = 0; // fine reset control
+ reg csr_reset_or_reset_rx_digital = 0; // fine reset control
+ reg [lanes - 1 : 0] csr_reset_ch_bitmask = {lanes{1'b1}};
+
+ // read-only status registers
+ // These are synchronized forms of transceiver status signals
+ // async inputs go to reg [sync_stages], and come out synchronized at reg [1]
+ (* altera_attribute = SDC_CONSTRAINTS *) // Apply timing constraints (does not matter which node)
+ reg [plls - 1 : 0] csr_pll_locked [sync_stages:1];
+ reg [lanes - 1 : 0] csr_rx_is_lockedtoref [sync_stages:1];
+ reg [lanes - 1 : 0] csr_rx_is_lockedtodata [sync_stages:1];
+ reg [lanes - 1 : 0] csr_rx_signaldetect [sync_stages:1];
+
+ always @(posedge clk or posedge reset) begin
+ if (reset == 1) begin
+ readdata <= 0;
+ csr_interrupt_ch_bitmask <= {lanes{1'b1}};
+
+ csr_reset_tx_digital <= 0;
+ csr_reset_rx_digital <= 0;
+ csr_reset_all <= 1; // reset to 1 to trigger auto-init sequence
+ csr_reset_ch_bitmask <= {lanes{1'b1}};
+ csr_reset_or_pll_powerdown <= 0; // fine reset control
+ csr_reset_or_reset_tx_digital <= 0; // fine reset control
+ csr_reset_or_reset_rx_analog <= 0; // fine reset control
+ csr_reset_or_reset_rx_digital <= 0; // fine reset control
+
+ csr_phy_loopback_serial <= 0;
+ csr_rx_set_locktoref <= 0;
+ csr_rx_set_locktodata <= 0;
+ end
+ else begin
+ // decode read & write for each supported address
+ case (address)
+ // interrupt control
+ ADDR_INTERRUPT_CH_BITMASK: begin
+ readdata <= (32'd0 | csr_interrupt_ch_bitmask);
+ if (write) csr_interrupt_ch_bitmask <= writedata[lanes-1:0];
+ end
+
+ // reset control
+ ADDR_RESET_CONTROL: begin
+ // on read, returns two bits: bit0: TX ready, bit1: RX ready
+ readdata <= (32'd0 | {reset_controller_rx_ready, reset_controller_tx_ready});
+ // on write, bit0 is 'reset_tx_digital', bit1 is 'reset_rx_digital', bit2 is 'reset_all'
+ //if (write) begin
+ // reset_all write side-effect: when write a '1', force all reset_ch_bitmask bits to '1'
+ // csr_reset_ch_bitmask <= csr_reset_ch_bitmask | {(lanes){writedata[2]}};
+ //end
+ end
+ ADDR_RESET_CH_BITMASK: begin
+ readdata <= (32'd0 | csr_reset_ch_bitmask);
+ if (write) csr_reset_ch_bitmask <= writedata[lanes-1:0];
+ end
+
+ // loopback control
+ ADDR_PHY_LOOPBACK_SERIAL,
+ ADDR_PMA_LOOPBACK_SERIAL: begin
+ readdata <= (32'd0 | csr_phy_loopback_serial);
+ if (write) csr_phy_loopback_serial <= writedata[lanes-1:0];
+ end
+
+ // PMA control and status
+ ADDR_PMA_RX_SET_LOCKTOREF: begin
+ readdata <= (32'd0 | csr_rx_set_locktoref);
+ if (write) csr_rx_set_locktoref <= writedata[lanes-1:0];
+ end
+ ADDR_PMA_RX_SET_LOCKTODATA: begin
+ readdata <= (32'd0 | csr_rx_set_locktodata);
+ if (write) csr_rx_set_locktodata <= writedata[lanes-1:0];
+ end
+ // PMA status (read-only)
+ ADDR_PMA_PLL_IS_LOCKED: readdata <= (32'd0 | csr_pll_locked[1]);
+ ADDR_PMA_RX_IS_LOCKEDTOREF: readdata <= (32'd0 | csr_rx_is_lockedtoref[1]);
+ ADDR_PMA_RX_IS_LOCKEDTODATA: readdata <= (32'd0 | csr_rx_is_lockedtodata[1]);
+ ADDR_PMA_RX_SIGNALDETECT: readdata <= (32'd0 | csr_rx_signaldetect[1]);
+
+ // Fine reset control - device dependent
+ ADDR_RESET_FINE_CONTROL: begin
+ // bit 0: 'pll_powerdown', 1: 'reset_tx_digital', 2: 'reset_rx_analog', 3: 'reset_rx_digital'
+
+ readdata <= (32'd0 | {csr_reset_or_reset_rx_digital, csr_reset_or_reset_rx_analog,
+ csr_reset_or_reset_tx_digital, csr_reset_or_pll_powerdown});
+ if (write) begin
+ csr_reset_or_pll_powerdown <= writedata[0]; // fine reset control
+ csr_reset_or_reset_tx_digital <= writedata[1]; // fine reset control
+ csr_reset_or_reset_rx_analog <= writedata[2]; // fine reset control
+ csr_reset_or_reset_rx_digital <= writedata[3]; // fine reset control
+ end
+ end
+
+
+ default: readdata <= ~ 32'd0; // use too many LEs?
+ endcase
+
+ // special handling for registers that must auto-clear on cycle after a write
+ // reset control. on write, bit0 is 'reset_tx_digital', bit1 is 'reset_rx_digital', bit2 is 'reset_all'
+ csr_reset_tx_digital <= (address == ADDR_RESET_CONTROL) & write & writedata[0];
+ csr_reset_rx_digital <= (address == ADDR_RESET_CONTROL) & write & writedata[1];
+ csr_reset_all <= (address == ADDR_RESET_CONTROL) & write & writedata[2];
+
+ // synchronization registers for status signals from transceivers
+ csr_pll_locked[sync_stages] <= pll_locked; // input from transceiver
+ csr_rx_is_lockedtoref[sync_stages] <= rx_is_lockedtoref;
+ csr_rx_is_lockedtodata[sync_stages] <= rx_is_lockedtodata;
+ csr_rx_signaldetect[sync_stages] <= rx_signaldetect;
+ for (stage=2; stage <= sync_stages; stage = stage + 1) begin
+ // additional sync stages
+ csr_pll_locked[stage-1] <= csr_pll_locked[stage];
+ csr_rx_is_lockedtoref[stage-1] <= csr_rx_is_lockedtoref[stage];
+ csr_rx_is_lockedtodata[stage-1] <= csr_rx_is_lockedtodata[stage];
+ csr_rx_signaldetect[stage-1] <= csr_rx_signaldetect[stage];
+ end
+ end
+ end
+
+ // combine reset controller and CSR manual reset control settings
+ assign csr_pll_powerdown = reset_controller_pll_powerdown; // cut manual PLL reset path
+ // | csr_reset_or_pll_powerdown;
+ assign csr_tx_digitalreset = csr_reset_ch_bitmask & {(lanes)
+ {reset_controller_tx_digitalreset | csr_reset_or_reset_tx_digital}};
+ assign csr_rx_analogreset = csr_reset_ch_bitmask & {(lanes)
+ {reset_controller_rx_analogreset | csr_reset_or_reset_rx_analog}};
+ assign csr_rx_digitalreset = csr_reset_ch_bitmask & {(lanes)
+ {reset_controller_rx_digitalreset | csr_reset_or_reset_rx_digital}};
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_csr_common_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_csr_common_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..a323c0a2a16722d20880e2fd2d694fe5031fe780
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_csr_common_h.sv
@@ -0,0 +1,61 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common control & status register map for transceiver PHY IP
+// Applies to Stratix V-generation basic PHY components
+//
+// $Header$
+//
+// PACKAGE DECLARATION
+
+`timescale 1 ps / 1 ps
+
+package alt_xcvr_csr_common_h;
+
+ localparam alt_xcvr_csr_addr_width = 8;
+
+ // register bitmap ---------------------------------------------------------
+ // common blocks, interrupt control
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_INTERRUPT_CH_BITMASK = 1;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_INTERRUPT_ENABLE_BITMASK = 2;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_INTERRUPT_SOURCE = 3;
+
+ // common blocks, loopback control
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PHY_LOOPBACK_SERIAL = 6;
+
+ // common blocks, reset control
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_RESET_CONTROL_BASE = 64;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_RESET_CH_BITMASK = ADDR_RESET_CONTROL_BASE + 8'd1;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_RESET_CONTROL = ADDR_RESET_CONTROL_BASE + 8'd2;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_RESET_FINE_CONTROL = ADDR_RESET_CONTROL_BASE + 8'd4;
+
+ // common blocks, PMA common control & status
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_COMMON_BASE = 32;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_PLL_IS_LOCKED = ADDR_PMA_COMMON_BASE + 8'd2;
+ // common blocks, PMA channel control & status
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_CHANNEL_BASE = 96;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_LOOPBACK_SERIAL = ADDR_PMA_CHANNEL_BASE + 8'd1;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_RX_SIGNALDETECT = ADDR_PMA_CHANNEL_BASE + 8'd3;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_RX_SET_LOCKTODATA = ADDR_PMA_CHANNEL_BASE + 8'd4;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_RX_SET_LOCKTOREF = ADDR_PMA_CHANNEL_BASE + 8'd5;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_RX_IS_LOCKEDTODATA = ADDR_PMA_CHANNEL_BASE + 8'd6;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_RX_IS_LOCKEDTOREF = ADDR_PMA_CHANNEL_BASE + 8'd7;
+
+ // external block for PCS control & status
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS_BASE = 128; // 128-255
+
+ // First word in every PCS CSR is lane # (or lane group # as appropriate)
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS_LANE_GROUP = ADDR_PCS_BASE + 8'd0;
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_csr_pcs8g.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_csr_pcs8g.sv
new file mode 100644
index 0000000000000000000000000000000000000000..62ddfa2dce74f10cf83c30cd54f72573bbf216be
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_csr_pcs8g.sv
@@ -0,0 +1,350 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common control & status register map for transceiver PHY IP
+// Applies to Stratix V-generation basic PHY components
+//
+// $Header$
+//
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_csr_pcs8g #(
+ parameter lanes = 1,
+ parameter words = 2 // for status bits that are per-word, like 8B10B status
+)
+(
+ // user data (avalon-MM formatted)
+ input wire clk,
+ input tri0 reset,
+ input wire [7:0] address,
+ input tri1 read,
+ output reg [31:0] readdata = 0,
+ input tri0 write,
+ input wire [31:0] writedata,
+
+ input wire rx_clk, // to synchronize rx control outputs
+ input wire tx_clk, // to synchronize tx control outputs
+
+ // transceiver status inputs to this CSR
+ input wire [lanes*words - 1 : 0] rx_patterndetect,
+ input wire [lanes*words - 1 : 0] rx_syncstatus,
+ input wire [lanes*words - 1 : 0] rx_errdetect,
+ input wire [lanes*words - 1 : 0] rx_disperr,
+ input wire [lanes - 1 : 0] rx_phase_comp_fifo_error,
+ input wire [lanes - 1 : 0] tx_phase_comp_fifo_error,
+ input wire [lanes*5 - 1: 0] rx_bitslipboundaryselectout,
+ input wire [lanes - 1 : 0] rlv,
+ input wire [lanes*words - 1 : 0] rx_a1a2sizeout,
+
+ // read/write control outputs
+ // PCS controls
+ output wire [lanes - 1 : 0] csr_tx_invpolarity,
+ output wire [lanes*5 - 1 : 0] csr_tx_bitslipboundaryselect,
+ output wire [lanes - 1 : 0] csr_rx_invpolarity,
+ output wire [lanes - 1 : 0] csr_rx_enapatternalign,
+ output wire [lanes - 1 : 0] csr_rx_bitreversalenable,
+ output wire [lanes - 1 : 0] csr_rx_bytereversalenable,
+ output wire [lanes - 1 : 0] csr_rx_bitslip,
+ output wire [lanes - 1 : 0] csr_rx_a1a2size
+);
+ import alt_xcvr_csr_common_h::*;
+ import alt_xcvr_csr_pcs8g_h::*;
+
+ localparam sync_stages = 2; // number of sync stages for transceiver status signals
+ localparam sync_stages_str = "2"; // number of sync stages specified as string (for timing constraints)
+ localparam LANE_REGW = 5;
+
+ // Parameter strings for embedded timing constraints
+ localparam SYNC_RX_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_pcs8g*sync_rx_*[",sync_stages_str,"]*]\""};
+ localparam SYNC_TX_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_pcs8g*sync_tx_*[",sync_stages_str,"]*]\""};
+ localparam CSR_REG_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_pcs8g*csr_indexed_read_only_reg*sreg[",sync_stages_str,"]*]\""};
+ localparam SDC_CONSTRAINTS = {SYNC_RX_CONSTRAINT,";",SYNC_TX_CONSTRAINT,";",CSR_REG_CONSTRAINT};
+
+ // internal registers
+ reg [LANE_REGW-1:0] reg_lane_number = 0; // lane or group number for indirection
+
+ ////////////////////////////////////////////////////////
+ // Read/Write CSR registers with lane indirection
+ ////////////////////////////////////////////////////////
+ // Apply false path timing constraints to synchronization registers. (It does not matter as to which node these are applied).
+ (* altera_attribute = SDC_CONSTRAINTS *)
+ reg [lanes - 1 : 0] reg_tx_invpolarity = 0;
+ reg [lanes - 1 : 0] sync_tx_invpolarity [sync_stages:1]; // synchronize to tx_clk
+ wire [lanes - 1 : 0] write_tx_invpolarity; // indexed write group muxed in
+ wire [0 : 0] lane_tx_invpolarity; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_tx_invpolarity(.in_narrow(writedata[0]),
+ .in_wide(reg_tx_invpolarity), .sel(reg_lane_number),
+ .out_narrow(lane_tx_invpolarity), .out_wide(write_tx_invpolarity));
+
+ reg [lanes*5 - 1 : 0] reg_tx_bitslipboundaryselect = 0;
+ reg [lanes*5 - 1 : 0] sync_tx_bitslipboundaryselect [sync_stages:1]; //synchronize to tx_clk
+ wire [lanes*5 - 1 : 0] write_tx_bitslipboundaryselect; //indexed write group muxed in
+ wire [4:0] lane_tx_bitslipboundaryselect; //selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(5), .sel_size(LANE_REGW), .init_value(0))
+ wmux_tx_bitslipboundaryselect(.in_narrow(writedata[5:1]),
+ .in_wide(reg_tx_bitslipboundaryselect), .sel(reg_lane_number),
+ .out_narrow(lane_tx_bitslipboundaryselect), .out_wide(write_tx_bitslipboundaryselect));
+
+ reg [lanes - 1 : 0] reg_rx_invpolarity = 0;
+ reg [lanes - 1 : 0] sync_rx_invpolarity [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_invpolarity; // indexed write group muxed in
+ wire [0 : 0] lane_rx_invpolarity; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_invpolarity(.in_narrow(writedata[0]),
+ .in_wide(reg_rx_invpolarity), .sel(reg_lane_number),
+ .out_narrow(lane_rx_invpolarity), .out_wide(write_rx_invpolarity));
+
+ reg [lanes - 1 : 0] reg_rx_enapatternalign = 0;
+ reg [lanes - 1 : 0] sync_rx_enapatternalign [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_enapatternalign; // indexed write group muxed in
+ wire [0 : 0] lane_rx_enapatternalign; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_enapatternalign(.in_narrow(writedata[0]),
+ .in_wide(reg_rx_enapatternalign), .sel(reg_lane_number),
+ .out_narrow(lane_rx_enapatternalign), .out_wide(write_rx_enapatternalign));
+
+ reg [lanes - 1 : 0] reg_rx_bitreversalenable = 0;
+ reg [lanes - 1 : 0] sync_rx_bitreversalenable [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_bitreversalenable; // indexed write group muxed in
+ wire [0 : 0] lane_rx_bitreversalenable; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_bitreversalenable(.in_narrow(writedata[1]),
+ .in_wide(reg_rx_bitreversalenable), .sel(reg_lane_number),
+ .out_narrow(lane_rx_bitreversalenable), .out_wide(write_rx_bitreversalenable));
+
+ reg [lanes - 1 : 0] reg_rx_bytereversalenable = 0;
+ reg [lanes - 1 : 0] sync_rx_bytereversalenable [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_bytereversalenable; // indexed write group muxed in
+ wire [0 : 0] lane_rx_bytereversalenable; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_bytereversalenable(.in_narrow(writedata[2]),
+ .in_wide(reg_rx_bytereversalenable), .sel(reg_lane_number),
+ .out_narrow(lane_rx_bytereversalenable), .out_wide(write_rx_bytereversalenable));
+
+ reg [lanes - 1 : 0] reg_rx_bitslip = 0;
+ reg [lanes - 1 : 0] sync_rx_bitslip [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_bitslip; // indexed write group muxed in
+ wire [0 : 0] lane_rx_bitslip; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_bitslip(.in_narrow(writedata[3]),
+ .in_wide(reg_rx_bitslip), .sel(reg_lane_number),
+ .out_narrow(lane_rx_bitslip), .out_wide(write_rx_bitslip));
+
+ reg [lanes - 1 : 0] reg_rx_a1a2size = 0;
+ reg [lanes - 1 : 0] sync_rx_a1a2size [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_a1a2size; // indexed write group muxed in
+ wire [0 : 0] lane_rx_a1a2size; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_a1a2size(.in_narrow(writedata[3]),
+ .in_wide(reg_rx_a1a2size), .sel(reg_lane_number),
+ .out_narrow(lane_rx_a1a2size), .out_wide(write_rx_a1a2size));
+
+ ////////////////////////////////////////////////////////
+ // Read-only CSR registers with lane indirection
+ ////////////////////////////////////////////////////////
+ // read-only status registers are synchronized forms of transceiver status signals
+ // async inputs go to reg [sync_stages], and come out synchronized at reg [1]
+ ////////////////////////////////////////////////////////
+ // read selectors (muxes) that index using the indirect lane (group) number
+ wire [words-1 : 0] lane_rx_patterndetect;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(words), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_patterndetect(.clk(clk), .async_in_wide(rx_patterndetect),
+ .sel(reg_lane_number), .out_narrow(lane_rx_patterndetect));
+
+ wire [words-1 : 0] lane_rx_syncstatus;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(words), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_syncstatus(.clk(clk), .async_in_wide(rx_syncstatus),
+ .sel(reg_lane_number), .out_narrow(lane_rx_syncstatus));
+
+ wire [words-1 : 0] lane_rx_errdetect;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(words), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_errdetect(.clk(clk), .async_in_wide(rx_errdetect),
+ .sel(reg_lane_number), .out_narrow(lane_rx_errdetect));
+
+ wire [words-1 : 0] lane_rx_disperr;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(words), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_disperr(.clk(clk), .async_in_wide(rx_disperr),
+ .sel(reg_lane_number), .out_narrow(lane_rx_disperr));
+
+ wire [words-1 : 0] lane_rx_a1a2sizeout;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(words), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_a1a2sizeout(.clk(clk), .async_in_wide(rx_a1a2sizeout),
+ .sel(reg_lane_number), .out_narrow(lane_rx_a1a2sizeout));
+
+ wire [0 : 0] lane_rx_phase_comp_fifo_error;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_phase_comp_fifo_error(.clk(clk), .async_in_wide(rx_phase_comp_fifo_error),
+ .sel(reg_lane_number), .out_narrow(lane_rx_phase_comp_fifo_error));
+
+ wire [4 : 0] lane_rx_bitslipboundaryselectout;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(5), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_bitslipboundaryselectout(.clk(clk), .async_in_wide(rx_bitslipboundaryselectout),
+ .sel(reg_lane_number), .out_narrow(lane_rx_bitslipboundaryselectout));
+
+ wire [0 : 0] lane_tx_phase_comp_fifo_error;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_tx_phase_comp_fifo_error(.clk(clk), .async_in_wide(tx_phase_comp_fifo_error),
+ .sel(reg_lane_number), .out_narrow(lane_tx_phase_comp_fifo_error));
+
+ wire [0 : 0] lane_rlv;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rlv(.clk(clk), .async_in_wide(rlv),
+ .sel(reg_lane_number), .out_narrow(lane_rlv));
+
+
+ always @(posedge clk or posedge reset) begin
+ if (reset == 1) begin
+ readdata <= 0;
+ reg_lane_number <= 0;
+ reg_tx_invpolarity <= 0;
+ reg_tx_bitslipboundaryselect <= 0;
+ reg_rx_invpolarity <= 0;
+ reg_rx_enapatternalign <= 0;
+ reg_rx_bitreversalenable <= 0;
+ reg_rx_bytereversalenable <= 0;
+ reg_rx_bitslip <= 0;
+ reg_rx_a1a2size <= 0;
+
+ // no need to clear synchronization registers, since they do not store state
+ end
+ else begin
+ // decode read & write for each supported address
+ case (address)
+ // lane or group number for indirection
+ ADDR_PCS_LANE_GROUP: begin
+ readdata <= (32'd0 | reg_lane_number);
+ if (write) reg_lane_number <= writedata[LANE_REGW-1:0];
+ end
+
+ // offset + 1, read-only RX status bits
+ // bit 0, rx_phase_comp_fifo_error
+ // bit 5:1, rx_bitslipboundaryselectout
+ ADDR_PCS8G_RX_STATUS: begin
+ readdata <= (32'd0 |
+ {lane_rx_bitslipboundaryselectout, //bit 5-1
+ lane_rx_phase_comp_fifo_error}); // bit 0
+ end
+
+ // offset + 2, read-only TX status bits
+ // bit 0, tx_phase_comp_fifo_error
+ ADDR_PCS8G_TX_STATUS: begin
+ readdata <= (32'd0 | lane_tx_phase_comp_fifo_error); // bit 0
+ end
+
+ // offset + 3, read/write TX control bits
+ // bit 0, tx_invpolarity
+ // bit 5:1, tx_bitslipboundaryselect
+ ADDR_PCS8G_TX_CONTROL: begin
+ readdata <= (32'd0 | {lane_tx_bitslipboundaryselect, lane_tx_invpolarity});
+ if (write)
+ begin
+ reg_tx_invpolarity <= write_tx_invpolarity;
+ reg_tx_bitslipboundaryselect <= write_tx_bitslipboundaryselect;
+ end
+ end
+
+ // offset + 4, read/write RX control bits
+ // bit 0, rx_invpolarity
+ ADDR_PCS8G_RX_CONTROL: begin
+ readdata <= (32'd0 | lane_rx_invpolarity);
+ if (write) reg_rx_invpolarity <= write_rx_invpolarity;
+ end
+
+ // offset + 5, read/write RX WA control bits
+ // bit 0, rx_enapatternalign
+ // bit 1, rx_bitreversalenable
+ // bit 2, rx_bytereversalenable
+ // bit 3, rx_bitslip
+ // bit 4, rx_a1a2size
+ ADDR_PCS8G_RX_WA_CONTROL: begin
+ readdata <= (32'd0 | { lane_rx_a1a2size, // bit 4
+ lane_rx_bitslip, // bit 3
+ lane_rx_bytereversalenable, // bit 2
+ lane_rx_bitreversalenable, // bit 1
+ lane_rx_enapatternalign}); // bit 0
+ if (write)
+ begin
+ reg_rx_enapatternalign <= write_rx_enapatternalign;
+ reg_rx_bitreversalenable <= write_rx_bitreversalenable;
+ reg_rx_bytereversalenable <= write_rx_bytereversalenable;
+ reg_rx_bitslip <= write_rx_bitslip;
+ reg_rx_a1a2size <= write_rx_a1a2size;
+ end
+ end
+
+ // offset + 5, read RX WA status bits
+ // bit 3:0, rx_errdetect
+ // bit 7:4, rx_syncstatus
+ // bit 11:8, rx_disperr
+ // bit 15:12, rx_patterndetect
+ // bit 16, rlv
+ // bit 23:20, rx_a1a2sizeout
+ ADDR_PCS8G_RX_WA_STATUS: begin
+ readdata <= (32'd0 | {(4'b0 | lane_rx_a1a2sizeout), // bit 23:20
+ (4'b0 | lane_rlv), // bit 16
+ (4'b0 | lane_rx_patterndetect), // bit 15:12
+ (4'b0 | lane_rx_disperr), // bit 11:8
+ (4'b0 | lane_rx_syncstatus), // bit 7:4
+ (4'b0 | lane_rx_errdetect)}); // bit 3:0
+ end
+
+ default: readdata <= ~ 32'd0; // use too many LEs?
+ endcase
+ end
+ end
+
+ // synchronize TX controls to tx_clk before generating output
+ // sysclk-sync'ed input enters at [sync_stages], and tx_clk-sync'ed output exist at [1]
+ integer stage;
+ always @(posedge tx_clk) begin
+ sync_tx_invpolarity[sync_stages] <= reg_tx_invpolarity;
+ sync_tx_bitslipboundaryselect[sync_stages] <= reg_tx_bitslipboundaryselect;
+ for (stage=2; stage <= sync_stages; stage = stage + 1) begin
+ // additional sync stages
+ sync_tx_invpolarity[stage-1] <= sync_tx_invpolarity[stage];
+ sync_tx_bitslipboundaryselect[stage-1] <= sync_tx_bitslipboundaryselect[stage];
+ end
+ end
+ assign csr_tx_invpolarity = sync_tx_invpolarity[1];
+ assign csr_tx_bitslipboundaryselect = sync_tx_bitslipboundaryselect[1];
+
+ // synchronize RX controls to rx_clk before generating output
+ // sysclk-sync'ed input enters at [sync_stages], and rx_clk-sync'ed output exist at [1]
+ always @(posedge rx_clk) begin
+ sync_rx_invpolarity[sync_stages] <= reg_rx_invpolarity;
+ sync_rx_enapatternalign[sync_stages] <= reg_rx_enapatternalign;
+ sync_rx_bitreversalenable[sync_stages] <= reg_rx_bitreversalenable;
+ sync_rx_bytereversalenable[sync_stages] <= reg_rx_bytereversalenable;
+ sync_rx_bitslip[sync_stages] <= reg_rx_bitslip;
+ sync_rx_a1a2size[sync_stages] <= reg_rx_a1a2size;
+ for (stage=2; stage <= sync_stages; stage = stage + 1) begin
+ // additional sync stages
+ sync_rx_invpolarity[stage-1] <= sync_rx_invpolarity[stage];
+ sync_rx_enapatternalign[stage-1] <= sync_rx_enapatternalign[stage];
+ sync_rx_bitreversalenable[stage-1] <= sync_rx_bitreversalenable[stage];
+ sync_rx_bytereversalenable[stage-1] <= sync_rx_bytereversalenable[stage];
+ sync_rx_bitslip[stage-1] <= sync_rx_bitslip[stage];
+ sync_rx_a1a2size[stage-1] <= sync_rx_a1a2size[stage];
+ end
+ end
+ assign csr_rx_invpolarity = sync_rx_invpolarity[1];
+ assign csr_rx_enapatternalign = sync_rx_enapatternalign[1];
+ assign csr_rx_bitreversalenable = sync_rx_bitreversalenable[1];
+ assign csr_rx_bytereversalenable = sync_rx_bytereversalenable[1];
+ assign csr_rx_bitslip = sync_rx_bitslip[1];
+ assign csr_rx_a1a2size = sync_rx_a1a2size[1];
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_csr_pcs8g_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_csr_pcs8g_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..09f65ef3aee3227b1f9f9ba7d3359a300eb092ac
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_csr_pcs8g_h.sv
@@ -0,0 +1,33 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common control & status register map for transceiver PHY IP
+// Applies to Stratix V-generation basic PHY components
+//
+// $Header$
+//
+// PACKAGE DECLARATION
+package alt_xcvr_csr_pcs8g_h;
+
+ import alt_xcvr_csr_common_h::*;
+
+ // 8G PCS, a.k.a. "Standard PCS", control and status bits
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_RX_STATUS = ADDR_PCS_BASE + 8'd1;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_TX_STATUS = ADDR_PCS_BASE + 8'd2;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_TX_CONTROL = ADDR_PCS_BASE + 8'd3;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_RX_CONTROL = ADDR_PCS_BASE + 8'd4;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_RX_WA_CONTROL = ADDR_PCS_BASE + 8'd5;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_RX_WA_STATUS = ADDR_PCS_BASE + 8'd6;
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_csr_selector.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_csr_selector.sv
new file mode 100644
index 0000000000000000000000000000000000000000..2e843e4597c8292f41a2d244cf5bb2dae2d70abc
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_csr_selector.sv
@@ -0,0 +1,116 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Select a sub-group from a wide register
+// Useful for indirection indexing
+//
+// $Header$
+//
+
+`timescale 1 ns / 1 ns
+
+module csr_mux #(
+ parameter groups = 2,
+ parameter grp_size = 1,
+ parameter sel_size = 1
+)
+(
+ input wire [groups*grp_size-1:0] in_wide,
+ input tri0 [sel_size-1:0] sel,
+ output wire [grp_size-1:0] out_narrow
+);
+// lpm_mux #(.lpm_size(groups), .lpm_width(grp_size), .lpm_widths(sel_size))
+// mux (.data(in_wide), .sel(sel), .result(out_narrow));
+ wire [grp_size-1:0] in_groups [groups-1:0];
+
+ // a synthesizable mux, with a parameterized number of inputs
+ genvar i;
+ assign in_groups[0] = in_wide[grp_size-1:0] & {grp_size{sel == 0}};
+ generate for (i=1; i<groups; i = i+1) begin: mux
+ assign in_groups[i] = in_groups[i-1] | in_wide[i*grp_size +: grp_size] & {grp_size{sel == i}};
+ end
+ endgenerate
+ assign out_narrow = in_groups[groups-1];
+endmodule
+
+//
+// write to a sub-group of a wide register
+// Useful for indirection indexing on write
+//
+module csr_indexed_write_mux #(
+ parameter groups = 2,
+ parameter grp_size = 1,
+ parameter sel_size = 1,
+ parameter init_value = 0
+)
+(
+ input wire [grp_size-1:0] in_narrow,
+ input tri0 [sel_size-1:0] sel,
+ output wire [grp_size-1:0] out_narrow, // for read back to mgmt interface
+ input wire [groups*grp_size-1:0] in_wide, // full-width control reg state
+ output wire [groups*grp_size-1:0] out_wide // to write to full-width control reg
+);
+ wire [groups*grp_size-1:0] wire_wide [groups-1:0];
+
+ // in_narrow is output in the group position indicated by .sel() input
+ genvar i;
+ assign wire_wide[0] = (in_wide & {grp_size{sel != 0}}) | (in_narrow & {grp_size{sel == 0}});
+ generate for (i=1; i<groups; i = i+1) begin: mux
+ assign wire_wide[i] = wire_wide[i-1]
+ | (in_wide & {{grp_size{sel != i}}, {(grp_size*i){1'b0}}})
+ | ({in_narrow & {grp_size{sel == i}}, {(grp_size*i){1'b0}}});
+ end
+ endgenerate
+ assign out_wide = wire_wide[groups-1];
+
+ // generate out_narrow as ordinary mux of in_wide
+ csr_mux #(.groups(groups), .grp_size(grp_size), .sel_size(sel_size))
+ o_narrow(.in_wide(in_wide), .sel(sel), .out_narrow(out_narrow));
+
+endmodule
+
+//
+// read from a sub-group of a wide, async status input
+// Creates synchronization logic to sample in local clock domain
+// Useful for indirection indexing on read-only status bits
+//
+module csr_indexed_read_only_reg #(
+ parameter groups = 2,
+ parameter grp_size = 1,
+ parameter sel_size = 1,
+ parameter sync_stages = 2
+)
+(
+ input wire clk,
+ input tri0 [sel_size-1:0] sel,
+ output wire [grp_size-1:0] out_narrow, // for read back to mgmt interface
+ input wire [groups*grp_size-1:0] async_in_wide // full-width async status inputs
+);
+ // read-only status registers are synchronized forms of async status signals
+ // async inputs go to sreg [sync_stages], and come out synchronized at sreg [1]
+ reg [groups*grp_size-1:0] sreg [sync_stages:1];
+ integer stage;
+ always @(posedge clk) begin
+ sreg[sync_stages] <= async_in_wide;
+ for (stage=2; stage <= sync_stages; stage = stage + 1) begin
+ // additional sync stages
+ sreg[stage-1] <= sreg[stage];
+ end
+ end
+
+ // generate out_narrow as ordinary mux of out_wide
+ csr_mux #(.groups(groups), .grp_size(grp_size), .sel_size(sel_size))
+ o_narrow(.in_wide(sreg[1]), .sel(sel), .out_narrow(out_narrow));
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_m2s.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_m2s.sv
new file mode 100644
index 0000000000000000000000000000000000000000..143f8260ab27069cf2eb8fd54be2d08f84f018ec
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_m2s.sv
@@ -0,0 +1,61 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Master-to-slave access fabric
+//
+// Combined with external multi-master arbitration, this block gates
+// master read, write, address, and writedata outputs, and generates
+// a waitrequest when arbiter indicates access is not granted
+
+// $Header$
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_m2s #(
+ parameter width_addr = 3,
+ parameter width_data = 32
+) (
+ input wire clock,
+ output wire req, // request to arbiter for slave access
+ input wire grant,
+
+ // signals from/to master
+ input wire m_read,
+ input wire m_write,
+ input wire [width_addr-1:0] m_address,
+ input wire [width_data-1:0] m_writedata,
+ output wire [width_data-1:0] m_readdata,
+ output wire m_waitrequest,
+
+ // signals from/to slave
+ output wire s_read,
+ output wire s_write,
+ output wire [width_addr-1:0] s_address,
+ output wire [width_data-1:0] s_writedata,
+ input wire [width_data-1:0] s_readdata,
+ input wire s_waitrequest
+);
+
+ // If master is requesting access, generate waitreq until granted
+ assign req = m_read | m_write; // master access requests
+ assign m_waitrequest = grant ? s_waitrequest : req;
+
+ // gate outputs to slave with grant signal
+ assign s_read = m_read & grant;
+ assign s_write = m_write & grant;
+ assign s_address = m_address & {width_addr{grant}};
+ assign s_writedata = m_writedata & {width_data{grant}};
+
+ // slave data outputs pass through directly
+ assign m_readdata = s_readdata;
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_mgmt2dec.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_mgmt2dec.sv
new file mode 100644
index 0000000000000000000000000000000000000000..93ce24e6bb50518c47c242026699fb45dcee975a
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_mgmt2dec.sv
@@ -0,0 +1,90 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Management interface address decoder for Altera Transceiver PHY
+//
+// Addresses common case of 2 modules to be stitched together:
+// - 'top' PHY channel blocks (includes reset control, CSR, ...)
+// - dynamic reconfiguration block
+
+// $Header$
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_mgmt2dec (
+
+ // user-visible external management interface
+ input wire mgmt_clk_reset,
+ input wire mgmt_clk,
+
+ input wire [8:0] mgmt_address,
+ input wire mgmt_read,
+ output reg [31:0] mgmt_readdata = ~32'd0,
+ output reg mgmt_waitrequest = 0,
+ input wire mgmt_write,
+
+ // internal interface to 'top' csr block
+ output wire [7:0] topcsr_address,
+ output wire topcsr_read,
+ input wire [31:0] topcsr_readdata,
+ input wire topcsr_waitrequest,
+ output wire topcsr_write,
+
+ // internal interface to 'top' csr block
+ output wire [7:0] reconf_address,
+ output wire reconf_read,
+ input wire [31:0] reconf_readdata,
+ input wire reconf_waitrequest,
+ output wire reconf_write
+);
+ localparam width_swa = 7; // word address width of interface to slaves (2 for top.CSR and 1 for reconfig)
+ localparam dec_count = 2; // count of the total number of sub-components that can act
+ // as slaves to the mgmt interface
+ localparam dec_topcsr = 0; // uses 2 128-word address blocks
+ localparam dec_reconf = 1; // uses 1 128-word address block
+
+
+ ///////////////////////////////////////////////////////////////////////
+ // Decoder for multiple slaves of reconfig_mgmt interface
+ ///////////////////////////////////////////////////////////////////////
+ wire [dec_count-1:0] r_decode;
+ assign r_decode =
+ (mgmt_address[8:width_swa+1] == dec_topcsr) ? (({dec_count-dec_topcsr{1'b0}} | 1'b1) << dec_topcsr)
+ : (mgmt_address[8:width_swa] == 2'd2) ? (({dec_count-dec_reconf{1'b0}} | 1'b1) << dec_reconf)
+ : {dec_count{1'b0}};
+
+ // reconfig_mgmt output generation is muxing of decoded slave output
+ always @(*) begin
+ if (r_decode[dec_topcsr] == 1'b1) begin
+ mgmt_readdata = topcsr_readdata;
+ mgmt_waitrequest = topcsr_waitrequest;
+ end else if (r_decode[dec_reconf] == 1'b1) begin
+ mgmt_readdata = reconf_readdata;
+ mgmt_waitrequest = reconf_waitrequest;
+ end else begin
+ mgmt_readdata = -1;
+ mgmt_waitrequest = 1'b0;
+ end
+ end
+
+ // internal interface to 'top' csr block
+ assign topcsr_address = mgmt_address[width_swa:0]; // top.csr uses 2 128-word blocks
+ assign topcsr_read = mgmt_read & r_decode[dec_topcsr];
+ assign topcsr_write = mgmt_write & r_decode[dec_topcsr];
+
+ // internal interface to 'top' csr block
+ assign reconf_address = mgmt_address[width_swa-1:0]; // reconfig uses 1 128-word block
+ assign reconf_read = mgmt_read & r_decode[dec_reconf];
+ assign reconf_write = mgmt_write & r_decode[dec_reconf];
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_mgmt2dec_phyreconfig.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_mgmt2dec_phyreconfig.sv
new file mode 100644
index 0000000000000000000000000000000000000000..3993651a7280e45e8ed8823d62ce37b8836861c2
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_mgmt2dec_phyreconfig.sv
@@ -0,0 +1,110 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//-----------------------------------------------------------------------------
+//
+// Description: Custom management interface address decoder for Altera
+// transciever PHY. Addresses common case of 2 modules to be stitched together:
+// - 'top' PHY channel blocks (includes reset control, CSR, ...)
+// - dynamic reconfiguration block
+//
+// Authors: dunnikri 19-Aug-2010
+//
+// Copyright (c) Altera Corporation 1997 - 2010
+// All rights reserved.
+//
+//
+//-----------------------------------------------------------------------------
+
+//`timescale 1 ns / 1 ns
+
+module alt_xcvr_mgmt2dec_phyreconfig (
+
+ // user-visible external management interface
+ input wire mgmt_clk_reset,
+ input wire mgmt_clk,
+
+ input wire [8:0] mgmt_address,
+ input wire mgmt_read,
+ output reg [31:0] mgmt_readdata = ~32'd0,
+ output reg mgmt_waitrequest = 0,
+ input wire mgmt_write,
+
+ // internal interface to xaui phy block
+ output wire [7:0] sc_phy_address,
+ output wire sc_phy_read,
+ input wire [31:0] sc_phy_readdata,
+ input wire sc_phy_waitrequest,
+ output wire sc_phy_write,
+
+ // internal interface to reconfig block
+ output wire [6:0] sc_reconf_address,
+ output wire sc_reconf_read,
+ input wire [31:0] sc_reconf_readdata,
+ input wire sc_reconf_waitrequest,
+ output wire sc_reconf_write
+);
+ localparam width_swa = 7; // word address width of interface to slaves (2 for phy and 1 for reconfig)
+ localparam dec_count = 2; // count of the total number of sub-components that can act
+ // as slaves to the mgmt interface
+ localparam dec_sc_phy = 0; //
+ localparam dec_reconf = 1; //
+
+ ///////////////////////////////////////////////////////////////////////
+ // Decoder for multiple slaves of reconfig_mgmt interface
+ ///////////////////////////////////////////////////////////////////////
+ wire [dec_count-1:0] r_decode; //1-hot encoding
+
+ //-----------------------Memory Map Reference-------------------------
+ //--------------------------------------------------------------------
+ //Block | Word Address | Byte Address |
+ //-------------------------------------------------------------------
+ //PHY Common | 0x0 | 0x0 |
+ //PMA Controller | 0x20 | 0x80 |
+ //Reset Controller | 0x40 | 0x100 |
+ //PMA Channel Controller | 0x60 | 0x180 |
+ //PCS | 0x80 | 0x200 |
+ //XCVR Reconfig | 0x100 | 0x400 |
+ //--------------------------------------------------------------------
+
+ //Decoding is based on memory map word address
+ assign r_decode =
+ (mgmt_address[8:width_swa+1] == dec_sc_phy) ? (({dec_count-dec_sc_phy{1'b0}} | 1'b1) << dec_sc_phy)
+ : (mgmt_address[8:width_swa] == 2'd2) ? (({dec_count-dec_reconf{1'b0}} | 1'b1) << dec_reconf)
+ : {dec_count{1'b0}};
+
+ // reconfig_mgmt output generation is muxing of decoded slave output
+ always @(*) begin
+ if (r_decode[dec_sc_phy] == 1'b1) begin
+ mgmt_readdata = sc_phy_readdata;
+ mgmt_waitrequest = sc_phy_waitrequest;
+ end else if (r_decode[dec_reconf] == 1'b1) begin
+ mgmt_readdata = sc_reconf_readdata;
+ mgmt_waitrequest = sc_reconf_waitrequest;
+ end else begin
+ mgmt_readdata = -1;
+ mgmt_waitrequest = 1'b0;
+ end
+ end
+
+ // internal interface to 'top' phy block
+ assign sc_phy_address = mgmt_address[width_swa:0];
+ assign sc_phy_read = mgmt_read & r_decode[dec_sc_phy];
+ assign sc_phy_write = mgmt_write & r_decode[dec_sc_phy];
+
+ // internal interface to 'top' reconfig block
+ assign sc_reconf_address = mgmt_address[width_swa-1:0];
+ assign sc_reconf_read = mgmt_read & r_decode[dec_reconf];
+ assign sc_reconf_write = mgmt_write & r_decode[dec_reconf];
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_mgmt2dec_xaui.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_mgmt2dec_xaui.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5720dddc8ee64986827d0db95c96c90eec94cdf3
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_mgmt2dec_xaui.sv
@@ -0,0 +1,134 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//-----------------------------------------------------------------------------
+//
+// Description: Custom management interface address decoder for Altera
+// transciever PHY. Addresses common case of 3 modules to be stitched together:
+// - CSR, Alt_PMA controller, Alt_PMA_Channel controller
+//
+// Authors: dunnikri 19-Aug-2010
+//
+// Copyright (c) Altera Corporation 1997 - 2010
+// All rights reserved.
+//
+//
+//-----------------------------------------------------------------------------
+
+`timescale 1 ps / 1 ps
+
+module alt_xcvr_mgmt2dec_xaui (
+
+ // user-visible external management interface
+ input wire mgmt_clk_reset,
+ input wire mgmt_clk,
+
+ input wire [7:0] mgmt_address,
+ input wire mgmt_read,
+ output reg [31:0] mgmt_readdata = ~32'd0,
+ output reg mgmt_waitrequest = 0,
+ input wire mgmt_write,
+
+ // internal interface to xaui pma channel controller
+ output wire [5:0] sc_pma_ch_controller_address,
+ output wire sc_pma_ch_controller_read,
+ input wire [31:0] sc_pma_ch_controller_readdata,
+ input wire sc_pma_ch_controller_waitrequest,
+ output wire sc_pma_ch_controller_write,
+
+ // internal interface to pma controller block
+ output wire [1:0] sc_pma_controller_address,
+ output wire sc_pma_controller_read,
+ input wire [31:0] sc_pma_controller_readdata,
+ input wire sc_pma_controller_waitrequest,
+ output wire sc_pma_controller_write,
+
+ // internal interface to hxaui csr block
+ output wire [4:0] sc_csr_address,
+ output wire sc_csr_read,
+ input wire [31:0] sc_csr_readdata,
+ input wire sc_csr_waitrequest,
+ output wire sc_csr_write
+);
+ localparam width_swa = 7; // word address width of interface to slaves (2 for phy and 1 for reconfig)
+ localparam dec_count = 3; // count of the total number of sub-components that can act
+ // as slaves to the mgmt interface
+
+ localparam dec_pma_control = 0;
+ localparam dec_csr = 1;
+ localparam dec_pma_ch_control = 2;
+
+ //--------------------------------------------------------------------
+ //Block | Word Address | Byte Address |
+ //-------------------------------------------------------------------
+ //PHY Common | 0x0 | 0x0 |
+ //PMA Controller | 0x20 | 0x80 |
+ //Reset Controller | 0x40 | 0x100 |
+ //PMA Channel Controller | 0x60 | 0x180 |
+ //PCS | 0x80 | 0x200 |
+ //XCVR Reconfig | 0x100 | 0x400 |
+ //-------------------------------------------------------------------
+
+
+ ///////////////////////////////////////////////////////////////////////
+ // Decoder for multiple slaves of reconfig_mgmt interface
+ ///////////////////////////////////////////////////////////////////////
+ wire [dec_count-1:0] r_decode; //1-hot encoding
+
+ //PMA Controller - 0x20 (0010 0000)
+ //Reset Controller - 0x40 (0100 0000)
+ //Channel Controller - 0x60 (0110 0000)
+ //PCS - 0x80 (1000 0000)
+ //Consider first 3 MSBs for decoding
+ /*assign r_decode =
+ (mgmt_address[7:5] == 3'd1) ? (({dec_count-dec_pma_control{1'b0}} | 1'b1) << dec_pma_control)
+ : (mgmt_address[7:5] == 3'd4) ? (({dec_count-dec_csr{1'b0}} | 1'b1) << dec_csr)
+ : (mgmt_address[7:5] == 3'd3) ? (({dec_count-dec_pma_ch_control{1'b0}} | 1'b1) << dec_pma_ch_control)
+ : {dec_count{1'b0}};*/
+
+ assign r_decode[0] = (!mgmt_address[7]) & (!mgmt_address[6]) & (mgmt_address[5]);
+ assign r_decode[1] = (mgmt_address[7]) & (!mgmt_address[6]) & (!mgmt_address[5]);
+ assign r_decode[2] = (!mgmt_address[7]) & (mgmt_address[6]);
+
+
+ always @(*) begin
+ if (r_decode[dec_pma_ch_control] == 1'b1) begin
+ mgmt_readdata = sc_pma_ch_controller_readdata;
+ mgmt_waitrequest = sc_pma_ch_controller_waitrequest;
+ end else if (r_decode[dec_pma_control] == 1'b1) begin
+ mgmt_readdata = sc_pma_controller_readdata;
+ mgmt_waitrequest = sc_pma_controller_waitrequest;
+ end else if (r_decode[dec_csr] == 1'b1) begin
+ mgmt_readdata = sc_csr_readdata;
+ mgmt_waitrequest = sc_csr_waitrequest;
+ end else begin
+ mgmt_readdata = -1;
+ mgmt_waitrequest = 1'b0;
+ end
+ end
+
+ // internal interface to alt_pma_ch_control block
+ assign sc_pma_ch_controller_address = mgmt_address[5:0]; //6 bit address
+ assign sc_pma_ch_controller_read = mgmt_read & r_decode[dec_pma_ch_control];
+ assign sc_pma_ch_controller_write = mgmt_write & r_decode[dec_pma_ch_control];
+
+ // internal interface to pma_control block
+ assign sc_pma_controller_address = mgmt_address[1:0]; // 2 bit address
+ assign sc_pma_controller_read = mgmt_read & r_decode[dec_pma_control];
+ assign sc_pma_controller_write = mgmt_write & r_decode[dec_pma_control];
+
+ // internal interface to csr block
+ assign sc_csr_address = mgmt_address[4:0]; // 5 bit address
+ assign sc_csr_read = mgmt_read & r_decode[dec_csr];
+ assign sc_csr_write = mgmt_write & r_decode[dec_csr];
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_analog.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_analog.sv
new file mode 100644
index 0000000000000000000000000000000000000000..c11f7aa371601873a1d6fc77d0c67623f66bff56
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_analog.sv
@@ -0,0 +1,146 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_analog #(
+ parameter device_family = "Stratix V"
+)
+(
+
+input wire reconfig_clk, // this will be the reconfig clk
+input wire reset,
+
+//avalon MM slave
+input wire [2:0] analog_reconfig_address, // MM address
+input wire [31:0] analog_reconfig_writedata,
+input wire analog_reconfig_write,
+input wire analog_reconfig_read,
+
+//output MM slave
+output wire [31:0] analog_reconfig_readdata, // from MM
+output wire analog_reconfig_waitrequest,
+//output wire analog_reconfig_error,
+output wire analog_reconfig_done,
+
+// input from base_reconfig
+input wire analog_reconfig_irq_from_base,
+input wire analog_reconfig_waitrequest_from_base,
+
+
+// output to base_reconfig
+// Avalon MM Master
+output wire [2:0] analog_reconfig_address_base, // 3 bit MM
+output wire [31:0] analog_reconfig_writedata_base,
+output wire analog_reconfig_write_base, // start write to GXB
+output wire analog_reconfig_read_base, // start read from GXB
+
+// input from base reconfig
+input wire [31:0] analog_reconfig_readdata_base, // data from read command
+ output wire arb_req,
+ input wire arb_grant
+);
+
+//parameter device_family = "StratixIV"; // or ArriaII
+
+
+generate
+ //Deepak - added namespace support for CIVGX and AII GX
+ if((device_family == "Stratix IV") || (device_family == "Arria II") || (device_family == "Cyclone IV GX") || (device_family == "Arria II GX") || (device_family == "Arria II GZ") || (device_family == "HardCopy IV"))
+ begin
+ wire [4:0] w_tgx_analog_reconfig_address_base;
+ alt_xcvr_reconfig_analog_tgx reconfig_analog_tgx(
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .analog_reconfig_address(analog_reconfig_address),
+ .analog_reconfig_writedata(analog_reconfig_writedata),
+ .analog_reconfig_write(analog_reconfig_write),
+ .analog_reconfig_read(analog_reconfig_read),
+ .analog_reconfig_readdata(analog_reconfig_readdata),
+ .analog_reconfig_waitrequest(analog_reconfig_waitrequest),
+ .analog_reconfig_done(analog_reconfig_done),
+ .analog_reconfig_irq_from_base(analog_reconfig_irq_from_base),
+ .analog_reconfig_waitrequest_from_base(analog_reconfig_waitrequest_from_base),
+ .analog_reconfig_address_base(analog_reconfig_address_base),
+ .analog_reconfig_writedata_base(analog_reconfig_writedata_base),
+ .analog_reconfig_write_base(analog_reconfig_write_base),
+ .analog_reconfig_read_base(analog_reconfig_read_base),
+ .analog_reconfig_readdata_base(analog_reconfig_readdata_base)
+ );
+ assign analog_reconfig_address_base = w_tgx_analog_reconfig_address_base[4:2];
+ assign arb_req = 1'b0 & arb_grant; // not currently used in S4 architecture
+ end
+ else if(device_family == "Stratix V")
+ begin
+ alt_xcvr_reconfig_analog_sv reconfig_analog_sv(
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .analog_reconfig_address(analog_reconfig_address),
+ .analog_reconfig_writedata(analog_reconfig_writedata),
+ .analog_reconfig_write(analog_reconfig_write),
+ .analog_reconfig_read(analog_reconfig_read),
+ .analog_reconfig_readdata(analog_reconfig_readdata),
+ .analog_reconfig_waitrequest(analog_reconfig_waitrequest),
+ .analog_reconfig_done(analog_reconfig_done),
+ .analog_reconfig_irq_from_base(analog_reconfig_irq_from_base),
+ .analog_reconfig_waitrequest_from_base(analog_reconfig_waitrequest_from_base),
+ .analog_reconfig_address_base(analog_reconfig_address_base),
+ .analog_reconfig_writedata_base(analog_reconfig_writedata_base),
+ .analog_reconfig_write_base(analog_reconfig_write_base),
+ .analog_reconfig_read_base(analog_reconfig_read_base),
+ .analog_reconfig_readdata_base(analog_reconfig_readdata_base),
+ .arb_req(arb_req),
+ .arb_grant(arb_grant)
+
+ );
+ end
+ else if(device_family == "Arria V")
+ begin
+ alt_xcvr_reconfig_analog_av reconfig_analog_av(
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .analog_reconfig_address(analog_reconfig_address),
+ .analog_reconfig_writedata(analog_reconfig_writedata),
+ .analog_reconfig_write(analog_reconfig_write),
+ .analog_reconfig_read(analog_reconfig_read),
+ .analog_reconfig_readdata(analog_reconfig_readdata),
+ .analog_reconfig_waitrequest(analog_reconfig_waitrequest),
+ .analog_reconfig_done(analog_reconfig_done),
+ .analog_reconfig_irq_from_base(analog_reconfig_irq_from_base),
+ .analog_reconfig_waitrequest_from_base(analog_reconfig_waitrequest_from_base),
+ .analog_reconfig_address_base(analog_reconfig_address_base),
+ .analog_reconfig_writedata_base(analog_reconfig_writedata_base),
+ .analog_reconfig_write_base(analog_reconfig_write_base),
+ .analog_reconfig_read_base(analog_reconfig_read_base),
+ .analog_reconfig_readdata_base(analog_reconfig_readdata_base),
+ .arb_req(arb_req),
+ .arb_grant(arb_grant)
+
+ );
+ end
+ else
+ begin
+ assign analog_reconfig_readdata = 32'd0;
+ assign analog_reconfig_waitrequest = 1'd0;
+ assign analog_reconfig_done = 1'd1;
+ assign analog_reconfig_address_base = 3'd0;
+ assign analog_reconfig_writedata_base = 32'd0;
+ assign analog_reconfig_write_base = 1'd0;
+ assign analog_reconfig_read_base = 1'd0;
+ assign arb_req = 1'd0;
+ end
+
+endgenerate
+
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_analog_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_analog_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..b124cab8495ba45a26198a9b5ab25318441e6f01
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_analog_tgx.v
@@ -0,0 +1,763 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_analog_tgx (
+
+input wire reconfig_clk, // this will be the reconfig clk
+input wire reset,
+
+//avalon MM slave
+input wire [2:0] analog_reconfig_address, // MM address
+input wire [31:0] analog_reconfig_writedata,
+input wire analog_reconfig_write,
+input wire analog_reconfig_read,
+
+//output MM slave
+output reg [31:0] analog_reconfig_readdata, // from MM
+output wire analog_reconfig_waitrequest,
+//output wire analog_reconfig_error,
+output reg analog_reconfig_done,
+
+// input from base_reconfig
+ input wire analog_reconfig_irq_from_base,
+ input wire analog_reconfig_waitrequest_from_base,
+
+
+// output to base_reconfig
+// Avalon MM Master
+output wire [4:0] analog_reconfig_address_base, // 3 bit MM
+output wire [31:0] analog_reconfig_writedata_base,
+output wire analog_reconfig_write_base, // start write to GXB
+output wire analog_reconfig_read_base, // start read from GXB
+
+// input from base reconfig
+input wire [31:0] analog_reconfig_readdata_base // data from read command
+);
+
+parameter device_family = "Stratix IV"; // or ArriaII
+
+// new memory map -- register indirection
+//----------------------------------------------
+// address data[15:0]
+// 0 wr/rd logical_channel_address
+// 1 rd physical_chnl
+// 2 wr/rd control (write, read) / status (error, datavalid, busy)
+// 3 wr/rd addr_offset
+// 4 wr/rd data
+//
+// addr_offset ( upto 16 bits)
+// 0-15 TX parameters : vod, preemph_0t, preemph_1t, preemph_2t
+// 16-31 RX parameters : dcgain, eqctrl
+
+//local parameters
+localparam ADDR_WIDTH = 3;
+
+localparam IDLE = 4'b0000;
+localparam READ_FROM_GXB = 4'b0001;
+localparam WRITE_TO_GXB = 4'b0010;
+localparam SET_INFO_ON_BASIC = 4'b0011;
+localparam WRITE_DONE = 4'b0100;
+localparam READ_FROM_BASIC = 4'b0101;
+localparam READ_FROM_BASIC_DONE = 4'b0110;
+localparam READ_IDLE = 4'b0111;
+localparam GET_MUTEX = 4'b1000;
+localparam WRITE_CHL_ADDR = 4'b1001;
+localparam READ_OR_SET_INFO = 4'b1010;
+
+localparam ILLEGAL_PHYSICAL_CHNL = 12'b111111111111;
+
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [3:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+//reg [3:0] prev_state;
+genvar i;
+integer j;
+wire [(2**ADDR_WIDTH)-1:0] address_decode;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [4:0] master_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_read;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [31:0] master_writedata;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] chnl_addr_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [11:0] phys_chnl_addr_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg logical_chnl_addr_updated;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] status_reg;
+reg [1:0] control_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] data_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg needs_second_access;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [4:0] addr_offset;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg needs_second_write_access;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg do_read_before_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg set_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg have_mutex;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg req_and_use_mutex;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg do_read_phys_chnl;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg do_write_chnl_addr;
+
+wire mutex_grant;
+wire mutex_acq_waitrequest;
+wire [31:0] mutex_acq_readdata;
+wire accessing_rxeqctrl;
+wire accessing_rxdcgain;
+wire accessing_vod;
+wire accessing_preemph1t;
+wire accessing_preemph0t;
+wire accessing_preemph2t;
+
+// Implement waitrequest to match previous implementation
+altera_wait_generate wait_gen(
+ .rst(reset),
+ .clk(reconfig_clk),
+ .launch_signal(analog_reconfig_read),
+ .wait_req(analog_reconfig_waitrequest)
+);
+
+// synopsys translate_off
+initial begin
+ state <= 3'b000;
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ master_writedata <= 16'b0;
+ master_addr <= 5'b0;
+ status_reg <= 2'b0;
+ control_reg <= 2'b0;
+ data_reg <= 16'b0;
+ needs_second_access <= 1'b0;
+ do_read_before_write <= 1'b0;
+ addr_offset <= 5'b0;
+ set_addr <= 1'b0;
+ needs_second_write_access <= 1'b0;
+ have_mutex <= 0;
+ req_and_use_mutex <= 0;
+ do_read_phys_chnl <= 0;
+ do_write_chnl_addr <= 0;
+ logical_chnl_addr_updated <= 0;
+end
+// synopsys translate_on
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset)
+ begin
+ state <= IDLE;
+ analog_reconfig_readdata[31:0] <= 32'b0;
+ analog_reconfig_done <= 1'b0;
+ status_reg <= 2'b0;
+ control_reg <= 2'b0;
+ needs_second_access <= 1'b0;
+ needs_second_write_access <= 1'b0;
+ set_addr <= 1'b0;
+ do_read_before_write <= 1'b0;
+ data_reg <= 16'b0;
+ have_mutex <= 0;
+ req_and_use_mutex <= 0;
+ do_read_phys_chnl <= 0;
+ do_write_chnl_addr <= 0;
+ logical_chnl_addr_updated <= 0;
+ end
+ else begin
+ have_mutex <= mutex_grant;
+ if (analog_reconfig_read == 1'b1) // allow status read during GX read
+ begin
+ if (analog_reconfig_address == 3'b000) // logical channel address
+ analog_reconfig_readdata <= {{16{1'b0}}, chnl_addr_reg};
+ else if (analog_reconfig_address == 3'b001) // physical channel address
+ analog_reconfig_readdata <= {{20{1'b0}}, phys_chnl_addr_reg};
+ else if (analog_reconfig_address == 3'b010) // status
+ analog_reconfig_readdata <= {{22{1'b0}}, status_reg[1:0], {8{1'b0}}};
+ else if (analog_reconfig_address == 3'b011) // TX/RX offset
+ analog_reconfig_readdata <= {{16{1'b0}}, addr_offset};
+ else if (analog_reconfig_address == 3'b100) // previously read data
+ analog_reconfig_readdata <= {{16{1'b0}}, data_reg};
+ else
+ analog_reconfig_readdata <= {32{1'b0}};
+ end
+ case (state)
+ IDLE: begin
+ needs_second_access <= 1'b0;
+ if (analog_reconfig_address == 3'b0)
+ begin
+ if (analog_reconfig_write == 1'b1)
+ begin
+ chnl_addr_reg <= {{4{1'b0}},analog_reconfig_writedata[11:0]}; // write logical_ch_addr
+ logical_chnl_addr_updated <= 1'b1;
+ end
+ end
+ else if (analog_reconfig_write == 1'b1 && analog_reconfig_address == 3'b011) // addr_offset
+ begin
+ addr_offset <= analog_reconfig_writedata[4:0];
+ end
+ else if (analog_reconfig_address == 3'b100) // DPRIO write data
+ begin
+ if (analog_reconfig_write == 1'b1)
+ data_reg[15:0] <= analog_reconfig_writedata[15:0];
+ end
+ else if (analog_reconfig_read == 1'b1 && analog_reconfig_address == 3'b001) // physical chnl
+ begin
+ if (logical_chnl_addr_updated == 1'b1) // if logical chnl addr was updated from the last time we read the phys addr, go do the read again
+ begin
+ status_reg <= {1'b0, 1'b1}; //set busy bit
+ if (have_mutex)
+ begin
+ state <= WRITE_CHL_ADDR;
+ do_read_phys_chnl <= 1;
+ end
+ else begin
+ state <= READ_IDLE;
+ req_and_use_mutex <= 1'b1;
+ do_write_chnl_addr <= 1'b1;
+ do_read_phys_chnl <= 1;
+ end
+ logical_chnl_addr_updated <= 1'b0;
+ end
+ end
+ else if (analog_reconfig_address == 3'b010 && analog_reconfig_write == 1'b1) // control reg bit 1 rd, bit 0 wr
+ begin
+ status_reg <= {1'b0, 1'b1}; // set busy bit
+ control_reg <= analog_reconfig_writedata[1:0];
+ if (analog_reconfig_writedata[0] == 1'b1)
+ do_read_before_write <= 1'b1;
+ if (have_mutex)
+ begin
+ state <= WRITE_CHL_ADDR;
+ end
+ else begin
+ state <= READ_IDLE;
+ req_and_use_mutex <= 1'b1;
+ do_write_chnl_addr <= 1'b1;
+ status_reg <= {1'b0, 1'b1}; // set busy bit
+ end
+ end
+ else if (analog_reconfig_address > 3'b100 && analog_reconfig_write == 1'b1) //
+ begin
+ // synopsys translate_off
+ $display ("Illegal operation to reserved address %h", analog_reconfig_address);
+ $display ("Time: %0t Instance: %m", $time);
+ // synopsys translate_on
+ end
+ else if (have_mutex == 1'b1)
+ begin
+ // holding the mutex in idle state, release it
+ req_and_use_mutex <= 1'b0;
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ end
+ end
+ WRITE_CHL_ADDR: begin
+ master_addr <= 5'b00100;
+ master_write <= 1'b1;
+ master_writedata <= chnl_addr_reg;
+ state <= READ_OR_SET_INFO;
+ end
+ READ_OR_SET_INFO: begin
+ if (analog_reconfig_waitrequest_from_base == 1'b1)
+ state <= READ_OR_SET_INFO;
+ else
+ begin
+ master_write <= 1'b0;
+ if (do_read_phys_chnl)
+ begin
+ state <= READ_FROM_BASIC;
+ // do_read_phys_chnl = 0;
+ end
+ else begin
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ master_read <= 0;
+ end
+ end
+ end
+ GET_MUTEX:
+ begin
+ if (have_mutex == 1'b1)
+ begin
+ if (do_write_chnl_addr == 1'b1)
+ state <= WRITE_CHL_ADDR;
+ else
+ state <= READ_OR_SET_INFO;
+ end
+ else
+ begin
+ state <= GET_MUTEX;
+ end
+ end
+ READ_FROM_BASIC: begin
+ if (analog_reconfig_waitrequest == 1'b0)
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ if (analog_reconfig_irq_from_base == 1'b1) // start read access to data reg. of base_reconfig
+ begin
+ master_addr <= 5'b10100;
+ end
+ else begin
+ master_addr <= 5'b01000;
+ end
+ state <= READ_IDLE;
+ end
+ else
+ begin
+ state <= READ_FROM_BASIC;
+ end
+ end
+ READ_IDLE: begin
+ if (analog_reconfig_waitrequest == 1'b0)
+ begin
+ if (have_mutex)
+ state <= READ_FROM_BASIC_DONE;
+ else
+ begin
+ state <= GET_MUTEX;
+ end
+ end
+ else
+ begin
+ state <= READ_IDLE;
+ end
+ end
+ READ_FROM_BASIC_DONE: begin
+ if (analog_reconfig_waitrequest == 1'b0)
+ begin
+ master_read <= 1'b0;
+ if (do_read_phys_chnl)
+ begin
+ do_read_phys_chnl <= 0;
+ phys_chnl_addr_reg <= mutex_acq_readdata[11:0];
+ if (mutex_acq_readdata[11:0] == ILLEGAL_PHYSICAL_CHNL)
+ begin
+ //set error bit
+ status_reg <= {1'b1, 1'b0};
+ // error message for sim
+ //$display();
+ //$display();
+ end
+ else begin
+ // unset busy bit
+ status_reg <= 2'b0;
+ end
+ state <= IDLE;
+ end
+ else if (accessing_vod)
+ begin
+
+ // This is for Stratix IV only
+ //////////////////////////////////////////////////
+ //Port | DPRIO CRAM bit value
+ //2..0 | 2..0
+ //////////////////////////////////////////////////
+ //000 | 000
+ //001 | 001
+ //010 | 010
+ //011 | 110
+ //100 | 011
+ //101 | 111
+ //110 | 100
+ //111 | 101
+ /////////////////////////////////////////////////
+ if (control_reg[0] == 1'b1) // this was a write cycle to begin with
+ begin
+ master_writedata[31:16] <= {16{1'b0}};
+ master_writedata[15:13] <= {(data_reg[2] & data_reg[1]) | (data_reg[2] & data_reg[0]) | (data_reg[1] & data_reg[0]), data_reg[2] ^ data_reg[1], (~data_reg[1] & data_reg[0]) | (data_reg[2] & data_reg[0]) | (data_reg[2] & ~data_reg[1])};
+ master_writedata[12:0] <= mutex_acq_readdata[12:0];
+ master_addr <= 5'b10100;
+ master_write <= 1'b1;
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ end
+ else begin
+ data_reg <= {{13{1'b0}}, (mutex_acq_readdata[15] & ~mutex_acq_readdata[14]) | (mutex_acq_readdata[14] & mutex_acq_readdata[13]), (mutex_acq_readdata[15] & ~mutex_acq_readdata[14]) | (mutex_acq_readdata[14] & ~mutex_acq_readdata[13]), (~mutex_acq_readdata[14] & mutex_acq_readdata[13]) | (mutex_acq_readdata[15] & mutex_acq_readdata[14])};
+ // unset busy bit
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ else if (accessing_rxdcgain)
+ begin
+ // This is for Stratix IV only
+ //////////////////////////////////////////////////
+ //Port | DRIO CRAM bit value
+ //2..0 | 10..7
+ //////////////////////////////////////////////////
+ //000 | 0000
+ //001 | 0001
+ //010 | 0011
+ //011 | 0111
+ //100 | 1111
+ //Others | Assume to be 1's
+ /////////////////////////////////////////////////
+
+ // This is for Arria II only
+ //////////////////////////////////////////////////
+ //Port | DRIO CRAM bit value
+ //1..0 | 10..7
+ //////////////////////////////////////////////////
+ //00 | 0000
+ //01 | 0001
+ //10 | 0011
+ //Others | Assume to be 1's
+ /////////////////////////////////////////////////
+ if (control_reg[0] == 1'b1)
+ begin
+ if ((device_family == "Stratix IV") || (device_family == "HardCopy IV"))
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:11], data_reg[2], data_reg[1] & data_reg[0] | data_reg[2], data_reg[2] | data_reg[1], data_reg[2] | data_reg[1] | data_reg[0], mutex_acq_readdata[6:0]};
+ else
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:11], 1'b0, 1'b0, data_reg[1], data_reg[1] | data_reg[0], mutex_acq_readdata[6:0]};
+ master_addr <= 5'b10100;
+ master_write <= 1'b1;
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ end
+ else begin
+ if ((device_family == "Stratix IV") || (device_family == "HardCopy IV"))
+ data_reg <= {{13{1'b0}}, mutex_acq_readdata[10], ~mutex_acq_readdata[10] & mutex_acq_readdata[8], mutex_acq_readdata[10] ^ mutex_acq_readdata[9] ^ mutex_acq_readdata[8] ^ mutex_acq_readdata[7]};
+ else
+ data_reg <= {{14{1'b0}}, mutex_acq_readdata[8], mutex_acq_readdata[7] ^ mutex_acq_readdata[8]};
+ // unset busy bit
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ else if (accessing_rxeqctrl) // encode/decode rx_eqctrl
+ begin
+ ////////////////////////////////////////
+ // Wiz A B C D V
+ // 3210 EDC BA9 876 543 210
+ // 0000 000 000 000 000 000
+ // L0 0001 011 000 000 000 111
+ // L1 0010 100 000 000 000 000
+ // L2 0011 111 000 000 000 000
+ // L3 0100 111 000 000 000 111
+ // L4 0101 101 101 000 000 000
+ // M0 0110 111 111 000 000 000
+ // M1 0111 111 111 000 000 100
+ // M2 1000 111 111 000 000 111
+ // M3 1001 111 111 111 000 001
+ // M4 1010 111 111 111 000 100
+ // H0 1011 111 111 111 111 000
+ // H1 1100 111 111 111 111 001
+ // H2 1101 111 111 111 111 100
+ // H3 1110 111 111 111 111 110
+ // H4 1111 111 111 111 111 111
+ ////////////////////////////////////////
+ if (control_reg[0] == 1'b1)
+ begin
+ master_writedata[31:16] <= 0;
+ master_writedata[15] <= mutex_acq_readdata[15];
+ if (data_reg[3:0] > 4'b1010)
+ master_writedata[14:3] <= {12{1'b1}};
+ else if (data_reg[3:0] > 4'b0110)
+ master_writedata[14:3] <= {{3{1'b0}}, {9{1'b1}}};
+ else if (data_reg[3:0] > 4'b0011)
+ master_writedata[14:3] <= {{6{1'b0}}, {6{1'b1}}};
+ else if (data_reg[3:0] > 4'b0)
+ master_writedata[14:3] <= {{9{1'b0}}, {3{1'b1}}};
+ else
+ master_writedata[14:3] <= {12{1'b0}};
+ master_writedata[2] <= (data_reg[1] & ~data_reg[0]) | (~data_reg[3] & ~data_reg[2] & data_reg[1]) | (data_reg[2] & ~data_reg[1] & data_reg[0] | (data_reg[3] & data_reg[2] & data_reg[0]) | (data_reg[3] & ~data_reg[2] & ~data_reg[1]));
+ master_writedata[1] <= ( data_reg[1] & (data_reg[0] ^ (data_reg[2] ^ data_reg[3]))) | (data_reg[3] & data_reg[2] & ~data_reg[1] & ~data_reg[0]);
+ master_writedata[0] <= (~(data_reg[3] ^ data_reg[2]) & data_reg[1] & data_reg[0]) | (data_reg[2] & data_reg[1] & ~data_reg[0]) | (data_reg[3] & data_reg[1] & ~data_reg[0]) | (data_reg[3] & data_reg[2] & ~data_reg[0]) | (data_reg[3] & ~data_reg[2] & ~data_reg[1] & data_reg[0]);
+
+ master_addr <= 5'b10100;
+ master_write <= 1'b1;
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ end
+ else begin
+ if (mutex_acq_readdata[14:12] == 3'b111) // > 10
+ data_reg <= {{12{1'b0}}, 1'b1, (mutex_acq_readdata[1] & mutex_acq_readdata[0]) | (mutex_acq_readdata[2] & ~mutex_acq_readdata[1]), (mutex_acq_readdata[2] & mutex_acq_readdata[0]) | (~mutex_acq_readdata[0] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[2]), (~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]) | (mutex_acq_readdata[2] & mutex_acq_readdata[1] & mutex_acq_readdata[0])};
+ else if (mutex_acq_readdata[11:9] == 3'b111) // > 6 only
+ data_reg <= {{12{1'b0}}, mutex_acq_readdata[2], ~mutex_acq_readdata[2], (mutex_acq_readdata[2] & mutex_acq_readdata[1] & mutex_acq_readdata[0]) | (~mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]), (~mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]) | (mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & mutex_acq_readdata[0])};
+ else if (mutex_acq_readdata[8:6] == 3'b111) // > 3 only
+ data_reg <= {{12{1'b0}}, 1'b0, 1'b1, mutex_acq_readdata[2] & mutex_acq_readdata[1] & mutex_acq_readdata[0], mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]};
+ else if (mutex_acq_readdata[5:3] == 3'b111) // > 0 only
+ data_reg <= {{12{1'b0}}, {2{1'b0}}, (mutex_acq_readdata[2] & mutex_acq_readdata[1] & mutex_acq_readdata[0]) | (mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]), (mutex_acq_readdata[2] & mutex_acq_readdata[1] & mutex_acq_readdata[0]) | (~mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]) };
+ else
+ data_reg <= {16{1'b0}};
+
+ // unset busy bit
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ else if (accessing_preemph1t)
+ begin
+ // This is for Arria II only
+ //////////////////////////////////////////////////
+ //Port | DRIO CRAM bit value
+ //4..0 | 15..11
+ //////////////////////////////////////////////////
+ //00000 | 00000
+ //00001 | 00001
+ //00010 | 00101
+ //00011 | 01001
+ //00100 | 01101
+ //00101 | 10001
+ //00110 | 10101
+ //Others | Assume to be 1's
+ /////////////////////////////////////////////////
+ if (control_reg[0] == 1'b1)
+ begin
+ if (device_family == "Stratix IV")
+ master_writedata <= {{16{1'b0}}, data_reg[4:0], mutex_acq_readdata[10:0]};
+ else
+ master_writedata <= {{16{1'b0}}, data_reg[2] & data_reg[1] ^ data_reg[0], data_reg[2] & ~data_reg[1] & ~data_reg[0] | (data_reg[1] & data_reg[0]), (data_reg[2] | data_reg[1]) & ~data_reg[0], 1'b0, (data_reg[2] | data_reg[1] | data_reg[0]), mutex_acq_readdata[10:0]};
+ master_addr <= 5'b10100;
+ master_write <= 1'b1;
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ end
+ else begin
+ if (device_family == "Stratix IV")
+ data_reg <= {{11{1'b0}}, mutex_acq_readdata[15:11]};
+ else
+ data_reg <= {{11{1'b0}}, 1'b0, 1'b0, mutex_acq_readdata[15] | (mutex_acq_readdata[14] & mutex_acq_readdata[13]), mutex_acq_readdata[14] ^ mutex_acq_readdata[13], mutex_acq_readdata[13] ^ mutex_acq_readdata[11]};
+ // unset busy bit
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ else if (accessing_preemph0t || accessing_preemph2t)
+ begin
+ if (control_reg[0] == 1'b1)
+ begin
+ if (accessing_preemph0t)
+ begin
+ if (needs_second_write_access)
+ begin
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:5], ~data_reg[4], mutex_acq_readdata[3:0]};
+ end
+ else begin
+ if (data_reg[4] == 1'b0)
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:4], 4'b0000 - data_reg[3:0]};
+ else
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:4], data_reg[3:0]};
+ end
+ end
+ else if (accessing_preemph2t)
+ begin
+ if (needs_second_write_access)
+ begin
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:4], ~data_reg[4], mutex_acq_readdata[2:0]};
+ end
+ else begin
+ if (data_reg[4] == 1'b0)
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:8], 4'b0000 - data_reg[3:0], mutex_acq_readdata[3:0]};
+ else
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:8], data_reg[3:0], mutex_acq_readdata[3:0]};
+ end
+ end
+ master_addr <= 5'b10100;
+ master_write <= 1'b1;
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ end
+ else begin
+ if (needs_second_access)
+ begin
+ data_reg <= mutex_acq_readdata[15:0];
+ master_write <= 1'b1; // start access for INV bit
+ master_addr <= 5'b10000;
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {8{1'b0}}, 2'b11}; // DPRIO register address
+ state <= SET_INFO_ON_BASIC;
+ needs_second_access <= 1'b0;
+ end
+ else begin
+ if (accessing_preemph0t)
+ begin
+ if (mutex_acq_readdata[4] == 1'b1)
+ data_reg <= {{11{1'b0}}, 1'b0, 4'b0000 - data_reg[3:0]};
+ else
+ data_reg <= {{11{1'b0}}, 1'b1, data_reg[3:0]};
+ end
+ else begin
+ if (mutex_acq_readdata[3] == 1'b1)
+ data_reg <= {{11{1'b0}}, 1'b0, 4'b0000 - data_reg[7:4]};
+ else
+ data_reg <= {{11{1'b0}}, 1'b1, data_reg[7:4]};
+ end
+ // unset busy
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ end
+ else begin // dont know what the operation is
+ analog_reconfig_readdata <= mutex_acq_readdata;
+ // unset busy bit
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ else
+ begin
+ state <= READ_FROM_BASIC_DONE;
+ end
+ end
+ SET_INFO_ON_BASIC: begin
+ if (set_addr)
+ begin
+ master_addr <= 5'b10000;
+ master_write <= 1'b1;
+ if (accessing_vod)
+ begin
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {10{1'b0}}};
+ end
+ else if (accessing_preemph1t)
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {8{1'b0}}, 2'b01};
+ else if (accessing_rxdcgain)
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b11, 10'b0};
+ else if (accessing_rxeqctrl)
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b11, 10'b0000001011};
+ else if (accessing_preemph0t || accessing_preemph2t)
+ begin
+ if (needs_second_write_access)
+ begin
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {8{1'b0}}, 2'b11};
+ end
+ else
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {8{1'b0}}, 2'b10};
+ if (control_reg[1] == 1'b1) // pure read cycle
+ needs_second_access <= 1'b1;
+ end
+ set_addr <= 1'b0;
+ end
+ else if (control_reg[1] == 1'b1 || (control_reg[0] == 1'b1 & do_read_before_write)) // read
+ begin
+ master_addr <= 5'b01100;
+ master_write <= 1'b1;
+ master_writedata <= {{16{1'b0}}, {14{1'b0}}, 2'b10}; // initiate read first
+ state <= READ_FROM_GXB;
+ do_read_before_write <= 1'b0;
+ end
+ else if (control_reg[0] == 1'b1) // actual write
+ begin
+ master_write <= 1'b1;
+ master_addr <= 5'b01100;
+ master_writedata <= {{16{1'b0}}, {14{1'b0}}, 2'b01}; // issue write to basic's control_reg to start WRITE
+ state <= WRITE_TO_GXB;
+ end
+ end
+ READ_FROM_GXB: begin
+ master_write <= 1'b0;
+ if (analog_reconfig_irq_from_base == 1'b1)
+ state <= READ_FROM_BASIC;
+ end
+ WRITE_TO_GXB: begin
+ master_write <= 1'b0;
+ if (analog_reconfig_irq_from_base == 1'b1)
+ begin
+ //start access to clear interrupt control reg. on slave
+ master_addr <= 5'b01100;
+ master_write <= 1'b1;
+ master_writedata <= {{16{1'b0}}, {13{1'b0}}, 3'b000};
+ state <= WRITE_DONE;
+ end
+ end
+ WRITE_DONE: begin
+ master_write <= 1'b0;
+ if (analog_reconfig_irq_from_base == 1'b1)
+ begin
+ if ((accessing_preemph0t || accessing_preemph2t) & (!needs_second_write_access))
+ begin
+ needs_second_write_access <= 1'b1;
+ do_read_before_write <= 1'b1;
+ master_write <= 1'b1;
+ master_addr <= 5'b10000;
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {8{1'b0}}, 2'b11}; // DPRIO register address for INV
+ state <= SET_INFO_ON_BASIC;
+ end
+ else begin
+ needs_second_write_access <= 1'b0;
+ status_reg <= {1'b0, 1'b0}; // unset busy
+ analog_reconfig_done <= 1'b1; // send INTERRUPT
+ state <= IDLE;
+ end
+ end
+ end
+ default:begin
+ state <= IDLE;
+ end
+ endcase
+ end
+// prev_state <= state;
+end
+
+assign accessing_vod = (addr_offset[4:0] == 5'b0);
+assign accessing_preemph0t = (addr_offset[4:0] == 5'b00001);
+assign accessing_preemph1t = (addr_offset[4:0] == 5'b00010);
+assign accessing_preemph2t = (addr_offset[4:0] == 5'b00011);
+assign accessing_rxdcgain = (addr_offset[4] == 1'b1 && addr_offset[3:0] == 4'b0000);
+assign accessing_rxeqctrl = (addr_offset[4] == 1'b1 && addr_offset[3:0] == 4'b0001);
+
+//assign analog_reconfig_address_base = master_addr;
+//assign analog_reconfig_write_base = master_write;
+//assign analog_reconfig_read_base = master_read;
+//assign analog_reconfig_writedata_base = master_writedata;
+
+
+ alt_mutex_acq #(
+ .mutex_wait_time(101),
+ .addr_width(5),
+ .data_width(32)
+ )
+ mutex_inst (
+ .clk(reconfig_clk),
+ .reset(reset),
+ // inputs to the base that should be routed through the mutex
+ .address(master_addr),
+ .writedata(master_writedata),
+ .write(master_write),
+ .read(master_read),
+ // output from the mutex which is processed form of output from base
+ .waitrequest(mutex_acq_waitrequest),
+ .readdata(mutex_acq_readdata),
+
+
+ // outputs from mutex to be routed to the base
+ .master_address(analog_reconfig_address_base),
+ .master_writedata(analog_reconfig_writedata_base),
+ .master_write(analog_reconfig_write_base),
+ .master_read(analog_reconfig_read_base),
+
+ // these ports are from the base routed to the mutex
+ .master_waitrequest(analog_reconfig_waitrequest_from_base),
+ .master_readdata(analog_reconfig_readdata_base), // from MM
+
+ //request signal to the mutex should be kept high as long as the mutex is being used
+ .mutex_req(req_and_use_mutex),
+ // output from mutex indicates whether you have mutex or not
+ .mutex_grant(mutex_grant)
+ );
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_basic_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_basic_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..2c4f79b384db04a1ab6911dc33951886c61d0f08
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_basic_tgx.v
@@ -0,0 +1,367 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+(* ALTERA_ATTRIBUTE = {"{-to address_pres_reg[11]} DPRIO_CHANNEL_NUM=11;{-to address_pres_reg[10]} DPRIO_CHANNEL_NUM=10;{-to address_pres_reg[9]} DPRIO_CHANNEL_NUM=9;{-to address_pres_reg[8]} DPRIO_CHANNEL_NUM=8;{-to address_pres_reg[7]} DPRIO_CHANNEL_NUM=7;{-to address_pres_reg[6]} DPRIO_CHANNEL_NUM=6;{-to address_pres_reg[5]} DPRIO_CHANNEL_NUM=5;{-to address_pres_reg[4]} DPRIO_CHANNEL_NUM=4;{-to address_pres_reg[3]} DPRIO_CHANNEL_NUM=3;{-to address_pres_reg[2]} DPRIO_CHANNEL_NUM=2;{-to address_pres_reg[1]} DPRIO_CHANNEL_NUM=1;{-to address_pres_reg[0]} DPRIO_CHANNEL_NUM=0; disable_da_rule=\"S102,R102\""} *)
+module alt_xcvr_reconfig_basic_tgx
+#( parameter number_of_reconfig_interfaces = 1
+ )
+(
+ // avalon clock interface
+ input wire reconfig_clk,
+ input wire reset,
+
+ // avalon MM
+ input wire basic_reconfig_write,
+ input wire basic_reconfig_read,
+ input wire [31:0] basic_reconfig_writedata,
+ input wire [2:0] basic_reconfig_address, // address to MM described below
+
+ output reg [31:0] basic_reconfig_readdata, // reconfig_fromgxb_data
+ output wire basic_reconfig_waitrequest,
+
+ // avalon MM
+// output wire reconfig_write_base,
+// output wire reconfig_read_base,
+// output wire [31:0] reconfig_writedata_base,
+// output wire [4:0] reconfig_address_base, // address to MM described below
+
+// input wire [31:0] reconfig_readdata_base, // reconfig_fromgxb_data
+// input wire reconfig_waitrequest_from_base,
+
+
+ // avalon ST interface
+ input wire [number_of_reconfig_interfaces*17 - 1 : 0] basic_reconfig_fromgxb_data, // dprioout, testbus from altgx : (17+4 bits/quad)
+ input wire [number_of_reconfig_interfaces*8 - 1 : 0] aeq_fromgxb_data, // for ADCE dprio
+ output wire [3:0] basic_reconfig_togxb_data, // busy, dprioin, dprioload, dpriodisable and aeq to altgx
+ output reg [number_of_reconfig_interfaces*24 - 1 : 0] aeq_togxb_data, // for ADCE
+ output reg [number_of_reconfig_interfaces*16 - 1 : 0] testbus_data,
+
+ output reg basic_reconfig_irq // interrupt to Master
+);
+
+//assign reconfig_write_base = 1'b0;
+//assign reconfig_read_base = 1'b0;
+//assign reconfig_writedata_base = 32'd0;
+//assign reconfig_address_base = 5'd0;
+
+
+// Memeory Map for register indirection
+// addr wr/rd description
+// ------------------------------------------------------
+// 0 wr/rd mutex : bit[0]
+// 1 wr/rd logical_ch_addr (10 bits)
+// 2 rd physical_chnl_map
+// 3 rd/wr status/control -- bit 0 busy/bit 1 read, bit 0 write, bit 3 = absolute addressing
+// 4 wr/rd DPRIO addr_offset
+// 5 wr/rd DPRIO data
+// 6 rd/wr adce_standby, adce_capture, testbussel : bit 7 -- adcedone, bit 6 -- adcetestbus, bits 5,4 -- adce, 3 to 0 -- bussel
+// 7 rd/wr offset cancellation busy output to GX bit 0
+
+//local parameters
+localparam quad_address_width = 9;
+localparam IDLE_STATE = 2'b00;
+localparam WRITE_STATE = 2'b01;
+localparam READ_STATE = 2'b10;
+
+
+(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON"} *)
+reg [11:0] address_pres_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [11:0] logical_channel_addr_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [14:0] dprio_table_addr_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] pma_pcs_id_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg dprio_busy_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] data_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [5:0] testbussel;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] adce_testdata;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] control_reg;
+// mutex
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg mutex_value;
+//reg [15:0] mutex_owner;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [10:0] mutex_timeout_cntr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg offset_cancellation_busy;
+
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg basic_reconfig_absolute_addressing;
+
+
+wire [quad_address_width-1:0] quad_address;
+wire [quad_address_width-1:0] dprio_quad_address;
+
+wire busy_state;
+wire [15:0] dprio_address;
+wire dprio_busy;
+wire [15:0] dprio_datain;
+wire [15:0] dprio_dataout;
+wire dprio_dprioout;
+wire dprio_rden;
+wire dprio_pulse;
+wire rd_pulse;
+wire read_done;
+wire read_word_done;
+wire reset_system;
+wire dprio_wren;
+wire write_done;
+wire wr_pulse;
+wire read_data_valid;
+wire write_word_done;
+
+integer i,j;
+
+
+assign basic_reconfig_waitrequest = 1'b0;
+
+// synopsys translate_off
+initial
+begin
+ state = 2'b00;
+ basic_reconfig_irq = 1'b0;
+ logical_channel_addr_reg = 12'b0;
+ testbussel = 0;
+ control_reg = 0;
+ mutex_value = 0;
+ mutex_timeout_cntr = 0;
+ offset_cancellation_busy = 0;
+ data_reg = 16'h0000;
+ dprio_table_addr_reg = 15'h0000;
+ pma_pcs_id_reg = 2'b00;
+
+end
+// synopsys translate_on
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset === 1'b1)
+ adce_testdata <= 0;
+ else begin
+ for (i=0; i<=1; i=i+1)
+ begin
+ adce_testdata[i] <= aeq_fromgxb_data[(logical_channel_addr_reg) + i];
+ end
+ end
+end
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset === 1'b1)
+ begin
+ state <= IDLE_STATE;
+ basic_reconfig_readdata <= 16'b0;
+ basic_reconfig_irq <= 1'b0;
+ testbussel <= 0;
+ control_reg <= 0;
+ // mutex registers
+ mutex_value <= 0;
+ mutex_timeout_cntr <= 0;
+ end
+ else begin
+ // mutex
+ if (basic_reconfig_address == 3'b0)
+ begin
+ //read first only update the mutex_value
+ if (basic_reconfig_read == 1'b1)
+ begin
+ basic_reconfig_readdata <= {{31{1'b0}}, mutex_value};
+ // if (basic_reconfig_waitrequest == 1'b0)
+ if (mutex_value == 1'b0) // mutex is free, so grant access
+ mutex_value <= 1'b1;
+ end
+ else if (basic_reconfig_write == 1'b1)
+ begin
+ mutex_value <= 0;
+ end
+ end
+
+ case (state)
+ IDLE_STATE: begin
+ if (basic_reconfig_write == 1'b1)
+ begin
+ mutex_timeout_cntr <= 0; // reset the mutex_timeout counter
+ if (basic_reconfig_address == 3'b001)
+ begin
+ logical_channel_addr_reg <= basic_reconfig_writedata[11:0];
+ address_pres_reg <= {basic_reconfig_writedata[10:2], 1'b0, basic_reconfig_writedata[1:0]}; //chestan
+ end
+ else if (basic_reconfig_address == 3'b100)
+ begin
+ dprio_table_addr_reg <= basic_reconfig_writedata[14:0];
+ pma_pcs_id_reg <= basic_reconfig_writedata[11:10];
+ end
+ else if (basic_reconfig_address == 3'b011) // control reg
+ begin
+ if (basic_reconfig_writedata[0] == 1'b1) // write
+ begin
+ state <= WRITE_STATE;
+ control_reg <= 2'b01;
+ end
+ else if (basic_reconfig_writedata[1] == 1'b1) // read
+ begin
+ state <= READ_STATE;
+ control_reg <= 2'b10;
+ end
+ if (basic_reconfig_writedata[2] == 1'b0) begin
+ basic_reconfig_irq <= 1'b0; // clear WRITE interrupt
+ end
+ basic_reconfig_absolute_addressing <= basic_reconfig_writedata[3]; // use the full address from dprio_addr, not the derived address
+ end
+ else if (basic_reconfig_address == 3'b101) // data
+ begin
+ data_reg <= basic_reconfig_writedata[15:0];
+ end
+ else if (basic_reconfig_address == 3'b110) // testbussel
+ testbussel <= basic_reconfig_writedata[5:0];
+ else if (basic_reconfig_address == 3'b111)
+ offset_cancellation_busy <= basic_reconfig_writedata[0];
+ begin
+ end
+ end
+ else if (basic_reconfig_read == 1'b1)
+ begin
+ if (basic_reconfig_address == 3'b001)
+ basic_reconfig_readdata <= {{20{1'b0}}, logical_channel_addr_reg};
+ else if (basic_reconfig_address == 3'b010) // physical chnl
+ basic_reconfig_readdata <= {{21{1'b0}}, address_pres_reg[11:3], address_pres_reg[1:0]}; // check this
+ else if (basic_reconfig_address == 3'b011) // status
+ basic_reconfig_readdata <= {{23{1'b0}}, busy_state, {5{1'b0}}, basic_reconfig_irq, control_reg};
+ else if (basic_reconfig_address == 3'b100)
+ basic_reconfig_readdata <= {{20{1'b0}}, pma_pcs_id_reg, dprio_table_addr_reg};
+ else if (basic_reconfig_address == 3'b101) // DPRIO readdata
+ begin
+ basic_reconfig_readdata <= {{16{1'b0}}, data_reg};
+ basic_reconfig_irq <= 1'b0; // clear READ interrupt
+ end
+ else if (basic_reconfig_address == 3'b110)
+ basic_reconfig_readdata <= {{24{1'b0}}, adce_testdata, testbussel};
+ else if (basic_reconfig_address == 3'b111) // testbusdata
+ basic_reconfig_readdata <= {{31{1'b0}}, offset_cancellation_busy};
+ if (basic_reconfig_address != 3'b0) // if not reading the mutex val
+ mutex_timeout_cntr <= 0; // reset the mutex counter
+ end
+ else if (mutex_value == 1'b1) // if mutex was granted to someone
+ if (mutex_timeout_cntr == 10'd1000) // and they didnt do anything for 1000 cycles
+ begin
+ mutex_value <= 1'b0; // reset the mutex and give it to the next person
+ mutex_timeout_cntr <= 0;
+ end
+ else
+ mutex_timeout_cntr <= mutex_timeout_cntr[9:0] + 10'b1; // count up the timer from the last access
+ end
+ WRITE_STATE: begin
+ if (write_done)
+ begin
+ state <= IDLE_STATE;
+ basic_reconfig_irq <= 1'b1; // send interrupt to master
+ end
+ // allow status_register read here
+ if (basic_reconfig_read == 1'b1 && basic_reconfig_address == 3'b011)
+ basic_reconfig_readdata <= {{23{1'b0}}, busy_state, {5{1'b0}}, basic_reconfig_irq, control_reg};
+ end
+ READ_STATE: begin
+ if (read_word_done == 1'b1)
+ begin
+ data_reg <= dprio_dataout;
+ basic_reconfig_irq <= 1'b1; // send interrupt
+ state <= IDLE_STATE;
+ end
+ // allow status_register read here
+ if (basic_reconfig_read == 1'b1 && basic_reconfig_address == 3'b011)
+ basic_reconfig_readdata <= {{23{1'b0}}, busy_state, {5{1'b0}}, basic_reconfig_irq, control_reg};
+ end
+ default: begin
+ state <= IDLE_STATE;
+ end
+ endcase
+ end
+end
+
+// synopsys translate_off
+initial address_pres_reg = 0;
+// synopsys translate_on
+
+assign quad_address = logical_channel_addr_reg[10:2];
+assign dprio_address[15:0] = basic_reconfig_absolute_addressing ? {1'b0, dprio_table_addr_reg[14:0]} : {1'b0, address_pres_reg[2], address_pres_reg[1:0], pma_pcs_id_reg[1:0], dprio_table_addr_reg[9:0]};
+assign dprio_quad_address = address_pres_reg[11:3];
+assign dprio_dprioout = basic_reconfig_fromgxb_data[quad_address * 17];
+assign dprio_datain = data_reg;
+assign dprio_rden = rd_pulse;
+assign rd_pulse = (state == READ_STATE) & ~dprio_pulse & ~read_done;
+assign read_done = read_word_done | reset_system;
+assign read_word_done = (state == READ_STATE) & read_data_valid;
+assign read_data_valid = (state == READ_STATE) & dprio_pulse;
+assign dprio_wren = wr_pulse;
+assign wr_pulse = (state == WRITE_STATE) & ~dprio_pulse & ~write_done;
+assign write_done = write_word_done | reset_system;
+assign write_word_done = (state == WRITE_STATE) & dprio_pulse;
+assign reset_system = reset;
+assign busy_state = (state == READ_STATE) | (state == WRITE_STATE);
+
+// synopsys translate_off
+initial dprio_busy_reg = 0;
+// synopsys translate_on
+
+always @(posedge reconfig_clk) dprio_busy_reg <= dprio_busy;
+assign dprio_pulse = (dprio_busy_reg ^ dprio_busy) & (~dprio_busy);
+
+alt_dprio inst_alt_dprio (.dpclk(reconfig_clk),
+ .datain(dprio_datain),
+ .address(dprio_address),
+ .wren(dprio_wren),
+ .rden(dprio_rden),
+// .rdinc(),
+ .wren_data(1'b0),
+ .dprioout(dprio_dprioout), // reconfig_fromgxb_data[0]
+ .quad_address(dprio_quad_address),
+ // outputs
+ .dprioin(basic_reconfig_togxb_data[0]),
+ .dpriodisable(basic_reconfig_togxb_data[1]),
+ .dprioload(basic_reconfig_togxb_data[2]),
+ .dataout(dprio_dataout),
+ .busy(dprio_busy)
+ );
+
+//assign testbus_data = (testbussel == 3'b110) ? basic_reconfig_fromgxb_data : 'b0;
+
+assign basic_reconfig_togxb_data[3] = offset_cancellation_busy;
+
+always @(basic_reconfig_fromgxb_data)
+begin
+ for (i=0; i<number_of_reconfig_interfaces; i=i+1)
+ begin
+ for (j=0; j<= 15; j=j+1)
+ begin
+ testbus_data[(i*16) + j] = basic_reconfig_fromgxb_data[(i*17) + j+1];
+ end
+ end
+end
+
+always @(logical_channel_addr_reg or testbussel)
+begin
+ aeq_togxb_data = {number_of_reconfig_interfaces*24{1'b0}};
+ for (i=0; i<=5; i=i+1)
+ begin
+ aeq_togxb_data[(logical_channel_addr_reg*6) + i] = testbussel[i];
+ end
+end
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_dfe_tgx.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_dfe_tgx.sv
new file mode 100644
index 0000000000000000000000000000000000000000..107fa27aa9d4e7684eaf3ff65891450a40db21ac
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_dfe_tgx.sv
@@ -0,0 +1,502 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_dfe_tgx
+#(
+ parameter device_family = "StratixIV",
+ parameter number_of_reconfig_interfaces = 1
+)
+(
+ input wire reconfig_clk, // this will be the reconfig clk
+ input wire reset,
+
+ //avalon MM slave
+ input wire [2:0] dfe_address, // Check this! fix me!
+ input wire [31:0] dfe_writedata,
+ input wire dfe_write,
+ input wire dfe_read,
+
+ //output MM slave
+ output wire [31:0] dfe_readdata, // from MM
+ output wire dfe_waitrequest, // from MM
+
+ output reg dfe_irq,
+
+ // input from base_reconfig
+ input wire dfe_irq_from_base,
+ input wire dfe_waitrequest_from_base,
+
+ // output to base_reconfig
+ // Avalon MM Master
+ output wire [2:0] dfe_address_base, // 3 bit MM
+ output wire [31:0] dfe_writedata_base,
+ output wire dfe_write_base, // start write to GXB
+ output wire dfe_read_base, // start read from GXB
+
+ // input from base reconfig
+ input wire [31:0] dfe_readdata_base // data from read command
+
+);
+
+//local parameters
+//state
+localparam IDLE_STATE = 4'b0000;
+localparam LOGICAL_ADDRESS_STATE = 4'b0001;
+localparam WRITE_DATA_STATE = 4'b0010;
+localparam CONTROL_STATE = 4'b0011;
+localparam BUSY_STATE = 4'b0100;
+localparam READ_PHY_ADDR_STATE = 4'b0101;
+localparam CHECK_PHY_ADDR_STATE = 4'b0110;
+localparam ADDRESS_OFFSET_STATE = 4'b0111;
+localparam BASE_BUSY_STATE = 4'b1000;
+localparam READ_DATA_STATE = 4'b1001;
+localparam WRITE_DONE_STATE = 4'b1010;
+
+localparam ILLEGAL_PHYSICAL_CHNL = 10'b1111111111;
+wire [4:0] dfe_addr_all; // 5 bit MM
+
+wire mutex_grant;
+wire [31:0] master_read_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [3:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg write_read_control;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_read;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [31:0] master_write_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [2:0] master_address;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg req_and_use_mutex;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg set_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg wait_phy_addr_ready;
+
+wire [4:0] master_address_shifted;
+
+//alt_dfe instantiation
+wire alt_dfe_busy;
+wire [15:0] alt_dfe_dprio_dataout;
+wire alt_dfe_dprio_wren;
+wire alt_dfe_dprio_rden;
+wire [(number_of_reconfig_interfaces*4-1) : 0] alt_dfe_error;
+
+wire [15:0] alt_dfe_dprio_addr;
+wire [8:0] alt_dfe_quad_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [11:0] alt_dfe_remap_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_dfe_dprio_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_dfe_dprio_busy_int;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] alt_dfe_dprio_datain;
+
+function integer CLogB2;
+input integer Depth;
+integer i;
+begin
+i = Depth;
+for(CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1)
+i = i >> 1;
+end
+endfunction
+
+// synopsys translate_off
+initial begin
+ state = 3'b000;
+ alt_dfe_remap_addr = 12'h000;
+ req_and_use_mutex = 1'b0;
+ wait_phy_addr_ready = 1'b0;
+ alt_dfe_dprio_datain = 16'h0000;
+ alt_dfe_dprio_busy = 1'b0;
+ alt_dfe_dprio_busy_int = 1'b0;
+
+ master_write = 1'b0;
+ master_read = 1'b0;
+ master_write_data = {32{1'b0}};
+ master_address = 3'h0;
+
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy = 1'b0; // 1 for assert busy, 0 for deassert busy
+
+ dfe_irq = 1'b0;
+
+end
+// synopsys translate_on
+
+integer count;
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset)
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ master_write_data <= {32{1'b0}};
+ master_address <= 3'h0;
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ req_and_use_mutex <= 1'b0;
+ wait_phy_addr_ready <= 1'b0;
+ alt_dfe_dprio_busy_int<= 1'b0;
+ dfe_irq <= 1'b0;
+ end
+ else begin
+ if(alt_dfe_busy == 1'b0)
+ req_and_use_mutex <= 1'b0;
+ else
+ req_and_use_mutex <= 1'b1;
+
+ case (state)
+ IDLE_STATE:
+ begin
+ dfe_irq <= 1'b0; // reset write/read done flag
+ //reset the signal
+ set_busy <= 1'b0;
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ alt_dfe_remap_addr <= 12'h000;
+
+ //alt_dfe will not assert wren and rden at the same time
+ if((alt_dfe_dprio_wren == 1'b1) || (alt_dfe_dprio_rden == 1'b1))
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(alt_dfe_dprio_wren == 1'b1)
+ write_read_control <= 1'b1; // 1 for write
+ else
+ write_read_control <= 1'b0; // 0 for read
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ else
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ state <= IDLE_STATE;
+ end
+ end
+ LOGICAL_ADDRESS_STATE: //sending channel and quad address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h1;
+ master_write_data <= {{21{1'b0}}, alt_dfe_quad_addr, alt_dfe_dprio_addr[13:12]};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= READ_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ end
+ READ_PHY_ADDR_STATE: //read phsical address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h2;
+ master_read <= 1'b1;
+ master_write <= 1'b0;
+ if (wait_phy_addr_ready == 1'b1)
+ begin
+ wait_phy_addr_ready <= 1'b0;
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ wait_phy_addr_ready <= 1'b1;
+ state <= READ_PHY_ADDR_STATE;
+ //state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_PHY_ADDR_STATE;
+ end
+ end
+ CHECK_PHY_ADDR_STATE: //check physical address correct or not
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ if (master_read_data[9:0] == ILLEGAL_PHYSICAL_CHNL)
+ begin
+ // synopsys translate_off
+ $display ("Illegal physical address: 10'h%h", master_read_data);
+ $display ("Time: %0t Instance: %m", $time);
+ // synopsys translate_on
+ alt_dfe_remap_addr <= 12'hfff;
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ alt_dfe_remap_addr <= master_read_data[11:0];
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ else
+ begin
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ ADDRESS_OFFSET_STATE: // send address offset to alt_dprio
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h4;
+ master_write_data <= {{20{1'b0}}, alt_dfe_dprio_addr[11:0]};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(write_read_control == 1'b1)
+ state <= WRITE_DATA_STATE;
+ else
+ state <= CONTROL_STATE;
+ end
+ else
+ begin
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ WRITE_DATA_STATE:
+ begin
+ master_address <= 3'h5;
+ master_write_data = {{16{1'b0}}, alt_dfe_dprio_dataout};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= CONTROL_STATE;
+ end
+ CONTROL_STATE: // sending write/read command
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h3; // get ready to send control command to alt_dprio
+ master_write_data <= {{29{1'b0}}, (~write_read_control), write_read_control};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ state <= BASE_BUSY_STATE;
+ end
+ else
+ begin
+ state <= CONTROL_STATE;
+ end
+ end
+ BASE_BUSY_STATE: // send busy to reconfig_togxb
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h7; // set offset cancellation busy to reconfig_togxb
+ master_write_data <= {{30{1'b0}}, alt_dfe_busy};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(set_busy == 1'b0)
+ begin
+ set_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ else
+ begin
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= BASE_BUSY_STATE;
+ end
+ end
+ BUSY_STATE: // wait for write done
+ begin
+ if(dfe_irq_from_base == 1'b1)
+ begin
+ alt_dfe_dprio_busy <= 1'b1;
+ if(write_read_control == 1'b0) //read
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_dfe_dprio_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ end
+ WRITE_DONE_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(dfe_irq_from_base == 1'b1)
+ begin
+ if(alt_dfe_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_dfe_dprio_busy_int <= master_read_data[8];
+ alt_dfe_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ else
+ begin
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ master_address <= 3'h3;
+ master_write_data <= {{16{1'b0}}, {16'h0000}}; //acknowledge write operation
+ alt_dfe_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_dfe_dprio_busy <= 1'b0;
+ dfe_irq <= 1'b1; // write done
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ READ_DATA_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(dfe_irq_from_base == 1'b1)
+ begin
+ if(alt_dfe_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_dfe_dprio_busy_int <= master_read_data[8];
+ alt_dfe_dprio_busy <= 1'b1;
+ end
+ else
+ begin
+ master_address <= 3'h5;
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ alt_dfe_dprio_busy <= 1'b1;
+ end
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ dfe_irq <= 1'b1; // read done
+ alt_dfe_dprio_datain <= master_read_data[15:0];
+ alt_dfe_dprio_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_DATA_STATE;
+ end
+ end
+ default:
+ begin
+ state <= IDLE_STATE;
+ end
+ endcase
+ end
+end
+
+alt_dfe #(
+ .channel_address_width (CLogB2(number_of_reconfig_interfaces*4)),
+ .avmm_slave_addr_width (3),
+ .avmm_slave_rdata_width ( 32),
+ .avmm_slave_wdata_width (32)
+)alt_dfe_inst(
+ .i_resetn (~reset),
+ .i_avmm_clk (reconfig_clk),
+ .i_avmm_saddress (dfe_address),
+ .i_avmm_sread (dfe_read),
+ .i_avmm_swrite (dfe_write),
+ .i_avmm_swritedata (dfe_writedata),
+//. i_avmm_sbegintransfer,
+ .o_avmm_sreaddata (dfe_readdata),
+ .o_avmm_swaitrequest (dfe_waitrequest),
+
+ .i_remap_address (alt_dfe_remap_addr),
+ .o_quad_address (alt_dfe_quad_addr),
+ .o_reconfig_busy (alt_dfe_busy),
+
+ .i_dprio_busy (alt_dfe_dprio_busy),
+ .i_dprio_in (alt_dfe_dprio_datain),
+ .o_dprio_wren (alt_dfe_dprio_wren),
+ .o_dprio_rden (alt_dfe_dprio_rden),
+ .o_dprio_addr (alt_dfe_dprio_addr),
+ .o_dprio_data (alt_dfe_dprio_dataout)
+);
+alt_mutex_acq #(
+ .mutex_wait_time(103), //analog uses 101, offset cancellation uses 102
+ .addr_width(5),
+ .data_width(32)
+)
+mutex_inst (
+ .clk(reconfig_clk),
+ .reset(reset),
+// inputs to the base that should be routed through the mutex
+ .address(master_address_shifted),
+ .writedata(master_write_data),
+ .write(master_write),
+ .read(master_read),
+// output from the mutex which is processed form of output from base
+ .waitrequest(),
+ .readdata(master_read_data),
+
+// outputs from mutex to be routed to the base
+ .master_address(dfe_addr_all),
+ .master_writedata(dfe_writedata_base),
+ .master_write(dfe_write_base),
+ .master_read(dfe_read_base),
+
+// these ports are from the base routed to the mutex
+ .master_waitrequest(dfe_waitrequest_from_base),
+ .master_readdata(dfe_readdata_base), // from MM
+
+//request signal to the mutex should be kept high as long as the mutex is being used
+ .mutex_req(req_and_use_mutex),
+// output from mutex indicates whether you have mutex or not
+ .mutex_grant(mutex_grant)
+);
+assign dfe_address_base = dfe_addr_all[ 4:2];
+//wire assignment
+assign master_address_shifted = {master_address, {2'b00}};
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_eyemon_tgx.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_eyemon_tgx.sv
new file mode 100644
index 0000000000000000000000000000000000000000..cb0a8d147058a8522ece5c1f9b7c0eb17b8ec6bc
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_eyemon_tgx.sv
@@ -0,0 +1,504 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_eyemon_tgx
+#(
+ parameter device_family = "StratixIV",
+ parameter number_of_reconfig_interfaces = 1
+)
+(
+ input wire reconfig_clk, // this will be the reconfig clk
+ input wire reset,
+
+ //avalon MM slave
+ input wire [2:0] eyemon_address, // Check this! fix me!
+ input wire [31:0] eyemon_writedata,
+ input wire eyemon_write,
+ input wire eyemon_read,
+
+ //output MM slave
+ output wire [31:0] eyemon_readdata, // from MM
+ output wire eyemon_waitrequest, // from MM
+
+ output reg eyemon_irq,
+
+ // input from base_reconfig
+ input wire eyemon_irq_from_base,
+ input wire eyemon_waitrequest_from_base,
+
+ // output to base_reconfig
+ // Avalon MM Master
+ output wire [2:0] eyemon_address_base, // 3 bit MM
+ output wire [31:0] eyemon_writedata_base,
+ output wire eyemon_write_base, // start write to GXB
+ output wire eyemon_read_base, // start read from GXB
+
+ // input from base reconfig
+ input wire [31:0] eyemon_readdata_base // data from read command
+
+);
+
+//local parameters
+//state
+localparam IDLE_STATE = 4'b0000;
+localparam LOGICAL_ADDRESS_STATE = 4'b0001;
+localparam WRITE_DATA_STATE = 4'b0010;
+localparam CONTROL_STATE = 4'b0011;
+localparam BUSY_STATE = 4'b0100;
+localparam READ_PHY_ADDR_STATE = 4'b0101;
+localparam CHECK_PHY_ADDR_STATE = 4'b0110;
+localparam ADDRESS_OFFSET_STATE = 4'b0111;
+localparam BASE_BUSY_STATE = 4'b1000;
+localparam READ_DATA_STATE = 4'b1001;
+localparam WRITE_DONE_STATE = 4'b1010;
+
+localparam ILLEGAL_PHYSICAL_CHNL = 10'b1111111111;
+
+wire [4:0] eyemon_address_all; // 5 bit MM
+wire mutex_grant;
+wire [31:0] master_read_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [3:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg write_read_control;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_read;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [31:0] master_write_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [2:0] master_address;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg req_and_use_mutex;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg set_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg wait_phy_addr_ready;
+
+wire [4:0] master_address_shifted;
+
+//alt_eyemon instantiation
+wire alt_eyemon_busy;
+wire [15:0] alt_eyemon_dprio_dataout;
+wire alt_eyemon_dprio_wren;
+wire alt_eyemon_dprio_rden;
+wire [(number_of_reconfig_interfaces*4-1) : 0] alt_eyemon_error;
+
+wire [15:0] alt_eyemon_dprio_addr;
+wire [8:0] alt_eyemon_quad_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [11:0] alt_eyemon_remap_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_eyemon_dprio_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_eyemon_dprio_busy_int;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] alt_eyemon_dprio_datain;
+
+function integer CLogB2;
+input integer Depth;
+integer i;
+begin
+i = Depth;
+for(CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1)
+i = i >> 1;
+end
+endfunction
+
+// synopsys translate_off
+initial begin
+ state = 3'b000;
+ alt_eyemon_remap_addr = 12'h000;
+ req_and_use_mutex = 1'b0;
+ wait_phy_addr_ready = 1'b0;
+ alt_eyemon_dprio_datain = 16'h0000;
+ alt_eyemon_dprio_busy = 1'b0;
+ alt_eyemon_dprio_busy_int = 1'b0;
+
+ master_write = 1'b0;
+ master_read = 1'b0;
+ master_write_data = {32{1'b0}};
+ master_address = 3'h0;
+
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy = 1'b0; // 1 for assert busy, 0 for deassert busy
+
+ eyemon_irq = 1'b0;
+
+end
+// synopsys translate_on
+
+integer count;
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset)
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ master_write_data <= {32{1'b0}};
+ master_address <= 3'h0;
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ req_and_use_mutex <= 1'b0;
+ wait_phy_addr_ready <= 1'b0;
+ alt_eyemon_dprio_busy_int<= 1'b0;
+ eyemon_irq <= 1'b0;
+ end
+ else begin
+ if(alt_eyemon_busy == 1'b0)
+ req_and_use_mutex <= 1'b0;
+ else
+ req_and_use_mutex <= 1'b1;
+
+ case (state)
+ IDLE_STATE:
+ begin
+ eyemon_irq <= 1'b0; // reset write/read done flag
+ //reset the signal
+ set_busy <= 1'b0;
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ alt_eyemon_remap_addr <= 12'h000;
+
+ //alt_eyemon will not assert wren and rden at the same time
+ if((alt_eyemon_dprio_wren == 1'b1) || (alt_eyemon_dprio_rden == 1'b1))
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(alt_eyemon_dprio_wren == 1'b1)
+ write_read_control <= 1'b1; // 1 for write
+ else
+ write_read_control <= 1'b0; // 0 for read
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ else
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ state <= IDLE_STATE;
+ end
+ end
+ LOGICAL_ADDRESS_STATE: //sending channel and quad address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h1;
+ master_write_data <= {{21{1'b0}}, alt_eyemon_quad_addr, alt_eyemon_dprio_addr[13:12]};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= READ_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ end
+ READ_PHY_ADDR_STATE: //read phsical address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h2;
+ master_read <= 1'b1;
+ master_write <= 1'b0;
+ if (wait_phy_addr_ready == 1'b1)
+ begin
+ wait_phy_addr_ready <= 1'b0;
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ wait_phy_addr_ready <= 1'b1;
+ state <= READ_PHY_ADDR_STATE;
+ //state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_PHY_ADDR_STATE;
+ end
+ end
+ CHECK_PHY_ADDR_STATE: //check physical address correct or not
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ if (master_read_data[9:0] == ILLEGAL_PHYSICAL_CHNL)
+ begin
+ // synopsys translate_off
+ $display ("Illegal physical address: 10'h%h", master_read_data);
+ $display ("Time: %0t Instance: %m", $time);
+ // synopsys translate_on
+ alt_eyemon_remap_addr <= 12'hfff;
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ alt_eyemon_remap_addr <= master_read_data[11:0];
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ else
+ begin
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ ADDRESS_OFFSET_STATE: // send address offset to alt_dprio
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h4;
+ master_write_data <= {{20{1'b0}}, alt_eyemon_dprio_addr[11:0]};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(write_read_control == 1'b1)
+ state <= WRITE_DATA_STATE;
+ else
+ state <= CONTROL_STATE;
+ end
+ else
+ begin
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ WRITE_DATA_STATE:
+ begin
+ master_address <= 3'h5;
+ master_write_data = {{16{1'b0}}, alt_eyemon_dprio_dataout};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= CONTROL_STATE;
+ end
+ CONTROL_STATE: // sending write/read command
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h3; // get ready to send control command to alt_dprio
+ master_write_data <= {{29{1'b0}}, (~write_read_control), write_read_control};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ state <= BASE_BUSY_STATE;
+ end
+ else
+ begin
+ state <= CONTROL_STATE;
+ end
+ end
+ BASE_BUSY_STATE: // send busy to reconfig_togxb
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h7; // set offset cancellation busy to reconfig_togxb
+ master_write_data <= {{30{1'b0}}, alt_eyemon_busy};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(set_busy == 1'b0)
+ begin
+ set_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ else
+ begin
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= BASE_BUSY_STATE;
+ end
+ end
+ BUSY_STATE: // wait for write done
+ begin
+ if(eyemon_irq_from_base == 1'b1)
+ begin
+ alt_eyemon_dprio_busy <= 1'b1;
+ if(write_read_control == 1'b0) //read
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_eyemon_dprio_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ end
+ WRITE_DONE_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(eyemon_irq_from_base == 1'b1)
+ begin
+ if(alt_eyemon_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_eyemon_dprio_busy_int <= master_read_data[8];
+ alt_eyemon_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ else
+ begin
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ master_address <= 3'h3;
+ master_write_data <= {{16{1'b0}}, {16'h0000}}; //acknowledge write operation
+ alt_eyemon_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_eyemon_dprio_busy <= 1'b0;
+ eyemon_irq <= 1'b1; // write done
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ READ_DATA_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(eyemon_irq_from_base == 1'b1)
+ begin
+ if(alt_eyemon_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_eyemon_dprio_busy_int <= master_read_data[8];
+ alt_eyemon_dprio_busy <= 1'b1;
+ end
+ else
+ begin
+ master_address <= 3'h5;
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ alt_eyemon_dprio_busy <= 1'b1;
+ end
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ eyemon_irq <= 1'b1; // read done
+ alt_eyemon_dprio_datain <= master_read_data[15:0];
+ alt_eyemon_dprio_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_DATA_STATE;
+ end
+ end
+ default:
+ begin
+ state <= IDLE_STATE;
+ end
+ endcase
+ end
+end
+
+alt_eyemon #(
+ .channel_address_width (CLogB2(number_of_reconfig_interfaces*4)),
+ .avmm_slave_addr_width (3),
+ .avmm_slave_rdata_width ( 32),
+ .avmm_slave_wdata_width (32)
+)alt_eyemon_inst(
+ .i_resetn (~reset),
+ .i_avmm_clk (reconfig_clk),
+ .i_avmm_saddress (eyemon_address),
+ .i_avmm_sread (eyemon_read),
+ .i_avmm_swrite (eyemon_write),
+ .i_avmm_swritedata (eyemon_writedata),
+//. i_avmm_sbegintransfer,
+ .o_avmm_sreaddata (eyemon_readdata),
+ .o_avmm_swaitrequest (eyemon_waitrequest),
+
+ .i_remap_phase (1'b1), // need to figure out best way to control this - for now, always remap - fix me!
+ .i_remap_address (alt_eyemon_remap_addr),
+ .o_quad_address (alt_eyemon_quad_addr),
+ .o_reconfig_busy (alt_eyemon_busy),
+
+ .i_dprio_busy (alt_eyemon_dprio_busy),
+ .i_dprio_in (alt_eyemon_dprio_datain),
+ .o_dprio_wren (alt_eyemon_dprio_wren),
+ .o_dprio_rden (alt_eyemon_dprio_rden),
+ .o_dprio_addr (alt_eyemon_dprio_addr),
+ .o_dprio_data (alt_eyemon_dprio_dataout)
+);
+alt_mutex_acq #(
+ .mutex_wait_time(103), //analog uses 101, offset cancellation uses 102
+ .addr_width(5),
+ .data_width(32)
+)
+mutex_inst (
+ .clk(reconfig_clk),
+ .reset(reset),
+// inputs to the base that should be routed through the mutex
+ .address(master_address_shifted),
+ .writedata(master_write_data),
+ .write(master_write),
+ .read(master_read),
+// output from the mutex which is processed form of output from base
+ .waitrequest(),
+ .readdata(master_read_data),
+
+// outputs from mutex to be routed to the base
+ .master_address({eyemon_address_all}),
+ .master_writedata(eyemon_writedata_base),
+ .master_write(eyemon_write_base),
+ .master_read(eyemon_read_base),
+
+// these ports are from the base routed to the mutex
+ .master_waitrequest(eyemon_waitrequest_from_base),
+ .master_readdata(eyemon_readdata_base), // from MM
+
+//request signal to the mutex should be kept high as long as the mutex is being used
+ .mutex_req(req_and_use_mutex),
+// output from mutex indicates whether you have mutex or not
+ .mutex_grant(mutex_grant)
+);
+
+//wire assignment
+assign eyemon_address_base = eyemon_address_all[4:2];
+assign master_address_shifted = {master_address, {2'b00}};
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..102856f4162133620df696f7e6ccb75bc2dca7f4
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_h.sv
@@ -0,0 +1,266 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Top-level definitions for transceiver reconfig IP
+//
+// $Header$
+//
+// PACKAGE DECLARATION
+package alt_xcvr_reconfig_h;
+
+ ////////////////////////////////////////////////////////
+ // Top-level register map for transceiver reconfig IP
+ ////////////////////////////////////////////////////////
+ localparam W_XR_ADDR = 7; // address width on mgmt interface
+ localparam W_XR_FEATURE_LADDR = 3; // address width of standard feature block, and basic logical interface
+ typedef bit [W_XR_ADDR -1:0] t_xreconf_addr;
+ typedef bit [W_XR_FEATURE_LADDR-1:0] t_xr_feature_addr;
+
+ // Feature block indices (used for address decoding for each block)
+ localparam INDEX_XR_OFFSET = 0;
+ localparam INDEX_XR_ANALOG = 1;
+ localparam INDEX_XR_EYEMON = 2;
+ localparam INDEX_XR_DFE = 3;
+ localparam INDEX_XR_DIRECT = 4;
+ localparam INDEX_XR_ADCE = 5;
+ localparam INDEX_XR_LC = 6;
+ localparam INDEX_XR_MIF = 7;
+ localparam INDEX_XR_PLL = 8;
+ localparam INDEX_XR_DCD = 9;
+ localparam INDEX_XR_END = 10; // must always mark end of address space
+
+ // Each feature block is allocated an 8-word address range
+ localparam [W_XR_ADDR-1:0] ADDR_XR_OFFSET_BASE = t_xreconf_addr'(INDEX_XR_OFFSET << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_BASE = t_xreconf_addr'(INDEX_XR_ANALOG << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_BASE = t_xreconf_addr'(INDEX_XR_EYEMON << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_BASE = t_xreconf_addr'(INDEX_XR_DFE << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_BASE = t_xreconf_addr'(INDEX_XR_DIRECT << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_BASE = t_xreconf_addr'(INDEX_XR_ADCE << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_LC_BASE = t_xreconf_addr'(INDEX_XR_LC << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_BASE = t_xreconf_addr'(INDEX_XR_MIF << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_BASE = t_xreconf_addr'(INDEX_XR_PLL << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_BASE = t_xreconf_addr'(INDEX_XR_DCD << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_END_BASE = t_xreconf_addr'(INDEX_XR_END << W_XR_FEATURE_LADDR); // must always mark end of address space
+
+ localparam [W_XR_FEATURE_LADDR-1:0] XR_STATUS_OFST = t_xr_feature_addr'(2);
+ localparam XR_STATUS_OFST_COMB_BUSY = 8;
+
+ ////////////////////////////////////////////////////////
+ // Offset Cancellation block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_OFFSET_STATUS = t_xreconf_addr'(ADDR_XR_OFFSET_BASE + 2);
+
+
+ ////////////////////////////////////////////////////////
+ // Analog block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_LCH = t_xreconf_addr'(ADDR_XR_ANALOG_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_PCH = t_xreconf_addr'(ADDR_XR_ANALOG_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_STATUS = t_xreconf_addr'(ADDR_XR_ANALOG_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_OFFSET = t_xreconf_addr'(ADDR_XR_ANALOG_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_DATA = t_xreconf_addr'(ADDR_XR_ANALOG_BASE + 4);
+
+ // Analog internal register offsets
+ // These are to be written to the analog offset address register, ADDR_XR_ANALOG_OFFSET
+ localparam XR_ANALOG_OFFSET_VOD = 0;
+ localparam XR_ANALOG_OFFSET_PREEMPH0T = 1;
+ localparam XR_ANALOG_OFFSET_PREEMPH1T = 2;
+ localparam XR_ANALOG_OFFSET_PREEMPH2T = 3;
+ localparam XR_ANALOG_OFFSET_RXDCGAIN = 16;
+ localparam XR_ANALOG_OFFSET_RXEQCTRL = 17;
+ localparam XR_ANALOG_OFFSET_PRECDRLPBK = 32;
+ localparam XR_ANALOG_OFFSET_POSTCDRLPBK = 33;
+
+ ////////////////////////////////////////////////////////
+ // DFE block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_LCH = t_xreconf_addr'(ADDR_XR_DFE_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_PCH = t_xreconf_addr'(ADDR_XR_DFE_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_STATUS = t_xreconf_addr'(ADDR_XR_DFE_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_OFFSET = t_xreconf_addr'(ADDR_XR_DFE_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_DATA = t_xreconf_addr'(ADDR_XR_DFE_BASE + 4);
+
+ // DFE internal register offsets
+ // These are to be written to the DFE offset address register, ADDR_XR_DFE_OFFSET
+ localparam XR_DFE_OFFSET_CTRL = 0;
+ localparam XR_DFE_OFFSET_TAP1 = 1;
+ localparam XR_DFE_OFFSET_TAP2 = 2;
+ localparam XR_DFE_OFFSET_TAP3 = 3;
+ localparam XR_DFE_OFFSET_TAP4 = 4;
+ localparam XR_DFE_OFFSET_TAP5 = 5;
+ localparam XR_DFE_OFFSET_REF = 6;
+ localparam XR_DFE_OFFSET_STEP = 7;
+ localparam XR_DFE_OFFSET_DFE12 = 18;
+ localparam XR_DFE_OFFSET_DFE13 = 19;
+ localparam XR_DFE_OFFSET_DFE14 = 20;
+ localparam XR_DFE_OFFSET_DFE15 = 21;
+ localparam XR_DFE_OFFSET_CAL_PLL = 22;
+ localparam XR_DFE_OFFSET_CAL_TBUS = 23;
+ localparam XR_DFE_OFFSET_CAL_SAMPL = 24;
+ ////////////////////////////////////////////////////////
+ // Eyemon block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_LCH = t_xreconf_addr'(ADDR_XR_EYEMON_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_PCH = t_xreconf_addr'(ADDR_XR_EYEMON_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_STATUS = t_xreconf_addr'(ADDR_XR_EYEMON_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_OFFSET = t_xreconf_addr'(ADDR_XR_EYEMON_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_DATA = t_xreconf_addr'(ADDR_XR_EYEMON_BASE + 4);
+
+ // EYEMON internal register offsets
+ // These are to be written to the EYEMON offset address register, ADDR_XR_EYEMON_OFFSET
+ localparam XR_EYEMON_OFFSET_CTRL = 0;
+ localparam XR_EYEMON_OFFSET_HPHASE = 1;
+ localparam XR_EYEMON_OFFSET_VHEIGHT = 2;
+ localparam XR_EYEMON_OFFSET_EYEMON16 = 3;
+ localparam XR_EYEMON_OFFSET_EYEMON17 = 4;
+
+ ////////////////////////////////////////////////////////
+ // ADCE block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_LCH = t_xreconf_addr'(ADDR_XR_ADCE_BASE + 0); // Logical channel number
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_PCH = t_xreconf_addr'(ADDR_XR_ADCE_BASE + 1); // Physical channel number
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_STATUS = t_xreconf_addr'(ADDR_XR_ADCE_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_OFFSET = t_xreconf_addr'(ADDR_XR_ADCE_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_DATA = t_xreconf_addr'(ADDR_XR_ADCE_BASE + 4);
+
+ // ADCE internal register offsets
+ // These are to be written to the ADCE offset address register, ADDR_XR_ADCE_OFFSET
+ localparam XR_ADCE_OFFSET_CTRL = 0;
+ localparam XR_ADCE_OFFSET_RESULTS = 1; // Manual setting equivalent to ADCE results
+ localparam XR_ADCE_OFFSET_RADCE_ATT_0 = 9; // radce_att[15: 0]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_1 = 10; // radce_att[31:15]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_2 = 11; // radce_att[47:32]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_3 = 12; // radce_att[63:48]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_4 = 13; // radce_att[79:64]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_5 = 14; // radce_att[95:80]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_6 = 15; // radce_att[111:96]
+
+ ////////////////////////////////////////////////////////
+ // DCD block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_LCH = t_xreconf_addr'(ADDR_XR_DCD_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_PCH = t_xreconf_addr'(ADDR_XR_DCD_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_STATUS = t_xreconf_addr'(ADDR_XR_DCD_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_OFFSET = t_xreconf_addr'(ADDR_XR_DCD_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_DATA = t_xreconf_addr'(ADDR_XR_DCD_BASE + 4);
+
+ // DCD internal register offsets
+ // These are to be written to the DFE offset address register, ADDR_XR_DCD_OFFSET
+ localparam XR_DCD_OFFSET_CTRL = 0;
+
+ ////////////////////////////////////////////////////////
+ // MIF block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_LCH = t_xreconf_addr'(ADDR_XR_MIF_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_PCH = t_xreconf_addr'(ADDR_XR_MIF_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_STATUS = t_xreconf_addr'(ADDR_XR_MIF_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_OFFSET = t_xreconf_addr'(ADDR_XR_MIF_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_DATA = t_xreconf_addr'(ADDR_XR_MIF_BASE + 4);
+
+ ////////////////////////////////////////////////////////
+ // PLL block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_LCH = t_xreconf_addr'(ADDR_XR_PLL_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_PCH = t_xreconf_addr'(ADDR_XR_PLL_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_STATUS = t_xreconf_addr'(ADDR_XR_PLL_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_OFFSET = t_xreconf_addr'(ADDR_XR_PLL_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_DATA = t_xreconf_addr'(ADDR_XR_PLL_BASE + 4);
+
+
+
+
+ ////////////////////////////////////////////////////////
+ // Basic block addresses (internal, private addresses)
+ ////////////////////////////////////////////////////////
+ // The 'basic' interface block is the switch that routes requests to
+ // an appropriate physical reconfiguration interface. A logical channel
+ // number acts as a channel ID, which allows the basic block to find
+ // the corresponding physical reconfiguration interface, and a physical
+ // channel index within a physical interface.
+ //
+ // The Basic (B) block features are also available via the direct access block.
+ // All users of the basic block, including the direct access block, must
+ // acquire appropriate semaphores before using an interface, and release
+ // the semaphores when done, to avoid locking out other feature blocks.
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_MUTEX = t_xr_feature_addr'(0);
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_LOGICAL_CHANNEL = t_xr_feature_addr'(1);
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_PHYSICAL_CHANNEL = t_xr_feature_addr'(2);
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_CONTROL = t_xr_feature_addr'(3);
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_OFFSET_ADDR = t_xr_feature_addr'(4);
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_DATA = t_xr_feature_addr'(5);
+
+
+ ////////////////////////////////////////////////////////
+ // Direct Access & Basic block addresses
+ ////////////////////////////////////////////////////////
+ //
+ // The minimum steps to read & write a reconfiguration word are the following:
+ // Step 1 - acquire basic arbiter lock (write 1 to ADDR_XR_DIRECT_ARB_ACQ)
+ // Step 2 - write logical channel number to ADDR_XR_DIRECT_LCH
+ // Step 3 - acquire channel lock
+ // 3a - request channel lock (write XR_DIRECT_CONTROL_PHYS_LOCK_SET to ADDR_XR_DIRECT_CONTROL)
+ // 3b - confirm channel lock (read ADDR_XR_DIRECT_CONTROL, mask with XR_DIRECT_STATUS_BITMASK_PHYS_LOCK_GRANTED)
+ // -- repeat step 3b until result after applying mask is != 0
+ // Step 4 - write channel offset address to ADDR_XR_DIRECT_OFFSET
+ // Step 5 - read existing value from reconfig space, modify, then write back
+ // 5a (read cycle part 1) - write XR_DIRECT_CONTROL_RECONF_READ to ADDR_XR_DIRECT_CONTROL
+ // 5b (read cycle part 2) - read data from ADDR_XR_DIRECT_DATA
+ // 5c (write cycle part 1) - write modified value to ADDR_XR_DIRECT_DATA
+ // 5d (write cycle part 2) - write XR_DIRECT_CONTROL_RECONF_WRITE to ADDR_XR_DIRECT_CONTROL
+ // -- addtional read-modify-write cycles, repeat from step 2 or 4 (can skip step 3a)
+ // Step 6 - release channel lock (write XR_DIRECT_CONTROL_PHYS_LOCK_CLEAR to ADDR_XR_DIRECT_CONTROL)
+ // Step 7 - release basic arbiter lock (write 0 to ADDR_XR_DIRECT_ARB_ACQ)
+ //
+ // Direct/Basic register bitmap ---------------------------------------------------------
+ // word addr wr/rd description
+ // ------------------------------------------------------
+ // 0 wr basic arbiter, 1 to request access, 0 to release lock
+ // 1 wr/rd logical channel number
+ // 2 rd physical channel number. When lower 3 bits are 3'b111, means ch is not present
+ // 3 wr/rd status/control -- see XR_DIRECT_CONTROL_* opcodes and XR_DIRECT_STATUS_* bitfield definitions
+ // 4 wr/rd offset_addr -- for opcode-based reads & writes
+ // 5 wr/rd data -- for opcode-based reads & writes
+ // 6 -- reserved
+ // 7 -- reserved
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_ARB_ACQ = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + 0); // write 1 to request B access, 0 to release
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_LCH = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + ADDR_XCVR_RECONFIG_BASIC_LOGICAL_CHANNEL);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_PCH = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + ADDR_XCVR_RECONFIG_BASIC_PHYSICAL_CHANNEL);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_CONTROL = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + ADDR_XCVR_RECONFIG_BASIC_CONTROL);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_OFFSET = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + ADDR_XCVR_RECONFIG_BASIC_OFFSET_ADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_DATA = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + ADDR_XCVR_RECONFIG_BASIC_DATA);
+
+ // Opcode values for writes to control word, ADDR_XR_DIRECT_CONTROL
+ localparam XR_DIRECT_CONTROL_RECONF_WRITE = 32'b0000; // reconfig space: write current DATA to OFFSET addr (as physical addr or ch offset addr)
+ localparam XR_DIRECT_CONTROL_RECONF_READ = 32'b0001; // reconfig space: read from OFFSET_ADDR, save result in DATA
+ localparam XR_DIRECT_CONTROL_LADDR_SET = 32'b0010; // interpret OFFSET_ADDR as logical addr, with automatic ch addr offset
+ localparam XR_DIRECT_CONTROL_PADDR_SET = 32'b0011; // interpret OFFSET_ADDR as physical addr, with no automatic addr offset
+ localparam XR_DIRECT_CONTROL_PHYS_LOCK_CLEAR = 32'b0100; // clear lock request for current channel
+ localparam XR_DIRECT_CONTROL_PHYS_LOCK_SET = 32'b0101; // set lock request for current channel
+ localparam XR_DIRECT_CONTROL_ADDR_AUTO_INCR_CLEAR = 32'b0110; // clear auto-write-and-address-increment mode for data writes
+ localparam XR_DIRECT_CONTROL_ADDR_AUTO_INCR_SET = 32'b0111; // set auto-write-and-address-increment mode for data writes
+ localparam XR_DIRECT_CONTROL_INTERNAL_WRITE = 32'b1000; // Internal registers, mainly testbus control
+ //localparam XR_DIRECT_CONTROL_INTERNAL_READ = 32'b1001; // internal reg space: read from OFFSET_ADDR, save result in DATA
+ localparam XR_DIRECT_CONTROL_TABLE_READ = 32'b1011; // ROM table lookup, especially for PLL and clock mux remapping
+
+ // Read of control/status reg returns this bitfield data
+ localparam XR_DIRECT_STATUS_BITMASK_PHYS_LOCK_GRANTED = 32'b0001; // on read, bit 0 is grant status
+ localparam XR_DIRECT_STATUS_BITMASK_PHYS_LOCK_REQUESTED = 32'b0010; // on read, bit 1 is physical lock request flag
+ localparam XR_DIRECT_STATUS_BITMASK_USING_PHYS_ADDR = 32'b0100; // on read, bit 2 is physical addr mode indicator (0 mean logical addr)
+ localparam XR_DIRECT_STATUS_BITMASK_USING_ADDR_AUTO_INCR = 32'b1000; // on read, bit 3 is auto-write-and-addr-incr mode indicator
+
+ // Internal register addresses, for read/write via these opcodes: XR_DIRECT_CONTROL_INTERNAL_*
+ localparam XR_DIRECT_OFFSET_TESTBUS_SEL = 2'd0; // internal register for testbus sel
+
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_offset_cancellation.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_offset_cancellation.sv
new file mode 100644
index 0000000000000000000000000000000000000000..0dd5517bb661acbd542861fa584fe89ae3aa336c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_offset_cancellation.sv
@@ -0,0 +1,174 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_offset_cancellation
+#(
+ parameter device_family = "StratixV",
+ parameter number_of_reconfig_interfaces = 1
+)
+(
+ input wire reconfig_clk, // this will be the reconfig clk
+ input wire reset,
+
+ //avalon MM slave
+ input wire [2:0] offset_cancellation_address, // MM address
+ input wire [31:0] offset_cancellation_writedata,
+ input wire offset_cancellation_write,
+ input wire offset_cancellation_read,
+
+ //output MM slave
+ output wire [31:0] offset_cancellation_readdata, // from MM
+
+ output wire offset_cancellation_done,
+
+ // input from base_reconfig
+ input wire offset_cancellation_irq_from_base,
+ input wire offset_cancellation_waitrequest_from_base,
+ output wire offset_cancellation_waitrequest,
+
+ // output to base_reconfig
+ // Avalon MM Master
+ output wire [2:0] offset_cancellation_address_base, // 3 bit MM
+ output wire [31:0] offset_cancellation_writedata_base,
+ output wire offset_cancellation_write_base, // start write to GXB
+ output wire offset_cancellation_read_base, // start read from GXB
+
+ // input from base reconfig
+ input wire [31:0] offset_cancellation_readdata_base, // data from read command
+
+ // Avalon ST
+ input wire [number_of_reconfig_interfaces*16 - 1 : 0] testbus_data,
+
+ // external connect to switch fabric: request basic access from arbiter
+ output wire arb_req,
+ input wire arb_grant
+
+);
+
+import altera_xcvr_functions::*;
+localparam is_s4 = has_s4_style_hssi(device_family);
+localparam is_s5 = has_s5_style_hssi(device_family);
+localparam is_a5 = has_a5_style_hssi(device_family);
+
+
+generate
+ //Deepak - Namespace support for AII GX and CIVGX
+ if(is_s4)
+ begin
+ wire [4:0] w_tgx_offset_cancellation_address_base;
+ alt_xcvr_reconfig_offset_cancellation_tgx
+ #(
+ .device_family(device_family),
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces)
+ ) offset_cancellation_tgx
+ (
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .offset_cancellation_address(offset_cancellation_address),
+ .offset_cancellation_writedata(offset_cancellation_writedata),
+ .offset_cancellation_write(offset_cancellation_write),
+ .offset_cancellation_read(offset_cancellation_read),
+ .offset_cancellation_readdata(offset_cancellation_readdata),
+ .offset_cancellation_done(offset_cancellation_done),
+ .offset_cancellation_irq_from_base(offset_cancellation_irq_from_base),
+ .offset_cancellation_waitrequest_from_base(offset_cancellation_waitrequest_from_base),
+ .offset_cancellation_waitrequest(offset_cancellation_waitrequest),
+ .offset_cancellation_address_base(w_tgx_offset_cancellation_address_base),
+ .offset_cancellation_writedata_base(offset_cancellation_writedata_base),
+ .offset_cancellation_write_base(offset_cancellation_write_base),
+ .offset_cancellation_read_base(offset_cancellation_read_base),
+ .offset_cancellation_readdata_base(offset_cancellation_readdata_base),
+ .testbus_data(testbus_data)
+ );
+ assign offset_cancellation_address_base = w_tgx_offset_cancellation_address_base[4:2];
+ assign arb_req = 1'b0 & arb_grant; // not currently used in S4 architecture
+ end
+ else if (is_s5)
+ begin
+ alt_xcvr_reconfig_offset_cancellation_sv
+ #(
+ .device_family(device_family),
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces)
+ ) offset_cancellation_sv
+ (
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .offset_cancellation_address(offset_cancellation_address),
+ .offset_cancellation_writedata(offset_cancellation_writedata),
+ .offset_cancellation_write(offset_cancellation_write),
+ .offset_cancellation_read(offset_cancellation_read),
+ .offset_cancellation_readdata(offset_cancellation_readdata),
+ .offset_cancellation_done(offset_cancellation_done),
+ .offset_cancellation_irq_from_base(offset_cancellation_irq_from_base),
+ .offset_cancellation_waitrequest_from_base(offset_cancellation_waitrequest_from_base),
+ .offset_cancellation_waitrequest(offset_cancellation_waitrequest),
+ .offset_cancellation_address_base(offset_cancellation_address_base),
+ .offset_cancellation_writedata_base(offset_cancellation_writedata_base),
+ .offset_cancellation_write_base(offset_cancellation_write_base),
+ .offset_cancellation_read_base(offset_cancellation_read_base),
+ .offset_cancellation_readdata_base(offset_cancellation_readdata_base),
+ .testbus_data(testbus_data[7:0]), // testbus data is now provided on a per-channel basis from the 'B' - only need the lower 8 bits
+ .arb_req(arb_req),
+ .arb_grant(arb_grant)
+ );
+ end
+ else if (is_a5)
+ begin
+ alt_xcvr_reconfig_offset_cancellation_av
+ #(
+ .device_family(device_family),
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces)
+ ) offset_cancellation_av
+ (
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .offset_cancellation_address(offset_cancellation_address),
+ .offset_cancellation_writedata(offset_cancellation_writedata),
+ .offset_cancellation_write(offset_cancellation_write),
+ .offset_cancellation_read(offset_cancellation_read),
+ .offset_cancellation_readdata(offset_cancellation_readdata),
+ .offset_cancellation_done(offset_cancellation_done),
+ .offset_cancellation_irq_from_base(offset_cancellation_irq_from_base),
+ .offset_cancellation_waitrequest_from_base(offset_cancellation_waitrequest_from_base),
+ .offset_cancellation_waitrequest(offset_cancellation_waitrequest),
+ .offset_cancellation_address_base(offset_cancellation_address_base),
+ .offset_cancellation_writedata_base(offset_cancellation_writedata_base),
+ .offset_cancellation_write_base(offset_cancellation_write_base),
+ .offset_cancellation_read_base(offset_cancellation_read_base),
+ .offset_cancellation_readdata_base(offset_cancellation_readdata_base),
+ .testbus_data(testbus_data[7:0]), // testbus data is now provided on a per-channel basis from the 'B' - only need the lower 8 bits
+ .arb_req(arb_req),
+ .arb_grant(arb_grant)
+ );
+ end
+ else
+ begin
+ assign offset_cancellation_readdata = 32'd0;
+ assign offset_cancellation_done = 1'd0;
+ assign offset_cancellation_waitrequest = 1'd0;
+ assign offset_cancellation_address_base = 3'd0;
+ assign offset_cancellation_writedata_base = 32'd0;
+ assign offset_cancellation_write_base = 1'd0;
+ assign offset_cancellation_read_base = 1'd0;
+ assign arb_req = 1'd0;
+ end
+
+
+
+endgenerate
+
+endmodule
+
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_offset_cancellation_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_offset_cancellation_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..01ee1edc16393c8b5f525ce12734b754321f57b7
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_offset_cancellation_tgx.v
@@ -0,0 +1,581 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_offset_cancellation_tgx
+#(
+ parameter device_family = "StratixIV",
+ parameter number_of_reconfig_interfaces = 1
+)
+(
+ input wire reconfig_clk, // this will be the reconfig clk
+ input wire reset,
+
+ //avalon MM slave
+ input wire offset_cancellation_address, // MM address
+ input wire [31:0] offset_cancellation_writedata,
+ input wire offset_cancellation_write,
+ input wire offset_cancellation_read,
+
+ //output MM slave
+ output reg [31:0] offset_cancellation_readdata, // from MM
+
+ output reg offset_cancellation_done,
+
+ // input from base_reconfig
+ input wire offset_cancellation_irq_from_base,
+ input wire offset_cancellation_waitrequest_from_base,
+
+ output wire offset_cancellation_waitrequest,
+
+ // output to base_reconfig
+ // Avalon MM Master
+ output wire [4:0] offset_cancellation_address_base, // 3 bit MM
+ output wire [31:0] offset_cancellation_writedata_base,
+ output wire offset_cancellation_write_base, // start write to GXB
+ output wire offset_cancellation_read_base, // start read from GXB
+
+ // input from base reconfig
+ input wire [31:0] offset_cancellation_readdata_base, // data from read command
+
+ // Avalon ST
+ input wire [number_of_reconfig_interfaces*16 - 1 : 0] testbus_data
+);
+
+///////////////////////////////////////////////////////////////////
+// Memory map | wr/rd | Description
+//----------------------------------------------------------------
+// 0 | wr/rd | [31:10] Reserved
+// | | [9] Error
+// | | [8] Busy
+// | | [7:1] Reserved
+// | | [0] Start (hidden for QII 9.1)
+///////////////////////////////////////////////////////////////////
+
+//local parameters
+//state
+localparam IDLE_STATE = 4'b0000;
+localparam LOGICAL_ADDRESS_STATE = 4'b0001;
+localparam WRITE_DATA_STATE = 4'b0010;
+localparam CONTROL_STATE = 4'b0011;
+localparam BUSY_STATE = 4'b0100;
+localparam READ_PHY_ADDR_STATE = 4'b0101;
+localparam CHECK_PHY_ADDR_STATE = 4'b0110;
+localparam ADDRESS_OFFSET_STATE = 4'b0111;
+localparam BASE_BUSY_STATE = 4'b1000;
+localparam READ_DATA_STATE = 4'b1001;
+localparam WRITE_DONE_STATE = 4'b1010;
+
+localparam ILLEGAL_PHYSICAL_CHNL = 10'b1111111111;
+
+wire mutex_grant;
+wire [31:0] master_read_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [3:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg write_read_control;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_read;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [31:0] master_write_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [2:0] master_address;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg req_and_use_mutex;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg set_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_cal_error_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg wait_phy_addr_ready;
+
+wire [4:0] master_address_shifted;
+
+//alt_cal instantiation
+wire alt_cal_busy;
+wire [15:0] alt_cal_dprio_dataout;
+wire alt_cal_dprio_wren;
+wire alt_cal_dprio_rden;
+wire alt_cal_retain_addr;
+wire [(number_of_reconfig_interfaces*4-1) : 0] alt_cal_error;
+
+wire [number_of_reconfig_interfaces*16 - 1 : 0] alt_cal_testbuses;
+wire [15:0] alt_cal_dprio_addr;
+wire [8:0] alt_cal_quad_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [11:0] alt_cal_remap_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_cal_dprio_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_cal_dprio_busy_int;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] alt_cal_dprio_datain;
+
+function integer CLogB2;
+input integer Depth;
+integer i;
+begin
+i = Depth;
+for(CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1)
+i = i >> 1;
+end
+endfunction
+
+// Implement waitrequest to match previous implementation
+altera_wait_generate wait_gen(
+ .rst(reset),
+ .clk(reconfig_clk),
+ .launch_signal(offset_cancellation_read),
+ .wait_req(offset_cancellation_waitrequest)
+);
+
+// synopsys translate_off
+initial begin
+ state = 3'b000;
+ alt_cal_remap_addr = 12'h000;
+ req_and_use_mutex = 1'b0;
+ wait_phy_addr_ready = 1'b0;
+ // alt_cal_testbuses = 0;
+ alt_cal_dprio_datain = 16'h0000;
+ alt_cal_dprio_busy = 1'b0;
+ alt_cal_dprio_busy_int = 1'b0;
+
+ master_write = 1'b0;
+ master_read = 1'b0;
+ master_write_data = {32{1'b0}};
+ master_address = 3'h0;
+
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy = 1'b0; // 1 for assert busy, 0 for deassert busy
+
+ alt_cal_error_reg = 1'b0;
+ offset_cancellation_done = 1'b0;
+
+end
+// synopsys translate_on
+
+integer count;
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset)
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ master_write_data <= {32{1'b0}};
+ master_address <= 3'h0;
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ offset_cancellation_readdata[31:0] <= {32{1'b0}};
+ alt_cal_error_reg <= 1'b0;
+ req_and_use_mutex <= 1'b0;
+ wait_phy_addr_ready <= 1'b0;
+ alt_cal_dprio_busy_int<= 1'b0;
+ offset_cancellation_done <= 1'b0;
+ end
+ else begin
+ if(offset_cancellation_read == 1'b1)
+ begin
+ if(offset_cancellation_address == 1'b0)
+ begin
+ offset_cancellation_readdata <= {{22{1'b0}}, alt_cal_error_reg, alt_cal_busy , {8{1'b0}}};
+ end
+ end
+
+ for(count=0; count < (number_of_reconfig_interfaces*4); count=count+1)
+ begin
+ alt_cal_error_reg = alt_cal_error[count] | alt_cal_error_reg;
+ end
+
+ if(alt_cal_busy == 1'b0)
+ req_and_use_mutex <= 1'b0;
+ else
+ req_and_use_mutex <= 1'b1;
+
+ case (state)
+ IDLE_STATE:
+ begin
+ offset_cancellation_done <= 1'b0; // reset write/read done flag
+ //reset the signal
+ set_busy <= 1'b0;
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ alt_cal_remap_addr <= 12'h000;
+
+ //al_cal will not assert wren and rden at the same time
+ if((alt_cal_dprio_wren == 1'b1) || (alt_cal_dprio_rden == 1'b1))
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(alt_cal_dprio_wren == 1'b1)
+ write_read_control <= 1'b1; // 1 for write
+ else
+ write_read_control <= 1'b0; // 0 for read
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ else
+ state <= IDLE_STATE;
+ end
+ else if(alt_cal_retain_addr == 1'b1)
+ begin
+ if(mutex_grant == 1'b1)
+ state <= WRITE_DATA_STATE;
+ else
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ state <= IDLE_STATE;
+ end
+ end
+ LOGICAL_ADDRESS_STATE: //sending channel and quad address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h1;
+ master_write_data <= {{21{1'b0}}, alt_cal_quad_addr, alt_cal_dprio_addr[13:12]};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= READ_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ end
+ READ_PHY_ADDR_STATE: //read phsical address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h2;
+ master_read <= 1'b1;
+ master_write <= 1'b0;
+ if (wait_phy_addr_ready == 1'b1)
+ begin
+ wait_phy_addr_ready <= 1'b0;
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ wait_phy_addr_ready <= 1'b1;
+ state <= READ_PHY_ADDR_STATE;
+ //state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_PHY_ADDR_STATE;
+ end
+ end
+ CHECK_PHY_ADDR_STATE: //check physical address correct or not
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ if (master_read_data[9:0] == ILLEGAL_PHYSICAL_CHNL)
+ begin
+ // synopsys translate_off
+ $display ("Illegal physical address: 10'h%h", master_read_data);
+ $display ("Time: %0t Instance: %m", $time);
+ // synopsys translate_on
+ alt_cal_remap_addr <= 12'hfff;
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ alt_cal_remap_addr <= master_read_data[11:0];
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ else
+ begin
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ ADDRESS_OFFSET_STATE: // send address offset to alt_dprio
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h4;
+ master_write_data <= {{17{1'b0}}, alt_cal_dprio_addr[14:0]};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(write_read_control == 1'b1)
+ state <= WRITE_DATA_STATE;
+ else
+ state <= CONTROL_STATE;
+ end
+ else
+ begin
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ WRITE_DATA_STATE:
+ begin
+ master_address <= 3'h5;
+ master_write_data = {{16{1'b0}}, alt_cal_dprio_dataout};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= CONTROL_STATE;
+ end
+ CONTROL_STATE: // sending write/read command
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h3; // get ready to send control command to alt_dprio
+// master_write_data <= {{29{1'b0}}, (~write_read_control), write_read_control};
+ master_write_data <= {{27{1'b0}}, 1'b1, 1'b0, (~write_read_control), write_read_control}; // use absolute addressing
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ state <= BASE_BUSY_STATE;
+ end
+ else
+ begin
+ state <= CONTROL_STATE;
+ end
+ end
+ BASE_BUSY_STATE: // send busy to reconfig_togxb
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h7; // set offset cancellation busy to reconfig_togxb
+ master_write_data <= {{30{1'b0}}, alt_cal_busy};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(set_busy == 1'b0)
+ begin
+ set_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ else
+ begin
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= BASE_BUSY_STATE;
+ end
+ end
+ BUSY_STATE: // wait for write done
+ begin
+ if(offset_cancellation_irq_from_base == 1'b1)
+ begin
+ alt_cal_dprio_busy <= 1'b1;
+ if(write_read_control == 1'b0) //read
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_cal_dprio_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ end
+ WRITE_DONE_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(offset_cancellation_irq_from_base == 1'b1)
+ begin
+ if(alt_cal_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_cal_dprio_busy_int <= master_read_data[8];
+ alt_cal_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ else
+ begin
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ master_address <= 3'h3;
+ master_write_data <= {{16{1'b0}}, {16'h0000}}; //acknowledge write operation
+ alt_cal_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_cal_dprio_busy <= 1'b0;
+ offset_cancellation_done <= 1'b1; // write done
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ READ_DATA_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(offset_cancellation_irq_from_base == 1'b1)
+ begin
+ if(alt_cal_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_cal_dprio_busy_int <= master_read_data[8];
+ alt_cal_dprio_busy <= 1'b1;
+ end
+ else
+ begin
+ master_address <= 3'h5;
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ alt_cal_dprio_busy <= 1'b1;
+ end
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ offset_cancellation_done <= 1'b1; // read done
+ alt_cal_dprio_datain <= master_read_data[15:0];
+ alt_cal_dprio_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_DATA_STATE;
+ end
+ end
+ default:
+ begin
+ state <= IDLE_STATE;
+ end
+ endcase
+ end
+end
+
+
+
+generate
+
+//Deepak Use alt_cal_mm for SIV and AIIGX
+if((device_family=="Stratix IV") || (device_family=="Arria II GX") || (device_family=="Arria II GZ") || (device_family=="HardCopy IV"))
+begin
+ alt_cal_mm #(
+ .number_of_channels (number_of_reconfig_interfaces*4),
+ .channel_address_width (CLogB2(number_of_reconfig_interfaces*4))
+ )alt_cal_inst
+ (
+ .clock(reconfig_clk),
+ .reset(reset),
+ .start(),
+ .busy(alt_cal_busy),
+ .dprio_addr(alt_cal_dprio_addr), // only extract the logical channel address
+ .quad_addr(alt_cal_quad_addr),
+ .dprio_dataout(alt_cal_dprio_dataout),
+ .dprio_datain(alt_cal_dprio_datain),
+ .dprio_wren(alt_cal_dprio_wren),
+ .dprio_rden(alt_cal_dprio_rden),
+ .dprio_busy(alt_cal_dprio_busy),
+ .retain_addr(alt_cal_retain_addr),
+ .remap_addr(alt_cal_remap_addr),
+ .testbuses(alt_cal_testbuses),
+ .cal_error(alt_cal_error)
+ );
+end
+//Deepak: Use alt_cal_c3gxb for Cyclone IV GX
+if(device_family=="Cyclone IV GX")
+begin
+ alt_cal_c3gxb alt_cal_inst
+ (
+ .clock(reconfig_clk),
+ .reset(reset),
+ .start(),
+ .busy(alt_cal_busy),
+ .dprio_addr(alt_cal_dprio_addr), // only extract the logical channel address
+ .quad_addr(alt_cal_quad_addr),
+ .dprio_dataout(alt_cal_dprio_dataout),
+ .dprio_datain(alt_cal_dprio_datain),
+ .dprio_wren(alt_cal_dprio_wren),
+ .dprio_rden(alt_cal_dprio_rden),
+ .dprio_busy(alt_cal_dprio_busy),
+ .retain_addr(alt_cal_retain_addr),
+ .remap_addr(alt_cal_remap_addr),
+ .testbuses(alt_cal_testbuses),
+ .cal_error(alt_cal_error)
+ );
+defparam
+ alt_cal_inst.number_of_channels = number_of_reconfig_interfaces*4,
+ alt_cal_inst.channel_address_width = CLogB2(number_of_reconfig_interfaces*4);
+end
+endgenerate
+
+alt_mutex_acq #(
+ .mutex_wait_time(102), ///Thia: pick a different mutex wait time to avoid collision. Say 102. (since analog is already using 101)
+ .addr_width(5),
+ .data_width(32)
+)
+mutex_inst (
+ .clk(reconfig_clk),
+ .reset(reset),
+// inputs to the base that should be routed through the mutex
+ .address(master_address_shifted),
+ .writedata(master_write_data),
+ .write(master_write),
+ .read(master_read),
+// output from the mutex which is processed form of output from base
+ .waitrequest(),
+ .readdata(master_read_data),
+
+// outputs from mutex to be routed to the base
+ .master_address(offset_cancellation_address_base),
+ .master_writedata(offset_cancellation_writedata_base),
+ .master_write(offset_cancellation_write_base),
+ .master_read(offset_cancellation_read_base),
+
+// these ports are from the base routed to the mutex
+ .master_waitrequest(offset_cancellation_waitrequest_from_base),
+ .master_readdata(offset_cancellation_readdata_base), // from MM
+
+//request signal to the mutex should be kept high as long as the mutex is being used
+ .mutex_req(req_and_use_mutex),
+// output from mutex indicates whether you have mutex or not
+ .mutex_grant(mutex_grant)
+);
+
+//wire assignment
+assign alt_cal_testbuses = testbus_data;
+assign master_address_shifted = {master_address, {2'b00}};
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_siv.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_siv.sv
new file mode 100644
index 0000000000000000000000000000000000000000..727be748a008f29b2f9649fef902f9787b9b1f47
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_reconfig_siv.sv
@@ -0,0 +1,441 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Transceiver Reconfiguration Module for Stratix IV architectures
+//
+// Includes many function-specific sub-modules, such as:
+// - analog reconfig (alt_xcvr_reconfig_analog)
+// - offset cancellation (alt_xcvr_reconfig_offset_cancellation)
+// - ...
+
+// $Header$
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_reconfig_siv #(
+ parameter number_of_reconfig_interfaces = 1
+) (
+ input wire mgmt_clk_clk, // mgmt_clk.clk
+ input wire mgmt_rst_reset, // mgmt_rst.reset
+
+ // user reconfiguration management interface
+ input wire [6:0] reconfig_mgmt_address, // reconfig_mgmt.address
+ output reg reconfig_mgmt_waitrequest = 0, // .waitrequest
+ input wire reconfig_mgmt_read, // .read
+ output reg [31:0] reconfig_mgmt_readdata = ~0, // .readdata
+ input wire reconfig_mgmt_write, // .write
+ input wire [31:0] reconfig_mgmt_writedata, // .writedata
+ output wire reconfig_done, // reconfig_done.export
+
+ output wire [3:0] reconfig_togxb, // reconfig_togxb_data.data
+ input wire [number_of_reconfig_interfaces*17 - 1 : 0] reconfig_fromgxb // dprioout, testbus from altgx : (17+4 bits/quad)
+);
+
+ // master interface to basic reconfiguration block that interfaces to the transceiver channel
+ wire [2:0] basic_address; // basic.address // master interface must include 2 lower addr bits
+ wire basic_waitrequest; // .waitrequest
+ wire basic_irq; // .irq
+ wire basic_read; // .read
+ wire [31:0] basic_readdata; // .readdata
+ wire basic_write; // .write
+ wire [31:0] basic_writedata; // .writedata
+
+ // native testbus input
+ wire [15:0] testbus_data;
+
+ localparam l_dev_family = "Stratix IV";
+ localparam width_awa = 3; // word address width of interface to analog reconfig block
+ localparam width_bwa = 3; // word address width of interface to basic reconfig block
+ localparam arb_count = 4; // count of the total number of sub-components that can act
+ // as slaves to the mgmt interface, and masters to the 'basic' block
+ localparam arb_offset = 0;
+ localparam arb_analog = 1;
+ localparam arb_eyemon = 2;
+ localparam arb_dfe = 3;
+
+ // Analog controls output ports, mgmt facing
+ wire [31:0] sc_analog_readdata;
+ wire sc_analog_waitrequest;
+
+ // Offset cancellation output ports, mgmt facing
+ wire [31:0] sc_offset_readdata;
+ wire sc_offset_waitrequest;
+
+ // Eyemon output ports, mgmt facing
+ wire [31:0] sc_eyemon_readdata;
+ wire sc_eyemon_waitrequest;
+
+ // DFE output ports, mgmt facing
+ wire [31:0] sc_dfe_readdata;
+ wire sc_dfe_waitrequest;
+
+ ///////////////////////////////////////////////////////////////////////
+ // Decoder for multiple slaves of reconfig_mgmt interface
+ ///////////////////////////////////////////////////////////////////////
+ wire [arb_count-1:0] r_decode;
+ assign r_decode =
+ (reconfig_mgmt_address[6:width_awa] == arb_offset) ? (({arb_count-arb_offset{1'b0}} | 1'b1) << arb_offset)
+ : (reconfig_mgmt_address[6:width_awa] == arb_analog) ? (({arb_count-arb_analog{1'b0}} | 1'b1) << arb_analog)
+ : (reconfig_mgmt_address[6:width_awa] == arb_eyemon) ? (({arb_count-arb_eyemon{1'b0}} | 1'b1) << arb_eyemon)
+ : (reconfig_mgmt_address[6:width_awa] == arb_dfe) ? (({arb_count-arb_dfe{1'b0}} | 1'b1) << arb_dfe)
+ : {arb_count{1'b0}};
+
+ // reconfig_mgmt output generation is muxing of decoded slave output
+ always @(*) begin
+ case (reconfig_mgmt_address[6:width_awa])
+ arb_offset: begin
+ reconfig_mgmt_readdata = sc_offset_readdata;
+ reconfig_mgmt_waitrequest = sc_offset_waitrequest;
+ end
+ arb_analog: begin
+ reconfig_mgmt_readdata = sc_analog_readdata;
+ reconfig_mgmt_waitrequest = sc_analog_waitrequest;
+ end
+ arb_eyemon: begin
+ reconfig_mgmt_readdata = sc_eyemon_readdata;
+ reconfig_mgmt_waitrequest = sc_eyemon_waitrequest;
+ end
+ arb_dfe: begin
+ reconfig_mgmt_readdata = sc_dfe_readdata;
+ reconfig_mgmt_waitrequest = sc_dfe_waitrequest;
+ end
+ default: begin
+ reconfig_mgmt_readdata = -1;
+ reconfig_mgmt_waitrequest = 1'b0;
+ end
+ endcase
+ end
+
+ ///////////////////////////////////////////////////////////////////////
+ // Arbiter for multiple masters accessing 'basic' reconfig slave port
+ ///////////////////////////////////////////////////////////////////////
+ wire [arb_count-1:0] req; // req[0] is highest priority when current grantee is done
+ wire [arb_count-1:0] grant;
+
+ alt_xcvr_arbiter #(
+ .width(arb_count) // count total number of sub-components that act as masters to 'basic'
+ ) arbiter (
+ .clock(mgmt_clk_clk),
+ .req(req),
+ .grant(grant)
+ );
+
+ ////////////////////////////////////
+ // Sub-component: analog controls
+ // word address offset: +0
+ ////////////////////////////////////
+
+ // Analog controls output ports, mgmt facing
+ wire analog_reconfig_done;
+ // Analog controls output ports, basic slave facing
+ wire [width_bwa+1:0] scs_analog_address;
+ wire [31:0] scs_analog_writedata;
+ wire scs_analog_write;
+ wire scs_analog_read;
+
+ // Analog controls master-to-slave access fabric outputs
+ tri0 m2s_analog_read;
+ tri0 m2s_analog_write;
+ tri0 [width_bwa-1:0] m2s_analog_address;
+ tri0 [31:0] m2s_analog_writedata;
+ wire [31:0] m2s_analog_readdata;
+ wire m2s_analog_waitrequest;
+
+ alt_xcvr_reconfig_analog_tgx sc_analog (
+ .reconfig_clk(mgmt_clk_clk),
+ .reset(mgmt_rst_reset),
+ // external mgmt interface facing
+ .analog_reconfig_address(reconfig_mgmt_address[width_awa-1:0]),
+ .analog_reconfig_writedata(reconfig_mgmt_writedata),
+ .analog_reconfig_write(reconfig_mgmt_write & r_decode[arb_analog]),
+ .analog_reconfig_read(reconfig_mgmt_read & r_decode[arb_analog]),
+ .analog_reconfig_readdata(sc_analog_readdata),
+ .analog_reconfig_waitrequest(sc_analog_waitrequest),
+ .analog_reconfig_done(analog_reconfig_done),
+ // master-to-slave fabric facing, to basic reconfig
+ .analog_reconfig_irq_from_base(basic_irq),
+ .analog_reconfig_waitrequest_from_base(m2s_analog_waitrequest),
+ .analog_reconfig_readdata_base(m2s_analog_readdata),
+ .analog_reconfig_address_base(scs_analog_address),
+ .analog_reconfig_writedata_base(scs_analog_writedata),
+ .analog_reconfig_write_base(scs_analog_write),
+ .analog_reconfig_read_base(scs_analog_read)
+ );
+
+ // master-to-slave access module
+ alt_xcvr_m2s #(
+ .width_addr(width_bwa),
+ .width_data(32)
+ ) m2s_analog (
+ .clock(mgmt_clk_clk),
+ .req(req[arb_analog]),
+ .grant(grant[arb_analog]),
+ // master ports, facing basic reconfig block
+ .m_read(scs_analog_read),
+ .m_write(scs_analog_write),
+ .m_address(scs_analog_address[2 +: width_bwa]), // drop 2 lower addr bits
+ .m_writedata(scs_analog_writedata),
+ .m_readdata(m2s_analog_readdata),
+ .m_waitrequest(m2s_analog_waitrequest),
+ // slave-side ports, from basic reconfig block
+ .s_readdata(basic_readdata),
+ .s_waitrequest(basic_waitrequest),
+ .s_read(m2s_analog_read),
+ .s_write(m2s_analog_write),
+ .s_address(m2s_analog_address),
+ .s_writedata(m2s_analog_writedata)
+ );
+
+ ///////////////////////////////////////////
+ // Sub-component: offset cancellation
+ // word address offset: +8 (0x20 in bytes)
+ ///////////////////////////////////////////
+
+ // Offset cancellation output ports:
+ wire offset_cancellation_done;
+ wire [width_bwa-1:0] scs_offset_address;
+ wire [31:0] scs_offset_writedata;
+ wire scs_offset_write;
+ wire scs_offset_read;
+
+ // Offset cancellation master-to-slave access fabric outputs
+ tri0 m2s_offset_read;
+ tri0 m2s_offset_write;
+ tri0 [width_bwa-1:0] m2s_offset_address;
+ tri0 [31:0] m2s_offset_writedata;
+ wire [31:0] m2s_offset_readdata;
+ wire m2s_offset_waitrequest;
+
+ alt_xcvr_reconfig_offset_cancellation #(
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces),
+ .device_family(l_dev_family)
+ ) sc_offset (
+ .reconfig_clk(mgmt_clk_clk),
+ .reset(mgmt_rst_reset),
+ // external mgmt interface facing
+ .offset_cancellation_address(reconfig_mgmt_address[0]), // slave uses a single address bit
+ .offset_cancellation_writedata(reconfig_mgmt_writedata),
+ .offset_cancellation_write(reconfig_mgmt_write & r_decode[arb_offset]),
+ .offset_cancellation_read(reconfig_mgmt_read & r_decode[arb_offset]),
+ .offset_cancellation_readdata(sc_offset_readdata),
+ .offset_cancellation_waitrequest(sc_offset_waitrequest),
+ // master-to-slave fabric facing, to basic reconfig
+ .offset_cancellation_irq_from_base(basic_irq),
+ .offset_cancellation_waitrequest_from_base(m2s_offset_waitrequest),
+ .offset_cancellation_readdata_base(m2s_offset_readdata),
+ .testbus_data(testbus_data),
+ .offset_cancellation_done(offset_cancellation_done),
+ .offset_cancellation_address_base(scs_offset_address),
+ .offset_cancellation_writedata_base(scs_offset_writedata),
+ .offset_cancellation_write_base(scs_offset_write),
+ .offset_cancellation_read_base(scs_offset_read)
+ );
+
+ // master-to-slave access module
+ alt_xcvr_m2s #(
+ .width_addr(width_bwa),
+ .width_data(32)
+ ) m2s_offset (
+ .clock(mgmt_clk_clk),
+ .req(req[arb_offset]),
+ .grant(grant[arb_offset]),
+ // master ports, facing basic reconfig block
+ .m_read(scs_offset_read),
+ .m_write(scs_offset_write),
+ .m_address(scs_offset_address), // drop 2 lower addr bits
+ .m_writedata(scs_offset_writedata),
+ .m_readdata(m2s_offset_readdata),
+ .m_waitrequest(m2s_offset_waitrequest),
+ // slave-side ports, from basic reconfig block
+ .s_readdata(basic_readdata),
+ .s_waitrequest(basic_waitrequest),
+ .s_read(m2s_offset_read),
+ .s_write(m2s_offset_write),
+ .s_address(m2s_offset_address),
+ .s_writedata(m2s_offset_writedata)
+ );
+
+ ///////////////////////////////////////////
+ // Sub-component: "EyeQ" eye monitor
+ // word address offset: +16 (0x40 in bytes)
+ ///////////////////////////////////////////
+
+ // Eyemon output ports:
+ wire eyemon_done;
+ wire [width_bwa+1:0] scs_eyemon_address;
+ wire [31:0] scs_eyemon_writedata;
+ wire scs_eyemon_write;
+ wire scs_eyemon_read;
+
+ // eyemon master-to-slave access fabric outputs
+ tri0 m2s_eyemon_read;
+ tri0 m2s_eyemon_write;
+ tri0 [width_bwa-1:0] m2s_eyemon_address;
+ tri0 [31:0] m2s_eyemon_writedata;
+ wire [31:0] m2s_eyemon_readdata;
+ wire m2s_eyemon_waitrequest;
+
+ alt_xcvr_reconfig_eyemon_tgx #(
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces),
+ .device_family(l_dev_family)
+ ) sc_eyemon (
+ .reconfig_clk(mgmt_clk_clk),
+ .reset(mgmt_rst_reset),
+ // external mgmt interface facing
+ .eyemon_address(reconfig_mgmt_address[width_awa-1:0]), // slave uses a 3-bit address
+ .eyemon_writedata(reconfig_mgmt_writedata),
+ .eyemon_write(reconfig_mgmt_write & r_decode[arb_eyemon]),
+ .eyemon_read(reconfig_mgmt_read & r_decode[arb_eyemon]),
+ .eyemon_readdata(sc_eyemon_readdata),
+ .eyemon_waitrequest(sc_eyemon_waitrequest),
+ // master-to-slave fabric facing, to basic reconfig
+ .eyemon_irq_from_base(basic_irq),
+ .eyemon_waitrequest_from_base(m2s_eyemon_waitrequest),
+ .eyemon_readdata_base(m2s_eyemon_readdata),
+ .eyemon_irq(eyemon_done),
+ .eyemon_address_base(scs_eyemon_address),
+ .eyemon_writedata_base(scs_eyemon_writedata),
+ .eyemon_write_base(scs_eyemon_write),
+ .eyemon_read_base(scs_eyemon_read)
+ );
+
+ // master-to-slave access module
+ alt_xcvr_m2s #(
+ .width_addr(width_bwa),
+ .width_data(32)
+ ) m2s_eyemon (
+ .clock(mgmt_clk_clk),
+ .req(req[arb_eyemon]),
+ .grant(grant[arb_eyemon]),
+ // master ports, facing basic reconfig block
+ .m_read(scs_eyemon_read),
+ .m_write(scs_eyemon_write),
+ .m_address(scs_eyemon_address[2 +: width_bwa]), // drop 2 lower addr bits
+ .m_writedata(scs_eyemon_writedata),
+ .m_readdata(m2s_eyemon_readdata),
+ .m_waitrequest(m2s_eyemon_waitrequest),
+ // slave-side ports, from basic reconfig block
+ .s_readdata(basic_readdata),
+ .s_waitrequest(basic_waitrequest),
+ .s_read(m2s_eyemon_read),
+ .s_write(m2s_eyemon_write),
+ .s_address(m2s_eyemon_address),
+ .s_writedata(m2s_eyemon_writedata)
+ );
+
+ ///////////////////////////////////////////
+ // Sub-component: DFE
+ // word address offset: +24 (0x60 in bytes)
+ ///////////////////////////////////////////
+
+ // DFE output ports:
+ wire dfe_done;
+ wire [width_bwa-1:0] scs_dfe_address;
+ wire [31:0] scs_dfe_writedata;
+ wire scs_dfe_write;
+ wire scs_dfe_read;
+
+ // dfe master-to-slave access fabric outputs
+ tri0 m2s_dfe_read;
+ tri0 m2s_dfe_write;
+ tri0 [width_bwa-1:0] m2s_dfe_address;
+ tri0 [31:0] m2s_dfe_writedata;
+ wire [31:0] m2s_dfe_readdata;
+ wire m2s_dfe_waitrequest;
+
+ alt_xcvr_reconfig_dfe_tgx #(
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces),
+ .device_family(l_dev_family)
+ ) sc_dfe (
+ .reconfig_clk(mgmt_clk_clk),
+ .reset(mgmt_rst_reset),
+ // external mgmt interface facing
+ .dfe_address(reconfig_mgmt_address[width_awa-1:0]), // slave uses a 3-bit address
+ .dfe_writedata(reconfig_mgmt_writedata),
+ .dfe_write(reconfig_mgmt_write & r_decode[arb_dfe]),
+ .dfe_read(reconfig_mgmt_read & r_decode[arb_dfe]),
+ .dfe_readdata(sc_dfe_readdata),
+ .dfe_waitrequest(sc_dfe_waitrequest),
+ // master-to-slave fabric facing, to basic reconfig
+ .dfe_irq_from_base(basic_irq),
+ .dfe_waitrequest_from_base(m2s_dfe_waitrequest),
+ .dfe_readdata_base(m2s_dfe_readdata),
+ .dfe_irq(dfe_done),
+ .dfe_address_base(scs_dfe_address),
+ .dfe_writedata_base(scs_dfe_writedata),
+ .dfe_write_base(scs_dfe_write),
+ .dfe_read_base(scs_dfe_read)
+ );
+
+ // master-to-slave access module
+ alt_xcvr_m2s #(
+ .width_addr(width_bwa),
+ .width_data(32)
+ ) m2s_dfe (
+ .clock(mgmt_clk_clk),
+ .req(req[arb_dfe]),
+ .grant(grant[arb_dfe]),
+ // master ports, facing basic reconfig block
+ .m_read(scs_dfe_read),
+ .m_write(scs_dfe_write),
+ .m_address(scs_dfe_address),
+ .m_writedata(scs_dfe_writedata),
+ .m_readdata(m2s_dfe_readdata),
+ .m_waitrequest(m2s_dfe_waitrequest),
+ // slave-side ports, from basic reconfig block
+ .s_readdata(basic_readdata),
+ .s_waitrequest(basic_waitrequest),
+ .s_read(m2s_dfe_read),
+ .s_write(m2s_dfe_write),
+ .s_address(m2s_dfe_address),
+ .s_writedata(m2s_dfe_writedata)
+ );
+
+
+ ///////////////////////////////////////////
+ // Outputs to basic block
+ ///////////////////////////////////////////
+ assign basic_address = m2s_analog_address | m2s_offset_address | m2s_eyemon_address | m2s_dfe_address;
+ assign basic_read = m2s_analog_read | m2s_offset_read | m2s_eyemon_read | m2s_dfe_read;
+ assign basic_write = m2s_analog_write | m2s_offset_write | m2s_eyemon_write | m2s_dfe_write;
+ assign basic_writedata = m2s_analog_writedata | m2s_offset_writedata | m2s_eyemon_writedata | m2s_dfe_writedata;
+
+ wire [number_of_reconfig_interfaces*8 - 1 : 0] aeq_fromgxb_data=0;
+ wire [number_of_reconfig_interfaces*24 - 1 : 0] aeq_togxb_data;
+
+ alt_xcvr_reconfig_basic_tgx #(
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces)
+ ) sc_basic (
+ .reconfig_clk(mgmt_clk_clk),
+ .reset(mgmt_rst_reset),
+ .basic_reconfig_write(basic_write),
+ .basic_reconfig_read(basic_read),
+ .basic_reconfig_writedata(basic_writedata),
+ .basic_reconfig_address(basic_address),
+ .basic_reconfig_fromgxb_data(reconfig_fromgxb),
+ .aeq_fromgxb_data(aeq_fromgxb_data),
+ .basic_reconfig_readdata(basic_readdata),
+ .basic_reconfig_waitrequest(basic_waitrequest),
+ .basic_reconfig_togxb_data(reconfig_togxb),
+ .aeq_togxb_data(aeq_togxb_data),
+ .testbus_data(testbus_data),
+ .basic_reconfig_irq(basic_irq)
+ );
+
+
+ ///////////////////////////////////////////
+ // Status to external mgmt interface
+ ///////////////////////////////////////////
+ assign reconfig_done = analog_reconfig_done | offset_cancellation_done | eyemon_done | dfe_done;
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_resync.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_resync.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5c723372b22da2640f7283962c5acdd598a91dfa
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/alt_xcvr_resync.sv
@@ -0,0 +1,98 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Module: alt_xcvr_resync
+//
+// Description:
+// A general purpose resynchronization module.
+//
+// Parameters:
+// SYNC_CHAIN_LENGTH
+// - Specifies the length of the synchronizer chain for metastability
+// retiming.
+// WIDTH
+// - Specifies the number of bits you want to synchronize. Controls the width of the
+// d and q ports.
+// SLOW_CLOCK - USE WITH CAUTION.
+// - Leaving this setting at its default will create a standard resynch circuit that
+// merely passes the input data through a chain of flip-flops. This setting assumes
+// that the input data has a pulse width longer than one clock cycle sufficient to
+// satisfy setup and hold requirements on at least one clock edge.
+// - By setting this to 1 (USE CAUTION) you are creating an asynchronous
+// circuit that will capture the input data regardless of the pulse width and
+// its relationship to the clock. However it is more difficult to apply static
+// timing constraints as it ties the data input to the clock input of the flop.
+// This implementation assumes the data rate is slow enough
+// INIT_VALUE
+// - Specifies the initial values of the synchronization registers.
+//
+// Apply embedded false path timing constraint
+(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_resync*sync_r[0]]\"" *)
+
+`timescale 1ps/1ps
+
+module alt_xcvr_resync #(
+ parameter SYNC_CHAIN_LENGTH = 2, // Number of flip-flops for retiming
+ parameter WIDTH = 1, // Number of bits to resync
+ parameter SLOW_CLOCK = 0, // See description above
+ parameter INIT_VALUE = 0
+ ) (
+ input wire clk,
+ input wire reset,
+ input wire [WIDTH-1:0] d,
+ output wire [WIDTH-1:0] q
+ );
+
+localparam INT_LEN = (SYNC_CHAIN_LENGTH > 0) ? SYNC_CHAIN_LENGTH : 1;
+localparam [INT_LEN-1:0] L_INIT_VALUE = (INIT_VALUE == 1) ? {INT_LEN{1'b1}} : {INT_LEN{1'b0}};
+
+genvar ig;
+
+// Generate a synchronizer chain for each bit
+generate begin
+ for(ig=0;ig<WIDTH;ig=ig+1) begin : resync_chains
+ wire d_in; // Input to sychronization chain.
+ reg [INT_LEN-1:0] sync_r = L_INIT_VALUE;
+ wire [INT_LEN :0] next_r; // One larger than real chain
+
+ assign q[ig] = sync_r[INT_LEN-1]; // Output signal
+ assign next_r = {sync_r,d_in};
+
+ always @(posedge clk or posedge reset)
+ if(reset)
+ sync_r <= L_INIT_VALUE;
+ else
+ sync_r <= next_r[INT_LEN-1:0];
+
+ // Generate asynchronous capture circuit if specified.
+ if(SLOW_CLOCK == 0) begin
+ assign d_in = d[ig];
+ end else begin
+ wire d_clk;
+ reg d_r = L_INIT_VALUE[0];
+ wire clr_n;
+
+ assign d_clk = d[ig];
+ assign d_in = d_r;
+ assign clr_n = ~q[ig] | d_clk; // Clear when output is logic 1 and input is logic 0
+
+ // Asynchronously latch the input signal.
+ always @(posedge d_clk or negedge clr_n)
+ if(!clr_n) d_r <= 1'b0;
+ else if(d_clk) d_r <= 1'b1;
+ end // SLOW_CLOCK
+ end // for loop
+end // generate
+endgenerate
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/altera_wait_generate.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/altera_wait_generate.v
new file mode 100644
index 0000000000000000000000000000000000000000..d11ec7e154387185d9a1d14b39c0410608a6c6ed
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/altera_wait_generate.v
@@ -0,0 +1,38 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module altera_wait_generate
+//#(
+//This code only works when wait_cycle =1, if need other case, you need to modify this code.
+//please set wait_cycle default value as 1 to keep old design works.
+// parameter wait_cycle =1
+// )
+(
+ input wire rst,
+ input wire clk,
+ input wire launch_signal,
+ output wire wait_req
+ );
+reg launch_reg = 0;
+reg wait_reg = 0;
+always @ (posedge clk, posedge rst) begin
+ if(rst) launch_reg <= 1'b0;
+ else launch_reg <= launch_signal;
+end
+always @ (posedge clk, posedge rst) begin
+ if(rst) wait_reg <= 1'b0;
+ else wait_reg <= launch_signal & launch_reg & (! wait_reg & !wait_req);
+end
+assign wait_req = (launch_signal & ~launch_reg) | (wait_reg & launch_signal ) ;
+endmodule
\ No newline at end of file
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/altera_xcvr_functions.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/altera_xcvr_functions.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5ef175a54cc3ce30e9dded8e494731600eb6ffda
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/altera_xcvr_functions.sv
@@ -0,0 +1,746 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common functions for transceiver PHY IP
+//
+// $Header$
+//
+// PACKAGE DECLARATION
+package altera_xcvr_functions;
+ localparam integer MAX_CHARS = 32;
+ localparam integer MAX_STRS = 16;
+ localparam integer MAX_XCVR_CHANNELS = 64;
+
+ // Reconfiguration bundle widths per family
+ localparam integer W_S5_RECONFIG_BUNDLE_TO_XCVR = 70;
+ localparam integer W_S5_RECONFIG_BUNDLE_FROM_XCVR = 46;
+ localparam integer W_A5_RECONFIG_BUNDLE_TO_XCVR = 70;
+ localparam integer W_A5_RECONFIG_BUNDLE_FROM_XCVR = 46;
+ localparam integer W_S4_RECONFIG_BUNDLE_TO_XCVR = 4;
+ localparam integer W_S4_RECONFIG_BUNDLE_FROM_XCVR = 17;
+ localparam integer W_C4_RECONFIG_BUNDLE_TO_XCVR = 4;
+ localparam integer W_C4_RECONFIG_BUNDLE_FROM_XCVR = 17;
+
+ // Reconfiguration bundle widths per family
+ localparam integer W_S5_RECONFIG_BUNDLE_TO_GXB = W_S5_RECONFIG_BUNDLE_TO_XCVR;
+ localparam integer W_S5_RECONFIG_BUNDLE_FROM_GXB = W_S5_RECONFIG_BUNDLE_FROM_XCVR;
+ localparam integer W_A5_RECONFIG_BUNDLE_TO_GXB = W_A5_RECONFIG_BUNDLE_TO_XCVR;
+ localparam integer W_A5_RECONFIG_BUNDLE_FROM_GXB = W_A5_RECONFIG_BUNDLE_FROM_XCVR;
+ localparam integer W_S4_RECONFIG_BUNDLE_TO_GXB = W_S4_RECONFIG_BUNDLE_TO_XCVR;
+ localparam integer W_S4_RECONFIG_BUNDLE_FROM_GXB = W_S4_RECONFIG_BUNDLE_FROM_XCVR;
+ localparam integer W_C4_RECONFIG_BUNDLE_TO_GXB = W_C4_RECONFIG_BUNDLE_TO_XCVR;
+ localparam integer W_C4_RECONFIG_BUNDLE_FROM_GXB = W_C4_RECONFIG_BUNDLE_FROM_XCVR;
+
+ // convert frequency string into integer Hz. Fractional Hz are truncated
+ // Must remain a constant function - can't use string.atoi().
+ function time str2hz (
+ input [8*MAX_CHARS:1] s
+ );
+
+ integer i;
+ integer c; // temp char storage for frequency conversion
+ integer unit_tens; // assume already Hz
+ integer is_numeric;
+ integer saw_dot;
+
+ reg [8:1] c_dot; // = ".";
+ reg [8:1] c_space; // = " ";
+ reg [8:1] c_a; // = 8'h61; //"a";
+ reg [8:1] c_z; // = 8'h7a; //"z";
+ reg [8*4:1] s_unit;
+ reg [8*MAX_CHARS:1] s_shift;
+
+ begin
+ // frequency ratio calculations
+ str2hz = 0;
+ unit_tens = 0; // assume already Hz
+ is_numeric = 1;
+ saw_dot = 0;
+ s_unit = "";
+
+ // Modelsim optimizer bug forces us to initialize these non-statically
+ c_dot = ".";
+ c_space = " ";
+ c_a = "a";
+ c_z = "z";
+ for (i=(MAX_CHARS-1); i>=0; i=i-1) begin
+ s_shift = (s >> (i*8));
+ c = s_shift[8:1] & 8'hff;
+ if (c > 0) begin
+ //$display("[%d] => '%1s',", i, c);
+ if (c >= 8'h30 && c <= 8'h39 && is_numeric) begin
+ str2hz = (str2hz * 10) + (c & 8'h0f);
+ if (saw_dot) unit_tens = unit_tens - 1; // count digits after decimal point
+ end else if (c == c_dot) saw_dot = 1;
+ else if (c != c_space) begin
+ is_numeric = 0; // stop accepting new numeric digits in value
+ // if it's a-z, convert to upper case A-Z
+ if (c >= c_a && c <= c_z) c = (c & 8'h5f); // convert a-z (lower) to A-Z (upper)
+ s_unit = (s_unit << 8) | c;
+ end
+ end
+ end
+ //$display("numeric = %d x 10**(%2d), unit = '%0s'", str2hz, unit_tens, s_unit);
+
+ // account for frequency unit
+ if (s_unit == "GHZ" || s_unit == "GBPS") unit_tens = unit_tens + 9; // 10**9
+ else if (s_unit == "MHZ" || s_unit == "MBPS") unit_tens = unit_tens + 6; // 10**6
+ else if (s_unit == "KHZ" || s_unit == "KBPS") unit_tens = unit_tens + 3; // 10**3
+ else if (s_unit != "HZ" && s_unit != "BPS") begin
+ $display("Invalid frequency unit '%0s', assuming %d x 10**(%2d) 'Hz'", s_unit, str2hz, unit_tens);
+ end
+ //$display("numeric in Hz = %d x 10**(%2d)", str2hz, unit_tens);
+
+ // align numeric to Hz
+ if (unit_tens < 0) begin
+ //str2hz = str2hz / (10**(-unit_tens));
+ for (i=0; i>unit_tens; i=i-1) begin
+ str2hz = str2hz / 10;
+ end
+ end else begin
+ //str2hz = str2hz * (10**unit_tens);
+ for (i=0; i<unit_tens; i=i+1) begin
+ str2hz = str2hz * 10;
+ end
+ end
+ //$display("%d Hz", str2hz);
+ end
+ endfunction
+
+ // convert integer Hz to a frequency string
+ // integer Hz as type time, and the frequency string will use MHz units
+ // Must remain a constant function - can't use $sformat or string.itoa().
+ function [MAX_CHARS*8-1:0] hz2str (
+ input time hz
+ );
+ integer pos;
+ integer f_unit; // 10**f_unit is offset from Hz for larger unit
+ time hz_mod_10;
+ begin
+ hz2str = "0.000000 MHz"; // minimum string value
+ f_unit = 6; // MHz offsets Hz value by 6 decimal digits
+
+ // convert time back to string with frequency units
+ // char positions 3 to 0 are used by " MHz", so start with digits at pos 4
+ for (pos = 4; pos < MAX_CHARS && hz > 0; pos = pos + 1) begin
+ if (f_unit == 0) begin
+ hz2str[pos*8 +: 8] = 8'h2e; // add "." character
+ pos = pos + 1;
+ end
+ f_unit = f_unit - 1;
+ hz_mod_10 = (hz % 10);
+ hz2str[pos*8 +: 8] = hz_mod_10[7:0] | 8'h30;
+ hz = hz / 10;
+ //$display("hz2str() => so far '%s', pos (%d), f_unit(%d) ", hz2str, pos, f_unit);
+ end
+ //$display("hz2str() returns '%s'", hz2str);
+ end
+ endfunction
+
+ // Convert a string to an integer
+ // Uses pre-existing str2hz function
+ function integer str2int(
+ input [MAX_CHARS*8-1:0] instring
+ );
+ time temp;
+ temp = str2hz({instring,"Hz"});
+ str2int = temp[31:0];
+ endfunction
+
+
+ // Convert an integer to a string
+ function [MAX_CHARS*8-1:0] int2str(
+ input integer in_int
+ );
+ integer i;
+ integer this_char;
+ i = 0;
+ int2str = "";
+ do
+ begin
+ this_char = (in_int % 10) + 48;
+ int2str[i*8+:8] = this_char[7:0];
+ i=i+1;
+ in_int = in_int / 10;
+ end
+ while(in_int > 0);
+ endfunction
+
+ // function to convert at most 40-bit long string to binary
+ function [39 : 0] m_str_to_bin;
+ input [40*8 : 1] s;
+ reg [40*8 : 1] reg_s;
+ reg [40:1] res;
+
+ integer m;
+ begin
+
+ reg_s = s;
+ for (m = 40; m > 0; m = m-1 )
+ begin
+ res[m] = reg_s[313];
+ reg_s = reg_s << 8;
+ end
+
+ m_str_to_bin = res;
+ end
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Verify that the string value is contained in the legal set.
+ //
+ // The 'set' can consist of a single string with no delimiters, e.g. "individual",
+ // or multiple values, separated by commas, and surrounded by parens, e.g. "(one,two,three,four,five)"
+ //
+ // Returns 1 if the value is in the set, and 0 otherwise
+ function integer is_in_legal_set(
+ input [MAX_CHARS*8-1:0] value,
+ input [MAX_STRS*MAX_CHARS*8-1:0] set
+ );
+ if (value == "<auto_any>")
+ is_in_legal_set = 1;
+ else if (value == "<auto_single>")
+ is_in_legal_set = (set[7:0] == 8'h29) ? 0 : 1; // 8'h29 is closing parenthesis char
+ else if (value == set)
+ is_in_legal_set = 1; // value matches single value in set
+ else begin
+ // check value against each in set
+ integer close_pos; // end of string marker can be comma or closing paren
+ integer open_pos; // open paren is start of set, if appropriate
+ reg [MAX_STRS*MAX_CHARS*8-1:0] legalstr;
+
+ is_in_legal_set = 0;
+ open_pos = MAX_STRS*MAX_CHARS-1;
+ // Remove closing parenthesis if exists
+ if(set[7:0] == 8'h29) begin
+ set = (set >> 8);
+ set[(MAX_STRS*MAX_CHARS*8-1)-:8] = 8'h00;
+ end
+ // look for first non-null and non open paren character
+ while (open_pos > 0 && (set[open_pos*8 +: 8] == 8'h00 || set[open_pos*8 +: 8] == 8'h28)) // look for first non-null
+ open_pos = open_pos - 1;
+
+ while (is_in_legal_set == 0 && open_pos >= 0) begin
+ close_pos = open_pos;
+ while (close_pos > 0
+ && set[close_pos*8 +: 8] != 8'h2c) // look for comma (8'h2c)
+ close_pos = close_pos - 1;
+ if (close_pos >= 0) begin
+ close_pos = close_pos == 0 ? 0 : close_pos + 1;
+ legalstr = ((set & ((1'b1 << open_pos*8+8)-1)) >> close_pos*8);
+ if (value == legalstr)
+ is_in_legal_set = 1;
+ end
+ open_pos = close_pos-2; // prepare to look for next legal string
+ end
+ end
+ //$display("is_in_legal_set(): returns %d", is_in_legal_set);
+ endfunction
+
+
+ // Accepts a string list of comma seperated numbers and returns a binary
+ // field where each bit indicates whether the index corresponding to that bit
+ // was found in the legal set.
+ //
+ // @param count - The number of integer indexes to check for in the set
+ // or the highest integer minus 1.
+ // @param set - The list containing the integer values to search for
+ // @return - A bitfield where each bit indicates whether the corresponding
+ // integer was found in the legal set.
+ function [MAX_XCVR_CHANNELS-1:0] map_numerical_is_in_legal_set(
+ input integer count,
+ input [MAX_STRS*MAX_CHARS*8-1:0] set
+ );
+ integer index;
+ reg [MAX_XCVR_CHANNELS-1:0] retval;
+
+ // Validate count parameter
+ if(count > MAX_XCVR_CHANNELS)
+ $display("Error: [map_numerical_is_in_legal_set]: Invalid value for count: %0d",count);
+
+ map_numerical_is_in_legal_set = {MAX_XCVR_CHANNELS{1'b0}};
+ retval = {MAX_XCVR_CHANNELS{1'b0}};
+ for(index = 0; index < count; index = index + 1) begin
+ if(is_in_legal_set(int2str(index),set))
+ retval = retval | (({MAX_XCVR_CHANNELS{1'b0}} | 1'b1) << index);
+ end
+ map_numerical_is_in_legal_set = retval;
+ endfunction
+
+
+ // Accepts a string list of comma seperated numbers and returns a binary
+ // field where each byte contains the corresponding number found in the
+ // list.
+ //
+ // @param count - The number of elements in the list.
+ // @param set - The list containing the integer values.
+ // @return - A bitfield where each byte contains the corresponding number found
+ // at that location in the list.
+ function [MAX_XCVR_CHANNELS*8-1:0] map_numerical_legal_set(
+ input integer count,
+ input [MAX_STRS*MAX_CHARS*8-1:0] set
+ );
+ integer index;
+ reg [MAX_XCVR_CHANNELS-1:0] retval;
+ reg [MAX_CHARS*8-1:0] str_val;
+ reg [7:0] int_val;
+
+ // Validate count parameter
+ if(count > MAX_XCVR_CHANNELS || count > 256)
+ $display("Error: [map_numerical_legal_set]: Invalid value for count: %0d",count);
+
+ map_numerical_legal_set = {MAX_XCVR_CHANNELS{8'd0}};
+ retval = {MAX_XCVR_CHANNELS{8'd0}};
+ for(index = 0; index < count; index = index + 1) begin
+ str_val = get_value_at_index(index,set);
+ if(str_val != "NA") begin
+ int_val = str2int(str_val);
+ if(int_val > 255)
+ $display("Error: [map_numerical_legal_set]: Invalid string contains non-numerical item or value:%0d",int_val);
+ else begin
+ retval = retval | ( ( {MAX_XCVR_CHANNELS{8'd0}} | int_val ) << (index * 8));
+ end
+ end
+ end
+ map_numerical_legal_set = retval;
+ endfunction
+
+
+ // Accepts a comma separated list of string values and returns the element
+ // found at the specified index. If the index is invalid, "NA" is returned
+ //
+ // @param index - The index of the value to return within "set"
+ // @param set - A comma separated list of string values. The entire list may
+ // be surrounded by parenthesis("(item0,item1,item2)")
+ function [MAX_CHARS*8-1:0] get_value_at_index(
+ input integer index,
+ input [MAX_STRS*MAX_CHARS*8-1:0] set
+ );
+ // check value against each in set
+ integer close_pos; // end of string marker can be comma or closing paren
+ integer open_pos; // open paren is start of set, if appropriate
+ reg [MAX_STRS*MAX_CHARS*8-1:0] legalstr;
+ integer cur_index = 0;
+
+ get_value_at_index = "";
+ legalstr = "NA";
+ cur_index = 0;
+ open_pos = MAX_STRS*MAX_CHARS-1;
+ // Remove closing parenthesis if exists
+ if(set[7:0] == 8'h29) begin
+ set = (set >> 8);
+ set[(MAX_STRS*MAX_CHARS*8-1)-:8] = 8'h00;
+ end
+ // Find the start of the string
+ while (open_pos >= 1 && (set[open_pos*8 +: 8] == 8'h00 || set[open_pos*8 +: 8] == 8'h28)) // look for first non-null
+ open_pos = open_pos - 1;
+
+ // Iterate through list until the string is found or we've reached the end of the list
+ while (legalstr == "NA" && open_pos >= 0 && cur_index <= index) begin
+ close_pos = open_pos;
+ // Move the close iterator to the end of the current value (or end of string)
+ while (close_pos > 0
+ && set[close_pos*8 +: 8] != 8'h2c) // look for comma (8'h2c)
+ close_pos = close_pos - 1;
+ if (close_pos >= 0) begin
+ close_pos = close_pos == 0 ? 0 : close_pos + 1;
+ if(index == cur_index) begin
+ legalstr = ((set & ((1'b1 << open_pos*8+8)-1)) >> close_pos*8);
+ end
+ open_pos = close_pos-2; // prepare to look for next legal string
+ end
+ cur_index = cur_index + 1;
+ end
+
+ cur_index = 0;
+ while(legalstr[cur_index*8+:8] != 0) begin
+ get_value_at_index[cur_index*8+:8] = legalstr[cur_index*8+:8];
+ cur_index = cur_index + 1;
+ end
+
+ //$display("is_in_legal_set(): returns %d", is_in_legal_set);
+ endfunction
+
+
+ ////////////////////////////////////////////////////////////////////////
+ // Calculate the minimum number of bits needed to hold an integer value
+ //
+ // Returns ceil_log2() value
+ localparam integer MAX_PRECISION = 32; // VCS requires this declaration outside the function
+ function integer ceil_log2;
+ input [MAX_PRECISION-1:0] input_num;
+ integer i;
+ reg [MAX_PRECISION-1:0] try_result;
+ begin
+ i = 0;
+ try_result = 1;
+ while ((try_result << i) < input_num && i < MAX_PRECISION)
+ i = i + 1;
+ ceil_log2 = i;
+ end
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Return current device family string for display purposes
+ `ifndef XCVR_DEV_FAM
+ `ifdef ALTERA_RESERVED_QIS_FAMILY
+ `define XCVR_DEV_FAM `ALTERA_RESERVED_QIS_FAMILY // synthesis: use QIS-defined value
+ `else
+ `define XCVR_DEV_FAM device_family // simulation: use passed-in value
+ `endif
+ `endif
+ function [MAX_CHARS*8-1:0] current_device_family (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ current_device_family = `XCVR_DEV_FAM;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Match device family against standard family name strings
+ //
+ // Returns 1 if the names feature is present in the given device family
+ function integer has_s4_style_hssi (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ has_s4_style_hssi = ( (`XCVR_DEV_FAM == "Stratix IV")
+ || (`XCVR_DEV_FAM == "Arria II")
+ || (`XCVR_DEV_FAM == "Cyclone IV GX") // not exact, but close enough
+ || (`XCVR_DEV_FAM == "Arria II GX")
+ || (`XCVR_DEV_FAM == "Arria II GZ")
+ || (`XCVR_DEV_FAM == "HardCopy IV")
+ ) ? 1 : 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Match device family against standard family name strings
+ //
+ // Returns 1 if the names feature is present in the given device family
+ function integer has_s5_style_hssi (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ has_s5_style_hssi = ( (`XCVR_DEV_FAM == "Stratix V")
+ ) ? 1 : 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Match device family against standard family name strings
+ //
+ // Returns 1 if the names feature is present in the given device family
+ function integer has_a5_style_hssi (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ has_a5_style_hssi = ( (`XCVR_DEV_FAM == "Arria V")
+ ) ? 1 : 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Match device family against standard family name strings
+ //
+ // Returns 1 if the names feature is present in the given device family
+ function integer has_c5_style_hssi (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ has_c5_style_hssi = ( (`XCVR_DEV_FAM == "Cyclone V")
+ ) ? 1 : 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Match device family against standard family name strings
+ //
+ // Returns 1 if the names feature is present in the given device family
+ function integer has_c4_style_hssi (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ has_c4_style_hssi = ( (`XCVR_DEV_FAM == "Cyclone IV GX")
+ ) ? 1 : 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_to_gxb bundle width for specified device family
+ //
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_to_gxb bundle for that family
+ function integer get_reconfig_to_gxb_width (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family))
+ get_reconfig_to_gxb_width = W_S5_RECONFIG_BUNDLE_TO_XCVR;
+ else if (has_s4_style_hssi(device_family))
+ get_reconfig_to_gxb_width = W_S4_RECONFIG_BUNDLE_TO_XCVR;
+ else if (has_c4_style_hssi(device_family))
+ get_reconfig_to_gxb_width = W_C4_RECONFIG_BUNDLE_TO_XCVR;
+ else
+ get_reconfig_to_gxb_width = 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_from_gxb bundle width for specified device family
+ //
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_gxb bundle for that family
+ function integer get_reconfig_from_gxb_width (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family))
+ get_reconfig_from_gxb_width = W_S5_RECONFIG_BUNDLE_FROM_XCVR;
+ else if (has_s4_style_hssi(device_family))
+ get_reconfig_from_gxb_width = W_S4_RECONFIG_BUNDLE_FROM_XCVR;
+ else if (has_c4_style_hssi(device_family))
+ get_reconfig_from_gxb_width = W_C4_RECONFIG_BUNDLE_FROM_XCVR;
+ else
+ get_reconfig_from_gxb_width = 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_to_xcvr total port width for specified device family
+ //
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_to_xcvr port for that family
+ function integer get_reconfig_to_width (
+ input [MAX_CHARS*8-1:0] device_family,
+ input integer reconfig_interfaces
+ );
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family))
+ get_reconfig_to_width = get_s5_reconfig_to_width(reconfig_interfaces);
+ else if (has_s4_style_hssi(device_family))
+ get_reconfig_to_width = W_S4_RECONFIG_BUNDLE_TO_XCVR;
+ else if (has_c4_style_hssi(device_family))
+ get_reconfig_to_width = W_C4_RECONFIG_BUNDLE_TO_XCVR;
+ else
+ get_reconfig_to_width = 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_to_xcvr total port width for Stratix V device family
+ //
+ function integer get_s5_reconfig_to_width (
+ input integer reconfig_interfaces
+ );
+ get_s5_reconfig_to_width = reconfig_interfaces * get_reconfig_to_gxb_width("Stratix V");
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_from_xcvr total port width for specified device family
+ //
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_reconfig_from_width (
+ input [MAX_CHARS*8-1:0] device_family,
+ input integer reconfig_interfaces
+ );
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family))
+ get_reconfig_from_width = reconfig_interfaces * get_reconfig_from_gxb_width(device_family);
+ else if (has_s4_style_hssi(device_family))
+ get_reconfig_from_width = reconfig_interfaces * get_reconfig_from_gxb_width(device_family);
+ else if (has_c4_style_hssi(device_family))
+ get_reconfig_from_width = reconfig_interfaces * get_reconfig_from_gxb_width(device_family);
+ else
+ get_reconfig_from_width = 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_from_xcvr total port width for Stratix V device family
+ //
+ function integer get_s5_reconfig_from_width (
+ input integer reconfig_interfaces
+ );
+ get_s5_reconfig_from_width = reconfig_interfaces * get_reconfig_from_gxb_width("Stratix V");
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get number of reconfig interfaces for Custom PHY
+ // NOTE - !!Has since been used by other PHY IP!!
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // @param lanes - Number of channels
+ // @param plls - Number of TX plls (per channel)
+ // @param bonded_group_size - Size of bonded group (1 or lanes)
+ // @param data_path_type - Abuse of function by overloading for ATT support
+ // - Carry on the abuse
+ //
+ // @return 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_custom_reconfig_interfaces(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer lanes,
+ input integer plls,
+ input integer bonded_group_size,
+ input [MAX_CHARS*8-1:0] data_path_type = "",
+ input [MAX_CHARS*8-1:0] bonded_mode = "xN"
+ );
+ integer reconfig_interfaces;
+ reconfig_interfaces = 0;
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family)) begin
+ // ATT specific calculations
+ if( data_path_type == "ATT" ) begin
+ if((operation_mode == "RX_ONLY") || (operation_mode == "rx_only") || (operation_mode == "Rx") || (operation_mode == "RX") || (operation_mode == "rx")) begin
+ reconfig_interfaces = lanes;
+ end else if((operation_mode == "TX_ONLY") || (operation_mode == "tx_only") || (operation_mode == "Tx") || (operation_mode == "TX") || (operation_mode == "tx")) begin
+ reconfig_interfaces = 2*lanes;
+ end else begin
+ reconfig_interfaces = 3*lanes;
+ end
+ end else begin
+ // Custom PHY calculations
+ if((operation_mode == "RX") || (operation_mode == "Rx") || (operation_mode == "rx_only"))
+ reconfig_interfaces = lanes;
+ else begin
+ bonded_group_size = (bonded_mode == "fb_compensation") ? 1 : bonded_group_size;
+ reconfig_interfaces = lanes+(plls*(lanes/bonded_group_size));
+ end
+ end
+ end
+ get_custom_reconfig_interfaces = reconfig_interfaces;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_to_xcvr total port width for Custom PHY
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // @param lanes - Number of transceiver channels
+ // @param plls - Number of plls per bonded group
+ // @param bonded_group_size - Size of bonded group (1 or lanes)
+ // @param data_path_type - Abuse of function to support ATT
+ //
+ // @return - 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_custom_reconfig_to_width(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer lanes,
+ input integer plls,
+ input integer bonded_group_size,
+ input [MAX_CHARS*8-1:0] data_path_type = "",
+ input [MAX_CHARS*8-1:0] bonded_mode = "xN"
+ );
+ integer reconfig_interfaces;
+ reconfig_interfaces = get_custom_reconfig_interfaces(device_family,operation_mode,lanes,plls,bonded_group_size, data_path_type, bonded_mode );
+ get_custom_reconfig_to_width = get_s5_reconfig_to_width(reconfig_interfaces);
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_from_xcvr total port width for Custom PHY
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // @param lanes - Number of transceiver channels
+ // @param plls - Number of plls per bonded group
+ // @param bonded_group_size - Size of bonded group (1 or lanes)
+ // @param data_path_type - Abuse of function to support ATT
+ //
+ // @return - 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_custom_reconfig_from_width(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer lanes,
+ input integer plls,
+ input integer bonded_group_size,
+ input [MAX_CHARS*8-1:0] data_path_type = "",
+ input [MAX_CHARS*8-1:0] bonded_mode = "xN"
+ );
+ integer reconfig_interfaces;
+ reconfig_interfaces = get_custom_reconfig_interfaces(device_family,operation_mode,lanes,plls,bonded_group_size, data_path_type, bonded_mode);
+ get_custom_reconfig_from_width = get_s5_reconfig_from_width(reconfig_interfaces);
+ endfunction
+
+
+ ////////////////////////////////////////////////////////////////////
+ // Start Interlaken Specific functions for calculating reconfig interfaces
+ // and reconfig_to_gxb, reconfig_from_gxb widths
+
+ ////////////////////////////////////////////////////////////////////
+ // Get number of reconfig interfaces for Interlaken PHY
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_interlaken_reconfig_interfaces(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer bonded_group_size,
+ input integer lanes
+ );
+ integer reconfig_interfaces;
+ integer xslices;
+ integer xremain;
+ integer totalplls;
+
+ reconfig_interfaces = 0;
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family)) begin
+ if((operation_mode == "RX") || (operation_mode == "Rx") || (operation_mode == "rx_only"))
+ reconfig_interfaces = lanes;
+ else begin
+ xslices = lanes/bonded_group_size;
+ xremain = lanes % bonded_group_size;
+
+ if (xremain >0)
+ totalplls = xslices +1;
+ else
+ totalplls = xslices;
+ reconfig_interfaces = lanes+totalplls;
+ end // else: !if((operation_mode == "RX") || (operation_mode == "Rx") || (operation_mode == "rx_only"))
+ end // if (has_s5_style_hssi(device_family))
+ get_interlaken_reconfig_interfaces = reconfig_interfaces;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_to_xcvr total port width for Interlaken PHY
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // @param lanes - Number of transceiver channels
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_interlaken_reconfig_to_width(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer bonded_group_size,
+ input integer lanes
+ );
+ integer reconfig_interfaces;
+ reconfig_interfaces = get_interlaken_reconfig_interfaces(device_family,operation_mode,bonded_group_size,lanes);
+ get_interlaken_reconfig_to_width = get_s5_reconfig_to_width(reconfig_interfaces);
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_from_xcvr total port width for Custom PHY
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_interlaken_reconfig_from_width(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer bonded_group_size,
+ input integer lanes
+ );
+ integer reconfig_interfaces;
+ reconfig_interfaces = get_interlaken_reconfig_interfaces(device_family,operation_mode,bonded_group_size,lanes);
+ get_interlaken_reconfig_from_width = get_s5_reconfig_from_width(reconfig_interfaces);
+ endfunction
+
+ // End Interlaken specific functions
+ ////////////////////////////////////////////////////////////////////
+
+
+
+
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/altera_xcvr_xaui.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/altera_xcvr_xaui.sv
new file mode 100644
index 0000000000000000000000000000000000000000..f5731672ef25f5db829bfa5138a5ea5bee0aec5c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/altera_xcvr_xaui.sv
@@ -0,0 +1,510 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//-----------------------------------------------------------------------------
+//
+// Description: alt_xaui static verilog top level
+//
+// Authors: bauyeung 7-Sep-2010
+// Modified: ishimony 13-Dec-2010
+//
+// Copyright (c) Altera Corporation 1997 - 2010
+// All rights reserved.
+//
+//
+//-----------------------------------------------------------------------------
+
+// have separate generate statements for each component
+
+`timescale 1 ps / 1 ps
+import altera_xcvr_functions::*;
+(* altera_attribute = "-name IP_TOOL_NAME __ACDS_IP_CORE_NAME__; -name IP_TOOL_VERSION __ACDS_VERSION_SHORT__" *)
+module altera_xcvr_xaui #(
+ parameter device_family = "Stratix IV", // default Stratix IV
+ parameter starting_channel_number = 0, // only applies to SIV
+ parameter interface_type = "Hard XAUI",
+ parameter data_rate = "3125 Mbps",
+ parameter xaui_pll_type = "CMU",
+ parameter BASE_DATA_RATE = "3125 Mbps",
+ parameter use_control_and_status_ports = 0,
+ parameter external_pma_ctrl_reconf = 0,
+ parameter recovered_clk_out = 0,
+ parameter number_of_interfaces = 1,
+ parameter reconfig_interfaces = 1,
+ parameter use_rx_rate_match = 0,
+ parameter tx_termination = "OCT_150_OHMS",
+ parameter tx_vod_selection = 1,
+ parameter tx_preemp_pretap = 0,
+ parameter tx_preemp_pretap_inv = 0,
+ parameter tx_preemp_tap_1 = 5,
+ parameter tx_preemp_tap_2 = 0,
+ parameter tx_preemp_tap_2_inv = 0,
+ parameter rx_common_mode = "0.82v",
+ parameter rx_termination = "OCT_150_OHMS",
+ parameter rx_eq_dc_gain = 0,
+ parameter rx_eq_ctrl = 14,
+ parameter mgmt_clk_in_mhz = 50
+) (
+ input wire pll_ref_clk,
+ input wire xgmii_tx_clk,
+ output wire xgmii_rx_clk,
+ output wire tx_clk312_5, // dxaui: pma tx out clock, 312.5Mhz
+ input wire phy_mgmt_clk,
+ input wire phy_mgmt_clk_reset,
+ input wire [8:0] phy_mgmt_address,
+ output wire phy_mgmt_waitrequest,
+ input wire phy_mgmt_read,
+ output wire [31:0] phy_mgmt_readdata,
+ input wire phy_mgmt_write,
+ input wire [31:0] phy_mgmt_writedata,
+ input wire [71:0] xgmii_tx_dc,
+ output wire [71:0] xgmii_rx_dc,
+ output wire [3:0] xaui_tx_serial_data,
+ input wire [3:0] xaui_rx_serial_data,
+ output wire rx_ready,
+ output wire tx_ready,
+ output wire [3:0] rx_recovered_clk, // rx recovered clock from cdr
+
+// only used if use_control_and_status_ports is set
+ input tri0 rx_analogreset,
+ input tri0 rx_digitalreset,
+ input tri0 tx_digitalreset,
+ output tri0 rx_channelaligned,
+ input tri0 [3:0] rx_invpolarity,
+ input tri0 [3:0] rx_set_locktodata,
+ input tri0 [3:0] rx_set_locktoref,
+ input tri0 [3:0] rx_seriallpbken,
+ input tri0 [3:0] tx_invpolarity,
+ output tri1 [3:0] rx_is_lockedtodata,
+ output tri0 [3:0] rx_phase_comp_fifo_error,
+ output tri1 [3:0] rx_is_lockedtoref,
+ output tri0 [3:0] rx_rlv,
+ output tri0 [3:0] rx_rmfifoempty,
+ output tri0 [3:0] rx_rmfifofull,
+ output tri0 [3:0] tx_phase_comp_fifo_error,
+ output tri0 [7:0] rx_disperr,
+ output tri0 [7:0] rx_errdetect,
+ output tri0 [7:0] rx_patterndetect,
+ output tri0 [7:0] rx_rmfifodatadeleted,
+ output tri0 [7:0] rx_rmfifodatainserted,
+ output tri0 [7:0] rx_runningdisp,
+ output tri0 [7:0] rx_syncstatus,
+
+
+// only used if external_pma_ctrl_reconf is set
+ output tri0 [altera_xcvr_functions::get_reconfig_from_width(device_family,reconfig_interfaces)-1:0] reconfig_from_xcvr,
+ input tri0 [altera_xcvr_functions::get_reconfig_to_width(device_family,reconfig_interfaces) -1:0] reconfig_to_xcvr,
+ output tri0 pll_locked,
+ input tri0 cal_blk_powerdown,
+ input tri0 gxb_powerdown,
+ input tri0 pll_powerdown
+// need to add all possible port/param combinations
+// these should be set to tri0/1 where possible, so unused ports don't need to be terminated by the user
+);
+
+import altera_xcvr_functions::*;
+
+localparam reconfig_out_width = altera_xcvr_functions::get_reconfig_from_width(device_family,reconfig_interfaces);
+localparam reconfig_in_width = altera_xcvr_functions::get_reconfig_to_width(device_family,reconfig_interfaces);
+
+ wire [reconfig_out_width -1:0] l_reconfig_from_xcvr; // local reconfig_from_xcvr
+ wire [reconfig_in_width -1:0] l_reconfig_to_xcvr; // local reconfig_to_xcvr
+
+ wire [7:0] sc_phy_address; // mgmt.address
+ wire sc_phy_waitrequest; // .waitrequest
+ wire sc_phy_read; // .read
+ wire [31:0] sc_phy_readdata; // .readdata
+ wire sc_phy_write; // .write
+
+ wire [6:0] sc_reconf_address; // mgmt.address
+ wire sc_reconf_waitrequest; // .waitrequest
+ wire sc_reconf_read; // .read
+ wire [31:0] sc_reconf_readdata; // .readdata
+ wire sc_reconf_write; // .write
+
+///////////////////////////////////////////////////////////////////////
+// Custom decoder for multiple slaves of phy-reconfig interface
+///////////////////////////////////////////////////////////////////////
+// should be consistent across all device families
+ alt_xcvr_mgmt2dec_phyreconfig mgmtdec_phyreconfig (
+ .mgmt_clk_reset (phy_mgmt_clk_reset),
+ .mgmt_clk (phy_mgmt_clk),
+
+ .mgmt_address (phy_mgmt_address),
+ .mgmt_read (phy_mgmt_read),
+ .mgmt_write (phy_mgmt_write),
+ .mgmt_readdata (phy_mgmt_readdata),
+ .mgmt_waitrequest (phy_mgmt_waitrequest),
+
+ // internal interface to 'top' phy block
+ .sc_phy_readdata (sc_phy_readdata),
+ .sc_phy_waitrequest (sc_phy_waitrequest),
+ .sc_phy_address (sc_phy_address),
+ .sc_phy_read (sc_phy_read),
+ .sc_phy_write (sc_phy_write),
+
+ // internal interface to 'top' reconfig block
+ .sc_reconf_readdata (sc_reconf_readdata),
+ .sc_reconf_waitrequest (sc_reconf_waitrequest),
+ .sc_reconf_address (sc_reconf_address),
+ .sc_reconf_read (sc_reconf_read),
+ .sc_reconf_write (sc_reconf_write)
+ );
+
+
+///////////////////////////////////////////////////////////////////////
+// alt_xcvr_reconfig
+///////////////////////////////////////////////////////////////////////
+// add generate statement for this
+// need to account for external pma reconfig
+ generate
+ if (external_pma_ctrl_reconf == 1) begin
+ assign l_reconfig_to_xcvr = reconfig_to_xcvr;
+ assign reconfig_from_xcvr = l_reconfig_from_xcvr;
+ end else if ((interface_type == "Hard XAUI") && ((device_family == "Stratix IV") || (device_family == "HardCopy IV") || (device_family == "Arria II GX") || (device_family == "Arria II GX") || (device_family == "Arria II GZ"))) begin
+ alt_xcvr_reconfig_siv #(
+ .number_of_reconfig_interfaces (1)
+ ) alt_xcvr_reconfig_0 (
+ .mgmt_clk_clk (phy_mgmt_clk),
+ .mgmt_rst_reset (phy_mgmt_clk_reset),
+ .reconfig_mgmt_address (sc_reconf_address),
+ .reconfig_mgmt_waitrequest (sc_reconf_waitrequest),
+ .reconfig_mgmt_read (sc_reconf_read),
+ .reconfig_mgmt_readdata (sc_reconf_readdata),
+ .reconfig_mgmt_write (sc_reconf_write),
+ .reconfig_mgmt_writedata (phy_mgmt_writedata),
+ .reconfig_togxb (l_reconfig_to_xcvr),
+ .reconfig_fromgxb (l_reconfig_from_xcvr[16:0])
+ );
+ end else if ((interface_type == "Soft XAUI") && ((device_family == "Stratix IV") || (device_family == "HardCopy IV"))) begin // Arria II GX/GZ don't support soft xaui
+ alt_xcvr_reconfig_siv #(
+ .number_of_reconfig_interfaces (4)
+ ) alt_xcvr_reconfig_0 (
+ .mgmt_clk_clk (phy_mgmt_clk),
+ .mgmt_rst_reset (phy_mgmt_clk_reset),
+ .reconfig_mgmt_address (sc_reconf_address),
+ .reconfig_mgmt_waitrequest (sc_reconf_waitrequest),
+ .reconfig_mgmt_read (sc_reconf_read),
+ .reconfig_mgmt_readdata (sc_reconf_readdata),
+ .reconfig_mgmt_write (sc_reconf_write),
+ .reconfig_mgmt_writedata (phy_mgmt_writedata),
+ .reconfig_togxb (l_reconfig_to_xcvr),
+ .reconfig_fromgxb (l_reconfig_from_xcvr)
+ );
+ end else if ((interface_type == "DDR XAUI") && (device_family == "Stratix IV")) begin
+ // stub for now - nothing here
+ end else if (device_family == "Stratix V") begin
+ // stub for now - nothing here
+ assign l_reconfig_to_xcvr = reconfig_to_xcvr;
+ assign reconfig_from_xcvr = l_reconfig_from_xcvr;
+ end else if (device_family == "Cyclone IV GX") begin
+ alt_xcvr_reconfig_civ #(
+ .number_of_reconfig_interfaces (1)
+ ) alt_xcvr_reconfig_0 (
+ .reconfig_mgmt_clk_clk (phy_mgmt_clk),
+ .reconfig_mgmt_rst_reset (phy_mgmt_clk_reset),
+ .reconfig_mgmt_address (sc_reconf_address),
+ .reconfig_mgmt_waitrequest (sc_reconf_waitrequest),
+ .reconfig_mgmt_read (sc_reconf_read),
+ .reconfig_mgmt_readdata (sc_reconf_readdata),
+ .reconfig_mgmt_write (sc_reconf_write),
+ .reconfig_mgmt_writedata (phy_mgmt_writedata),
+ .reconfig_togxb (l_reconfig_to_xcvr),
+ .reconfig_fromgxb (l_reconfig_from_xcvr[16:0])
+ );
+ end
+ endgenerate
+
+///////////////////////////////////////////////////////////////////////
+// alt_xaui_phy - Integrates hxaui (i/f to hxaui_alt_c3gxb), csr, pma
+// controller and pma channel controller
+///////////////////////////////////////////////////////////////////////
+ generate
+ if (device_family == "Stratix V") begin
+ sv_xcvr_xaui #(
+ .device_family (device_family),
+ .starting_channel_number (starting_channel_number),
+ .interface_type (interface_type),
+ .reconfig_interfaces (reconfig_interfaces),
+ .sys_clk_in_mhz (mgmt_clk_in_mhz),
+ .data_rate (data_rate),
+ .xaui_pll_type (xaui_pll_type),
+ .BASE_DATA_RATE (BASE_DATA_RATE),
+ .use_control_and_status_ports (use_control_and_status_ports),
+ .tx_termination (tx_termination),
+ .rx_termination (rx_termination),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv (tx_preemp_pretap_inv),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv (tx_preemp_tap_2_inv),
+ .tx_vod_selection (tx_vod_selection),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .rx_common_mode (rx_common_mode),
+ .bonded_group_size (4), /// allowed values 1=> non-bonded 4=> bonded
+ .bonded_mode ("xN") /// allowed values "xN" and "fb_compensation"
+ ) alt_xaui_phy (
+ .pll_ref_clk (pll_ref_clk), // refclk.clk
+ .xgmii_tx_clk (xgmii_tx_clk), // xgmii_tx_clk.clk
+ .xgmii_rx_clk (xgmii_rx_clk), // xgmii_rx_clk.clk
+ .phy_mgmt_clk (phy_mgmt_clk), // mgmt_clk.clk
+ .phy_mgmt_clk_reset (phy_mgmt_clk_reset), // mgmt_clk_rst.reset_n
+ .phy_mgmt_address (sc_phy_address), // phy_mgmt.address
+ .phy_mgmt_waitrequest (sc_phy_waitrequest), // .waitrequest
+ .phy_mgmt_read (sc_phy_read), // .read
+ .phy_mgmt_readdata (sc_phy_readdata), // .readdata
+ .phy_mgmt_write (sc_phy_write), // .write
+ .phy_mgmt_writedata (phy_mgmt_writedata), // .writedata
+ .xgmii_tx_dc (xgmii_tx_dc), // xgmii_tx_dc.data
+ .xgmii_rx_dc (xgmii_rx_dc), // xgmii_rx_dc.data
+ .xaui_tx_serial_data (xaui_tx_serial_data), // xaui_tx_serial.export
+ .xaui_rx_serial_data (xaui_rx_serial_data), // xaui_rx_serial.export
+ .rx_digitalreset (rx_digitalreset), // rx_digitalreset.data
+ .tx_digitalreset (tx_digitalreset), // tx_digitalreset.data
+ .rx_channelaligned (rx_channelaligned), // rx_channelaligned.data
+ .rx_syncstatus (rx_syncstatus), // rx_syncstatus.data
+ .rx_disperr (rx_disperr), // rx_disperr.data
+ .rx_errdetect (rx_errdetect), // rx_errdetect.data
+ .rx_ready (rx_ready), // rx_pma_ready.data
+ .tx_ready (tx_ready), // tx_pma_ready.data
+ .reconfig_to_xcvr (l_reconfig_to_xcvr),
+ .reconfig_from_xcvr (l_reconfig_from_xcvr),
+ .rx_recovered_clk (rx_recovered_clk)
+ );
+ end else if ((interface_type == "DDR XAUI") && (device_family == "Stratix IV")) begin
+ dxaui_siv #(
+ .device_family (device_family),
+ .starting_channel_number (starting_channel_number),
+ .interface_type (interface_type),
+ .number_of_interfaces (1),
+ .reconfig_interfaces (reconfig_interfaces),
+ .sys_clk_in_mhz (mgmt_clk_in_mhz),
+ .xaui_pll_type (xaui_pll_type),
+ .use_control_and_status_ports (use_control_and_status_ports),
+ .external_pma_ctrl_reconf (external_pma_ctrl_reconf),
+ .tx_termination (tx_termination),
+ .tx_vod_selection (tx_vod_selection),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv (tx_preemp_pretap_inv),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv (tx_preemp_tap_2_inv),
+ .rx_common_mode (rx_common_mode),
+ .rx_termination (rx_termination),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .use_rx_rate_match (use_rx_rate_match)
+) dxaui_siv (
+ .pll_ref_clk (pll_ref_clk), // i
+ .xgmii_tx_clk (xgmii_tx_clk), // i
+ .xgmii_rx_clk (xgmii_rx_clk), // o
+ .tx_clk312_5 (tx_clk312_5), // o
+ .phy_mgmt_clk (phy_mgmt_clk), // i
+ .phy_mgmt_clk_reset (phy_mgmt_clk_reset), // i
+ .phy_mgmt_address (sc_phy_address), // i
+ .phy_mgmt_waitrequest (sc_phy_waitrequest), // o
+ .phy_mgmt_read (sc_phy_read), // i
+ .phy_mgmt_readdata (sc_phy_readdata), // o
+ .phy_mgmt_write (sc_phy_write), // i
+ .phy_mgmt_writedata (phy_mgmt_writedata), // i
+ .xgmii_tx_dc (xgmii_tx_dc), // i
+ .xgmii_rx_dc (xgmii_rx_dc), // o
+ .xaui_tx_serial_data (xaui_tx_serial_data), // o
+ .xaui_rx_serial_data (xaui_rx_serial_data), // i
+ .rx_ready (rx_ready), // o
+ .tx_ready (tx_ready), // o
+ .rx_recovered_clk (rx_recovered_clk), // o
+ .reconfig_from_xcvr (l_reconfig_from_xcvr), // o
+ .reconfig_to_xcvr (l_reconfig_to_xcvr), // i
+ .rx_analogreset (rx_analogreset), // i
+ .rx_digitalreset (rx_digitalreset), // i
+ .tx_digitalreset (tx_digitalreset), // i
+ .rx_channelaligned (rx_channelaligned), // o
+ .rx_invpolarity (rx_invpolarity), // i
+ .rx_set_locktodata (rx_set_locktodata), // i
+ .rx_set_locktoref (rx_set_locktoref), // i
+ .rx_seriallpbken (rx_seriallpbken), // i
+ .tx_invpolarity (tx_invpolarity), // i
+ .rx_is_lockedtodata (rx_is_lockedtodata), // o
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error), // o
+ .rx_is_lockedtoref (rx_is_lockedtoref), // o
+ .rx_rlv (rx_rlv), // o
+ .rx_rmfifoempty (rx_rmfifoempty), // o
+ .rx_rmfifofull (rx_rmfifofull), // o
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error), // o
+ .rx_disperr (rx_disperr), // o
+ .rx_errdetect (rx_errdetect), // o
+ .rx_patterndetect (rx_patterndetect), // o
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted), // o
+ .rx_rmfifodatainserted (rx_rmfifodatainserted), // o
+ .rx_runningdisp (rx_runningdisp), // o
+ .rx_syncstatus (rx_syncstatus), // o
+ .pll_locked (pll_locked), // o
+ .cal_blk_powerdown (cal_blk_powerdown), // i
+ .gxb_powerdown (gxb_powerdown), // i
+ .pll_powerdown (pll_powerdown) // i
+); // module dxaui_siv
+ end else if ((device_family == "Stratix IV") || (device_family == "HardCopy IV") ||(device_family == "Arria II GX") || (device_family == "Arria II GZ")) begin
+ siv_xcvr_xaui #(
+ .device_family (device_family),
+ .starting_channel_number (starting_channel_number),
+ .interface_type (interface_type),
+ .number_of_interfaces (1),
+ .reconfig_interfaces (reconfig_interfaces),
+ .sys_clk_in_mhz (mgmt_clk_in_mhz),
+ .xaui_pll_type (xaui_pll_type),
+ .use_control_and_status_ports (use_control_and_status_ports),
+ .external_pma_ctrl_reconf (external_pma_ctrl_reconf),
+ .tx_termination (tx_termination),
+ .rx_termination (rx_termination),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv (tx_preemp_pretap_inv),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv (tx_preemp_tap_2_inv),
+ .tx_vod_selection (tx_vod_selection),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .rx_common_mode (rx_common_mode)
+ ) xaui_phy (
+ .pll_ref_clk (pll_ref_clk),
+ .xgmii_rx_clk (xgmii_rx_clk),
+ .xgmii_tx_clk (xgmii_tx_clk),
+ .phy_mgmt_clk (phy_mgmt_clk),
+ .phy_mgmt_clk_reset (phy_mgmt_clk_reset),
+ .phy_mgmt_address (sc_phy_address),
+ .phy_mgmt_read (sc_phy_read),
+ .phy_mgmt_readdata (sc_phy_readdata),
+ .phy_mgmt_waitrequest (sc_phy_waitrequest),
+ .phy_mgmt_write (sc_phy_write),
+ .phy_mgmt_writedata (phy_mgmt_writedata),
+ .xaui_rx_serial_data (xaui_rx_serial_data),
+ .xaui_tx_serial_data (xaui_tx_serial_data),
+ .xgmii_rx_dc (xgmii_rx_dc),
+ .xgmii_tx_dc (xgmii_tx_dc),
+ .rx_ready (rx_ready),
+ .tx_ready (tx_ready),
+ .rx_recovered_clk (rx_recovered_clk), //o
+ .reconfig_from_xcvr (l_reconfig_from_xcvr),
+ .reconfig_to_xcvr (l_reconfig_to_xcvr),
+
+// optional control and status ports - will be terminated by tri0 if unconnected
+ .rx_analogreset (rx_analogreset), // input wire
+ .rx_digitalreset (rx_digitalreset), // input wire [3:0]
+ .tx_digitalreset (tx_digitalreset), // input wire [3:0]
+ .rx_channelaligned (rx_channelaligned), // output wire
+ .rx_invpolarity (rx_invpolarity), // input wire [3:0]
+ .rx_set_locktodata (rx_set_locktodata), // input wire [3:0]
+ .rx_set_locktoref (rx_set_locktoref), // input wire [3:0]
+ .rx_seriallpbken (rx_seriallpbken), // input wire [3:0]
+ .tx_invpolarity (tx_invpolarity), // input wire [3:0]
+ .rx_is_lockedtodata (rx_is_lockedtodata), // output wire [3:0]
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error), // output wire [3:0]
+ .rx_is_lockedtoref (rx_is_lockedtoref), // output wire [3:0]
+ .rx_rlv (rx_rlv), // output wire [3:0]
+ .rx_rmfifoempty (rx_rmfifoempty), // output wire [3:0]
+ .rx_rmfifofull (rx_rmfifofull), // output wire [3:0]
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error), // output wire [3:0]
+ .rx_disperr (rx_disperr), // output wire [7:0]
+ .rx_errdetect (rx_errdetect), // output wire [7:0]
+ .rx_patterndetect (rx_patterndetect), // output wire [7:0]
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted), // output wire [7:0]
+ .rx_rmfifodatainserted (rx_rmfifodatainserted), // output wire [7:0]
+ .rx_runningdisp (rx_runningdisp), // output wire [7:0]
+ .rx_syncstatus (rx_syncstatus), // output wire [7:0]
+
+// external_pma_ctrl_reconf
+ .pll_locked (pll_locked), // output wire
+ .cal_blk_powerdown (cal_blk_powerdown), // input wire
+ .gxb_powerdown (gxb_powerdown), // input wire
+ .pll_powerdown (pll_powerdown) // input wire
+ );
+ end else if (device_family == "Cyclone IV GX") begin
+// need to add the extra optional ports for c&s and ext_pma
+ civ_xcvr_xaui #(
+ .device_family (device_family),
+ .starting_channel_number (starting_channel_number),
+ .interface_type (interface_type),
+ .number_of_interfaces (1),
+ .sys_clk_in_mhz (mgmt_clk_in_mhz),
+ .xaui_pll_type (xaui_pll_type),
+ .use_control_and_status_ports (use_control_and_status_ports),
+ .tx_termination (tx_termination),
+ .rx_termination (rx_termination),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv (tx_preemp_pretap_inv),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv (tx_preemp_tap_2_inv),
+ .tx_vod_selection (tx_vod_selection),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .rx_common_mode (rx_common_mode)
+ ) xaui_phy (
+ .pll_ref_clk (pll_ref_clk),
+ .xgmii_rx_clk (xgmii_rx_clk),
+ .xgmii_tx_clk (xgmii_tx_clk),
+ .phy_mgmt_clk (phy_mgmt_clk),
+ .phy_mgmt_clk_reset (phy_mgmt_clk_reset),
+ .phy_mgmt_address (sc_phy_address),
+ .phy_mgmt_read (sc_phy_read),
+ .phy_mgmt_readdata (sc_phy_readdata),
+ .phy_mgmt_waitrequest (sc_phy_waitrequest),
+ .phy_mgmt_write (sc_phy_write),
+ .phy_mgmt_writedata (phy_mgmt_writedata),
+ .xaui_rx_serial_data (xaui_rx_serial_data),
+ .xaui_tx_serial_data (xaui_tx_serial_data),
+ .xgmii_rx_dc (xgmii_rx_dc),
+ .xgmii_tx_dc (xgmii_tx_dc),
+ .rx_ready (rx_ready),
+ .tx_ready (tx_ready),
+ .rx_recovered_clk (rx_recovered_clk), //o
+ .reconfig_from_xcvr (l_reconfig_from_xcvr[16:0]),
+ .reconfig_to_xcvr (l_reconfig_to_xcvr),
+
+// optional control and status ports - will be terminated by tri0 if unconnected
+ .rx_analogreset (rx_analogreset), // input wire
+ .rx_digitalreset (rx_digitalreset), // input wire [3:0]
+ .tx_digitalreset (tx_digitalreset), // input wire [3:0]
+ .rx_channelaligned (rx_channelaligned), // output wire
+ .rx_invpolarity (rx_invpolarity), // input wire [3:0]
+ .rx_set_locktodata (rx_set_locktodata), // input wire [3:0]
+ .rx_set_locktoref (rx_set_locktoref), // input wire [3:0]
+ .rx_seriallpbken (rx_seriallpbken), // input wire [3:0]
+ .tx_invpolarity (tx_invpolarity), // input wire [3:0]
+ .rx_is_lockedtodata (rx_is_lockedtodata), // output wire [3:0]
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error), // output wire [3:0]
+ .rx_is_lockedtoref (rx_is_lockedtoref), // output wire [3:0]
+ .rx_rlv (rx_rlv), // output wire [3:0]
+ .rx_rmfifoempty (rx_rmfifoempty), // output wire [3:0]
+ .rx_rmfifofull (rx_rmfifofull), // output wire [3:0]
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error), // output wire [3:0]
+ .rx_disperr (rx_disperr), // output wire [7:0]
+ .rx_errdetect (rx_errdetect), // output wire [7:0]
+ .rx_patterndetect (rx_patterndetect), // output wire [7:0]
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted), // output wire [7:0]
+ .rx_rmfifodatainserted (rx_rmfifodatainserted), // output wire [7:0]
+ .rx_runningdisp (rx_runningdisp), // output wire [7:0]
+ .rx_syncstatus (rx_syncstatus), // output wire [7:0]
+
+// external_pma_ctrl_reconf
+ .pll_locked (pll_locked), // output wire
+ .cal_blk_powerdown (cal_blk_powerdown), // input wire
+ .gxb_powerdown (gxb_powerdown), // input wire
+ .pll_powerdown (pll_powerdown) // input wire
+ );
+ end
+ endgenerate
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/cadence_files.txt b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/cadence_files.txt
new file mode 100644
index 0000000000000000000000000000000000000000..96175539fe10e847160e3bb13c7980081beae5b3
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/cadence_files.txt
@@ -0,0 +1,34 @@
+./altera_xcvr_functions.sv
+./altera_xcvr_xaui.sv
+./hxaui_csr_h.sv
+./hxaui_csr.sv
+./alt_xcvr_mgmt2dec_phyreconfig.sv
+./alt_xcvr_mgmt2dec_xaui.sv
+./alt_pma_ch_controller_tgx.v
+./alt_pma_controller_tgx.v
+./alt_reset_ctrl_lego.sv
+./alt_reset_ctrl_tgx_cdrauto.sv
+./alt_xcvr_resync.sv
+./alt_xcvr_csr_common_h.sv
+./alt_xcvr_csr_common.sv
+./alt_xcvr_csr_pcs8g_h.sv
+./alt_xcvr_csr_pcs8g.sv
+./alt_xcvr_csr_selector.sv
+./alt_xcvr_mgmt2dec.sv
+./altera_wait_generate.v
+./hxaui_alt4gxb.v
+./hxaui.v
+./siv_xcvr_xaui.sv
+./alt_xcvr_reconfig_h.sv
+./alt_xcvr_reconfig_siv.sv
+./alt_xcvr_reconfig_analog.sv
+./alt_xcvr_reconfig_analog_tgx.v
+./alt_xcvr_reconfig_offset_cancellation.sv
+./alt_xcvr_reconfig_offset_cancellation_tgx.v
+./alt_xcvr_reconfig_eyemon_tgx.sv
+./alt_xcvr_reconfig_dfe_tgx.sv
+./alt_xcvr_reconfig_basic_tgx.v
+./alt_mutex_acq.v
+./alt_dprio.v
+./alt_xcvr_arbiter.sv
+./alt_xcvr_m2s.sv
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/hxaui.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/hxaui.v
new file mode 100644
index 0000000000000000000000000000000000000000..de12fe1dceb673e679f042133e3e4c48d0c3e778
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/hxaui.v
@@ -0,0 +1,499 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//-----------------------------------------------------------------------------
+//
+// Description: hxaui - instantiates hard xaui and shim layer
+//
+// Authors: ishimony 14-Jan-2009
+//
+// Copyright (c) Altera Corporation 1997 - 2009
+// All rights reserved.
+//
+// //
+//-----------------------------------------------------------------------------
+
+`timescale 1 ps / 1 ps
+
+module hxaui(
+ xgmii_tx_clk, refclk, xgmii_tx_dc, xgmii_rx_clk, xgmii_rx_dc, xaui_rx_serial,
+ xaui_tx_serial, rx_analogreset, rx_digitalreset,
+ tx_digitalreset, rx_channelaligned, rx_invpolarity, rx_set_locktodata,
+ rx_set_locktoref, rx_seriallpbken, tx_invpolarity, rx_is_lockedtodata,
+ rx_phase_comp_fifo_error, rx_is_lockedtoref, rx_rlv, rx_rmfifoempty,
+ rx_rmfifofull, tx_phase_comp_fifo_error, rx_disperr, rx_errdetect,
+ rx_patterndetect, rx_rmfifodatadeleted, rx_rmfifodatainserted, rx_recovered_clk,
+ rx_runningdisp, rx_syncstatus, reconfig_togxb, reconfig_fromgxb,
+ reconfig_clk, cal_blk_clk, cal_blk_powerdown,
+ gxb_powerdown, pll_powerdown, pll_locked, r_cal_blk_powerdown,
+ r_gxb_powerdown, r_pll_powerdown, r_rx_set_locktodata, r_rx_set_locktoref,
+ r_rx_seriallpbken, r_rx_analogreset, r_rx_digitalreset, r_tx_digitalreset,
+ r_rx_invpolarity, r_tx_invpolarity
+); // module hxaui
+
+// parameters --------------------------------------------------------------
+parameter starting_channel_number = 0;
+parameter xaui_pll_type = "CMU"; // values: CMU/LCTANK
+parameter use_control_and_status_ports = "true";
+parameter device_family = "Stratix IV";
+parameter external_pma_ctrl_reconf = "true";
+
+ //analog parameters
+parameter tx_termination = "OCT_100_OHMS"; //Valid values for SIV/AII - OCT_85_OHMS,OCT_100_OHMS,OCT_120_OHMS,OCT_150_OHMS
+ //Valid values for CIV - OCT_100_OHMS,OCT_150_OHMS
+parameter rx_termination = "OCT_100_OHMS"; //Valid values for SIV/AII - OCT_85_OHMS,OCT_100_OHMS,OCT_120_OHMS,OCT_150_OHMS
+ //Valid values for CIV - OCT_100_OHMS,OCT_150_OHMS
+parameter rx_common_mode = "0.82v";
+
+parameter tx_preemp_pretap = 0;//0-7
+parameter tx_preemp_pretap_inv = "FALSE";//TRUE or FALSE.
+parameter tx_preemp_tap_1 = 5; //Valid values for SIV/AII - 0-15
+ //Valid values for CIV - 0-31
+parameter tx_preemp_tap_2 = 0; //0-7
+parameter tx_preemp_tap_2_inv = "FALSE";//TRUE or FALSE.
+parameter tx_vod_selection = 1;//0-7
+
+parameter rx_eq_dc_gain = 0; //Valid values for SIV/AII - 0-4
+ //Valid values for CIV - 0-3
+parameter rx_eq_ctrl = 14;//0-16
+
+
+localparam rx_term = ((rx_termination == "OCT_85_OHMS") ? "OCT 85 OHMS" : ((rx_termination == "OCT_100_OHMS") ? "OCT 100 OHMS" :
+ ((rx_termination == "OCT_120_OHMS") ? "OCT 120 OHMS" : ((rx_termination == "OCT_150_OHMS") ? "OCT 150 OHMS" : "NONE"))));
+localparam tx_term = ((tx_termination == "OCT_85_OHMS") ? "OCT 85 OHMS" : ((tx_termination == "OCT_100_OHMS") ? "OCT 100 OHMS" :
+ ((tx_termination == "OCT_120_OHMS") ? "OCT 120 OHMS" : ((tx_termination == "OCT_150_OHMS") ? "OCT 150 OHMS" : "NONE"))));
+localparam tx_preemp_ptinv = (tx_preemp_pretap_inv == 1) ? "TRUE" : "FALSE";
+localparam tx_preemp_t2inv = (tx_preemp_tap_2_inv == 1) ? "TRUE" : "FALSE";
+
+/*Equalization settings*/
+/*Deepak - Found an SPR (287703) that says there is a difference in legality check between SIV and AII. Arria II has a restricted equalization and preemphasis setting. In the case of equalization, EQA, B,C, D and V can all be 0 or 1 whereas on TGX they can all be 0 to 7. Recheck with Brian on whether the following code is the correct way to change it*/
+
+// Arria II GZ uses SIV EQ settings, so don't add it to this if statement
+localparam rx_eqa_ctrl = (device_family=="Arria II GX") ? ((rx_eq_ctrl >10)? 1 :0) : ((rx_eq_ctrl >10)? 7 :0);
+localparam rx_eqb_ctrl = (device_family=="Arria II GX") ? ((rx_eq_ctrl >6) ? 1 :0) : ((rx_eq_ctrl >6) ? 7 :0);
+localparam rx_eqc_ctrl = (device_family=="Arria II GX") ? ((rx_eq_ctrl >3) ? 1 :0) : ((rx_eq_ctrl >3) ? 7 :0);
+localparam rx_eqd_ctrl = (device_family=="Arria II GX") ? ((rx_eq_ctrl >0) ? 1 :0) : ((rx_eq_ctrl >0) ? 7 :0);
+localparam rx_eqv_ctrl = (device_family=="Arria II GX") ? (((rx_eq_ctrl==2 | rx_eq_ctrl==5 | rx_eq_ctrl==8 | rx_eq_ctrl==13)? 1 :
+ ((rx_eq_ctrl==3 | rx_eq_ctrl==6 | rx_eq_ctrl==10 | rx_eq_ctrl==15)? 1 :
+ ((rx_eq_ctrl==9 | rx_eq_ctrl==14 )? 1 :
+ (rx_eq_ctrl==12)? 1 : 0)))):
+ (((rx_eq_ctrl==2 | rx_eq_ctrl==5 | rx_eq_ctrl==8 | rx_eq_ctrl==13)? 4 :
+ ((rx_eq_ctrl==3 | rx_eq_ctrl==6 | rx_eq_ctrl==10 | rx_eq_ctrl==15)? 7 :
+ ((rx_eq_ctrl==9 | rx_eq_ctrl==14 )? 5 :
+ (rx_eq_ctrl==12)? 3 : 0))));
+
+//Deepak:Cyclone IV GX reconfig_fromgxb_width = 4. But we keep it as 16 for backward compatibility with Stratix IV
+localparam RECONFIG_FROMGXB_WIDTH = 16;
+
+// ports -------------------------------------------------------------------
+
+// xgmii
+input xgmii_tx_clk;
+input refclk;
+input [71:0] xgmii_tx_dc;
+output xgmii_rx_clk;
+output [71:0] xgmii_rx_dc;
+
+// xaui
+input [3:0] xaui_rx_serial;
+output [3:0] xaui_tx_serial;
+
+// clock_reset
+input rx_analogreset;
+input [3:0] rx_digitalreset; //SPR 346070
+input [3:0] tx_digitalreset; //SPR 346070
+
+// ctrl_stat: control and status
+output rx_channelaligned;
+input [3:0] rx_invpolarity;
+input [3:0] rx_set_locktodata; // should be [3:0]
+input [3:0] rx_set_locktoref; // should be [3:0]
+input [3:0] rx_seriallpbken; // should be [3:0]
+input [3:0] tx_invpolarity;
+output [3:0] rx_is_lockedtodata; // should be [3:0]
+output [3:0] rx_phase_comp_fifo_error;
+output [3:0] rx_is_lockedtoref; // should be [3:0]
+output [3:0] rx_rlv;
+output [3:0] rx_rmfifoempty;
+output [3:0] rx_rmfifofull;
+output [3:0] tx_phase_comp_fifo_error;
+output [7:0] rx_disperr;
+output [7:0] rx_errdetect;
+output [7:0] rx_patterndetect;
+output [7:0] rx_rmfifodatadeleted;
+output [7:0] rx_rmfifodatainserted;
+output [7:0] rx_runningdisp;
+output [7:0] rx_syncstatus;
+output [3:0] rx_recovered_clk;
+
+// reconfig
+input [3:0] reconfig_togxb;
+output [RECONFIG_FROMGXB_WIDTH:0] reconfig_fromgxb;
+input reconfig_clk;
+
+// pma control
+input cal_blk_clk;
+input gxb_powerdown;
+input cal_blk_powerdown;
+input pll_powerdown;
+output pll_locked;
+
+input r_gxb_powerdown;
+input r_cal_blk_powerdown;
+input r_pll_powerdown;
+input [3:0] r_rx_set_locktodata; // should be [3:0]
+input [3:0] r_rx_set_locktoref; // should be [3:0]
+input [3:0] r_rx_seriallpbken; // should be [3:0]
+input [3:0] r_rx_analogreset; // should be width 1
+input r_rx_digitalreset;
+input r_tx_digitalreset;
+input [3:0] r_rx_invpolarity;
+input [3:0] r_tx_invpolarity;
+
+
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+
+// ports -------------------------------------------------------------------
+
+wire xgmii_tx_clk;
+wire [71:0] xgmii_tx_dc;
+wire xgmii_rx_clk;
+wire [71:0] xgmii_rx_dc;
+wire [3:0] xaui_rx_serial;
+wire [3:0] xaui_tx_serial;
+wire [3:0] rx_cruclk;
+wire rx_analogreset;
+wire [3:0] rx_digitalreset; //SPR 346070
+wire [3:0] tx_digitalreset; //SPR 346070
+wire rx_channelaligned;
+wire [3:0] rx_invpolarity;
+wire [3:0] rx_set_locktodata;
+wire [3:0] rx_set_locktoref;
+wire [3:0] rx_seriallpbken;
+wire [3:0] tx_invpolarity;
+wire [3:0] rx_is_lockedtodata;
+wire [3:0] rx_phase_comp_fifo_error;
+wire [3:0] rx_is_lockedtoref;
+wire [3:0] rx_rlv;
+wire [3:0] rx_rmfifoempty;
+wire [3:0] rx_rmfifofull;
+wire [3:0] tx_phase_comp_fifo_error;
+wire [7:0] rx_disperr;
+wire [7:0] rx_errdetect;
+wire [7:0] rx_patterndetect;
+wire [7:0] rx_rmfifodatadeleted;
+wire [7:0] rx_rmfifodatainserted;
+wire [7:0] rx_runningdisp;
+wire [7:0] rx_syncstatus;
+wire [3:0] reconfig_togxb;
+wire [RECONFIG_FROMGXB_WIDTH:0] reconfig_fromgxb;
+wire reconfig_clk;
+wire cal_blk_clk;
+wire cal_blk_powerdown;
+wire gxb_powerdown;
+wire pll_powerdown;
+wire pll_locked;
+
+
+// locals ------------------------------------------------------------------
+wire [7:0] xgmii_tx_c;
+wire [63:0] xgmii_tx_d;
+wire [7:0] xgmii_rx_c;
+wire [63:0] xgmii_rx_d;
+
+// local version
+wire l_cal_blk_powerdown;
+wire l_gxb_powerdown;
+wire l_rx_analogreset;
+wire l_rx_digitalreset;
+wire l_tx_digitalreset;
+wire l_pll_powerdown;
+wire [3:0] l_rx_invpolarity;
+wire [3:0] l_rx_set_locktodata;
+wire [3:0] l_rx_set_locktoref;
+wire [3:0] l_rx_seriallpbken;
+wire [3:0] l_tx_invpolarity;
+
+// register file version
+wire r_gxb_powerdown;
+wire r_cal_blk_powerdown;
+wire [3:0] r_rx_analogreset;
+wire r_rx_digitalreset;
+wire r_tx_digitalreset;
+wire r_pll_powerdown;
+wire [3:0] r_rx_invpolarity;
+wire [3:0] r_rx_set_locktodata;
+wire [3:0] r_rx_set_locktoref;
+wire [3:0] r_rx_seriallpbken;
+wire [3:0] r_tx_invpolarity;
+
+
+// hard xaui signals -------------------------------------------------------
+wire coreclkout;
+wire pll_inclk;
+wire [7:0] tx_ctrlenable;
+wire [63:0] tx_datain;
+wire [7:0] rx_ctrldetect;
+wire [63:0] rx_dataout;
+wire [3:0] rx_datain;
+wire [3:0] tx_dataout;
+wire [3:0] tx_coreclk;
+
+// body --------------------------------------------------------------------
+
+// Convert to/from Avalon Streaming Interface single bus to data + control
+genvar g;
+generate
+ for (g = 0; g < 8; g = g + 1) begin : st_to_dc_b
+ assign xgmii_tx_d [g*8 +: 8] = xgmii_tx_dc[g*9 +: 8];
+ assign xgmii_tx_c [g] = xgmii_tx_dc[g*9 + 8];
+ assign xgmii_rx_dc[g*9 +: 8] = xgmii_rx_d [g*8 +: 8];
+ assign xgmii_rx_dc[g*9 + 8] = xgmii_rx_c [g];
+ end
+endgenerate
+
+// Default values in case ports are not and without control/status registers
+generate
+ if (use_control_and_status_ports == "true" & external_pma_ctrl_reconf == "false" ) begin: use_cs_ports_true
+ assign l_cal_blk_powerdown = cal_blk_powerdown | r_cal_blk_powerdown;
+ assign l_gxb_powerdown = gxb_powerdown | r_gxb_powerdown;
+ assign l_pll_powerdown = pll_powerdown | r_pll_powerdown;
+ assign l_rx_analogreset = rx_analogreset | r_rx_analogreset[0];
+ assign l_rx_digitalreset = |rx_digitalreset | r_rx_digitalreset; //SPR 346070
+ assign l_rx_invpolarity = rx_invpolarity | r_rx_invpolarity;
+ assign l_rx_set_locktodata = rx_set_locktodata[3:0] |
+ r_rx_set_locktodata[3:0];
+ assign l_rx_set_locktoref = rx_set_locktoref[3:0] |
+ r_rx_set_locktoref[3:0];
+ assign l_rx_seriallpbken = rx_seriallpbken[3:0] |
+ r_rx_seriallpbken[3:0];
+ assign l_tx_digitalreset = |tx_digitalreset | r_tx_digitalreset; //SPR 346070
+ assign l_tx_invpolarity = tx_invpolarity | r_tx_invpolarity;
+ end
+ else if (external_pma_ctrl_reconf == "true" ) begin: use_extern_ctrl_true
+ assign l_cal_blk_powerdown = cal_blk_powerdown ;
+ assign l_gxb_powerdown = gxb_powerdown ;
+ assign l_pll_powerdown = pll_powerdown ;
+ assign l_rx_analogreset = rx_analogreset | r_rx_analogreset[0];
+ assign l_rx_digitalreset = |rx_digitalreset | r_rx_digitalreset; //SPR 346070
+ assign l_rx_invpolarity = rx_invpolarity | r_rx_invpolarity;
+ assign l_rx_set_locktodata = rx_set_locktodata[3:0] |
+ r_rx_set_locktodata[3:0];
+ assign l_rx_set_locktoref = rx_set_locktoref[3:0] |
+ r_rx_set_locktoref[3:0];
+ assign l_rx_seriallpbken = rx_seriallpbken[3:0] |
+ r_rx_seriallpbken[3:0];
+ assign l_tx_digitalreset = |tx_digitalreset | r_tx_digitalreset; //SPR 346070
+ assign l_tx_invpolarity = tx_invpolarity | r_tx_invpolarity;
+ end
+ else begin: use_cs_ports_false
+ assign l_cal_blk_powerdown = r_cal_blk_powerdown;
+ assign l_gxb_powerdown = r_gxb_powerdown;
+ assign l_pll_powerdown = r_pll_powerdown;
+ assign l_rx_analogreset = r_rx_analogreset[0];
+ assign l_rx_digitalreset = r_rx_digitalreset | |rx_digitalreset;
+ assign l_rx_invpolarity = r_rx_invpolarity;
+ assign l_rx_set_locktodata = r_rx_set_locktodata[3:0];
+ assign l_rx_set_locktoref = r_rx_set_locktoref[3:0];
+ assign l_rx_seriallpbken = r_rx_seriallpbken[3:0];
+ assign l_tx_digitalreset = r_tx_digitalreset | |tx_digitalreset;
+ assign l_tx_invpolarity = r_tx_invpolarity;
+ end
+endgenerate
+
+// hard xaui --------------------------------------------------------------
+
+// interleave shim
+assign tx_datain[ 0 +: 8] = xgmii_tx_d[ 0 +: 8];
+assign tx_datain[ 8 +: 8] = xgmii_tx_d[32 +: 8];
+assign tx_datain[16 +: 8] = xgmii_tx_d[ 8 +: 8];
+assign tx_datain[24 +: 8] = xgmii_tx_d[40 +: 8];
+assign tx_datain[32 +: 8] = xgmii_tx_d[16 +: 8];
+assign tx_datain[40 +: 8] = xgmii_tx_d[48 +: 8];
+assign tx_datain[48 +: 8] = xgmii_tx_d[24 +: 8];
+assign tx_datain[56 +: 8] = xgmii_tx_d[56 +: 8];
+
+assign tx_ctrlenable[0] = xgmii_tx_c[0];
+assign tx_ctrlenable[1] = xgmii_tx_c[4];
+assign tx_ctrlenable[2] = xgmii_tx_c[1];
+assign tx_ctrlenable[3] = xgmii_tx_c[5];
+assign tx_ctrlenable[4] = xgmii_tx_c[2];
+assign tx_ctrlenable[5] = xgmii_tx_c[6];
+assign tx_ctrlenable[6] = xgmii_tx_c[3];
+assign tx_ctrlenable[7] = xgmii_tx_c[7];
+
+assign xgmii_rx_d[ 0 +: 8] = rx_dataout[ 0 +: 8];
+assign xgmii_rx_d[ 8 +: 8] = rx_dataout[16 +: 8];
+assign xgmii_rx_d[16 +: 8] = rx_dataout[32 +: 8];
+assign xgmii_rx_d[24 +: 8] = rx_dataout[48 +: 8];
+assign xgmii_rx_d[32 +: 8] = rx_dataout[ 8 +: 8];
+assign xgmii_rx_d[40 +: 8] = rx_dataout[24 +: 8];
+assign xgmii_rx_d[48 +: 8] = rx_dataout[40 +: 8];
+assign xgmii_rx_d[56 +: 8] = rx_dataout[56 +: 8];
+
+assign xgmii_rx_c[0] = rx_ctrldetect[0];
+assign xgmii_rx_c[1] = rx_ctrldetect[2];
+assign xgmii_rx_c[2] = rx_ctrldetect[4];
+assign xgmii_rx_c[3] = rx_ctrldetect[6];
+assign xgmii_rx_c[4] = rx_ctrldetect[1];
+assign xgmii_rx_c[5] = rx_ctrldetect[3];
+assign xgmii_rx_c[6] = rx_ctrldetect[5];
+assign xgmii_rx_c[7] = rx_ctrldetect[7];
+
+// translate signal names
+assign pll_inclk = refclk;
+assign xgmii_rx_clk = coreclkout;
+assign rx_datain = xaui_rx_serial;
+assign xaui_tx_serial = tx_dataout;
+assign rx_cruclk = {4{refclk}};
+assign tx_coreclk = {4{xgmii_tx_clk}};
+
+// hard pcs instantiation
+generate
+if((device_family=="Stratix IV") || (device_family=="HardCopy IV") || (device_family=="Arria II GX") || (device_family=="Arria II GZ")) begin: use_device_family_siv_sv
+hxaui_alt4gxb #(
+ .starting_channel_number(starting_channel_number),
+ .receiver_termination(rx_term),
+ .transmitter_termination(tx_term),
+ .preemphasis_ctrl_pretap_setting(tx_preemp_pretap),
+ .preemphasis_ctrl_pretap_inv_setting(tx_preemp_ptinv),
+ .preemphasis_ctrl_1stposttap_setting(tx_preemp_tap_1),
+ .preemphasis_ctrl_2ndposttap_setting(tx_preemp_tap_2),
+ .preemphasis_ctrl_2ndposttap_inv_setting(tx_preemp_t2inv),
+ .vod_ctrl_setting(tx_vod_selection),
+ .rx_common_mode(rx_common_mode),
+ .equalizer_ctrl_a_setting(rx_eqa_ctrl),
+ .equalizer_ctrl_b_setting(rx_eqb_ctrl),
+ .equalizer_ctrl_c_setting(rx_eqc_ctrl),
+ .equalizer_ctrl_d_setting(rx_eqd_ctrl),
+ .equalizer_ctrl_v_setting(rx_eqv_ctrl),
+ .equalizer_dcgain_setting(rx_eq_dc_gain)
+)hxaui_alt4gxb(
+ .cal_blk_clk (cal_blk_clk), // i
+ .cal_blk_powerdown (l_cal_blk_powerdown), // i
+ .gxb_powerdown (l_gxb_powerdown), // i
+ .pll_inclk (pll_inclk), // i
+ .pll_powerdown (l_pll_powerdown), // i
+ .reconfig_clk (reconfig_clk), // i
+ .reconfig_togxb (reconfig_togxb), // i
+ .rx_analogreset (l_rx_analogreset), // i
+ .rx_cruclk (rx_cruclk),
+ .rx_datain (rx_datain), // i
+ .rx_digitalreset (l_rx_digitalreset), // i
+ .rx_invpolarity (l_rx_invpolarity), // i
+ .rx_locktodata (l_rx_set_locktodata), // i
+ .rx_locktorefclk (l_rx_set_locktoref), // i
+ .rx_seriallpbken (l_rx_seriallpbken), // i
+ .tx_coreclk (tx_coreclk), // i - user should tie this to xgmii_rx_clk at top level, if not used
+ .tx_ctrlenable (tx_ctrlenable),
+ .tx_datain (tx_datain), // i
+ .tx_digitalreset (l_tx_digitalreset), // i
+ .tx_invpolarity (l_tx_invpolarity), // i
+ .coreclkout (coreclkout), // o
+ .pll_locked (pll_locked), // o
+ .reconfig_fromgxb (reconfig_fromgxb), // o
+ .rx_channelaligned (rx_channelaligned), // o
+ .rx_ctrldetect (rx_ctrldetect), // o
+ .rx_dataout (rx_dataout), // o
+ .rx_disperr (rx_disperr), // o
+ .rx_errdetect (rx_errdetect), // o
+ .rx_freqlocked (rx_is_lockedtodata[3:0]), // o
+ .rx_patterndetect (rx_patterndetect), // o
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error), // o
+ .rx_pll_locked (rx_is_lockedtoref[3:0]), // o
+ .rx_rlv (rx_rlv), // o
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted), // o
+ .rx_rmfifodatainserted (rx_rmfifodatainserted), // o
+ .rx_rmfifoempty (rx_rmfifoempty), // o
+ .rx_rmfifofull (rx_rmfifofull), // o
+ .rx_runningdisp (rx_runningdisp), // o
+ .rx_recovered_clk (rx_recovered_clk), // o
+ .rx_syncstatus (rx_syncstatus), // o
+ .tx_dataout (tx_dataout), // o
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error) // o
+);
+defparam
+ hxaui_alt4gxb.starting_channel_number = starting_channel_number;
+end
+
+if((device_family=="Cyclone IV GX")) begin: use_device_family_civ
+
+//Deepak : from Mei Yin Tan, PN
+//Cyclone IV GX:
+//if you are using duplex design, both the tx and rx is sharing the same ALTPLL, so the pll_locked will determine whether the pll is locked.
+//assign rx_is_lockedtoref[3:0] = {4{pll_locked}};
+assign rx_is_lockedtoref[3:0] = rx_is_lockedtodata[3:0];
+
+
+hxaui_alt_c3gxb #(
+ .starting_channel_number(starting_channel_number),
+ .receiver_termination(rx_term),
+ .transmitter_termination(tx_term),
+ .preemphasis_ctrl_1stposttap_setting(tx_preemp_tap_1),
+ .vod_ctrl_setting(tx_vod_selection),
+ .rx_common_mode(rx_common_mode),
+ .equalizer_dcgain_setting(rx_eq_dc_gain)
+)hxaui_alt_c3gxb (
+
+ .cal_blk_clk (cal_blk_clk), // i
+ .cal_blk_powerdown (l_cal_blk_powerdown), // i
+ .gxb_powerdown (l_gxb_powerdown), // i
+ .pll_inclk (pll_inclk), // i
+ .pll_powerdown (l_pll_powerdown), // i
+ .reconfig_clk (reconfig_clk), // i
+ .reconfig_togxb (reconfig_togxb), // i
+ .rx_analogreset (l_rx_analogreset), // i
+ .rx_datain (rx_datain), // i
+ .rx_digitalreset (l_rx_digitalreset), // i
+ .rx_invpolarity (l_rx_invpolarity), // i
+ .rx_locktodata (l_rx_set_locktodata), // i
+ .rx_locktorefclk (l_rx_set_locktoref), // i
+
+ .tx_coreclk (tx_coreclk), // i - user should tie this to xgmii_rx_clk at top level, if not used
+ .tx_ctrlenable (tx_ctrlenable),
+ .tx_datain (tx_datain), // i
+ .tx_digitalreset (l_tx_digitalreset), // i
+ .tx_invpolarity (l_tx_invpolarity), // i
+ .coreclkout (coreclkout), // o
+ .pll_locked (pll_locked), // o
+ .reconfig_fromgxb (reconfig_fromgxb[4:0]), // o - alt3gxb uses only lower 5 bits of 17 bits from Stratix IV
+ .rx_channelaligned (rx_channelaligned), // o
+ .rx_ctrldetect (rx_ctrldetect), // o
+ .rx_dataout (rx_dataout), // o
+ .rx_disperr (rx_disperr), // o
+ .rx_errdetect (rx_errdetect), // o
+ .rx_freqlocked (rx_is_lockedtodata[3:0]), // o
+ .rx_patterndetect (rx_patterndetect), // o
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error), // o
+ .rx_rlv (rx_rlv), // o
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted), // o
+ .rx_rmfifodatainserted (rx_rmfifodatainserted), // o
+ .rx_rmfifoempty (rx_rmfifoempty), // o
+ .rx_rmfifofull (rx_rmfifofull), // o
+ .rx_recovered_clk (rx_recovered_clk), // o
+ .rx_runningdisp (rx_runningdisp), // o
+ .rx_syncstatus (rx_syncstatus), // o
+ .tx_dataout (tx_dataout), // o
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error) // o
+);
+defparam
+ hxaui_alt_c3gxb.starting_channel_number = starting_channel_number;
+
+assign reconfig_fromgxb[16:5] = 12'b0;
+end
+endgenerate
+
+endmodule // alt_xaui
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/hxaui_alt4gxb.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/hxaui_alt4gxb.v
new file mode 100644
index 0000000000000000000000000000000000000000..3c73ae92cf771e2eb4711d03be66a8166501ab4d
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/hxaui_alt4gxb.v
@@ -0,0 +1,4048 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// megafunction wizard: %ALTGX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: alt4gxb
+
+// ============================================================
+// File Name: hxaui_alt4gxb.v
+// Megafunction Name(s):
+// alt4gxb
+//
+// Simulation Library Files(s):
+// stratixiv_hssi
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 9.1 Build 301 01/06/2010 SP 1 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//alt4gxb CBX_AUTO_BLACKBOX="ALL" coreclkout_control_width=1 device_family="Stratix IV" effective_data_rate="3125 Mbps" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=0 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="AUTO" gxb_powerdown_width=1 input_clock_frequency="156.25 MHz" intended_device_speed_grade="2" intended_device_variant="GX" loopback_mode="slb" number_of_channels=4 number_of_quads=1 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="xaui" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_fromgxb_port_width=17 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="true" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_bonding="x4" rx_channel_width=16 rx_common_mode="0.82v" rx_cru_bandwidth_type="auto" rx_cru_inclock0_period=6400 rx_cru_m_divider=10 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=2 rx_data_rate=3125 rx_data_rate_remainder=0 rx_datapath_protocol="xaui" rx_digitalreset_port_width=1 rx_dwidth_factor=2 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="true" rx_enable_lock_to_refclk_sig="true" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="1101000011" rx_rate_match_pattern2="0010111100" rx_rate_match_pattern_size=10 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=2 rx_signal_detect_valid_threshold=1 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="true" rx_use_double_data_mode="true" rx_use_external_termination="false" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="true" tx_analog_power="AUTO" tx_channel_bonding="x4" tx_channel_width=16 tx_clkout_width=4 tx_common_mode="0.65v" tx_data_rate=3125 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=2 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="auto" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=6400 tx_pll_m_divider=10 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=2 tx_slew_rate="low" tx_transmit_protocol="xaui" tx_use_coreclk="true" tx_use_double_data_mode="true" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk cal_blk_powerdown coreclkout gxb_powerdown pll_inclk pll_locked pll_powerdown reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_channelaligned rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_freqlocked rx_invpolarity rx_locktodata rx_locktorefclk rx_patterndetect rx_phase_comp_fifo_error rx_pll_locked rx_rlv rx_rmfifodatadeleted rx_rmfifodatainserted rx_rmfifoempty rx_rmfifofull rx_runningdisp rx_seriallpbken rx_syncstatus tx_coreclk tx_ctrlenable tx_datain tx_dataout tx_digitalreset tx_invpolarity tx_phase_comp_fifo_error
+//VERSION_BEGIN 9.1SP1 cbx_alt4gxb 2010:01:06:21:12:59:SJ cbx_mgl 2010:01:06:21:19:19:SJ cbx_tgx 2010:01:06:21:12:59:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = reg 6 stratixiv_hssi_calibration_block 1 stratixiv_hssi_clock_divider 1 stratixiv_hssi_cmu 1 stratixiv_hssi_pll 5 stratixiv_hssi_rx_pcs 4 stratixiv_hssi_rx_pma 4 stratixiv_hssi_tx_pcs 4 stratixiv_hssi_tx_pma 4
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module hxaui_alt4gxb_alt4gxb_dksa
+ (
+ cal_blk_clk,
+ cal_blk_powerdown,
+ coreclkout,
+ gxb_powerdown,
+ pll_inclk,
+ pll_locked,
+ pll_powerdown,
+ reconfig_clk,
+ reconfig_fromgxb,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_channelaligned,
+ rx_coreclk,
+ rx_cruclk,
+ rx_ctrldetect,
+ rx_datain,
+ rx_dataout,
+ rx_digitalreset,
+ rx_disperr,
+ rx_errdetect,
+ rx_freqlocked,
+ rx_invpolarity,
+ rx_locktodata,
+ rx_locktorefclk,
+ rx_patterndetect,
+ rx_phase_comp_fifo_error,
+ rx_pll_locked,
+ rx_rlv,
+ rx_rmfifodatadeleted,
+ rx_rmfifodatainserted,
+ rx_rmfifoempty,
+ rx_rmfifofull,
+ rx_runningdisp,
+ rx_seriallpbken,
+ rx_syncstatus,
+ rx_recovered_clk,
+ tx_coreclk,
+ tx_ctrlenable,
+ tx_datain,
+ tx_dataout,
+ tx_digitalreset,
+ tx_invpolarity,
+ tx_phase_comp_fifo_error) ;
+ input cal_blk_clk;
+ input cal_blk_powerdown;
+ output [0:0] coreclkout;
+ input [0:0] gxb_powerdown;
+ input pll_inclk;
+ output [0:0] pll_locked;
+ input [0:0] pll_powerdown;
+ input reconfig_clk;
+ output [16:0] reconfig_fromgxb;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ output [0:0] rx_channelaligned;
+ input [3:0] rx_coreclk;
+ input [3:0] rx_cruclk;
+ output [7:0] rx_ctrldetect;
+ input [3:0] rx_datain;
+ output [63:0] rx_dataout;
+ input [0:0] rx_digitalreset;
+ output [7:0] rx_disperr;
+ output [7:0] rx_errdetect;
+ output [3:0] rx_freqlocked;
+ input [3:0] rx_invpolarity;
+ input [3:0] rx_locktodata;
+ input [3:0] rx_locktorefclk;
+ output [7:0] rx_patterndetect;
+ output [3:0] rx_phase_comp_fifo_error;
+ output [3:0] rx_pll_locked;
+ output [3:0] rx_rlv;
+ output [7:0] rx_rmfifodatadeleted;
+ output [7:0] rx_rmfifodatainserted;
+ output [3:0] rx_rmfifoempty;
+ output [3:0] rx_rmfifofull;
+ output [7:0] rx_runningdisp;
+ input [3:0] rx_seriallpbken;
+ output [7:0] rx_syncstatus;
+ input [3:0] tx_coreclk;
+ input [7:0] tx_ctrlenable;
+ input [63:0] tx_datain;
+ output [3:0] tx_dataout;
+ input [0:0] tx_digitalreset;
+ input [3:0] tx_invpolarity;
+ output [3:0] tx_phase_comp_fifo_error;
+ output [3:0] rx_recovered_clk;
+
+ wire wire_receive_pcs0_clkout;
+ wire wire_receive_pcs1_clkout;
+ wire wire_receive_pcs2_clkout;
+ wire wire_receive_pcs3_clkout;
+ assign rx_recovered_clk = {wire_receive_pcs0_clkout,wire_receive_pcs1_clkout,wire_receive_pcs2_clkout,wire_receive_pcs3_clkout};
+
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 cal_blk_clk;
+ tri0 cal_blk_powerdown;
+ tri0 [0:0] gxb_powerdown;
+ tri0 pll_inclk;
+ tri0 [0:0] pll_powerdown;
+ tri0 reconfig_clk;
+ tri0 [0:0] rx_analogreset;
+ tri0 [3:0] rx_coreclk;
+ tri0 [3:0] rx_cruclk;
+ tri0 [0:0] rx_digitalreset;
+ tri0 [3:0] rx_invpolarity;
+ tri0 [3:0] rx_locktodata;
+ tri0 [3:0] rx_locktorefclk;
+ tri0 [3:0] rx_seriallpbken;
+ tri0 [3:0] tx_coreclk;
+ tri0 [7:0] tx_ctrlenable;
+ tri0 [63:0] tx_datain;
+ tri0 [0:0] tx_digitalreset;
+ tri0 [3:0] tx_invpolarity;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+
+ parameter starting_channel_number = 0;
+ parameter transmitter_termination = "OCT 100 OHMS";//OCT_85_OHMS,OCT_100_OHMS,OCT_120_OHMS,OCT_150_OHMS
+ parameter receiver_termination = "OCT 100 OHMS"; //OCT_85_OHMS,OCT_100_OHMS,OCT_120_OHMS,OCT_150_OHMS
+ parameter rx_common_mode = "0.82v";
+
+ parameter preemphasis_ctrl_pretap_setting = 0;//0-7
+ parameter preemphasis_ctrl_pretap_inv_setting = "FALSE";//TRUE or FALSE.
+ parameter preemphasis_ctrl_1stposttap_setting = 5;//0-15
+ parameter preemphasis_ctrl_2ndposttap_setting = 0;//0-7
+ parameter preemphasis_ctrl_2ndposttap_inv_setting = "FALSE";//TRUE or FALSE.
+ parameter vod_ctrl_setting = 1;//0-7
+
+ parameter equalizer_dcgain_setting = 0; //0-4
+ parameter equalizer_ctrl_a_setting = 0;
+ parameter equalizer_ctrl_b_setting = 0;
+ parameter equalizer_ctrl_c_setting = 0;
+ parameter equalizer_ctrl_d_setting = 0;
+ parameter equalizer_ctrl_v_setting = 0;
+
+
+ wire [2:0] wire_rx_digitalreset_reg0c_d;
+ reg [2:0] rx_digitalreset_reg0c;
+ wire [2:0] wire_rx_digitalreset_reg0c_clk;
+ wire [2:0] wire_tx_digitalreset_reg0c_d;
+ reg [2:0] tx_digitalreset_reg0c;
+ wire [2:0] wire_tx_digitalreset_reg0c_clk;
+ wire wire_cal_blk0_nonusertocmu;
+ wire [1:0] wire_central_clk_div0_analogfastrefclkout;
+ wire [1:0] wire_central_clk_div0_analogrefclkout;
+ wire wire_central_clk_div0_analogrefclkpulse;
+ wire wire_central_clk_div0_coreclkout;
+ wire [99:0] wire_central_clk_div0_dprioout;
+ wire wire_central_clk_div0_rateswitchdone;
+ wire wire_central_clk_div0_refclkout;
+ wire wire_cent_unit0_alignstatus;
+ wire [1:0] wire_cent_unit0_clkdivpowerdn;
+ wire [599:0] wire_cent_unit0_cmudividerdprioout;
+ wire [1799:0] wire_cent_unit0_cmuplldprioout;
+ wire wire_cent_unit0_dpriodisableout;
+ wire wire_cent_unit0_dprioout;
+ wire wire_cent_unit0_enabledeskew;
+ wire wire_cent_unit0_fiforesetrd;
+ wire [1:0] wire_cent_unit0_pllpowerdn;
+ wire [1:0] wire_cent_unit0_pllresetout;
+ wire wire_cent_unit0_quadresetout;
+ wire [5:0] wire_cent_unit0_rxanalogresetout;
+ wire [5:0] wire_cent_unit0_rxcrupowerdown;
+ wire [5:0] wire_cent_unit0_rxcruresetout;
+ wire [3:0] wire_cent_unit0_rxctrlout;
+ wire [31:0] wire_cent_unit0_rxdataout;
+ wire [3:0] wire_cent_unit0_rxdigitalresetout;
+ wire [5:0] wire_cent_unit0_rxibpowerdown;
+ wire [1599:0] wire_cent_unit0_rxpcsdprioout;
+ wire wire_cent_unit0_rxphfifox4byteselout;
+ wire wire_cent_unit0_rxphfifox4rdenableout;
+ wire wire_cent_unit0_rxphfifox4wrclkout;
+ wire wire_cent_unit0_rxphfifox4wrenableout;
+ wire [1799:0] wire_cent_unit0_rxpmadprioout;
+ wire [5:0] wire_cent_unit0_txanalogresetout;
+ wire [3:0] wire_cent_unit0_txctrlout;
+ wire [31:0] wire_cent_unit0_txdataout;
+ wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
+ wire [3:0] wire_cent_unit0_txdigitalresetout;
+ wire [5:0] wire_cent_unit0_txobpowerdown;
+ wire [599:0] wire_cent_unit0_txpcsdprioout;
+ wire wire_cent_unit0_txphfifox4byteselout;
+ wire wire_cent_unit0_txphfifox4rdclkout;
+ wire wire_cent_unit0_txphfifox4rdenableout;
+ wire wire_cent_unit0_txphfifox4wrenableout;
+ wire [1799:0] wire_cent_unit0_txpmadprioout;
+ wire [3:0] wire_rx_cdr_pll0_clk;
+ wire [1:0] wire_rx_cdr_pll0_dataout;
+ wire [299:0] wire_rx_cdr_pll0_dprioout;
+ wire wire_rx_cdr_pll0_freqlocked;
+ wire wire_rx_cdr_pll0_locked;
+ wire wire_rx_cdr_pll0_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll1_clk;
+ wire [1:0] wire_rx_cdr_pll1_dataout;
+ wire [299:0] wire_rx_cdr_pll1_dprioout;
+ wire wire_rx_cdr_pll1_freqlocked;
+ wire wire_rx_cdr_pll1_locked;
+ wire wire_rx_cdr_pll1_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll2_clk;
+ wire [1:0] wire_rx_cdr_pll2_dataout;
+ wire [299:0] wire_rx_cdr_pll2_dprioout;
+ wire wire_rx_cdr_pll2_freqlocked;
+ wire wire_rx_cdr_pll2_locked;
+ wire wire_rx_cdr_pll2_pfdrefclkout;
+ wire [3:0] wire_rx_cdr_pll3_clk;
+ wire [1:0] wire_rx_cdr_pll3_dataout;
+ wire [299:0] wire_rx_cdr_pll3_dprioout;
+ wire wire_rx_cdr_pll3_freqlocked;
+ wire wire_rx_cdr_pll3_locked;
+ wire wire_rx_cdr_pll3_pfdrefclkout;
+ wire [3:0] wire_tx_pll0_clk;
+ wire [299:0] wire_tx_pll0_dprioout;
+ wire wire_tx_pll0_locked;
+ wire wire_receive_pcs0_adetectdeskew;
+ wire wire_receive_pcs0_alignstatussyncout;
+ wire wire_receive_pcs0_cdrctrllocktorefclkout;
+ wire wire_receive_pcs0_coreclkout;
+ wire [3:0] wire_receive_pcs0_ctrldetect;
+ wire [39:0] wire_receive_pcs0_dataout;
+ wire wire_receive_pcs0_disablefifordout;
+ wire wire_receive_pcs0_disablefifowrout;
+ wire [3:0] wire_receive_pcs0_disperr;
+ wire [399:0] wire_receive_pcs0_dprioout;
+ wire [3:0] wire_receive_pcs0_errdetect;
+ wire wire_receive_pcs0_fifordout;
+ wire [3:0] wire_receive_pcs0_patterndetect;
+ wire wire_receive_pcs0_phfifobyteserdisableout;
+ wire wire_receive_pcs0_phfifooverflow;
+ wire wire_receive_pcs0_phfifoptrsresetout;
+ wire wire_receive_pcs0_phfifordenableout;
+ wire wire_receive_pcs0_phfiforesetout;
+ wire wire_receive_pcs0_phfifounderflow;
+ wire wire_receive_pcs0_phfifowrdisableout;
+ wire wire_receive_pcs0_rateswitchout;
+ wire wire_receive_pcs0_rdalign;
+ wire wire_receive_pcs0_rlv;
+ wire [3:0] wire_receive_pcs0_rmfifodatadeleted;
+ wire [3:0] wire_receive_pcs0_rmfifodatainserted;
+ wire wire_receive_pcs0_rmfifoempty;
+ wire wire_receive_pcs0_rmfifofull;
+ wire [3:0] wire_receive_pcs0_runningdisp;
+ wire [3:0] wire_receive_pcs0_syncstatus;
+ wire wire_receive_pcs0_syncstatusdeskew;
+ wire wire_receive_pcs0_xgmctrldet;
+ wire [7:0] wire_receive_pcs0_xgmdataout;
+ wire wire_receive_pcs0_xgmdatavalid;
+ wire wire_receive_pcs0_xgmrunningdisp;
+ wire wire_receive_pcs1_adetectdeskew;
+ wire wire_receive_pcs1_alignstatussyncout;
+ wire wire_receive_pcs1_cdrctrllocktorefclkout;
+ wire wire_receive_pcs1_coreclkout;
+ wire [3:0] wire_receive_pcs1_ctrldetect;
+ wire [39:0] wire_receive_pcs1_dataout;
+ wire wire_receive_pcs1_disablefifordout;
+ wire wire_receive_pcs1_disablefifowrout;
+ wire [3:0] wire_receive_pcs1_disperr;
+ wire [399:0] wire_receive_pcs1_dprioout;
+ wire [3:0] wire_receive_pcs1_errdetect;
+ wire wire_receive_pcs1_fifordout;
+ wire [3:0] wire_receive_pcs1_patterndetect;
+ wire wire_receive_pcs1_phfifobyteserdisableout;
+ wire wire_receive_pcs1_phfifooverflow;
+ wire wire_receive_pcs1_phfifoptrsresetout;
+ wire wire_receive_pcs1_phfifordenableout;
+ wire wire_receive_pcs1_phfiforesetout;
+ wire wire_receive_pcs1_phfifounderflow;
+ wire wire_receive_pcs1_phfifowrdisableout;
+ wire wire_receive_pcs1_rateswitchout;
+ wire wire_receive_pcs1_rdalign;
+ wire wire_receive_pcs1_rlv;
+ wire [3:0] wire_receive_pcs1_rmfifodatadeleted;
+ wire [3:0] wire_receive_pcs1_rmfifodatainserted;
+ wire wire_receive_pcs1_rmfifoempty;
+ wire wire_receive_pcs1_rmfifofull;
+ wire [3:0] wire_receive_pcs1_runningdisp;
+ wire [3:0] wire_receive_pcs1_syncstatus;
+ wire wire_receive_pcs1_syncstatusdeskew;
+ wire wire_receive_pcs1_xgmctrldet;
+ wire [7:0] wire_receive_pcs1_xgmdataout;
+ wire wire_receive_pcs1_xgmdatavalid;
+ wire wire_receive_pcs1_xgmrunningdisp;
+ wire wire_receive_pcs2_adetectdeskew;
+ wire wire_receive_pcs2_alignstatussyncout;
+ wire wire_receive_pcs2_cdrctrllocktorefclkout;
+ wire wire_receive_pcs2_coreclkout;
+ wire [3:0] wire_receive_pcs2_ctrldetect;
+ wire [39:0] wire_receive_pcs2_dataout;
+ wire wire_receive_pcs2_disablefifordout;
+ wire wire_receive_pcs2_disablefifowrout;
+ wire [3:0] wire_receive_pcs2_disperr;
+ wire [399:0] wire_receive_pcs2_dprioout;
+ wire [3:0] wire_receive_pcs2_errdetect;
+ wire wire_receive_pcs2_fifordout;
+ wire [3:0] wire_receive_pcs2_patterndetect;
+ wire wire_receive_pcs2_phfifobyteserdisableout;
+ wire wire_receive_pcs2_phfifooverflow;
+ wire wire_receive_pcs2_phfifoptrsresetout;
+ wire wire_receive_pcs2_phfifordenableout;
+ wire wire_receive_pcs2_phfiforesetout;
+ wire wire_receive_pcs2_phfifounderflow;
+ wire wire_receive_pcs2_phfifowrdisableout;
+ wire wire_receive_pcs2_rateswitchout;
+ wire wire_receive_pcs2_rdalign;
+ wire wire_receive_pcs2_rlv;
+ wire [3:0] wire_receive_pcs2_rmfifodatadeleted;
+ wire [3:0] wire_receive_pcs2_rmfifodatainserted;
+ wire wire_receive_pcs2_rmfifoempty;
+ wire wire_receive_pcs2_rmfifofull;
+ wire [3:0] wire_receive_pcs2_runningdisp;
+ wire [3:0] wire_receive_pcs2_syncstatus;
+ wire wire_receive_pcs2_syncstatusdeskew;
+ wire wire_receive_pcs2_xgmctrldet;
+ wire [7:0] wire_receive_pcs2_xgmdataout;
+ wire wire_receive_pcs2_xgmdatavalid;
+ wire wire_receive_pcs2_xgmrunningdisp;
+ wire wire_receive_pcs3_adetectdeskew;
+ wire wire_receive_pcs3_alignstatussyncout;
+ wire wire_receive_pcs3_cdrctrllocktorefclkout;
+ wire wire_receive_pcs3_coreclkout;
+ wire [3:0] wire_receive_pcs3_ctrldetect;
+ wire [39:0] wire_receive_pcs3_dataout;
+ wire wire_receive_pcs3_disablefifordout;
+ wire wire_receive_pcs3_disablefifowrout;
+ wire [3:0] wire_receive_pcs3_disperr;
+ wire [399:0] wire_receive_pcs3_dprioout;
+ wire [3:0] wire_receive_pcs3_errdetect;
+ wire wire_receive_pcs3_fifordout;
+ wire [3:0] wire_receive_pcs3_patterndetect;
+ wire wire_receive_pcs3_phfifobyteserdisableout;
+ wire wire_receive_pcs3_phfifooverflow;
+ wire wire_receive_pcs3_phfifoptrsresetout;
+ wire wire_receive_pcs3_phfifordenableout;
+ wire wire_receive_pcs3_phfiforesetout;
+ wire wire_receive_pcs3_phfifounderflow;
+ wire wire_receive_pcs3_phfifowrdisableout;
+ wire wire_receive_pcs3_rateswitchout;
+ wire wire_receive_pcs3_rdalign;
+ wire wire_receive_pcs3_rlv;
+ wire [3:0] wire_receive_pcs3_rmfifodatadeleted;
+ wire [3:0] wire_receive_pcs3_rmfifodatainserted;
+ wire wire_receive_pcs3_rmfifoempty;
+ wire wire_receive_pcs3_rmfifofull;
+ wire [3:0] wire_receive_pcs3_runningdisp;
+ wire [3:0] wire_receive_pcs3_syncstatus;
+ wire wire_receive_pcs3_syncstatusdeskew;
+ wire wire_receive_pcs3_xgmctrldet;
+ wire [7:0] wire_receive_pcs3_xgmdataout;
+ wire wire_receive_pcs3_xgmdatavalid;
+ wire wire_receive_pcs3_xgmrunningdisp;
+ wire [7:0] wire_receive_pma0_analogtestbus;
+ wire wire_receive_pma0_clockout;
+ wire wire_receive_pma0_dataout;
+ wire [299:0] wire_receive_pma0_dprioout;
+ wire wire_receive_pma0_locktorefout;
+ wire [63:0] wire_receive_pma0_recoverdataout;
+ wire wire_receive_pma0_signaldetect;
+ wire [7:0] wire_receive_pma1_analogtestbus;
+ wire wire_receive_pma1_clockout;
+ wire wire_receive_pma1_dataout;
+ wire [299:0] wire_receive_pma1_dprioout;
+ wire wire_receive_pma1_locktorefout;
+ wire [63:0] wire_receive_pma1_recoverdataout;
+ wire wire_receive_pma1_signaldetect;
+ wire [7:0] wire_receive_pma2_analogtestbus;
+ wire wire_receive_pma2_clockout;
+ wire wire_receive_pma2_dataout;
+ wire [299:0] wire_receive_pma2_dprioout;
+ wire wire_receive_pma2_locktorefout;
+ wire [63:0] wire_receive_pma2_recoverdataout;
+ wire wire_receive_pma2_signaldetect;
+ wire [7:0] wire_receive_pma3_analogtestbus;
+ wire wire_receive_pma3_clockout;
+ wire wire_receive_pma3_dataout;
+ wire [299:0] wire_receive_pma3_dprioout;
+ wire wire_receive_pma3_locktorefout;
+ wire [63:0] wire_receive_pma3_recoverdataout;
+ wire wire_receive_pma3_signaldetect;
+ wire wire_transmit_pcs0_coreclkout;
+ wire [19:0] wire_transmit_pcs0_dataout;
+ wire [149:0] wire_transmit_pcs0_dprioout;
+ wire wire_transmit_pcs0_forceelecidleout;
+ wire wire_transmit_pcs0_phfifooverflow;
+ wire wire_transmit_pcs0_phfiforddisableout;
+ wire wire_transmit_pcs0_phfiforesetout;
+ wire wire_transmit_pcs0_phfifounderflow;
+ wire wire_transmit_pcs0_phfifowrenableout;
+ wire wire_transmit_pcs0_rdenablesync;
+ wire wire_transmit_pcs0_txdetectrx;
+ wire wire_transmit_pcs0_xgmctrlenable;
+ wire [7:0] wire_transmit_pcs0_xgmdataout;
+ wire wire_transmit_pcs1_coreclkout;
+ wire [19:0] wire_transmit_pcs1_dataout;
+ wire [149:0] wire_transmit_pcs1_dprioout;
+ wire wire_transmit_pcs1_forceelecidleout;
+ wire wire_transmit_pcs1_phfifooverflow;
+ wire wire_transmit_pcs1_phfiforddisableout;
+ wire wire_transmit_pcs1_phfiforesetout;
+ wire wire_transmit_pcs1_phfifounderflow;
+ wire wire_transmit_pcs1_phfifowrenableout;
+ wire wire_transmit_pcs1_rdenablesync;
+ wire wire_transmit_pcs1_txdetectrx;
+ wire wire_transmit_pcs1_xgmctrlenable;
+ wire [7:0] wire_transmit_pcs1_xgmdataout;
+ wire wire_transmit_pcs2_coreclkout;
+ wire [19:0] wire_transmit_pcs2_dataout;
+ wire [149:0] wire_transmit_pcs2_dprioout;
+ wire wire_transmit_pcs2_forceelecidleout;
+ wire wire_transmit_pcs2_phfifooverflow;
+ wire wire_transmit_pcs2_phfiforddisableout;
+ wire wire_transmit_pcs2_phfiforesetout;
+ wire wire_transmit_pcs2_phfifounderflow;
+ wire wire_transmit_pcs2_phfifowrenableout;
+ wire wire_transmit_pcs2_rdenablesync;
+ wire wire_transmit_pcs2_txdetectrx;
+ wire wire_transmit_pcs2_xgmctrlenable;
+ wire [7:0] wire_transmit_pcs2_xgmdataout;
+ wire wire_transmit_pcs3_coreclkout;
+ wire [19:0] wire_transmit_pcs3_dataout;
+ wire [149:0] wire_transmit_pcs3_dprioout;
+ wire wire_transmit_pcs3_forceelecidleout;
+ wire wire_transmit_pcs3_phfifooverflow;
+ wire wire_transmit_pcs3_phfiforddisableout;
+ wire wire_transmit_pcs3_phfiforesetout;
+ wire wire_transmit_pcs3_phfifounderflow;
+ wire wire_transmit_pcs3_phfifowrenableout;
+ wire wire_transmit_pcs3_rdenablesync;
+ wire wire_transmit_pcs3_txdetectrx;
+ wire wire_transmit_pcs3_xgmctrlenable;
+ wire [7:0] wire_transmit_pcs3_xgmdataout;
+ wire wire_transmit_pma0_clockout;
+ wire wire_transmit_pma0_dataout;
+ wire [299:0] wire_transmit_pma0_dprioout;
+ wire wire_transmit_pma0_seriallpbkout;
+ wire wire_transmit_pma1_clockout;
+ wire wire_transmit_pma1_dataout;
+ wire [299:0] wire_transmit_pma1_dprioout;
+ wire wire_transmit_pma1_seriallpbkout;
+ wire wire_transmit_pma2_clockout;
+ wire wire_transmit_pma2_dataout;
+ wire [299:0] wire_transmit_pma2_dprioout;
+ wire wire_transmit_pma2_seriallpbkout;
+ wire wire_transmit_pma3_clockout;
+ wire wire_transmit_pma3_dataout;
+ wire [299:0] wire_transmit_pma3_dprioout;
+ wire wire_transmit_pma3_seriallpbkout;
+ wire [0:0] cent_unit_clkdivpowerdn;
+ wire [599:0] cent_unit_cmudividerdprioout;
+ wire [1799:0] cent_unit_cmuplldprioout;
+ wire [1:0] cent_unit_pllpowerdn;
+ wire [1:0] cent_unit_pllresetout;
+ wire [0:0] cent_unit_quadresetout;
+ wire [0:0] cent_unit_rdenablesync;
+ wire [3:0] cent_unit_rx_ctrl;
+ wire [31:0] cent_unit_rx_xgmdataout;
+ wire [5:0] cent_unit_rxcrupowerdn;
+ wire [5:0] cent_unit_rxibpowerdn;
+ wire [1599:0] cent_unit_rxpcsdprioin;
+ wire [1599:0] cent_unit_rxpcsdprioout;
+ wire [1799:0] cent_unit_rxpmadprioin;
+ wire [1799:0] cent_unit_rxpmadprioout;
+ wire [1199:0] cent_unit_tx_dprioin;
+ wire [31:0] cent_unit_tx_xgmdataout;
+ wire [3:0] cent_unit_txctrlout;
+ wire [5:0] cent_unit_txdetectrxpowerdn;
+ wire [599:0] cent_unit_txdprioout;
+ wire [5:0] cent_unit_txobpowerdn;
+ wire [1799:0] cent_unit_txpmadprioin;
+ wire [1799:0] cent_unit_txpmadprioout;
+ wire [3:0] clk_div_clk0in;
+ wire [599:0] clk_div_cmudividerdprioin;
+ wire [1:0] cmu_analogfastrefclkout;
+ wire [1:0] cmu_analogrefclkout;
+ wire [0:0] cmu_analogrefclkpulse;
+ wire [0:0] coreclkout_wire;
+ wire [0:0] enabledeskew;
+ wire [5:0] fixedclk_to_cmu;
+ wire [0:0] int_hiprateswtichdone;
+ wire [3:0] int_rx_coreclkout;
+ wire [0:0] int_rx_digitalreset_reg;
+ wire [3:0] int_rx_phfifobyteserdisable;
+ wire [3:0] int_rx_phfifoptrsresetout;
+ wire [3:0] int_rx_phfifordenableout;
+ wire [3:0] int_rx_phfiforesetout;
+ wire [3:0] int_rx_phfifowrdisableout;
+ wire [11:0] int_rx_phfifoxnbytesel;
+ wire [11:0] int_rx_phfifoxnrdenable;
+ wire [11:0] int_rx_phfifoxnwrclk;
+ wire [11:0] int_rx_phfifoxnwrenable;
+ wire [0:0] int_rxcoreclk;
+ wire [0:0] int_rxphfifordenable;
+ wire [0:0] int_rxphfiforeset;
+ wire [0:0] int_rxphfifox4byteselout;
+ wire [0:0] int_rxphfifox4rdenableout;
+ wire [0:0] int_rxphfifox4wrclkout;
+ wire [0:0] int_rxphfifox4wrenableout;
+ wire [3:0] int_tx_coreclkout;
+ wire [0:0] int_tx_digitalreset_reg;
+ wire [3:0] int_tx_phfiforddisableout;
+ wire [3:0] int_tx_phfiforesetout;
+ wire [3:0] int_tx_phfifowrenableout;
+ wire [11:0] int_tx_phfifoxnbytesel;
+ wire [11:0] int_tx_phfifoxnrdclk;
+ wire [11:0] int_tx_phfifoxnrdenable;
+ wire [11:0] int_tx_phfifoxnwrenable;
+ wire [0:0] int_txcoreclk;
+ wire [0:0] int_txphfiforddisable;
+ wire [0:0] int_txphfiforeset;
+ wire [0:0] int_txphfifowrenable;
+ wire [0:0] int_txphfifox4byteselout;
+ wire [0:0] int_txphfifox4rdclkout;
+ wire [0:0] int_txphfifox4rdenableout;
+ wire [0:0] int_txphfifox4wrenableout;
+ wire [0:0] nonusertocmu_out;
+ wire [9:0] pll0_clkin;
+ wire [299:0] pll0_dprioin;
+ wire [299:0] pll0_dprioout;
+ wire [3:0] pll0_out;
+ wire [7:0] pll_ch_dataout_wire;
+ wire [1199:0] pll_ch_dprioout;
+ wire [1799:0] pll_cmuplldprioout;
+ wire [0:0] pll_inclk_wire;
+ wire [0:0] pll_locked_out;
+ wire [1:0] pllpowerdn_in;
+ wire [1:0] pllreset_in;
+ wire [0:0] reconfig_togxb_busy;
+ wire [0:0] reconfig_togxb_disable;
+ wire [0:0] reconfig_togxb_in;
+ wire [0:0] reconfig_togxb_load;
+ wire [0:0] refclk_pma;
+ wire [3:0] rx_adetectdeskew;
+ wire [0:0] rx_alignstatussync;
+ wire [3:0] rx_alignstatussyncout;
+ wire [5:0] rx_analogreset_in;
+ wire [5:0] rx_analogreset_out;
+ wire [0:0] rx_channelaligned_in;
+ wire [3:0] rx_coreclk_in;
+ wire [39:0] rx_cruclk_in;
+ wire [15:0] rx_deserclock_in;
+ wire [3:0] rx_digitalreset_in;
+ wire [3:0] rx_digitalreset_out;
+ wire [0:0] rx_disablefifordin_in;
+ wire [3:0] rx_disablefifordout_wire;
+ wire [0:0] rx_disablefifowrin_in;
+ wire [3:0] rx_disablefifowrout_wire;
+ wire [3:0] rx_enapatternalign;
+ wire [0:0] rx_fifordin_in;
+ wire [3:0] rx_fifordout_wire;
+ wire [0:0] rx_fiforesetrd;
+ wire [3:0] rx_freqlocked_wire;
+ wire [3:0] rx_locktodata_wire;
+ wire [3:0] rx_locktorefclk_wire;
+ wire [0:0] rx_masterclk;
+ wire [63:0] rx_out_wire;
+ wire [1599:0] rx_pcsdprioin_wire;
+ wire [1599:0] rx_pcsdprioout;
+ wire [3:0] rx_phfifooverflowout;
+ wire [3:0] rx_phfifordenable;
+ wire [3:0] rx_phfiforeset;
+ wire [3:0] rx_phfifounderflowout;
+ wire [3:0] rx_phfifowrdisable;
+ wire [3:0] rx_pldcruclk_in;
+ wire [15:0] rx_pll_clkout;
+ wire [3:0] rx_pll_pfdrefclkout_wire;
+ wire [3:0] rx_plllocked_wire;
+ wire [67:0] rx_pma_analogtestbus;
+ wire [3:0] rx_pma_clockout;
+ wire [3:0] rx_pma_dataout;
+ wire [3:0] rx_pma_locktorefout;
+ wire [79:0] rx_pma_recoverdataout_wire;
+ wire [1799:0] rx_pmadprioin_wire;
+ wire [1799:0] rx_pmadprioout;
+ wire [3:0] rx_powerdown;
+ wire [5:0] rx_powerdown_in;
+ wire [3:0] rx_prbscidenable;
+ wire [3:0] rx_rdalign;
+ wire [3:0] rx_rmfiforeset;
+ wire [5:0] rx_rxcruresetout;
+ wire [3:0] rx_syncstatusdeskew;
+ wire [3:0] rx_xgmctrlin;
+ wire [31:0] rx_xgmdataout;
+ wire [3:0] rx_xgmdatavalid;
+ wire [3:0] rx_xgmrunningdisp;
+ wire [0:0] rxphfifowrdisable;
+ wire [1799:0] rxpll_dprioin;
+ wire [5:0] tx_analogreset_out;
+ wire [3:0] tx_clkout_int_wire;
+ wire [3:0] tx_coreclk_in;
+ wire [63:0] tx_datain_wire;
+ wire [79:0] tx_dataout_pcs_to_pma;
+ wire [3:0] tx_digitalreset_in;
+ wire [3:0] tx_digitalreset_out;
+ wire [1199:0] tx_dprioin_wire;
+ wire [7:0] tx_forcedisp_wire;
+ wire [3:0] tx_localrefclk;
+ wire [3:0] tx_phfifooverflowout;
+ wire [3:0] tx_phfiforeset;
+ wire [3:0] tx_phfifounderflowout;
+ wire [1799:0] tx_pmadprioin_wire;
+ wire [1799:0] tx_pmadprioout;
+ wire [3:0] tx_rdenablesync;
+ wire [3:0] tx_serialloopbackout;
+ wire [599:0] tx_txdprioout;
+ wire [3:0] tx_xgmctrlenable;
+ wire [31:0] tx_xgmdataout;
+ wire [3:0] txdetectrxout;
+ wire [0:0] w_cent_unit_dpriodisableout1w;
+
+ // These are synchronized forms digital reset
+ // async inputs go to *digitalreset_reg0c, synced with data path clock
+ // synopsys translate_off
+ initial
+ rx_digitalreset_reg0c[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_rx_digitalreset_reg0c_clk[0:0])
+ rx_digitalreset_reg0c[0:0] <= wire_rx_digitalreset_reg0c_d[0:0];
+ // synopsys translate_off
+ initial
+ rx_digitalreset_reg0c[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_rx_digitalreset_reg0c_clk[1:1])
+ rx_digitalreset_reg0c[1:1] <= wire_rx_digitalreset_reg0c_d[1:1];
+ // synopsys translate_off
+ initial
+ rx_digitalreset_reg0c[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_rx_digitalreset_reg0c_clk[2:2])
+ rx_digitalreset_reg0c[2:2] <= wire_rx_digitalreset_reg0c_d[2:2];
+ assign
+ wire_rx_digitalreset_reg0c_d = {rx_digitalreset_reg0c[1:0], rx_digitalreset[0]};
+ assign
+ wire_rx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
+ // synopsys translate_off
+ initial
+ tx_digitalreset_reg0c[0:0] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_tx_digitalreset_reg0c_clk[0:0])
+ tx_digitalreset_reg0c[0:0] <= wire_tx_digitalreset_reg0c_d[0:0];
+ // synopsys translate_off
+ initial
+ tx_digitalreset_reg0c[1:1] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_tx_digitalreset_reg0c_clk[1:1])
+ tx_digitalreset_reg0c[1:1] <= wire_tx_digitalreset_reg0c_d[1:1];
+ // synopsys translate_off
+ initial
+ tx_digitalreset_reg0c[2:2] = 0;
+ // synopsys translate_on
+ always @ ( posedge wire_tx_digitalreset_reg0c_clk[2:2])
+ tx_digitalreset_reg0c[2:2] <= wire_tx_digitalreset_reg0c_d[2:2];
+ assign
+ wire_tx_digitalreset_reg0c_d = {tx_digitalreset_reg0c[1:0], tx_digitalreset[0]};
+ assign
+ wire_tx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
+
+ // Parameter strings for embedded timing constraints
+ localparam TX_DIGITALRESET_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to {*xaui_phy*tx_digitalreset_reg0c[0]};\""};
+ localparam RX_DIGITALRESET_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to {*xaui_phy*rx_digitalreset_reg0c[0]};\""};
+ localparam SDC_CONSTRAINTS = {TX_DIGITALRESET_CONSTRAINT,";",RX_DIGITALRESET_CONSTRAINT};
+ (* altera_attribute = SDC_CONSTRAINTS *) // Apply timing constraints (does not matter which node)
+
+ stratixiv_hssi_calibration_block cal_blk0
+ (
+ .calibrationstatus(),
+ .clk(cal_blk_clk),
+ .enabletestbus(1'b1),
+ .nonusertocmu(wire_cal_blk0_nonusertocmu),
+ .powerdn(cal_blk_powerdown)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .testctrl(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ stratixiv_hssi_clock_divider central_clk_div0
+ (
+ .analogfastrefclkout(wire_central_clk_div0_analogfastrefclkout),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(wire_central_clk_div0_analogrefclkout),
+ .analogrefclkoutshifted(),
+ .analogrefclkpulse(wire_central_clk_div0_analogrefclkpulse),
+ .analogrefclkpulseshifted(),
+ .clk0in(clk_div_clk0in[3:0]),
+ .coreclkout(wire_central_clk_div0_coreclkout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(cent_unit_cmudividerdprioout[499:400]),
+ .dprioout(wire_central_clk_div0_dprioout),
+ .powerdn(cent_unit_clkdivpowerdn[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchbaseclock(),
+ .rateswitchdone(wire_central_clk_div0_rateswitchdone),
+ .rateswitchout(),
+ .refclkout(wire_central_clk_div0_refclkout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .clk1in({4{1'b0}}),
+ .rateswitch(1'b0),
+ .rateswitchbaseclkin({2{1'b0}}),
+ .rateswitchdonein({2{1'b0}}),
+ .refclkdig(1'b0),
+ .refclkin({2{1'b0}}),
+ .vcobypassin(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ central_clk_div0.divide_by = 5,
+ central_clk_div0.divider_type = "CENTRAL_ENHANCED",
+ central_clk_div0.effective_data_rate = "3125 Mbps",
+ central_clk_div0.enable_dynamic_divider = "false",
+ central_clk_div0.enable_refclk_out = "true",
+ central_clk_div0.inclk_select = 0,
+ central_clk_div0.logical_channel_address = 0,
+ central_clk_div0.pre_divide_by = 1,
+ central_clk_div0.refclkin_select = 0,
+ central_clk_div0.select_local_rate_switch_base_clock = "true",
+ central_clk_div0.select_local_refclk = "true",
+ central_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
+ central_clk_div0.sim_analogrefclkout_phase_shift = 0,
+ central_clk_div0.sim_coreclkout_phase_shift = 0,
+ central_clk_div0.sim_refclkout_phase_shift = 0,
+ central_clk_div0.use_coreclk_out_post_divider = "true",
+ central_clk_div0.use_refclk_post_divider = "false",
+ central_clk_div0.use_vco_bypass = "false",
+ central_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
+ stratixiv_hssi_cmu cent_unit0
+ (
+ .adet(rx_adetectdeskew[3:0]),
+ .alignstatus(wire_cent_unit0_alignstatus),
+ .autospdx4configsel(),
+ .autospdx4rateswitchout(),
+ .autospdx4spdchg(),
+ .clkdivpowerdn(wire_cent_unit0_clkdivpowerdn),
+ .cmudividerdprioin({clk_div_cmudividerdprioin[599:0]}),
+ .cmudividerdprioout(wire_cent_unit0_cmudividerdprioout),
+ .cmuplldprioin(pll_cmuplldprioout[1799:0]),
+ .cmuplldprioout(wire_cent_unit0_cmuplldprioout),
+ .digitaltestout(),
+ .dpclk(reconfig_clk),
+ .dpriodisable(reconfig_togxb_disable),
+ .dpriodisableout(wire_cent_unit0_dpriodisableout),
+ .dprioin(reconfig_togxb_in),
+ .dprioload(reconfig_togxb_load),
+ .dpriooe(),
+ .dprioout(wire_cent_unit0_dprioout),
+ .enabledeskew(wire_cent_unit0_enabledeskew),
+ .extra10gout(),
+ .fiforesetrd(wire_cent_unit0_fiforesetrd),
+ .fixedclk({{2{1'b0}}, fixedclk_to_cmu[3:0]}),
+ .lccmutestbus(),
+ .nonuserfromcal(nonusertocmu_out[0]),
+ .phfifiox4ptrsreset(),
+ .pllpowerdn(wire_cent_unit0_pllpowerdn),
+ .pllresetout(wire_cent_unit0_pllresetout),
+ .quadreset(gxb_powerdown[0]),
+ .quadresetout(wire_cent_unit0_quadresetout),
+ .rateswitchdonein(int_hiprateswtichdone[0]),
+ .rdalign(rx_rdalign[3:0]),
+ .rdenablesync(cent_unit_rdenablesync[0]),
+ .recovclk(rx_masterclk[0]),
+ .refclkdividerdprioin({2{1'b0}}),
+ .refclkdividerdprioout(),
+ .rxadcepowerdown(),
+ .rxadceresetout(),
+ .rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
+ .rxanalogresetout(wire_cent_unit0_rxanalogresetout),
+ .rxclk(refclk_pma[0]),
+ .rxcoreclk(int_rxcoreclk[0]),
+ .rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
+ .rxcruresetout(wire_cent_unit0_rxcruresetout),
+ .rxctrl(cent_unit_rx_ctrl[3:0]),
+ .rxctrlout(wire_cent_unit0_rxctrlout),
+ .rxdatain(rx_xgmdataout[31:0]),
+ .rxdataout(wire_cent_unit0_rxdataout),
+ .rxdatavalid(rx_xgmdatavalid[3:0]),
+ .rxdigitalreset({rx_digitalreset_in[3:0]}),
+ .rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
+ .rxibpowerdown(wire_cent_unit0_rxibpowerdown),
+ .rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
+ .rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
+ .rxphfifordenable(int_rxphfifordenable[0]),
+ .rxphfiforeset(int_rxphfiforeset[0]),
+ .rxphfifowrdisable(rxphfifowrdisable[0]),
+ .rxphfifox4byteselout(wire_cent_unit0_rxphfifox4byteselout),
+ .rxphfifox4rdenableout(wire_cent_unit0_rxphfifox4rdenableout),
+ .rxphfifox4wrclkout(wire_cent_unit0_rxphfifox4wrclkout),
+ .rxphfifox4wrenableout(wire_cent_unit0_rxphfifox4wrenableout),
+ .rxpmadprioin({cent_unit_rxpmadprioin[1799:0]}),
+ .rxpmadprioout(wire_cent_unit0_rxpmadprioout),
+ .rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
+ .rxrunningdisp(rx_xgmrunningdisp[3:0]),
+ .scanout(),
+ .syncstatus(rx_syncstatusdeskew[3:0]),
+ .testout(),
+ .txanalogresetout(wire_cent_unit0_txanalogresetout),
+ .txclk(refclk_pma[0]),
+ .txcoreclk(int_txcoreclk[0]),
+ .txctrl(tx_xgmctrlenable[3:0]),
+ .txctrlout(wire_cent_unit0_txctrlout),
+ .txdatain(tx_xgmdataout[31:0]),
+ .txdataout(wire_cent_unit0_txdataout),
+ .txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
+ .txdigitalreset({tx_digitalreset_in[3:0]}),
+ .txdigitalresetout(wire_cent_unit0_txdigitalresetout),
+ .txdividerpowerdown(),
+ .txobpowerdown(wire_cent_unit0_txobpowerdown),
+ .txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
+ .txpcsdprioout(wire_cent_unit0_txpcsdprioout),
+ .txphfiforddisable(int_txphfiforddisable[0]),
+ .txphfiforeset(int_txphfiforeset[0]),
+ .txphfifowrenable(int_txphfifowrenable[0]),
+ .txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
+ .txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
+ .txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
+ .txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout),
+ .txpllreset({{1{1'b0}}, pll_powerdown[0]}),
+ .txpmadprioin({cent_unit_txpmadprioin[1799:0]}),
+ .txpmadprioout(wire_cent_unit0_txpmadprioout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .extra10gin({7{1'b0}}),
+ .lccmurtestbussel({3{1'b0}}),
+ .pmacramtest(1'b0),
+ .rateswitch(1'b0),
+ .scanclk(1'b0),
+ .scanin({23{1'b0}}),
+ .scanmode(1'b0),
+ .scanshift(1'b0),
+ .testin({10000{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ cent_unit0.auto_spd_phystatus_notify_count = 0,
+ cent_unit0.bonded_quad_mode = "none",
+ cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
+ cent_unit0.in_xaui_mode = "true",
+ cent_unit0.offset_all_errors_align = "false",
+ cent_unit0.pipe_auto_speed_nego_enable = "false",
+ cent_unit0.pipe_freq_scale_mode = "Frequency",
+ cent_unit0.pma_done_count = 249950,
+ cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
+ cent_unit0.rx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.rx0_channel_bonding = "x4",
+ cent_unit0.rx0_clk1_mux_select = "master clock",
+ cent_unit0.rx0_clk2_mux_select = "digital reference clock",
+ cent_unit0.rx0_ph_fifo_reg_mode = "false",
+ cent_unit0.rx0_rd_clk_mux_select = "core clock",
+ cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
+ cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
+ cent_unit0.rx0_use_double_data_mode = "true",
+ cent_unit0.tx0_auto_spd_self_switch_enable = "false",
+ cent_unit0.tx0_channel_bonding = "x4",
+ cent_unit0.tx0_ph_fifo_reg_mode = "false",
+ cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
+ cent_unit0.tx0_use_double_data_mode = "true",
+ cent_unit0.tx0_wr_clk_mux_select = "core_clk",
+ cent_unit0.use_deskew_fifo = "true",
+ cent_unit0.vcceh_voltage = "Auto",
+ cent_unit0.lpm_type = "stratixiv_hssi_cmu";
+ stratixiv_hssi_pll rx_cdr_pll0
+ (
+ .areset(rx_rxcruresetout[0]),
+ .clk(wire_rx_cdr_pll0_clk),
+ .datain(rx_pma_dataout[0]),
+ .dataout(wire_rx_cdr_pll0_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[299:0]),
+ .dprioout(wire_rx_cdr_pll0_dprioout),
+ .freqlocked(wire_rx_cdr_pll0_freqlocked),
+ .inclk({rx_cruclk_in[9:0]}),
+ .locked(wire_rx_cdr_pll0_locked),
+ .locktorefclk(rx_pma_locktorefout[0]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll0.bandwidth_type = "Auto",
+ rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
+ rx_cdr_pll0.dprio_config_mode = 6'h00,
+ rx_cdr_pll0.effective_data_rate = "3125 Mbps",
+ rx_cdr_pll0.enable_dynamic_divider = "false",
+ rx_cdr_pll0.fast_lock_control = "false",
+ rx_cdr_pll0.inclk0_input_period = 6400,
+ rx_cdr_pll0.input_clock_frequency = "156.25 MHz",
+ rx_cdr_pll0.m = 10,
+ rx_cdr_pll0.n = 1,
+ rx_cdr_pll0.pfd_clk_select = 0,
+ rx_cdr_pll0.pll_type = "RX CDR",
+ rx_cdr_pll0.use_refclk_pin = "false",
+ rx_cdr_pll0.vco_post_scale = 2,
+ rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll1
+ (
+ .areset(rx_rxcruresetout[1]),
+ .clk(wire_rx_cdr_pll1_clk),
+ .datain(rx_pma_dataout[1]),
+ .dataout(wire_rx_cdr_pll1_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[599:300]),
+ .dprioout(wire_rx_cdr_pll1_dprioout),
+ .freqlocked(wire_rx_cdr_pll1_freqlocked),
+ .inclk({rx_cruclk_in[19:10]}),
+ .locked(wire_rx_cdr_pll1_locked),
+ .locktorefclk(rx_pma_locktorefout[1]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll1_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[1]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll1.bandwidth_type = "Auto",
+ rx_cdr_pll1.channel_num = ((starting_channel_number + 1) % 4),
+ rx_cdr_pll1.dprio_config_mode = 6'h00,
+ rx_cdr_pll1.effective_data_rate = "3125 Mbps",
+ rx_cdr_pll1.enable_dynamic_divider = "false",
+ rx_cdr_pll1.fast_lock_control = "false",
+ rx_cdr_pll1.inclk0_input_period = 6400,
+ rx_cdr_pll1.input_clock_frequency = "156.25 MHz",
+ rx_cdr_pll1.m = 10,
+ rx_cdr_pll1.n = 1,
+ rx_cdr_pll1.pfd_clk_select = 0,
+ rx_cdr_pll1.pll_type = "RX CDR",
+ rx_cdr_pll1.use_refclk_pin = "false",
+ rx_cdr_pll1.vco_post_scale = 2,
+ rx_cdr_pll1.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll2
+ (
+ .areset(rx_rxcruresetout[2]),
+ .clk(wire_rx_cdr_pll2_clk),
+ .datain(rx_pma_dataout[2]),
+ .dataout(wire_rx_cdr_pll2_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[899:600]),
+ .dprioout(wire_rx_cdr_pll2_dprioout),
+ .freqlocked(wire_rx_cdr_pll2_freqlocked),
+ .inclk({rx_cruclk_in[29:20]}),
+ .locked(wire_rx_cdr_pll2_locked),
+ .locktorefclk(rx_pma_locktorefout[2]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll2_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[2]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll2.bandwidth_type = "Auto",
+ rx_cdr_pll2.channel_num = ((starting_channel_number + 2) % 4),
+ rx_cdr_pll2.dprio_config_mode = 6'h00,
+ rx_cdr_pll2.effective_data_rate = "3125 Mbps",
+ rx_cdr_pll2.enable_dynamic_divider = "false",
+ rx_cdr_pll2.fast_lock_control = "false",
+ rx_cdr_pll2.inclk0_input_period = 6400,
+ rx_cdr_pll2.input_clock_frequency = "156.25 MHz",
+ rx_cdr_pll2.m = 10,
+ rx_cdr_pll2.n = 1,
+ rx_cdr_pll2.pfd_clk_select = 0,
+ rx_cdr_pll2.pll_type = "RX CDR",
+ rx_cdr_pll2.use_refclk_pin = "false",
+ rx_cdr_pll2.vco_post_scale = 2,
+ rx_cdr_pll2.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll rx_cdr_pll3
+ (
+ .areset(rx_rxcruresetout[3]),
+ .clk(wire_rx_cdr_pll3_clk),
+ .datain(rx_pma_dataout[3]),
+ .dataout(wire_rx_cdr_pll3_dataout),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rxpll_dprioin[1199:900]),
+ .dprioout(wire_rx_cdr_pll3_dprioout),
+ .freqlocked(wire_rx_cdr_pll3_freqlocked),
+ .inclk({rx_cruclk_in[39:30]}),
+ .locked(wire_rx_cdr_pll3_locked),
+ .locktorefclk(rx_pma_locktorefout[3]),
+ .pfdfbclkout(),
+ .pfdrefclkout(wire_rx_cdr_pll3_pfdrefclkout),
+ .powerdown(cent_unit_rxcrupowerdn[3]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ rx_cdr_pll3.bandwidth_type = "Auto",
+ rx_cdr_pll3.channel_num = ((starting_channel_number + 3) % 4),
+ rx_cdr_pll3.dprio_config_mode = 6'h00,
+ rx_cdr_pll3.effective_data_rate = "3125 Mbps",
+ rx_cdr_pll3.enable_dynamic_divider = "false",
+ rx_cdr_pll3.fast_lock_control = "false",
+ rx_cdr_pll3.inclk0_input_period = 6400,
+ rx_cdr_pll3.input_clock_frequency = "156.25 MHz",
+ rx_cdr_pll3.m = 10,
+ rx_cdr_pll3.n = 1,
+ rx_cdr_pll3.pfd_clk_select = 0,
+ rx_cdr_pll3.pll_type = "RX CDR",
+ rx_cdr_pll3.use_refclk_pin = "false",
+ rx_cdr_pll3.vco_post_scale = 2,
+ rx_cdr_pll3.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_pll tx_pll0
+ (
+ .areset(pllreset_in[0]),
+ .clk(wire_tx_pll0_clk),
+ .dataout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(pll0_dprioin[299:0]),
+ .dprioout(wire_tx_pll0_dprioout),
+ .freqlocked(),
+ .inclk({pll0_clkin[9:0]}),
+ .locked(wire_tx_pll0_locked),
+ .pfdfbclkout(),
+ .pfdrefclkout(),
+ .powerdown(pllpowerdn_in[0]),
+ .vcobypassout()
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datain(1'b0),
+ .earlyeios(1'b0),
+ .extra10gin({6{1'b0}}),
+ .locktorefclk(1'b1),
+ .pfdfbclk(1'b0),
+ .rateswitch(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ tx_pll0.bandwidth_type = "Auto",
+ tx_pll0.channel_num = 4,
+ tx_pll0.dprio_config_mode = 6'h00,
+ tx_pll0.inclk0_input_period = 6400,
+ tx_pll0.input_clock_frequency = "156.25 MHz",
+ tx_pll0.logical_tx_pll_number = 0,
+ tx_pll0.m = 10,
+ tx_pll0.n = 1,
+ tx_pll0.pfd_clk_select = 0,
+ tx_pll0.pfd_fb_select = "internal",
+ tx_pll0.pll_type = "CMU",
+ tx_pll0.use_refclk_pin = "false",
+ tx_pll0.vco_post_scale = 2,
+ tx_pll0.lpm_type = "stratixiv_hssi_pll";
+ stratixiv_hssi_rx_pcs receive_pcs0
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(wire_receive_pcs0_adetectdeskew),
+ .alignstatus(rx_channelaligned_in[0]),
+ .alignstatussync(rx_alignstatussync[0]),
+ .alignstatussyncout(wire_receive_pcs0_alignstatussyncout),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefcl((reconfig_togxb_busy | rx_locktorefclk[0])),
+ .cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
+ .clkout(wire_receive_pcs0_clkout),
+ .coreclk(rx_coreclk_in[0]),
+ .coreclkout(wire_receive_pcs0_coreclkout),
+ .ctrldetect(wire_receive_pcs0_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[19:0]),
+ .dataout(wire_receive_pcs0_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[0]),
+ .digitaltestout(),
+ .disablefifordin(rx_disablefifordin_in[0]),
+ .disablefifordout(wire_receive_pcs0_disablefifordout),
+ .disablefifowrin(rx_disablefifowrin_in[0]),
+ .disablefifowrout(wire_receive_pcs0_disablefifowrout),
+ .disperr(wire_receive_pcs0_disperr),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[399:0]),
+ .dprioout(wire_receive_pcs0_dprioout),
+ .enabledeskew(enabledeskew[0]),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[0]),
+ .errdetect(wire_receive_pcs0_errdetect),
+ .fifordin(rx_fifordin_in[0]),
+ .fifordout(wire_receive_pcs0_fifordout),
+ .fiforesetrd(rx_fiforesetrd[0]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(rx_invpolarity[0]),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(rx_masterclk[0]),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs0_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs0_phfifobyteserdisableout),
+ .phfifooverflow(wire_receive_pcs0_phfifooverflow),
+ .phfifoptrsresetout(wire_receive_pcs0_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[0]),
+ .phfifordenableout(wire_receive_pcs0_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[0]),
+ .phfiforesetout(wire_receive_pcs0_phfiforesetout),
+ .phfifounderflow(wire_receive_pcs0_phfifounderflow),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[0]),
+ .phfifowrdisableout(wire_receive_pcs0_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[2:0]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[2:0]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[2:0]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[2:0]),
+ .pipebufferstat(),
+ .pipedatavalid(),
+ .pipeelecidle(),
+ .pipephydonestatus(),
+ .pipepowerdown({2{1'b0}}),
+ .pipepowerstate({4{1'b0}}),
+ .pipestatetransdoneout(),
+ .pipestatus(),
+ .prbscidenable(rx_prbscidenable[0]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs0_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(wire_receive_pcs0_rdalign),
+ .recoveredclk(rx_pma_clockout[0]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(),
+ .rlv(wire_receive_pcs0_rlv),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(wire_receive_pcs0_rmfifodatadeleted),
+ .rmfifodatainserted(wire_receive_pcs0_rmfifodatainserted),
+ .rmfifoempty(wire_receive_pcs0_rmfifoempty),
+ .rmfifofull(wire_receive_pcs0_rmfifofull),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[0]),
+ .rmfifowrena(1'b0),
+ .runningdisp(wire_receive_pcs0_runningdisp),
+ .rxdetectvalid(1'b0),
+ .rxfound({2{1'b0}}),
+ .signaldetect(),
+ .syncstatus(wire_receive_pcs0_syncstatus),
+ .syncstatusdeskew(wire_receive_pcs0_syncstatusdeskew),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(wire_receive_pcs0_xgmctrldet),
+ .xgmctrlin(rx_xgmctrlin[0]),
+ .xgmdatain(cent_unit_rx_xgmdataout[7:0]),
+ .xgmdataout(wire_receive_pcs0_xgmdataout),
+ .xgmdatavalid(wire_receive_pcs0_xgmdatavalid),
+ .xgmrunningdisp(wire_receive_pcs0_xgmrunningdisp)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .elecidleinfersel({3{1'b0}}),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipe8b10binvpolarity(1'b0),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .powerdn({2{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .signaldetected(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs0.align_pattern = "0101111100",
+ receive_pcs0.align_pattern_length = 10,
+ receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs0.allow_align_polarity_inversion = "true",
+ receive_pcs0.allow_pipe_polarity_inversion = "false",
+ receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs0.auto_spd_phystatus_notify_count = 0,
+ receive_pcs0.auto_spd_self_switch_enable = "false",
+ receive_pcs0.bit_slip_enable = "false",
+ receive_pcs0.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs0.byte_order_mode = "none",
+ receive_pcs0.byte_order_pad_pattern = "0",
+ receive_pcs0.byte_order_pattern = "0",
+ receive_pcs0.byte_order_pld_ctrl_enable = "false",
+ receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs0.cdrctrl_enable = "false",
+ receive_pcs0.cdrctrl_mask_cycle = 800,
+ receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs0.cdrctrl_rxvalid_mask = "false",
+ receive_pcs0.channel_bonding = "x4",
+ receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pcs0.channel_width = 16,
+ receive_pcs0.clk1_mux_select = "master clock",
+ receive_pcs0.clk2_mux_select = "digital reference clock",
+ receive_pcs0.core_clock_0ppm = "true",
+ receive_pcs0.datapath_low_latency_mode = "false",
+ receive_pcs0.datapath_protocol = "xaui",
+ receive_pcs0.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs0.dec_8b_10b_mode = "normal",
+ receive_pcs0.dec_8b_10b_polarity_inv_enable = "false",
+ receive_pcs0.deskew_pattern = "0011000011",
+ receive_pcs0.disable_auto_idle_insertion = "true",
+ receive_pcs0.disable_running_disp_in_word_align = "false",
+ receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs0.dprio_config_mode = 6'h01,
+ receive_pcs0.elec_idle_infer_enable = "false",
+ receive_pcs0.elec_idle_num_com_detect = 3,
+ receive_pcs0.enable_bit_reversal = "false",
+ receive_pcs0.enable_deep_align = "false",
+ receive_pcs0.enable_deep_align_byte_swap = "false",
+ receive_pcs0.enable_self_test_mode = "false",
+ receive_pcs0.enable_true_complement_match_in_word_align = "false",
+ receive_pcs0.force_signal_detect_dig = "true",
+ receive_pcs0.hip_enable = "false",
+ receive_pcs0.infiniband_invalid_code = 0,
+ receive_pcs0.insert_pad_on_underflow = "false",
+ receive_pcs0.logical_channel_address = (starting_channel_number + 0),
+ receive_pcs0.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs0.num_align_cons_good_data = 4,
+ receive_pcs0.num_align_cons_pat = 4,
+ receive_pcs0.num_align_loss_sync_error = 4,
+ receive_pcs0.ph_fifo_low_latency_enable = "true",
+ receive_pcs0.ph_fifo_reg_mode = "false",
+ receive_pcs0.ph_fifo_xn_mapping0 = "none",
+ receive_pcs0.ph_fifo_xn_mapping1 = "none",
+ receive_pcs0.ph_fifo_xn_mapping2 = "central",
+ receive_pcs0.ph_fifo_xn_select = 2,
+ receive_pcs0.pipe_auto_speed_nego_enable = "false",
+ receive_pcs0.pipe_freq_scale_mode = "Frequency",
+ receive_pcs0.pma_done_count = 249950,
+ receive_pcs0.protocol_hint = "xaui",
+ receive_pcs0.rate_match_almost_empty_threshold = 11,
+ receive_pcs0.rate_match_almost_full_threshold = 13,
+ receive_pcs0.rate_match_back_to_back = "true",
+ receive_pcs0.rate_match_delete_threshold = 13,
+ receive_pcs0.rate_match_empty_threshold = 5,
+ receive_pcs0.rate_match_fifo_mode = "true",
+ receive_pcs0.rate_match_full_threshold = 20,
+ receive_pcs0.rate_match_insert_threshold = 11,
+ receive_pcs0.rate_match_ordered_set_based = "false",
+ receive_pcs0.rate_match_pattern1 = "1101000011",
+ receive_pcs0.rate_match_pattern2 = "0010111100",
+ receive_pcs0.rate_match_pattern_size = 10,
+ receive_pcs0.rate_match_reset_enable = "false",
+ receive_pcs0.rate_match_skip_set_based = "false",
+ receive_pcs0.rate_match_start_threshold = 7,
+ receive_pcs0.rd_clk_mux_select = "core clock",
+ receive_pcs0.recovered_clk_mux_select = "recovered clock",
+ receive_pcs0.run_length = 40,
+ receive_pcs0.run_length_enable = "true",
+ receive_pcs0.rx_detect_bypass = "false",
+ receive_pcs0.rx_phfifo_wait_cnt = 15,
+ receive_pcs0.rxstatus_error_report_mode = 0,
+ receive_pcs0.self_test_mode = "incremental",
+ receive_pcs0.use_alignment_state_machine = "true",
+ receive_pcs0.use_deserializer_double_data_mode = "false",
+ receive_pcs0.use_deskew_fifo = "true",
+ receive_pcs0.use_double_data_mode = "true",
+ receive_pcs0.use_parallel_loopback = "false",
+ receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs1
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(wire_receive_pcs1_adetectdeskew),
+ .alignstatus(rx_channelaligned_in[0]),
+ .alignstatussync(rx_alignstatussync[0]),
+ .alignstatussyncout(wire_receive_pcs1_alignstatussyncout),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefcl((reconfig_togxb_busy | rx_locktorefclk[1])),
+ .cdrctrllocktorefclkout(wire_receive_pcs1_cdrctrllocktorefclkout),
+ .clkout(wire_receive_pcs1_clkout),
+ .coreclk(rx_coreclk_in[1]),
+ .coreclkout(wire_receive_pcs1_coreclkout),
+ .ctrldetect(wire_receive_pcs1_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[39:20]),
+ .dataout(wire_receive_pcs1_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[1]),
+ .digitaltestout(),
+ .disablefifordin(rx_disablefifordin_in[0]),
+ .disablefifordout(wire_receive_pcs1_disablefifordout),
+ .disablefifowrin(rx_disablefifowrin_in[0]),
+ .disablefifowrout(wire_receive_pcs1_disablefifowrout),
+ .disperr(wire_receive_pcs1_disperr),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[799:400]),
+ .dprioout(wire_receive_pcs1_dprioout),
+ .enabledeskew(enabledeskew[0]),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[1]),
+ .errdetect(wire_receive_pcs1_errdetect),
+ .fifordin(rx_fifordin_in[0]),
+ .fifordout(wire_receive_pcs1_fifordout),
+ .fiforesetrd(rx_fiforesetrd[0]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(rx_invpolarity[1]),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(rx_masterclk[0]),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs1_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs1_phfifobyteserdisableout),
+ .phfifooverflow(wire_receive_pcs1_phfifooverflow),
+ .phfifoptrsresetout(wire_receive_pcs1_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[1]),
+ .phfifordenableout(wire_receive_pcs1_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[1]),
+ .phfiforesetout(wire_receive_pcs1_phfiforesetout),
+ .phfifounderflow(wire_receive_pcs1_phfifounderflow),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[1]),
+ .phfifowrdisableout(wire_receive_pcs1_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[5:3]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[5:3]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[5:3]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[5:3]),
+ .pipebufferstat(),
+ .pipedatavalid(),
+ .pipeelecidle(),
+ .pipephydonestatus(),
+ .pipepowerdown({2{1'b0}}),
+ .pipepowerstate({4{1'b0}}),
+ .pipestatetransdoneout(),
+ .pipestatus(),
+ .prbscidenable(rx_prbscidenable[1]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs1_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(wire_receive_pcs1_rdalign),
+ .recoveredclk(rx_pma_clockout[1]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(),
+ .rlv(wire_receive_pcs1_rlv),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(wire_receive_pcs1_rmfifodatadeleted),
+ .rmfifodatainserted(wire_receive_pcs1_rmfifodatainserted),
+ .rmfifoempty(wire_receive_pcs1_rmfifoempty),
+ .rmfifofull(wire_receive_pcs1_rmfifofull),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[1]),
+ .rmfifowrena(1'b0),
+ .runningdisp(wire_receive_pcs1_runningdisp),
+ .rxdetectvalid(1'b0),
+ .rxfound({2{1'b0}}),
+ .signaldetect(),
+ .syncstatus(wire_receive_pcs1_syncstatus),
+ .syncstatusdeskew(wire_receive_pcs1_syncstatusdeskew),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(wire_receive_pcs1_xgmctrldet),
+ .xgmctrlin(rx_xgmctrlin[1]),
+ .xgmdatain(cent_unit_rx_xgmdataout[15:8]),
+ .xgmdataout(wire_receive_pcs1_xgmdataout),
+ .xgmdatavalid(wire_receive_pcs1_xgmdatavalid),
+ .xgmrunningdisp(wire_receive_pcs1_xgmrunningdisp)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .elecidleinfersel({3{1'b0}}),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipe8b10binvpolarity(1'b0),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .powerdn({2{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .signaldetected(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs1.align_pattern = "0101111100",
+ receive_pcs1.align_pattern_length = 10,
+ receive_pcs1.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs1.allow_align_polarity_inversion = "true",
+ receive_pcs1.allow_pipe_polarity_inversion = "false",
+ receive_pcs1.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs1.auto_spd_phystatus_notify_count = 0,
+ receive_pcs1.auto_spd_self_switch_enable = "false",
+ receive_pcs1.bit_slip_enable = "false",
+ receive_pcs1.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs1.byte_order_mode = "none",
+ receive_pcs1.byte_order_pad_pattern = "0",
+ receive_pcs1.byte_order_pattern = "0",
+ receive_pcs1.byte_order_pld_ctrl_enable = "false",
+ receive_pcs1.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs1.cdrctrl_enable = "false",
+ receive_pcs1.cdrctrl_mask_cycle = 800,
+ receive_pcs1.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs1.cdrctrl_rxvalid_mask = "false",
+ receive_pcs1.channel_bonding = "x4",
+ receive_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pcs1.channel_width = 16,
+ receive_pcs1.clk1_mux_select = "master clock",
+ receive_pcs1.clk2_mux_select = "digital reference clock",
+ receive_pcs1.core_clock_0ppm = "true",
+ receive_pcs1.datapath_low_latency_mode = "false",
+ receive_pcs1.datapath_protocol = "xaui",
+ receive_pcs1.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs1.dec_8b_10b_mode = "normal",
+ receive_pcs1.dec_8b_10b_polarity_inv_enable = "false",
+ receive_pcs1.deskew_pattern = "0011000011",
+ receive_pcs1.disable_auto_idle_insertion = "true",
+ receive_pcs1.disable_running_disp_in_word_align = "false",
+ receive_pcs1.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs1.dprio_config_mode = 6'h01,
+ receive_pcs1.elec_idle_infer_enable = "false",
+ receive_pcs1.elec_idle_num_com_detect = 3,
+ receive_pcs1.enable_bit_reversal = "false",
+ receive_pcs1.enable_deep_align = "false",
+ receive_pcs1.enable_deep_align_byte_swap = "false",
+ receive_pcs1.enable_self_test_mode = "false",
+ receive_pcs1.enable_true_complement_match_in_word_align = "false",
+ receive_pcs1.force_signal_detect_dig = "true",
+ receive_pcs1.hip_enable = "false",
+ receive_pcs1.infiniband_invalid_code = 0,
+ receive_pcs1.insert_pad_on_underflow = "false",
+ receive_pcs1.logical_channel_address = (starting_channel_number + 1),
+ receive_pcs1.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs1.num_align_cons_good_data = 4,
+ receive_pcs1.num_align_cons_pat = 4,
+ receive_pcs1.num_align_loss_sync_error = 4,
+ receive_pcs1.ph_fifo_low_latency_enable = "true",
+ receive_pcs1.ph_fifo_reg_mode = "false",
+ receive_pcs1.ph_fifo_xn_mapping0 = "none",
+ receive_pcs1.ph_fifo_xn_mapping1 = "none",
+ receive_pcs1.ph_fifo_xn_mapping2 = "central",
+ receive_pcs1.ph_fifo_xn_select = 2,
+ receive_pcs1.pipe_auto_speed_nego_enable = "false",
+ receive_pcs1.pipe_freq_scale_mode = "Frequency",
+ receive_pcs1.pma_done_count = 249950,
+ receive_pcs1.protocol_hint = "xaui",
+ receive_pcs1.rate_match_almost_empty_threshold = 11,
+ receive_pcs1.rate_match_almost_full_threshold = 13,
+ receive_pcs1.rate_match_back_to_back = "true",
+ receive_pcs1.rate_match_delete_threshold = 13,
+ receive_pcs1.rate_match_empty_threshold = 5,
+ receive_pcs1.rate_match_fifo_mode = "true",
+ receive_pcs1.rate_match_full_threshold = 20,
+ receive_pcs1.rate_match_insert_threshold = 11,
+ receive_pcs1.rate_match_ordered_set_based = "false",
+ receive_pcs1.rate_match_pattern1 = "1101000011",
+ receive_pcs1.rate_match_pattern2 = "0010111100",
+ receive_pcs1.rate_match_pattern_size = 10,
+ receive_pcs1.rate_match_reset_enable = "false",
+ receive_pcs1.rate_match_skip_set_based = "false",
+ receive_pcs1.rate_match_start_threshold = 7,
+ receive_pcs1.rd_clk_mux_select = "core clock",
+ receive_pcs1.recovered_clk_mux_select = "recovered clock",
+ receive_pcs1.run_length = 40,
+ receive_pcs1.run_length_enable = "true",
+ receive_pcs1.rx_detect_bypass = "false",
+ receive_pcs1.rx_phfifo_wait_cnt = 15,
+ receive_pcs1.rxstatus_error_report_mode = 0,
+ receive_pcs1.self_test_mode = "incremental",
+ receive_pcs1.use_alignment_state_machine = "true",
+ receive_pcs1.use_deserializer_double_data_mode = "false",
+ receive_pcs1.use_deskew_fifo = "true",
+ receive_pcs1.use_double_data_mode = "true",
+ receive_pcs1.use_parallel_loopback = "false",
+ receive_pcs1.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs1.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs2
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(wire_receive_pcs2_adetectdeskew),
+ .alignstatus(rx_channelaligned_in[0]),
+ .alignstatussync(rx_alignstatussync[0]),
+ .alignstatussyncout(wire_receive_pcs2_alignstatussyncout),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefcl((reconfig_togxb_busy | rx_locktorefclk[2])),
+ .cdrctrllocktorefclkout(wire_receive_pcs2_cdrctrllocktorefclkout),
+ .clkout(wire_receive_pcs2_clkout),
+ .coreclk(rx_coreclk_in[2]),
+ .coreclkout(wire_receive_pcs2_coreclkout),
+ .ctrldetect(wire_receive_pcs2_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[59:40]),
+ .dataout(wire_receive_pcs2_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[2]),
+ .digitaltestout(),
+ .disablefifordin(rx_disablefifordin_in[0]),
+ .disablefifordout(wire_receive_pcs2_disablefifordout),
+ .disablefifowrin(rx_disablefifowrin_in[0]),
+ .disablefifowrout(wire_receive_pcs2_disablefifowrout),
+ .disperr(wire_receive_pcs2_disperr),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[1199:800]),
+ .dprioout(wire_receive_pcs2_dprioout),
+ .enabledeskew(enabledeskew[0]),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[2]),
+ .errdetect(wire_receive_pcs2_errdetect),
+ .fifordin(rx_fifordin_in[0]),
+ .fifordout(wire_receive_pcs2_fifordout),
+ .fiforesetrd(rx_fiforesetrd[0]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(rx_invpolarity[2]),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(rx_masterclk[0]),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs2_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs2_phfifobyteserdisableout),
+ .phfifooverflow(wire_receive_pcs2_phfifooverflow),
+ .phfifoptrsresetout(wire_receive_pcs2_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[2]),
+ .phfifordenableout(wire_receive_pcs2_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[2]),
+ .phfiforesetout(wire_receive_pcs2_phfiforesetout),
+ .phfifounderflow(wire_receive_pcs2_phfifounderflow),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[2]),
+ .phfifowrdisableout(wire_receive_pcs2_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[8:6]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[8:6]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[8:6]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[8:6]),
+ .pipebufferstat(),
+ .pipedatavalid(),
+ .pipeelecidle(),
+ .pipephydonestatus(),
+ .pipepowerdown({2{1'b0}}),
+ .pipepowerstate({4{1'b0}}),
+ .pipestatetransdoneout(),
+ .pipestatus(),
+ .prbscidenable(rx_prbscidenable[2]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs2_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(wire_receive_pcs2_rdalign),
+ .recoveredclk(rx_pma_clockout[2]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(),
+ .rlv(wire_receive_pcs2_rlv),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(wire_receive_pcs2_rmfifodatadeleted),
+ .rmfifodatainserted(wire_receive_pcs2_rmfifodatainserted),
+ .rmfifoempty(wire_receive_pcs2_rmfifoempty),
+ .rmfifofull(wire_receive_pcs2_rmfifofull),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[2]),
+ .rmfifowrena(1'b0),
+ .runningdisp(wire_receive_pcs2_runningdisp),
+ .rxdetectvalid(1'b0),
+ .rxfound({2{1'b0}}),
+ .signaldetect(),
+ .syncstatus(wire_receive_pcs2_syncstatus),
+ .syncstatusdeskew(wire_receive_pcs2_syncstatusdeskew),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(wire_receive_pcs2_xgmctrldet),
+ .xgmctrlin(rx_xgmctrlin[2]),
+ .xgmdatain(cent_unit_rx_xgmdataout[23:16]),
+ .xgmdataout(wire_receive_pcs2_xgmdataout),
+ .xgmdatavalid(wire_receive_pcs2_xgmdatavalid),
+ .xgmrunningdisp(wire_receive_pcs2_xgmrunningdisp)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .elecidleinfersel({3{1'b0}}),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipe8b10binvpolarity(1'b0),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .powerdn({2{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .signaldetected(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs2.align_pattern = "0101111100",
+ receive_pcs2.align_pattern_length = 10,
+ receive_pcs2.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs2.allow_align_polarity_inversion = "true",
+ receive_pcs2.allow_pipe_polarity_inversion = "false",
+ receive_pcs2.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs2.auto_spd_phystatus_notify_count = 0,
+ receive_pcs2.auto_spd_self_switch_enable = "false",
+ receive_pcs2.bit_slip_enable = "false",
+ receive_pcs2.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs2.byte_order_mode = "none",
+ receive_pcs2.byte_order_pad_pattern = "0",
+ receive_pcs2.byte_order_pattern = "0",
+ receive_pcs2.byte_order_pld_ctrl_enable = "false",
+ receive_pcs2.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs2.cdrctrl_enable = "false",
+ receive_pcs2.cdrctrl_mask_cycle = 800,
+ receive_pcs2.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs2.cdrctrl_rxvalid_mask = "false",
+ receive_pcs2.channel_bonding = "x4",
+ receive_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pcs2.channel_width = 16,
+ receive_pcs2.clk1_mux_select = "master clock",
+ receive_pcs2.clk2_mux_select = "digital reference clock",
+ receive_pcs2.core_clock_0ppm = "true",
+ receive_pcs2.datapath_low_latency_mode = "false",
+ receive_pcs2.datapath_protocol = "xaui",
+ receive_pcs2.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs2.dec_8b_10b_mode = "normal",
+ receive_pcs2.dec_8b_10b_polarity_inv_enable = "false",
+ receive_pcs2.deskew_pattern = "0011000011",
+ receive_pcs2.disable_auto_idle_insertion = "true",
+ receive_pcs2.disable_running_disp_in_word_align = "false",
+ receive_pcs2.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs2.dprio_config_mode = 6'h01,
+ receive_pcs2.elec_idle_infer_enable = "false",
+ receive_pcs2.elec_idle_num_com_detect = 3,
+ receive_pcs2.enable_bit_reversal = "false",
+ receive_pcs2.enable_deep_align = "false",
+ receive_pcs2.enable_deep_align_byte_swap = "false",
+ receive_pcs2.enable_self_test_mode = "false",
+ receive_pcs2.enable_true_complement_match_in_word_align = "false",
+ receive_pcs2.force_signal_detect_dig = "true",
+ receive_pcs2.hip_enable = "false",
+ receive_pcs2.infiniband_invalid_code = 0,
+ receive_pcs2.insert_pad_on_underflow = "false",
+ receive_pcs2.logical_channel_address = (starting_channel_number + 2),
+ receive_pcs2.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs2.num_align_cons_good_data = 4,
+ receive_pcs2.num_align_cons_pat = 4,
+ receive_pcs2.num_align_loss_sync_error = 4,
+ receive_pcs2.ph_fifo_low_latency_enable = "true",
+ receive_pcs2.ph_fifo_reg_mode = "false",
+ receive_pcs2.ph_fifo_xn_mapping0 = "none",
+ receive_pcs2.ph_fifo_xn_mapping1 = "none",
+ receive_pcs2.ph_fifo_xn_mapping2 = "central",
+ receive_pcs2.ph_fifo_xn_select = 2,
+ receive_pcs2.pipe_auto_speed_nego_enable = "false",
+ receive_pcs2.pipe_freq_scale_mode = "Frequency",
+ receive_pcs2.pma_done_count = 249950,
+ receive_pcs2.protocol_hint = "xaui",
+ receive_pcs2.rate_match_almost_empty_threshold = 11,
+ receive_pcs2.rate_match_almost_full_threshold = 13,
+ receive_pcs2.rate_match_back_to_back = "true",
+ receive_pcs2.rate_match_delete_threshold = 13,
+ receive_pcs2.rate_match_empty_threshold = 5,
+ receive_pcs2.rate_match_fifo_mode = "true",
+ receive_pcs2.rate_match_full_threshold = 20,
+ receive_pcs2.rate_match_insert_threshold = 11,
+ receive_pcs2.rate_match_ordered_set_based = "false",
+ receive_pcs2.rate_match_pattern1 = "1101000011",
+ receive_pcs2.rate_match_pattern2 = "0010111100",
+ receive_pcs2.rate_match_pattern_size = 10,
+ receive_pcs2.rate_match_reset_enable = "false",
+ receive_pcs2.rate_match_skip_set_based = "false",
+ receive_pcs2.rate_match_start_threshold = 7,
+ receive_pcs2.rd_clk_mux_select = "core clock",
+ receive_pcs2.recovered_clk_mux_select = "recovered clock",
+ receive_pcs2.run_length = 40,
+ receive_pcs2.run_length_enable = "true",
+ receive_pcs2.rx_detect_bypass = "false",
+ receive_pcs2.rx_phfifo_wait_cnt = 15,
+ receive_pcs2.rxstatus_error_report_mode = 0,
+ receive_pcs2.self_test_mode = "incremental",
+ receive_pcs2.use_alignment_state_machine = "true",
+ receive_pcs2.use_deserializer_double_data_mode = "false",
+ receive_pcs2.use_deskew_fifo = "true",
+ receive_pcs2.use_double_data_mode = "true",
+ receive_pcs2.use_parallel_loopback = "false",
+ receive_pcs2.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs2.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pcs receive_pcs3
+ (
+ .a1a2size(1'b0),
+ .a1a2sizeout(),
+ .a1detect(),
+ .a2detect(),
+ .adetectdeskew(wire_receive_pcs3_adetectdeskew),
+ .alignstatus(rx_channelaligned_in[0]),
+ .alignstatussync(rx_alignstatussync[0]),
+ .alignstatussyncout(wire_receive_pcs3_alignstatussyncout),
+ .autospdrateswitchout(),
+ .autospdspdchgout(),
+ .bistdone(),
+ .bisterr(),
+ .bitslipboundaryselectout(),
+ .byteorderalignstatus(),
+ .cdrctrlearlyeios(),
+ .cdrctrllocktorefcl((reconfig_togxb_busy | rx_locktorefclk[3])),
+ .cdrctrllocktorefclkout(wire_receive_pcs3_cdrctrllocktorefclkout),
+ .clkout(wire_receive_pcs3_clkout),
+ .coreclk(rx_coreclk_in[3]),
+ .coreclkout(wire_receive_pcs3_coreclkout),
+ .ctrldetect(wire_receive_pcs3_ctrldetect),
+ .datain(rx_pma_recoverdataout_wire[79:60]),
+ .dataout(wire_receive_pcs3_dataout),
+ .dataoutfull(),
+ .digitalreset(rx_digitalreset_out[3]),
+ .digitaltestout(),
+ .disablefifordin(rx_disablefifordin_in[0]),
+ .disablefifordout(wire_receive_pcs3_disablefifordout),
+ .disablefifowrin(rx_disablefifowrin_in[0]),
+ .disablefifowrout(wire_receive_pcs3_disablefifowrout),
+ .disperr(wire_receive_pcs3_disperr),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pcsdprioin_wire[1599:1200]),
+ .dprioout(wire_receive_pcs3_dprioout),
+ .enabledeskew(enabledeskew[0]),
+ .enabyteord(1'b0),
+ .enapatternalign(rx_enapatternalign[3]),
+ .errdetect(wire_receive_pcs3_errdetect),
+ .fifordin(rx_fifordin_in[0]),
+ .fifordout(wire_receive_pcs3_fifordout),
+ .fiforesetrd(rx_fiforesetrd[0]),
+ .hipdataout(),
+ .hipdatavalid(),
+ .hipelecidle(),
+ .hipphydonestatus(),
+ .hipstatus(),
+ .invpol(rx_invpolarity[3]),
+ .iqpphfifobyteselout(),
+ .iqpphfifoptrsresetout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrclkout(),
+ .iqpphfifowrenableout(),
+ .k1detect(),
+ .k2detect(),
+ .localrefclk(1'b0),
+ .masterclk(rx_masterclk[0]),
+ .parallelfdbk({20{1'b0}}),
+ .patterndetect(wire_receive_pcs3_patterndetect),
+ .phfifobyteselout(),
+ .phfifobyteserdisableout(wire_receive_pcs3_phfifobyteserdisableout),
+ .phfifooverflow(wire_receive_pcs3_phfifooverflow),
+ .phfifoptrsresetout(wire_receive_pcs3_phfifoptrsresetout),
+ .phfifordenable(rx_phfifordenable[3]),
+ .phfifordenableout(wire_receive_pcs3_phfifordenableout),
+ .phfiforeset(rx_phfiforeset[3]),
+ .phfiforesetout(wire_receive_pcs3_phfiforesetout),
+ .phfifounderflow(wire_receive_pcs3_phfifounderflow),
+ .phfifowrclkout(),
+ .phfifowrdisable(rx_phfifowrdisable[3]),
+ .phfifowrdisableout(wire_receive_pcs3_phfifowrdisableout),
+ .phfifowrenableout(),
+ .phfifoxnbytesel(int_rx_phfifoxnbytesel[11:9]),
+ .phfifoxnrdenable(int_rx_phfifoxnrdenable[11:9]),
+ .phfifoxnwrclk(int_rx_phfifoxnwrclk[11:9]),
+ .phfifoxnwrenable(int_rx_phfifoxnwrenable[11:9]),
+ .pipebufferstat(),
+ .pipedatavalid(),
+ .pipeelecidle(),
+ .pipephydonestatus(),
+ .pipepowerdown({2{1'b0}}),
+ .pipepowerstate({4{1'b0}}),
+ .pipestatetransdoneout(),
+ .pipestatus(),
+ .prbscidenable(rx_prbscidenable[3]),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(wire_receive_pcs3_rateswitchout),
+ .rateswitchxndone(int_hiprateswtichdone[0]),
+ .rdalign(wire_receive_pcs3_rdalign),
+ .recoveredclk(rx_pma_clockout[3]),
+ .refclk(refclk_pma[0]),
+ .revbitorderwa(1'b0),
+ .revbyteorderwa(1'b0),
+ .revparallelfdbkdata(),
+ .rlv(wire_receive_pcs3_rlv),
+ .rmfifoalmostempty(),
+ .rmfifoalmostfull(),
+ .rmfifodatadeleted(wire_receive_pcs3_rmfifodatadeleted),
+ .rmfifodatainserted(wire_receive_pcs3_rmfifodatainserted),
+ .rmfifoempty(wire_receive_pcs3_rmfifoempty),
+ .rmfifofull(wire_receive_pcs3_rmfifofull),
+ .rmfifordena(1'b0),
+ .rmfiforeset(rx_rmfiforeset[3]),
+ .rmfifowrena(1'b0),
+ .runningdisp(wire_receive_pcs3_runningdisp),
+ .rxdetectvalid(1'b0),
+ .rxfound({2{1'b0}}),
+ .signaldetect(),
+ .syncstatus(wire_receive_pcs3_syncstatus),
+ .syncstatusdeskew(wire_receive_pcs3_syncstatusdeskew),
+ .xauidelcondmetout(),
+ .xauififoovrout(),
+ .xauiinsertincompleteout(),
+ .xauilatencycompout(),
+ .xgmctrldet(wire_receive_pcs3_xgmctrldet),
+ .xgmctrlin(rx_xgmctrlin[3]),
+ .xgmdatain(cent_unit_rx_xgmdataout[31:24]),
+ .xgmdataout(wire_receive_pcs3_xgmdataout),
+ .xgmdatavalid(wire_receive_pcs3_xgmdatavalid),
+ .xgmrunningdisp(wire_receive_pcs3_xgmrunningdisp)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .autospdxnconfigsel({3{1'b0}}),
+ .autospdxnspdchg({3{1'b0}}),
+ .bitslip(1'b0),
+ .elecidleinfersel({3{1'b0}}),
+ .grayelecidleinferselfromtx({3{1'b0}}),
+ .hip8b10binvpolarity(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hippowerdown({2{1'b0}}),
+ .hiprateswitch(1'b0),
+ .iqpautospdxnspgchg({2{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnptrsreset({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrclk({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrclk(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifox8bytesel(1'b0),
+ .phfifox8rdenable(1'b0),
+ .phfifox8wrclk(1'b0),
+ .phfifox8wrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .pipe8b10binvpolarity(1'b0),
+ .pipeenrevparallellpbkfromtx(1'b0),
+ .pmatestbusin({8{1'b0}}),
+ .powerdn({2{1'b0}}),
+ .ppmdetectdividedclk(1'b0),
+ .ppmdetectrefclk(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rxelecidlerateswitch(1'b0),
+ .signaldetected(1'b0),
+ .wareset(1'b0),
+ .xauidelcondmet(1'b0),
+ .xauififoovr(1'b0),
+ .xauiinsertincomplete(1'b0),
+ .xauilatencycomp(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pcs3.align_pattern = "0101111100",
+ receive_pcs3.align_pattern_length = 10,
+ receive_pcs3.align_to_deskew_pattern_pos_disp_only = "false",
+ receive_pcs3.allow_align_polarity_inversion = "true",
+ receive_pcs3.allow_pipe_polarity_inversion = "false",
+ receive_pcs3.auto_spd_deassert_ph_fifo_rst_count = 8,
+ receive_pcs3.auto_spd_phystatus_notify_count = 0,
+ receive_pcs3.auto_spd_self_switch_enable = "false",
+ receive_pcs3.bit_slip_enable = "false",
+ receive_pcs3.byte_order_double_data_mode_mask_enable = "false",
+ receive_pcs3.byte_order_mode = "none",
+ receive_pcs3.byte_order_pad_pattern = "0",
+ receive_pcs3.byte_order_pattern = "0",
+ receive_pcs3.byte_order_pld_ctrl_enable = "false",
+ receive_pcs3.cdrctrl_bypass_ppm_detector_cycle = 1000,
+ receive_pcs3.cdrctrl_enable = "false",
+ receive_pcs3.cdrctrl_mask_cycle = 800,
+ receive_pcs3.cdrctrl_min_lock_to_ref_cycle = 63,
+ receive_pcs3.cdrctrl_rxvalid_mask = "false",
+ receive_pcs3.channel_bonding = "x4",
+ receive_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pcs3.channel_width = 16,
+ receive_pcs3.clk1_mux_select = "master clock",
+ receive_pcs3.clk2_mux_select = "digital reference clock",
+ receive_pcs3.core_clock_0ppm = "true",
+ receive_pcs3.datapath_low_latency_mode = "false",
+ receive_pcs3.datapath_protocol = "xaui",
+ receive_pcs3.dec_8b_10b_compatibility_mode = "true",
+ receive_pcs3.dec_8b_10b_mode = "normal",
+ receive_pcs3.dec_8b_10b_polarity_inv_enable = "false",
+ receive_pcs3.deskew_pattern = "0011000011",
+ receive_pcs3.disable_auto_idle_insertion = "true",
+ receive_pcs3.disable_running_disp_in_word_align = "false",
+ receive_pcs3.disallow_kchar_after_pattern_ordered_set = "false",
+ receive_pcs3.dprio_config_mode = 6'h01,
+ receive_pcs3.elec_idle_infer_enable = "false",
+ receive_pcs3.elec_idle_num_com_detect = 3,
+ receive_pcs3.enable_bit_reversal = "false",
+ receive_pcs3.enable_deep_align = "false",
+ receive_pcs3.enable_deep_align_byte_swap = "false",
+ receive_pcs3.enable_self_test_mode = "false",
+ receive_pcs3.enable_true_complement_match_in_word_align = "false",
+ receive_pcs3.force_signal_detect_dig = "true",
+ receive_pcs3.hip_enable = "false",
+ receive_pcs3.infiniband_invalid_code = 0,
+ receive_pcs3.insert_pad_on_underflow = "false",
+ receive_pcs3.logical_channel_address = (starting_channel_number + 3),
+ receive_pcs3.num_align_code_groups_in_ordered_set = 0,
+ receive_pcs3.num_align_cons_good_data = 4,
+ receive_pcs3.num_align_cons_pat = 4,
+ receive_pcs3.num_align_loss_sync_error = 4,
+ receive_pcs3.ph_fifo_low_latency_enable = "true",
+ receive_pcs3.ph_fifo_reg_mode = "false",
+ receive_pcs3.ph_fifo_xn_mapping0 = "none",
+ receive_pcs3.ph_fifo_xn_mapping1 = "none",
+ receive_pcs3.ph_fifo_xn_mapping2 = "central",
+ receive_pcs3.ph_fifo_xn_select = 2,
+ receive_pcs3.pipe_auto_speed_nego_enable = "false",
+ receive_pcs3.pipe_freq_scale_mode = "Frequency",
+ receive_pcs3.pma_done_count = 249950,
+ receive_pcs3.protocol_hint = "xaui",
+ receive_pcs3.rate_match_almost_empty_threshold = 11,
+ receive_pcs3.rate_match_almost_full_threshold = 13,
+ receive_pcs3.rate_match_back_to_back = "true",
+ receive_pcs3.rate_match_delete_threshold = 13,
+ receive_pcs3.rate_match_empty_threshold = 5,
+ receive_pcs3.rate_match_fifo_mode = "true",
+ receive_pcs3.rate_match_full_threshold = 20,
+ receive_pcs3.rate_match_insert_threshold = 11,
+ receive_pcs3.rate_match_ordered_set_based = "false",
+ receive_pcs3.rate_match_pattern1 = "1101000011",
+ receive_pcs3.rate_match_pattern2 = "0010111100",
+ receive_pcs3.rate_match_pattern_size = 10,
+ receive_pcs3.rate_match_reset_enable = "false",
+ receive_pcs3.rate_match_skip_set_based = "false",
+ receive_pcs3.rate_match_start_threshold = 7,
+ receive_pcs3.rd_clk_mux_select = "core clock",
+ receive_pcs3.recovered_clk_mux_select = "recovered clock",
+ receive_pcs3.run_length = 40,
+ receive_pcs3.run_length_enable = "true",
+ receive_pcs3.rx_detect_bypass = "false",
+ receive_pcs3.rx_phfifo_wait_cnt = 15,
+ receive_pcs3.rxstatus_error_report_mode = 0,
+ receive_pcs3.self_test_mode = "incremental",
+ receive_pcs3.use_alignment_state_machine = "true",
+ receive_pcs3.use_deserializer_double_data_mode = "false",
+ receive_pcs3.use_deskew_fifo = "true",
+ receive_pcs3.use_double_data_mode = "true",
+ receive_pcs3.use_parallel_loopback = "false",
+ receive_pcs3.use_rising_edge_triggered_pattern_align = "false",
+ receive_pcs3.lpm_type = "stratixiv_hssi_rx_pcs";
+ stratixiv_hssi_rx_pma receive_pma0
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma0_analogtestbus),
+ .clockout(wire_receive_pma0_clockout),
+ .datain(rx_datain[0]),
+ .dataout(wire_receive_pma0_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[3:0]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[299:0]),
+ .dprioout(wire_receive_pma0_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[0]),
+ .locktoref(rx_locktorefclk_wire[0]),
+ .locktorefout(wire_receive_pma0_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[0]),
+ .powerdn(cent_unit_rxibpowerdn[0]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
+ .recoverdatain(pll_ch_dataout_wire[1:0]),
+ .recoverdataout(wire_receive_pma0_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[0]),
+ .seriallpbken(rx_seriallpbken[0]),
+ .seriallpbkin(tx_serialloopbackout[0]),
+ .signaldetect(wire_receive_pma0_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma0.adaptive_equalization_mode = "none",
+ receive_pma0.allow_serial_loopback = "true",
+ receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ receive_pma0.channel_type = "auto",
+ receive_pma0.common_mode = rx_common_mode,
+ receive_pma0.deserialization_factor = 10,
+ receive_pma0.dprio_config_mode = 6'h01,
+ receive_pma0.enable_ltd = "true",
+ receive_pma0.enable_ltr = "true",
+ receive_pma0.eq_dc_gain = equalizer_dcgain_setting,
+ receive_pma0.eqa_ctrl = equalizer_ctrl_a_setting,
+ receive_pma0.eqb_ctrl = equalizer_ctrl_b_setting,
+ receive_pma0.eqc_ctrl = equalizer_ctrl_c_setting,
+ receive_pma0.eqd_ctrl = equalizer_ctrl_d_setting,
+ receive_pma0.eqv_ctrl = equalizer_ctrl_v_setting,
+ receive_pma0.eyemon_bandwidth = 0,
+ receive_pma0.force_signal_detect = "true",
+ receive_pma0.logical_channel_address = (starting_channel_number + 0),
+ receive_pma0.low_speed_test_select = 0,
+ receive_pma0.offset_cancellation = 1,
+ receive_pma0.ppmselect = 32,
+ receive_pma0.protocol_hint = "xaui",
+ receive_pma0.send_direct_reverse_serial_loopback = "None",
+ receive_pma0.signal_detect_hysteresis = 2,
+ receive_pma0.signal_detect_hysteresis_valid_threshold = 1,
+ receive_pma0.signal_detect_loss_threshold = 1,
+ receive_pma0.termination = receiver_termination,
+ receive_pma0.use_deser_double_data_width = "false",
+ receive_pma0.use_external_termination = "false",
+ receive_pma0.use_pma_direct = "false",
+ receive_pma0.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma1
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma1_analogtestbus),
+ .clockout(wire_receive_pma1_clockout),
+ .datain(rx_datain[1]),
+ .dataout(wire_receive_pma1_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[7:4]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[599:300]),
+ .dprioout(wire_receive_pma1_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[1]),
+ .locktoref(rx_locktorefclk_wire[1]),
+ .locktorefout(wire_receive_pma1_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[1]),
+ .powerdn(cent_unit_rxibpowerdn[1]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[1]),
+ .recoverdatain(pll_ch_dataout_wire[3:2]),
+ .recoverdataout(wire_receive_pma1_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[1]),
+ .seriallpbken(rx_seriallpbken[1]),
+ .seriallpbkin(tx_serialloopbackout[1]),
+ .signaldetect(wire_receive_pma1_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma1.adaptive_equalization_mode = "none",
+ receive_pma1.allow_serial_loopback = "true",
+ receive_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ receive_pma1.channel_type = "auto",
+ receive_pma1.common_mode = rx_common_mode,
+ receive_pma1.deserialization_factor = 10,
+ receive_pma1.dprio_config_mode = 6'h01,
+ receive_pma1.enable_ltd = "true",
+ receive_pma1.enable_ltr = "true",
+ receive_pma1.eq_dc_gain = equalizer_dcgain_setting,
+ receive_pma1.eqa_ctrl = equalizer_ctrl_a_setting,
+ receive_pma1.eqb_ctrl = equalizer_ctrl_b_setting,
+ receive_pma1.eqc_ctrl = equalizer_ctrl_c_setting,
+ receive_pma1.eqd_ctrl = equalizer_ctrl_d_setting,
+ receive_pma1.eqv_ctrl = equalizer_ctrl_v_setting,
+ receive_pma1.eyemon_bandwidth = 0,
+ receive_pma1.force_signal_detect = "true",
+ receive_pma1.logical_channel_address = (starting_channel_number + 1),
+ receive_pma1.low_speed_test_select = 0,
+ receive_pma1.offset_cancellation = 1,
+ receive_pma1.ppmselect = 32,
+ receive_pma1.protocol_hint = "xaui",
+ receive_pma1.send_direct_reverse_serial_loopback = "None",
+ receive_pma1.signal_detect_hysteresis = 2,
+ receive_pma1.signal_detect_hysteresis_valid_threshold = 1,
+ receive_pma1.signal_detect_loss_threshold = 1,
+ receive_pma1.termination = receiver_termination,
+ receive_pma1.use_deser_double_data_width = "false",
+ receive_pma1.use_external_termination = "false",
+ receive_pma1.use_pma_direct = "false",
+ receive_pma1.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma2
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma2_analogtestbus),
+ .clockout(wire_receive_pma2_clockout),
+ .datain(rx_datain[2]),
+ .dataout(wire_receive_pma2_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[11:8]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[899:600]),
+ .dprioout(wire_receive_pma2_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[2]),
+ .locktoref(rx_locktorefclk_wire[2]),
+ .locktorefout(wire_receive_pma2_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[2]),
+ .powerdn(cent_unit_rxibpowerdn[2]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[2]),
+ .recoverdatain(pll_ch_dataout_wire[5:4]),
+ .recoverdataout(wire_receive_pma2_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[2]),
+ .seriallpbken(rx_seriallpbken[2]),
+ .seriallpbkin(tx_serialloopbackout[2]),
+ .signaldetect(wire_receive_pma2_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma2.adaptive_equalization_mode = "none",
+ receive_pma2.allow_serial_loopback = "true",
+ receive_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ receive_pma2.channel_type = "auto",
+ receive_pma2.common_mode = rx_common_mode,
+ receive_pma2.deserialization_factor = 10,
+ receive_pma2.dprio_config_mode = 6'h01,
+ receive_pma2.enable_ltd = "true",
+ receive_pma2.enable_ltr = "true",
+ receive_pma2.eq_dc_gain = equalizer_dcgain_setting,
+ receive_pma2.eqa_ctrl = equalizer_ctrl_a_setting,
+ receive_pma2.eqb_ctrl = equalizer_ctrl_b_setting,
+ receive_pma2.eqc_ctrl = equalizer_ctrl_c_setting,
+ receive_pma2.eqd_ctrl = equalizer_ctrl_d_setting,
+ receive_pma2.eqv_ctrl = equalizer_ctrl_v_setting,
+ receive_pma2.eyemon_bandwidth = 0,
+ receive_pma2.force_signal_detect = "true",
+ receive_pma2.logical_channel_address = (starting_channel_number + 2),
+ receive_pma2.low_speed_test_select = 0,
+ receive_pma2.offset_cancellation = 1,
+ receive_pma2.ppmselect = 32,
+ receive_pma2.protocol_hint = "xaui",
+ receive_pma2.send_direct_reverse_serial_loopback = "None",
+ receive_pma2.signal_detect_hysteresis = 2,
+ receive_pma2.signal_detect_hysteresis_valid_threshold = 1,
+ receive_pma2.signal_detect_loss_threshold = 1,
+ receive_pma2.termination = receiver_termination,
+ receive_pma2.use_deser_double_data_width = "false",
+ receive_pma2.use_external_termination = "false",
+ receive_pma2.use_pma_direct = "false",
+ receive_pma2.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_rx_pma receive_pma3
+ (
+ .adaptdone(),
+ .analogtestbus(wire_receive_pma3_analogtestbus),
+ .clockout(wire_receive_pma3_clockout),
+ .datain(rx_datain[3]),
+ .dataout(wire_receive_pma3_dataout),
+ .dataoutfull(),
+ .deserclock(rx_deserclock_in[15:12]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(rx_pmadprioin_wire[1199:900]),
+ .dprioout(wire_receive_pma3_dprioout),
+ .freqlock(1'b0),
+ .ignorephslck(1'b0),
+ .locktodata(rx_locktodata_wire[3]),
+ .locktoref(rx_locktorefclk_wire[3]),
+ .locktorefout(wire_receive_pma3_locktorefout),
+ .offsetcancellationen(1'b0),
+ .plllocked(rx_plllocked_wire[3]),
+ .powerdn(cent_unit_rxibpowerdn[3]),
+ .ppmdetectclkrel(),
+ .ppmdetectrefclk(rx_pll_pfdrefclkout_wire[3]),
+ .recoverdatain(pll_ch_dataout_wire[7:6]),
+ .recoverdataout(wire_receive_pma3_recoverdataout),
+ .reverselpbkout(),
+ .revserialfdbkout(),
+ .rxpmareset(rx_analogreset_out[3]),
+ .seriallpbken(rx_seriallpbken[3]),
+ .seriallpbkin(tx_serialloopbackout[3]),
+ .signaldetect(wire_receive_pma3_signaldetect),
+ .testbussel(4'b0110)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .adaptcapture(1'b0),
+ .adcepowerdn(1'b0),
+ .adcereset(1'b0),
+ .adcestandby(1'b0),
+ .extra10gin({38{1'b0}}),
+ .ppmdetectdividedclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ receive_pma3.adaptive_equalization_mode = "none",
+ receive_pma3.allow_serial_loopback = "true",
+ receive_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ receive_pma3.channel_type = "auto",
+ receive_pma3.common_mode = rx_common_mode,
+ receive_pma3.deserialization_factor = 10,
+ receive_pma3.dprio_config_mode = 6'h01,
+ receive_pma3.enable_ltd = "true",
+ receive_pma3.enable_ltr = "true",
+ receive_pma3.eq_dc_gain = equalizer_dcgain_setting,
+ receive_pma3.eqa_ctrl = equalizer_ctrl_a_setting,
+ receive_pma3.eqb_ctrl = equalizer_ctrl_b_setting,
+ receive_pma3.eqc_ctrl = equalizer_ctrl_c_setting,
+ receive_pma3.eqd_ctrl = equalizer_ctrl_d_setting,
+ receive_pma3.eqv_ctrl = equalizer_ctrl_v_setting,
+ receive_pma3.eyemon_bandwidth = 0,
+ receive_pma3.force_signal_detect = "true",
+ receive_pma3.logical_channel_address = (starting_channel_number + 3),
+ receive_pma3.low_speed_test_select = 0,
+ receive_pma3.offset_cancellation = 1,
+ receive_pma3.ppmselect = 32,
+ receive_pma3.protocol_hint = "xaui",
+ receive_pma3.send_direct_reverse_serial_loopback = "None",
+ receive_pma3.signal_detect_hysteresis = 2,
+ receive_pma3.signal_detect_hysteresis_valid_threshold = 1,
+ receive_pma3.signal_detect_loss_threshold = 1,
+ receive_pma3.termination = receiver_termination,
+ receive_pma3.use_deser_double_data_width = "false",
+ receive_pma3.use_external_termination = "false",
+ receive_pma3.use_pma_direct = "false",
+ receive_pma3.lpm_type = "stratixiv_hssi_rx_pma";
+ stratixiv_hssi_tx_pcs transmit_pcs0
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[0]),
+ .coreclkout(wire_transmit_pcs0_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[1:0]}),
+ .datain({{24{1'b0}}, tx_datain_wire[15:0]}),
+ .datainfull({44{1'b0}}),
+ .dataout(wire_transmit_pcs0_dataout),
+ .detectrxloop(1'b0),
+ .digitalreset(tx_digitalreset_out[0]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[149:0]),
+ .dprioout(wire_transmit_pcs0_dprioout),
+ .enrevparallellpbk(1'b0),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[1:0]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidleout(wire_transmit_pcs0_forceelecidleout),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[0]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[0]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[0]),
+ .phfifooverflow(wire_transmit_pcs0_phfifooverflow),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[0]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[0]),
+ .phfiforesetout(wire_transmit_pcs0_phfiforesetout),
+ .phfifounderflow(wire_transmit_pcs0_phfifounderflow),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[2:0]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[2:0]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[2:0]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[2:0]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(),
+ .pipepowerstateout(),
+ .pipestatetransdone(1'b0),
+ .powerdn({2{1'b0}}),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(wire_transmit_pcs0_rdenablesync),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk({20{1'b0}}),
+ .txdetectrx(wire_transmit_pcs0_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[0]),
+ .xgmctrlenable(wire_transmit_pcs0_xgmctrlenable),
+ .xgmdatain(cent_unit_tx_xgmdataout[7:0]),
+ .xgmdataout(wire_transmit_pcs0_xgmdataout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .dispval({4{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .forceelecidle(1'b0),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .pipetxdeemph(1'b0),
+ .pipetxmargin({3{1'b0}}),
+ .pipetxswing(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs0.allow_polarity_inversion = "true",
+ transmit_pcs0.auto_spd_self_switch_enable = "false",
+ transmit_pcs0.bitslip_enable = "false",
+ transmit_pcs0.channel_bonding = "x4",
+ transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pcs0.channel_width = 16,
+ transmit_pcs0.core_clock_0ppm = "true",
+ transmit_pcs0.datapath_low_latency_mode = "false",
+ transmit_pcs0.datapath_protocol = "xaui",
+ transmit_pcs0.disable_ph_low_latency_mode = "false",
+ transmit_pcs0.disparity_mode = "none",
+ transmit_pcs0.dprio_config_mode = 6'h01,
+ transmit_pcs0.elec_idle_delay = 6,
+ transmit_pcs0.enable_bit_reversal = "false",
+ transmit_pcs0.enable_idle_selection = "false",
+ transmit_pcs0.enable_reverse_parallel_loopback = "false",
+ transmit_pcs0.enable_self_test_mode = "false",
+ transmit_pcs0.enable_symbol_swap = "false",
+ transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs0.enc_8b_10b_mode = "normal",
+ transmit_pcs0.force_echar = "false",
+ transmit_pcs0.force_kchar = "false",
+ transmit_pcs0.hip_enable = "false",
+ transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pcs0.ph_fifo_reg_mode = "false",
+ transmit_pcs0.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs0.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs0.ph_fifo_xn_select = 2,
+ transmit_pcs0.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs0.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs0.prbs_cid_pattern = "false",
+ transmit_pcs0.protocol_hint = "xaui",
+ transmit_pcs0.refclk_select = "cmu_clock_divider",
+ transmit_pcs0.self_test_mode = "incremental",
+ transmit_pcs0.use_double_data_mode = "true",
+ transmit_pcs0.use_serializer_double_data_mode = "false",
+ transmit_pcs0.wr_clk_mux_select = "core_clk",
+ transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs1
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[1]),
+ .coreclkout(wire_transmit_pcs1_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[3:2]}),
+ .datain({{24{1'b0}}, tx_datain_wire[31:16]}),
+ .datainfull({44{1'b0}}),
+ .dataout(wire_transmit_pcs1_dataout),
+ .detectrxloop(1'b0),
+ .digitalreset(tx_digitalreset_out[1]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[299:150]),
+ .dprioout(wire_transmit_pcs1_dprioout),
+ .enrevparallellpbk(1'b0),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[3:2]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidleout(wire_transmit_pcs1_forceelecidleout),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[1]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[1]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[1]),
+ .phfifooverflow(wire_transmit_pcs1_phfifooverflow),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[1]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[1]),
+ .phfiforesetout(wire_transmit_pcs1_phfiforesetout),
+ .phfifounderflow(wire_transmit_pcs1_phfifounderflow),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[5:3]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[5:3]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[5:3]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[5:3]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(),
+ .pipepowerstateout(),
+ .pipestatetransdone(1'b0),
+ .powerdn({2{1'b0}}),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(wire_transmit_pcs1_rdenablesync),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk({20{1'b0}}),
+ .txdetectrx(wire_transmit_pcs1_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[1]),
+ .xgmctrlenable(wire_transmit_pcs1_xgmctrlenable),
+ .xgmdatain(cent_unit_tx_xgmdataout[15:8]),
+ .xgmdataout(wire_transmit_pcs1_xgmdataout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .dispval({4{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .forceelecidle(1'b0),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .pipetxdeemph(1'b0),
+ .pipetxmargin({3{1'b0}}),
+ .pipetxswing(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs1.allow_polarity_inversion = "true",
+ transmit_pcs1.auto_spd_self_switch_enable = "false",
+ transmit_pcs1.bitslip_enable = "false",
+ transmit_pcs1.channel_bonding = "x4",
+ transmit_pcs1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pcs1.channel_width = 16,
+ transmit_pcs1.core_clock_0ppm = "true",
+ transmit_pcs1.datapath_low_latency_mode = "false",
+ transmit_pcs1.datapath_protocol = "xaui",
+ transmit_pcs1.disable_ph_low_latency_mode = "false",
+ transmit_pcs1.disparity_mode = "none",
+ transmit_pcs1.dprio_config_mode = 6'h01,
+ transmit_pcs1.elec_idle_delay = 6,
+ transmit_pcs1.enable_bit_reversal = "false",
+ transmit_pcs1.enable_idle_selection = "false",
+ transmit_pcs1.enable_reverse_parallel_loopback = "false",
+ transmit_pcs1.enable_self_test_mode = "false",
+ transmit_pcs1.enable_symbol_swap = "false",
+ transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs1.enc_8b_10b_mode = "normal",
+ transmit_pcs1.force_echar = "false",
+ transmit_pcs1.force_kchar = "false",
+ transmit_pcs1.hip_enable = "false",
+ transmit_pcs1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pcs1.ph_fifo_reg_mode = "false",
+ transmit_pcs1.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs1.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs1.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs1.ph_fifo_xn_select = 2,
+ transmit_pcs1.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs1.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs1.prbs_cid_pattern = "false",
+ transmit_pcs1.protocol_hint = "xaui",
+ transmit_pcs1.refclk_select = "cmu_clock_divider",
+ transmit_pcs1.self_test_mode = "incremental",
+ transmit_pcs1.use_double_data_mode = "true",
+ transmit_pcs1.use_serializer_double_data_mode = "false",
+ transmit_pcs1.wr_clk_mux_select = "core_clk",
+ transmit_pcs1.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs2
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[2]),
+ .coreclkout(wire_transmit_pcs2_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[5:4]}),
+ .datain({{24{1'b0}}, tx_datain_wire[47:32]}),
+ .datainfull({44{1'b0}}),
+ .dataout(wire_transmit_pcs2_dataout),
+ .detectrxloop(1'b0),
+ .digitalreset(tx_digitalreset_out[2]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[449:300]),
+ .dprioout(wire_transmit_pcs2_dprioout),
+ .enrevparallellpbk(1'b0),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[5:4]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidleout(wire_transmit_pcs2_forceelecidleout),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[2]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[2]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[2]),
+ .phfifooverflow(wire_transmit_pcs2_phfifooverflow),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[2]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs2_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[2]),
+ .phfiforesetout(wire_transmit_pcs2_phfiforesetout),
+ .phfifounderflow(wire_transmit_pcs2_phfifounderflow),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs2_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[8:6]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[8:6]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[8:6]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[8:6]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(),
+ .pipepowerstateout(),
+ .pipestatetransdone(1'b0),
+ .powerdn({2{1'b0}}),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(wire_transmit_pcs2_rdenablesync),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk({20{1'b0}}),
+ .txdetectrx(wire_transmit_pcs2_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[2]),
+ .xgmctrlenable(wire_transmit_pcs2_xgmctrlenable),
+ .xgmdatain(cent_unit_tx_xgmdataout[23:16]),
+ .xgmdataout(wire_transmit_pcs2_xgmdataout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .dispval({4{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .forceelecidle(1'b0),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .pipetxdeemph(1'b0),
+ .pipetxmargin({3{1'b0}}),
+ .pipetxswing(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs2.allow_polarity_inversion = "true",
+ transmit_pcs2.auto_spd_self_switch_enable = "false",
+ transmit_pcs2.bitslip_enable = "false",
+ transmit_pcs2.channel_bonding = "x4",
+ transmit_pcs2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pcs2.channel_width = 16,
+ transmit_pcs2.core_clock_0ppm = "true",
+ transmit_pcs2.datapath_low_latency_mode = "false",
+ transmit_pcs2.datapath_protocol = "xaui",
+ transmit_pcs2.disable_ph_low_latency_mode = "false",
+ transmit_pcs2.disparity_mode = "none",
+ transmit_pcs2.dprio_config_mode = 6'h01,
+ transmit_pcs2.elec_idle_delay = 6,
+ transmit_pcs2.enable_bit_reversal = "false",
+ transmit_pcs2.enable_idle_selection = "false",
+ transmit_pcs2.enable_reverse_parallel_loopback = "false",
+ transmit_pcs2.enable_self_test_mode = "false",
+ transmit_pcs2.enable_symbol_swap = "false",
+ transmit_pcs2.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs2.enc_8b_10b_mode = "normal",
+ transmit_pcs2.force_echar = "false",
+ transmit_pcs2.force_kchar = "false",
+ transmit_pcs2.hip_enable = "false",
+ transmit_pcs2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pcs2.ph_fifo_reg_mode = "false",
+ transmit_pcs2.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs2.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs2.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs2.ph_fifo_xn_select = 2,
+ transmit_pcs2.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs2.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs2.prbs_cid_pattern = "false",
+ transmit_pcs2.protocol_hint = "xaui",
+ transmit_pcs2.refclk_select = "cmu_clock_divider",
+ transmit_pcs2.self_test_mode = "incremental",
+ transmit_pcs2.use_double_data_mode = "true",
+ transmit_pcs2.use_serializer_double_data_mode = "false",
+ transmit_pcs2.wr_clk_mux_select = "core_clk",
+ transmit_pcs2.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pcs transmit_pcs3
+ (
+ .clkout(),
+ .coreclk(tx_coreclk_in[3]),
+ .coreclkout(wire_transmit_pcs3_coreclkout),
+ .ctrlenable({{2{1'b0}}, tx_ctrlenable[7:6]}),
+ .datain({{24{1'b0}}, tx_datain_wire[63:48]}),
+ .datainfull({44{1'b0}}),
+ .dataout(wire_transmit_pcs3_dataout),
+ .detectrxloop(1'b0),
+ .digitalreset(tx_digitalreset_out[3]),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_dprioin_wire[599:450]),
+ .dprioout(wire_transmit_pcs3_dprioout),
+ .enrevparallellpbk(1'b0),
+ .forcedisp({{2{1'b0}}, tx_forcedisp_wire[7:6]}),
+ .forcedispcompliance(1'b0),
+ .forceelecidleout(wire_transmit_pcs3_forceelecidleout),
+ .grayelecidleinferselout(),
+ .hiptxclkout(),
+ .invpol(tx_invpolarity[3]),
+ .iqpphfifobyteselout(),
+ .iqpphfifordclkout(),
+ .iqpphfifordenableout(),
+ .iqpphfifowrenableout(),
+ .localrefclk(tx_localrefclk[3]),
+ .parallelfdbkout(),
+ .phfifobyteselout(),
+ .phfifobyteserdisable(int_rx_phfifobyteserdisable[3]),
+ .phfifooverflow(wire_transmit_pcs3_phfifooverflow),
+ .phfifoptrsreset(int_rx_phfifoptrsresetout[3]),
+ .phfifordclkout(),
+ .phfiforddisable(1'b0),
+ .phfiforddisableout(wire_transmit_pcs3_phfiforddisableout),
+ .phfifordenableout(),
+ .phfiforeset(tx_phfiforeset[3]),
+ .phfiforesetout(wire_transmit_pcs3_phfiforesetout),
+ .phfifounderflow(wire_transmit_pcs3_phfifounderflow),
+ .phfifowrenable(1'b1),
+ .phfifowrenableout(wire_transmit_pcs3_phfifowrenableout),
+ .phfifoxnbytesel(int_tx_phfifoxnbytesel[11:9]),
+ .phfifoxnrdclk(int_tx_phfifoxnrdclk[11:9]),
+ .phfifoxnrdenable(int_tx_phfifoxnrdenable[11:9]),
+ .phfifoxnwrenable(int_tx_phfifoxnwrenable[11:9]),
+ .pipeenrevparallellpbkout(),
+ .pipepowerdownout(),
+ .pipepowerstateout(),
+ .pipestatetransdone(1'b0),
+ .powerdn({2{1'b0}}),
+ .quadreset(cent_unit_quadresetout[0]),
+ .rateswitchout(),
+ .rdenablesync(wire_transmit_pcs3_rdenablesync),
+ .refclk(refclk_pma[0]),
+ .revparallelfdbk({20{1'b0}}),
+ .txdetectrx(wire_transmit_pcs3_txdetectrx),
+ .xgmctrl(cent_unit_txctrlout[3]),
+ .xgmctrlenable(wire_transmit_pcs3_xgmctrlenable),
+ .xgmdatain(cent_unit_tx_xgmdataout[31:24]),
+ .xgmdataout(wire_transmit_pcs3_xgmdataout)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .bitslipboundaryselect({5{1'b0}}),
+ .dispval({4{1'b0}}),
+ .elecidleinfersel({3{1'b0}}),
+ .forceelecidle(1'b0),
+ .freezptr(1'b0),
+ .hipdatain({10{1'b0}}),
+ .hipdetectrxloop(1'b0),
+ .hipelecidleinfersel({3{1'b0}}),
+ .hipforceelecidle(1'b0),
+ .hippowerdn({2{1'b0}}),
+ .hiptxdeemph(1'b0),
+ .hiptxmargin({3{1'b0}}),
+ .iqpphfifoxnbytesel({2{1'b0}}),
+ .iqpphfifoxnrdclk({2{1'b0}}),
+ .iqpphfifoxnrdenable({2{1'b0}}),
+ .iqpphfifoxnwrenable({2{1'b0}}),
+ .phfifox4bytesel(1'b0),
+ .phfifox4rdclk(1'b0),
+ .phfifox4rdenable(1'b0),
+ .phfifox4wrenable(1'b0),
+ .phfifoxnbottombytesel(1'b0),
+ .phfifoxnbottomrdclk(1'b0),
+ .phfifoxnbottomrdenable(1'b0),
+ .phfifoxnbottomwrenable(1'b0),
+ .phfifoxnptrsreset({3{1'b0}}),
+ .phfifoxntopbytesel(1'b0),
+ .phfifoxntoprdclk(1'b0),
+ .phfifoxntoprdenable(1'b0),
+ .phfifoxntopwrenable(1'b0),
+ .pipetxdeemph(1'b0),
+ .pipetxmargin({3{1'b0}}),
+ .pipetxswing(1'b0),
+ .prbscidenable(1'b0),
+ .rateswitch(1'b0),
+ .rateswitchisdone(1'b0),
+ .rateswitchxndone(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pcs3.allow_polarity_inversion = "true",
+ transmit_pcs3.auto_spd_self_switch_enable = "false",
+ transmit_pcs3.bitslip_enable = "false",
+ transmit_pcs3.channel_bonding = "x4",
+ transmit_pcs3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pcs3.channel_width = 16,
+ transmit_pcs3.core_clock_0ppm = "true",
+ transmit_pcs3.datapath_low_latency_mode = "false",
+ transmit_pcs3.datapath_protocol = "xaui",
+ transmit_pcs3.disable_ph_low_latency_mode = "false",
+ transmit_pcs3.disparity_mode = "none",
+ transmit_pcs3.dprio_config_mode = 6'h01,
+ transmit_pcs3.elec_idle_delay = 6,
+ transmit_pcs3.enable_bit_reversal = "false",
+ transmit_pcs3.enable_idle_selection = "false",
+ transmit_pcs3.enable_reverse_parallel_loopback = "false",
+ transmit_pcs3.enable_self_test_mode = "false",
+ transmit_pcs3.enable_symbol_swap = "false",
+ transmit_pcs3.enc_8b_10b_compatibility_mode = "true",
+ transmit_pcs3.enc_8b_10b_mode = "normal",
+ transmit_pcs3.force_echar = "false",
+ transmit_pcs3.force_kchar = "false",
+ transmit_pcs3.hip_enable = "false",
+ transmit_pcs3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pcs3.ph_fifo_reg_mode = "false",
+ transmit_pcs3.ph_fifo_xn_mapping0 = "none",
+ transmit_pcs3.ph_fifo_xn_mapping1 = "none",
+ transmit_pcs3.ph_fifo_xn_mapping2 = "central",
+ transmit_pcs3.ph_fifo_xn_select = 2,
+ transmit_pcs3.pipe_auto_speed_nego_enable = "false",
+ transmit_pcs3.pipe_freq_scale_mode = "Frequency",
+ transmit_pcs3.prbs_cid_pattern = "false",
+ transmit_pcs3.protocol_hint = "xaui",
+ transmit_pcs3.refclk_select = "cmu_clock_divider",
+ transmit_pcs3.self_test_mode = "incremental",
+ transmit_pcs3.use_double_data_mode = "true",
+ transmit_pcs3.use_serializer_double_data_mode = "false",
+ transmit_pcs3.wr_clk_mux_select = "core_clk",
+ transmit_pcs3.lpm_type = "stratixiv_hssi_tx_pcs";
+ stratixiv_hssi_tx_pma transmit_pma0
+ (
+ .clockout(wire_transmit_pma0_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[19:0]}),
+ .dataout(wire_transmit_pma0_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[299:0]),
+ .dprioout(wire_transmit_pma0_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(1'b0),
+ .powerdn(cent_unit_txobpowerdn[0]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[0]),
+ .rxdetectvalidout(),
+ .rxfoundout(),
+ .seriallpbkout(wire_transmit_pma0_seriallpbkout),
+ .txpmareset(tx_analogreset_out[0])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma0.analog_power = "auto",
+ transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
+ transmit_pma0.channel_type = "auto",
+ transmit_pma0.clkin_select = 1,
+ transmit_pma0.clkmux_delay = "false",
+ transmit_pma0.common_mode = "0.65V",
+ transmit_pma0.dprio_config_mode = 6'h01,
+ transmit_pma0.enable_reverse_serial_loopback = "false",
+ transmit_pma0.logical_channel_address = (starting_channel_number + 0),
+ transmit_pma0.logical_protocol_hint_0 = "xaui",
+ transmit_pma0.low_speed_test_select = 0,
+ transmit_pma0.physical_clkin1_mapping = "x4",
+ transmit_pma0.preemp_pretap = preemphasis_ctrl_pretap_setting,
+ transmit_pma0.preemp_pretap_inv = preemphasis_ctrl_pretap_inv_setting,
+ transmit_pma0.preemp_tap_1 = preemphasis_ctrl_1stposttap_setting,
+ transmit_pma0.preemp_tap_2 = preemphasis_ctrl_2ndposttap_setting,
+ transmit_pma0.preemp_tap_2_inv = preemphasis_ctrl_2ndposttap_inv_setting,
+ transmit_pma0.protocol_hint = "xaui",
+ transmit_pma0.rx_detect = 0,
+ transmit_pma0.serialization_factor = 10,
+ transmit_pma0.slew_rate = "low",
+ transmit_pma0.termination = transmitter_termination,
+ transmit_pma0.use_external_termination = "false",
+ transmit_pma0.use_pma_direct = "false",
+ transmit_pma0.use_ser_double_data_mode = "false",
+ transmit_pma0.vod_selection = vod_ctrl_setting,
+ transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma1
+ (
+ .clockout(wire_transmit_pma1_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[39:20]}),
+ .dataout(wire_transmit_pma1_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[599:300]),
+ .dprioout(wire_transmit_pma1_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(1'b0),
+ .powerdn(cent_unit_txobpowerdn[1]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[1]),
+ .rxdetectvalidout(),
+ .rxfoundout(),
+ .seriallpbkout(wire_transmit_pma1_seriallpbkout),
+ .txpmareset(tx_analogreset_out[1])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma1.analog_power = "auto",
+ transmit_pma1.channel_number = ((starting_channel_number + 1) % 4),
+ transmit_pma1.channel_type = "auto",
+ transmit_pma1.clkin_select = 1,
+ transmit_pma1.clkmux_delay = "false",
+ transmit_pma1.common_mode = "0.65V",
+ transmit_pma1.dprio_config_mode = 6'h01,
+ transmit_pma1.enable_reverse_serial_loopback = "false",
+ transmit_pma1.logical_channel_address = (starting_channel_number + 1),
+ transmit_pma1.logical_protocol_hint_0 = "xaui",
+ transmit_pma1.low_speed_test_select = 0,
+ transmit_pma1.physical_clkin1_mapping = "x4",
+ transmit_pma1.preemp_pretap = preemphasis_ctrl_pretap_setting,
+ transmit_pma1.preemp_pretap_inv = preemphasis_ctrl_pretap_inv_setting,
+ transmit_pma1.preemp_tap_1 = preemphasis_ctrl_1stposttap_setting,
+ transmit_pma1.preemp_tap_2 = preemphasis_ctrl_2ndposttap_setting,
+ transmit_pma1.preemp_tap_2_inv = preemphasis_ctrl_2ndposttap_inv_setting,
+ transmit_pma1.protocol_hint = "xaui",
+ transmit_pma1.rx_detect = 0,
+ transmit_pma1.serialization_factor = 10,
+ transmit_pma1.slew_rate = "low",
+ transmit_pma1.termination = transmitter_termination,
+ transmit_pma1.use_external_termination = "false",
+ transmit_pma1.use_pma_direct = "false",
+ transmit_pma1.use_ser_double_data_mode = "false",
+ transmit_pma1.vod_selection = vod_ctrl_setting,
+ transmit_pma1.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma2
+ (
+ .clockout(wire_transmit_pma2_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[59:40]}),
+ .dataout(wire_transmit_pma2_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[2]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[899:600]),
+ .dprioout(wire_transmit_pma2_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(1'b0),
+ .powerdn(cent_unit_txobpowerdn[2]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[2]),
+ .rxdetectvalidout(),
+ .rxfoundout(),
+ .seriallpbkout(wire_transmit_pma2_seriallpbkout),
+ .txpmareset(tx_analogreset_out[2])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma2.analog_power = "auto",
+ transmit_pma2.channel_number = ((starting_channel_number + 2) % 4),
+ transmit_pma2.channel_type = "auto",
+ transmit_pma2.clkin_select = 1,
+ transmit_pma2.clkmux_delay = "false",
+ transmit_pma2.common_mode = "0.65V",
+ transmit_pma2.dprio_config_mode = 6'h01,
+ transmit_pma2.enable_reverse_serial_loopback = "false",
+ transmit_pma2.logical_channel_address = (starting_channel_number + 2),
+ transmit_pma2.logical_protocol_hint_0 = "xaui",
+ transmit_pma2.low_speed_test_select = 0,
+ transmit_pma2.physical_clkin1_mapping = "x4",
+ transmit_pma2.preemp_pretap = preemphasis_ctrl_pretap_setting,
+ transmit_pma2.preemp_pretap_inv = preemphasis_ctrl_pretap_inv_setting,
+ transmit_pma2.preemp_tap_1 = preemphasis_ctrl_1stposttap_setting,
+ transmit_pma2.preemp_tap_2 = preemphasis_ctrl_2ndposttap_setting,
+ transmit_pma2.preemp_tap_2_inv = preemphasis_ctrl_2ndposttap_inv_setting,
+ transmit_pma2.protocol_hint = "xaui",
+ transmit_pma2.rx_detect = 0,
+ transmit_pma2.serialization_factor = 10,
+ transmit_pma2.slew_rate = "low",
+ transmit_pma2.termination = transmitter_termination,
+ transmit_pma2.use_external_termination = "false",
+ transmit_pma2.use_pma_direct = "false",
+ transmit_pma2.use_ser_double_data_mode = "false",
+ transmit_pma2.vod_selection = vod_ctrl_setting,
+ transmit_pma2.lpm_type = "stratixiv_hssi_tx_pma";
+ stratixiv_hssi_tx_pma transmit_pma3
+ (
+ .clockout(wire_transmit_pma3_clockout),
+ .datain({{44{1'b0}}, tx_dataout_pcs_to_pma[79:60]}),
+ .dataout(wire_transmit_pma3_dataout),
+ .detectrxpowerdown(cent_unit_txdetectrxpowerdn[3]),
+ .dftout(),
+ .dpriodisable(w_cent_unit_dpriodisableout1w[0]),
+ .dprioin(tx_pmadprioin_wire[1199:900]),
+ .dprioout(wire_transmit_pma3_dprioout),
+ .fastrefclk0in({2{1'b0}}),
+ .fastrefclk1in(cmu_analogfastrefclkout[1:0]),
+ .fastrefclk2in({2{1'b0}}),
+ .fastrefclk4in({2{1'b0}}),
+ .forceelecidle(1'b0),
+ .powerdn(cent_unit_txobpowerdn[3]),
+ .refclk0in({2{1'b0}}),
+ .refclk0inpulse(1'b0),
+ .refclk1in(cmu_analogrefclkout[1:0]),
+ .refclk1inpulse(cmu_analogrefclkpulse[0]),
+ .refclk2in({2{1'b0}}),
+ .refclk2inpulse(1'b0),
+ .refclk4in({2{1'b0}}),
+ .refclk4inpulse(1'b0),
+ .revserialfdbk(1'b0),
+ .rxdetecten(txdetectrxout[3]),
+ .rxdetectvalidout(),
+ .rxfoundout(),
+ .seriallpbkout(wire_transmit_pma3_seriallpbkout),
+ .txpmareset(tx_analogreset_out[3])
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .datainfull({20{1'b0}}),
+ .extra10gin({11{1'b0}}),
+ .fastrefclk3in({2{1'b0}}),
+ .pclk({5{1'b0}}),
+ .refclk3in({2{1'b0}}),
+ .refclk3inpulse(1'b0),
+ .rxdetectclk(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ transmit_pma3.analog_power = "auto",
+ transmit_pma3.channel_number = ((starting_channel_number + 3) % 4),
+ transmit_pma3.channel_type = "auto",
+ transmit_pma3.clkin_select = 1,
+ transmit_pma3.clkmux_delay = "false",
+ transmit_pma3.common_mode = "0.65V",
+ transmit_pma3.dprio_config_mode = 6'h01,
+ transmit_pma3.enable_reverse_serial_loopback = "false",
+ transmit_pma3.logical_channel_address = (starting_channel_number + 3),
+ transmit_pma3.logical_protocol_hint_0 = "xaui",
+ transmit_pma3.low_speed_test_select = 0,
+ transmit_pma3.physical_clkin1_mapping = "x4",
+ transmit_pma3.preemp_pretap = preemphasis_ctrl_pretap_setting,
+ transmit_pma3.preemp_pretap_inv = preemphasis_ctrl_pretap_inv_setting,
+ transmit_pma3.preemp_tap_1 = preemphasis_ctrl_1stposttap_setting,
+ transmit_pma3.preemp_tap_2 = preemphasis_ctrl_2ndposttap_setting,
+ transmit_pma3.preemp_tap_2_inv = preemphasis_ctrl_2ndposttap_inv_setting,
+ transmit_pma3.protocol_hint = "xaui",
+ transmit_pma3.rx_detect = 0,
+ transmit_pma3.serialization_factor = 10,
+ transmit_pma3.slew_rate = "low",
+ transmit_pma3.termination = transmitter_termination,
+ transmit_pma3.use_external_termination = "false",
+ transmit_pma3.use_pma_direct = "false",
+ transmit_pma3.use_ser_double_data_mode = "false",
+ transmit_pma3.vod_selection = vod_ctrl_setting,
+ transmit_pma3.lpm_type = "stratixiv_hssi_tx_pma";
+ assign
+ cent_unit_clkdivpowerdn = {wire_cent_unit0_clkdivpowerdn[0]},
+ cent_unit_cmudividerdprioout = {wire_cent_unit0_cmudividerdprioout},
+ cent_unit_cmuplldprioout = {wire_cent_unit0_cmuplldprioout},
+ cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]},
+ cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]},
+ cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
+ cent_unit_rdenablesync = {tx_rdenablesync[0]},
+ cent_unit_rx_ctrl = {wire_receive_pcs3_xgmctrldet, wire_receive_pcs2_xgmctrldet, wire_receive_pcs1_xgmctrldet, wire_receive_pcs0_xgmctrldet},
+ cent_unit_rx_xgmdataout = {wire_cent_unit0_rxdataout},
+ cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]},
+ cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]},
+ cent_unit_rxpcsdprioin = {rx_pcsdprioout[1599:0]},
+ cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout[1599:0]},
+ cent_unit_rxpmadprioin = {{2{{300{1'b0}}}}, rx_pmadprioout[1199:0]},
+ cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout[1799:0]},
+ cent_unit_tx_dprioin = {{600{1'b0}}, tx_txdprioout[599:0]},
+ cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout[31:0]},
+ cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
+ cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[5:0]},
+ cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout[599:0]},
+ cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
+ cent_unit_txpmadprioin = {{2{{300{1'b0}}}}, tx_pmadprioout[1199:0]},
+ cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout[1799:0]},
+ clk_div_clk0in = {pll0_out[3:0]},
+ clk_div_cmudividerdprioin = {{100{1'b0}}, wire_central_clk_div0_dprioout, {400{1'b0}}},
+ cmu_analogfastrefclkout = {wire_central_clk_div0_analogfastrefclkout},
+ cmu_analogrefclkout = {wire_central_clk_div0_analogrefclkout},
+ cmu_analogrefclkpulse = {wire_central_clk_div0_analogrefclkpulse},
+ coreclkout = {coreclkout_wire[0]},
+ coreclkout_wire = {wire_central_clk_div0_coreclkout},
+ enabledeskew = {wire_cent_unit0_enabledeskew},
+ fixedclk_to_cmu = {6{reconfig_clk}},
+ int_hiprateswtichdone = {wire_central_clk_div0_rateswitchdone},
+ int_rx_coreclkout = {wire_receive_pcs3_coreclkout, wire_receive_pcs2_coreclkout, wire_receive_pcs1_coreclkout, wire_receive_pcs0_coreclkout},
+ int_rx_digitalreset_reg = {rx_digitalreset_reg0c[2]},
+ int_rx_phfifobyteserdisable = {wire_receive_pcs3_phfifobyteserdisableout, wire_receive_pcs2_phfifobyteserdisableout, wire_receive_pcs1_phfifobyteserdisableout, wire_receive_pcs0_phfifobyteserdisableout},
+ int_rx_phfifoptrsresetout = {wire_receive_pcs3_phfifoptrsresetout, wire_receive_pcs2_phfifoptrsresetout, wire_receive_pcs1_phfifoptrsresetout, wire_receive_pcs0_phfifoptrsresetout},
+ int_rx_phfifordenableout = {wire_receive_pcs3_phfifordenableout, wire_receive_pcs2_phfifordenableout, wire_receive_pcs1_phfifordenableout, wire_receive_pcs0_phfifordenableout},
+ int_rx_phfiforesetout = {wire_receive_pcs3_phfiforesetout, wire_receive_pcs2_phfiforesetout, wire_receive_pcs1_phfiforesetout, wire_receive_pcs0_phfiforesetout},
+ int_rx_phfifowrdisableout = {wire_receive_pcs3_phfifowrdisableout, wire_receive_pcs2_phfifowrdisableout, wire_receive_pcs1_phfifowrdisableout, wire_receive_pcs0_phfifowrdisableout},
+ int_rx_phfifoxnbytesel = {int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}},
+ int_rx_phfifoxnrdenable = {int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}},
+ int_rx_phfifoxnwrclk = {int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}},
+ int_rx_phfifoxnwrenable = {int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}},
+ int_rxcoreclk = {int_rx_coreclkout[0]},
+ int_rxphfifordenable = {int_rx_phfifordenableout[0]},
+ int_rxphfiforeset = {int_rx_phfiforesetout[0]},
+ int_rxphfifox4byteselout = {wire_cent_unit0_rxphfifox4byteselout},
+ int_rxphfifox4rdenableout = {wire_cent_unit0_rxphfifox4rdenableout},
+ int_rxphfifox4wrclkout = {wire_cent_unit0_rxphfifox4wrclkout},
+ int_rxphfifox4wrenableout = {wire_cent_unit0_rxphfifox4wrenableout},
+ int_tx_coreclkout = {wire_transmit_pcs3_coreclkout, wire_transmit_pcs2_coreclkout, wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
+ int_tx_digitalreset_reg = {tx_digitalreset_reg0c[2]},
+ int_tx_phfiforddisableout = {wire_transmit_pcs3_phfiforddisableout, wire_transmit_pcs2_phfiforddisableout, wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
+ int_tx_phfiforesetout = {wire_transmit_pcs3_phfiforesetout, wire_transmit_pcs2_phfiforesetout, wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
+ int_tx_phfifowrenableout = {wire_transmit_pcs3_phfifowrenableout, wire_transmit_pcs2_phfifowrenableout, wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
+ int_tx_phfifoxnbytesel = {int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}},
+ int_tx_phfifoxnrdclk = {int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}},
+ int_tx_phfifoxnrdenable = {int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}},
+ int_tx_phfifoxnwrenable = {int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}},
+ int_txcoreclk = {int_tx_coreclkout[0]},
+ int_txphfiforddisable = {int_tx_phfiforddisableout[0]},
+ int_txphfiforeset = {int_tx_phfiforesetout[0]},
+ int_txphfifowrenable = {int_tx_phfifowrenableout[0]},
+ int_txphfifox4byteselout = {wire_cent_unit0_txphfifox4byteselout},
+ int_txphfifox4rdclkout = {wire_cent_unit0_txphfifox4rdclkout},
+ int_txphfifox4rdenableout = {wire_cent_unit0_txphfifox4rdenableout},
+ int_txphfifox4wrenableout = {wire_cent_unit0_txphfifox4wrenableout},
+ nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
+ pll0_clkin = {{9{1'b0}}, pll_inclk_wire[0]},
+ pll0_dprioin = {cent_unit_cmuplldprioout[1499:1200]},
+ pll0_dprioout = {wire_tx_pll0_dprioout},
+ pll0_out = {wire_tx_pll0_clk[3:0]},
+ pll_ch_dataout_wire = {wire_rx_cdr_pll3_dataout, wire_rx_cdr_pll2_dataout, wire_rx_cdr_pll1_dataout, wire_rx_cdr_pll0_dataout},
+ pll_ch_dprioout = {wire_rx_cdr_pll3_dprioout, wire_rx_cdr_pll2_dprioout, wire_rx_cdr_pll1_dprioout, wire_rx_cdr_pll0_dprioout},
+ pll_cmuplldprioout = {{300{1'b0}}, pll0_dprioout[299:0], pll_ch_dprioout[1199:0]},
+ pll_inclk_wire = {pll_inclk},
+ pll_locked = {pll_locked_out[0]},
+ pll_locked_out = {wire_tx_pll0_locked},
+ pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]},
+ pllreset_in = {1'b0, cent_unit_pllresetout[0]},
+ reconfig_fromgxb = {rx_pma_analogtestbus[16:1], wire_cent_unit0_dprioout},
+ reconfig_togxb_busy = reconfig_togxb[3],
+ reconfig_togxb_disable = reconfig_togxb[1],
+ reconfig_togxb_in = reconfig_togxb[0],
+ reconfig_togxb_load = reconfig_togxb[2],
+ refclk_pma = {wire_central_clk_div0_refclkout},
+ rx_adetectdeskew = {wire_receive_pcs3_adetectdeskew, wire_receive_pcs2_adetectdeskew, wire_receive_pcs1_adetectdeskew, wire_receive_pcs0_adetectdeskew},
+ rx_alignstatussync = {rx_alignstatussyncout[0]},
+ rx_alignstatussyncout = {wire_receive_pcs3_alignstatussyncout, wire_receive_pcs2_alignstatussyncout, wire_receive_pcs1_alignstatussyncout, wire_receive_pcs0_alignstatussyncout},
+ rx_analogreset_in = {{2{1'b0}}, {4{((~ reconfig_togxb_busy) & rx_analogreset[0])}}},
+ rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]},
+ rx_channelaligned = {rx_channelaligned_in[0]},
+ rx_channelaligned_in = {wire_cent_unit0_alignstatus},
+ rx_coreclk_in = {rx_coreclk[3:0]},
+ rx_cruclk_in = {{9{1'b0}}, rx_pldcruclk_in[3], {9{1'b0}}, rx_pldcruclk_in[2], {9{1'b0}}, rx_pldcruclk_in[1], {9{1'b0}}, rx_pldcruclk_in[0]},
+ rx_ctrldetect = {wire_receive_pcs3_ctrldetect[1:0], wire_receive_pcs2_ctrldetect[1:0], wire_receive_pcs1_ctrldetect[1:0], wire_receive_pcs0_ctrldetect[1:0]},
+ rx_dataout = {rx_out_wire[63:0]},
+ rx_deserclock_in = {rx_pll_clkout[15:0]},
+ rx_digitalreset_in = {4{int_rx_digitalreset_reg[0]}},
+ rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]},
+ rx_disablefifordin_in = {rx_disablefifordout_wire[0]},
+ rx_disablefifordout_wire = {wire_receive_pcs3_disablefifordout, wire_receive_pcs2_disablefifordout, wire_receive_pcs1_disablefifordout, wire_receive_pcs0_disablefifordout},
+ rx_disablefifowrin_in = {rx_disablefifowrout_wire[0]},
+ rx_disablefifowrout_wire = {wire_receive_pcs3_disablefifowrout, wire_receive_pcs2_disablefifowrout, wire_receive_pcs1_disablefifowrout, wire_receive_pcs0_disablefifowrout},
+ rx_disperr = {wire_receive_pcs3_disperr[1:0], wire_receive_pcs2_disperr[1:0], wire_receive_pcs1_disperr[1:0], wire_receive_pcs0_disperr[1:0]},
+ rx_enapatternalign = {4{1'b0}},
+ rx_errdetect = {wire_receive_pcs3_errdetect[1:0], wire_receive_pcs2_errdetect[1:0], wire_receive_pcs1_errdetect[1:0], wire_receive_pcs0_errdetect[1:0]},
+ rx_fifordin_in = {rx_fifordout_wire[0]},
+ rx_fifordout_wire = {wire_receive_pcs3_fifordout, wire_receive_pcs2_fifordout, wire_receive_pcs1_fifordout, wire_receive_pcs0_fifordout},
+ rx_fiforesetrd = {wire_cent_unit0_fiforesetrd},
+ rx_freqlocked = {(rx_freqlocked_wire[3] & (~ rx_analogreset[0])), (rx_freqlocked_wire[2] & (~ rx_analogreset[0])), (rx_freqlocked_wire[1] & (~ rx_analogreset[0])), (rx_freqlocked_wire[0] & (~ rx_analogreset[0]))},
+ rx_freqlocked_wire = {wire_rx_cdr_pll3_freqlocked, wire_rx_cdr_pll2_freqlocked, wire_rx_cdr_pll1_freqlocked, wire_rx_cdr_pll0_freqlocked},
+ rx_locktodata_wire = {((~ reconfig_togxb_busy) & rx_locktodata[3]), ((~ reconfig_togxb_busy) & rx_locktodata[2]), ((~ reconfig_togxb_busy) & rx_locktodata[1]), ((~ reconfig_togxb_busy) & rx_locktodata[0])},
+ rx_locktorefclk_wire = {wire_receive_pcs3_cdrctrllocktorefclkout, wire_receive_pcs2_cdrctrllocktorefclkout, wire_receive_pcs1_cdrctrllocktorefclkout, wire_receive_pcs0_cdrctrllocktorefclkout},
+ rx_masterclk = {rx_pma_clockout[0]},
+ rx_out_wire = {wire_receive_pcs3_dataout[15:0], wire_receive_pcs2_dataout[15:0], wire_receive_pcs1_dataout[15:0], wire_receive_pcs0_dataout[15:0]},
+ rx_patterndetect = {wire_receive_pcs3_patterndetect[1:0], wire_receive_pcs2_patterndetect[1:0], wire_receive_pcs1_patterndetect[1:0], wire_receive_pcs0_patterndetect[1:0]},
+ rx_pcsdprioin_wire = {cent_unit_rxpcsdprioout[1599:0]},
+ rx_pcsdprioout = {wire_receive_pcs3_dprioout, wire_receive_pcs2_dprioout, wire_receive_pcs1_dprioout, wire_receive_pcs0_dprioout},
+ rx_phase_comp_fifo_error = {(rx_phfifooverflowout[3] | rx_phfifounderflowout[3]), (rx_phfifooverflowout[2] | rx_phfifounderflowout[2]), (rx_phfifooverflowout[1] | rx_phfifounderflowout[1]), (rx_phfifooverflowout[0] | rx_phfifounderflowout[0])},
+ rx_phfifooverflowout = {wire_receive_pcs3_phfifooverflow, wire_receive_pcs2_phfifooverflow, wire_receive_pcs1_phfifooverflow, wire_receive_pcs0_phfifooverflow},
+ rx_phfifordenable = {4{1'b1}},
+ rx_phfiforeset = {4{1'b0}},
+ rx_phfifounderflowout = {wire_receive_pcs3_phfifounderflow, wire_receive_pcs2_phfifounderflow, wire_receive_pcs1_phfifounderflow, wire_receive_pcs0_phfifounderflow},
+ rx_phfifowrdisable = {4{1'b0}},
+ rx_pldcruclk_in = {rx_cruclk[3:0]},
+ rx_pll_clkout = {wire_rx_cdr_pll3_clk, wire_rx_cdr_pll2_clk, wire_rx_cdr_pll1_clk, wire_rx_cdr_pll0_clk},
+ rx_pll_locked = {(rx_plllocked_wire[3] & (~ rx_analogreset[0])), (rx_plllocked_wire[2] & (~ rx_analogreset[0])), (rx_plllocked_wire[1] & (~ rx_analogreset[0])), (rx_plllocked_wire[0] & (~ rx_analogreset[0]))},
+ rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll3_pfdrefclkout, wire_rx_cdr_pll2_pfdrefclkout, wire_rx_cdr_pll1_pfdrefclkout, wire_rx_cdr_pll0_pfdrefclkout},
+ rx_plllocked_wire = {wire_rx_cdr_pll3_locked, wire_rx_cdr_pll2_locked, wire_rx_cdr_pll1_locked, wire_rx_cdr_pll0_locked},
+ rx_pma_analogtestbus = {{51{1'b0}}, wire_receive_pma3_analogtestbus[5:2], wire_receive_pma2_analogtestbus[5:2], wire_receive_pma1_analogtestbus[5:2], wire_receive_pma0_analogtestbus[5:2], 1'b0},
+ rx_pma_clockout = {wire_receive_pma3_clockout, wire_receive_pma2_clockout, wire_receive_pma1_clockout, wire_receive_pma0_clockout},
+ rx_pma_dataout = {wire_receive_pma3_dataout, wire_receive_pma2_dataout, wire_receive_pma1_dataout, wire_receive_pma0_dataout},
+ rx_pma_locktorefout = {wire_receive_pma3_locktorefout, wire_receive_pma2_locktorefout, wire_receive_pma1_locktorefout, wire_receive_pma0_locktorefout},
+ rx_pma_recoverdataout_wire = {wire_receive_pma3_recoverdataout[19:0], wire_receive_pma2_recoverdataout[19:0], wire_receive_pma1_recoverdataout[19:0], wire_receive_pma0_recoverdataout[19:0]},
+ rx_pmadprioin_wire = {{2{{300{1'b0}}}}, cent_unit_rxpmadprioout[1199:0]},
+ rx_pmadprioout = {{2{{300{1'b0}}}}, wire_receive_pma3_dprioout, wire_receive_pma2_dprioout, wire_receive_pma1_dprioout, wire_receive_pma0_dprioout},
+ rx_powerdown = {4{1'b0}},
+ rx_powerdown_in = {{2{1'b0}}, rx_powerdown[3:0]},
+ rx_prbscidenable = {4{1'b0}},
+ rx_rdalign = {wire_receive_pcs3_rdalign, wire_receive_pcs2_rdalign, wire_receive_pcs1_rdalign, wire_receive_pcs0_rdalign},
+ rx_rlv = {wire_receive_pcs3_rlv, wire_receive_pcs2_rlv, wire_receive_pcs1_rlv, wire_receive_pcs0_rlv},
+ rx_rmfifodatadeleted = {wire_receive_pcs3_rmfifodatadeleted[1:0], wire_receive_pcs2_rmfifodatadeleted[1:0], wire_receive_pcs1_rmfifodatadeleted[1:0], wire_receive_pcs0_rmfifodatadeleted[1:0]},
+ rx_rmfifodatainserted = {wire_receive_pcs3_rmfifodatainserted[1:0], wire_receive_pcs2_rmfifodatainserted[1:0], wire_receive_pcs1_rmfifodatainserted[1:0], wire_receive_pcs0_rmfifodatainserted[1:0]},
+ rx_rmfifoempty = {wire_receive_pcs3_rmfifoempty, wire_receive_pcs2_rmfifoempty, wire_receive_pcs1_rmfifoempty, wire_receive_pcs0_rmfifoempty},
+ rx_rmfifofull = {wire_receive_pcs3_rmfifofull, wire_receive_pcs2_rmfifofull, wire_receive_pcs1_rmfifofull, wire_receive_pcs0_rmfifofull},
+ rx_rmfiforeset = {4{1'b0}},
+ rx_runningdisp = {wire_receive_pcs3_runningdisp[1:0], wire_receive_pcs2_runningdisp[1:0], wire_receive_pcs1_runningdisp[1:0], wire_receive_pcs0_runningdisp[1:0]},
+ rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]},
+ rx_syncstatus = {wire_receive_pcs3_syncstatus[1:0], wire_receive_pcs2_syncstatus[1:0], wire_receive_pcs1_syncstatus[1:0], wire_receive_pcs0_syncstatus[1:0]},
+ rx_syncstatusdeskew = {wire_receive_pcs3_syncstatusdeskew, wire_receive_pcs2_syncstatusdeskew, wire_receive_pcs1_syncstatusdeskew, wire_receive_pcs0_syncstatusdeskew},
+ rx_xgmctrlin = {wire_cent_unit0_rxctrlout},
+ rx_xgmdataout = {wire_receive_pcs3_xgmdataout, wire_receive_pcs2_xgmdataout, wire_receive_pcs1_xgmdataout, wire_receive_pcs0_xgmdataout},
+ rx_xgmdatavalid = {wire_receive_pcs3_xgmdatavalid, wire_receive_pcs2_xgmdatavalid, wire_receive_pcs1_xgmdatavalid, wire_receive_pcs0_xgmdatavalid},
+ rx_xgmrunningdisp = {wire_receive_pcs3_xgmrunningdisp, wire_receive_pcs2_xgmrunningdisp, wire_receive_pcs1_xgmrunningdisp, wire_receive_pcs0_xgmrunningdisp},
+ rxphfifowrdisable = {int_rx_phfifowrdisableout[0]},
+ rxpll_dprioin = {{2{{300{1'b0}}}}, cent_unit_cmuplldprioout[1199:0]},
+ tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
+ tx_coreclk_in = {tx_coreclk[3:0]},
+ tx_datain_wire = {tx_datain[63:0]},
+ tx_dataout = {wire_transmit_pma3_dataout, wire_transmit_pma2_dataout, wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
+ tx_dataout_pcs_to_pma = {wire_transmit_pcs3_dataout, wire_transmit_pcs2_dataout, wire_transmit_pcs1_dataout, wire_transmit_pcs0_dataout},
+ tx_digitalreset_in = {4{int_tx_digitalreset_reg[0]}},
+ tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]},
+ tx_dprioin_wire = {{600{1'b0}}, cent_unit_txdprioout[599:0]},
+ tx_forcedisp_wire = {4{{2{1'b0}}}},
+ tx_localrefclk = {wire_transmit_pma3_clockout, wire_transmit_pma2_clockout, wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
+ tx_phase_comp_fifo_error = {(tx_phfifooverflowout[3] | tx_phfifounderflowout[3]), (tx_phfifooverflowout[2] | tx_phfifounderflowout[2]), (tx_phfifooverflowout[1] | tx_phfifounderflowout[1]), (tx_phfifooverflowout[0] | tx_phfifounderflowout[0])},
+ tx_phfifooverflowout = {wire_transmit_pcs3_phfifooverflow, wire_transmit_pcs2_phfifooverflow, wire_transmit_pcs1_phfifooverflow, wire_transmit_pcs0_phfifooverflow},
+ tx_phfiforeset = {4{1'b0}},
+ tx_phfifounderflowout = {wire_transmit_pcs3_phfifounderflow, wire_transmit_pcs2_phfifounderflow, wire_transmit_pcs1_phfifounderflow, wire_transmit_pcs0_phfifounderflow},
+ tx_pmadprioin_wire = {{2{{300{1'b0}}}}, cent_unit_txpmadprioout[1199:0]},
+ tx_pmadprioout = {{2{{300{1'b0}}}}, wire_transmit_pma3_dprioout, wire_transmit_pma2_dprioout, wire_transmit_pma1_dprioout, wire_transmit_pma0_dprioout},
+ tx_rdenablesync = {wire_transmit_pcs3_rdenablesync, wire_transmit_pcs2_rdenablesync, wire_transmit_pcs1_rdenablesync, wire_transmit_pcs0_rdenablesync},
+ tx_serialloopbackout = {wire_transmit_pma3_seriallpbkout, wire_transmit_pma2_seriallpbkout, wire_transmit_pma1_seriallpbkout, wire_transmit_pma0_seriallpbkout},
+ tx_txdprioout = {wire_transmit_pcs3_dprioout, wire_transmit_pcs2_dprioout, wire_transmit_pcs1_dprioout, wire_transmit_pcs0_dprioout},
+ tx_xgmctrlenable = {wire_transmit_pcs3_xgmctrlenable, wire_transmit_pcs2_xgmctrlenable, wire_transmit_pcs1_xgmctrlenable, wire_transmit_pcs0_xgmctrlenable},
+ tx_xgmdataout = {wire_transmit_pcs3_xgmdataout, wire_transmit_pcs2_xgmdataout, wire_transmit_pcs1_xgmdataout, wire_transmit_pcs0_xgmdataout},
+ txdetectrxout = {wire_transmit_pcs3_txdetectrx, wire_transmit_pcs2_txdetectrx, wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx},
+ w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
+endmodule //hxaui_alt4gxb_alt4gxb_dksa
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+//(* ALTERA_ATTRIBUTE = {"-name SDC_STATEMENT \"set_false_path -from [get_registers *hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component*fifo*flow] -to [get_registers *xaui_phy*hxaui_csr*tx_phase_comp_fifo_error_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers *hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component*] -to [get_registers *xaui_phy*hxaui_csr*rx*_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*siv_xcvr_xaui*hxaui_csr*hxaui_csr_reset0q[*]}] -to [get_registers {*xaui_phy*hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component|*digitalreset*}]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*siv_xcvr_xaui*alt_pma_ch_controller_0*rc*}] -to [get_registers {*xaui_phy*hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component|*digitalreset*}]\""} *)
+module hxaui_alt4gxb (
+ cal_blk_clk,
+ cal_blk_powerdown,
+ gxb_powerdown,
+ pll_inclk,
+ pll_powerdown,
+ reconfig_clk,
+ reconfig_togxb,
+ rx_analogreset,
+ rx_cruclk,
+ rx_datain,
+ rx_digitalreset,
+ rx_invpolarity,
+ rx_locktodata,
+ rx_locktorefclk,
+ rx_seriallpbken,
+ tx_coreclk,
+ tx_ctrlenable,
+ tx_datain,
+ tx_digitalreset,
+ tx_invpolarity,
+ coreclkout,
+ pll_locked,
+ reconfig_fromgxb,
+ rx_channelaligned,
+ rx_ctrldetect,
+ rx_dataout,
+ rx_disperr,
+ rx_errdetect,
+ rx_freqlocked,
+ rx_patterndetect,
+ rx_phase_comp_fifo_error,
+ rx_pll_locked,
+ rx_rlv,
+ rx_rmfifodatadeleted,
+ rx_rmfifodatainserted,
+ rx_rmfifoempty,
+ rx_rmfifofull,
+ rx_runningdisp,
+ rx_syncstatus,
+ rx_recovered_clk,
+ tx_dataout,
+ tx_phase_comp_fifo_error);
+
+ input cal_blk_clk;
+ input cal_blk_powerdown;
+ input [0:0] gxb_powerdown;
+ input pll_inclk;
+ input [0:0] pll_powerdown;
+ input reconfig_clk;
+ input [3:0] reconfig_togxb;
+ input [0:0] rx_analogreset;
+ wire [3:0] rx_coreclk;
+ input [3:0] rx_cruclk;
+ input [3:0] rx_datain;
+ input [0:0] rx_digitalreset;
+ input [3:0] rx_invpolarity;
+ input [3:0] rx_locktodata;
+ input [3:0] rx_locktorefclk;
+ input [3:0] rx_seriallpbken;
+ input [3:0] tx_coreclk;
+ input [7:0] tx_ctrlenable;
+ input [63:0] tx_datain;
+ input [0:0] tx_digitalreset;
+ input [3:0] tx_invpolarity;
+ output [0:0] coreclkout;
+ output [0:0] pll_locked;
+ output [16:0] reconfig_fromgxb;
+ output [0:0] rx_channelaligned;
+ output [7:0] rx_ctrldetect;
+ output [63:0] rx_dataout;
+ output [7:0] rx_disperr;
+ output [7:0] rx_errdetect;
+ output [3:0] rx_freqlocked;
+ output [3:0] rx_recovered_clk;
+ output [7:0] rx_patterndetect;
+ output [3:0] rx_phase_comp_fifo_error;
+ output [3:0] rx_pll_locked;
+ output [3:0] rx_rlv;
+ output [7:0] rx_rmfifodatadeleted;
+ output [7:0] rx_rmfifodatainserted;
+ output [3:0] rx_rmfifoempty;
+ output [3:0] rx_rmfifofull;
+ output [7:0] rx_runningdisp;
+ output [7:0] rx_syncstatus;
+ output [3:0] tx_dataout;
+ output [3:0] tx_phase_comp_fifo_error;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 [3:0] rx_cruclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ parameter starting_channel_number = 0;
+ parameter transmitter_termination = "OCT 100 OHMS";//OCT_85_OHMS,OCT_100_OHMS,OCT_120_OHMS,OCT_150_OHMS
+ parameter receiver_termination = "OCT 100 OHMS"; //OCT_85_OHMS,OCT_100_OHMS,OCT_120_OHMS,OCT_150_OHMS
+ parameter rx_common_mode = "0.82v";
+
+ parameter preemphasis_ctrl_pretap_setting = 0;//0-7
+ parameter preemphasis_ctrl_pretap_inv_setting = "FALSE";//TRUE or FALSE.
+ parameter preemphasis_ctrl_1stposttap_setting = 5;//0-15
+ parameter preemphasis_ctrl_2ndposttap_setting = 0;//0-7
+ parameter preemphasis_ctrl_2ndposttap_inv_setting = "FALSE";//TRUE or FALSE.
+ parameter vod_ctrl_setting = 1;//0-7
+
+ parameter equalizer_dcgain_setting = 0; //0-4
+ parameter equalizer_ctrl_a_setting = 0;
+ parameter equalizer_ctrl_b_setting = 0;
+ parameter equalizer_ctrl_c_setting = 0;
+ parameter equalizer_ctrl_d_setting = 0;
+ parameter equalizer_ctrl_v_setting = 0;
+
+
+ wire [7:0] sub_wire0;
+ wire [3:0] sub_wire1;
+ wire [3:0] sub_wire2;
+ wire [7:0] sub_wire3;
+ wire [0:0] sub_wire4;
+ wire [7:0] sub_wire5;
+ wire [7:0] sub_wire6;
+ wire [7:0] sub_wire7;
+ wire [3:0] sub_wire8;
+ wire [3:0] sub_wire9;
+ wire [7:0] sub_wire10;
+ wire [3:0] sub_wire11;
+ wire [3:0] sub_wire12;
+ wire [7:0] sub_wire13;
+ wire [3:0] sub_wire14;
+ wire [0:0] sub_wire15;
+ wire [3:0] sub_wire16;
+ wire [7:0] sub_wire17;
+ wire [16:0] sub_wire18;
+ wire [0:0] sub_wire19;
+ wire [63:0] sub_wire20;
+ wire [7:0] rx_disperr = sub_wire0[7:0];
+ wire [3:0] rx_rmfifoempty = sub_wire1[3:0];
+ wire [3:0] rx_rlv = sub_wire2[3:0];
+ wire [7:0] rx_patterndetect = sub_wire3[7:0];
+ wire [0:0] coreclkout = sub_wire4[0:0];
+ wire [7:0] rx_ctrldetect = sub_wire5[7:0];
+ wire [7:0] rx_errdetect = sub_wire6[7:0];
+ wire [7:0] rx_rmfifodatadeleted = sub_wire7[7:0];
+ wire [3:0] rx_pll_locked = sub_wire8[3:0];
+ wire [3:0] rx_freqlocked = sub_wire9[3:0];
+ wire [7:0] rx_runningdisp = sub_wire10[7:0];
+ wire [3:0] tx_phase_comp_fifo_error = sub_wire11[3:0];
+ wire [3:0] tx_dataout = sub_wire12[3:0];
+ wire [7:0] rx_rmfifodatainserted = sub_wire13[7:0];
+ wire [3:0] rx_phase_comp_fifo_error = sub_wire14[3:0];
+ wire [0:0] rx_channelaligned = sub_wire15[0:0];
+ wire [3:0] rx_rmfifofull = sub_wire16[3:0];
+ wire [7:0] rx_syncstatus = sub_wire17[7:0];
+ wire [16:0] reconfig_fromgxb = sub_wire18[16:0];
+ wire [0:0] pll_locked = sub_wire19[0:0];
+ wire [63:0] rx_dataout = sub_wire20[63:0];
+ wire coreclkout_global;
+ // Start - Manually instantiate the clock control block without requiring the MegaWizard generated file
+ stratixiv_clkena sd1
+ (
+ .ena(1'b1),
+ .enaout(),
+ .inclk(sub_wire4),
+ .outclk(coreclkout_global)
+ // synopsys translate_off
+ ,
+ .devclrn(1'b1),
+ .devpor(1'b1)
+ // synopsys translate_on
+ );
+ defparam
+ //sd1.clock_type = "Global Clock",
+ sd1.ena_register_mode = "falling edge",
+ sd1.lpm_type = "stratixiv_clkena";
+ // End
+ assign rx_coreclk = {4{coreclkout_global}};
+
+ hxaui_alt4gxb_alt4gxb_dksa hxaui_alt4gxb_alt4gxb_dksa_component (
+ .rx_locktorefclk (rx_locktorefclk),
+ .rx_invpolarity (rx_invpolarity),
+ .pll_inclk (pll_inclk),
+ .tx_invpolarity (tx_invpolarity),
+ .gxb_powerdown (gxb_powerdown),
+ .tx_datain (tx_datain),
+ .rx_cruclk (rx_cruclk),
+ .cal_blk_clk (cal_blk_clk),
+ .pll_powerdown (pll_powerdown),
+ .reconfig_clk (reconfig_clk),
+ .rx_seriallpbken (rx_seriallpbken),
+ .rx_locktodata (rx_locktodata),
+ .rx_datain (rx_datain),
+ .cal_blk_powerdown (cal_blk_powerdown),
+ .reconfig_togxb (reconfig_togxb),
+ .tx_coreclk (tx_coreclk),
+ .tx_ctrlenable (tx_ctrlenable),
+ .rx_analogreset (rx_analogreset),
+ .rx_digitalreset (rx_digitalreset),
+ .tx_digitalreset (tx_digitalreset),
+ .rx_disperr (sub_wire0),
+ .rx_rmfifoempty (sub_wire1),
+ .rx_rlv (sub_wire2),
+ .rx_patterndetect (sub_wire3),
+ .coreclkout (sub_wire4),
+ .rx_ctrldetect (sub_wire5),
+ .rx_errdetect (sub_wire6),
+ .rx_rmfifodatadeleted (sub_wire7),
+ .rx_pll_locked (sub_wire8),
+ .rx_freqlocked (sub_wire9),
+ .rx_runningdisp (sub_wire10),
+ .tx_phase_comp_fifo_error (sub_wire11),
+ .tx_dataout (sub_wire12),
+ .rx_rmfifodatainserted (sub_wire13),
+ .rx_phase_comp_fifo_error (sub_wire14),
+ .rx_channelaligned (sub_wire15),
+ .rx_rmfifofull (sub_wire16),
+ .rx_coreclk (rx_coreclk),
+ .rx_syncstatus (sub_wire17),
+ .rx_recovered_clk(rx_recovered_clk), // o
+ .reconfig_fromgxb (sub_wire18),
+ .pll_locked (sub_wire19),
+ .rx_dataout (sub_wire20));
+ defparam
+ hxaui_alt4gxb_alt4gxb_dksa_component.starting_channel_number = starting_channel_number,
+ hxaui_alt4gxb_alt4gxb_dksa_component.receiver_termination = receiver_termination,
+ hxaui_alt4gxb_alt4gxb_dksa_component.transmitter_termination = transmitter_termination,
+ hxaui_alt4gxb_alt4gxb_dksa_component.preemphasis_ctrl_pretap_setting = preemphasis_ctrl_pretap_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.preemphasis_ctrl_pretap_inv_setting = preemphasis_ctrl_pretap_inv_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.preemphasis_ctrl_1stposttap_setting = preemphasis_ctrl_1stposttap_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.preemphasis_ctrl_2ndposttap_setting = preemphasis_ctrl_2ndposttap_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.preemphasis_ctrl_2ndposttap_inv_setting = preemphasis_ctrl_2ndposttap_inv_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.vod_ctrl_setting = vod_ctrl_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.rx_common_mode = rx_common_mode,
+ hxaui_alt4gxb_alt4gxb_dksa_component.equalizer_ctrl_a_setting = equalizer_ctrl_a_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.equalizer_ctrl_b_setting = equalizer_ctrl_b_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.equalizer_ctrl_c_setting = equalizer_ctrl_c_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.equalizer_ctrl_d_setting = equalizer_ctrl_d_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.equalizer_ctrl_v_setting = equalizer_ctrl_v_setting,
+ hxaui_alt4gxb_alt4gxb_dksa_component.equalizer_dcgain_setting = equalizer_dcgain_setting;
+
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
+// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
+// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
+// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "3125.0"
+// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
+// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "3125"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "50.0 "
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "50.0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "250.0"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "XAUI"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
+// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
+// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "1"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "156.25"
+// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "156.25"
+// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "3125"
+// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
+// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "156.25"
+// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
+// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "XAUI"
+// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "None"
+// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
+// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
+// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "3125 Mbps"
+// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
+// Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "AUTO"
+// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "156.25 MHz"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "2"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "GX"
+// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "slb"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "4"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
+// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
+// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
+// Retrieval info: CONSTANT: PROTOCOL STRING "xaui"
+// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
+// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
+// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
+// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false"
+// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
+// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
+// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x4"
+// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
+// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Auto"
+// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "6400"
+// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "xaui"
+// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "3125"
+// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "true"
+// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "true"
+// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
+// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "1101000011"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "0010111100"
+// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "10"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
+// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
+// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "2"
+// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
+// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "true"
+// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
+// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
+// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
+// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "true"
+// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "AUTO"
+// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x4"
+// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "4"
+// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
+// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "3125"
+// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
+// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
+// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
+// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "Auto"
+// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "6400"
+// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
+// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "low"
+// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "xaui"
+// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "true"
+// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
+// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
+// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
+// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
+// Retrieval info: CONSTANT: coreclkout_control_width NUMERIC "1"
+// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
+// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
+// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
+// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "17"
+// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
+// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "10"
+// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "1"
+// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "2"
+// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "1"
+// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "1"
+// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
+// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
+// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "2"
+// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "10"
+// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "1"
+// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "2"
+// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
+// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
+// Retrieval info: USED_PORT: cal_blk_powerdown 0 0 0 0 INPUT NODEFVAL "cal_blk_powerdown"
+// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
+// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
+// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
+// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
+// Retrieval info: USED_PORT: pll_powerdown 0 0 1 0 INPUT NODEFVAL "pll_powerdown[0..0]"
+// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 OUTPUT NODEFVAL "reconfig_fromgxb[16..0]"
+// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
+// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
+// Retrieval info: USED_PORT: rx_channelaligned 0 0 1 0 OUTPUT NODEFVAL "rx_channelaligned[0..0]"
+// Retrieval info: USED_PORT: rx_cruclk 0 0 4 0 INPUT GND "rx_cruclk[3..0]"
+// Retrieval info: USED_PORT: rx_ctrldetect 0 0 8 0 OUTPUT NODEFVAL "rx_ctrldetect[7..0]"
+// Retrieval info: USED_PORT: rx_datain 0 0 4 0 INPUT NODEFVAL "rx_datain[3..0]"
+// Retrieval info: USED_PORT: rx_dataout 0 0 64 0 OUTPUT NODEFVAL "rx_dataout[63..0]"
+// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: rx_disperr 0 0 8 0 OUTPUT NODEFVAL "rx_disperr[7..0]"
+// Retrieval info: USED_PORT: rx_errdetect 0 0 8 0 OUTPUT NODEFVAL "rx_errdetect[7..0]"
+// Retrieval info: USED_PORT: rx_freqlocked 0 0 4 0 OUTPUT NODEFVAL "rx_freqlocked[3..0]"
+// Retrieval info: USED_PORT: rx_invpolarity 0 0 4 0 INPUT NODEFVAL "rx_invpolarity[3..0]"
+// Retrieval info: USED_PORT: rx_locktodata 0 0 4 0 INPUT NODEFVAL "rx_locktodata[3..0]"
+// Retrieval info: USED_PORT: rx_locktorefclk 0 0 4 0 INPUT NODEFVAL "rx_locktorefclk[3..0]"
+// Retrieval info: USED_PORT: rx_patterndetect 0 0 8 0 OUTPUT NODEFVAL "rx_patterndetect[7..0]"
+// Retrieval info: USED_PORT: rx_phase_comp_fifo_error 0 0 4 0 OUTPUT NODEFVAL "rx_phase_comp_fifo_error[3..0]"
+// Retrieval info: USED_PORT: rx_pll_locked 0 0 4 0 OUTPUT NODEFVAL "rx_pll_locked[3..0]"
+// Retrieval info: USED_PORT: rx_rlv 0 0 4 0 OUTPUT NODEFVAL "rx_rlv[3..0]"
+// Retrieval info: USED_PORT: rx_rmfifodatadeleted 0 0 8 0 OUTPUT NODEFVAL "rx_rmfifodatadeleted[7..0]"
+// Retrieval info: USED_PORT: rx_rmfifodatainserted 0 0 8 0 OUTPUT NODEFVAL "rx_rmfifodatainserted[7..0]"
+// Retrieval info: USED_PORT: rx_rmfifoempty 0 0 4 0 OUTPUT NODEFVAL "rx_rmfifoempty[3..0]"
+// Retrieval info: USED_PORT: rx_rmfifofull 0 0 4 0 OUTPUT NODEFVAL "rx_rmfifofull[3..0]"
+// Retrieval info: USED_PORT: rx_runningdisp 0 0 8 0 OUTPUT NODEFVAL "rx_runningdisp[7..0]"
+// Retrieval info: USED_PORT: rx_seriallpbken 0 0 4 0 INPUT NODEFVAL "rx_seriallpbken[3..0]"
+// Retrieval info: USED_PORT: rx_syncstatus 0 0 8 0 OUTPUT NODEFVAL "rx_syncstatus[7..0]"
+// Retrieval info: USED_PORT: tx_coreclk 0 0 4 0 INPUT NODEFVAL "tx_coreclk[3..0]"
+// Retrieval info: USED_PORT: tx_ctrlenable 0 0 8 0 INPUT NODEFVAL "tx_ctrlenable[7..0]"
+// Retrieval info: USED_PORT: tx_datain 0 0 64 0 INPUT NODEFVAL "tx_datain[63..0]"
+// Retrieval info: USED_PORT: tx_dataout 0 0 4 0 OUTPUT NODEFVAL "tx_dataout[3..0]"
+// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
+// Retrieval info: USED_PORT: tx_invpolarity 0 0 4 0 INPUT NODEFVAL "tx_invpolarity[3..0]"
+// Retrieval info: USED_PORT: tx_phase_comp_fifo_error 0 0 4 0 OUTPUT NODEFVAL "tx_phase_comp_fifo_error[3..0]"
+// Retrieval info: CONNECT: rx_patterndetect 0 0 8 0 @rx_patterndetect 0 0 8 0
+// Retrieval info: CONNECT: @rx_invpolarity 0 0 4 0 rx_invpolarity 0 0 4 0
+// Retrieval info: CONNECT: @rx_locktorefclk 0 0 4 0 rx_locktorefclk 0 0 4 0
+// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
+// Retrieval info: CONNECT: rx_ctrldetect 0 0 8 0 @rx_ctrldetect 0 0 8 0
+// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
+// Retrieval info: CONNECT: rx_dataout 0 0 64 0 @rx_dataout 0 0 64 0
+// Retrieval info: CONNECT: rx_runningdisp 0 0 8 0 @rx_runningdisp 0 0 8 0
+// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
+// Retrieval info: CONNECT: rx_phase_comp_fifo_error 0 0 4 0 @rx_phase_comp_fifo_error 0 0 4 0
+// Retrieval info: CONNECT: rx_rmfifofull 0 0 4 0 @rx_rmfifofull 0 0 4 0
+// Retrieval info: CONNECT: rx_errdetect 0 0 8 0 @rx_errdetect 0 0 8 0
+// Retrieval info: CONNECT: rx_channelaligned 0 0 1 0 @rx_channelaligned 0 0 1 0
+// Retrieval info: CONNECT: @tx_coreclk 0 0 4 0 tx_coreclk 0 0 4 0
+// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: rx_pll_locked 0 0 4 0 @rx_pll_locked 0 0 4 0
+// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
+// Retrieval info: CONNECT: rx_syncstatus 0 0 8 0 @rx_syncstatus 0 0 8 0
+// Retrieval info: CONNECT: @rx_seriallpbken 0 0 4 0 rx_seriallpbken 0 0 4 0
+// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+// Retrieval info: CONNECT: tx_phase_comp_fifo_error 0 0 4 0 @tx_phase_comp_fifo_error 0 0 4 0
+// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
+// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
+// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
+// Retrieval info: CONNECT: @rx_cruclk 0 0 4 0 rx_cruclk 0 0 4 0
+// Retrieval info: CONNECT: @tx_invpolarity 0 0 4 0 tx_invpolarity 0 0 4 0
+// Retrieval info: CONNECT: rx_rlv 0 0 4 0 @rx_rlv 0 0 4 0
+// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
+// Retrieval info: CONNECT: @tx_ctrlenable 0 0 8 0 tx_ctrlenable 0 0 8 0
+// Retrieval info: CONNECT: tx_dataout 0 0 4 0 @tx_dataout 0 0 4 0
+// Retrieval info: CONNECT: @tx_datain 0 0 64 0 tx_datain 0 0 64 0
+// Retrieval info: CONNECT: reconfig_fromgxb 0 0 17 0 @reconfig_fromgxb 0 0 17 0
+// Retrieval info: CONNECT: rx_rmfifoempty 0 0 4 0 @rx_rmfifoempty 0 0 4 0
+// Retrieval info: CONNECT: @cal_blk_powerdown 0 0 0 0 cal_blk_powerdown 0 0 0 0
+// Retrieval info: CONNECT: rx_freqlocked 0 0 4 0 @rx_freqlocked 0 0 4 0
+// Retrieval info: CONNECT: @rx_locktodata 0 0 4 0 rx_locktodata 0 0 4 0
+// Retrieval info: CONNECT: @rx_datain 0 0 4 0 rx_datain 0 0 4 0
+// Retrieval info: CONNECT: rx_rmfifodatainserted 0 0 8 0 @rx_rmfifodatainserted 0 0 8 0
+// Retrieval info: CONNECT: rx_rmfifodatadeleted 0 0 8 0 @rx_rmfifodatadeleted 0 0 8 0
+// Retrieval info: CONNECT: rx_disperr 0 0 8 0 @rx_disperr 0 0 8 0
+// Retrieval info: CONNECT: @pll_powerdown 0 0 1 0 pll_powerdown 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL hxaui_alt4gxb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL hxaui_alt4gxb.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL hxaui_alt4gxb.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL hxaui_alt4gxb.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL hxaui_alt4gxb.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL hxaui_alt4gxb_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL hxaui_alt4gxb_bb.v TRUE
+// Retrieval info: LIB_FILE: stratixiv_hssi
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/hxaui_csr.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/hxaui_csr.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5ad633285f019d30350c678e518974f6621093e3
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/hxaui_csr.sv
@@ -0,0 +1,415 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// (C) 2001-2010 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+///////////////////////////////////////////////////////////////////////////////
+//
+//
+// Description: Hard xaui control and status registers
+//
+// Authors: ishimony 12-Jun-2009
+//
+// Copyright (c) Altera Corporation 1997 - 2009
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+//
+// TBD: unless synthesis is smart enough all synchronization flops will have
+// to be manually instantiated (altera_std_synchronizer)
+//
+
+`timescale 1 ps / 1 ps
+
+module hxaui_csr(
+ clk, reset, address, byteenable, read, readdata, write, writedata,
+ rx_patterndetect, rx_syncstatus, rx_runningdisp, rx_errdetect,
+ rx_disperr, rx_phase_comp_fifo_error, rx_rlv, rx_rmfifodatadeleted,
+ rx_rmfifodatainserted, rx_rmfifoempty, rx_rmfifofull,
+ tx_phase_comp_fifo_error, r_rx_invpolarity, r_tx_invpolarity,
+ r_rx_digitalreset, r_tx_digitalreset, simulation_flag
+); // module hxaui_csr
+import hxaui_csr_h::*;
+
+// ports -------------------------------------------------------------------
+
+// Avalon MM slave
+input clk;
+input reset;
+
+input [4:0] address;
+input [3:0] byteenable;
+
+input read;
+output [31:0] readdata;
+
+input write;
+input [31:0] writedata;
+
+// hard xaui control/status
+input [7:0] rx_patterndetect;
+input [7:0] rx_syncstatus;
+input [7:0] rx_runningdisp; // nc
+
+input [7:0] rx_errdetect;
+input [7:0] rx_disperr;
+
+input [3:0] rx_phase_comp_fifo_error;
+input [3:0] rx_rlv;
+
+input [7:0] rx_rmfifodatadeleted;
+input [7:0] rx_rmfifodatainserted;
+input [3:0] rx_rmfifoempty;
+input [3:0] rx_rmfifofull;
+
+input [3:0] tx_phase_comp_fifo_error;
+
+output [3:0] r_rx_invpolarity;
+output [3:0] r_tx_invpolarity;
+output r_rx_digitalreset;
+output r_tx_digitalreset;
+
+output simulation_flag; // '1' shortens reset and loss_timer length
+
+// ports -------------------------------------------------------------------
+wire clk;
+wire reset;
+wire [4:0] address;
+wire [6:0] addr;
+wire [3:0] byteenable;
+wire read;
+reg [31:0] readdata;
+wire write;
+wire [31:0] writedata;
+wire [3:0] rx_phase_comp_fifo_error;
+wire [3:0] rx_rlv;
+wire [3:0] rx_rmfifoempty;
+wire [3:0] rx_rmfifofull;
+wire [3:0] tx_phase_comp_fifo_error;
+wire [7:0] rx_disperr;
+wire [7:0] rx_errdetect;
+wire [7:0] rx_patterndetect;
+wire [7:0] rx_rmfifodatadeleted;
+wire [7:0] rx_rmfifodatainserted;
+wire [7:0] rx_runningdisp;
+wire [7:0] rx_syncstatus;
+wire [3:0] r_rx_invpolarity;
+wire [3:0] r_tx_invpolarity;
+wire r_rx_digitalreset;
+wire r_tx_digitalreset;
+wire simulation_flag;
+
+// locals ------------------------------------------------------------------
+reg [1:0] hxaui_csr_reset, hxaui_csr_reset0q;
+reg [3:0] hxaui_csr_rx_cntrl, hxaui_csr_rx_cntrl0q;
+reg [3:0] hxaui_csr_tx_cntrl, hxaui_csr_tx_cntrl0q;
+wire [31:0] hxaui_csr_rx_status_0;
+wire [31:0] hxaui_csr_rx_status_1;
+wire [31:0] hxaui_csr_rx_status_2;
+wire [31:0] hxaui_csr_rx_status_3;
+wire [31:0] hxaui_csr_rx_status_4;
+wire [31:0] hxaui_csr_tx_status_0;
+reg hxaui_csr_simulation_flag, hxaui_csr_simulation_flag0q;
+
+
+reg [7:0] rx_patterndetect_c; // rx_patterndetect synced to clk
+reg [7:0] rx_syncstatus_c; // rx_syncstatus synced to clk
+reg [7:0] rx_patterndetect_sr; // rx_patterndetect sr ff
+reg [7:0] rx_syncstatus_sr; // rx_syncstatus sr ff
+wire read_rx_status_0;
+
+reg [7:0] rx_errdetect_c; // rx_errdetect synced to clk
+reg [7:0] rx_disperr_c; // rx_disperr synced to clk
+reg [7:0] rx_errdetect_sr; // rx_errdetect sr ff
+reg [7:0] rx_disperr_sr; // rx_disperr sr ff
+wire read_rx_status_1;
+
+reg [3:0] rx_phase_comp_fifo_error_c; // rx_phase_comp_fifo_error synced
+reg [3:0] rx_rlv_c; // rx_rlv synced to clk
+reg [3:0] rx_phase_comp_fifo_error_sr; // rx_phase_comp_fifo_error sr ff
+reg [3:0] rx_rlv_sr; // rx_rlv sr ff
+wire read_rx_status_2;
+
+reg [7:0] rx_rmfifodatainserted_c; // rx_rmfifodatainserted synced to clk
+reg [7:0] rx_rmfifodatadeleted_c; // rx_rmfifodatadeleted synced to clk
+reg [7:0] rx_rmfifodatainserted_sr;// rx_rmfifodatainserted sr ff
+reg [7:0] rx_rmfifodatadeleted_sr; // rx_rmfifodatadeleted sr ff
+wire read_rx_status_3;
+
+reg [3:0] rx_rmfifofull_c; // rx_rmfifo_full synced
+reg [3:0] rx_rmfifoempty_c; // rx_rmfifoempty synced to clk
+reg [3:0] rx_rmfifofull_sr; // rx_rmfifo_full sr ff
+reg [3:0] rx_rmfifoempty_sr; // rx_rmfifoempty sr ff
+wire read_rx_status_4;
+
+wire read_rx_status_5;
+
+reg [3:0] tx_phase_comp_fifo_error_c; // tx_phase_comp_fifo_error synced
+reg [3:0] tx_phase_comp_fifo_error_sr; // tx_phase_comp_fifo_error sr ff
+wire read_tx_status_0;
+
+// body --------------------------------------------------------------------
+
+//--- readdata output latch ---
+// For easier address debug shift back 2 bits
+assign addr = {address[4:0], 2'b00};
+
+always @(*) begin
+ case (addr)
+ HXAUI_CSR_RESET_ADDR:
+ readdata <= hxaui_csr_reset0q;
+ HXAUI_CSR_RX_CNTRL_ADDR:
+ readdata <= hxaui_csr_rx_cntrl0q;
+ HXAUI_CSR_TX_CNTRL_ADDR:
+ readdata <= hxaui_csr_tx_cntrl0q;
+ HXAUI_CSR_RX_STATUS_0_ADDR:
+ readdata <= hxaui_csr_rx_status_0;
+ HXAUI_CSR_RX_STATUS_1_ADDR:
+ readdata <= hxaui_csr_rx_status_1;
+ HXAUI_CSR_RX_STATUS_2_ADDR:
+ readdata <= hxaui_csr_rx_status_2;
+ HXAUI_CSR_RX_STATUS_3_ADDR:
+ readdata <= hxaui_csr_rx_status_3;
+ HXAUI_CSR_RX_STATUS_4_ADDR:
+ readdata <= hxaui_csr_rx_status_4;
+ HXAUI_CSR_TX_STATUS_0_ADDR:
+ readdata <= hxaui_csr_tx_status_0;
+ HXAUI_CSR_SIMULATION_FLAG_ADDR:
+ readdata <= hxaui_csr_simulation_flag0q;
+ default:
+ readdata <= 32'h0;
+ endcase // case (addr)
+end
+
+always @ (posedge clk or posedge reset) begin
+ if (reset) begin
+ hxaui_csr_reset0q <= 2'b0;
+ hxaui_csr_rx_cntrl0q <= 4'b0;
+ hxaui_csr_tx_cntrl0q <= 4'b0;
+ hxaui_csr_simulation_flag0q <= 1'b0;
+ end else begin
+ hxaui_csr_reset0q <= hxaui_csr_reset;
+ hxaui_csr_rx_cntrl0q <= hxaui_csr_rx_cntrl;
+ hxaui_csr_tx_cntrl0q <= hxaui_csr_tx_cntrl;
+ hxaui_csr_simulation_flag0q <= hxaui_csr_simulation_flag;
+ end
+end
+
+
+always @ (*) begin
+ hxaui_csr_reset = hxaui_csr_reset0q;
+ hxaui_csr_rx_cntrl = hxaui_csr_rx_cntrl0q;
+ hxaui_csr_tx_cntrl = hxaui_csr_tx_cntrl0q;
+ hxaui_csr_simulation_flag = hxaui_csr_simulation_flag0q;
+ if (write) begin
+ case (addr)
+ HXAUI_CSR_RESET_ADDR:
+ hxaui_csr_reset = writedata[1:0];
+ HXAUI_CSR_RX_CNTRL_ADDR:
+ hxaui_csr_rx_cntrl = writedata[3:0];
+ HXAUI_CSR_TX_CNTRL_ADDR:
+ hxaui_csr_tx_cntrl = writedata[3:0];
+ HXAUI_CSR_SIMULATION_FLAG_ADDR:
+ hxaui_csr_simulation_flag = writedata[0];
+ default:;
+ endcase // case (addr)
+ end
+end
+
+assign {r_rx_digitalreset, r_tx_digitalreset} = hxaui_csr_reset0q[1:0];
+assign r_rx_invpolarity[3:0] = hxaui_csr_rx_cntrl0q[3:0];
+assign r_tx_invpolarity[3:0] = hxaui_csr_tx_cntrl0q[3:0];
+assign simulation_flag = hxaui_csr_simulation_flag0q;
+
+//--- rx_status_0 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ rx_patterndetect_c <= rx_patterndetect;
+ rx_syncstatus_c <= rx_syncstatus;
+end
+
+assign read_rx_status_0 = read && (addr == HXAUI_CSR_RX_STATUS_0_ADDR);
+
+// sticky bits implementation -
+// set: status signal
+// reset: read from register
+// Set has precedence over reset
+//
+// s r q nq
+// ------------
+// 0 0 x q
+// 0 1 x 0
+// 1 x x 1
+//
+// nq <= s + qr'
+//
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ rx_patterndetect_sr <= 8'h0;
+ rx_syncstatus_sr <= 8'h0;
+ end else begin
+ rx_patterndetect_sr <= rx_patterndetect_c |
+ (rx_patterndetect_sr & {8{read_rx_status_0}});
+ rx_syncstatus_sr <= rx_syncstatus_c |
+ (rx_syncstatus_sr & {8{read_rx_status_0}});
+ end
+end
+
+assign hxaui_csr_rx_status_0 = {rx_patterndetect_sr, rx_syncstatus_sr};
+
+//--- rx_status_1 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ rx_errdetect_c <= rx_errdetect;
+ rx_disperr_c <= rx_disperr;
+end
+
+assign read_rx_status_1 = read && (addr == HXAUI_CSR_RX_STATUS_1_ADDR);
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ rx_errdetect_sr <= 8'h0;
+ rx_disperr_sr <= 8'h0;
+ end else begin
+ rx_errdetect_sr <= rx_errdetect_c |
+ (rx_errdetect_sr & {8{read_rx_status_1}});
+ rx_disperr_sr <= rx_disperr_c |
+ (rx_disperr_sr & {8{read_rx_status_1}});
+ end
+end
+
+assign hxaui_csr_rx_status_1 = {rx_errdetect_sr, rx_disperr_sr};
+
+//--- rx_status_2 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ rx_phase_comp_fifo_error_c <= rx_phase_comp_fifo_error;
+ rx_rlv_c <= rx_rlv;
+end
+
+assign read_rx_status_2 = read && (addr == HXAUI_CSR_RX_STATUS_2_ADDR);
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ rx_phase_comp_fifo_error_sr <= 4'h0;
+ rx_rlv_sr <= 4'h0;
+ end else begin
+ rx_phase_comp_fifo_error_sr <= rx_phase_comp_fifo_error_c |
+ (rx_phase_comp_fifo_error_sr & {4{read_rx_status_2}});
+ rx_rlv_sr <= rx_rlv_c |
+ (rx_rlv_sr & {4{read_rx_status_2}});
+ end
+end
+
+assign hxaui_csr_rx_status_2 = {rx_phase_comp_fifo_error_sr, rx_rlv_sr};
+
+//--- rx_status_3 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ rx_rmfifodatainserted_c <= rx_rmfifodatainserted;
+ rx_rmfifodatadeleted_c <= rx_rmfifodatadeleted;
+end
+
+assign read_rx_status_3 = read && (addr == HXAUI_CSR_RX_STATUS_3_ADDR);
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ rx_rmfifodatainserted_sr <= 8'h0;
+ rx_rmfifodatadeleted_sr <= 8'h0;
+ end else begin
+ rx_rmfifodatainserted_sr <= rx_rmfifodatainserted_c |
+ (rx_rmfifodatainserted_sr & {8{read_rx_status_3}});
+ rx_rmfifodatadeleted_sr <= rx_rmfifodatadeleted_c |
+ (rx_rmfifodatadeleted_sr & {8{read_rx_status_3}});
+ end
+end
+
+assign hxaui_csr_rx_status_3 = {rx_rmfifodatainserted_sr,
+ rx_rmfifodatadeleted_sr};
+
+//--- rx_status_4 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ rx_rmfifoempty_c <= rx_rmfifoempty;
+ rx_rmfifofull_c <= rx_rmfifofull;
+end
+
+assign read_rx_status_4 = read && (addr == HXAUI_CSR_RX_STATUS_4_ADDR);
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ rx_rmfifoempty_sr <= 4'h0;
+ rx_rmfifofull_sr <= 4'h0;
+ end else begin
+ rx_rmfifoempty_sr <= rx_rmfifoempty_c |
+ (rx_rmfifoempty_sr & {4{read_rx_status_4}});
+ rx_rmfifofull_sr <= rx_rmfifofull_c |
+ (rx_rmfifofull_sr & {4{read_rx_status_4}});
+ end
+end
+
+assign hxaui_csr_rx_status_4 = {rx_rmfifoempty_sr, rx_rmfifofull_sr};
+
+//--- tx_status_0 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ tx_phase_comp_fifo_error_c <= tx_phase_comp_fifo_error;
+end
+
+assign read_tx_status_0 = read && (addr == HXAUI_CSR_TX_STATUS_0_ADDR);
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ tx_phase_comp_fifo_error_sr <= 4'h0;
+ end else begin
+ tx_phase_comp_fifo_error_sr <= tx_phase_comp_fifo_error_c |
+ (tx_phase_comp_fifo_error_sr & {4{read_tx_status_0}});
+ end
+end
+
+assign hxaui_csr_tx_status_0 = tx_phase_comp_fifo_error_sr;
+
+
+endmodule // hxaui_csr
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/hxaui_csr_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/hxaui_csr_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..b4856c0cf54dc1a394a545937fa14fa28b03a1ce
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/hxaui_csr_h.sv
@@ -0,0 +1,155 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// (C) 2001-2011 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+///////////////////////////////////////////////////////////////////////////////
+//
+//
+// Description: Hard xaui control and status registers header file
+//
+// Authors: ishimony 12-Jun-2009
+//
+// Copyright (c) Altera Corporation 1997 - 2009
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+`timescale 1 ps / 1 ps
+
+package hxaui_csr_h;
+
+
+// address map
+localparam [11:0]ALT_PMA_CONTROLLER_ADDR =12'h080;
+localparam [11:0]ALT_PMA_CH_CONTROLLER_ADDR =12'h180;
+//localparam ALT_PMA_ADDR 12'h080
+localparam [11:0]ALT_RECONFIG_ANALOG_ADDR =12'h400;
+localparam [11:0]ALT_RECONFIG_OC_ADDR =12'h408;
+localparam [11:0]HXAUI_CSR_ADDR =12'h200;
+
+
+// registers address -------------------------------------------------------
+// preserve 7'h00 for indirection register (future implementation)
+localparam [6:0]HXAUI_CSR_RESET_ADDR =7'h04;
+localparam [6:0]HXAUI_CSR_RX_CNTRL_ADDR =7'h08;
+localparam [6:0]HXAUI_CSR_TX_CNTRL_ADDR =7'h0C;
+localparam [6:0]HXAUI_CSR_RX_STATUS_0_ADDR =7'h10;
+localparam [6:0]HXAUI_CSR_RX_STATUS_1_ADDR =7'h14;
+localparam [6:0]HXAUI_CSR_RX_STATUS_2_ADDR =7'h18;
+localparam [6:0]HXAUI_CSR_RX_STATUS_3_ADDR =7'h1C;
+localparam [6:0]HXAUI_CSR_RX_STATUS_4_ADDR =7'h20;
+localparam [6:0]HXAUI_CSR_TX_STATUS_0_ADDR =7'h24;
+localparam [6:0]HXAUI_CSR_SIMULATION_FLAG_ADDR =7'h28;
+
+// register bitmap ---------------------------------------------------------
+localparam [32:0]HXAUI_CSR_RESET_RX_DIGITAL =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RESET_TX_DIGITAL =32'h0000_0002;
+
+localparam [32:0]HXAUI_CSR_RX_CNTRL_INVPOLARITY_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_CNTRL_INVPOLARITY_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_CNTRL_INVPOLARITY_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_CNTRL_INVPOLARITY_3 =32'h0000_0008;
+
+localparam [32:0]HXAUI_CSR_TX_CNTRL_INVPOLARITY_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_TX_CNTRL_INVPOLARITY_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_TX_CNTRL_INVPOLARITY_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_TX_CNTRL_INVPOLARITY_3 =32'h0000_0008;
+
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_3 =32'h0000_0008;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_4 =32'h0000_0010;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_5 =32'h0000_0020;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_6 =32'h0000_0040;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_7 =32'h0000_0080;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_0 =32'h0000_0100;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_1 =32'h0000_0200;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_2 =32'h0000_0400;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_3 =32'h0000_0800;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_4 =32'h0000_1000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_5 =32'h0000_2000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_6 =32'h0000_4000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_7 =32'h0000_8000;
+
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_3 =32'h0000_0008;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_4 =32'h0000_0010;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_5 =32'h0000_0020;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_6 =32'h0000_0040;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_7 =32'h0000_0080;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_0 =32'h0000_0100;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_1 =32'h0000_0200;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_2 =32'h0000_0400;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_3 =32'h0000_0800;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_4 =32'h0000_1000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_5 =32'h0000_2000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_6 =32'h0000_4000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_7 =32'h0000_8000;
+
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_RLV_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_RLV_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_RLV_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_RLV_3 =32'h0000_0008;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_PHASE_COMP_FIFO_ERROR_0 =32'h0000_0010;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_PHASE_COMP_FIFO_ERROR_1 =32'h0000_0020;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_PHASE_COMP_FIFO_ERROR_2 =32'h0000_0040;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_PHASE_COMP_FIFO_ERROR_3 =32'h0000_0080;
+
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_3 =32'h0000_0008;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_4 =32'h0000_0010;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_5 =32'h0000_0020;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_6 =32'h0000_0040;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_7 =32'h0000_0080;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_0 =32'h0000_0100;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_1 =32'h0000_0200;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_2 =32'h0000_0400;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_3 =32'h0000_0800;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_4 =32'h0000_1000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_5 =32'h0000_2000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_6 =32'h0000_4000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_7 =32'h0000_8000;
+
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOFULL_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOFULL_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOFULL_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOFULL_3 =32'h0000_0008;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOEMPTY_0 =32'h0000_0010;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOEMPTY_1 =32'h0000_0020;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOEMPTY_2 =32'h0000_0040;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOEMPTY_3 =32'h0000_0080;
+
+localparam [32:0]HXAUI_CSR_TX_STATUS_0_PHASE_COMP_FIFO_ERROR_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_TX_STATUS_0_PHASE_COMP_FIFO_ERROR_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_TX_STATUS_0_PHASE_COMP_FIFO_ERROR_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_TX_STATUS_0_PHASE_COMP_FIFO_ERROR_3 =32'h0000_0008;
+
+localparam [32:0]HXAUI_CSR_SIMULATION_FLAG =32'h0000_0001;
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_dprio.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_dprio.v
new file mode 100644
index 0000000000000000000000000000000000000000..72342c0350fe6cec94b878f3a747c230666430ee
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_dprio.v
@@ -0,0 +1,210 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_mutex_acq.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_mutex_acq.v
new file mode 100644
index 0000000000000000000000000000000000000000..724b5ba53e2106feb9ab923b2df6e714d830fc91
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_mutex_acq.v
@@ -0,0 +1,193 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 7520)
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+IQgN6YkosNlQmTcoDe3AWjcUwL4Um7Q3+3VTlRCMR8w=
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_pma_ch_controller_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_pma_ch_controller_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..f22b03e4b0b361896c232091a7ab96b3b8920a72
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_pma_ch_controller_tgx.v
@@ -0,0 +1,184 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 7072)
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+w+ld+hrZn5KDlwOAfwc86w==
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_pma_controller_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_pma_controller_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..5760024984a14c31d24e078458bdc5aa1f898cbe
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_pma_controller_tgx.v
@@ -0,0 +1,151 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 5488)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_reset_ctrl_lego.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_reset_ctrl_lego.sv
new file mode 100644
index 0000000000000000000000000000000000000000..65b81465e061b87494a14045dc11a9a8eea218f6
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_reset_ctrl_lego.sv
@@ -0,0 +1,249 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_reset_ctrl_tgx_cdrauto.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_reset_ctrl_tgx_cdrauto.sv
new file mode 100644
index 0000000000000000000000000000000000000000..00a639830a0bb4222b123eef29eef247c1c99ebd
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_reset_ctrl_tgx_cdrauto.sv
@@ -0,0 +1,245 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 10032)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_arbiter.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_arbiter.sv
new file mode 100644
index 0000000000000000000000000000000000000000..9201fe9392a1f83a96bded3635bdcecbf1c3cc31
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_arbiter.sv
@@ -0,0 +1,100 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+00Re0NHMdK06PlP+94zS3uLQr1Ofr0PoWzK8LhRxtCc=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 3056)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_common.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_common.sv
new file mode 100644
index 0000000000000000000000000000000000000000..05d47a63ff795a780953a7207b4cd30623e546a1
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_common.sv
@@ -0,0 +1,244 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 9984)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_common_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_common_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..6c497c12da003abbeaacd57513e9aff063cbe2ea
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_common_h.sv
@@ -0,0 +1,108 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+TOWgEh7Q0ry2M5e2DMIblPJfQNlm8NM1EHMNgV/rtWM=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 3424)
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+W4DVx5ruiC47L9RN0oSqeQ==
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_pcs8g.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_pcs8g.sv
new file mode 100644
index 0000000000000000000000000000000000000000..de318f36893e8a7e31873670221476b68c5faed7
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_pcs8g.sv
@@ -0,0 +1,410 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 17952)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_pcs8g_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_pcs8g_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..d1ec34e1c710d34265ab9b98577b6f3f498c0cc5
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_pcs8g_h.sv
@@ -0,0 +1,76 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+FdI/HIJng41AFhkct+wjpUFz+wmpC/3EdHZZzPUP+nQ=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 1920)
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+899qyXiX6Pa4WBo2v+IG+Gix0Ys8hbbfFBRMWRsH7Zad/67ygyMdlYds3YkJE/ez
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+GiZqz2Spxk9oi0TZXSKPEan+aOW6Cics2Wvjm12oVHFgcvH/elqkI3BmcnSEC7Ia
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_selector.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_selector.sv
new file mode 100644
index 0000000000000000000000000000000000000000..801b179409a7cbbdf6cad6c84fadcfaff3a6c41c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_selector.sv
@@ -0,0 +1,131 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+IAPQvGS2WEQvamIfKh4zuSYeYfJ+NmmR23TMuspMGcjny+aZb4gLlECCuBo5Xd7j
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+8cWLA40AHzbLMzNX3PnyyyYLRZUJHUVPGGQDK288CtI=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 4544)
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+HOZjIbPnkEBDWs9ZEZUKrEvQPKmTDZaaxFatmEK2+jc=
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_m2s.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_m2s.sv
new file mode 100644
index 0000000000000000000000000000000000000000..6fbcca4dbd02d0124af931a01c68765c9fe60ba9
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_m2s.sv
@@ -0,0 +1,90 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+HS+I8naY9DPGVQxPrII2Frh1VJghpPubC5j5F0w2tZKpYlOfA9o38NqMkGQvPRYb
+ixx79iSmdoLQVAlfKvGITv++cqXK8yAHwZm2NwuCEOeEMw5LYL/hbU8LJB6+Ckv9
+Smz71GMpWXutaeBQTP3kCIKoCml/V7N7Z/k/VCdY0lg=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 2592)
+5r/HMrfpfAS3xARr91zeCBVm/Wg9g3j7Raz2VOHJb217xDWTkdu5vZR054h/UyTO
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+iDgazn1HrvrsnvccMo9FRJm7jmQycvGFtXczDfOHUdwfsjo8NfHeKoAVtCpGnJEt
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec.sv
new file mode 100644
index 0000000000000000000000000000000000000000..708f65dd161bd7db8620762a6f22c0aa9e2a3ab1
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec.sv
@@ -0,0 +1,122 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+m3n1EU+tPJ6e1Bo0jc/upKK4zeA4L/m/zhi0BBbmE18=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 4112)
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+CPTSgMbDPK6EBbGuS57DJfprBMzWSJWDYNWH38jj6g8=
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec_phyreconfig.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec_phyreconfig.sv
new file mode 100644
index 0000000000000000000000000000000000000000..d6e371c82c763fbe90f5485fd1aae9abf8d49b07
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec_phyreconfig.sv
@@ -0,0 +1,141 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 5024)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec_xaui.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec_xaui.sv
new file mode 100644
index 0000000000000000000000000000000000000000..4bcb992c45e33b9053483c24b99e6e61338c37c6
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec_xaui.sv
@@ -0,0 +1,167 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 6256)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_analog.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_analog.sv
new file mode 100644
index 0000000000000000000000000000000000000000..2309672b77ddf40b1462ae30705167bbd20aa885
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_analog.sv
@@ -0,0 +1,185 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 7136)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_analog_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_analog_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..e586ed1dd708be01feb654b2d017ce915dbaded8
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_analog_tgx.v
@@ -0,0 +1,795 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 36432)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_basic_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_basic_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..c8025cdc92b5ddad3fe624f477ad4a8466f90142
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_basic_tgx.v
@@ -0,0 +1,375 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 16240)
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+b7RxtNIMCTZt6Vg7HQ8p+g==
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_dfe_tgx.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_dfe_tgx.sv
new file mode 100644
index 0000000000000000000000000000000000000000..4931754e1edddd25d71e21e04fc484b42ab66de9
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_dfe_tgx.sv
@@ -0,0 +1,386 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+SqfVDrFG6yrlTOdcDIIXNUV1sqZqyoSUkbmI1rn83Uo=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 16800)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_eyemon_tgx.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_eyemon_tgx.sv
new file mode 100644
index 0000000000000000000000000000000000000000..694a5541e8a54d5afd1a0a675e127d8547df47c2
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_eyemon_tgx.sv
@@ -0,0 +1,395 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 17216)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..22240cbc9f16d013a29b1a9607b2afe16b218fe2
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_h.sv
@@ -0,0 +1,427 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 18768)
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+mJ/fB0i5fMvz4NVk2Mr8wu2Z47vu+QE6ybpnwf47jT3cphd+a5ucVHSXVhZ5zp5x
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_offset_cancellation.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_offset_cancellation.sv
new file mode 100644
index 0000000000000000000000000000000000000000..0e1898bbb251fd03e589fde44d76c3ff4645985e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_offset_cancellation.sv
@@ -0,0 +1,214 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 8528)
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+tClSSjNKRkyGJGLwb0cdEKwZBXsKopwaWGcZhUXuwCE=
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_offset_cancellation_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_offset_cancellation_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..fe29ab815570c89edf71a3e5a9616e4f34bcda21
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_offset_cancellation_tgx.v
@@ -0,0 +1,452 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 19968)
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+jh6w2tkAGWgZXZXSVi5JJip3AMtnI3cdkxwaEIDEDe1fO7Sj/v3mHIYv2ky2vFVA
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_siv.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_siv.sv
new file mode 100644
index 0000000000000000000000000000000000000000..b458a1f9ed061719de8ae09f3183d825ad0cbfd8
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_siv.sv
@@ -0,0 +1,388 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+Sme+DdEA8vUR0C9Y13VZfsPzHqxIPHiKpzqfoF4Zg1s=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 16880)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_resync.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_resync.sv
new file mode 100644
index 0000000000000000000000000000000000000000..b1e6c11c30214d200e1e3e3c547f9f71b640545d
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/alt_xcvr_resync.sv
@@ -0,0 +1,125 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 4240)
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+tSg1lSaQ+syFuRnZmV+p7d9uAFz5EUYNmb1PkVNsAWdVok8eR9I3FwC9oXbI7gMO
+s6MQ1LfJMuSirDjuRbO6iiTngFtg3IvVG4o8O1F4z3azC9cpuEyumOLGv1ZIdtf1
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+f1mFQ9GDW+GQP8A+54vFKRjUCf/UYM2CUfXWcBTO14Phk0MMUG3BY2DvIrPah2d+
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+K7fcKFVqylEaw5PEizuX8A==
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/altera_wait_generate.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/altera_wait_generate.v
new file mode 100644
index 0000000000000000000000000000000000000000..ef008094f669832fc7edb6f42638490009bac90d
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/altera_wait_generate.v
@@ -0,0 +1,76 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+NTatKXD2vaAi56tZ5DimfYyEBW+JNwsK30ioUF5+LXwIzabb/re9ghIliAm41Kbj
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+Ebf5ievExkme2joWSqIoSRCeN2RIunNQaCIQ1jdUM7A=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 1888)
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++vCKN0rkhBcVPddr9EUQdw==
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/altera_xcvr_functions.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/altera_xcvr_functions.sv
new file mode 100644
index 0000000000000000000000000000000000000000..bb92d08605ea29f7d2b2458456ce2000eb9e6a44
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/altera_xcvr_functions.sv
@@ -0,0 +1,666 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+pRrIJQeGz7EPVbooxqUk8+gHN8vsYnsYQxfwYXc6oQ3OyWm0ShI/K9+U/IAxgVtE
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+nZ1qLsgZjHQCmBZQO3ECvHA7fcd5oe6LXuKiYuNnCyY=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 30240)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/altera_xcvr_xaui.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/altera_xcvr_xaui.sv
new file mode 100644
index 0000000000000000000000000000000000000000..199fefd6d98f060aac8d275e961846eb91c1ace9
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/altera_xcvr_xaui.sv
@@ -0,0 +1,643 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 29136)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/hxaui.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/hxaui.v
new file mode 100644
index 0000000000000000000000000000000000000000..6c5f23dad7e673fd3984bebb502031442ecc47ba
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/hxaui.v
@@ -0,0 +1,552 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 24768)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/hxaui_alt4gxb.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/hxaui_alt4gxb.v
new file mode 100644
index 0000000000000000000000000000000000000000..b57f027a22c51eb2b36b1f18f9f7d26381a41319
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/hxaui_alt4gxb.v
@@ -0,0 +1,3651 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+zkhkDZwVGCfCdMWIXI5hHZb4zwmImo6ba29bVxfDsC4=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 173488)
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+8Nh7ss29tJtogpZTkw7V3Q==
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/hxaui_csr.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/hxaui_csr.sv
new file mode 100644
index 0000000000000000000000000000000000000000..691fc06c19c7976aec73e754c81780de616faafe
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/hxaui_csr.sv
@@ -0,0 +1,353 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+8nymk6WmKIb3qNlUoGaqdtbjMaHliFW+uo8WahUFRE8=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 15200)
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+A2u8eMgaHLgP2n1XETE9f4D916oMGE+ylT3IXM552XY=
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/hxaui_csr_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/hxaui_csr_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..03d1dfb48ea29b6a691b63e7caa467a92364ef9e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/hxaui_csr_h.sv
@@ -0,0 +1,238 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+h2LSz/En+HRA39DsjKt3KBzDqdoJr+MS4bf1BH/kAdc=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 9664)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/siv_xcvr_xaui.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/siv_xcvr_xaui.sv
new file mode 100644
index 0000000000000000000000000000000000000000..283b5136ac768134fe20afe4e80f18be4a1785bc
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor/siv_xcvr_xaui.sv
@@ -0,0 +1,706 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 32144)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor_files.txt b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor_files.txt
new file mode 100644
index 0000000000000000000000000000000000000000..01050d7710cc87175e4be0cf4227f05ab6f83554
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/mentor_files.txt
@@ -0,0 +1,34 @@
+./mentor/altera_xcvr_functions.sv
+./mentor/altera_xcvr_xaui.sv
+./mentor/hxaui_csr_h.sv
+./mentor/hxaui_csr.sv
+./mentor/alt_xcvr_mgmt2dec_phyreconfig.sv
+./mentor/alt_xcvr_mgmt2dec_xaui.sv
+./mentor/alt_pma_ch_controller_tgx.v
+./mentor/alt_pma_controller_tgx.v
+./mentor/alt_reset_ctrl_lego.sv
+./mentor/alt_reset_ctrl_tgx_cdrauto.sv
+./mentor/alt_xcvr_resync.sv
+./mentor/alt_xcvr_csr_common_h.sv
+./mentor/alt_xcvr_csr_common.sv
+./mentor/alt_xcvr_csr_pcs8g_h.sv
+./mentor/alt_xcvr_csr_pcs8g.sv
+./mentor/alt_xcvr_csr_selector.sv
+./mentor/alt_xcvr_mgmt2dec.sv
+./mentor/altera_wait_generate.v
+./mentor/hxaui_alt4gxb.v
+./mentor/hxaui.v
+./mentor/siv_xcvr_xaui.sv
+./mentor/alt_xcvr_reconfig_h.sv
+./mentor/alt_xcvr_reconfig_siv.sv
+./mentor/alt_xcvr_reconfig_analog.sv
+./mentor/alt_xcvr_reconfig_analog_tgx.v
+./mentor/alt_xcvr_reconfig_offset_cancellation.sv
+./mentor/alt_xcvr_reconfig_offset_cancellation_tgx.v
+./mentor/alt_xcvr_reconfig_eyemon_tgx.sv
+./mentor/alt_xcvr_reconfig_dfe_tgx.sv
+./mentor/alt_xcvr_reconfig_basic_tgx.v
+./mentor/alt_mutex_acq.v
+./mentor/alt_dprio.v
+./mentor/alt_xcvr_arbiter.sv
+./mentor/alt_xcvr_m2s.sv
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/modelsim_sim_script_example.tcl b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/modelsim_sim_script_example.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..64f09857ea3ab03830ff65cce67d58db4b3c3eed
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/modelsim_sim_script_example.tcl
@@ -0,0 +1,380 @@
+# (C) 2001-2012 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and other
+# software and tools, and its AMPP partner logic functions, and any output
+# files any of the foregoing (including device programming or simulation
+# files), and any associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License Subscription
+# Agreement, Altera MegaCore Function License Agreement, or other applicable
+# license agreement, including, without limitation, that your use is for the
+# sole purpose of programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+
+###########################################
+#
+# This is an example file for compilation/simulation of 10GBASER-R PHY instance in Modelsim
+#
+# You can modify this script and use it to compile/simulate your design depending on
+# the following Modelsim license options:
+# (1) Mixed language license
+# - Top-level PHY IP variant can be in Verilog or VHDL
+# - Underlying PHY IP files are in plaintext Verilog
+# - Testbench can be in Verilog or VHDL
+#
+# (2) Non-mixed language license
+# (a) Verilog Only:
+# - Top-level PHY IP variant should be in Verilog
+# - Underlying PHY IP files are in plaintext Verilog
+# - Testbench should be in Verilog
+#
+# (b) VHDL Only:
+# - Top-level PHY IP variant should be in VHDL
+# - Underlying PHY IP files are in encrypted Verilog
+# - Testbench should be in VHDL
+#
+# (3) Quartus encrypted some files for copyright. Those file will be encrypted for different simulator
+#
+# Please do the following changes in this script in order to use it:
+# - Set the language (verilog or vhdl) of the generated PHY IP variant
+# - Set your top-level PHY IP variant name
+# - Set your top-level testbench name
+# - Compile your other design files and your testbench. You would use vlog or vcom according
+# to the language of your design files/testbench and your Modelsim license.
+#
+# Note that the PHY IP files are correctly compiled in this script according to the the
+# "language" variable you set.
+#
+##############################################################################################
+
+set QUARTUS_ROOTDIR $env(QUARTUS_ROOTDIR)
+#################################################################################
+##
+## Set your language, simulator and top level design name here
+## e.g. vsim -c -do "do ./test_sim/modelsim_example_script.tcl verilog stratixiv modelsim test test_tst hard"
+##
+#################################################################################
+# language = verilog (verilog variant of the PHY IP) or vhdl (vhdl variant of the PHY IP)
+# defaulted to verilog
+set language $1
+if {$language != "verilog" && $language != "vhdl"} {
+ echo "invalid setting for language: $language. valid settings are verilog and vhdl"
+ exit
+}
+
+# family =
+# defaulted to stratixv
+set family $2
+if {$family != "stratixiv" && $family != "stratixv" && $family != "cycloneiv" && $family != "arriaiigx" && $family != "arriaiigz" && $family != "hardcopyiv"} {
+ echo "invalid setting for family: $family. valid settings are stratixiv,stratixv,cycloneiv,arriaiigx,arriaiigz,hardcopyiv"
+ exit
+}
+
+# simulator = modelsim or VCS
+# defaulted to modelsim
+# This file not support VCS yet, you can use this file as reference for VCS
+set simulator $3
+if {$simulator != "modelsim"} {
+ echo "invalid setting for simulator: $simulator. valid settings are modelsim"
+ exit
+}
+## Set your top level design name here
+##set dut_name <top level design name as generted in Quartus or Qsys>
+set dut_name $4
+if {$dut_name == ""} {
+ echo "Missing top level design name: $dut_name"
+}
+## Set your test bench name here
+##set tb_name <test bench>
+set tb_name $5
+if {$tb_name == ""} {
+ echo "Missing test bench name: $tb_name"
+}
+
+## Set your XAUI type
+##set xaui_type soft or hard
+set xaui_type $6
+if {$xaui_type == ""} {
+ echo "Missing test xaui_type: $xaui_type"
+}
+
+puts " simulator=$simulator"
+puts " language=$language"
+puts " family=$family"
+#################################################################################
+## Set directory path according to simulator
+## unenc_file_dir for Quartus unecrypted files
+## enc_file_dir is for Quartus ecrypted files
+## This file only support modelsim simulation. You can use the following path
+## as reference of other simulator
+#################################################################################
+## Modelsim Verilog/Modelsim VHDL with Mixed language license
+if { $simulator == "modelsim" } {
+ set enc_file_dir ./${dut_name}_sim/altera_xcvr_xaui/mentor
+ if {$language == "verilog"} {
+ set unenc_file_dir ./${dut_name}_sim/altera_xcvr_xaui
+ } else {
+ ## Modelsim-AE / Models
+ set unenc_file_dir ./${dut_name}_sim/altera_xcvr_xaui/mentor
+ }
+
+} elseif { $simulator == "VCS" } {
+ set unenc_file_dir ${dut_name}_sim
+ set enc_file_dir $dut_name_sim/synopsys
+
+} elseif { $simulator == "Aldec" } {
+ set unenc_file_dir ${dut_name}_sim
+ set enc_file_dir $dut_name_sim/Aldec
+
+} elseif { $simulator == "VCS" } {
+ set unenc_file_dir ./${dut_name}_sim
+ set enc_file_dir ./${dut_name}_sim/synopsys
+
+} elseif { $simulator == "NCSIM" } {
+ set unenc_file_dir ./${dut_name}_sim
+ set enc_file_dir ./${dut_name}_sim/cadence
+
+}
+
+exec rm -rf work
+vlib work
+puts " unenc_file_dir=$unenc_file_dir"
+puts " enc_file_dir=$enc_file_dir"
+
+###########################################
+# Library files
+###########################################
+if {$language == "verilog"} {
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/220model.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/altera_primitives.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/sgate.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/altera_mf.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/stratixiv_hssi_atoms.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/stratixii_atoms.v
+
+ if {$family == "stratixiv" || $family == "arriaiigx" || $family == "arriaiigz" || $family == "hardcopyiv"} {
+ ###########################################
+ # Stratix IV library files
+ ###########################################
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/stratixiv_hssi_atoms.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/stratixiv_atoms.v
+ vlog $QUARTUS_ROOTDIR/libraries/megafunctions/alt_cal_c3gxb.v
+ }
+ if {$family == "cycloneiv"} {
+ ###########################################
+ # Cyclone IV library files
+ ###########################################
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/cycloneiv_hssi_atoms.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/cycloneiv_atoms.v
+ vlog $QUARTUS_ROOTDIR/libraries/megafunctions/alt_cal_c3gxb.v
+ }
+ if {$family == "stratixv"} {
+ ###########################################
+ # Stratix V library files
+ ###########################################
+ vlog -sv $QUARTUS_ROOTDIR/eda/sim_lib/altera_lnsim.sv
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/mentor/stratixv_atoms_ncrypt.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/stratixv_atoms.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/mentor/stratixv_hssi_atoms_ncrypt.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/stratixv_hssi_atoms.v
+ }
+} else {
+ vmap altera work
+ vmap altera_mf work
+ vmap lpm work
+ vmap sgate work
+ vmap stratixiv_hssi work
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/220pack.vhd
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/220model.vhd
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/altera_primitives_components.vhd
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/altera_primitives.vhd
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/sgate_pack.vhd
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/sgate.vhd
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/altera_mf_components.vhd
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/altera_mf.vhd
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/stratixii_atoms.vhd
+
+ if {$family == "stratixiv" || $family == "arriaiigx" || $family == "arriaiigz"} {
+ ###########################################
+ # Stratix IV library files
+ ###########################################
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/stratixiv_hssi_components.vhd
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/stratixiv_hssi_atoms.vhd
+ vcom $QUARTUS_ROOTDIR/libraries/megafunctions/alt_cal_c3gxb.vhd
+ }
+ if {$family == "cycloneiv"} {
+ ###########################################
+ # Cyclone IV library files
+ ###########################################
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/cycloneiv_hssi_components.vhd
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/cycloneiv_hssi_atoms.vhd
+ vcom $QUARTUS_ROOTDIR/libraries/megafunctions/alt_cal_c3gxb.vhd
+ }
+ if {$family == "stratixv"} {
+ ###########################################
+ # Stratix V library files
+ ###########################################
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/mentor/stratixv_atoms_for_vhdl.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/mentor/stratixv_hssi_atoms_for_vhdl.v
+ }
+}
+
+if {$xaui_type == "hard" } {
+ vlog -sv $unenc_file_dir/alt_xcvr_csr_common_h.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_csr_common.sv
+ vlog $unenc_file_dir/alt_dprio.v
+ vlog $unenc_file_dir/alt_mutex_acq.v
+ vlog $unenc_file_dir/alt_pma_ch_controller_tgx.v
+ vlog $unenc_file_dir/alt_pma_controller_tgx.v
+ vlog -sv $unenc_file_dir/altera_xcvr_functions.sv
+ vlog -sv $unenc_file_dir/alt_reset_ctrl_lego.sv
+ vlog -sv $unenc_file_dir/alt_reset_ctrl_tgx_cdrauto.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_resync.sv
+ vlog -sv $unenc_file_dir/altera_xcvr_xaui.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_arbiter.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_m2s.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_mgmt2dec_phyreconfig.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_mgmt2dec_xaui.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_csr_pcs8g_h.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_csr_pcs8g.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_csr_selector.sv
+ vlog $unenc_file_dir/altera_wait_generate.v
+ vlog $unenc_file_dir/hxaui.v
+ vlog $unenc_file_dir/hxaui_csr_h.sv
+ vlog +incdir+$unenc_file_dir $unenc_file_dir/hxaui_csr.sv
+ if {$family == "stratixiv" || $family == "arriaiigx" || $family == "arriaiigz" || $family == "hardcopyiv"} {
+ ###########################################
+ # Use this section for Stratix IV/Arria II GX Hard XAUI
+ ###########################################
+ vlog -sv $unenc_file_dir/siv_xcvr_xaui.sv
+ vlog $unenc_file_dir/alt_dprio.v
+ vlog $unenc_file_dir/alt_xcvr_reconfig*.v
+ vlog -sv $unenc_file_dir/alt_xcvr_reconfig*.sv
+ vlog $unenc_file_dir/hxaui_alt4gxb.v
+ }
+ if {$family == "cycloneiv"} {
+ ###########################################
+ # Use this section for Cyclone IV GX Hard XAUI
+ ###########################################
+ vlog $unenc_file_dir/civ_xcvr_xaui.v
+ vlog $unenc_file_dir/alt_xcvr_reconfig*.v
+ vlog -sv $unenc_file_dir/alt_xcvr_reconfig*.sv
+ vlog $unenc_file_dir/hxaui_alt_c3gxb.v
+ }
+ } else {
+ vlog -sv $unenc_file_dir/alt_xcvr_csr_common_h.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_csr_common.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_csr_pcs8g_h.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_csr_pcs8g.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_csr_selector.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_m2s.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_mgmt2dec_phyreconfig.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_mgmt2dec_xaui.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_arbiter.sv
+ vlog -sv $unenc_file_dir/altera_xcvr_functions.sv
+ vlog $enc_file_dir/alt_soft_xaui_pcs.v
+ vlog $enc_file_dir/alt_soft_xaui_reset.v
+ vlog $enc_file_dir/alt_soft_xaui_rx.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_8b10b_dec.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_channel_synch.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_deskew.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_deskew_channel.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_deskew_ram.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_invalid_code_det.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_parity.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_parity_4b.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_parity_6b.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_rate_match.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_rate_match_ram.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_rl_chk_6g.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_sm.v
+ vlog $enc_file_dir/alt_soft_xaui_tx.v
+ vlog $enc_file_dir/alt_soft_xaui_tx_8b10b_enc.v
+ vlog $enc_file_dir/alt_soft_xaui_tx_idle_conv.v
+ vlog $enc_file_dir/l_modules.v
+ vlog $unenc_file_dir/hxaui_csr_h.sv
+ vlog +incdir+$unenc_file_dir $unenc_file_dir/hxaui_csr.sv
+ vlog $unenc_file_dir/sxaui.v
+ vlog -sv $unenc_file_dir/alt_reset_ctrl_lego.sv
+ vlog $unenc_file_dir/altera_wait_generate.v
+ vlog -sv $unenc_file_dir/altera_xcvr_xaui.sv
+ vlog -sv $unenc_file_dir/alt_reset_ctrl_tgx_cdrauto.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_resync.sv
+ if {$family == "stratixiv" } {
+ ###########################################
+ # Use this section for Stratix IV Soft XAUI
+ ###########################################
+ vlog -sv $unenc_file_dir/siv_xcvr_xaui.sv
+ vlog $unenc_file_dir/alt4gxb_vo.v
+ vlog $unenc_file_dir/alt_mutex_acq.v
+ vlog $unenc_file_dir/alt_pma_ch_controller_tgx.v
+ vlog $unenc_file_dir/alt_pma_controller_tgx.v
+ vlog -sv $unenc_file_dir/alt_pma_functions.sv
+ vlog -sv $unenc_file_dir/siv_xcvr_low_latency_phy_nr.sv
+ vlog $unenc_file_dir/alt_dprio.v
+ vlog $unenc_file_dir/alt_xcvr_reconfig*.v
+ vlog -sv $unenc_file_dir/alt_xcvr_reconfig*.sv
+ } else {
+
+ ###########################################
+ # Use this section for Stratix V Soft XAUI
+ ###########################################
+
+ vlog -sv $unenc_file_dir/sv_xcvr_h.sv
+ vlog -sv $unenc_file_dir/sv_xcvr_xaui.sv
+ vlog -sv $unenc_file_dir/sv_xcvr_plls.sv
+ vlog $unenc_file_dir/alt_pma_ch_controller_tgx.v
+ vlog $unenc_file_dir/alt_pma_controller_tgx.v
+ vlog -sv $unenc_file_dir/alt_pma_functions.sv
+ vlog -sv $unenc_file_dir/sv_xcvr_low_latency_phy_nr.sv
+ vlog -sv $unenc_file_dir/sv_xcvr_avmm.sv
+ vlog -sv $unenc_file_dir/sv_xcvr_avmm_csr.sv
+ vlog -sv $unenc_file_dir/sv_xcvr_avmm_dcd.sv
+ vlog -sv $unenc_file_dir/sv_xcvr_custom_native.sv
+ vlog -sv $unenc_file_dir/sv_xcvr_data_adapter.sv
+ vlog -sv $unenc_file_dir/sv_xcvr_native.sv
+ vlog -sv $unenc_file_dir/sv_reconfig_bundle_to_xcvr.sv
+ vlog -sv $unenc_file_dir/sv_reconfig_bundle_merger.sv
+ vlog -sv $unenc_file_dir/sv_reconfig_bundle_to_ip.sv
+ vlog -sv $unenc_file_dir/sv_pcs.sv
+ vlog -sv $unenc_file_dir/sv_pcs_ch.sv
+ vlog -sv $unenc_file_dir/sv_pma.sv
+ vlog -sv $unenc_file_dir/sv_rx_pma.sv
+ vlog -sv $unenc_file_dir/sv_tx_pma.sv
+ vlog -sv $unenc_file_dir/sv_tx_pma_ch.sv
+ vlog -sv $unenc_file_dir/sv_pcs_ch.sv
+ vlog -sv $unenc_file_dir/sv_pcs_ch.sv
+ vlog -sv $unenc_file_dir/stratixv_hssi_8g_rx_pcs_rbc.sv
+ vlog -sv $unenc_file_dir/stratixv_hssi_8g_tx_pcs_rbc.sv
+ vlog -sv $unenc_file_dir/stratixv_hssi_common_pcs_pma_interface_rbc.sv
+ vlog -sv $unenc_file_dir/stratixv_hssi_common_pld_pcs_interface_rbc.sv
+ vlog -sv $unenc_file_dir/stratixv_hssi_rx_pcs_pma_interface_rbc.sv
+ vlog -sv $unenc_file_dir/stratixv_hssi_rx_pld_pcs_interface_rbc.sv
+ vlog -sv $unenc_file_dir/stratixv_hssi_tx_pcs_pma_interface_rbc.sv
+ vlog -sv $unenc_file_dir/stratixv_hssi_tx_pld_pcs_interface_rbc.sv
+ }
+ }
+
+
+#################################################################
+# Add your custom library compilation here and testbench
+#################################################################
+set custom_compilation custom_lib.tcl
+if {[file exists $custom_compilation]} {
+ source $custom_compilation
+}
+
+###########################################
+# Add your test bench here
+###########################################
+vlog ${dut_name}.v
+vsim -c -t 1ps $tb_name -novopt
+
+
+###########################################
+# Run and Quit your simulator
+###########################################
+run -all
+quit -sim
+exit
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/plain_files.txt b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/plain_files.txt
new file mode 100644
index 0000000000000000000000000000000000000000..96175539fe10e847160e3bb13c7980081beae5b3
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/plain_files.txt
@@ -0,0 +1,34 @@
+./altera_xcvr_functions.sv
+./altera_xcvr_xaui.sv
+./hxaui_csr_h.sv
+./hxaui_csr.sv
+./alt_xcvr_mgmt2dec_phyreconfig.sv
+./alt_xcvr_mgmt2dec_xaui.sv
+./alt_pma_ch_controller_tgx.v
+./alt_pma_controller_tgx.v
+./alt_reset_ctrl_lego.sv
+./alt_reset_ctrl_tgx_cdrauto.sv
+./alt_xcvr_resync.sv
+./alt_xcvr_csr_common_h.sv
+./alt_xcvr_csr_common.sv
+./alt_xcvr_csr_pcs8g_h.sv
+./alt_xcvr_csr_pcs8g.sv
+./alt_xcvr_csr_selector.sv
+./alt_xcvr_mgmt2dec.sv
+./altera_wait_generate.v
+./hxaui_alt4gxb.v
+./hxaui.v
+./siv_xcvr_xaui.sv
+./alt_xcvr_reconfig_h.sv
+./alt_xcvr_reconfig_siv.sv
+./alt_xcvr_reconfig_analog.sv
+./alt_xcvr_reconfig_analog_tgx.v
+./alt_xcvr_reconfig_offset_cancellation.sv
+./alt_xcvr_reconfig_offset_cancellation_tgx.v
+./alt_xcvr_reconfig_eyemon_tgx.sv
+./alt_xcvr_reconfig_dfe_tgx.sv
+./alt_xcvr_reconfig_basic_tgx.v
+./alt_mutex_acq.v
+./alt_dprio.v
+./alt_xcvr_arbiter.sv
+./alt_xcvr_m2s.sv
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/sim_script_files.txt b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/sim_script_files.txt
new file mode 100644
index 0000000000000000000000000000000000000000..96175539fe10e847160e3bb13c7980081beae5b3
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/sim_script_files.txt
@@ -0,0 +1,34 @@
+./altera_xcvr_functions.sv
+./altera_xcvr_xaui.sv
+./hxaui_csr_h.sv
+./hxaui_csr.sv
+./alt_xcvr_mgmt2dec_phyreconfig.sv
+./alt_xcvr_mgmt2dec_xaui.sv
+./alt_pma_ch_controller_tgx.v
+./alt_pma_controller_tgx.v
+./alt_reset_ctrl_lego.sv
+./alt_reset_ctrl_tgx_cdrauto.sv
+./alt_xcvr_resync.sv
+./alt_xcvr_csr_common_h.sv
+./alt_xcvr_csr_common.sv
+./alt_xcvr_csr_pcs8g_h.sv
+./alt_xcvr_csr_pcs8g.sv
+./alt_xcvr_csr_selector.sv
+./alt_xcvr_mgmt2dec.sv
+./altera_wait_generate.v
+./hxaui_alt4gxb.v
+./hxaui.v
+./siv_xcvr_xaui.sv
+./alt_xcvr_reconfig_h.sv
+./alt_xcvr_reconfig_siv.sv
+./alt_xcvr_reconfig_analog.sv
+./alt_xcvr_reconfig_analog_tgx.v
+./alt_xcvr_reconfig_offset_cancellation.sv
+./alt_xcvr_reconfig_offset_cancellation_tgx.v
+./alt_xcvr_reconfig_eyemon_tgx.sv
+./alt_xcvr_reconfig_dfe_tgx.sv
+./alt_xcvr_reconfig_basic_tgx.v
+./alt_mutex_acq.v
+./alt_dprio.v
+./alt_xcvr_arbiter.sv
+./alt_xcvr_m2s.sv
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/siv_xcvr_xaui.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/siv_xcvr_xaui.sv
new file mode 100644
index 0000000000000000000000000000000000000000..16ad2c9b0c247529918db040a9c41da5f8639e0c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/siv_xcvr_xaui.sv
@@ -0,0 +1,539 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//-----------------------------------------------------------------------------
+//
+// Description: hxaui static verilog for Stratix IV
+//
+// Authors: bauyeung 7-Sep-2010
+//
+// Copyright (c) Altera Corporation 1997 - 2010
+// All rights reserved.
+//
+//-----------------------------------------------------------------------------
+ /*ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"set_false_path -from [get_registers *hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component*] -to [get_registers *xaui_phy*hxaui_csr*tx_phase_comp_fifo_error_c[*]]\" " */
+
+module siv_xcvr_xaui #(
+ parameter device_family = "Stratix IV",
+ parameter starting_channel_number = 0,
+ parameter interface_type = "Hard XAUI",
+ parameter number_of_interfaces = 1,
+ parameter sys_clk_in_mhz = 50,
+ parameter xaui_pll_type = "CMU",
+ parameter reconfig_interfaces = 1,
+ parameter use_control_and_status_ports = 0,
+ parameter external_pma_ctrl_reconf = 0,
+ parameter tx_termination = "OCT_150_OHMS",
+ parameter tx_vod_selection = 1,
+ parameter tx_preemp_pretap = 0,
+ parameter tx_preemp_pretap_inv = 0,
+ parameter tx_preemp_tap_1 = 5,
+ parameter tx_preemp_tap_2 = 0,
+ parameter tx_preemp_tap_2_inv = 0,
+ parameter rx_common_mode = "0.82v",
+ parameter rx_termination = "OCT_150_OHMS",
+ parameter rx_eq_dc_gain = 0,
+ parameter rx_eq_ctrl = 14
+) (
+ input wire pll_ref_clk, // refclk.clk
+ input wire xgmii_tx_clk, // xgmii_tx_clk.clk
+ output wire xgmii_rx_clk, // xgmii_rx_clk.clk
+ input wire phy_mgmt_clk, // mgmt_clk.clk
+ input wire phy_mgmt_clk_reset, // mgmt_clk_rst.reset_n
+ input wire [7:0] phy_mgmt_address, // phy_mgmt.address
+ output wire phy_mgmt_waitrequest, // .waitrequest
+ input wire phy_mgmt_read, // .read
+ output wire [31:0] phy_mgmt_readdata, // .readdata
+ input wire phy_mgmt_write, // .write
+ input wire [31:0] phy_mgmt_writedata, // .writedata
+ input wire [71:0] xgmii_tx_dc, // xgmii_tx_dc.data
+ output wire [71:0] xgmii_rx_dc, // xgmii_rx_dc.data
+ output wire [3:0] xaui_tx_serial_data, // xaui_tx_serial.export
+ input wire [3:0] xaui_rx_serial_data, // xaui_rx_serial.export
+ output wire rx_ready, // rx_pma_ready.data
+ output wire tx_ready, // tx_pma_ready.data
+ output tri0 [altera_xcvr_functions::get_reconfig_from_width(device_family,reconfig_interfaces)-1:0] reconfig_from_xcvr,
+ input tri0 [altera_xcvr_functions::get_reconfig_to_width(device_family,reconfig_interfaces) -1:0] reconfig_to_xcvr,
+
+ output wire [3:0] rx_recovered_clk, // rx recovered clock from cdr
+// optional control and status ports
+ input wire rx_analogreset,
+ input wire rx_digitalreset,
+ input wire tx_digitalreset,
+ output wire rx_channelaligned,
+ input wire [3:0] rx_invpolarity,
+ input wire [3:0] rx_set_locktodata,
+ input wire [3:0] rx_set_locktoref,
+ input wire [3:0] rx_seriallpbken,
+ input wire [3:0] tx_invpolarity,
+ output wire [3:0] rx_is_lockedtodata,
+ output wire [3:0] rx_phase_comp_fifo_error,
+ output wire [3:0] rx_is_lockedtoref,
+ output wire [3:0] rx_rlv,
+ output wire [3:0] rx_rmfifoempty,
+ output wire [3:0] rx_rmfifofull,
+ output wire [3:0] tx_phase_comp_fifo_error,
+ output wire [7:0] rx_disperr,
+ output wire [7:0] rx_errdetect,
+ output wire [7:0] rx_patterndetect,
+ output wire [7:0] rx_rmfifodatadeleted,
+ output wire [7:0] rx_rmfifodatainserted,
+ output wire [7:0] rx_runningdisp,
+ output wire [7:0] rx_syncstatus,
+
+// external_pma_ctrl_reconf
+ output wire pll_locked,
+ input wire cal_blk_powerdown,
+ input wire gxb_powerdown,
+ input wire pll_powerdown
+);
+
+import altera_xcvr_functions::*;
+
+ wire alt_pma_controller_0_cal_blk_pdn_data;
+ wire alt_pma_controller_0_pll_pdn0_data;
+ wire alt_pma_controller_0_gx_pdn_data;
+ wire pll_locked_data;
+ wire [7:0] rx_disperr_data;
+ wire [7:0] rx_errdetect_data;
+ wire [7:0] rx_patterndetect_data;
+ wire [3:0] rx_phase_comp_fifo_error_data;
+ wire [3:0] rx_rlv_data;
+ wire [7:0] rx_rmfifodatadeleted_data;
+ wire [7:0] rx_rmfifodatainserted_data;
+ wire [3:0] rx_rmfifoempty_data;
+ wire [3:0] rx_rmfifofull_data;
+ wire [7:0] rx_runningdisp_data;
+ wire [7:0] rx_syncstatus_data;
+ wire [3:0] tx_phase_comp_fifo_error_data;
+ wire [3:0] alt_pma_ch_controller_0_rx_set_locktodata_data;
+ wire [3:0] alt_pma_ch_controller_0_rx_set_locktoref_data;
+ wire [3:0] alt_pma_ch_controller_0_rx_seriallpbken_data;
+ wire [3:0] alt_pma_ch_controller_0_rx_analog_rst_data;
+ wire [3:0] rx_is_lockedtodata_data;
+ wire [3:0] rx_is_lockedtoref_data;
+ wire [3:0] alt_pma_ch_controller_0_tx_digital_rst_data;
+ wire [3:0] alt_pma_ch_controller_0_rx_digital_rst_data;
+ wire hxaui_csr_r_rx_digitalreset_data;
+ wire [3:0] hxaui_csr_r_rx_invpolarity_data;
+ wire hxaui_csr_r_tx_digitalreset_data;
+ wire [3:0] hxaui_csr_r_tx_invpolarity_data;
+ wire hxaui_csr_simulation_flag_data;
+ wire alt_pma_controller_0_pll_pdn;
+ wire [3:0] alt_pma_0_tx_out_clk_clk;
+ wire [3:0] alt_pma_0_rx_recovered_clk_clk;
+ wire [79:0] sxaui_0_tx_parallel_data_data;
+ wire [79:0] alt_pma_0_rx_parallel_data_data;
+ wire [3:0] alt_pma_0_rx_is_lockedtodata_data;
+ wire rx_pma_ready;
+ wire sxaui_rst_done;
+
+
+ wire [5:0] sc_pma_ch_controller_address;
+ wire sc_pma_ch_controller_read;
+ wire [31:0] sc_pma_ch_controller_readdata;
+ wire sc_pma_ch_controller_waitrequest;
+ wire sc_pma_ch_controller_write;
+
+
+ wire [1:0] sc_pma_controller_address;
+ wire sc_pma_controller_read;
+ wire [31:0] sc_pma_controller_readdata;
+ wire sc_pma_controller_waitrequest;
+ wire sc_pma_controller_write;
+
+ wire [4:0] sc_csr_address;
+ wire sc_csr_read;
+ wire [31:0] sc_csr_readdata;
+ wire sc_csr_write;
+
+// assign output wires for status ports - whether or not they are used will be decided by the top level
+ assign rx_is_lockedtodata = rx_is_lockedtodata_data;
+ assign rx_phase_comp_fifo_error = rx_phase_comp_fifo_error_data;
+ assign rx_is_lockedtoref = rx_is_lockedtoref_data;
+ assign rx_rlv = rx_rlv_data;
+ assign rx_rmfifoempty = rx_rmfifoempty_data;
+ assign rx_rmfifofull = rx_rmfifofull_data;
+ assign tx_phase_comp_fifo_error = tx_phase_comp_fifo_error_data;
+ assign rx_disperr = rx_disperr_data;
+ assign rx_errdetect = rx_errdetect_data;
+ assign rx_patterndetect = rx_patterndetect_data;
+ assign rx_rmfifodatadeleted = rx_rmfifodatadeleted_data;
+ assign rx_rmfifodatainserted = rx_rmfifodatainserted_data;
+ assign rx_runningdisp = rx_runningdisp_data;
+ assign rx_syncstatus = rx_syncstatus_data;
+ assign rx_recovered_clk = alt_pma_0_rx_recovered_clk_clk;
+
+ // assign output wires for external pma_ctrl - whether or not they are used will be decided by the top level
+ assign pll_locked = pll_locked_data;
+ assign rx_ready = rx_pma_ready & sxaui_rst_done; // pma and PCS must be both ready
+
+ ///////////////////////////////////////////////////////////////////////
+ // Decoder for multiple slaves of pma_ch_control,pma_control,hxaui i/f
+ ///////////////////////////////////////////////////////////////////////
+ alt_xcvr_mgmt2dec_xaui mgmtdec_xaui (
+ .mgmt_clk_reset (phy_mgmt_clk_reset),
+ .mgmt_clk (phy_mgmt_clk),
+ .mgmt_address (phy_mgmt_address),
+ .mgmt_read (phy_mgmt_read),
+ .mgmt_write (phy_mgmt_write),
+ .mgmt_readdata (phy_mgmt_readdata),
+ .mgmt_waitrequest (phy_mgmt_waitrequest),
+
+ // internal interface to 'top' pma ch controller block
+ .sc_pma_ch_controller_readdata (sc_pma_ch_controller_readdata),
+ .sc_pma_ch_controller_waitrequest (sc_pma_ch_controller_waitrequest),
+ .sc_pma_ch_controller_address (sc_pma_ch_controller_address), //6 bit wide
+ .sc_pma_ch_controller_read (sc_pma_ch_controller_read),
+ .sc_pma_ch_controller_write (sc_pma_ch_controller_write),
+
+ // internal interface to 'top' pma controller block
+ .sc_pma_controller_readdata (sc_pma_controller_readdata),
+ .sc_pma_controller_waitrequest (sc_pma_controller_waitrequest),
+ .sc_pma_controller_address (sc_pma_controller_address), //2 bit wide
+ .sc_pma_controller_read (sc_pma_controller_read),
+ .sc_pma_controller_write (sc_pma_controller_write),
+
+ // internal interface to 'top' hxaui csr block
+ .sc_csr_readdata (sc_csr_readdata),
+ .sc_csr_waitrequest (1'b0), // PCS CSR is always ready
+ .sc_csr_address (sc_csr_address), //5 bit wide
+ .sc_csr_read (sc_csr_read),
+ .sc_csr_write (sc_csr_write)
+ );
+
+ ///////////////////////////////////////////////////////////////////////
+ // PMA Channel Controller - only for HXAUI
+ ///////////////////////////////////////////////////////////////////////
+// add generate for hxaui/sxaui - only use ch_controller for hxaui
+ generate
+ if (interface_type == "Hard XAUI") begin
+ alt_pma_ch_controller_tgx #(
+ .number_of_channels (4),
+ .sync_depth (2),
+ .sys_clk_in_mhz (sys_clk_in_mhz)
+ ) alt_pma_ch_controller_0 (
+ .clk (phy_mgmt_clk),
+ .rst (phy_mgmt_clk_reset),
+ .ch_mgmt_address (sc_pma_ch_controller_address),
+ .ch_mgmt_read (sc_pma_ch_controller_read),
+ .ch_mgmt_readdata (sc_pma_ch_controller_readdata),
+ .ch_mgmt_write (sc_pma_ch_controller_write),
+ .ch_mgmt_writedata (phy_mgmt_writedata),
+ .ch_mgmt_waitrequest (sc_pma_ch_controller_waitrequest),
+ .rx_pma_ready (rx_pma_ready),
+ .tx_pma_ready (tx_ready),
+ .rx_is_lockedtodata (rx_is_lockedtodata_data),
+ .rx_is_lockedtoref (rx_is_lockedtoref_data),
+ .rx_set_locktodata (alt_pma_ch_controller_0_rx_set_locktodata_data),
+ .rx_set_locktoref (alt_pma_ch_controller_0_rx_set_locktoref_data),
+ .rx_seriallpbken (alt_pma_ch_controller_0_rx_seriallpbken_data),
+ .rx_analog_rst (alt_pma_ch_controller_0_rx_analog_rst_data),
+ .tx_digital_rst (alt_pma_ch_controller_0_tx_digital_rst_data),
+ .rx_digital_rst (alt_pma_ch_controller_0_rx_digital_rst_data),
+ .rx_rst_digital (rx_digitalreset), // optional user triggered rx_digitalreset
+ .tx_rst_digital (tx_digitalreset), // optional user triggered tx_digitalreset
+ //reconfig_to_xcvr bit configuration
+ //Bit | Value
+ //-------------------------------------------
+ //3 | offset_cancellation_is_busy |
+ //2 | dprio_load |
+ //1 | dprio_disable |
+ //0 | dprio_in |
+ //-------------------------------------------
+ // .rx_oc_busy (reconfig_to_xcvr[3]), // rx_oc_busy.data
+ .rx_cal_busy (reconfig_to_xcvr[3]), // rx_oc_busy.data
+ .tx_cal_busy (1'b0), // rx_oc_busy.data
+ .pll_locked (pll_locked_data)
+ );
+ end else if (interface_type == "Soft XAUI") begin
+ siv_xcvr_low_latency_phy_nr #(
+ .device_family (device_family),
+ .intended_device_variant ("ANY"),
+ .number_of_channels (4),
+ .number_of_reconfig_interface (reconfig_interfaces),
+ .operation_mode ("DUPLEX"),
+ .phase_comp_fifo_mode ("NONE"),
+ .serialization_factor (20),
+ .data_rate ("3125 Mbps"),
+ .pll_input_frequency ("156.25 MHz"),
+ .number_pll_inclks (1),
+ .pll_inclk_select (0),
+ .pll_type (xaui_pll_type),
+ .starting_channel_number (starting_channel_number),
+ .bonded_mode ("TRUE"),
+ .sys_clk_in_mhz (sys_clk_in_mhz),
+ //.rx_bitslip_en (0),
+ //.tx_bitslip_en (0),
+ //.select_10g_pcs (0),
+ //.tx_use_coreclk (0),
+ //.rx_use_coreclk (0),
+ .gx_analog_power ("AUTO"),
+ .pll_lock_speed ("AUTO"),
+ .tx_analog_power ("AUTO"),
+ .tx_slew_rate ("OFF"),
+ .tx_termination (tx_termination),
+ .tx_common_mode ("0.65V"),
+ .rx_pll_lock_speed ("AUTO"),
+ .rx_common_mode (rx_common_mode),
+ .rx_signal_detect_threshold (2),
+ .rx_ppmselect (32),
+ .rx_termination (rx_termination),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv ((tx_preemp_pretap_inv==1)? "TRUE" : "FALSE"),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv ((tx_preemp_tap_2_inv==1)? "TRUE" : "FALSE"),
+ .tx_vod_selection (tx_vod_selection),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .rx_use_cruclk ("FALSE"),
+ .loopback_mode ("SLB")
+ ) alt_pma_0 (
+ .clk (phy_mgmt_clk),
+ .rst (phy_mgmt_clk_reset),
+ .gx_pdn (alt_pma_controller_0_gx_pdn_data),
+ .ch_mgmt_address (sc_pma_ch_controller_address),
+ .ch_mgmt_read (sc_pma_ch_controller_read),
+ .ch_mgmt_readdata (sc_pma_ch_controller_readdata),
+ .ch_mgmt_write (sc_pma_ch_controller_write),
+ .ch_mgmt_writedata (phy_mgmt_writedata),
+ .ch_mgmt_waitrequest (sc_pma_ch_controller_waitrequest),
+ .cal_blk_clk (phy_mgmt_clk),
+ .cal_blk_pdn (alt_pma_controller_0_cal_blk_pdn_data),
+ .pll_ref_clk (pll_ref_clk),
+ .tx_out_clk (alt_pma_0_tx_out_clk_clk),
+ .tx_parallel_data (sxaui_0_tx_parallel_data_data),
+ .tx_serial_data (xaui_tx_serial_data),
+ .tx_pma_ready (tx_ready),
+ .pll_pdn (alt_pma_controller_0_pll_pdn0_data),
+ .pll_locked (pll_locked_data),
+ .rx_is_lockedtodata (alt_pma_0_rx_is_lockedtodata_data),
+ .rx_is_lockedtoref (),
+ .rx_recovered_clk (alt_pma_0_rx_recovered_clk_clk),
+ .rx_serial_data (xaui_rx_serial_data),
+ .rx_parallel_data (alt_pma_0_rx_parallel_data_data),
+ .rx_cdr_ref_clk (),
+ .rx_pma_ready (rx_pma_ready),
+ .reconfig_clk (phy_mgmt_clk),
+ .reconfig_to_gxb (reconfig_to_xcvr),
+ .reconfig_from_gxb (reconfig_from_xcvr),
+ .rx_rst_digital (rx_digitalreset), //optional user triggered rx_digitalreset
+ .tx_rst_digital (tx_digitalreset), //optional user triggered tx_digitalreset
+ //.tx_bitslip (28'b0),
+ //.tx_coreclk (4'b0),
+ //.rx_offset_cancellation_done (1'b1),
+ //.rx_bitslip (4'b0),
+ //.rx_parallel_data_read (4'b0),
+ //.rx_coreclk (4'b0),
+ //.aeq_to_gxb (96'b0),
+ //.aeq_from_gxb (),
+ .tx_digital_rst (alt_pma_ch_controller_0_tx_digital_rst_data),
+ .rx_digital_rst (alt_pma_ch_controller_0_rx_digital_rst_data)
+ );
+ end
+ // don't instantiate anything if the interface type is invalid
+ endgenerate
+
+ ///////////////////////////////////////////////////////////////////////
+ // PMA Controller
+ ///////////////////////////////////////////////////////////////////////
+ generate
+ if (external_pma_ctrl_reconf == 0) begin
+ alt_pma_controller_tgx #(
+ .number_of_plls (1),
+ .sync_depth (2),
+ .tx_pll_reset_hold_time (20)
+ ) alt_pma_controller_0 (
+ .clk (phy_mgmt_clk),
+ .rst (phy_mgmt_clk_reset),
+ .pma_mgmt_address (sc_pma_controller_address),
+ .pma_mgmt_read (sc_pma_controller_read),
+ .pma_mgmt_readdata (sc_pma_controller_readdata),
+ .pma_mgmt_write (sc_pma_controller_write),
+ .pma_mgmt_writedata (phy_mgmt_writedata),
+ .pma_mgmt_waitrequest (sc_pma_controller_waitrequest),
+ .cal_blk_clk (phy_mgmt_clk),
+ .cal_blk_pdn (alt_pma_controller_0_cal_blk_pdn_data),
+ .tx_pll_ready (),
+ .gx_pdn (alt_pma_controller_0_gx_pdn_data),
+ .pll_pdn (alt_pma_controller_0_pll_pdn0_data),
+ .pll_locked (pll_locked_data)
+ );
+ end else begin
+ assign alt_pma_controller_0_cal_blk_pdn_data = cal_blk_powerdown;
+ assign alt_pma_controller_0_gx_pdn_data = gxb_powerdown;
+ assign alt_pma_controller_0_pll_pdn0_data = pll_powerdown;
+ end
+ endgenerate
+
+
+ ///////////////////////////////////////////////////////////////////////
+ // HXAUI CSR
+ ///////////////////////////////////////////////////////////////////////
+// should be consistent across all device families and interface types
+// -might need a generate statement for some of the connections that don't exist between hxaui/sxaui
+ hxaui_csr hxaui_csr (
+ .clk (phy_mgmt_clk),
+ .reset (phy_mgmt_clk_reset),
+ .address (sc_csr_address),
+ .byteenable (4'b1111), // .byteenable (Tie byteenable to all 1s)
+ .read (sc_csr_read),
+ .readdata (sc_csr_readdata),
+ .write (sc_csr_write),
+ .writedata (phy_mgmt_writedata),
+ .rx_patterndetect (rx_patterndetect_data),
+ .rx_syncstatus (rx_syncstatus_data),
+ .rx_runningdisp (rx_runningdisp_data),
+ .rx_errdetect (rx_errdetect_data),
+ .rx_disperr (rx_disperr_data),
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error_data),
+ .rx_rlv (rx_rlv_data),
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted_data),
+ .rx_rmfifodatainserted (rx_rmfifodatainserted_data),
+ .rx_rmfifoempty (rx_rmfifoempty_data),
+ .rx_rmfifofull (rx_rmfifofull_data),
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error_data),
+ .r_rx_invpolarity (hxaui_csr_r_rx_invpolarity_data),
+ .r_tx_invpolarity (hxaui_csr_r_tx_invpolarity_data),
+ .r_rx_digitalreset (hxaui_csr_r_rx_digitalreset_data),
+ .r_tx_digitalreset (hxaui_csr_r_tx_digitalreset_data),
+ .simulation_flag (hxaui_csr_simulation_flag_data) // only for soft_xaui
+ );
+
+
+ ///////////////////////////////////////////////////////////////////////
+ // HXAUI - Interface to alt4gxb megafunction block
+ ///////////////////////////////////////////////////////////////////////
+// need to add generate to pick between sxaui and hxaui
+ generate
+ if (interface_type == "Hard XAUI") begin
+ (* ALTERA_ATTRIBUTE = {"-name SDC_STATEMENT \"set_false_path -from [get_registers *hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component*fifo*flow] -to [get_registers *xaui_phy*hxaui_csr*tx_phase_comp_fifo_error_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers *hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component*] -to [get_registers *xaui_phy*hxaui_csr*rx*_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*siv_xcvr_xaui*hxaui_csr*hxaui_csr_reset0q[*]}] -to [get_registers {*xaui_phy*hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component|*digitalreset*}]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*siv_xcvr_xaui*alt_pma_ch_controller_0*rc*}] -to [get_registers {*xaui_phy*hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component|*digitalreset*}]\""} *)
+ hxaui #(
+ .device_family (device_family),
+ .starting_channel_number (starting_channel_number),
+ .xaui_pll_type (xaui_pll_type),
+ .use_control_and_status_ports (use_control_and_status_ports),
+ .external_pma_ctrl_reconf (external_pma_ctrl_reconf),
+ .tx_termination (tx_termination),
+ .rx_termination (rx_termination),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv (tx_preemp_pretap_inv),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv (tx_preemp_tap_2_inv),
+ .tx_vod_selection (tx_vod_selection),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .rx_common_mode (rx_common_mode)
+ ) hxaui_0 (
+ .xgmii_tx_clk (xgmii_tx_clk),
+ .xgmii_tx_dc (xgmii_tx_dc),
+ .xgmii_rx_clk (xgmii_rx_clk),
+ .xgmii_rx_dc (xgmii_rx_dc),
+ .refclk (pll_ref_clk),
+ .xaui_tx_serial (xaui_tx_serial_data),
+ .xaui_rx_serial (xaui_rx_serial_data),
+ .rx_analogreset (rx_analogreset), // use_cs_ports, input
+ .rx_digitalreset (alt_pma_ch_controller_0_rx_digital_rst_data),
+ .tx_digitalreset (alt_pma_ch_controller_0_tx_digital_rst_data),
+ .rx_channelaligned (rx_channelaligned), // use_cs_ports, output
+ .rx_invpolarity (rx_invpolarity), // use_cs_ports, input
+ .rx_set_locktodata (rx_set_locktodata), // use_cs_ports, input
+ .rx_set_locktoref (rx_set_locktoref), // use_cs_ports, input
+ .rx_seriallpbken (rx_seriallpbken), // use_cs_ports, input
+ .tx_invpolarity (tx_invpolarity), // use_cs_ports, input
+ .rx_is_lockedtodata (rx_is_lockedtodata_data), // use_cs_ports, output
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error_data), // use_cs_ports, output
+ .rx_is_lockedtoref (rx_is_lockedtoref_data), // use_cs_ports, output
+ .rx_rlv (rx_rlv_data), // use_cs_ports, output
+ .rx_rmfifoempty (rx_rmfifoempty_data), // use_cs_ports, output
+ .rx_rmfifofull (rx_rmfifofull_data), // use_cs_ports, output
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error_data), // use_cs_ports, output
+ .rx_disperr (rx_disperr_data), // use_cs_ports, output
+ .rx_errdetect (rx_errdetect_data), // use_cs_ports, output
+ .rx_patterndetect (rx_patterndetect_data), // use_cs_ports, output
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted_data), // use_cs_ports, output
+ .rx_rmfifodatainserted (rx_rmfifodatainserted_data), // use_cs_ports, output
+ .rx_runningdisp (rx_runningdisp_data), // use_cs_ports, output
+ .rx_syncstatus (rx_syncstatus_data), // use_cs_ports, output
+ .reconfig_clk (phy_mgmt_clk),
+ .reconfig_togxb (reconfig_to_xcvr), // external_pma_ctrl_reconf
+ .reconfig_fromgxb (reconfig_from_xcvr[16:0]), // external_pma_ctrl_reconf
+ .rx_recovered_clk (alt_pma_0_rx_recovered_clk_clk),
+ .cal_blk_clk (phy_mgmt_clk),
+ .cal_blk_powerdown (1'b0), // not used, should remove
+ .gxb_powerdown (1'b0), // not used, should remove
+ .pll_powerdown (1'b0), // not used, should remove
+ .pll_locked (pll_locked_data),
+ .r_cal_blk_powerdown (alt_pma_controller_0_cal_blk_pdn_data),
+ .r_gxb_powerdown (alt_pma_controller_0_gx_pdn_data),
+ .r_pll_powerdown (alt_pma_controller_0_pll_pdn0_data),
+ .r_rx_set_locktodata (alt_pma_ch_controller_0_rx_set_locktodata_data),
+ .r_rx_set_locktoref (alt_pma_ch_controller_0_rx_set_locktoref_data),
+ .r_rx_seriallpbken (alt_pma_ch_controller_0_rx_seriallpbken_data),
+ .r_rx_analogreset (alt_pma_ch_controller_0_rx_analog_rst_data),
+ .r_rx_digitalreset (hxaui_csr_r_rx_digitalreset_data),
+ .r_tx_digitalreset (hxaui_csr_r_tx_digitalreset_data),
+ .r_rx_invpolarity (hxaui_csr_r_rx_invpolarity_data),
+ .r_tx_invpolarity (hxaui_csr_r_tx_invpolarity_data)
+ );
+ assign sxaui_rst_done = 1'b1; // if using hard xaui, assign this to 1 to always be ready
+ end else if (interface_type == "Soft XAUI") begin
+ (* ALTERA_ATTRIBUTE = {" -name SDC_STATEMENT \"set_false_path -from [get_registers {*sxaui_0*alt_soft_xaui_pcs*xaui_rx*disp_err_delay[*]}] -to [get_registers *xaui_phy*hxaui_csr*rx*_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*sxaui_0*alt_soft_xaui_pcs*xaui_rx*pcs_rx_syncstatus[*]}] -to [get_registers *xaui_phy*hxaui_csr*rx*_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*sxaui_0*alt_soft_xaui_pcs*xaui_rx*channel_align_synchclk[*]}] -to [get_registers *xaui_phy*hxaui_csr*rx*_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*siv_xcvr_xaui*hxaui_csr*hxaui_csr_reset0q[1]}] -to [get_registers *sxaui_0*alt_soft_xaui_pcs*tx_reset*] \" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*siv_xcvr_xaui*hxaui_csr*hxaui_csr_reset0q[1]}] -to [get_registers *sxaui_0*alt_soft_xaui_pcs*rx_reset*] \" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*sxaui_0*alt_soft_xaui_pcs*xaui_rx*rd_ptr_latched_del[*]}] -to [get_registers *sxaui_0*alt_soft_xaui_pcs*xaui_rx*rd_ptr_wr[*]]\""} *)
+ sxaui #(
+ .starting_channel_number (starting_channel_number),
+ .xaui_pll_type (xaui_pll_type),
+ .use_control_and_status_ports (use_control_and_status_ports)
+ ) sxaui_0 (
+ .xgmii_tx_clk (xgmii_tx_clk), // xgmii_tx_clk.clk
+ .xgmii_tx_dc (xgmii_tx_dc), // xgmii_tx_dc.data
+ .xgmii_rx_clk (xgmii_rx_clk), // xgmii_rx_clk.clk
+ .xgmii_rx_dc (xgmii_rx_dc), // xgmii_rx_dc.data
+ .refclk (pll_ref_clk), // refclk.clk
+ .mgmt_clk (phy_mgmt_clk), // mgmt_clk.clk
+ .tx_out_clk (alt_pma_0_tx_out_clk_clk), // tx_out_clk.clk
+ .rx_recovered_clk (alt_pma_0_rx_recovered_clk_clk), // rx_recovered_clk.clk
+ .tx_parallel_data (sxaui_0_tx_parallel_data_data), // tx_parallel_data.data
+ .rx_parallel_data (alt_pma_0_rx_parallel_data_data), // rx_parallel_data.data
+ .rx_is_lockedtodata (alt_pma_0_rx_is_lockedtodata_data), // rx_is_lockedtodata.data
+ .rx_digitalreset (alt_pma_ch_controller_0_rx_digital_rst_data[0] ), // rx_digitalreset from cahnnel controller in alt_pma
+ .tx_digitalreset (alt_pma_ch_controller_0_tx_digital_rst_data[0] ), // tx_digitalreset from cahnnel controller in alt_pma
+ .pll_locked (pll_locked_data), // pll_locked.data
+ .rx_syncstatus (rx_syncstatus_data), // rx_syncstatus.data
+ .rx_channelaligned (rx_channelaligned), // rx_channelaligned.data
+ .rx_disperr (rx_disperr_data), // rx_disperr.data
+ .rx_errdetect (rx_errdetect_data), // rx_errdetect.data
+ .r_rx_digitalreset (hxaui_csr_r_rx_digitalreset_data), // r_rx_digitalreset.data
+ .r_tx_digitalreset (hxaui_csr_r_tx_digitalreset_data), // r_tx_digitalreset.data
+ .pma_stat_rst_done (sxaui_rst_done), // soft reset done
+ .simulation_flag (hxaui_csr_simulation_flag_data) // simulation_flag.data
+ );
+ assign rx_patterndetect_data = 8'b0; // not supported by soft PCS
+ assign rx_runningdisp_data = 8'b0; // not supported by soft PCS
+ assign rx_phase_comp_fifo_error_data = 4'b0; // not supported by soft PCS
+ assign rx_rlv_data = 4'b0; // not supported by soft PCS
+ assign rx_rmfifodatadeleted_data = 8'b0; // not supported by soft PCS
+ assign rx_rmfifodatainserted_data = 8'b0; // not supported by soft PCS
+ assign rx_rmfifoempty_data = 4'b0; // not supported by soft PCS
+ assign rx_rmfifofull_data = 4'b0; // not supported by soft PCS
+ assign tx_phase_comp_fifo_error_data = 4'b0; // not supported by soft PCS
+ assign hxaui_csr_r_rx_invpolarity_data = 4'b0; // not supported by soft PCS
+ assign hxaui_csr_r_tx_invpolarity_data = 4'b0; // not supported by soft PCS
+ assign rx_is_lockedtodata_data = 4'b0; // not supported by soft PCS
+ assign rx_is_lockedtoref_data = 4'b0; // not supported by soft PCS
+ end
+ // don't instantiate anything if the interface type is invalid
+ endgenerate
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/synopsys_files.txt b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/synopsys_files.txt
new file mode 100644
index 0000000000000000000000000000000000000000..96175539fe10e847160e3bb13c7980081beae5b3
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/altera_xcvr_xaui/synopsys_files.txt
@@ -0,0 +1,34 @@
+./altera_xcvr_functions.sv
+./altera_xcvr_xaui.sv
+./hxaui_csr_h.sv
+./hxaui_csr.sv
+./alt_xcvr_mgmt2dec_phyreconfig.sv
+./alt_xcvr_mgmt2dec_xaui.sv
+./alt_pma_ch_controller_tgx.v
+./alt_pma_controller_tgx.v
+./alt_reset_ctrl_lego.sv
+./alt_reset_ctrl_tgx_cdrauto.sv
+./alt_xcvr_resync.sv
+./alt_xcvr_csr_common_h.sv
+./alt_xcvr_csr_common.sv
+./alt_xcvr_csr_pcs8g_h.sv
+./alt_xcvr_csr_pcs8g.sv
+./alt_xcvr_csr_selector.sv
+./alt_xcvr_mgmt2dec.sv
+./altera_wait_generate.v
+./hxaui_alt4gxb.v
+./hxaui.v
+./siv_xcvr_xaui.sv
+./alt_xcvr_reconfig_h.sv
+./alt_xcvr_reconfig_siv.sv
+./alt_xcvr_reconfig_analog.sv
+./alt_xcvr_reconfig_analog_tgx.v
+./alt_xcvr_reconfig_offset_cancellation.sv
+./alt_xcvr_reconfig_offset_cancellation_tgx.v
+./alt_xcvr_reconfig_eyemon_tgx.sv
+./alt_xcvr_reconfig_dfe_tgx.sv
+./alt_xcvr_reconfig_basic_tgx.v
+./alt_mutex_acq.v
+./alt_dprio.v
+./alt_xcvr_arbiter.sv
+./alt_xcvr_m2s.sv
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/ip_stratixiv_phy_xaui_0.vhd b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/ip_stratixiv_phy_xaui_0.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4e561332dedee9ffd0ef1cf1d4f1ec6400aa7b73
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/ip_stratixiv_phy_xaui_0.vhd
@@ -0,0 +1,220 @@
+-- ip_stratixiv_phy_xaui_0.vhd
+
+-- Generated using ACDS version 11.1sp2 259 at 2014.09.29.14:00:54
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ip_stratixiv_phy_xaui_0 is
+ port (
+ pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
+ xgmii_tx_clk : in std_logic := '0'; -- xgmii_tx_clk.clk
+ xgmii_rx_clk : out std_logic; -- xgmii_rx_clk.clk
+ xgmii_rx_dc : out std_logic_vector(71 downto 0); -- xgmii_rx_dc.data
+ xgmii_tx_dc : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_tx_dc.data
+ xaui_rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- xaui_rx_serial_data.export
+ xaui_tx_serial_data : out std_logic_vector(3 downto 0); -- xaui_tx_serial_data.export
+ rx_ready : out std_logic; -- rx_ready.export
+ tx_ready : out std_logic; -- tx_ready.export
+ phy_mgmt_clk : in std_logic := '0'; -- phy_mgmt_clk.clk
+ phy_mgmt_clk_reset : in std_logic := '0'; -- phy_mgmt_clk_reset.reset
+ phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => '0'); -- phy_mgmt.address
+ phy_mgmt_read : in std_logic := '0'; -- .read
+ phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ phy_mgmt_write : in std_logic := '0'; -- .write
+ phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ phy_mgmt_waitrequest : out std_logic; -- .waitrequest
+ rx_digitalreset : in std_logic := '0'; -- rx_digitalreset.data
+ tx_digitalreset : in std_logic := '0'; -- tx_digitalreset.data
+ rx_channelaligned : out std_logic; -- rx_channelaligned.data
+ rx_syncstatus : out std_logic_vector(7 downto 0); -- rx_syncstatus.data
+ rx_disperr : out std_logic_vector(7 downto 0); -- rx_disperr.data
+ rx_errdetect : out std_logic_vector(7 downto 0); -- rx_errdetect.data
+ rx_analogreset : in std_logic := '0'; -- rx_analogreset.data
+ rx_invpolarity : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_invpolarity.data
+ rx_set_locktodata : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_set_locktodata.data
+ rx_set_locktoref : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_set_locktoref.data
+ rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_seriallpbken.data
+ tx_invpolarity : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_invpolarity.data
+ rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- rx_is_lockedtodata.data
+ rx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- rx_phase_comp_fifo_error.data
+ rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- rx_is_lockedtoref.data
+ rx_rlv : out std_logic_vector(3 downto 0); -- rx_rlv.data
+ rx_rmfifoempty : out std_logic_vector(3 downto 0); -- rx_rmfifoempty.data
+ rx_rmfifofull : out std_logic_vector(3 downto 0); -- rx_rmfifofull.data
+ tx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- tx_phase_comp_fifo_error.data
+ rx_patterndetect : out std_logic_vector(7 downto 0); -- rx_patterndetect.data
+ rx_rmfifodatadeleted : out std_logic_vector(7 downto 0); -- rx_rmfifodatadeleted.data
+ rx_rmfifodatainserted : out std_logic_vector(7 downto 0); -- rx_rmfifodatainserted.data
+ rx_runningdisp : out std_logic_vector(7 downto 0); -- rx_runningdisp.data
+ cal_blk_powerdown : in std_logic := '0'; -- cal_blk_powerdown.data
+ pll_powerdown : in std_logic := '0'; -- pll_powerdown.data
+ gxb_powerdown : in std_logic := '0'; -- gxb_powerdown.data
+ pll_locked : out std_logic; -- pll_locked.data
+ reconfig_from_xcvr : out std_logic_vector(16 downto 0); -- reconfig_from_xcvr.data
+ reconfig_to_xcvr : in std_logic_vector(3 downto 0) := (others => '0') -- reconfig_to_xcvr.data
+ );
+end entity ip_stratixiv_phy_xaui_0;
+
+architecture rtl of ip_stratixiv_phy_xaui_0 is
+ component altera_xcvr_xaui is
+ generic (
+ device_family : string := "Stratix IV";
+ starting_channel_number : integer := 0;
+ interface_type : string := "Hard XAUI";
+ data_rate : string := "3125 Mbps";
+ xaui_pll_type : string := "AUTO";
+ BASE_DATA_RATE : string := "";
+ use_control_and_status_ports : integer := 0;
+ external_pma_ctrl_reconf : integer := 0;
+ recovered_clk_out : integer := 0;
+ number_of_interfaces : integer := 1;
+ reconfig_interfaces : integer := 1;
+ use_rx_rate_match : integer := 0;
+ tx_termination : string := "OCT_100_OHMS";
+ tx_vod_selection : integer := 4;
+ tx_preemp_pretap : integer := 0;
+ tx_preemp_pretap_inv : integer := 0;
+ tx_preemp_tap_1 : integer := 0;
+ tx_preemp_tap_2 : integer := 0;
+ tx_preemp_tap_2_inv : integer := 0;
+ rx_common_mode : string := "0.82v";
+ rx_termination : string := "OCT_100_OHMS";
+ rx_eq_dc_gain : integer := 0;
+ rx_eq_ctrl : integer := 0;
+ mgmt_clk_in_mhz : integer := 150
+ );
+ port (
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ xgmii_tx_clk : in std_logic := 'X'; -- clk
+ xgmii_rx_clk : out std_logic; -- clk
+ xgmii_rx_dc : out std_logic_vector(71 downto 0); -- data
+ xgmii_tx_dc : in std_logic_vector(71 downto 0) := (others => 'X'); -- data
+ xaui_rx_serial_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ xaui_tx_serial_data : out std_logic_vector(3 downto 0); -- export
+ rx_ready : out std_logic; -- export
+ tx_ready : out std_logic; -- export
+ phy_mgmt_clk : in std_logic := 'X'; -- clk
+ phy_mgmt_clk_reset : in std_logic := 'X'; -- reset
+ phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
+ phy_mgmt_read : in std_logic := 'X'; -- read
+ phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- readdata
+ phy_mgmt_write : in std_logic := 'X'; -- write
+ phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ phy_mgmt_waitrequest : out std_logic; -- waitrequest
+ rx_digitalreset : in std_logic := 'X'; -- data
+ tx_digitalreset : in std_logic := 'X'; -- data
+ rx_channelaligned : out std_logic; -- data
+ rx_syncstatus : out std_logic_vector(7 downto 0); -- data
+ rx_disperr : out std_logic_vector(7 downto 0); -- data
+ rx_errdetect : out std_logic_vector(7 downto 0); -- data
+ rx_analogreset : in std_logic := 'X'; -- data
+ rx_invpolarity : in std_logic_vector(3 downto 0) := (others => 'X'); -- data
+ rx_set_locktodata : in std_logic_vector(3 downto 0) := (others => 'X'); -- data
+ rx_set_locktoref : in std_logic_vector(3 downto 0) := (others => 'X'); -- data
+ rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => 'X'); -- data
+ tx_invpolarity : in std_logic_vector(3 downto 0) := (others => 'X'); -- data
+ rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- data
+ rx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- data
+ rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- data
+ rx_rlv : out std_logic_vector(3 downto 0); -- data
+ rx_rmfifoempty : out std_logic_vector(3 downto 0); -- data
+ rx_rmfifofull : out std_logic_vector(3 downto 0); -- data
+ tx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- data
+ rx_patterndetect : out std_logic_vector(7 downto 0); -- data
+ rx_rmfifodatadeleted : out std_logic_vector(7 downto 0); -- data
+ rx_rmfifodatainserted : out std_logic_vector(7 downto 0); -- data
+ rx_runningdisp : out std_logic_vector(7 downto 0); -- data
+ cal_blk_powerdown : in std_logic := 'X'; -- data
+ pll_powerdown : in std_logic := 'X'; -- data
+ gxb_powerdown : in std_logic := 'X'; -- data
+ pll_locked : out std_logic; -- data
+ reconfig_from_xcvr : out std_logic_vector(16 downto 0); -- data
+ reconfig_to_xcvr : in std_logic_vector(3 downto 0) := (others => 'X'); -- data
+ rx_recovered_clk : out std_logic_vector(3 downto 0); -- export
+ tx_clk312_5 : out std_logic -- export
+ );
+ end component altera_xcvr_xaui;
+
+begin
+
+ ip_stratixiv_phy_xaui_0_inst : component altera_xcvr_xaui
+ generic map (
+ device_family => "Stratix IV",
+ starting_channel_number => 0,
+ interface_type => "Hard XAUI",
+ data_rate => "3125 Mbps",
+ xaui_pll_type => "CMU",
+ BASE_DATA_RATE => "",
+ use_control_and_status_ports => 1,
+ external_pma_ctrl_reconf => 1,
+ recovered_clk_out => 0,
+ number_of_interfaces => 1,
+ reconfig_interfaces => 1,
+ use_rx_rate_match => 0,
+ tx_termination => "OCT_100_OHMS",
+ tx_vod_selection => 4,
+ tx_preemp_pretap => 0,
+ tx_preemp_pretap_inv => 0,
+ tx_preemp_tap_1 => 0,
+ tx_preemp_tap_2 => 0,
+ tx_preemp_tap_2_inv => 0,
+ rx_common_mode => "0.82v",
+ rx_termination => "OCT_100_OHMS",
+ rx_eq_dc_gain => 0,
+ rx_eq_ctrl => 0,
+ mgmt_clk_in_mhz => 150
+ )
+ port map (
+ pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk
+ xgmii_tx_clk => xgmii_tx_clk, -- xgmii_tx_clk.clk
+ xgmii_rx_clk => xgmii_rx_clk, -- xgmii_rx_clk.clk
+ xgmii_rx_dc => xgmii_rx_dc, -- xgmii_rx_dc.data
+ xgmii_tx_dc => xgmii_tx_dc, -- xgmii_tx_dc.data
+ xaui_rx_serial_data => xaui_rx_serial_data, -- xaui_rx_serial_data.export
+ xaui_tx_serial_data => xaui_tx_serial_data, -- xaui_tx_serial_data.export
+ rx_ready => rx_ready, -- rx_ready.export
+ tx_ready => tx_ready, -- tx_ready.export
+ phy_mgmt_clk => phy_mgmt_clk, -- phy_mgmt_clk.clk
+ phy_mgmt_clk_reset => phy_mgmt_clk_reset, -- phy_mgmt_clk_reset.reset
+ phy_mgmt_address => phy_mgmt_address, -- phy_mgmt.address
+ phy_mgmt_read => phy_mgmt_read, -- .read
+ phy_mgmt_readdata => phy_mgmt_readdata, -- .readdata
+ phy_mgmt_write => phy_mgmt_write, -- .write
+ phy_mgmt_writedata => phy_mgmt_writedata, -- .writedata
+ phy_mgmt_waitrequest => phy_mgmt_waitrequest, -- .waitrequest
+ rx_digitalreset => rx_digitalreset, -- rx_digitalreset.data
+ tx_digitalreset => tx_digitalreset, -- tx_digitalreset.data
+ rx_channelaligned => rx_channelaligned, -- rx_channelaligned.data
+ rx_syncstatus => rx_syncstatus, -- rx_syncstatus.data
+ rx_disperr => rx_disperr, -- rx_disperr.data
+ rx_errdetect => rx_errdetect, -- rx_errdetect.data
+ rx_analogreset => rx_analogreset, -- rx_analogreset.data
+ rx_invpolarity => rx_invpolarity, -- rx_invpolarity.data
+ rx_set_locktodata => rx_set_locktodata, -- rx_set_locktodata.data
+ rx_set_locktoref => rx_set_locktoref, -- rx_set_locktoref.data
+ rx_seriallpbken => rx_seriallpbken, -- rx_seriallpbken.data
+ tx_invpolarity => tx_invpolarity, -- tx_invpolarity.data
+ rx_is_lockedtodata => rx_is_lockedtodata, -- rx_is_lockedtodata.data
+ rx_phase_comp_fifo_error => rx_phase_comp_fifo_error, -- rx_phase_comp_fifo_error.data
+ rx_is_lockedtoref => rx_is_lockedtoref, -- rx_is_lockedtoref.data
+ rx_rlv => rx_rlv, -- rx_rlv.data
+ rx_rmfifoempty => rx_rmfifoempty, -- rx_rmfifoempty.data
+ rx_rmfifofull => rx_rmfifofull, -- rx_rmfifofull.data
+ tx_phase_comp_fifo_error => tx_phase_comp_fifo_error, -- tx_phase_comp_fifo_error.data
+ rx_patterndetect => rx_patterndetect, -- rx_patterndetect.data
+ rx_rmfifodatadeleted => rx_rmfifodatadeleted, -- rx_rmfifodatadeleted.data
+ rx_rmfifodatainserted => rx_rmfifodatainserted, -- rx_rmfifodatainserted.data
+ rx_runningdisp => rx_runningdisp, -- rx_runningdisp.data
+ cal_blk_powerdown => cal_blk_powerdown, -- cal_blk_powerdown.data
+ pll_powerdown => pll_powerdown, -- pll_powerdown.data
+ gxb_powerdown => gxb_powerdown, -- gxb_powerdown.data
+ pll_locked => pll_locked, -- pll_locked.data
+ reconfig_from_xcvr => reconfig_from_xcvr, -- reconfig_from_xcvr.data
+ reconfig_to_xcvr => reconfig_to_xcvr, -- reconfig_to_xcvr.data
+ rx_recovered_clk => open, -- (terminated)
+ tx_clk312_5 => open -- (terminated)
+ );
+
+end architecture rtl; -- of ip_stratixiv_phy_xaui_0
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/mentor/msim_setup.tcl b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/mentor/msim_setup.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e19fa6f7e7fa37fc50ac7264c417da2639ddbc0f
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_0_sim/mentor/msim_setup.tcl
@@ -0,0 +1,252 @@
+
+# (C) 2001-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ----------------------------------------
+# Auto-generated simulation script
+
+# ----------------------------------------
+# Initialize the variable
+if ![info exists SYSTEM_INSTANCE_NAME] {
+ set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
+ set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] {
+ set TOP_LEVEL_NAME "ip_stratixiv_phy_xaui_0"
+} elseif { ![ string match "" $TOP_LEVEL_NAME ] } {
+ set TOP_LEVEL_NAME "$TOP_LEVEL_NAME"
+}
+
+if ![info exists QSYS_SIMDIR] {
+ set QSYS_SIMDIR "./../"
+} elseif { ![ string match "" $QSYS_SIMDIR ] } {
+ set QSYS_SIMDIR "$QSYS_SIMDIR"
+}
+
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib ./libraries/
+ensure_lib ./libraries/work/
+vmap work ./libraries/work/
+if { ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] } {
+ ensure_lib ./libraries/altera_ver/
+ vmap altera_ver ./libraries/altera_ver/
+ ensure_lib ./libraries/lpm_ver/
+ vmap lpm_ver ./libraries/lpm_ver/
+ ensure_lib ./libraries/sgate_ver/
+ vmap sgate_ver ./libraries/sgate_ver/
+ ensure_lib ./libraries/altera_mf_ver/
+ vmap altera_mf_ver ./libraries/altera_mf_ver/
+ ensure_lib ./libraries/altera_lnsim_ver/
+ vmap altera_lnsim_ver ./libraries/altera_lnsim_ver/
+ ensure_lib ./libraries/stratixiv_hssi_ver/
+ vmap stratixiv_hssi_ver ./libraries/stratixiv_hssi_ver/
+ ensure_lib ./libraries/stratixiv_pcie_hip_ver/
+ vmap stratixiv_pcie_hip_ver ./libraries/stratixiv_pcie_hip_ver/
+ ensure_lib ./libraries/stratixiv_ver/
+ vmap stratixiv_ver ./libraries/stratixiv_ver/
+ ensure_lib ./libraries/altera/
+ vmap altera ./libraries/altera/
+ ensure_lib ./libraries/lpm/
+ vmap lpm ./libraries/lpm/
+ ensure_lib ./libraries/sgate/
+ vmap sgate ./libraries/sgate/
+ ensure_lib ./libraries/altera_mf/
+ vmap altera_mf ./libraries/altera_mf/
+ ensure_lib ./libraries/altera_lnsim/
+ vmap altera_lnsim ./libraries/altera_lnsim/
+ ensure_lib ./libraries/stratixiv_hssi/
+ vmap stratixiv_hssi ./libraries/stratixiv_hssi/
+ ensure_lib ./libraries/stratixiv_pcie_hip/
+ vmap stratixiv_pcie_hip ./libraries/stratixiv_pcie_hip/
+ ensure_lib ./libraries/stratixiv/
+ vmap stratixiv ./libraries/stratixiv/
+}
+ensure_lib ./libraries/ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0/
+vmap ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0 ./libraries/ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0/
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+ echo "\[exec\] dev_com"
+ if { ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] } {
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_primitives.v" -work altera_ver
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/220model.v" -work lpm_ver
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/sgate.v" -work sgate_ver
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_mf.v" -work altera_mf_ver
+ vlog -sv "/home/software/Altera/11.1/quartus/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv" -work altera_lnsim_ver
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_hssi_atoms.v" -work stratixiv_hssi_ver
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_pcie_hip_atoms.v" -work stratixiv_pcie_hip_ver
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_atoms.v" -work stratixiv_ver
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_syn_attributes.vhd" -work altera
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_standard_functions.vhd" -work altera
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_primitives_components.vhd" -work altera
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_primitives.vhd" -work altera
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/220pack.vhd" -work lpm
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/220model.vhd" -work lpm
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/sgate_pack.vhd" -work sgate
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/sgate.vhd" -work sgate
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_mf.vhd" -work altera_mf
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_hssi_components.vhd" -work stratixiv_hssi
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_hssi_atoms.vhd" -work stratixiv_hssi
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_pcie_hip_components.vhd" -work stratixiv_pcie_hip
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_pcie_hip_atoms.vhd" -work stratixiv_pcie_hip
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_atoms.vhd" -work stratixiv
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_components.vhd" -work stratixiv
+ }
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+ echo "\[exec\] com"
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/altera_xcvr_functions.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/altera_xcvr_functions.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/altera_xcvr_xaui.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/hxaui_csr_h.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/hxaui_csr.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_mgmt2dec_phyreconfig.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_mgmt2dec_xaui.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/altera_xcvr_xaui.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/hxaui_csr_h.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/hxaui_csr.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec_phyreconfig.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec_xaui.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/alt_pma_ch_controller_tgx.v" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_pma_ch_controller_tgx.v" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/alt_pma_controller_tgx.v" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_pma_controller_tgx.v" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_reset_ctrl_lego.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_reset_ctrl_tgx_cdrauto.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_resync.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_csr_common_h.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_csr_common.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_csr_pcs8g_h.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_csr_pcs8g.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_csr_selector.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_mgmt2dec.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/altera_wait_generate.v" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_reset_ctrl_lego.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_reset_ctrl_tgx_cdrauto.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_resync.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_csr_common_h.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_csr_common.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_csr_pcs8g_h.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_csr_pcs8g.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_csr_selector.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/altera_wait_generate.v" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/hxaui_alt4gxb.v" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/hxaui_alt4gxb.v" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/hxaui.v" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/hxaui.v" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/siv_xcvr_xaui.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/siv_xcvr_xaui.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_reconfig_h.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_h.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_reconfig_siv.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_siv.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_reconfig_analog.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_analog.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_reconfig_analog_tgx.v" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_analog_tgx.v" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_reconfig_offset_cancellation.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_offset_cancellation.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_reconfig_offset_cancellation_tgx.v" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_offset_cancellation_tgx.v" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_reconfig_eyemon_tgx.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_eyemon_tgx.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_reconfig_dfe_tgx.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_dfe_tgx.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_reconfig_basic_tgx.v" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/alt_mutex_acq.v" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/alt_dprio.v" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_basic_tgx.v" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_mutex_acq.v" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_dprio.v" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_arbiter.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_m2s.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_arbiter.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_m2s.sv" -work ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0
+ vcom "$QSYS_SIMDIR/ip_stratixiv_phy_xaui_0.vhd"
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+ echo "\[exec\] elab"
+ vsim -t ps -L work -L ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0 -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixiv_hssi_ver -L stratixiv_pcie_hip_ver -L stratixiv_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L stratixiv_hssi -L stratixiv_pcie_hip -L stratixiv $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with novopt option
+alias elab_debug {
+ echo "\[exec\] elab_debug"
+ vsim -novopt -t ps -L work -L ip_stratixiv_phy_xaui_0_ip_stratixiv_phy_xaui_0 -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixiv_hssi_ver -L stratixiv_pcie_hip_ver -L stratixiv_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L stratixiv_hssi -L stratixiv_pcie_hip -L stratixiv $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+ dev_com
+ com
+ elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -novopt
+alias ld_debug "
+ dev_com
+ com
+ elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+ echo "List Of Command Line Aliases"
+ echo
+ echo "dev_com -- Compile device library files"
+ echo
+ echo "com -- Compile the design files in correct order"
+ echo
+ echo "elab -- Elaborate top level design"
+ echo
+ echo "elab_debug -- Elaborate the top level design with novopt option"
+ echo
+ echo "ld -- Compile all the design files and elaborate the top level design"
+ echo
+ echo "ld_debug -- Compile all the design files and elaborate the top level design with -novopt"
+ echo
+ echo
+ echo
+ echo "List Of Variables"
+ echo
+ echo "TOP_LEVEL_NAME -- Top level module name."
+ echo
+ echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
+ echo
+ echo "QSYS_SIMDIR -- Qsys base simulation directory."
+}
+h
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft.qip b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft.qip
new file mode 100644
index 0000000000000000000000000000000000000000..b780b77d75b1615fd18d486d844a342c76df74eb
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft.qip
@@ -0,0 +1,72 @@
+set_global_assignment -entity "ip_stratixiv_phy_xaui_soft" -library "lib_ip_stratixiv_phy_xaui_soft" -name IP_TOOL_NAME "altera_xcvr_xaui"
+set_global_assignment -entity "ip_stratixiv_phy_xaui_soft" -library "lib_ip_stratixiv_phy_xaui_soft" -name IP_TOOL_VERSION "11.1sp2"
+set_global_assignment -entity "ip_stratixiv_phy_xaui_soft" -library "lib_ip_stratixiv_phy_xaui_soft" -name IP_TOOL_ENV "mwpim"
+
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VHDL_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft.vhd]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/altera_xcvr_functions.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_pma_functions.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/altera_xcvr_xaui.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/hxaui_csr_h.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/hxaui_csr.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_mgmt2dec_phyreconfig.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_mgmt2dec_xaui.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_pma_ch_controller_tgx.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_pma_controller_tgx.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_reset_ctrl_lego.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_reset_ctrl_tgx_cdrauto.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_resync.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_common_h.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_common.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_pcs8g_h.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_pcs8g.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_selector.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_mgmt2dec.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/altera_wait_generate.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_pcs.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_reset.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_8b10b_dec.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_channel_synch.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_deskew.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_deskew_channel.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_deskew_ram.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_invalid_code_det.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_parity.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_parity_4b.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_parity_6b.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_rate_match.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_rate_match_ram.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_rl_chk_6g.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_rx_sm.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_tx.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_tx_8b10b_enc.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_tx_idle_conv.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/l_modules.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/serdes_4_unit_lc_siv.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/serdes_4_unit_siv.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/serdes_4unit.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_soft_xaui_pcs.ocp]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/sxaui.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/siv_xcvr_low_latency_phy_nr.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/siv_xcvr_xaui.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name QIP_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xaui_phy_assignments.qip]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SDC_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xaui_phy_top.sdc]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_h.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_siv.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_analog.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_analog_tgx.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_offset_cancellation.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_offset_cancellation_tgx.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_eyemon_tgx.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_dfe_tgx.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_basic_tgx.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_mutex_acq.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name VERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_dprio.v]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_arbiter.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/alt_xcvr_m2s.sv]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/plain_files.txt]
+set_global_assignment -library "lib_ip_stratixiv_phy_xaui_soft" -name SOURCE_FILE [file join $::quartus(qip_path) ip_stratixiv_phy_xaui_soft/qencrypt_files.txt]
+
+set_global_assignment -entity "altera_xcvr_xaui" -library "lib_ip_stratixiv_phy_xaui_soft" -name IP_TOOL_NAME "altera_xcvr_xaui"
+set_global_assignment -entity "altera_xcvr_xaui" -library "lib_ip_stratixiv_phy_xaui_soft" -name IP_TOOL_VERSION "11.1"
+set_global_assignment -entity "altera_xcvr_xaui" -library "lib_ip_stratixiv_phy_xaui_soft" -name IP_TOOL_ENV "mwpim"
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_dprio.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_dprio.v
new file mode 100644
index 0000000000000000000000000000000000000000..c8cb550d6c519e9fddf949f789fe95544e45690e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_dprio.v
@@ -0,0 +1,199 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"{-to addr_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to wr_out_data_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to rd_out_data_shift_reg[13]} DPRIO_INTERFACE_REG=ON;{-to in_data_shift_reg[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[1]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[2]} DPRIO_INTERFACE_REG=ON"} *)
+module alt_dprio (
+ input wire [15:0] address,
+ output wire busy,
+ input wire [15:0] datain,
+ output wire [15:0] dataout,
+ input wire dpclk,
+ output wire dpriodisable,
+ output wire dprioin,
+ output wire dprioload,
+ input wire dprioout,
+ input wire [6:0] quad_address,
+ input wire rden,
+ input wire wren,
+ input wire wren_data
+ );
+
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [31:0] addr_shift_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [15:0] in_data_shift_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [15:0] rd_out_data_shift_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [2:0] startup_cntr;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg [2:0] state_mc_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [31:0] wr_out_data_shift_reg;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg [5:0] state_mc_counter_q;
+
+ wire pre_amble_cmpr_agb;
+ wire [7:0] state_mc_decode_eq;
+ wire dprioin_mux_dataout;
+ wire busy_state;
+ wire idle_state;
+ wire rd_addr_done;
+ wire rd_addr_state;
+ wire rd_data_done;
+ wire rd_data_input_state;
+ wire rd_data_output_state;
+ wire rd_data_state;
+ wire rdinc;
+ wire read_state;
+ wire s0_to_0;
+ wire s0_to_1;
+ wire s1_to_0;
+ wire s1_to_1;
+ wire s2_to_0;
+ wire s2_to_1;
+ wire startup_done;
+ wire startup_idle;
+ wire wr_addr_done;
+ wire wr_addr_state;
+ wire wr_data_done;
+ wire wr_data_state;
+ wire write_state;
+ wire [2:0] startup_cntr_d;
+ wire [2:0] startup_cntr_ena;
+
+ // synopsys translate_off
+ initial
+ begin
+ addr_shift_reg = 0;
+ in_data_shift_reg = 0;
+ rd_out_data_shift_reg = 0;
+ startup_cntr[2:0] = 3'b0;
+ state_mc_reg = 0;
+ wr_out_data_shift_reg = 0;
+ state_mc_counter_q = 6'b0;
+ end
+ // synopsys translate_on
+
+ always @ (posedge dpclk)
+ begin
+ if (state_mc_counter_q == 6'b011111)
+ begin
+ addr_shift_reg <= {{2{{2{1'b0}}}}, {3{1'b0}}, quad_address, 2'b10, address};
+ rd_out_data_shift_reg <= {{2{1'b0}}, {2{1'b1}}, {3{1'b0}}, quad_address, 2'b10};
+ wr_out_data_shift_reg <= {{2{1'b0}}, 2'b01, {3{1'b0}}, quad_address, 2'b10, datain};
+ end
+ else begin
+ addr_shift_reg <= {addr_shift_reg[30:0], 1'b0};
+ rd_out_data_shift_reg <= {rd_out_data_shift_reg[14:0], 1'b0};
+ wr_out_data_shift_reg <= {wr_out_data_shift_reg[30:0], 1'b0};
+ end
+
+ if (rd_data_input_state == 1'b1)
+ in_data_shift_reg <= {in_data_shift_reg[14:0], dprioout};
+ end
+
+ always @ (posedge dpclk)
+ begin
+ if (startup_cntr_ena[0] == 1'b1)
+ startup_cntr[0] <= startup_cntr_d[0];
+ if (startup_cntr_ena[1:1] == 1'b1)
+ startup_cntr[1] <= startup_cntr_d[1];
+ if (startup_cntr_ena[2:2] == 1'b1)
+ startup_cntr[2] <= startup_cntr_d[2];
+ end
+
+ assign startup_cntr_d = {(startup_cntr[2] ^ (startup_cntr[1] & startup_cntr[0])), (startup_cntr[0] ^ startup_cntr[1]), (~ startup_cntr[0])};
+ assign startup_cntr_ena = {3{((((rden | wren) | rdinc) | (~ startup_idle)) & (~ startup_done))}};
+
+ always @ ( posedge dpclk)
+ begin
+ state_mc_reg <= {(s2_to_1 | (((~ s2_to_0) & (~ s2_to_1)) & state_mc_reg[2])), (s1_to_1 | (((~ s1_to_0) & (~ s1_to_1)) & state_mc_reg[1])), (s0_to_1 | (((~ s0_to_0) & (~ s0_to_1)) & state_mc_reg[0]))};
+ end
+
+ always @(posedge dpclk)
+ begin
+ if (write_state | read_state)
+ begin
+ if (state_mc_counter_q == 6'b111111)
+ state_mc_counter_q <= 6'b0;
+ else
+ state_mc_counter_q <= state_mc_counter_q[5:0] + 6'b1;
+ end
+ end
+
+ lpm_decode #(
+ .lpm_decodes (8),
+ .lpm_width (3),
+ .lpm_type ("lpm_decode"))
+ state_mc_decode(
+ .data(state_mc_reg),
+ .eq(state_mc_decode_eq)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .clken(1'b1),
+ .clock(1'b0),
+ .enable(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+
+ or(dprioin_mux_dataout, ((((((wr_addr_state | rd_addr_state) & addr_shift_reg[31]) & pre_amble_cmpr_agb) | ((~ pre_amble_cmpr_agb) & (wr_addr_state | rd_addr_state))) | (((wr_data_state & wr_out_data_shift_reg[31]) & pre_amble_cmpr_agb) | ((~ pre_amble_cmpr_agb) & wr_data_state))) | (((rd_data_output_state & rd_out_data_shift_reg[15]) & pre_amble_cmpr_agb) | ((~ pre_amble_cmpr_agb) & rd_data_output_state))), ~(((write_state | rd_addr_state) | rd_data_output_state)));
+
+ assign
+ pre_amble_cmpr_agb = (state_mc_counter_q > 6'b011111),
+ busy = busy_state,
+ busy_state = (write_state | read_state),
+ dataout = in_data_shift_reg,
+ dpriodisable = (~ (startup_cntr[2] & (startup_cntr[0] | startup_cntr[1]))),
+ dprioin = dprioin_mux_dataout,
+ dprioload = (~ ((startup_cntr[0] ^ startup_cntr[1]) & (~ startup_cntr[2]))),
+ idle_state = state_mc_decode_eq[0],
+
+ rd_addr_done = (rd_addr_state & (state_mc_counter_q == 6'b111111)),
+
+ rd_addr_state = (state_mc_decode_eq[5] & startup_done),
+ rd_data_done = (rd_data_state & (state_mc_counter_q == 6'b111111)),
+
+ rd_data_input_state = ((state_mc_counter_q >= 6'b110000) & rd_data_state),
+
+ rd_data_output_state = (state_mc_counter_q < 6'b110000 & rd_data_state),
+ rd_data_state = (state_mc_decode_eq[7] & startup_done),
+ rdinc = 1'b0,
+ read_state = (rd_addr_state | rd_data_state),
+ s0_to_0 = ((wr_data_state & wr_data_done) | (rd_data_state & rd_data_done)),
+ s0_to_1 = (((idle_state & (wren | ((~ wren) & ((rden | rdinc) | wren_data)))) | (wr_addr_state & wr_addr_done)) | (rd_addr_state & rd_addr_done)),
+ s1_to_0 = (((wr_data_state & wr_data_done) | (rd_data_state & rd_data_done)) | (idle_state & (wren | (((~ wren) & (~ wren_data)) & rden)))),
+ s1_to_1 = (((idle_state & ((~ wren) & (rdinc | wren_data))) | (wr_addr_state & wr_addr_done)) | (rd_addr_state & rd_addr_done)),
+ s2_to_0 = ((((wr_addr_state & wr_addr_done) | (wr_data_state & wr_data_done)) | (rd_data_state & rd_data_done)) | (idle_state & (wren | wren_data))),
+ s2_to_1 = ((idle_state & (((~ wren) & (~ wren_data)) & (rdinc | rden))) | (rd_addr_state & rd_addr_done)),
+ startup_done = ((startup_cntr[2] & (~ startup_cntr[0])) & startup_cntr[1]),
+ startup_idle = ((~ startup_cntr[0]) & (~ (startup_cntr[2] ^ startup_cntr[1]))),
+
+ wr_addr_done = (wr_addr_state & (state_mc_counter_q == 6'b111111)),
+
+ wr_addr_state = (state_mc_decode_eq[1] & startup_done),
+
+ wr_data_done = (wr_data_state & (state_mc_counter_q == 6'b111111)),
+
+ wr_data_state = (state_mc_decode_eq[3] & startup_done),
+ write_state = (wr_addr_state | wr_data_state);
+endmodule //alt_dprio
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_mutex_acq.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_mutex_acq.v
new file mode 100644
index 0000000000000000000000000000000000000000..c5d020f703904fbb94916ef75bd1fda144424ba9
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_mutex_acq.v
@@ -0,0 +1,221 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_mutex_acq #(
+ parameter mutex_wait_time = 101,
+ parameter mutex_wait_time_cntr_width = 7, // do we need this parameter?
+ parameter addr_width = 5,
+ parameter data_width = 32,
+ parameter read_mutex_addr_offset = 0 // address of the mutex word
+)
+(
+
+input wire clk, // this will be the reconfig clk
+input wire reset,
+
+// Internal interface for the bigger controlling module, like analog reconfig
+input wire [addr_width-1:0] address, // MM address
+input wire [data_width-1:0] writedata,
+input wire write,
+input wire read,
+output reg waitrequest, // can use to tell internal master to wait when auto-request+release
+output wire [data_width-1:0] readdata,
+
+
+// MM master external interface, that connects to mutex-slave, like the reconfig_basic block
+output wire [addr_width-1:0] master_address, // MM address
+output wire [data_width-1:0] master_writedata,
+output wire master_write,
+output wire master_read,
+input wire master_waitrequest, // needed for a valid master interface
+input wire [data_width-1:0] master_readdata, // from mutex-slave
+
+
+
+// request mutex access and should be held high as long as mutex is used
+input wire mutex_req,
+// output indicating whether mutex access was granted or not
+output reg mutex_grant
+
+);
+
+
+
+localparam IDLE = 2'b00;
+localparam GET_MUTEX = 2'b01;
+localparam RELEASE_MUTEX = 2'b10;
+
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [9:0] mutex_timeout_cntr;
+
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *) // should we make this variable
+reg [mutex_wait_time_cntr_width-1:0] mutex_wait_cntr;
+
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [addr_width-1:0] mutex_int_address; // MM address
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [data_width-1:0] mutex_int_writedata;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg mutex_int_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg mutex_int_read;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg do_base_readwrite;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
+reg mutex_mux_ctrl;
+
+// synopsys translate_off
+initial
+begin
+ mutex_grant = 0;
+ mutex_mux_ctrl = 1'b1;
+ mutex_timeout_cntr = 0;
+ mutex_wait_cntr = 0;
+ mutex_int_address = 0;
+ mutex_int_writedata = 0;
+ mutex_int_read = 0;
+ mutex_int_write = 0;
+ waitrequest = 0;
+ do_base_readwrite = 0;
+ state = 0;
+end
+// synopsys translate_on
+
+always @(posedge clk or posedge reset)
+begin
+ if (reset === 1'b1)
+ begin
+ mutex_grant <= 0;
+ mutex_mux_ctrl <= 1'b1;
+ mutex_timeout_cntr <= 0;
+ mutex_wait_cntr <= 0;
+ mutex_int_address <= 'b0;
+ mutex_int_writedata <= 'b0;
+ mutex_int_read <= 'b0;
+ mutex_int_write <= 'b0;
+ waitrequest <= 'b0;
+ do_base_readwrite <= 'b0;
+ state <= 'b0;
+ end
+ else begin
+ case (state)
+ IDLE:begin
+// fix SPR:343567 - Avalon slaves are permitted to keep waitrequest asserted during idle cycles.
+// The state machine will still work correctly by simply removing this condition.
+// The next state is GET_MUTEX, and it will wait there if waitrequest is legitimately asserted.
+// if (master_waitrequest == 1'b1)
+// state <= IDLE; // wait till the waitrequest goes low
+// else if (mutex_grant == 0 &&
+ if (mutex_grant == 0 &&
+ (mutex_req == 1'b1 || write == 1'b1 || read == 1'b1))
+ begin
+ state <= GET_MUTEX;
+ mutex_int_read <= 1'b1;
+ mutex_int_address <= read_mutex_addr_offset;
+ mutex_int_write <= 1'b0;
+ mutex_wait_cntr <= 0;
+ mutex_mux_ctrl <= 1'b1;
+ waitrequest <= 1'b1; // pull the waitrequest high
+ if (write == 1'b1 || read == 1'b1)
+ do_base_readwrite <= 1'b1;
+ else
+ do_base_readwrite <= 1'b0;
+ end
+ else if (mutex_grant == 1'b1)
+ begin
+ do_base_readwrite <= 1'b0;
+ if (mutex_req == 1'b1 || write == 1'b1 || read == 1'b1)
+ begin
+ mutex_mux_ctrl <= 1'b0; // relinquish control of the mux
+ if (write == 1'b1 || read == 1'b1)
+ waitrequest <= master_waitrequest;
+ else
+ waitrequest <= 1'b0;
+ if (read == 1'b1 || write == 1'b1)
+ mutex_timeout_cntr <= 0;
+ else if (mutex_timeout_cntr == 10'd1000)
+ state <= RELEASE_MUTEX;
+ else
+ mutex_timeout_cntr <= mutex_timeout_cntr[9:0] + 10'b1;
+ end
+ else
+ state <= RELEASE_MUTEX;
+ end
+ else
+ begin
+ mutex_mux_ctrl <= 1'b1; // choke the inputs going to basic as mux is not available
+ mutex_int_read <= 1'b0;
+ mutex_int_write <= 1'b0;
+ waitrequest <= 1'b0;
+ end
+ end
+ RELEASE_MUTEX: begin
+ // release the mutex
+ mutex_mux_ctrl <= 1'b1;
+ mutex_int_read <= 1'b0;
+ mutex_int_write <= 1'b1;
+ mutex_int_address <= read_mutex_addr_offset;
+ mutex_int_writedata <= 16'b0;
+ mutex_grant <= 1'b0;
+ state <= IDLE;
+ mutex_timeout_cntr <= 0;
+ waitrequest <= 1'b0;
+ end
+ GET_MUTEX: begin
+ if (master_waitrequest == 1'b1) // wait in this state itself
+ begin
+ state <= GET_MUTEX;
+ end
+ else if (mutex_int_read == 1'b1 && master_readdata[0] == 1'b0) // check mutex bit
+ begin
+ mutex_grant <= 1; // mutex is available
+ state <= IDLE;
+ mutex_int_read <= 1'b0; // reset the read and mux ctrl bits
+ mutex_mux_ctrl <= 0;
+ if (do_base_readwrite == 1'b1)
+ waitrequest <= master_waitrequest;
+ else
+ waitrequest <= 1'b0;
+ end
+ else if (mutex_wait_cntr != mutex_wait_time)
+ begin // continue waiting till the wait time is hit
+ mutex_wait_cntr <= mutex_wait_cntr[mutex_wait_time_cntr_width-1:0] + 1;
+ mutex_int_read <= 1'b0; // pull down the read
+ state <= GET_MUTEX;
+ end
+ else // try and read again
+ begin
+ mutex_wait_cntr <= 0; // reset the wait cntr and try and read again
+ mutex_int_read <= 1'b1;
+ state <= GET_MUTEX;
+ end
+ end
+ default: begin
+ state <= IDLE;
+ end
+ endcase
+ end
+
+end
+
+
+assign master_address = mutex_mux_ctrl ? mutex_int_address : address;
+assign master_writedata = mutex_mux_ctrl ? mutex_int_writedata : writedata;
+assign master_write = mutex_mux_ctrl ? mutex_int_write : write;
+assign master_read = mutex_mux_ctrl ? mutex_int_read : read;
+assign readdata = master_readdata; // pipe the readdata out
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_pma_ch_controller_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_pma_ch_controller_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..6347c1ae0190510fae1e3cec2d4c58e3c11c0d34
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_pma_ch_controller_tgx.v
@@ -0,0 +1,164 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ns/10ps
+module alt_pma_ch_controller_tgx #(
+ parameter
+ number_of_channels = 4,
+ sys_clk_in_mhz = 50, // used to calculate internal delays in terms of system clock cycles
+ manual_reset = "false",
+ sync_depth =2
+ )
+ (
+ //controller standard interface to user
+ input tri0 rst, // controller logic reset
+// input wire powerdown_all, // save power
+ input tri0 rx_rst_digital, // tx_digitalreset
+ input tri0 tx_rst_digital, // rx_digitalreset
+ output wire tx_pma_ready, // pma tx pll_locked
+ output wire rx_pma_ready, // pma rx pll is locked to data
+ input tri0 tx_cal_busy, // tx calibration in progress
+ input tri0 rx_cal_busy, // rx calibration in progress
+ input tri1 pll_locked, // tx pll_locked
+
+ // user data (avalon-MM formatted)
+ input wire clk,
+ input tri0 [5:0] ch_mgmt_address,
+ input tri1 ch_mgmt_read,
+ output wire [31:0] ch_mgmt_readdata,
+ input tri0 ch_mgmt_write,
+ input tri0 [31:0] ch_mgmt_writedata,
+ output wire ch_mgmt_waitrequest,
+
+ input tri1 [number_of_channels-1:0] rx_is_lockedtodata,
+ input tri1 [number_of_channels-1:0] rx_is_lockedtoref,
+
+ output wire [number_of_channels-1:0] rx_set_locktodata,
+ output wire [number_of_channels-1:0] rx_set_locktoref,
+ output wire [number_of_channels-1:0] rx_seriallpbken,
+
+ output wire [number_of_channels-1:0] rx_analog_rst,
+ output wire [number_of_channels-1:0] tx_digital_rst,
+ output wire [number_of_channels-1:0] rx_digital_rst,
+ output wire pll_powerdown
+);
+ // reset controller outputs
+ wire reset_controller_tx_ready;
+ wire reset_controller_rx_ready;
+ wire reset_controller_pll_powerdown;
+ wire reset_controller_tx_digitalreset;
+ wire reset_controller_rx_analogreset;
+ wire reset_controller_rx_digitalreset;
+ wire reset_controller_manual_mode;
+
+ // Control & status register map (CSR) outputs
+ wire csr_reset_tx_digital; // to reset controller
+ wire csr_reset_rx_digital; // to reset controller
+ wire csr_reset_all; // to reset controller
+ wire csr_pll_powerdown;
+ wire [number_of_channels - 1 : 0] csr_tx_digitalreset; // to xcvr instance
+ wire [number_of_channels - 1 : 0] csr_rx_analogreset; // to xcvr instance
+ wire [number_of_channels - 1 : 0] csr_rx_digitalreset; // to xcvr instance
+ wire [number_of_channels - 1 : 0] csr_phy_loopback_serial; // to xcvr instance
+ wire [number_of_channels - 1 : 0] csr_rx_set_locktoref; // to xcvr instance
+ wire [number_of_channels - 1 : 0] csr_rx_set_locktodata; // to xcvr instance
+
+
+ ///////////////////////////////////////////////////////////////////
+
+ // Implement waitrequest to match previous implementation
+ altera_wait_generate wait_gen(
+ .rst(rst),
+ .clk(clk),
+ .launch_signal(ch_mgmt_read),
+ .wait_req(ch_mgmt_waitrequest)
+ );
+ // Instantiate memory map logic for given number of lanes & PLL's
+ // Includes all except PCS
+ alt_xcvr_csr_common #(
+ .lanes(number_of_channels),
+ .plls(1)
+ ) csr (
+ .clk(clk),
+ .reset(rst),
+ .address(8'h40 | ch_mgmt_address), // map word 0 of this module to word 64 of alt_xcvr_csr_common
+ .read(ch_mgmt_read),
+ .write(ch_mgmt_write),
+ .writedata(ch_mgmt_writedata),
+ .pll_locked(pll_locked),
+ .rx_is_lockedtoref(rx_is_lockedtoref),
+ .rx_is_lockedtodata(rx_is_lockedtodata),
+ .rx_signaldetect({number_of_channels{1'b0}}),
+ .reset_controller_tx_ready(reset_controller_tx_ready),
+ .reset_controller_rx_ready(reset_controller_rx_ready),
+ .reset_controller_pll_powerdown(reset_controller_pll_powerdown),
+ .reset_controller_tx_digitalreset(reset_controller_tx_digitalreset),
+ .reset_controller_rx_analogreset(reset_controller_rx_analogreset),
+ .reset_controller_rx_digitalreset(reset_controller_rx_digitalreset),
+ .readdata(ch_mgmt_readdata),
+ .csr_reset_tx_digital(csr_reset_tx_digital),
+ .csr_reset_rx_digital(csr_reset_rx_digital),
+ .csr_reset_all(csr_reset_all),
+ .csr_pll_powerdown(csr_pll_powerdown),
+ .csr_tx_digitalreset(csr_tx_digitalreset),
+ .csr_rx_analogreset(csr_rx_analogreset),
+ .csr_rx_digitalreset(csr_rx_digitalreset),
+ .csr_phy_loopback_serial(csr_phy_loopback_serial),
+ .csr_rx_set_locktoref(csr_rx_set_locktoref),
+ .csr_rx_set_locktodata(csr_rx_set_locktodata)
+ );
+
+
+ // Instantiate reset controller for PMA channels
+ alt_reset_ctrl_tgx_cdrauto #(
+ .sys_clk_in_mhz(sys_clk_in_mhz)
+ ) rc (
+ .clock(clk),
+ .reset_all(csr_reset_all),
+ .reset_tx_digital(csr_reset_tx_digital | tx_rst_digital),
+ .reset_rx_digital(csr_reset_rx_digital | rx_rst_digital),
+ .powerdown_all(rst),
+ .tx_ready(reset_controller_tx_ready),
+ .rx_ready(reset_controller_rx_ready),
+ .pll_powerdown (reset_controller_pll_powerdown),
+ .tx_digitalreset(reset_controller_tx_digitalreset),
+ .rx_analogreset(reset_controller_rx_analogreset),
+ .rx_digitalreset(reset_controller_rx_digitalreset),
+ .gxb_powerdown(),
+ .pll_is_locked(pll_locked),
+ .tx_cal_busy(tx_cal_busy),
+ .rx_cal_busy(rx_cal_busy),
+ .rx_is_lockedtodata(&rx_is_lockedtodata),
+ .manual_mode(reset_controller_manual_mode)
+ );
+
+ // Assign outputs from reset controller
+ assign tx_pma_ready = reset_controller_tx_ready;
+ assign rx_pma_ready = reset_controller_rx_ready;
+
+ // Assign outputs from CSR to channel control bits
+ assign rx_set_locktodata = csr_rx_set_locktodata;
+ assign rx_set_locktoref = csr_rx_set_locktoref;
+ assign rx_seriallpbken = csr_phy_loopback_serial;
+
+ assign rx_analog_rst = csr_rx_analogreset;
+ assign tx_digital_rst = csr_tx_digitalreset;
+ assign rx_digital_rst = csr_rx_digitalreset;
+
+ assign reset_controller_manual_mode = (manual_reset == "true") ? 1'b1
+ : (csr_rx_set_locktoref || csr_rx_set_locktodata);
+
+ assign pll_powerdown = csr_pll_powerdown;
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_pma_controller_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_pma_controller_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..614ad6278ca4a3cbbfa013d414c4e6c8410c156e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_pma_controller_tgx.v
@@ -0,0 +1,198 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ns/10ps
+module alt_pma_controller_tgx #(
+ parameter number_of_plls = 1,// One controller only control the possible merged pll. If more pll is needed, user can use multiplier controller for none share plls.
+ parameter tx_pll_reset_hold_time = 0,// ignored - now calculated according to system clock
+ parameter sync_depth = 2,
+ parameter sys_clk_in_mhz = 50 // needed for 1us and 4us delay timers
+)
+(
+ input rst, // controller logic reset
+ output tx_pll_ready,
+
+ // user data (avalon-MM formatted)
+ input wire clk,
+ input wire [1:0] pma_mgmt_address,
+ input wire pma_mgmt_read,
+ output reg [31:0] pma_mgmt_readdata,
+ input wire pma_mgmt_write,
+ input wire [31:0] pma_mgmt_writedata,
+ output wire pma_mgmt_waitrequest,
+
+ // user data (avalon-clock formatted)
+ input wire cal_blk_clk,
+
+ // user data: pll control (avalon-ST formatted)
+ output wire cal_blk_pdn,//sync with cal_blk_clk
+ output wire gx_pdn,//sync with clk
+ output wire [number_of_plls-1:0] pll_pdn, //sync with clk
+ input wire [number_of_plls-1:0] pll_locked //
+);
+
+localparam clk_in_mhz =
+`ifdef QUARTUS__SIMGEN
+ 2; // simulation-only value
+`elsif ALTERA_RESERVED_QIS
+ sys_clk_in_mhz; // use real counter lengths for normal Quartus synthesis
+`else
+ 2; // simulation-only value
+`endif
+localparam t_pll_powerdown = clk_in_mhz; // 1 us minimum
+localparam t_ltd_auto = clk_in_mhz*4; // 4 us minimum
+
+wire [number_of_plls-1:0] pll_locked_sync;
+reg cal_blk_pdn_reg;
+reg read_delay;
+reg gx_pdn_reg;
+reg pll_pdn_resetall_avmm;
+wire pll_pdn_int;
+reg pll_pdn_reg;
+
+wire gx_pdn_int;
+wire gx_pdn_done;
+
+altera_wait_generate wait_gen(
+ .rst(rst),
+.clk(clk),
+.launch_signal(pma_mgmt_read),
+.wait_req(pma_mgmt_waitrequest)
+ );
+
+alt_reset_ctrl_lego
+#(
+.reset_hold_cycles (t_pll_powerdown) // reset pulse length in clock cycles
+) pll_pdn_rst
+(
+.clock(clk),
+.start(1'b1 ),
+.reset(pll_pdn_int),
+.rdone(pll_locked), // reset done signal
+.aclr(rst),
+.sdone(tx_pll_ready) // sequence done for this lego
+);
+
+alt_reset_ctrl_lego
+#(
+.reset_hold_cycles (2) // reset pulse length in clock cycles
+) gx_pdn_rst
+(
+.clock(clk),
+.start(1'b1 ),
+.reset(gx_pdn_int),
+.rdone(1'b1), // reset done signal
+.aclr(rst),
+.sdone(gx_pdn_done) // sequence done for this lego
+);
+
+assign pll_pdn= pll_pdn_reg | {number_of_plls{pll_pdn_int}} ;
+
+initial
+begin
+ pll_pdn_reg <= 0;
+end
+always @ (posedge clk, posedge rst)
+begin
+ if(rst) begin
+ pll_pdn_reg <= 1'b0;
+ end
+ else if (pma_mgmt_write==1'b1 & pma_mgmt_address==2'b00) begin
+ pll_pdn_reg <= pma_mgmt_writedata[number_of_plls -1 :0];
+ end
+end
+
+initial
+begin
+ pma_mgmt_readdata <= 0;
+end
+always @ (posedge clk, posedge rst)
+begin
+ if(rst) begin
+ pma_mgmt_readdata <= 0;
+ end
+ else if (pma_mgmt_read==1'b1 & pma_mgmt_address==2'b00) begin
+ pma_mgmt_readdata[number_of_plls -1 :0] <= pll_pdn;
+ end
+ else if (pma_mgmt_read==1'b1 & pma_mgmt_address==2'b01) begin
+ pma_mgmt_readdata[0] <= cal_blk_pdn_reg;
+ pma_mgmt_readdata[1] <= gx_pdn;
+ end
+ else if (pma_mgmt_read==1'b1 & pma_mgmt_address==2'b10) begin
+ pma_mgmt_readdata[number_of_plls -1 :0] <= pll_locked_sync;
+ end
+ else
+ pma_mgmt_readdata <= 0;
+end
+
+generate
+genvar i;
+for (i=0; i<number_of_plls; i=i+1)
+begin: lock_sync
+ altera_std_synchronizer
+ #(
+ .depth (sync_depth) // reset pulse length in clock cycles
+ )stdsync
+ (
+ .clk(clk),
+ .din(pll_locked[i]),
+ .dout(pll_locked_sync[i]),
+ .reset_n((~ rst))
+ );
+end
+endgenerate
+
+initial
+begin
+ cal_blk_pdn_reg <= 0;
+end
+always @ (posedge clk, posedge rst)
+begin
+ if(rst) begin
+ cal_blk_pdn_reg <= 0;
+ end
+ else if (pma_mgmt_write==1'b1 & pma_mgmt_address==2'b01) begin
+ cal_blk_pdn_reg <= pma_mgmt_writedata[0];
+ end
+end
+altera_std_synchronizer
+#(
+ .depth (sync_depth) // reset pulse length in clock cycles
+)stdsync
+(
+ .clk(cal_blk_clk),
+ .din(cal_blk_pdn_reg),
+ .dout(cal_blk_pdn),
+ .reset_n((~ rst))
+);
+
+assign gx_pdn = gx_pdn_reg | gx_pdn_int;
+initial
+begin
+ gx_pdn_reg <= 0;
+end
+always @ (posedge clk, posedge rst)
+begin
+ if(rst) begin
+ gx_pdn_reg <= 0;
+ end
+ else if (pma_mgmt_write==1'b1 & pma_mgmt_address==2'b01) begin
+ gx_pdn_reg <= pma_mgmt_writedata[1];
+ end
+ else begin
+ gx_pdn_reg <= gx_pdn_reg;
+ end
+
+end
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_pma_functions.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_pma_functions.sv
new file mode 100644
index 0000000000000000000000000000000000000000..3b2ad149729abe8a029617dbbf1964bb6ce925dc
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_pma_functions.sv
@@ -0,0 +1,73 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common functions for PMA serdes
+//
+// $Header$
+//
+// PACKAGE DECLARATION
+package alt_pma_functions;
+
+ // convert "xx.xxx MHz" to ps
+ function integer freq2ps;
+ input [8*16:1] s;
+
+ integer in_freq_khz;
+ integer period_ps;
+
+ in_freq_khz = mega2k(s);
+ freq2ps = 1000000000/(in_freq_khz);
+ endfunction
+
+
+ // convert "xx.xxx MHz" string to integer with hz as unit
+ function integer mega2k;
+ input [8*16:1] s;
+
+ reg [8*16:1] reg_s;
+ reg [8:1] digit;
+ reg [8:1] tmp;
+ integer m, magnitude;
+ integer final_mag;
+ integer unit_mag;
+ integer point_pos;
+
+ begin
+ magnitude = 0;
+ reg_s = s;
+ unit_mag = 1000000;
+ point_pos = 0;
+ for (m=1; m<=16; m=m+1)
+ begin
+ tmp = reg_s[128:121];
+ digit = tmp & 8'b00001111;
+ reg_s = reg_s << 8;
+ // Accumulate ascii digits 0-9 only.
+ if (tmp == 77)
+ unit_mag = 1000; // Found a 'M' character, Mhz
+ if (tmp == 46)
+ point_pos = 1; // Found a '.' character, point
+ if ((tmp>=48) && (tmp<=57)) begin
+ magnitude = (magnitude * 10) + digit;
+ point_pos = point_pos *10;
+ end
+ end
+ if(point_pos > 0)
+ mega2k = magnitude*unit_mag/point_pos;
+ else
+ mega2k = magnitude*unit_mag;
+ end
+ endfunction
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_reset_ctrl_lego.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_reset_ctrl_lego.sv
new file mode 100644
index 0000000000000000000000000000000000000000..38d99a0658aa5380a62046e68a3b66cb9158881b
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_reset_ctrl_lego.sv
@@ -0,0 +1,265 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Reset controller building block.
+//
+// Handles a single reset stage. Can be daisy-chained with other blocks for purely sequential resets.
+// Options include reset pulse length in clock cycles, and a counter for sdone stability checking.
+//
+// $Header$
+//
+
+`timescale 1 ns / 1 ns
+
+module alt_reset_ctrl_lego
+#(
+ parameter reset_hold_til_rdone = 0, // 1 means reset stays high until rdone arrives
+ // 0 means fixed pulse length, defined by reset_hold_cycles
+ parameter reset_hold_cycles = 1, // reset pulse length in clock cycles
+ parameter sdone_delay_cycles = 0, // optional delay from rdone received til sdone sent to next block
+ parameter rdone_is_edge_sensitive = 0 // default is level sensitive rdone
+)
+(
+ // clocks and PLLs
+ input wire clock,
+ input wire start,
+ input tri0 aclr, // active-high asynchronous reset
+ output wire reset,
+ input tri1 rdone, // reset done signal
+ output reg sdone // sequence done for this lego
+);
+ localparam max_precision = 32; // VCS requires this declaration outside the function
+ function integer ceil_log2;
+ input [max_precision-1:0] input_num;
+ integer i;
+ reg [max_precision-1:0] try_result;
+ begin
+ i = 0;
+ try_result = 1;
+ while ((try_result << i) < input_num && i < max_precision)
+ i = i + 1;
+ ceil_log2 = i;
+ end
+ endfunction
+
+ // How many bits are needed for 'reset_hold_cycles' counter?
+ localparam rhc_bits = ceil_log2(reset_hold_cycles);
+ localparam rhc_load_constant = (1 << rhc_bits) | (reset_hold_cycles-1);
+ // How many bits are needed for 'sdone_delay_cycles' counter?
+ localparam sdc_bits = ceil_log2(sdone_delay_cycles);
+ localparam sdc_load_constant = (1 << sdc_bits)
+ | ((rdone_is_edge_sensitive == 1 && sdone_delay_cycles > 1) ? sdone_delay_cycles-2 : sdone_delay_cycles-1);
+ localparam sdone_stable_cycles = (sdone_delay_cycles > 1 ? sdone_delay_cycles+1 : 0);
+
+ wire spulse; // synchronous detection of 'start' 0-to-1 transition
+ wire rhold;
+ wire timed_reset_in_progress;
+ wire rinit_next; // combinatorial input to rinit DFF
+ wire rdonei; // internal selector between rdone and rdsave (rdone_is_edge_sensitive==1)
+ wire rdpulse; // synchronous detection of 'rdone' 0-to-1 transition, when rdone_is_edge_sensitive==1
+
+ reg zstart = 0; // delayed value of 'start' input, used for detection of 0-to-1 transition
+ reg rinit = 0; // state bit that indicates sequence is in progress
+
+ initial begin
+ sdone = 0; // 1 indicates sequence is done
+ end
+
+
+ // 'start' input, detect 0-to-1 transition that triggers sequence
+ assign spulse = start & ~zstart;
+ always @(posedge clock or posedge aclr)
+ if (aclr == 1'b1)
+ zstart <= 0;
+ else
+ zstart <= start;
+
+ // rinit state bit, triggered by spulse, waits while rhold = 1
+ assign rinit_next = spulse | (rinit & (rhold | ~rdonei | rdpulse)) | timed_reset_in_progress;
+ always @(posedge clock or posedge aclr)
+ if (aclr == 1'b1)
+ rinit <= 0;
+ else
+ rinit <= rinit_next;
+
+ // optional internal 'rdone' generation logic, if rdone_is_edge_sensitive==1
+ generate
+ if (rdone_is_edge_sensitive == 0) begin
+ assign rdpulse = 0;
+ assign rdonei = rdone;
+ end
+ else begin
+ // instantiate synchronous edge-detection logic for rdone
+ reg zrdone = 0; // for edge-sensitive rdone, detect 0-to-1 transition synchronously
+ reg rdsave = 0; // for edge-sensitive rdone, use this as internal rdone
+ always @(posedge clock or posedge aclr) begin
+ if (aclr == 1'b1) begin
+ zrdone <= 0;
+ rdsave <= 0;
+ end
+ else begin
+ zrdone <= rdone; // previous value of rdone for synchronous edge detection
+ rdsave <= ~spulse & (rdpulse | rdsave);
+ end
+ end
+ assign rdpulse = rdone & ~zrdone;
+ assign rdonei = rdsave;
+ end
+ endgenerate
+
+ // rhold depends on sdone_delay_cycles and rdone_is_edge_sensitive
+ generate
+ if (sdone_delay_cycles == 0 || (sdone_delay_cycles == 1 && rdone_is_edge_sensitive == 1))
+ assign rhold = ~rdonei; // sdone_delay_cycles=0
+ else begin
+ // declare only when needed to avoid Quartus synthesis warnings
+ reg [sdc_bits:0] rhold_reg = 0; // for sdone_delay_cycles > 0
+ if (sdone_delay_cycles == 1) begin
+ always @(posedge clock or posedge aclr) begin
+ if (aclr == 1'b1)
+ rhold_reg <= 0;
+ else
+ rhold_reg <= ~(rinit & rdonei);
+ end
+ assign rhold = rhold_reg[0]; // sdone_delay_cycles=1
+ end
+ else begin
+ // need to count cycles to make sure rdone is stable
+ always @(posedge clock or posedge aclr)
+ begin
+ if (aclr == 1'b1)
+ rhold_reg <= 0;
+ else if ((rinit & rdonei & ~rdpulse) == 0)
+ // keep load value until rinit & rdone both high, and no new rdone pulses
+ rhold_reg <= sdc_load_constant[sdc_bits:0];
+ else
+ rhold_reg <= rhold_reg - 1'b1;
+ end
+ assign rhold = rhold_reg[sdc_bits]; // sdone_delay_cycles > 1
+ end
+ end
+ endgenerate
+
+ // sdone state bit indicates that reset sequence completed. Clear again on 'start'
+ always @(posedge clock or posedge aclr)
+ if (aclr == 1'b1)
+ sdone <= 0;
+ else
+ sdone <= ~spulse & (sdone | (rinit & ~rinit_next));
+
+ // reset pulse generation logic depends on 2 parameters
+ generate
+ if (reset_hold_til_rdone == 1) begin
+ assign reset = rinit;
+ assign timed_reset_in_progress = 0;
+ end
+ else if (reset_hold_cycles < 1) begin // 0 is legal, but catch negative (illegal) values too
+ assign reset = spulse;
+ assign timed_reset_in_progress = 0;
+ end
+ else begin
+ // declare only when needed to avoid Quartus synthesis warnings
+ reg [rhc_bits:0] zspulse = 0; // bits for reset pulse if fixed length
+ assign timed_reset_in_progress = zspulse[rhc_bits];
+ assign reset = zspulse[rhc_bits];
+
+ if (reset_hold_cycles == 1)
+ // a single-cycle reset pulse needs 1 register
+ always @(posedge clock or posedge aclr)
+ if (aclr == 1'b1)
+ zspulse <= 0;
+ else
+ zspulse <= spulse;
+ else begin
+ // multi-cycle reset pulse needs a counter
+ always @(posedge clock or posedge aclr)
+ begin
+ if (aclr == 1'b1)
+ zspulse <= 0;
+ else if (spulse == 1)
+ zspulse <= rhc_load_constant[rhc_bits:0];
+ else if (zspulse[rhc_bits] == 1)
+ zspulse <= zspulse - 1'b1;
+ end
+ end
+ end
+ endgenerate
+
+// generate
+// case (reset_hold_til_rdone)
+// 0 : m1 U1 (a, b, c);
+// 2 : m2 U1 (a, b, c);
+// default : m3 U1 (a, b, c);
+// endcase
+// endgenerate
+
+ // general assertions
+ //synopsys translate_off
+ // vlog/vcs/ncverilog: +define+ALTERA_XCVR_ASSERTIONS
+`ifdef ALTERA_XCVR_ASSERTIONS
+ // when rdone is edge sensitive, last rdone +ve edge triggers sdone +ve edge,
+ // 'sdone_delay_cycles' later. "##1 1" is an always-true cycle to match $rise(sdone)
+ sequence rdone_last_edge;
+ @(posedge clock) $rose(rdone) ##1 !$rose(rdone) [*sdone_delay_cycles] ##1 1;
+ endsequence
+
+ // when rdone is level sensitive, stable rdone for 'sdone_delay_cycles' consecutive cycles
+ // triggers sdone +ve edge. "##1 1" is an always-true cycle to match $rise(sdone)
+ sequence rdone_stable_level;
+ @(posedge clock) rdone [*(sdone_delay_cycles+1)] ##1 1;
+ endsequence
+
+// Most assertions aren't valid when 'aclr' is active
+//`define assert_awake(arg) assert property (disable iff (aclr) arg )
+ always @(aclr)
+ if (aclr) $assertkill;
+ else $asserton;
+
+ generate
+ always @(posedge clock) begin
+ // A rising edge on start will result in reset high within 1 clock cycle
+ assert property ($rose(start & ~aclr) |-> ##[0:1] reset);
+ // A rising edge on reset will result in sdone low within 1 clock cycle
+ assert property ($rose(reset) |-> ##[0:1] !sdone);
+
+ // assertions for optional behavior: reset pulse length options
+ if (reset_hold_til_rdone == 0 && reset_hold_cycles > 1)
+ // Verify fixed-length reset pulse option
+ assert property ($rose(reset) |-> reset [*reset_hold_cycles] ##1 !reset)
+ else $error("Reset pulse length should be %d", reset_hold_cycles);
+ if (reset_hold_til_rdone == 0 && reset_hold_cycles == 1)
+ // Verify fixed 1-length reset pulse option
+ assert property ($rose(reset) |=> !reset);
+ if (reset_hold_til_rdone == 0 && reset_hold_cycles == 0)
+ // Verify minimal-length reset pulse option, which mirrors 'start' edge detection
+ assert property ($rose(start & ~aclr) |-> reset ##1 !reset);
+ if (reset_hold_til_rdone == 1) begin
+ // with hold-til-rdone, reset should not deassert until after rdone asserts, then deassert immediately
+ assert property ($rose(reset) && !rdone |=> $stable(reset) [*0:$] ##1 (reset && rdone) ##1 !reset);
+ assert property ($rose(reset) && rdone ##1 rdone [*sdone_delay_cycles] |=> !reset); // rdone was already high
+ //assert property ($rose(reset) && !rdone |-> ##[0:$] rdone ##1 !reset);
+ end
+
+ // assertions for optional behavior: sdone delay options and rdone edge sensitive option
+ if (rdone_is_edge_sensitive == 1)
+ // rdone edge-sensitive option only has an effect when sdone_delay_cycles > 0
+ assert property ($rose(sdone) |-> rdone_last_edge.ended);
+ if (rdone_is_edge_sensitive == 0)
+ // rdone defaults to level-sensitive
+ assert property ($rose(sdone) |-> (rdone_stable_level.ended or $past($fell(reset),1)));
+ end
+ endgenerate
+`endif // ALTERA_XCVR_ASSERTIONS
+ //synopsys translate_on
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_reset_ctrl_tgx_cdrauto.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_reset_ctrl_tgx_cdrauto.sv
new file mode 100644
index 0000000000000000000000000000000000000000..d785de6ee8eb397584ea1833c7e8a7ddf5c3b045
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_reset_ctrl_tgx_cdrauto.sv
@@ -0,0 +1,201 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Reset controller for Stratix IV transceivers with RX CDR in auto-lock mode.
+//
+// Uses alt_reset_ctrl_lego to handle each reset stage, with 3 required for the overall sequence.
+// Parameter defaults for pll-powerdown and lock-to-data-auto timers assume 50 MHz system clock
+//
+// $Header$
+//
+
+`timescale 1 ns / 1 ns
+
+(* altera_attribute = "-name MERGE_TX_PLL_DRIVEN_BY_REGISTERS_WITH_SAME_CLEAR ON -to \"alt_reset_ctrl_lego:lego_pll_powerdown|zspulse\" " *)
+module alt_reset_ctrl_tgx_cdrauto
+#(
+ parameter sys_clk_in_mhz = 50 // needed for 1us and 4us delay timers
+)
+(
+ // User inputs and outputs
+ input wire clock,
+ input wire reset_all,
+ input tri0 reset_tx_digital,
+ input tri0 reset_rx_digital,
+ input wire powerdown_all,
+ output wire tx_ready,
+ output wire rx_ready,
+
+ // I/O to Stratix IV transceiver control & status
+ output wire pll_powerdown, // reset TX PLL
+ output wire tx_digitalreset, // reset TX PCS
+ output wire rx_analogreset, // reset RX PMA
+ output wire rx_digitalreset, // reset RX PCS
+ output wire gxb_powerdown, // powerdown whole quad
+ input wire pll_is_locked, // TX PLL is locked status
+ input tri0 tx_cal_busy, // TX channel calibration status
+ input tri0 rx_cal_busy, // RX channel calibration status
+ input tri1 rx_is_lockedtodata, // RX CDR PLL is locked to data status
+ input tri0 manual_mode // 0=Automatically reset RX after loss of rx_is_lockedtodata
+);
+
+localparam clk_in_mhz =
+`ifdef QUARTUS__SIMGEN
+ 2; // simulation-only value
+`elsif ALTERA_RESERVED_QIS
+ sys_clk_in_mhz; // use real counter lengths for normal Quartus synthesis
+`else
+ 2; // simulation-only value
+`endif
+localparam t_pll_powerdown = clk_in_mhz; // 1 us minimum
+localparam t_ltd_auto = clk_in_mhz*4; // 4 us minimum
+
+
+wire pll_is_locked_r; // pll_is_locked resynchronized
+wire tx_cal_busy_r; // tx_cal_busy resynchronized
+wire rx_cal_busy_r; // rx_cal_busy resynchronized
+wire rx_is_lockedtodata_r; // rx_is_lockedtodata resynchronized
+
+wire sdone_lego_pll_powerdown; // 'sequence done' output of pll_powerdown lego
+wire sdone_lego_tx_digitalreset;// 'sequence done' output of tx_digitalreset lego
+wire sdone_lego_rx_digitalreset;// 'sequence done' output of rx_digitalreset lego
+wire sdone_lego_rx_analogreset; // 'sequence done' output of rx_analogreset lego
+wire wire_tx_digital_only_reset;// reset output for TX digital-only
+wire wire_rx_digital_only_reset;// reset output for RX digital-only
+wire wire_tx_digitalreset; // TX digital full-reset source
+wire wire_rx_digitalreset; // RX digital full-reset source
+wire wire_rx_digital_retrigger; // Trigger new RX digital sequence after main sequence completes, and lose lock-to-data
+
+// Resynchronize input signals
+alt_xcvr_resync #(
+ .WIDTH(2)
+ ) alt_xcvr_resync_inst_0 (
+ .clk (clock),
+ .reset (1'b0),
+ .d ({pll_is_locked ,rx_is_lockedtodata }),
+ .q ({pll_is_locked_r,rx_is_lockedtodata_r})
+);
+
+alt_xcvr_resync #(
+ .WIDTH(2),
+ .INIT_VALUE(1)
+ ) alt_xcvr_resync_inst_1 (
+ .clk (clock),
+ .reset (1'b0),
+ .d ({rx_cal_busy,tx_cal_busy}),
+ .q ({rx_cal_busy_r,tx_cal_busy_r})
+);
+
+// First reset ctrl sequencer lego is for pll_powerdown generation
+alt_reset_ctrl_lego #(
+ .reset_hold_cycles(t_pll_powerdown) // hold pll_powerdown for 1us
+ ) lego_pll_powerdown ( .clock(clock),
+ .start(reset_all), // Do not use resynched version of reset_all here
+ .aclr(powerdown_all),
+ .reset(pll_powerdown),
+ .rdone(pll_is_locked_r),
+ .sdone(sdone_lego_pll_powerdown));
+
+// next reset ctrl sequencer lego is for tx_digitalreset generation
+alt_reset_ctrl_lego #(
+ .reset_hold_til_rdone(1) // hold until rdone arrives for this test case
+ ) lego_tx_digitalreset ( .clock(clock),
+ .start(reset_all),
+ .aclr(powerdown_all),
+ .reset(wire_tx_digitalreset),
+ .rdone(sdone_lego_pll_powerdown & ~tx_cal_busy_r),
+ .sdone(sdone_lego_tx_digitalreset));
+
+// next reset ctrl sequencer lego is for rx_analogreset generation
+alt_reset_ctrl_lego #(
+ .reset_hold_til_rdone(1), // hold until rdone arrives for this test case
+ .sdone_delay_cycles(2) // hold rx_analogreset 2 parallel_clock cycles after offset cancellation done
+ ) lego_rx_analogreset ( .clock(clock),
+ .start(reset_all),
+ .aclr(powerdown_all),
+ .reset(rx_analogreset),
+ .rdone(sdone_lego_tx_digitalreset & ~rx_cal_busy_r),
+ .sdone(sdone_lego_rx_analogreset));
+
+// last reset ctrl sequencer lego is for rx_digitalreset generation
+alt_reset_ctrl_lego #(
+ .reset_hold_til_rdone(1), // hold until rdone arrives for this test case
+ .sdone_delay_cycles(t_ltd_auto) // hold rx_digitalreset for 4us
+ ) lego_rx_digitalreset ( .clock(clock),
+ .start(~manual_mode & reset_all | wire_rx_digital_retrigger),
+ .aclr(powerdown_all),
+ .reset(wire_rx_digitalreset),
+ .rdone(sdone_lego_rx_analogreset & rx_is_lockedtodata_r),
+ .sdone(sdone_lego_rx_digitalreset));
+
+//////////// digital-only reset ////////////
+// separate reset ctrl sequencer lego for digital-only reset generation
+alt_reset_ctrl_lego #(
+ .reset_hold_cycles(3) // hold 2 parallel clock cycles (assumes sysclk slower or same freq as parallel clock)
+ ) lego_tx_digitalonly ( .clock(clock),
+ .start(reset_tx_digital | reset_all),
+ .aclr(powerdown_all),
+ .reset(wire_tx_digital_only_reset),
+ .rdone(sdone_lego_tx_digitalreset),
+ .sdone(tx_ready)); // TX status indicator for user
+
+alt_reset_ctrl_lego #(
+ .reset_hold_cycles(3) // hold 2 parallel clock cycles (assumes sysclk slower or same freq as parallel clock)
+ ) lego_rx_digitalonly ( .clock(clock),
+ .start(reset_rx_digital | (reset_all & ~manual_mode) | wire_rx_digital_retrigger),
+ .aclr(powerdown_all),
+ .reset(wire_rx_digital_only_reset),
+ .rdone(sdone_lego_rx_digitalreset),
+ .sdone(rx_ready)); // RX status indicator for user
+
+// digital resets have 2 possible sources: full-reset or digital-only
+assign tx_digitalreset = wire_tx_digitalreset | wire_tx_digital_only_reset;
+assign rx_digitalreset = wire_rx_digitalreset | wire_rx_digital_only_reset;
+
+// re-trigger RX digital sequence when main sequence is complete (indicated by sdone_lego_rx_digitalreset)
+// not manual mode, and lose lock-to-data
+assign wire_rx_digital_retrigger = ~manual_mode & sdone_lego_rx_digitalreset & ~rx_is_lockedtodata_r;
+
+// Quad power-down
+assign gxb_powerdown = powerdown_all;
+
+
+////////////////////////
+// general assertions
+//synopsys translate_off
+// vlog/vcs/ncverilog: +define+ALTERA_XCVR_ASSERTIONS
+`ifdef ALTERA_XCVR_ASSERTIONS
+always @(posedge clock) begin
+ // reset_all starts by triggering CMU PLL powerdown
+ assert property ($rose(reset_all) |=> $rose(pll_powerdown));
+ // While CMU PLL powerdown is asserted, all other resets must be asserted
+ assert property (pll_powerdown |-> (tx_digitalreset & rx_analogreset & rx_digitalreset));
+ // While rx_analogreset is asserted, rx_digitalreset must be asserted
+ assert property (rx_analogreset |-> rx_digitalreset);
+ // When pll_is_locked is asserted, tx_digitalreset must be deasserted
+ assert property ($rose(pll_is_locked_r) |-> ##[0:2] !tx_digitalreset);
+ // During a reset, rx_digitalreset should remain high for t_ltd_auto after rx_is_lockedtodata rising edge
+ assert property ($rose(rx_is_lockedtodata_r) & ~manual_mode|-> rx_digitalreset [*(t_ltd_auto+1)] ##1 !rx_digitalreset);
+ assert property ($rose(rx_is_lockedtodata_r) & manual_mode|->!rx_digitalreset);
+ // reset_tx_digital results in only a brief pulse on tx_digitalreset
+ assert property ($rose(reset_tx_digital) |=> tx_digitalreset [*3] );
+ assert property ($rose(reset_tx_digital) & tx_ready |=> tx_digitalreset [*3] ##1 ~tx_digitalreset ##1 $rose(tx_ready) );
+ // reset_rx_digital results in only a brief pulse on rx_digitalreset
+ assert property ($rose(reset_rx_digital) |=> rx_digitalreset [*3] );
+ assert property ($rose(reset_rx_digital) & rx_ready |=> rx_digitalreset [*3] ##1 ~rx_digitalreset ##1 $rose(rx_ready) );
+end
+`endif
+//synopsys translate_on
+
+endmodule
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diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xaui_phy_assignments.qip b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xaui_phy_assignments.qip
new file mode 100644
index 0000000000000000000000000000000000000000..6b854ad5bc76259e81a1220b8e3fb397d6826122
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xaui_phy_assignments.qip
@@ -0,0 +1,4 @@
+#comment: example of PLL TYPE assignment for TX PLL. This assignment is needed for every TX PLL that exist in the design
+
+# For Stratix V Soft XAUI:
+#set_instance_assignment -name PLL_TYPE ATX -to "*sv_xcvr_xaui:alt_xaui_phy*alt_pma_0*sv_xcvr_native_insts*pll*.tx_pll"
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xaui_phy_top.sdc b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xaui_phy_top.sdc
new file mode 100644
index 0000000000000000000000000000000000000000..3c125358eb82fe3f94dbea0afd1092f76ba3c68f
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xaui_phy_top.sdc
@@ -0,0 +1,43 @@
+# (C) 2001-2012 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and other
+# software and tools, and its AMPP partner logic functions, and any output
+# files any of the foregoing (including device programming or simulation
+# files), and any associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License Subscription
+# Agreement, Altera MegaCore Function License Agreement, or other applicable
+# license agreement, including, without limitation, that your use is for the
+# sole purpose of programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+
+#-----------------------------------------------------------------------------
+#
+# Description: SDC file for alt_xaui
+#
+# Authors: bauyeung
+#
+# Copyright (c) Altera Corporation 1997 - 2010
+# All rights reserved.
+#
+#
+#-----------------------------------------------------------------------------
+
+set_time_format -unit ns -decimal_places 3
+#derive_pll_clocks
+derive_clock_uncertainty
+
+#
+# input clocks
+#
+create_clock -name {xgmii_tx_clk} \
+ -period 6.400 -waveform {0.000 3.2} \
+ [ get_ports {xgmii_tx_clk} ]
+create_clock -name {phy_mgmt_clk} \
+ -period 20.000 -waveform {0.000 10.0} \
+ [ get_ports {phy_mgmt_clk} ]
+create_clock -name {refclk} \
+ -period 6.400 -waveform {0.000 3.2} \
+ [ get_ports {pll_ref_clk} ]
+
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_arbiter.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_arbiter.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5b0e914d4dea0be5e022a29a6df73240a4f4f29e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_arbiter.sv
@@ -0,0 +1,64 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Clocked priority encoder with state
+//
+// On each clock cycle, updates state to show which request is granted.
+// Most recent grant holder is always the highest priority.
+// If current grant holder is not making a request, while others are,
+// then new grant holder is always the requester with lowest bit number.
+// If no requests, current grant holder retains grant state
+
+// $Header$
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_arbiter #(
+ parameter width = 2
+) (
+ input wire clock,
+ input wire [width-1:0] req, // req[n] requests for this cycle
+ output reg [width-1:0] grant // grant[n] means requester n is grantee in this cycle
+);
+
+ wire idle; // idle when no requests
+ wire [width-1:0] keep; // keep[n] means requester n is requesting, and already has the grant
+ // Note: current grantee is always highest priority for next grant
+ wire [width-1:0] take; // take[n] means requester n is requesting, and there are no higher-priority requests
+
+ assign keep = req & grant; // current grantee is always highest priority for next grant
+ assign idle = ~| req; // idle when no requests
+
+ initial begin
+ grant = 0;
+ end
+
+ // grant next state depends on current grant and take priority
+ always @(posedge clock) begin
+ grant <= keep // if current grantee is requesting, gets to keep grant
+ | ({width{idle}} & grant) // if no requests, grant state remains unchanged
+ | take; // take applies only if current grantee is not requesting
+ end
+
+ // 'take' bus encodes priority. Request with lowest bit number wins when current grantee not requesting
+ assign take[0] = req[0]
+ & (~| (keep & ({width{1'b1}} << 1))); // no 'keep' from lower-priority inputs
+ genvar i;
+ generate
+ for (i=1; i < width; i = i + 1) begin : arb
+ assign take[i] = req[i]
+ & (~| (keep & ({width{1'b1}} << (i+1)))) // no 'keep' from lower-priority inputs
+ & (~| (req & {i{1'b1}})); // no 'req' from higher-priority inputs
+ end
+ endgenerate
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_common.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_common.sv
new file mode 100644
index 0000000000000000000000000000000000000000..dbe3e5a5fcf1db4a9ce64efc08efa2005e19cbe8
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_common.sv
@@ -0,0 +1,209 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common control & status register map for transceiver PHY IP
+// Applies to Stratix V-generation basic PHY components
+//
+// $Header$
+//
+
+`timescale 1 ps / 1 ps
+
+module alt_xcvr_csr_common #(
+ parameter lanes = 1,
+ parameter plls = 1
+)
+(
+ // user data (avalon-MM formatted)
+ input wire clk,
+ input tri0 reset,
+ input wire [7:0] address,
+ input tri1 read,
+ output reg [31:0] readdata = 0,
+ input tri0 write,
+ input wire [31:0] writedata,
+
+ // transceiver status inputs to this CSR
+ input wire [plls - 1 : 0] pll_locked,
+ input wire [lanes - 1 : 0] rx_is_lockedtoref,
+ input wire [lanes - 1 : 0] rx_is_lockedtodata,
+ input wire [lanes - 1 : 0] rx_signaldetect,
+
+ // reset controller outputs
+ input wire reset_controller_tx_ready,
+ input wire reset_controller_rx_ready,
+ input wire reset_controller_pll_powerdown,
+ input wire reset_controller_tx_digitalreset,
+ input wire reset_controller_rx_analogreset,
+ input wire reset_controller_rx_digitalreset,
+
+ // read/write control registers
+ // to reset controller
+ output reg csr_reset_tx_digital = 0,
+ output reg csr_reset_rx_digital = 0,
+ output reg csr_reset_all = 1, // power-up to 1 to trigger auto-init sequence
+ // to PMA and PCS reset inputs
+ output wire csr_pll_powerdown, // reset controller or manual
+ output wire [lanes - 1 : 0] csr_tx_digitalreset, // reset controller or manual
+ output wire [lanes - 1 : 0] csr_rx_analogreset, // reset controller or manual
+ output wire [lanes - 1 : 0] csr_rx_digitalreset, // reset controller or manual
+ // common PMA controls
+ output reg [lanes - 1 : 0] csr_phy_loopback_serial = 0,
+ output reg [lanes - 1 : 0] csr_rx_set_locktoref = 0,
+ output reg [lanes - 1 : 0] csr_rx_set_locktodata = 0
+);
+ import alt_xcvr_csr_common_h::*;
+
+ localparam sync_stages = 2; // number of sync stages for transceiver status signals
+ localparam sync_stages_str = "2"; // number of sync stages specified as string (for timing constraints)
+ integer stage;
+
+ // Parameter strings for embedded timing constraints
+ localparam CSR_PLLLOCKED_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_common*csr_pll_locked*[",sync_stages_str,"]*]\""};
+ localparam CSR_RXISLOCKED_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_common*csr_rx_is_locked*[",sync_stages_str,"]*]\""};
+ localparam CSR_RXSIGNALDET_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_common*csr_rx_signaldetect*[",sync_stages_str,"]*]\""};
+ localparam SDC_CONSTRAINTS = {CSR_PLLLOCKED_CONSTRAINT,";",CSR_RXISLOCKED_CONSTRAINT,";",CSR_RXSIGNALDET_CONSTRAINT};
+
+ // internal control registers
+ reg [lanes - 1 : 0] csr_interrupt_ch_bitmask = {lanes{1'b1}};
+ // fine reset control. 'OR' with reset controller equivalent signals
+ reg csr_reset_or_pll_powerdown = 0; // fine reset control
+ reg csr_reset_or_reset_tx_digital = 0; // fine reset control
+ reg csr_reset_or_reset_rx_analog = 0; // fine reset control
+ reg csr_reset_or_reset_rx_digital = 0; // fine reset control
+ reg [lanes - 1 : 0] csr_reset_ch_bitmask = {lanes{1'b1}};
+
+ // read-only status registers
+ // These are synchronized forms of transceiver status signals
+ // async inputs go to reg [sync_stages], and come out synchronized at reg [1]
+ (* altera_attribute = SDC_CONSTRAINTS *) // Apply timing constraints (does not matter which node)
+ reg [plls - 1 : 0] csr_pll_locked [sync_stages:1];
+ reg [lanes - 1 : 0] csr_rx_is_lockedtoref [sync_stages:1];
+ reg [lanes - 1 : 0] csr_rx_is_lockedtodata [sync_stages:1];
+ reg [lanes - 1 : 0] csr_rx_signaldetect [sync_stages:1];
+
+ always @(posedge clk or posedge reset) begin
+ if (reset == 1) begin
+ readdata <= 0;
+ csr_interrupt_ch_bitmask <= {lanes{1'b1}};
+
+ csr_reset_tx_digital <= 0;
+ csr_reset_rx_digital <= 0;
+ csr_reset_all <= 1; // reset to 1 to trigger auto-init sequence
+ csr_reset_ch_bitmask <= {lanes{1'b1}};
+ csr_reset_or_pll_powerdown <= 0; // fine reset control
+ csr_reset_or_reset_tx_digital <= 0; // fine reset control
+ csr_reset_or_reset_rx_analog <= 0; // fine reset control
+ csr_reset_or_reset_rx_digital <= 0; // fine reset control
+
+ csr_phy_loopback_serial <= 0;
+ csr_rx_set_locktoref <= 0;
+ csr_rx_set_locktodata <= 0;
+ end
+ else begin
+ // decode read & write for each supported address
+ case (address)
+ // interrupt control
+ ADDR_INTERRUPT_CH_BITMASK: begin
+ readdata <= (32'd0 | csr_interrupt_ch_bitmask);
+ if (write) csr_interrupt_ch_bitmask <= writedata[lanes-1:0];
+ end
+
+ // reset control
+ ADDR_RESET_CONTROL: begin
+ // on read, returns two bits: bit0: TX ready, bit1: RX ready
+ readdata <= (32'd0 | {reset_controller_rx_ready, reset_controller_tx_ready});
+ // on write, bit0 is 'reset_tx_digital', bit1 is 'reset_rx_digital', bit2 is 'reset_all'
+ //if (write) begin
+ // reset_all write side-effect: when write a '1', force all reset_ch_bitmask bits to '1'
+ // csr_reset_ch_bitmask <= csr_reset_ch_bitmask | {(lanes){writedata[2]}};
+ //end
+ end
+ ADDR_RESET_CH_BITMASK: begin
+ readdata <= (32'd0 | csr_reset_ch_bitmask);
+ if (write) csr_reset_ch_bitmask <= writedata[lanes-1:0];
+ end
+
+ // loopback control
+ ADDR_PHY_LOOPBACK_SERIAL,
+ ADDR_PMA_LOOPBACK_SERIAL: begin
+ readdata <= (32'd0 | csr_phy_loopback_serial);
+ if (write) csr_phy_loopback_serial <= writedata[lanes-1:0];
+ end
+
+ // PMA control and status
+ ADDR_PMA_RX_SET_LOCKTOREF: begin
+ readdata <= (32'd0 | csr_rx_set_locktoref);
+ if (write) csr_rx_set_locktoref <= writedata[lanes-1:0];
+ end
+ ADDR_PMA_RX_SET_LOCKTODATA: begin
+ readdata <= (32'd0 | csr_rx_set_locktodata);
+ if (write) csr_rx_set_locktodata <= writedata[lanes-1:0];
+ end
+ // PMA status (read-only)
+ ADDR_PMA_PLL_IS_LOCKED: readdata <= (32'd0 | csr_pll_locked[1]);
+ ADDR_PMA_RX_IS_LOCKEDTOREF: readdata <= (32'd0 | csr_rx_is_lockedtoref[1]);
+ ADDR_PMA_RX_IS_LOCKEDTODATA: readdata <= (32'd0 | csr_rx_is_lockedtodata[1]);
+ ADDR_PMA_RX_SIGNALDETECT: readdata <= (32'd0 | csr_rx_signaldetect[1]);
+
+ // Fine reset control - device dependent
+ ADDR_RESET_FINE_CONTROL: begin
+ // bit 0: 'pll_powerdown', 1: 'reset_tx_digital', 2: 'reset_rx_analog', 3: 'reset_rx_digital'
+
+ readdata <= (32'd0 | {csr_reset_or_reset_rx_digital, csr_reset_or_reset_rx_analog,
+ csr_reset_or_reset_tx_digital, csr_reset_or_pll_powerdown});
+ if (write) begin
+ csr_reset_or_pll_powerdown <= writedata[0]; // fine reset control
+ csr_reset_or_reset_tx_digital <= writedata[1]; // fine reset control
+ csr_reset_or_reset_rx_analog <= writedata[2]; // fine reset control
+ csr_reset_or_reset_rx_digital <= writedata[3]; // fine reset control
+ end
+ end
+
+
+ default: readdata <= ~ 32'd0; // use too many LEs?
+ endcase
+
+ // special handling for registers that must auto-clear on cycle after a write
+ // reset control. on write, bit0 is 'reset_tx_digital', bit1 is 'reset_rx_digital', bit2 is 'reset_all'
+ csr_reset_tx_digital <= (address == ADDR_RESET_CONTROL) & write & writedata[0];
+ csr_reset_rx_digital <= (address == ADDR_RESET_CONTROL) & write & writedata[1];
+ csr_reset_all <= (address == ADDR_RESET_CONTROL) & write & writedata[2];
+
+ // synchronization registers for status signals from transceivers
+ csr_pll_locked[sync_stages] <= pll_locked; // input from transceiver
+ csr_rx_is_lockedtoref[sync_stages] <= rx_is_lockedtoref;
+ csr_rx_is_lockedtodata[sync_stages] <= rx_is_lockedtodata;
+ csr_rx_signaldetect[sync_stages] <= rx_signaldetect;
+ for (stage=2; stage <= sync_stages; stage = stage + 1) begin
+ // additional sync stages
+ csr_pll_locked[stage-1] <= csr_pll_locked[stage];
+ csr_rx_is_lockedtoref[stage-1] <= csr_rx_is_lockedtoref[stage];
+ csr_rx_is_lockedtodata[stage-1] <= csr_rx_is_lockedtodata[stage];
+ csr_rx_signaldetect[stage-1] <= csr_rx_signaldetect[stage];
+ end
+ end
+ end
+
+ // combine reset controller and CSR manual reset control settings
+ assign csr_pll_powerdown = reset_controller_pll_powerdown; // cut manual PLL reset path
+ // | csr_reset_or_pll_powerdown;
+ assign csr_tx_digitalreset = csr_reset_ch_bitmask & {(lanes)
+ {reset_controller_tx_digitalreset | csr_reset_or_reset_tx_digital}};
+ assign csr_rx_analogreset = csr_reset_ch_bitmask & {(lanes)
+ {reset_controller_rx_analogreset | csr_reset_or_reset_rx_analog}};
+ assign csr_rx_digitalreset = csr_reset_ch_bitmask & {(lanes)
+ {reset_controller_rx_digitalreset | csr_reset_or_reset_rx_digital}};
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_common_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_common_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..a323c0a2a16722d20880e2fd2d694fe5031fe780
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_common_h.sv
@@ -0,0 +1,61 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common control & status register map for transceiver PHY IP
+// Applies to Stratix V-generation basic PHY components
+//
+// $Header$
+//
+// PACKAGE DECLARATION
+
+`timescale 1 ps / 1 ps
+
+package alt_xcvr_csr_common_h;
+
+ localparam alt_xcvr_csr_addr_width = 8;
+
+ // register bitmap ---------------------------------------------------------
+ // common blocks, interrupt control
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_INTERRUPT_CH_BITMASK = 1;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_INTERRUPT_ENABLE_BITMASK = 2;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_INTERRUPT_SOURCE = 3;
+
+ // common blocks, loopback control
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PHY_LOOPBACK_SERIAL = 6;
+
+ // common blocks, reset control
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_RESET_CONTROL_BASE = 64;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_RESET_CH_BITMASK = ADDR_RESET_CONTROL_BASE + 8'd1;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_RESET_CONTROL = ADDR_RESET_CONTROL_BASE + 8'd2;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_RESET_FINE_CONTROL = ADDR_RESET_CONTROL_BASE + 8'd4;
+
+ // common blocks, PMA common control & status
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_COMMON_BASE = 32;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_PLL_IS_LOCKED = ADDR_PMA_COMMON_BASE + 8'd2;
+ // common blocks, PMA channel control & status
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_CHANNEL_BASE = 96;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_LOOPBACK_SERIAL = ADDR_PMA_CHANNEL_BASE + 8'd1;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_RX_SIGNALDETECT = ADDR_PMA_CHANNEL_BASE + 8'd3;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_RX_SET_LOCKTODATA = ADDR_PMA_CHANNEL_BASE + 8'd4;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_RX_SET_LOCKTOREF = ADDR_PMA_CHANNEL_BASE + 8'd5;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_RX_IS_LOCKEDTODATA = ADDR_PMA_CHANNEL_BASE + 8'd6;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_RX_IS_LOCKEDTOREF = ADDR_PMA_CHANNEL_BASE + 8'd7;
+
+ // external block for PCS control & status
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS_BASE = 128; // 128-255
+
+ // First word in every PCS CSR is lane # (or lane group # as appropriate)
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS_LANE_GROUP = ADDR_PCS_BASE + 8'd0;
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_pcs8g.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_pcs8g.sv
new file mode 100644
index 0000000000000000000000000000000000000000..62ddfa2dce74f10cf83c30cd54f72573bbf216be
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_pcs8g.sv
@@ -0,0 +1,350 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common control & status register map for transceiver PHY IP
+// Applies to Stratix V-generation basic PHY components
+//
+// $Header$
+//
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_csr_pcs8g #(
+ parameter lanes = 1,
+ parameter words = 2 // for status bits that are per-word, like 8B10B status
+)
+(
+ // user data (avalon-MM formatted)
+ input wire clk,
+ input tri0 reset,
+ input wire [7:0] address,
+ input tri1 read,
+ output reg [31:0] readdata = 0,
+ input tri0 write,
+ input wire [31:0] writedata,
+
+ input wire rx_clk, // to synchronize rx control outputs
+ input wire tx_clk, // to synchronize tx control outputs
+
+ // transceiver status inputs to this CSR
+ input wire [lanes*words - 1 : 0] rx_patterndetect,
+ input wire [lanes*words - 1 : 0] rx_syncstatus,
+ input wire [lanes*words - 1 : 0] rx_errdetect,
+ input wire [lanes*words - 1 : 0] rx_disperr,
+ input wire [lanes - 1 : 0] rx_phase_comp_fifo_error,
+ input wire [lanes - 1 : 0] tx_phase_comp_fifo_error,
+ input wire [lanes*5 - 1: 0] rx_bitslipboundaryselectout,
+ input wire [lanes - 1 : 0] rlv,
+ input wire [lanes*words - 1 : 0] rx_a1a2sizeout,
+
+ // read/write control outputs
+ // PCS controls
+ output wire [lanes - 1 : 0] csr_tx_invpolarity,
+ output wire [lanes*5 - 1 : 0] csr_tx_bitslipboundaryselect,
+ output wire [lanes - 1 : 0] csr_rx_invpolarity,
+ output wire [lanes - 1 : 0] csr_rx_enapatternalign,
+ output wire [lanes - 1 : 0] csr_rx_bitreversalenable,
+ output wire [lanes - 1 : 0] csr_rx_bytereversalenable,
+ output wire [lanes - 1 : 0] csr_rx_bitslip,
+ output wire [lanes - 1 : 0] csr_rx_a1a2size
+);
+ import alt_xcvr_csr_common_h::*;
+ import alt_xcvr_csr_pcs8g_h::*;
+
+ localparam sync_stages = 2; // number of sync stages for transceiver status signals
+ localparam sync_stages_str = "2"; // number of sync stages specified as string (for timing constraints)
+ localparam LANE_REGW = 5;
+
+ // Parameter strings for embedded timing constraints
+ localparam SYNC_RX_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_pcs8g*sync_rx_*[",sync_stages_str,"]*]\""};
+ localparam SYNC_TX_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_pcs8g*sync_tx_*[",sync_stages_str,"]*]\""};
+ localparam CSR_REG_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_pcs8g*csr_indexed_read_only_reg*sreg[",sync_stages_str,"]*]\""};
+ localparam SDC_CONSTRAINTS = {SYNC_RX_CONSTRAINT,";",SYNC_TX_CONSTRAINT,";",CSR_REG_CONSTRAINT};
+
+ // internal registers
+ reg [LANE_REGW-1:0] reg_lane_number = 0; // lane or group number for indirection
+
+ ////////////////////////////////////////////////////////
+ // Read/Write CSR registers with lane indirection
+ ////////////////////////////////////////////////////////
+ // Apply false path timing constraints to synchronization registers. (It does not matter as to which node these are applied).
+ (* altera_attribute = SDC_CONSTRAINTS *)
+ reg [lanes - 1 : 0] reg_tx_invpolarity = 0;
+ reg [lanes - 1 : 0] sync_tx_invpolarity [sync_stages:1]; // synchronize to tx_clk
+ wire [lanes - 1 : 0] write_tx_invpolarity; // indexed write group muxed in
+ wire [0 : 0] lane_tx_invpolarity; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_tx_invpolarity(.in_narrow(writedata[0]),
+ .in_wide(reg_tx_invpolarity), .sel(reg_lane_number),
+ .out_narrow(lane_tx_invpolarity), .out_wide(write_tx_invpolarity));
+
+ reg [lanes*5 - 1 : 0] reg_tx_bitslipboundaryselect = 0;
+ reg [lanes*5 - 1 : 0] sync_tx_bitslipboundaryselect [sync_stages:1]; //synchronize to tx_clk
+ wire [lanes*5 - 1 : 0] write_tx_bitslipboundaryselect; //indexed write group muxed in
+ wire [4:0] lane_tx_bitslipboundaryselect; //selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(5), .sel_size(LANE_REGW), .init_value(0))
+ wmux_tx_bitslipboundaryselect(.in_narrow(writedata[5:1]),
+ .in_wide(reg_tx_bitslipboundaryselect), .sel(reg_lane_number),
+ .out_narrow(lane_tx_bitslipboundaryselect), .out_wide(write_tx_bitslipboundaryselect));
+
+ reg [lanes - 1 : 0] reg_rx_invpolarity = 0;
+ reg [lanes - 1 : 0] sync_rx_invpolarity [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_invpolarity; // indexed write group muxed in
+ wire [0 : 0] lane_rx_invpolarity; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_invpolarity(.in_narrow(writedata[0]),
+ .in_wide(reg_rx_invpolarity), .sel(reg_lane_number),
+ .out_narrow(lane_rx_invpolarity), .out_wide(write_rx_invpolarity));
+
+ reg [lanes - 1 : 0] reg_rx_enapatternalign = 0;
+ reg [lanes - 1 : 0] sync_rx_enapatternalign [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_enapatternalign; // indexed write group muxed in
+ wire [0 : 0] lane_rx_enapatternalign; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_enapatternalign(.in_narrow(writedata[0]),
+ .in_wide(reg_rx_enapatternalign), .sel(reg_lane_number),
+ .out_narrow(lane_rx_enapatternalign), .out_wide(write_rx_enapatternalign));
+
+ reg [lanes - 1 : 0] reg_rx_bitreversalenable = 0;
+ reg [lanes - 1 : 0] sync_rx_bitreversalenable [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_bitreversalenable; // indexed write group muxed in
+ wire [0 : 0] lane_rx_bitreversalenable; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_bitreversalenable(.in_narrow(writedata[1]),
+ .in_wide(reg_rx_bitreversalenable), .sel(reg_lane_number),
+ .out_narrow(lane_rx_bitreversalenable), .out_wide(write_rx_bitreversalenable));
+
+ reg [lanes - 1 : 0] reg_rx_bytereversalenable = 0;
+ reg [lanes - 1 : 0] sync_rx_bytereversalenable [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_bytereversalenable; // indexed write group muxed in
+ wire [0 : 0] lane_rx_bytereversalenable; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_bytereversalenable(.in_narrow(writedata[2]),
+ .in_wide(reg_rx_bytereversalenable), .sel(reg_lane_number),
+ .out_narrow(lane_rx_bytereversalenable), .out_wide(write_rx_bytereversalenable));
+
+ reg [lanes - 1 : 0] reg_rx_bitslip = 0;
+ reg [lanes - 1 : 0] sync_rx_bitslip [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_bitslip; // indexed write group muxed in
+ wire [0 : 0] lane_rx_bitslip; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_bitslip(.in_narrow(writedata[3]),
+ .in_wide(reg_rx_bitslip), .sel(reg_lane_number),
+ .out_narrow(lane_rx_bitslip), .out_wide(write_rx_bitslip));
+
+ reg [lanes - 1 : 0] reg_rx_a1a2size = 0;
+ reg [lanes - 1 : 0] sync_rx_a1a2size [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_a1a2size; // indexed write group muxed in
+ wire [0 : 0] lane_rx_a1a2size; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_a1a2size(.in_narrow(writedata[3]),
+ .in_wide(reg_rx_a1a2size), .sel(reg_lane_number),
+ .out_narrow(lane_rx_a1a2size), .out_wide(write_rx_a1a2size));
+
+ ////////////////////////////////////////////////////////
+ // Read-only CSR registers with lane indirection
+ ////////////////////////////////////////////////////////
+ // read-only status registers are synchronized forms of transceiver status signals
+ // async inputs go to reg [sync_stages], and come out synchronized at reg [1]
+ ////////////////////////////////////////////////////////
+ // read selectors (muxes) that index using the indirect lane (group) number
+ wire [words-1 : 0] lane_rx_patterndetect;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(words), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_patterndetect(.clk(clk), .async_in_wide(rx_patterndetect),
+ .sel(reg_lane_number), .out_narrow(lane_rx_patterndetect));
+
+ wire [words-1 : 0] lane_rx_syncstatus;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(words), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_syncstatus(.clk(clk), .async_in_wide(rx_syncstatus),
+ .sel(reg_lane_number), .out_narrow(lane_rx_syncstatus));
+
+ wire [words-1 : 0] lane_rx_errdetect;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(words), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_errdetect(.clk(clk), .async_in_wide(rx_errdetect),
+ .sel(reg_lane_number), .out_narrow(lane_rx_errdetect));
+
+ wire [words-1 : 0] lane_rx_disperr;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(words), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_disperr(.clk(clk), .async_in_wide(rx_disperr),
+ .sel(reg_lane_number), .out_narrow(lane_rx_disperr));
+
+ wire [words-1 : 0] lane_rx_a1a2sizeout;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(words), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_a1a2sizeout(.clk(clk), .async_in_wide(rx_a1a2sizeout),
+ .sel(reg_lane_number), .out_narrow(lane_rx_a1a2sizeout));
+
+ wire [0 : 0] lane_rx_phase_comp_fifo_error;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_phase_comp_fifo_error(.clk(clk), .async_in_wide(rx_phase_comp_fifo_error),
+ .sel(reg_lane_number), .out_narrow(lane_rx_phase_comp_fifo_error));
+
+ wire [4 : 0] lane_rx_bitslipboundaryselectout;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(5), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_bitslipboundaryselectout(.clk(clk), .async_in_wide(rx_bitslipboundaryselectout),
+ .sel(reg_lane_number), .out_narrow(lane_rx_bitslipboundaryselectout));
+
+ wire [0 : 0] lane_tx_phase_comp_fifo_error;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_tx_phase_comp_fifo_error(.clk(clk), .async_in_wide(tx_phase_comp_fifo_error),
+ .sel(reg_lane_number), .out_narrow(lane_tx_phase_comp_fifo_error));
+
+ wire [0 : 0] lane_rlv;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rlv(.clk(clk), .async_in_wide(rlv),
+ .sel(reg_lane_number), .out_narrow(lane_rlv));
+
+
+ always @(posedge clk or posedge reset) begin
+ if (reset == 1) begin
+ readdata <= 0;
+ reg_lane_number <= 0;
+ reg_tx_invpolarity <= 0;
+ reg_tx_bitslipboundaryselect <= 0;
+ reg_rx_invpolarity <= 0;
+ reg_rx_enapatternalign <= 0;
+ reg_rx_bitreversalenable <= 0;
+ reg_rx_bytereversalenable <= 0;
+ reg_rx_bitslip <= 0;
+ reg_rx_a1a2size <= 0;
+
+ // no need to clear synchronization registers, since they do not store state
+ end
+ else begin
+ // decode read & write for each supported address
+ case (address)
+ // lane or group number for indirection
+ ADDR_PCS_LANE_GROUP: begin
+ readdata <= (32'd0 | reg_lane_number);
+ if (write) reg_lane_number <= writedata[LANE_REGW-1:0];
+ end
+
+ // offset + 1, read-only RX status bits
+ // bit 0, rx_phase_comp_fifo_error
+ // bit 5:1, rx_bitslipboundaryselectout
+ ADDR_PCS8G_RX_STATUS: begin
+ readdata <= (32'd0 |
+ {lane_rx_bitslipboundaryselectout, //bit 5-1
+ lane_rx_phase_comp_fifo_error}); // bit 0
+ end
+
+ // offset + 2, read-only TX status bits
+ // bit 0, tx_phase_comp_fifo_error
+ ADDR_PCS8G_TX_STATUS: begin
+ readdata <= (32'd0 | lane_tx_phase_comp_fifo_error); // bit 0
+ end
+
+ // offset + 3, read/write TX control bits
+ // bit 0, tx_invpolarity
+ // bit 5:1, tx_bitslipboundaryselect
+ ADDR_PCS8G_TX_CONTROL: begin
+ readdata <= (32'd0 | {lane_tx_bitslipboundaryselect, lane_tx_invpolarity});
+ if (write)
+ begin
+ reg_tx_invpolarity <= write_tx_invpolarity;
+ reg_tx_bitslipboundaryselect <= write_tx_bitslipboundaryselect;
+ end
+ end
+
+ // offset + 4, read/write RX control bits
+ // bit 0, rx_invpolarity
+ ADDR_PCS8G_RX_CONTROL: begin
+ readdata <= (32'd0 | lane_rx_invpolarity);
+ if (write) reg_rx_invpolarity <= write_rx_invpolarity;
+ end
+
+ // offset + 5, read/write RX WA control bits
+ // bit 0, rx_enapatternalign
+ // bit 1, rx_bitreversalenable
+ // bit 2, rx_bytereversalenable
+ // bit 3, rx_bitslip
+ // bit 4, rx_a1a2size
+ ADDR_PCS8G_RX_WA_CONTROL: begin
+ readdata <= (32'd0 | { lane_rx_a1a2size, // bit 4
+ lane_rx_bitslip, // bit 3
+ lane_rx_bytereversalenable, // bit 2
+ lane_rx_bitreversalenable, // bit 1
+ lane_rx_enapatternalign}); // bit 0
+ if (write)
+ begin
+ reg_rx_enapatternalign <= write_rx_enapatternalign;
+ reg_rx_bitreversalenable <= write_rx_bitreversalenable;
+ reg_rx_bytereversalenable <= write_rx_bytereversalenable;
+ reg_rx_bitslip <= write_rx_bitslip;
+ reg_rx_a1a2size <= write_rx_a1a2size;
+ end
+ end
+
+ // offset + 5, read RX WA status bits
+ // bit 3:0, rx_errdetect
+ // bit 7:4, rx_syncstatus
+ // bit 11:8, rx_disperr
+ // bit 15:12, rx_patterndetect
+ // bit 16, rlv
+ // bit 23:20, rx_a1a2sizeout
+ ADDR_PCS8G_RX_WA_STATUS: begin
+ readdata <= (32'd0 | {(4'b0 | lane_rx_a1a2sizeout), // bit 23:20
+ (4'b0 | lane_rlv), // bit 16
+ (4'b0 | lane_rx_patterndetect), // bit 15:12
+ (4'b0 | lane_rx_disperr), // bit 11:8
+ (4'b0 | lane_rx_syncstatus), // bit 7:4
+ (4'b0 | lane_rx_errdetect)}); // bit 3:0
+ end
+
+ default: readdata <= ~ 32'd0; // use too many LEs?
+ endcase
+ end
+ end
+
+ // synchronize TX controls to tx_clk before generating output
+ // sysclk-sync'ed input enters at [sync_stages], and tx_clk-sync'ed output exist at [1]
+ integer stage;
+ always @(posedge tx_clk) begin
+ sync_tx_invpolarity[sync_stages] <= reg_tx_invpolarity;
+ sync_tx_bitslipboundaryselect[sync_stages] <= reg_tx_bitslipboundaryselect;
+ for (stage=2; stage <= sync_stages; stage = stage + 1) begin
+ // additional sync stages
+ sync_tx_invpolarity[stage-1] <= sync_tx_invpolarity[stage];
+ sync_tx_bitslipboundaryselect[stage-1] <= sync_tx_bitslipboundaryselect[stage];
+ end
+ end
+ assign csr_tx_invpolarity = sync_tx_invpolarity[1];
+ assign csr_tx_bitslipboundaryselect = sync_tx_bitslipboundaryselect[1];
+
+ // synchronize RX controls to rx_clk before generating output
+ // sysclk-sync'ed input enters at [sync_stages], and rx_clk-sync'ed output exist at [1]
+ always @(posedge rx_clk) begin
+ sync_rx_invpolarity[sync_stages] <= reg_rx_invpolarity;
+ sync_rx_enapatternalign[sync_stages] <= reg_rx_enapatternalign;
+ sync_rx_bitreversalenable[sync_stages] <= reg_rx_bitreversalenable;
+ sync_rx_bytereversalenable[sync_stages] <= reg_rx_bytereversalenable;
+ sync_rx_bitslip[sync_stages] <= reg_rx_bitslip;
+ sync_rx_a1a2size[sync_stages] <= reg_rx_a1a2size;
+ for (stage=2; stage <= sync_stages; stage = stage + 1) begin
+ // additional sync stages
+ sync_rx_invpolarity[stage-1] <= sync_rx_invpolarity[stage];
+ sync_rx_enapatternalign[stage-1] <= sync_rx_enapatternalign[stage];
+ sync_rx_bitreversalenable[stage-1] <= sync_rx_bitreversalenable[stage];
+ sync_rx_bytereversalenable[stage-1] <= sync_rx_bytereversalenable[stage];
+ sync_rx_bitslip[stage-1] <= sync_rx_bitslip[stage];
+ sync_rx_a1a2size[stage-1] <= sync_rx_a1a2size[stage];
+ end
+ end
+ assign csr_rx_invpolarity = sync_rx_invpolarity[1];
+ assign csr_rx_enapatternalign = sync_rx_enapatternalign[1];
+ assign csr_rx_bitreversalenable = sync_rx_bitreversalenable[1];
+ assign csr_rx_bytereversalenable = sync_rx_bytereversalenable[1];
+ assign csr_rx_bitslip = sync_rx_bitslip[1];
+ assign csr_rx_a1a2size = sync_rx_a1a2size[1];
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_pcs8g_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_pcs8g_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..09f65ef3aee3227b1f9f9ba7d3359a300eb092ac
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_pcs8g_h.sv
@@ -0,0 +1,33 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common control & status register map for transceiver PHY IP
+// Applies to Stratix V-generation basic PHY components
+//
+// $Header$
+//
+// PACKAGE DECLARATION
+package alt_xcvr_csr_pcs8g_h;
+
+ import alt_xcvr_csr_common_h::*;
+
+ // 8G PCS, a.k.a. "Standard PCS", control and status bits
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_RX_STATUS = ADDR_PCS_BASE + 8'd1;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_TX_STATUS = ADDR_PCS_BASE + 8'd2;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_TX_CONTROL = ADDR_PCS_BASE + 8'd3;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_RX_CONTROL = ADDR_PCS_BASE + 8'd4;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_RX_WA_CONTROL = ADDR_PCS_BASE + 8'd5;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_RX_WA_STATUS = ADDR_PCS_BASE + 8'd6;
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_selector.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_selector.sv
new file mode 100644
index 0000000000000000000000000000000000000000..2e843e4597c8292f41a2d244cf5bb2dae2d70abc
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_csr_selector.sv
@@ -0,0 +1,116 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Select a sub-group from a wide register
+// Useful for indirection indexing
+//
+// $Header$
+//
+
+`timescale 1 ns / 1 ns
+
+module csr_mux #(
+ parameter groups = 2,
+ parameter grp_size = 1,
+ parameter sel_size = 1
+)
+(
+ input wire [groups*grp_size-1:0] in_wide,
+ input tri0 [sel_size-1:0] sel,
+ output wire [grp_size-1:0] out_narrow
+);
+// lpm_mux #(.lpm_size(groups), .lpm_width(grp_size), .lpm_widths(sel_size))
+// mux (.data(in_wide), .sel(sel), .result(out_narrow));
+ wire [grp_size-1:0] in_groups [groups-1:0];
+
+ // a synthesizable mux, with a parameterized number of inputs
+ genvar i;
+ assign in_groups[0] = in_wide[grp_size-1:0] & {grp_size{sel == 0}};
+ generate for (i=1; i<groups; i = i+1) begin: mux
+ assign in_groups[i] = in_groups[i-1] | in_wide[i*grp_size +: grp_size] & {grp_size{sel == i}};
+ end
+ endgenerate
+ assign out_narrow = in_groups[groups-1];
+endmodule
+
+//
+// write to a sub-group of a wide register
+// Useful for indirection indexing on write
+//
+module csr_indexed_write_mux #(
+ parameter groups = 2,
+ parameter grp_size = 1,
+ parameter sel_size = 1,
+ parameter init_value = 0
+)
+(
+ input wire [grp_size-1:0] in_narrow,
+ input tri0 [sel_size-1:0] sel,
+ output wire [grp_size-1:0] out_narrow, // for read back to mgmt interface
+ input wire [groups*grp_size-1:0] in_wide, // full-width control reg state
+ output wire [groups*grp_size-1:0] out_wide // to write to full-width control reg
+);
+ wire [groups*grp_size-1:0] wire_wide [groups-1:0];
+
+ // in_narrow is output in the group position indicated by .sel() input
+ genvar i;
+ assign wire_wide[0] = (in_wide & {grp_size{sel != 0}}) | (in_narrow & {grp_size{sel == 0}});
+ generate for (i=1; i<groups; i = i+1) begin: mux
+ assign wire_wide[i] = wire_wide[i-1]
+ | (in_wide & {{grp_size{sel != i}}, {(grp_size*i){1'b0}}})
+ | ({in_narrow & {grp_size{sel == i}}, {(grp_size*i){1'b0}}});
+ end
+ endgenerate
+ assign out_wide = wire_wide[groups-1];
+
+ // generate out_narrow as ordinary mux of in_wide
+ csr_mux #(.groups(groups), .grp_size(grp_size), .sel_size(sel_size))
+ o_narrow(.in_wide(in_wide), .sel(sel), .out_narrow(out_narrow));
+
+endmodule
+
+//
+// read from a sub-group of a wide, async status input
+// Creates synchronization logic to sample in local clock domain
+// Useful for indirection indexing on read-only status bits
+//
+module csr_indexed_read_only_reg #(
+ parameter groups = 2,
+ parameter grp_size = 1,
+ parameter sel_size = 1,
+ parameter sync_stages = 2
+)
+(
+ input wire clk,
+ input tri0 [sel_size-1:0] sel,
+ output wire [grp_size-1:0] out_narrow, // for read back to mgmt interface
+ input wire [groups*grp_size-1:0] async_in_wide // full-width async status inputs
+);
+ // read-only status registers are synchronized forms of async status signals
+ // async inputs go to sreg [sync_stages], and come out synchronized at sreg [1]
+ reg [groups*grp_size-1:0] sreg [sync_stages:1];
+ integer stage;
+ always @(posedge clk) begin
+ sreg[sync_stages] <= async_in_wide;
+ for (stage=2; stage <= sync_stages; stage = stage + 1) begin
+ // additional sync stages
+ sreg[stage-1] <= sreg[stage];
+ end
+ end
+
+ // generate out_narrow as ordinary mux of out_wide
+ csr_mux #(.groups(groups), .grp_size(grp_size), .sel_size(sel_size))
+ o_narrow(.in_wide(sreg[1]), .sel(sel), .out_narrow(out_narrow));
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_m2s.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_m2s.sv
new file mode 100644
index 0000000000000000000000000000000000000000..143f8260ab27069cf2eb8fd54be2d08f84f018ec
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_m2s.sv
@@ -0,0 +1,61 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Master-to-slave access fabric
+//
+// Combined with external multi-master arbitration, this block gates
+// master read, write, address, and writedata outputs, and generates
+// a waitrequest when arbiter indicates access is not granted
+
+// $Header$
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_m2s #(
+ parameter width_addr = 3,
+ parameter width_data = 32
+) (
+ input wire clock,
+ output wire req, // request to arbiter for slave access
+ input wire grant,
+
+ // signals from/to master
+ input wire m_read,
+ input wire m_write,
+ input wire [width_addr-1:0] m_address,
+ input wire [width_data-1:0] m_writedata,
+ output wire [width_data-1:0] m_readdata,
+ output wire m_waitrequest,
+
+ // signals from/to slave
+ output wire s_read,
+ output wire s_write,
+ output wire [width_addr-1:0] s_address,
+ output wire [width_data-1:0] s_writedata,
+ input wire [width_data-1:0] s_readdata,
+ input wire s_waitrequest
+);
+
+ // If master is requesting access, generate waitreq until granted
+ assign req = m_read | m_write; // master access requests
+ assign m_waitrequest = grant ? s_waitrequest : req;
+
+ // gate outputs to slave with grant signal
+ assign s_read = m_read & grant;
+ assign s_write = m_write & grant;
+ assign s_address = m_address & {width_addr{grant}};
+ assign s_writedata = m_writedata & {width_data{grant}};
+
+ // slave data outputs pass through directly
+ assign m_readdata = s_readdata;
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_mgmt2dec.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_mgmt2dec.sv
new file mode 100644
index 0000000000000000000000000000000000000000..93ce24e6bb50518c47c242026699fb45dcee975a
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_mgmt2dec.sv
@@ -0,0 +1,90 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Management interface address decoder for Altera Transceiver PHY
+//
+// Addresses common case of 2 modules to be stitched together:
+// - 'top' PHY channel blocks (includes reset control, CSR, ...)
+// - dynamic reconfiguration block
+
+// $Header$
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_mgmt2dec (
+
+ // user-visible external management interface
+ input wire mgmt_clk_reset,
+ input wire mgmt_clk,
+
+ input wire [8:0] mgmt_address,
+ input wire mgmt_read,
+ output reg [31:0] mgmt_readdata = ~32'd0,
+ output reg mgmt_waitrequest = 0,
+ input wire mgmt_write,
+
+ // internal interface to 'top' csr block
+ output wire [7:0] topcsr_address,
+ output wire topcsr_read,
+ input wire [31:0] topcsr_readdata,
+ input wire topcsr_waitrequest,
+ output wire topcsr_write,
+
+ // internal interface to 'top' csr block
+ output wire [7:0] reconf_address,
+ output wire reconf_read,
+ input wire [31:0] reconf_readdata,
+ input wire reconf_waitrequest,
+ output wire reconf_write
+);
+ localparam width_swa = 7; // word address width of interface to slaves (2 for top.CSR and 1 for reconfig)
+ localparam dec_count = 2; // count of the total number of sub-components that can act
+ // as slaves to the mgmt interface
+ localparam dec_topcsr = 0; // uses 2 128-word address blocks
+ localparam dec_reconf = 1; // uses 1 128-word address block
+
+
+ ///////////////////////////////////////////////////////////////////////
+ // Decoder for multiple slaves of reconfig_mgmt interface
+ ///////////////////////////////////////////////////////////////////////
+ wire [dec_count-1:0] r_decode;
+ assign r_decode =
+ (mgmt_address[8:width_swa+1] == dec_topcsr) ? (({dec_count-dec_topcsr{1'b0}} | 1'b1) << dec_topcsr)
+ : (mgmt_address[8:width_swa] == 2'd2) ? (({dec_count-dec_reconf{1'b0}} | 1'b1) << dec_reconf)
+ : {dec_count{1'b0}};
+
+ // reconfig_mgmt output generation is muxing of decoded slave output
+ always @(*) begin
+ if (r_decode[dec_topcsr] == 1'b1) begin
+ mgmt_readdata = topcsr_readdata;
+ mgmt_waitrequest = topcsr_waitrequest;
+ end else if (r_decode[dec_reconf] == 1'b1) begin
+ mgmt_readdata = reconf_readdata;
+ mgmt_waitrequest = reconf_waitrequest;
+ end else begin
+ mgmt_readdata = -1;
+ mgmt_waitrequest = 1'b0;
+ end
+ end
+
+ // internal interface to 'top' csr block
+ assign topcsr_address = mgmt_address[width_swa:0]; // top.csr uses 2 128-word blocks
+ assign topcsr_read = mgmt_read & r_decode[dec_topcsr];
+ assign topcsr_write = mgmt_write & r_decode[dec_topcsr];
+
+ // internal interface to 'top' csr block
+ assign reconf_address = mgmt_address[width_swa-1:0]; // reconfig uses 1 128-word block
+ assign reconf_read = mgmt_read & r_decode[dec_reconf];
+ assign reconf_write = mgmt_write & r_decode[dec_reconf];
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_mgmt2dec_phyreconfig.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_mgmt2dec_phyreconfig.sv
new file mode 100644
index 0000000000000000000000000000000000000000..3993651a7280e45e8ed8823d62ce37b8836861c2
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_mgmt2dec_phyreconfig.sv
@@ -0,0 +1,110 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//-----------------------------------------------------------------------------
+//
+// Description: Custom management interface address decoder for Altera
+// transciever PHY. Addresses common case of 2 modules to be stitched together:
+// - 'top' PHY channel blocks (includes reset control, CSR, ...)
+// - dynamic reconfiguration block
+//
+// Authors: dunnikri 19-Aug-2010
+//
+// Copyright (c) Altera Corporation 1997 - 2010
+// All rights reserved.
+//
+//
+//-----------------------------------------------------------------------------
+
+//`timescale 1 ns / 1 ns
+
+module alt_xcvr_mgmt2dec_phyreconfig (
+
+ // user-visible external management interface
+ input wire mgmt_clk_reset,
+ input wire mgmt_clk,
+
+ input wire [8:0] mgmt_address,
+ input wire mgmt_read,
+ output reg [31:0] mgmt_readdata = ~32'd0,
+ output reg mgmt_waitrequest = 0,
+ input wire mgmt_write,
+
+ // internal interface to xaui phy block
+ output wire [7:0] sc_phy_address,
+ output wire sc_phy_read,
+ input wire [31:0] sc_phy_readdata,
+ input wire sc_phy_waitrequest,
+ output wire sc_phy_write,
+
+ // internal interface to reconfig block
+ output wire [6:0] sc_reconf_address,
+ output wire sc_reconf_read,
+ input wire [31:0] sc_reconf_readdata,
+ input wire sc_reconf_waitrequest,
+ output wire sc_reconf_write
+);
+ localparam width_swa = 7; // word address width of interface to slaves (2 for phy and 1 for reconfig)
+ localparam dec_count = 2; // count of the total number of sub-components that can act
+ // as slaves to the mgmt interface
+ localparam dec_sc_phy = 0; //
+ localparam dec_reconf = 1; //
+
+ ///////////////////////////////////////////////////////////////////////
+ // Decoder for multiple slaves of reconfig_mgmt interface
+ ///////////////////////////////////////////////////////////////////////
+ wire [dec_count-1:0] r_decode; //1-hot encoding
+
+ //-----------------------Memory Map Reference-------------------------
+ //--------------------------------------------------------------------
+ //Block | Word Address | Byte Address |
+ //-------------------------------------------------------------------
+ //PHY Common | 0x0 | 0x0 |
+ //PMA Controller | 0x20 | 0x80 |
+ //Reset Controller | 0x40 | 0x100 |
+ //PMA Channel Controller | 0x60 | 0x180 |
+ //PCS | 0x80 | 0x200 |
+ //XCVR Reconfig | 0x100 | 0x400 |
+ //--------------------------------------------------------------------
+
+ //Decoding is based on memory map word address
+ assign r_decode =
+ (mgmt_address[8:width_swa+1] == dec_sc_phy) ? (({dec_count-dec_sc_phy{1'b0}} | 1'b1) << dec_sc_phy)
+ : (mgmt_address[8:width_swa] == 2'd2) ? (({dec_count-dec_reconf{1'b0}} | 1'b1) << dec_reconf)
+ : {dec_count{1'b0}};
+
+ // reconfig_mgmt output generation is muxing of decoded slave output
+ always @(*) begin
+ if (r_decode[dec_sc_phy] == 1'b1) begin
+ mgmt_readdata = sc_phy_readdata;
+ mgmt_waitrequest = sc_phy_waitrequest;
+ end else if (r_decode[dec_reconf] == 1'b1) begin
+ mgmt_readdata = sc_reconf_readdata;
+ mgmt_waitrequest = sc_reconf_waitrequest;
+ end else begin
+ mgmt_readdata = -1;
+ mgmt_waitrequest = 1'b0;
+ end
+ end
+
+ // internal interface to 'top' phy block
+ assign sc_phy_address = mgmt_address[width_swa:0];
+ assign sc_phy_read = mgmt_read & r_decode[dec_sc_phy];
+ assign sc_phy_write = mgmt_write & r_decode[dec_sc_phy];
+
+ // internal interface to 'top' reconfig block
+ assign sc_reconf_address = mgmt_address[width_swa-1:0];
+ assign sc_reconf_read = mgmt_read & r_decode[dec_reconf];
+ assign sc_reconf_write = mgmt_write & r_decode[dec_reconf];
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_mgmt2dec_xaui.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_mgmt2dec_xaui.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5720dddc8ee64986827d0db95c96c90eec94cdf3
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_mgmt2dec_xaui.sv
@@ -0,0 +1,134 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//-----------------------------------------------------------------------------
+//
+// Description: Custom management interface address decoder for Altera
+// transciever PHY. Addresses common case of 3 modules to be stitched together:
+// - CSR, Alt_PMA controller, Alt_PMA_Channel controller
+//
+// Authors: dunnikri 19-Aug-2010
+//
+// Copyright (c) Altera Corporation 1997 - 2010
+// All rights reserved.
+//
+//
+//-----------------------------------------------------------------------------
+
+`timescale 1 ps / 1 ps
+
+module alt_xcvr_mgmt2dec_xaui (
+
+ // user-visible external management interface
+ input wire mgmt_clk_reset,
+ input wire mgmt_clk,
+
+ input wire [7:0] mgmt_address,
+ input wire mgmt_read,
+ output reg [31:0] mgmt_readdata = ~32'd0,
+ output reg mgmt_waitrequest = 0,
+ input wire mgmt_write,
+
+ // internal interface to xaui pma channel controller
+ output wire [5:0] sc_pma_ch_controller_address,
+ output wire sc_pma_ch_controller_read,
+ input wire [31:0] sc_pma_ch_controller_readdata,
+ input wire sc_pma_ch_controller_waitrequest,
+ output wire sc_pma_ch_controller_write,
+
+ // internal interface to pma controller block
+ output wire [1:0] sc_pma_controller_address,
+ output wire sc_pma_controller_read,
+ input wire [31:0] sc_pma_controller_readdata,
+ input wire sc_pma_controller_waitrequest,
+ output wire sc_pma_controller_write,
+
+ // internal interface to hxaui csr block
+ output wire [4:0] sc_csr_address,
+ output wire sc_csr_read,
+ input wire [31:0] sc_csr_readdata,
+ input wire sc_csr_waitrequest,
+ output wire sc_csr_write
+);
+ localparam width_swa = 7; // word address width of interface to slaves (2 for phy and 1 for reconfig)
+ localparam dec_count = 3; // count of the total number of sub-components that can act
+ // as slaves to the mgmt interface
+
+ localparam dec_pma_control = 0;
+ localparam dec_csr = 1;
+ localparam dec_pma_ch_control = 2;
+
+ //--------------------------------------------------------------------
+ //Block | Word Address | Byte Address |
+ //-------------------------------------------------------------------
+ //PHY Common | 0x0 | 0x0 |
+ //PMA Controller | 0x20 | 0x80 |
+ //Reset Controller | 0x40 | 0x100 |
+ //PMA Channel Controller | 0x60 | 0x180 |
+ //PCS | 0x80 | 0x200 |
+ //XCVR Reconfig | 0x100 | 0x400 |
+ //-------------------------------------------------------------------
+
+
+ ///////////////////////////////////////////////////////////////////////
+ // Decoder for multiple slaves of reconfig_mgmt interface
+ ///////////////////////////////////////////////////////////////////////
+ wire [dec_count-1:0] r_decode; //1-hot encoding
+
+ //PMA Controller - 0x20 (0010 0000)
+ //Reset Controller - 0x40 (0100 0000)
+ //Channel Controller - 0x60 (0110 0000)
+ //PCS - 0x80 (1000 0000)
+ //Consider first 3 MSBs for decoding
+ /*assign r_decode =
+ (mgmt_address[7:5] == 3'd1) ? (({dec_count-dec_pma_control{1'b0}} | 1'b1) << dec_pma_control)
+ : (mgmt_address[7:5] == 3'd4) ? (({dec_count-dec_csr{1'b0}} | 1'b1) << dec_csr)
+ : (mgmt_address[7:5] == 3'd3) ? (({dec_count-dec_pma_ch_control{1'b0}} | 1'b1) << dec_pma_ch_control)
+ : {dec_count{1'b0}};*/
+
+ assign r_decode[0] = (!mgmt_address[7]) & (!mgmt_address[6]) & (mgmt_address[5]);
+ assign r_decode[1] = (mgmt_address[7]) & (!mgmt_address[6]) & (!mgmt_address[5]);
+ assign r_decode[2] = (!mgmt_address[7]) & (mgmt_address[6]);
+
+
+ always @(*) begin
+ if (r_decode[dec_pma_ch_control] == 1'b1) begin
+ mgmt_readdata = sc_pma_ch_controller_readdata;
+ mgmt_waitrequest = sc_pma_ch_controller_waitrequest;
+ end else if (r_decode[dec_pma_control] == 1'b1) begin
+ mgmt_readdata = sc_pma_controller_readdata;
+ mgmt_waitrequest = sc_pma_controller_waitrequest;
+ end else if (r_decode[dec_csr] == 1'b1) begin
+ mgmt_readdata = sc_csr_readdata;
+ mgmt_waitrequest = sc_csr_waitrequest;
+ end else begin
+ mgmt_readdata = -1;
+ mgmt_waitrequest = 1'b0;
+ end
+ end
+
+ // internal interface to alt_pma_ch_control block
+ assign sc_pma_ch_controller_address = mgmt_address[5:0]; //6 bit address
+ assign sc_pma_ch_controller_read = mgmt_read & r_decode[dec_pma_ch_control];
+ assign sc_pma_ch_controller_write = mgmt_write & r_decode[dec_pma_ch_control];
+
+ // internal interface to pma_control block
+ assign sc_pma_controller_address = mgmt_address[1:0]; // 2 bit address
+ assign sc_pma_controller_read = mgmt_read & r_decode[dec_pma_control];
+ assign sc_pma_controller_write = mgmt_write & r_decode[dec_pma_control];
+
+ // internal interface to csr block
+ assign sc_csr_address = mgmt_address[4:0]; // 5 bit address
+ assign sc_csr_read = mgmt_read & r_decode[dec_csr];
+ assign sc_csr_write = mgmt_write & r_decode[dec_csr];
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_analog.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_analog.sv
new file mode 100644
index 0000000000000000000000000000000000000000..c11f7aa371601873a1d6fc77d0c67623f66bff56
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_analog.sv
@@ -0,0 +1,146 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_analog #(
+ parameter device_family = "Stratix V"
+)
+(
+
+input wire reconfig_clk, // this will be the reconfig clk
+input wire reset,
+
+//avalon MM slave
+input wire [2:0] analog_reconfig_address, // MM address
+input wire [31:0] analog_reconfig_writedata,
+input wire analog_reconfig_write,
+input wire analog_reconfig_read,
+
+//output MM slave
+output wire [31:0] analog_reconfig_readdata, // from MM
+output wire analog_reconfig_waitrequest,
+//output wire analog_reconfig_error,
+output wire analog_reconfig_done,
+
+// input from base_reconfig
+input wire analog_reconfig_irq_from_base,
+input wire analog_reconfig_waitrequest_from_base,
+
+
+// output to base_reconfig
+// Avalon MM Master
+output wire [2:0] analog_reconfig_address_base, // 3 bit MM
+output wire [31:0] analog_reconfig_writedata_base,
+output wire analog_reconfig_write_base, // start write to GXB
+output wire analog_reconfig_read_base, // start read from GXB
+
+// input from base reconfig
+input wire [31:0] analog_reconfig_readdata_base, // data from read command
+ output wire arb_req,
+ input wire arb_grant
+);
+
+//parameter device_family = "StratixIV"; // or ArriaII
+
+
+generate
+ //Deepak - added namespace support for CIVGX and AII GX
+ if((device_family == "Stratix IV") || (device_family == "Arria II") || (device_family == "Cyclone IV GX") || (device_family == "Arria II GX") || (device_family == "Arria II GZ") || (device_family == "HardCopy IV"))
+ begin
+ wire [4:0] w_tgx_analog_reconfig_address_base;
+ alt_xcvr_reconfig_analog_tgx reconfig_analog_tgx(
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .analog_reconfig_address(analog_reconfig_address),
+ .analog_reconfig_writedata(analog_reconfig_writedata),
+ .analog_reconfig_write(analog_reconfig_write),
+ .analog_reconfig_read(analog_reconfig_read),
+ .analog_reconfig_readdata(analog_reconfig_readdata),
+ .analog_reconfig_waitrequest(analog_reconfig_waitrequest),
+ .analog_reconfig_done(analog_reconfig_done),
+ .analog_reconfig_irq_from_base(analog_reconfig_irq_from_base),
+ .analog_reconfig_waitrequest_from_base(analog_reconfig_waitrequest_from_base),
+ .analog_reconfig_address_base(analog_reconfig_address_base),
+ .analog_reconfig_writedata_base(analog_reconfig_writedata_base),
+ .analog_reconfig_write_base(analog_reconfig_write_base),
+ .analog_reconfig_read_base(analog_reconfig_read_base),
+ .analog_reconfig_readdata_base(analog_reconfig_readdata_base)
+ );
+ assign analog_reconfig_address_base = w_tgx_analog_reconfig_address_base[4:2];
+ assign arb_req = 1'b0 & arb_grant; // not currently used in S4 architecture
+ end
+ else if(device_family == "Stratix V")
+ begin
+ alt_xcvr_reconfig_analog_sv reconfig_analog_sv(
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .analog_reconfig_address(analog_reconfig_address),
+ .analog_reconfig_writedata(analog_reconfig_writedata),
+ .analog_reconfig_write(analog_reconfig_write),
+ .analog_reconfig_read(analog_reconfig_read),
+ .analog_reconfig_readdata(analog_reconfig_readdata),
+ .analog_reconfig_waitrequest(analog_reconfig_waitrequest),
+ .analog_reconfig_done(analog_reconfig_done),
+ .analog_reconfig_irq_from_base(analog_reconfig_irq_from_base),
+ .analog_reconfig_waitrequest_from_base(analog_reconfig_waitrequest_from_base),
+ .analog_reconfig_address_base(analog_reconfig_address_base),
+ .analog_reconfig_writedata_base(analog_reconfig_writedata_base),
+ .analog_reconfig_write_base(analog_reconfig_write_base),
+ .analog_reconfig_read_base(analog_reconfig_read_base),
+ .analog_reconfig_readdata_base(analog_reconfig_readdata_base),
+ .arb_req(arb_req),
+ .arb_grant(arb_grant)
+
+ );
+ end
+ else if(device_family == "Arria V")
+ begin
+ alt_xcvr_reconfig_analog_av reconfig_analog_av(
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .analog_reconfig_address(analog_reconfig_address),
+ .analog_reconfig_writedata(analog_reconfig_writedata),
+ .analog_reconfig_write(analog_reconfig_write),
+ .analog_reconfig_read(analog_reconfig_read),
+ .analog_reconfig_readdata(analog_reconfig_readdata),
+ .analog_reconfig_waitrequest(analog_reconfig_waitrequest),
+ .analog_reconfig_done(analog_reconfig_done),
+ .analog_reconfig_irq_from_base(analog_reconfig_irq_from_base),
+ .analog_reconfig_waitrequest_from_base(analog_reconfig_waitrequest_from_base),
+ .analog_reconfig_address_base(analog_reconfig_address_base),
+ .analog_reconfig_writedata_base(analog_reconfig_writedata_base),
+ .analog_reconfig_write_base(analog_reconfig_write_base),
+ .analog_reconfig_read_base(analog_reconfig_read_base),
+ .analog_reconfig_readdata_base(analog_reconfig_readdata_base),
+ .arb_req(arb_req),
+ .arb_grant(arb_grant)
+
+ );
+ end
+ else
+ begin
+ assign analog_reconfig_readdata = 32'd0;
+ assign analog_reconfig_waitrequest = 1'd0;
+ assign analog_reconfig_done = 1'd1;
+ assign analog_reconfig_address_base = 3'd0;
+ assign analog_reconfig_writedata_base = 32'd0;
+ assign analog_reconfig_write_base = 1'd0;
+ assign analog_reconfig_read_base = 1'd0;
+ assign arb_req = 1'd0;
+ end
+
+endgenerate
+
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_analog_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_analog_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..b124cab8495ba45a26198a9b5ab25318441e6f01
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_analog_tgx.v
@@ -0,0 +1,763 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_analog_tgx (
+
+input wire reconfig_clk, // this will be the reconfig clk
+input wire reset,
+
+//avalon MM slave
+input wire [2:0] analog_reconfig_address, // MM address
+input wire [31:0] analog_reconfig_writedata,
+input wire analog_reconfig_write,
+input wire analog_reconfig_read,
+
+//output MM slave
+output reg [31:0] analog_reconfig_readdata, // from MM
+output wire analog_reconfig_waitrequest,
+//output wire analog_reconfig_error,
+output reg analog_reconfig_done,
+
+// input from base_reconfig
+ input wire analog_reconfig_irq_from_base,
+ input wire analog_reconfig_waitrequest_from_base,
+
+
+// output to base_reconfig
+// Avalon MM Master
+output wire [4:0] analog_reconfig_address_base, // 3 bit MM
+output wire [31:0] analog_reconfig_writedata_base,
+output wire analog_reconfig_write_base, // start write to GXB
+output wire analog_reconfig_read_base, // start read from GXB
+
+// input from base reconfig
+input wire [31:0] analog_reconfig_readdata_base // data from read command
+);
+
+parameter device_family = "Stratix IV"; // or ArriaII
+
+// new memory map -- register indirection
+//----------------------------------------------
+// address data[15:0]
+// 0 wr/rd logical_channel_address
+// 1 rd physical_chnl
+// 2 wr/rd control (write, read) / status (error, datavalid, busy)
+// 3 wr/rd addr_offset
+// 4 wr/rd data
+//
+// addr_offset ( upto 16 bits)
+// 0-15 TX parameters : vod, preemph_0t, preemph_1t, preemph_2t
+// 16-31 RX parameters : dcgain, eqctrl
+
+//local parameters
+localparam ADDR_WIDTH = 3;
+
+localparam IDLE = 4'b0000;
+localparam READ_FROM_GXB = 4'b0001;
+localparam WRITE_TO_GXB = 4'b0010;
+localparam SET_INFO_ON_BASIC = 4'b0011;
+localparam WRITE_DONE = 4'b0100;
+localparam READ_FROM_BASIC = 4'b0101;
+localparam READ_FROM_BASIC_DONE = 4'b0110;
+localparam READ_IDLE = 4'b0111;
+localparam GET_MUTEX = 4'b1000;
+localparam WRITE_CHL_ADDR = 4'b1001;
+localparam READ_OR_SET_INFO = 4'b1010;
+
+localparam ILLEGAL_PHYSICAL_CHNL = 12'b111111111111;
+
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [3:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+//reg [3:0] prev_state;
+genvar i;
+integer j;
+wire [(2**ADDR_WIDTH)-1:0] address_decode;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [4:0] master_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_read;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [31:0] master_writedata;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] chnl_addr_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [11:0] phys_chnl_addr_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg logical_chnl_addr_updated;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] status_reg;
+reg [1:0] control_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] data_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg needs_second_access;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [4:0] addr_offset;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg needs_second_write_access;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg do_read_before_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg set_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg have_mutex;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg req_and_use_mutex;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg do_read_phys_chnl;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg do_write_chnl_addr;
+
+wire mutex_grant;
+wire mutex_acq_waitrequest;
+wire [31:0] mutex_acq_readdata;
+wire accessing_rxeqctrl;
+wire accessing_rxdcgain;
+wire accessing_vod;
+wire accessing_preemph1t;
+wire accessing_preemph0t;
+wire accessing_preemph2t;
+
+// Implement waitrequest to match previous implementation
+altera_wait_generate wait_gen(
+ .rst(reset),
+ .clk(reconfig_clk),
+ .launch_signal(analog_reconfig_read),
+ .wait_req(analog_reconfig_waitrequest)
+);
+
+// synopsys translate_off
+initial begin
+ state <= 3'b000;
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ master_writedata <= 16'b0;
+ master_addr <= 5'b0;
+ status_reg <= 2'b0;
+ control_reg <= 2'b0;
+ data_reg <= 16'b0;
+ needs_second_access <= 1'b0;
+ do_read_before_write <= 1'b0;
+ addr_offset <= 5'b0;
+ set_addr <= 1'b0;
+ needs_second_write_access <= 1'b0;
+ have_mutex <= 0;
+ req_and_use_mutex <= 0;
+ do_read_phys_chnl <= 0;
+ do_write_chnl_addr <= 0;
+ logical_chnl_addr_updated <= 0;
+end
+// synopsys translate_on
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset)
+ begin
+ state <= IDLE;
+ analog_reconfig_readdata[31:0] <= 32'b0;
+ analog_reconfig_done <= 1'b0;
+ status_reg <= 2'b0;
+ control_reg <= 2'b0;
+ needs_second_access <= 1'b0;
+ needs_second_write_access <= 1'b0;
+ set_addr <= 1'b0;
+ do_read_before_write <= 1'b0;
+ data_reg <= 16'b0;
+ have_mutex <= 0;
+ req_and_use_mutex <= 0;
+ do_read_phys_chnl <= 0;
+ do_write_chnl_addr <= 0;
+ logical_chnl_addr_updated <= 0;
+ end
+ else begin
+ have_mutex <= mutex_grant;
+ if (analog_reconfig_read == 1'b1) // allow status read during GX read
+ begin
+ if (analog_reconfig_address == 3'b000) // logical channel address
+ analog_reconfig_readdata <= {{16{1'b0}}, chnl_addr_reg};
+ else if (analog_reconfig_address == 3'b001) // physical channel address
+ analog_reconfig_readdata <= {{20{1'b0}}, phys_chnl_addr_reg};
+ else if (analog_reconfig_address == 3'b010) // status
+ analog_reconfig_readdata <= {{22{1'b0}}, status_reg[1:0], {8{1'b0}}};
+ else if (analog_reconfig_address == 3'b011) // TX/RX offset
+ analog_reconfig_readdata <= {{16{1'b0}}, addr_offset};
+ else if (analog_reconfig_address == 3'b100) // previously read data
+ analog_reconfig_readdata <= {{16{1'b0}}, data_reg};
+ else
+ analog_reconfig_readdata <= {32{1'b0}};
+ end
+ case (state)
+ IDLE: begin
+ needs_second_access <= 1'b0;
+ if (analog_reconfig_address == 3'b0)
+ begin
+ if (analog_reconfig_write == 1'b1)
+ begin
+ chnl_addr_reg <= {{4{1'b0}},analog_reconfig_writedata[11:0]}; // write logical_ch_addr
+ logical_chnl_addr_updated <= 1'b1;
+ end
+ end
+ else if (analog_reconfig_write == 1'b1 && analog_reconfig_address == 3'b011) // addr_offset
+ begin
+ addr_offset <= analog_reconfig_writedata[4:0];
+ end
+ else if (analog_reconfig_address == 3'b100) // DPRIO write data
+ begin
+ if (analog_reconfig_write == 1'b1)
+ data_reg[15:0] <= analog_reconfig_writedata[15:0];
+ end
+ else if (analog_reconfig_read == 1'b1 && analog_reconfig_address == 3'b001) // physical chnl
+ begin
+ if (logical_chnl_addr_updated == 1'b1) // if logical chnl addr was updated from the last time we read the phys addr, go do the read again
+ begin
+ status_reg <= {1'b0, 1'b1}; //set busy bit
+ if (have_mutex)
+ begin
+ state <= WRITE_CHL_ADDR;
+ do_read_phys_chnl <= 1;
+ end
+ else begin
+ state <= READ_IDLE;
+ req_and_use_mutex <= 1'b1;
+ do_write_chnl_addr <= 1'b1;
+ do_read_phys_chnl <= 1;
+ end
+ logical_chnl_addr_updated <= 1'b0;
+ end
+ end
+ else if (analog_reconfig_address == 3'b010 && analog_reconfig_write == 1'b1) // control reg bit 1 rd, bit 0 wr
+ begin
+ status_reg <= {1'b0, 1'b1}; // set busy bit
+ control_reg <= analog_reconfig_writedata[1:0];
+ if (analog_reconfig_writedata[0] == 1'b1)
+ do_read_before_write <= 1'b1;
+ if (have_mutex)
+ begin
+ state <= WRITE_CHL_ADDR;
+ end
+ else begin
+ state <= READ_IDLE;
+ req_and_use_mutex <= 1'b1;
+ do_write_chnl_addr <= 1'b1;
+ status_reg <= {1'b0, 1'b1}; // set busy bit
+ end
+ end
+ else if (analog_reconfig_address > 3'b100 && analog_reconfig_write == 1'b1) //
+ begin
+ // synopsys translate_off
+ $display ("Illegal operation to reserved address %h", analog_reconfig_address);
+ $display ("Time: %0t Instance: %m", $time);
+ // synopsys translate_on
+ end
+ else if (have_mutex == 1'b1)
+ begin
+ // holding the mutex in idle state, release it
+ req_and_use_mutex <= 1'b0;
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ end
+ end
+ WRITE_CHL_ADDR: begin
+ master_addr <= 5'b00100;
+ master_write <= 1'b1;
+ master_writedata <= chnl_addr_reg;
+ state <= READ_OR_SET_INFO;
+ end
+ READ_OR_SET_INFO: begin
+ if (analog_reconfig_waitrequest_from_base == 1'b1)
+ state <= READ_OR_SET_INFO;
+ else
+ begin
+ master_write <= 1'b0;
+ if (do_read_phys_chnl)
+ begin
+ state <= READ_FROM_BASIC;
+ // do_read_phys_chnl = 0;
+ end
+ else begin
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ master_read <= 0;
+ end
+ end
+ end
+ GET_MUTEX:
+ begin
+ if (have_mutex == 1'b1)
+ begin
+ if (do_write_chnl_addr == 1'b1)
+ state <= WRITE_CHL_ADDR;
+ else
+ state <= READ_OR_SET_INFO;
+ end
+ else
+ begin
+ state <= GET_MUTEX;
+ end
+ end
+ READ_FROM_BASIC: begin
+ if (analog_reconfig_waitrequest == 1'b0)
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ if (analog_reconfig_irq_from_base == 1'b1) // start read access to data reg. of base_reconfig
+ begin
+ master_addr <= 5'b10100;
+ end
+ else begin
+ master_addr <= 5'b01000;
+ end
+ state <= READ_IDLE;
+ end
+ else
+ begin
+ state <= READ_FROM_BASIC;
+ end
+ end
+ READ_IDLE: begin
+ if (analog_reconfig_waitrequest == 1'b0)
+ begin
+ if (have_mutex)
+ state <= READ_FROM_BASIC_DONE;
+ else
+ begin
+ state <= GET_MUTEX;
+ end
+ end
+ else
+ begin
+ state <= READ_IDLE;
+ end
+ end
+ READ_FROM_BASIC_DONE: begin
+ if (analog_reconfig_waitrequest == 1'b0)
+ begin
+ master_read <= 1'b0;
+ if (do_read_phys_chnl)
+ begin
+ do_read_phys_chnl <= 0;
+ phys_chnl_addr_reg <= mutex_acq_readdata[11:0];
+ if (mutex_acq_readdata[11:0] == ILLEGAL_PHYSICAL_CHNL)
+ begin
+ //set error bit
+ status_reg <= {1'b1, 1'b0};
+ // error message for sim
+ //$display();
+ //$display();
+ end
+ else begin
+ // unset busy bit
+ status_reg <= 2'b0;
+ end
+ state <= IDLE;
+ end
+ else if (accessing_vod)
+ begin
+
+ // This is for Stratix IV only
+ //////////////////////////////////////////////////
+ //Port | DPRIO CRAM bit value
+ //2..0 | 2..0
+ //////////////////////////////////////////////////
+ //000 | 000
+ //001 | 001
+ //010 | 010
+ //011 | 110
+ //100 | 011
+ //101 | 111
+ //110 | 100
+ //111 | 101
+ /////////////////////////////////////////////////
+ if (control_reg[0] == 1'b1) // this was a write cycle to begin with
+ begin
+ master_writedata[31:16] <= {16{1'b0}};
+ master_writedata[15:13] <= {(data_reg[2] & data_reg[1]) | (data_reg[2] & data_reg[0]) | (data_reg[1] & data_reg[0]), data_reg[2] ^ data_reg[1], (~data_reg[1] & data_reg[0]) | (data_reg[2] & data_reg[0]) | (data_reg[2] & ~data_reg[1])};
+ master_writedata[12:0] <= mutex_acq_readdata[12:0];
+ master_addr <= 5'b10100;
+ master_write <= 1'b1;
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ end
+ else begin
+ data_reg <= {{13{1'b0}}, (mutex_acq_readdata[15] & ~mutex_acq_readdata[14]) | (mutex_acq_readdata[14] & mutex_acq_readdata[13]), (mutex_acq_readdata[15] & ~mutex_acq_readdata[14]) | (mutex_acq_readdata[14] & ~mutex_acq_readdata[13]), (~mutex_acq_readdata[14] & mutex_acq_readdata[13]) | (mutex_acq_readdata[15] & mutex_acq_readdata[14])};
+ // unset busy bit
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ else if (accessing_rxdcgain)
+ begin
+ // This is for Stratix IV only
+ //////////////////////////////////////////////////
+ //Port | DRIO CRAM bit value
+ //2..0 | 10..7
+ //////////////////////////////////////////////////
+ //000 | 0000
+ //001 | 0001
+ //010 | 0011
+ //011 | 0111
+ //100 | 1111
+ //Others | Assume to be 1's
+ /////////////////////////////////////////////////
+
+ // This is for Arria II only
+ //////////////////////////////////////////////////
+ //Port | DRIO CRAM bit value
+ //1..0 | 10..7
+ //////////////////////////////////////////////////
+ //00 | 0000
+ //01 | 0001
+ //10 | 0011
+ //Others | Assume to be 1's
+ /////////////////////////////////////////////////
+ if (control_reg[0] == 1'b1)
+ begin
+ if ((device_family == "Stratix IV") || (device_family == "HardCopy IV"))
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:11], data_reg[2], data_reg[1] & data_reg[0] | data_reg[2], data_reg[2] | data_reg[1], data_reg[2] | data_reg[1] | data_reg[0], mutex_acq_readdata[6:0]};
+ else
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:11], 1'b0, 1'b0, data_reg[1], data_reg[1] | data_reg[0], mutex_acq_readdata[6:0]};
+ master_addr <= 5'b10100;
+ master_write <= 1'b1;
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ end
+ else begin
+ if ((device_family == "Stratix IV") || (device_family == "HardCopy IV"))
+ data_reg <= {{13{1'b0}}, mutex_acq_readdata[10], ~mutex_acq_readdata[10] & mutex_acq_readdata[8], mutex_acq_readdata[10] ^ mutex_acq_readdata[9] ^ mutex_acq_readdata[8] ^ mutex_acq_readdata[7]};
+ else
+ data_reg <= {{14{1'b0}}, mutex_acq_readdata[8], mutex_acq_readdata[7] ^ mutex_acq_readdata[8]};
+ // unset busy bit
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ else if (accessing_rxeqctrl) // encode/decode rx_eqctrl
+ begin
+ ////////////////////////////////////////
+ // Wiz A B C D V
+ // 3210 EDC BA9 876 543 210
+ // 0000 000 000 000 000 000
+ // L0 0001 011 000 000 000 111
+ // L1 0010 100 000 000 000 000
+ // L2 0011 111 000 000 000 000
+ // L3 0100 111 000 000 000 111
+ // L4 0101 101 101 000 000 000
+ // M0 0110 111 111 000 000 000
+ // M1 0111 111 111 000 000 100
+ // M2 1000 111 111 000 000 111
+ // M3 1001 111 111 111 000 001
+ // M4 1010 111 111 111 000 100
+ // H0 1011 111 111 111 111 000
+ // H1 1100 111 111 111 111 001
+ // H2 1101 111 111 111 111 100
+ // H3 1110 111 111 111 111 110
+ // H4 1111 111 111 111 111 111
+ ////////////////////////////////////////
+ if (control_reg[0] == 1'b1)
+ begin
+ master_writedata[31:16] <= 0;
+ master_writedata[15] <= mutex_acq_readdata[15];
+ if (data_reg[3:0] > 4'b1010)
+ master_writedata[14:3] <= {12{1'b1}};
+ else if (data_reg[3:0] > 4'b0110)
+ master_writedata[14:3] <= {{3{1'b0}}, {9{1'b1}}};
+ else if (data_reg[3:0] > 4'b0011)
+ master_writedata[14:3] <= {{6{1'b0}}, {6{1'b1}}};
+ else if (data_reg[3:0] > 4'b0)
+ master_writedata[14:3] <= {{9{1'b0}}, {3{1'b1}}};
+ else
+ master_writedata[14:3] <= {12{1'b0}};
+ master_writedata[2] <= (data_reg[1] & ~data_reg[0]) | (~data_reg[3] & ~data_reg[2] & data_reg[1]) | (data_reg[2] & ~data_reg[1] & data_reg[0] | (data_reg[3] & data_reg[2] & data_reg[0]) | (data_reg[3] & ~data_reg[2] & ~data_reg[1]));
+ master_writedata[1] <= ( data_reg[1] & (data_reg[0] ^ (data_reg[2] ^ data_reg[3]))) | (data_reg[3] & data_reg[2] & ~data_reg[1] & ~data_reg[0]);
+ master_writedata[0] <= (~(data_reg[3] ^ data_reg[2]) & data_reg[1] & data_reg[0]) | (data_reg[2] & data_reg[1] & ~data_reg[0]) | (data_reg[3] & data_reg[1] & ~data_reg[0]) | (data_reg[3] & data_reg[2] & ~data_reg[0]) | (data_reg[3] & ~data_reg[2] & ~data_reg[1] & data_reg[0]);
+
+ master_addr <= 5'b10100;
+ master_write <= 1'b1;
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ end
+ else begin
+ if (mutex_acq_readdata[14:12] == 3'b111) // > 10
+ data_reg <= {{12{1'b0}}, 1'b1, (mutex_acq_readdata[1] & mutex_acq_readdata[0]) | (mutex_acq_readdata[2] & ~mutex_acq_readdata[1]), (mutex_acq_readdata[2] & mutex_acq_readdata[0]) | (~mutex_acq_readdata[0] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[2]), (~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]) | (mutex_acq_readdata[2] & mutex_acq_readdata[1] & mutex_acq_readdata[0])};
+ else if (mutex_acq_readdata[11:9] == 3'b111) // > 6 only
+ data_reg <= {{12{1'b0}}, mutex_acq_readdata[2], ~mutex_acq_readdata[2], (mutex_acq_readdata[2] & mutex_acq_readdata[1] & mutex_acq_readdata[0]) | (~mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]), (~mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]) | (mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & mutex_acq_readdata[0])};
+ else if (mutex_acq_readdata[8:6] == 3'b111) // > 3 only
+ data_reg <= {{12{1'b0}}, 1'b0, 1'b1, mutex_acq_readdata[2] & mutex_acq_readdata[1] & mutex_acq_readdata[0], mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]};
+ else if (mutex_acq_readdata[5:3] == 3'b111) // > 0 only
+ data_reg <= {{12{1'b0}}, {2{1'b0}}, (mutex_acq_readdata[2] & mutex_acq_readdata[1] & mutex_acq_readdata[0]) | (mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]), (mutex_acq_readdata[2] & mutex_acq_readdata[1] & mutex_acq_readdata[0]) | (~mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]) };
+ else
+ data_reg <= {16{1'b0}};
+
+ // unset busy bit
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ else if (accessing_preemph1t)
+ begin
+ // This is for Arria II only
+ //////////////////////////////////////////////////
+ //Port | DRIO CRAM bit value
+ //4..0 | 15..11
+ //////////////////////////////////////////////////
+ //00000 | 00000
+ //00001 | 00001
+ //00010 | 00101
+ //00011 | 01001
+ //00100 | 01101
+ //00101 | 10001
+ //00110 | 10101
+ //Others | Assume to be 1's
+ /////////////////////////////////////////////////
+ if (control_reg[0] == 1'b1)
+ begin
+ if (device_family == "Stratix IV")
+ master_writedata <= {{16{1'b0}}, data_reg[4:0], mutex_acq_readdata[10:0]};
+ else
+ master_writedata <= {{16{1'b0}}, data_reg[2] & data_reg[1] ^ data_reg[0], data_reg[2] & ~data_reg[1] & ~data_reg[0] | (data_reg[1] & data_reg[0]), (data_reg[2] | data_reg[1]) & ~data_reg[0], 1'b0, (data_reg[2] | data_reg[1] | data_reg[0]), mutex_acq_readdata[10:0]};
+ master_addr <= 5'b10100;
+ master_write <= 1'b1;
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ end
+ else begin
+ if (device_family == "Stratix IV")
+ data_reg <= {{11{1'b0}}, mutex_acq_readdata[15:11]};
+ else
+ data_reg <= {{11{1'b0}}, 1'b0, 1'b0, mutex_acq_readdata[15] | (mutex_acq_readdata[14] & mutex_acq_readdata[13]), mutex_acq_readdata[14] ^ mutex_acq_readdata[13], mutex_acq_readdata[13] ^ mutex_acq_readdata[11]};
+ // unset busy bit
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ else if (accessing_preemph0t || accessing_preemph2t)
+ begin
+ if (control_reg[0] == 1'b1)
+ begin
+ if (accessing_preemph0t)
+ begin
+ if (needs_second_write_access)
+ begin
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:5], ~data_reg[4], mutex_acq_readdata[3:0]};
+ end
+ else begin
+ if (data_reg[4] == 1'b0)
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:4], 4'b0000 - data_reg[3:0]};
+ else
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:4], data_reg[3:0]};
+ end
+ end
+ else if (accessing_preemph2t)
+ begin
+ if (needs_second_write_access)
+ begin
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:4], ~data_reg[4], mutex_acq_readdata[2:0]};
+ end
+ else begin
+ if (data_reg[4] == 1'b0)
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:8], 4'b0000 - data_reg[3:0], mutex_acq_readdata[3:0]};
+ else
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:8], data_reg[3:0], mutex_acq_readdata[3:0]};
+ end
+ end
+ master_addr <= 5'b10100;
+ master_write <= 1'b1;
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ end
+ else begin
+ if (needs_second_access)
+ begin
+ data_reg <= mutex_acq_readdata[15:0];
+ master_write <= 1'b1; // start access for INV bit
+ master_addr <= 5'b10000;
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {8{1'b0}}, 2'b11}; // DPRIO register address
+ state <= SET_INFO_ON_BASIC;
+ needs_second_access <= 1'b0;
+ end
+ else begin
+ if (accessing_preemph0t)
+ begin
+ if (mutex_acq_readdata[4] == 1'b1)
+ data_reg <= {{11{1'b0}}, 1'b0, 4'b0000 - data_reg[3:0]};
+ else
+ data_reg <= {{11{1'b0}}, 1'b1, data_reg[3:0]};
+ end
+ else begin
+ if (mutex_acq_readdata[3] == 1'b1)
+ data_reg <= {{11{1'b0}}, 1'b0, 4'b0000 - data_reg[7:4]};
+ else
+ data_reg <= {{11{1'b0}}, 1'b1, data_reg[7:4]};
+ end
+ // unset busy
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ end
+ else begin // dont know what the operation is
+ analog_reconfig_readdata <= mutex_acq_readdata;
+ // unset busy bit
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ else
+ begin
+ state <= READ_FROM_BASIC_DONE;
+ end
+ end
+ SET_INFO_ON_BASIC: begin
+ if (set_addr)
+ begin
+ master_addr <= 5'b10000;
+ master_write <= 1'b1;
+ if (accessing_vod)
+ begin
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {10{1'b0}}};
+ end
+ else if (accessing_preemph1t)
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {8{1'b0}}, 2'b01};
+ else if (accessing_rxdcgain)
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b11, 10'b0};
+ else if (accessing_rxeqctrl)
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b11, 10'b0000001011};
+ else if (accessing_preemph0t || accessing_preemph2t)
+ begin
+ if (needs_second_write_access)
+ begin
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {8{1'b0}}, 2'b11};
+ end
+ else
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {8{1'b0}}, 2'b10};
+ if (control_reg[1] == 1'b1) // pure read cycle
+ needs_second_access <= 1'b1;
+ end
+ set_addr <= 1'b0;
+ end
+ else if (control_reg[1] == 1'b1 || (control_reg[0] == 1'b1 & do_read_before_write)) // read
+ begin
+ master_addr <= 5'b01100;
+ master_write <= 1'b1;
+ master_writedata <= {{16{1'b0}}, {14{1'b0}}, 2'b10}; // initiate read first
+ state <= READ_FROM_GXB;
+ do_read_before_write <= 1'b0;
+ end
+ else if (control_reg[0] == 1'b1) // actual write
+ begin
+ master_write <= 1'b1;
+ master_addr <= 5'b01100;
+ master_writedata <= {{16{1'b0}}, {14{1'b0}}, 2'b01}; // issue write to basic's control_reg to start WRITE
+ state <= WRITE_TO_GXB;
+ end
+ end
+ READ_FROM_GXB: begin
+ master_write <= 1'b0;
+ if (analog_reconfig_irq_from_base == 1'b1)
+ state <= READ_FROM_BASIC;
+ end
+ WRITE_TO_GXB: begin
+ master_write <= 1'b0;
+ if (analog_reconfig_irq_from_base == 1'b1)
+ begin
+ //start access to clear interrupt control reg. on slave
+ master_addr <= 5'b01100;
+ master_write <= 1'b1;
+ master_writedata <= {{16{1'b0}}, {13{1'b0}}, 3'b000};
+ state <= WRITE_DONE;
+ end
+ end
+ WRITE_DONE: begin
+ master_write <= 1'b0;
+ if (analog_reconfig_irq_from_base == 1'b1)
+ begin
+ if ((accessing_preemph0t || accessing_preemph2t) & (!needs_second_write_access))
+ begin
+ needs_second_write_access <= 1'b1;
+ do_read_before_write <= 1'b1;
+ master_write <= 1'b1;
+ master_addr <= 5'b10000;
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {8{1'b0}}, 2'b11}; // DPRIO register address for INV
+ state <= SET_INFO_ON_BASIC;
+ end
+ else begin
+ needs_second_write_access <= 1'b0;
+ status_reg <= {1'b0, 1'b0}; // unset busy
+ analog_reconfig_done <= 1'b1; // send INTERRUPT
+ state <= IDLE;
+ end
+ end
+ end
+ default:begin
+ state <= IDLE;
+ end
+ endcase
+ end
+// prev_state <= state;
+end
+
+assign accessing_vod = (addr_offset[4:0] == 5'b0);
+assign accessing_preemph0t = (addr_offset[4:0] == 5'b00001);
+assign accessing_preemph1t = (addr_offset[4:0] == 5'b00010);
+assign accessing_preemph2t = (addr_offset[4:0] == 5'b00011);
+assign accessing_rxdcgain = (addr_offset[4] == 1'b1 && addr_offset[3:0] == 4'b0000);
+assign accessing_rxeqctrl = (addr_offset[4] == 1'b1 && addr_offset[3:0] == 4'b0001);
+
+//assign analog_reconfig_address_base = master_addr;
+//assign analog_reconfig_write_base = master_write;
+//assign analog_reconfig_read_base = master_read;
+//assign analog_reconfig_writedata_base = master_writedata;
+
+
+ alt_mutex_acq #(
+ .mutex_wait_time(101),
+ .addr_width(5),
+ .data_width(32)
+ )
+ mutex_inst (
+ .clk(reconfig_clk),
+ .reset(reset),
+ // inputs to the base that should be routed through the mutex
+ .address(master_addr),
+ .writedata(master_writedata),
+ .write(master_write),
+ .read(master_read),
+ // output from the mutex which is processed form of output from base
+ .waitrequest(mutex_acq_waitrequest),
+ .readdata(mutex_acq_readdata),
+
+
+ // outputs from mutex to be routed to the base
+ .master_address(analog_reconfig_address_base),
+ .master_writedata(analog_reconfig_writedata_base),
+ .master_write(analog_reconfig_write_base),
+ .master_read(analog_reconfig_read_base),
+
+ // these ports are from the base routed to the mutex
+ .master_waitrequest(analog_reconfig_waitrequest_from_base),
+ .master_readdata(analog_reconfig_readdata_base), // from MM
+
+ //request signal to the mutex should be kept high as long as the mutex is being used
+ .mutex_req(req_and_use_mutex),
+ // output from mutex indicates whether you have mutex or not
+ .mutex_grant(mutex_grant)
+ );
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_basic_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_basic_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..2c4f79b384db04a1ab6911dc33951886c61d0f08
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_basic_tgx.v
@@ -0,0 +1,367 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+(* ALTERA_ATTRIBUTE = {"{-to address_pres_reg[11]} DPRIO_CHANNEL_NUM=11;{-to address_pres_reg[10]} DPRIO_CHANNEL_NUM=10;{-to address_pres_reg[9]} DPRIO_CHANNEL_NUM=9;{-to address_pres_reg[8]} DPRIO_CHANNEL_NUM=8;{-to address_pres_reg[7]} DPRIO_CHANNEL_NUM=7;{-to address_pres_reg[6]} DPRIO_CHANNEL_NUM=6;{-to address_pres_reg[5]} DPRIO_CHANNEL_NUM=5;{-to address_pres_reg[4]} DPRIO_CHANNEL_NUM=4;{-to address_pres_reg[3]} DPRIO_CHANNEL_NUM=3;{-to address_pres_reg[2]} DPRIO_CHANNEL_NUM=2;{-to address_pres_reg[1]} DPRIO_CHANNEL_NUM=1;{-to address_pres_reg[0]} DPRIO_CHANNEL_NUM=0; disable_da_rule=\"S102,R102\""} *)
+module alt_xcvr_reconfig_basic_tgx
+#( parameter number_of_reconfig_interfaces = 1
+ )
+(
+ // avalon clock interface
+ input wire reconfig_clk,
+ input wire reset,
+
+ // avalon MM
+ input wire basic_reconfig_write,
+ input wire basic_reconfig_read,
+ input wire [31:0] basic_reconfig_writedata,
+ input wire [2:0] basic_reconfig_address, // address to MM described below
+
+ output reg [31:0] basic_reconfig_readdata, // reconfig_fromgxb_data
+ output wire basic_reconfig_waitrequest,
+
+ // avalon MM
+// output wire reconfig_write_base,
+// output wire reconfig_read_base,
+// output wire [31:0] reconfig_writedata_base,
+// output wire [4:0] reconfig_address_base, // address to MM described below
+
+// input wire [31:0] reconfig_readdata_base, // reconfig_fromgxb_data
+// input wire reconfig_waitrequest_from_base,
+
+
+ // avalon ST interface
+ input wire [number_of_reconfig_interfaces*17 - 1 : 0] basic_reconfig_fromgxb_data, // dprioout, testbus from altgx : (17+4 bits/quad)
+ input wire [number_of_reconfig_interfaces*8 - 1 : 0] aeq_fromgxb_data, // for ADCE dprio
+ output wire [3:0] basic_reconfig_togxb_data, // busy, dprioin, dprioload, dpriodisable and aeq to altgx
+ output reg [number_of_reconfig_interfaces*24 - 1 : 0] aeq_togxb_data, // for ADCE
+ output reg [number_of_reconfig_interfaces*16 - 1 : 0] testbus_data,
+
+ output reg basic_reconfig_irq // interrupt to Master
+);
+
+//assign reconfig_write_base = 1'b0;
+//assign reconfig_read_base = 1'b0;
+//assign reconfig_writedata_base = 32'd0;
+//assign reconfig_address_base = 5'd0;
+
+
+// Memeory Map for register indirection
+// addr wr/rd description
+// ------------------------------------------------------
+// 0 wr/rd mutex : bit[0]
+// 1 wr/rd logical_ch_addr (10 bits)
+// 2 rd physical_chnl_map
+// 3 rd/wr status/control -- bit 0 busy/bit 1 read, bit 0 write, bit 3 = absolute addressing
+// 4 wr/rd DPRIO addr_offset
+// 5 wr/rd DPRIO data
+// 6 rd/wr adce_standby, adce_capture, testbussel : bit 7 -- adcedone, bit 6 -- adcetestbus, bits 5,4 -- adce, 3 to 0 -- bussel
+// 7 rd/wr offset cancellation busy output to GX bit 0
+
+//local parameters
+localparam quad_address_width = 9;
+localparam IDLE_STATE = 2'b00;
+localparam WRITE_STATE = 2'b01;
+localparam READ_STATE = 2'b10;
+
+
+(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON"} *)
+reg [11:0] address_pres_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [11:0] logical_channel_addr_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [14:0] dprio_table_addr_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] pma_pcs_id_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg dprio_busy_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] data_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [5:0] testbussel;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] adce_testdata;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] control_reg;
+// mutex
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg mutex_value;
+//reg [15:0] mutex_owner;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [10:0] mutex_timeout_cntr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg offset_cancellation_busy;
+
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg basic_reconfig_absolute_addressing;
+
+
+wire [quad_address_width-1:0] quad_address;
+wire [quad_address_width-1:0] dprio_quad_address;
+
+wire busy_state;
+wire [15:0] dprio_address;
+wire dprio_busy;
+wire [15:0] dprio_datain;
+wire [15:0] dprio_dataout;
+wire dprio_dprioout;
+wire dprio_rden;
+wire dprio_pulse;
+wire rd_pulse;
+wire read_done;
+wire read_word_done;
+wire reset_system;
+wire dprio_wren;
+wire write_done;
+wire wr_pulse;
+wire read_data_valid;
+wire write_word_done;
+
+integer i,j;
+
+
+assign basic_reconfig_waitrequest = 1'b0;
+
+// synopsys translate_off
+initial
+begin
+ state = 2'b00;
+ basic_reconfig_irq = 1'b0;
+ logical_channel_addr_reg = 12'b0;
+ testbussel = 0;
+ control_reg = 0;
+ mutex_value = 0;
+ mutex_timeout_cntr = 0;
+ offset_cancellation_busy = 0;
+ data_reg = 16'h0000;
+ dprio_table_addr_reg = 15'h0000;
+ pma_pcs_id_reg = 2'b00;
+
+end
+// synopsys translate_on
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset === 1'b1)
+ adce_testdata <= 0;
+ else begin
+ for (i=0; i<=1; i=i+1)
+ begin
+ adce_testdata[i] <= aeq_fromgxb_data[(logical_channel_addr_reg) + i];
+ end
+ end
+end
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset === 1'b1)
+ begin
+ state <= IDLE_STATE;
+ basic_reconfig_readdata <= 16'b0;
+ basic_reconfig_irq <= 1'b0;
+ testbussel <= 0;
+ control_reg <= 0;
+ // mutex registers
+ mutex_value <= 0;
+ mutex_timeout_cntr <= 0;
+ end
+ else begin
+ // mutex
+ if (basic_reconfig_address == 3'b0)
+ begin
+ //read first only update the mutex_value
+ if (basic_reconfig_read == 1'b1)
+ begin
+ basic_reconfig_readdata <= {{31{1'b0}}, mutex_value};
+ // if (basic_reconfig_waitrequest == 1'b0)
+ if (mutex_value == 1'b0) // mutex is free, so grant access
+ mutex_value <= 1'b1;
+ end
+ else if (basic_reconfig_write == 1'b1)
+ begin
+ mutex_value <= 0;
+ end
+ end
+
+ case (state)
+ IDLE_STATE: begin
+ if (basic_reconfig_write == 1'b1)
+ begin
+ mutex_timeout_cntr <= 0; // reset the mutex_timeout counter
+ if (basic_reconfig_address == 3'b001)
+ begin
+ logical_channel_addr_reg <= basic_reconfig_writedata[11:0];
+ address_pres_reg <= {basic_reconfig_writedata[10:2], 1'b0, basic_reconfig_writedata[1:0]}; //chestan
+ end
+ else if (basic_reconfig_address == 3'b100)
+ begin
+ dprio_table_addr_reg <= basic_reconfig_writedata[14:0];
+ pma_pcs_id_reg <= basic_reconfig_writedata[11:10];
+ end
+ else if (basic_reconfig_address == 3'b011) // control reg
+ begin
+ if (basic_reconfig_writedata[0] == 1'b1) // write
+ begin
+ state <= WRITE_STATE;
+ control_reg <= 2'b01;
+ end
+ else if (basic_reconfig_writedata[1] == 1'b1) // read
+ begin
+ state <= READ_STATE;
+ control_reg <= 2'b10;
+ end
+ if (basic_reconfig_writedata[2] == 1'b0) begin
+ basic_reconfig_irq <= 1'b0; // clear WRITE interrupt
+ end
+ basic_reconfig_absolute_addressing <= basic_reconfig_writedata[3]; // use the full address from dprio_addr, not the derived address
+ end
+ else if (basic_reconfig_address == 3'b101) // data
+ begin
+ data_reg <= basic_reconfig_writedata[15:0];
+ end
+ else if (basic_reconfig_address == 3'b110) // testbussel
+ testbussel <= basic_reconfig_writedata[5:0];
+ else if (basic_reconfig_address == 3'b111)
+ offset_cancellation_busy <= basic_reconfig_writedata[0];
+ begin
+ end
+ end
+ else if (basic_reconfig_read == 1'b1)
+ begin
+ if (basic_reconfig_address == 3'b001)
+ basic_reconfig_readdata <= {{20{1'b0}}, logical_channel_addr_reg};
+ else if (basic_reconfig_address == 3'b010) // physical chnl
+ basic_reconfig_readdata <= {{21{1'b0}}, address_pres_reg[11:3], address_pres_reg[1:0]}; // check this
+ else if (basic_reconfig_address == 3'b011) // status
+ basic_reconfig_readdata <= {{23{1'b0}}, busy_state, {5{1'b0}}, basic_reconfig_irq, control_reg};
+ else if (basic_reconfig_address == 3'b100)
+ basic_reconfig_readdata <= {{20{1'b0}}, pma_pcs_id_reg, dprio_table_addr_reg};
+ else if (basic_reconfig_address == 3'b101) // DPRIO readdata
+ begin
+ basic_reconfig_readdata <= {{16{1'b0}}, data_reg};
+ basic_reconfig_irq <= 1'b0; // clear READ interrupt
+ end
+ else if (basic_reconfig_address == 3'b110)
+ basic_reconfig_readdata <= {{24{1'b0}}, adce_testdata, testbussel};
+ else if (basic_reconfig_address == 3'b111) // testbusdata
+ basic_reconfig_readdata <= {{31{1'b0}}, offset_cancellation_busy};
+ if (basic_reconfig_address != 3'b0) // if not reading the mutex val
+ mutex_timeout_cntr <= 0; // reset the mutex counter
+ end
+ else if (mutex_value == 1'b1) // if mutex was granted to someone
+ if (mutex_timeout_cntr == 10'd1000) // and they didnt do anything for 1000 cycles
+ begin
+ mutex_value <= 1'b0; // reset the mutex and give it to the next person
+ mutex_timeout_cntr <= 0;
+ end
+ else
+ mutex_timeout_cntr <= mutex_timeout_cntr[9:0] + 10'b1; // count up the timer from the last access
+ end
+ WRITE_STATE: begin
+ if (write_done)
+ begin
+ state <= IDLE_STATE;
+ basic_reconfig_irq <= 1'b1; // send interrupt to master
+ end
+ // allow status_register read here
+ if (basic_reconfig_read == 1'b1 && basic_reconfig_address == 3'b011)
+ basic_reconfig_readdata <= {{23{1'b0}}, busy_state, {5{1'b0}}, basic_reconfig_irq, control_reg};
+ end
+ READ_STATE: begin
+ if (read_word_done == 1'b1)
+ begin
+ data_reg <= dprio_dataout;
+ basic_reconfig_irq <= 1'b1; // send interrupt
+ state <= IDLE_STATE;
+ end
+ // allow status_register read here
+ if (basic_reconfig_read == 1'b1 && basic_reconfig_address == 3'b011)
+ basic_reconfig_readdata <= {{23{1'b0}}, busy_state, {5{1'b0}}, basic_reconfig_irq, control_reg};
+ end
+ default: begin
+ state <= IDLE_STATE;
+ end
+ endcase
+ end
+end
+
+// synopsys translate_off
+initial address_pres_reg = 0;
+// synopsys translate_on
+
+assign quad_address = logical_channel_addr_reg[10:2];
+assign dprio_address[15:0] = basic_reconfig_absolute_addressing ? {1'b0, dprio_table_addr_reg[14:0]} : {1'b0, address_pres_reg[2], address_pres_reg[1:0], pma_pcs_id_reg[1:0], dprio_table_addr_reg[9:0]};
+assign dprio_quad_address = address_pres_reg[11:3];
+assign dprio_dprioout = basic_reconfig_fromgxb_data[quad_address * 17];
+assign dprio_datain = data_reg;
+assign dprio_rden = rd_pulse;
+assign rd_pulse = (state == READ_STATE) & ~dprio_pulse & ~read_done;
+assign read_done = read_word_done | reset_system;
+assign read_word_done = (state == READ_STATE) & read_data_valid;
+assign read_data_valid = (state == READ_STATE) & dprio_pulse;
+assign dprio_wren = wr_pulse;
+assign wr_pulse = (state == WRITE_STATE) & ~dprio_pulse & ~write_done;
+assign write_done = write_word_done | reset_system;
+assign write_word_done = (state == WRITE_STATE) & dprio_pulse;
+assign reset_system = reset;
+assign busy_state = (state == READ_STATE) | (state == WRITE_STATE);
+
+// synopsys translate_off
+initial dprio_busy_reg = 0;
+// synopsys translate_on
+
+always @(posedge reconfig_clk) dprio_busy_reg <= dprio_busy;
+assign dprio_pulse = (dprio_busy_reg ^ dprio_busy) & (~dprio_busy);
+
+alt_dprio inst_alt_dprio (.dpclk(reconfig_clk),
+ .datain(dprio_datain),
+ .address(dprio_address),
+ .wren(dprio_wren),
+ .rden(dprio_rden),
+// .rdinc(),
+ .wren_data(1'b0),
+ .dprioout(dprio_dprioout), // reconfig_fromgxb_data[0]
+ .quad_address(dprio_quad_address),
+ // outputs
+ .dprioin(basic_reconfig_togxb_data[0]),
+ .dpriodisable(basic_reconfig_togxb_data[1]),
+ .dprioload(basic_reconfig_togxb_data[2]),
+ .dataout(dprio_dataout),
+ .busy(dprio_busy)
+ );
+
+//assign testbus_data = (testbussel == 3'b110) ? basic_reconfig_fromgxb_data : 'b0;
+
+assign basic_reconfig_togxb_data[3] = offset_cancellation_busy;
+
+always @(basic_reconfig_fromgxb_data)
+begin
+ for (i=0; i<number_of_reconfig_interfaces; i=i+1)
+ begin
+ for (j=0; j<= 15; j=j+1)
+ begin
+ testbus_data[(i*16) + j] = basic_reconfig_fromgxb_data[(i*17) + j+1];
+ end
+ end
+end
+
+always @(logical_channel_addr_reg or testbussel)
+begin
+ aeq_togxb_data = {number_of_reconfig_interfaces*24{1'b0}};
+ for (i=0; i<=5; i=i+1)
+ begin
+ aeq_togxb_data[(logical_channel_addr_reg*6) + i] = testbussel[i];
+ end
+end
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_dfe_tgx.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_dfe_tgx.sv
new file mode 100644
index 0000000000000000000000000000000000000000..107fa27aa9d4e7684eaf3ff65891450a40db21ac
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_dfe_tgx.sv
@@ -0,0 +1,502 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_dfe_tgx
+#(
+ parameter device_family = "StratixIV",
+ parameter number_of_reconfig_interfaces = 1
+)
+(
+ input wire reconfig_clk, // this will be the reconfig clk
+ input wire reset,
+
+ //avalon MM slave
+ input wire [2:0] dfe_address, // Check this! fix me!
+ input wire [31:0] dfe_writedata,
+ input wire dfe_write,
+ input wire dfe_read,
+
+ //output MM slave
+ output wire [31:0] dfe_readdata, // from MM
+ output wire dfe_waitrequest, // from MM
+
+ output reg dfe_irq,
+
+ // input from base_reconfig
+ input wire dfe_irq_from_base,
+ input wire dfe_waitrequest_from_base,
+
+ // output to base_reconfig
+ // Avalon MM Master
+ output wire [2:0] dfe_address_base, // 3 bit MM
+ output wire [31:0] dfe_writedata_base,
+ output wire dfe_write_base, // start write to GXB
+ output wire dfe_read_base, // start read from GXB
+
+ // input from base reconfig
+ input wire [31:0] dfe_readdata_base // data from read command
+
+);
+
+//local parameters
+//state
+localparam IDLE_STATE = 4'b0000;
+localparam LOGICAL_ADDRESS_STATE = 4'b0001;
+localparam WRITE_DATA_STATE = 4'b0010;
+localparam CONTROL_STATE = 4'b0011;
+localparam BUSY_STATE = 4'b0100;
+localparam READ_PHY_ADDR_STATE = 4'b0101;
+localparam CHECK_PHY_ADDR_STATE = 4'b0110;
+localparam ADDRESS_OFFSET_STATE = 4'b0111;
+localparam BASE_BUSY_STATE = 4'b1000;
+localparam READ_DATA_STATE = 4'b1001;
+localparam WRITE_DONE_STATE = 4'b1010;
+
+localparam ILLEGAL_PHYSICAL_CHNL = 10'b1111111111;
+wire [4:0] dfe_addr_all; // 5 bit MM
+
+wire mutex_grant;
+wire [31:0] master_read_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [3:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg write_read_control;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_read;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [31:0] master_write_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [2:0] master_address;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg req_and_use_mutex;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg set_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg wait_phy_addr_ready;
+
+wire [4:0] master_address_shifted;
+
+//alt_dfe instantiation
+wire alt_dfe_busy;
+wire [15:0] alt_dfe_dprio_dataout;
+wire alt_dfe_dprio_wren;
+wire alt_dfe_dprio_rden;
+wire [(number_of_reconfig_interfaces*4-1) : 0] alt_dfe_error;
+
+wire [15:0] alt_dfe_dprio_addr;
+wire [8:0] alt_dfe_quad_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [11:0] alt_dfe_remap_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_dfe_dprio_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_dfe_dprio_busy_int;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] alt_dfe_dprio_datain;
+
+function integer CLogB2;
+input integer Depth;
+integer i;
+begin
+i = Depth;
+for(CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1)
+i = i >> 1;
+end
+endfunction
+
+// synopsys translate_off
+initial begin
+ state = 3'b000;
+ alt_dfe_remap_addr = 12'h000;
+ req_and_use_mutex = 1'b0;
+ wait_phy_addr_ready = 1'b0;
+ alt_dfe_dprio_datain = 16'h0000;
+ alt_dfe_dprio_busy = 1'b0;
+ alt_dfe_dprio_busy_int = 1'b0;
+
+ master_write = 1'b0;
+ master_read = 1'b0;
+ master_write_data = {32{1'b0}};
+ master_address = 3'h0;
+
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy = 1'b0; // 1 for assert busy, 0 for deassert busy
+
+ dfe_irq = 1'b0;
+
+end
+// synopsys translate_on
+
+integer count;
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset)
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ master_write_data <= {32{1'b0}};
+ master_address <= 3'h0;
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ req_and_use_mutex <= 1'b0;
+ wait_phy_addr_ready <= 1'b0;
+ alt_dfe_dprio_busy_int<= 1'b0;
+ dfe_irq <= 1'b0;
+ end
+ else begin
+ if(alt_dfe_busy == 1'b0)
+ req_and_use_mutex <= 1'b0;
+ else
+ req_and_use_mutex <= 1'b1;
+
+ case (state)
+ IDLE_STATE:
+ begin
+ dfe_irq <= 1'b0; // reset write/read done flag
+ //reset the signal
+ set_busy <= 1'b0;
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ alt_dfe_remap_addr <= 12'h000;
+
+ //alt_dfe will not assert wren and rden at the same time
+ if((alt_dfe_dprio_wren == 1'b1) || (alt_dfe_dprio_rden == 1'b1))
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(alt_dfe_dprio_wren == 1'b1)
+ write_read_control <= 1'b1; // 1 for write
+ else
+ write_read_control <= 1'b0; // 0 for read
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ else
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ state <= IDLE_STATE;
+ end
+ end
+ LOGICAL_ADDRESS_STATE: //sending channel and quad address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h1;
+ master_write_data <= {{21{1'b0}}, alt_dfe_quad_addr, alt_dfe_dprio_addr[13:12]};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= READ_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ end
+ READ_PHY_ADDR_STATE: //read phsical address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h2;
+ master_read <= 1'b1;
+ master_write <= 1'b0;
+ if (wait_phy_addr_ready == 1'b1)
+ begin
+ wait_phy_addr_ready <= 1'b0;
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ wait_phy_addr_ready <= 1'b1;
+ state <= READ_PHY_ADDR_STATE;
+ //state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_PHY_ADDR_STATE;
+ end
+ end
+ CHECK_PHY_ADDR_STATE: //check physical address correct or not
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ if (master_read_data[9:0] == ILLEGAL_PHYSICAL_CHNL)
+ begin
+ // synopsys translate_off
+ $display ("Illegal physical address: 10'h%h", master_read_data);
+ $display ("Time: %0t Instance: %m", $time);
+ // synopsys translate_on
+ alt_dfe_remap_addr <= 12'hfff;
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ alt_dfe_remap_addr <= master_read_data[11:0];
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ else
+ begin
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ ADDRESS_OFFSET_STATE: // send address offset to alt_dprio
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h4;
+ master_write_data <= {{20{1'b0}}, alt_dfe_dprio_addr[11:0]};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(write_read_control == 1'b1)
+ state <= WRITE_DATA_STATE;
+ else
+ state <= CONTROL_STATE;
+ end
+ else
+ begin
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ WRITE_DATA_STATE:
+ begin
+ master_address <= 3'h5;
+ master_write_data = {{16{1'b0}}, alt_dfe_dprio_dataout};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= CONTROL_STATE;
+ end
+ CONTROL_STATE: // sending write/read command
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h3; // get ready to send control command to alt_dprio
+ master_write_data <= {{29{1'b0}}, (~write_read_control), write_read_control};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ state <= BASE_BUSY_STATE;
+ end
+ else
+ begin
+ state <= CONTROL_STATE;
+ end
+ end
+ BASE_BUSY_STATE: // send busy to reconfig_togxb
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h7; // set offset cancellation busy to reconfig_togxb
+ master_write_data <= {{30{1'b0}}, alt_dfe_busy};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(set_busy == 1'b0)
+ begin
+ set_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ else
+ begin
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= BASE_BUSY_STATE;
+ end
+ end
+ BUSY_STATE: // wait for write done
+ begin
+ if(dfe_irq_from_base == 1'b1)
+ begin
+ alt_dfe_dprio_busy <= 1'b1;
+ if(write_read_control == 1'b0) //read
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_dfe_dprio_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ end
+ WRITE_DONE_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(dfe_irq_from_base == 1'b1)
+ begin
+ if(alt_dfe_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_dfe_dprio_busy_int <= master_read_data[8];
+ alt_dfe_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ else
+ begin
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ master_address <= 3'h3;
+ master_write_data <= {{16{1'b0}}, {16'h0000}}; //acknowledge write operation
+ alt_dfe_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_dfe_dprio_busy <= 1'b0;
+ dfe_irq <= 1'b1; // write done
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ READ_DATA_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(dfe_irq_from_base == 1'b1)
+ begin
+ if(alt_dfe_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_dfe_dprio_busy_int <= master_read_data[8];
+ alt_dfe_dprio_busy <= 1'b1;
+ end
+ else
+ begin
+ master_address <= 3'h5;
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ alt_dfe_dprio_busy <= 1'b1;
+ end
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ dfe_irq <= 1'b1; // read done
+ alt_dfe_dprio_datain <= master_read_data[15:0];
+ alt_dfe_dprio_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_DATA_STATE;
+ end
+ end
+ default:
+ begin
+ state <= IDLE_STATE;
+ end
+ endcase
+ end
+end
+
+alt_dfe #(
+ .channel_address_width (CLogB2(number_of_reconfig_interfaces*4)),
+ .avmm_slave_addr_width (3),
+ .avmm_slave_rdata_width ( 32),
+ .avmm_slave_wdata_width (32)
+)alt_dfe_inst(
+ .i_resetn (~reset),
+ .i_avmm_clk (reconfig_clk),
+ .i_avmm_saddress (dfe_address),
+ .i_avmm_sread (dfe_read),
+ .i_avmm_swrite (dfe_write),
+ .i_avmm_swritedata (dfe_writedata),
+//. i_avmm_sbegintransfer,
+ .o_avmm_sreaddata (dfe_readdata),
+ .o_avmm_swaitrequest (dfe_waitrequest),
+
+ .i_remap_address (alt_dfe_remap_addr),
+ .o_quad_address (alt_dfe_quad_addr),
+ .o_reconfig_busy (alt_dfe_busy),
+
+ .i_dprio_busy (alt_dfe_dprio_busy),
+ .i_dprio_in (alt_dfe_dprio_datain),
+ .o_dprio_wren (alt_dfe_dprio_wren),
+ .o_dprio_rden (alt_dfe_dprio_rden),
+ .o_dprio_addr (alt_dfe_dprio_addr),
+ .o_dprio_data (alt_dfe_dprio_dataout)
+);
+alt_mutex_acq #(
+ .mutex_wait_time(103), //analog uses 101, offset cancellation uses 102
+ .addr_width(5),
+ .data_width(32)
+)
+mutex_inst (
+ .clk(reconfig_clk),
+ .reset(reset),
+// inputs to the base that should be routed through the mutex
+ .address(master_address_shifted),
+ .writedata(master_write_data),
+ .write(master_write),
+ .read(master_read),
+// output from the mutex which is processed form of output from base
+ .waitrequest(),
+ .readdata(master_read_data),
+
+// outputs from mutex to be routed to the base
+ .master_address(dfe_addr_all),
+ .master_writedata(dfe_writedata_base),
+ .master_write(dfe_write_base),
+ .master_read(dfe_read_base),
+
+// these ports are from the base routed to the mutex
+ .master_waitrequest(dfe_waitrequest_from_base),
+ .master_readdata(dfe_readdata_base), // from MM
+
+//request signal to the mutex should be kept high as long as the mutex is being used
+ .mutex_req(req_and_use_mutex),
+// output from mutex indicates whether you have mutex or not
+ .mutex_grant(mutex_grant)
+);
+assign dfe_address_base = dfe_addr_all[ 4:2];
+//wire assignment
+assign master_address_shifted = {master_address, {2'b00}};
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_eyemon_tgx.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_eyemon_tgx.sv
new file mode 100644
index 0000000000000000000000000000000000000000..cb0a8d147058a8522ece5c1f9b7c0eb17b8ec6bc
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_eyemon_tgx.sv
@@ -0,0 +1,504 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_eyemon_tgx
+#(
+ parameter device_family = "StratixIV",
+ parameter number_of_reconfig_interfaces = 1
+)
+(
+ input wire reconfig_clk, // this will be the reconfig clk
+ input wire reset,
+
+ //avalon MM slave
+ input wire [2:0] eyemon_address, // Check this! fix me!
+ input wire [31:0] eyemon_writedata,
+ input wire eyemon_write,
+ input wire eyemon_read,
+
+ //output MM slave
+ output wire [31:0] eyemon_readdata, // from MM
+ output wire eyemon_waitrequest, // from MM
+
+ output reg eyemon_irq,
+
+ // input from base_reconfig
+ input wire eyemon_irq_from_base,
+ input wire eyemon_waitrequest_from_base,
+
+ // output to base_reconfig
+ // Avalon MM Master
+ output wire [2:0] eyemon_address_base, // 3 bit MM
+ output wire [31:0] eyemon_writedata_base,
+ output wire eyemon_write_base, // start write to GXB
+ output wire eyemon_read_base, // start read from GXB
+
+ // input from base reconfig
+ input wire [31:0] eyemon_readdata_base // data from read command
+
+);
+
+//local parameters
+//state
+localparam IDLE_STATE = 4'b0000;
+localparam LOGICAL_ADDRESS_STATE = 4'b0001;
+localparam WRITE_DATA_STATE = 4'b0010;
+localparam CONTROL_STATE = 4'b0011;
+localparam BUSY_STATE = 4'b0100;
+localparam READ_PHY_ADDR_STATE = 4'b0101;
+localparam CHECK_PHY_ADDR_STATE = 4'b0110;
+localparam ADDRESS_OFFSET_STATE = 4'b0111;
+localparam BASE_BUSY_STATE = 4'b1000;
+localparam READ_DATA_STATE = 4'b1001;
+localparam WRITE_DONE_STATE = 4'b1010;
+
+localparam ILLEGAL_PHYSICAL_CHNL = 10'b1111111111;
+
+wire [4:0] eyemon_address_all; // 5 bit MM
+wire mutex_grant;
+wire [31:0] master_read_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [3:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg write_read_control;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_read;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [31:0] master_write_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [2:0] master_address;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg req_and_use_mutex;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg set_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg wait_phy_addr_ready;
+
+wire [4:0] master_address_shifted;
+
+//alt_eyemon instantiation
+wire alt_eyemon_busy;
+wire [15:0] alt_eyemon_dprio_dataout;
+wire alt_eyemon_dprio_wren;
+wire alt_eyemon_dprio_rden;
+wire [(number_of_reconfig_interfaces*4-1) : 0] alt_eyemon_error;
+
+wire [15:0] alt_eyemon_dprio_addr;
+wire [8:0] alt_eyemon_quad_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [11:0] alt_eyemon_remap_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_eyemon_dprio_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_eyemon_dprio_busy_int;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] alt_eyemon_dprio_datain;
+
+function integer CLogB2;
+input integer Depth;
+integer i;
+begin
+i = Depth;
+for(CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1)
+i = i >> 1;
+end
+endfunction
+
+// synopsys translate_off
+initial begin
+ state = 3'b000;
+ alt_eyemon_remap_addr = 12'h000;
+ req_and_use_mutex = 1'b0;
+ wait_phy_addr_ready = 1'b0;
+ alt_eyemon_dprio_datain = 16'h0000;
+ alt_eyemon_dprio_busy = 1'b0;
+ alt_eyemon_dprio_busy_int = 1'b0;
+
+ master_write = 1'b0;
+ master_read = 1'b0;
+ master_write_data = {32{1'b0}};
+ master_address = 3'h0;
+
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy = 1'b0; // 1 for assert busy, 0 for deassert busy
+
+ eyemon_irq = 1'b0;
+
+end
+// synopsys translate_on
+
+integer count;
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset)
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ master_write_data <= {32{1'b0}};
+ master_address <= 3'h0;
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ req_and_use_mutex <= 1'b0;
+ wait_phy_addr_ready <= 1'b0;
+ alt_eyemon_dprio_busy_int<= 1'b0;
+ eyemon_irq <= 1'b0;
+ end
+ else begin
+ if(alt_eyemon_busy == 1'b0)
+ req_and_use_mutex <= 1'b0;
+ else
+ req_and_use_mutex <= 1'b1;
+
+ case (state)
+ IDLE_STATE:
+ begin
+ eyemon_irq <= 1'b0; // reset write/read done flag
+ //reset the signal
+ set_busy <= 1'b0;
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ alt_eyemon_remap_addr <= 12'h000;
+
+ //alt_eyemon will not assert wren and rden at the same time
+ if((alt_eyemon_dprio_wren == 1'b1) || (alt_eyemon_dprio_rden == 1'b1))
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(alt_eyemon_dprio_wren == 1'b1)
+ write_read_control <= 1'b1; // 1 for write
+ else
+ write_read_control <= 1'b0; // 0 for read
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ else
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ state <= IDLE_STATE;
+ end
+ end
+ LOGICAL_ADDRESS_STATE: //sending channel and quad address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h1;
+ master_write_data <= {{21{1'b0}}, alt_eyemon_quad_addr, alt_eyemon_dprio_addr[13:12]};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= READ_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ end
+ READ_PHY_ADDR_STATE: //read phsical address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h2;
+ master_read <= 1'b1;
+ master_write <= 1'b0;
+ if (wait_phy_addr_ready == 1'b1)
+ begin
+ wait_phy_addr_ready <= 1'b0;
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ wait_phy_addr_ready <= 1'b1;
+ state <= READ_PHY_ADDR_STATE;
+ //state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_PHY_ADDR_STATE;
+ end
+ end
+ CHECK_PHY_ADDR_STATE: //check physical address correct or not
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ if (master_read_data[9:0] == ILLEGAL_PHYSICAL_CHNL)
+ begin
+ // synopsys translate_off
+ $display ("Illegal physical address: 10'h%h", master_read_data);
+ $display ("Time: %0t Instance: %m", $time);
+ // synopsys translate_on
+ alt_eyemon_remap_addr <= 12'hfff;
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ alt_eyemon_remap_addr <= master_read_data[11:0];
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ else
+ begin
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ ADDRESS_OFFSET_STATE: // send address offset to alt_dprio
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h4;
+ master_write_data <= {{20{1'b0}}, alt_eyemon_dprio_addr[11:0]};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(write_read_control == 1'b1)
+ state <= WRITE_DATA_STATE;
+ else
+ state <= CONTROL_STATE;
+ end
+ else
+ begin
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ WRITE_DATA_STATE:
+ begin
+ master_address <= 3'h5;
+ master_write_data = {{16{1'b0}}, alt_eyemon_dprio_dataout};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= CONTROL_STATE;
+ end
+ CONTROL_STATE: // sending write/read command
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h3; // get ready to send control command to alt_dprio
+ master_write_data <= {{29{1'b0}}, (~write_read_control), write_read_control};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ state <= BASE_BUSY_STATE;
+ end
+ else
+ begin
+ state <= CONTROL_STATE;
+ end
+ end
+ BASE_BUSY_STATE: // send busy to reconfig_togxb
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h7; // set offset cancellation busy to reconfig_togxb
+ master_write_data <= {{30{1'b0}}, alt_eyemon_busy};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(set_busy == 1'b0)
+ begin
+ set_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ else
+ begin
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= BASE_BUSY_STATE;
+ end
+ end
+ BUSY_STATE: // wait for write done
+ begin
+ if(eyemon_irq_from_base == 1'b1)
+ begin
+ alt_eyemon_dprio_busy <= 1'b1;
+ if(write_read_control == 1'b0) //read
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_eyemon_dprio_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ end
+ WRITE_DONE_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(eyemon_irq_from_base == 1'b1)
+ begin
+ if(alt_eyemon_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_eyemon_dprio_busy_int <= master_read_data[8];
+ alt_eyemon_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ else
+ begin
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ master_address <= 3'h3;
+ master_write_data <= {{16{1'b0}}, {16'h0000}}; //acknowledge write operation
+ alt_eyemon_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_eyemon_dprio_busy <= 1'b0;
+ eyemon_irq <= 1'b1; // write done
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ READ_DATA_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(eyemon_irq_from_base == 1'b1)
+ begin
+ if(alt_eyemon_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_eyemon_dprio_busy_int <= master_read_data[8];
+ alt_eyemon_dprio_busy <= 1'b1;
+ end
+ else
+ begin
+ master_address <= 3'h5;
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ alt_eyemon_dprio_busy <= 1'b1;
+ end
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ eyemon_irq <= 1'b1; // read done
+ alt_eyemon_dprio_datain <= master_read_data[15:0];
+ alt_eyemon_dprio_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_DATA_STATE;
+ end
+ end
+ default:
+ begin
+ state <= IDLE_STATE;
+ end
+ endcase
+ end
+end
+
+alt_eyemon #(
+ .channel_address_width (CLogB2(number_of_reconfig_interfaces*4)),
+ .avmm_slave_addr_width (3),
+ .avmm_slave_rdata_width ( 32),
+ .avmm_slave_wdata_width (32)
+)alt_eyemon_inst(
+ .i_resetn (~reset),
+ .i_avmm_clk (reconfig_clk),
+ .i_avmm_saddress (eyemon_address),
+ .i_avmm_sread (eyemon_read),
+ .i_avmm_swrite (eyemon_write),
+ .i_avmm_swritedata (eyemon_writedata),
+//. i_avmm_sbegintransfer,
+ .o_avmm_sreaddata (eyemon_readdata),
+ .o_avmm_swaitrequest (eyemon_waitrequest),
+
+ .i_remap_phase (1'b1), // need to figure out best way to control this - for now, always remap - fix me!
+ .i_remap_address (alt_eyemon_remap_addr),
+ .o_quad_address (alt_eyemon_quad_addr),
+ .o_reconfig_busy (alt_eyemon_busy),
+
+ .i_dprio_busy (alt_eyemon_dprio_busy),
+ .i_dprio_in (alt_eyemon_dprio_datain),
+ .o_dprio_wren (alt_eyemon_dprio_wren),
+ .o_dprio_rden (alt_eyemon_dprio_rden),
+ .o_dprio_addr (alt_eyemon_dprio_addr),
+ .o_dprio_data (alt_eyemon_dprio_dataout)
+);
+alt_mutex_acq #(
+ .mutex_wait_time(103), //analog uses 101, offset cancellation uses 102
+ .addr_width(5),
+ .data_width(32)
+)
+mutex_inst (
+ .clk(reconfig_clk),
+ .reset(reset),
+// inputs to the base that should be routed through the mutex
+ .address(master_address_shifted),
+ .writedata(master_write_data),
+ .write(master_write),
+ .read(master_read),
+// output from the mutex which is processed form of output from base
+ .waitrequest(),
+ .readdata(master_read_data),
+
+// outputs from mutex to be routed to the base
+ .master_address({eyemon_address_all}),
+ .master_writedata(eyemon_writedata_base),
+ .master_write(eyemon_write_base),
+ .master_read(eyemon_read_base),
+
+// these ports are from the base routed to the mutex
+ .master_waitrequest(eyemon_waitrequest_from_base),
+ .master_readdata(eyemon_readdata_base), // from MM
+
+//request signal to the mutex should be kept high as long as the mutex is being used
+ .mutex_req(req_and_use_mutex),
+// output from mutex indicates whether you have mutex or not
+ .mutex_grant(mutex_grant)
+);
+
+//wire assignment
+assign eyemon_address_base = eyemon_address_all[4:2];
+assign master_address_shifted = {master_address, {2'b00}};
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..102856f4162133620df696f7e6ccb75bc2dca7f4
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_h.sv
@@ -0,0 +1,266 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Top-level definitions for transceiver reconfig IP
+//
+// $Header$
+//
+// PACKAGE DECLARATION
+package alt_xcvr_reconfig_h;
+
+ ////////////////////////////////////////////////////////
+ // Top-level register map for transceiver reconfig IP
+ ////////////////////////////////////////////////////////
+ localparam W_XR_ADDR = 7; // address width on mgmt interface
+ localparam W_XR_FEATURE_LADDR = 3; // address width of standard feature block, and basic logical interface
+ typedef bit [W_XR_ADDR -1:0] t_xreconf_addr;
+ typedef bit [W_XR_FEATURE_LADDR-1:0] t_xr_feature_addr;
+
+ // Feature block indices (used for address decoding for each block)
+ localparam INDEX_XR_OFFSET = 0;
+ localparam INDEX_XR_ANALOG = 1;
+ localparam INDEX_XR_EYEMON = 2;
+ localparam INDEX_XR_DFE = 3;
+ localparam INDEX_XR_DIRECT = 4;
+ localparam INDEX_XR_ADCE = 5;
+ localparam INDEX_XR_LC = 6;
+ localparam INDEX_XR_MIF = 7;
+ localparam INDEX_XR_PLL = 8;
+ localparam INDEX_XR_DCD = 9;
+ localparam INDEX_XR_END = 10; // must always mark end of address space
+
+ // Each feature block is allocated an 8-word address range
+ localparam [W_XR_ADDR-1:0] ADDR_XR_OFFSET_BASE = t_xreconf_addr'(INDEX_XR_OFFSET << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_BASE = t_xreconf_addr'(INDEX_XR_ANALOG << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_BASE = t_xreconf_addr'(INDEX_XR_EYEMON << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_BASE = t_xreconf_addr'(INDEX_XR_DFE << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_BASE = t_xreconf_addr'(INDEX_XR_DIRECT << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_BASE = t_xreconf_addr'(INDEX_XR_ADCE << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_LC_BASE = t_xreconf_addr'(INDEX_XR_LC << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_BASE = t_xreconf_addr'(INDEX_XR_MIF << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_BASE = t_xreconf_addr'(INDEX_XR_PLL << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_BASE = t_xreconf_addr'(INDEX_XR_DCD << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_END_BASE = t_xreconf_addr'(INDEX_XR_END << W_XR_FEATURE_LADDR); // must always mark end of address space
+
+ localparam [W_XR_FEATURE_LADDR-1:0] XR_STATUS_OFST = t_xr_feature_addr'(2);
+ localparam XR_STATUS_OFST_COMB_BUSY = 8;
+
+ ////////////////////////////////////////////////////////
+ // Offset Cancellation block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_OFFSET_STATUS = t_xreconf_addr'(ADDR_XR_OFFSET_BASE + 2);
+
+
+ ////////////////////////////////////////////////////////
+ // Analog block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_LCH = t_xreconf_addr'(ADDR_XR_ANALOG_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_PCH = t_xreconf_addr'(ADDR_XR_ANALOG_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_STATUS = t_xreconf_addr'(ADDR_XR_ANALOG_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_OFFSET = t_xreconf_addr'(ADDR_XR_ANALOG_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_DATA = t_xreconf_addr'(ADDR_XR_ANALOG_BASE + 4);
+
+ // Analog internal register offsets
+ // These are to be written to the analog offset address register, ADDR_XR_ANALOG_OFFSET
+ localparam XR_ANALOG_OFFSET_VOD = 0;
+ localparam XR_ANALOG_OFFSET_PREEMPH0T = 1;
+ localparam XR_ANALOG_OFFSET_PREEMPH1T = 2;
+ localparam XR_ANALOG_OFFSET_PREEMPH2T = 3;
+ localparam XR_ANALOG_OFFSET_RXDCGAIN = 16;
+ localparam XR_ANALOG_OFFSET_RXEQCTRL = 17;
+ localparam XR_ANALOG_OFFSET_PRECDRLPBK = 32;
+ localparam XR_ANALOG_OFFSET_POSTCDRLPBK = 33;
+
+ ////////////////////////////////////////////////////////
+ // DFE block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_LCH = t_xreconf_addr'(ADDR_XR_DFE_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_PCH = t_xreconf_addr'(ADDR_XR_DFE_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_STATUS = t_xreconf_addr'(ADDR_XR_DFE_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_OFFSET = t_xreconf_addr'(ADDR_XR_DFE_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_DATA = t_xreconf_addr'(ADDR_XR_DFE_BASE + 4);
+
+ // DFE internal register offsets
+ // These are to be written to the DFE offset address register, ADDR_XR_DFE_OFFSET
+ localparam XR_DFE_OFFSET_CTRL = 0;
+ localparam XR_DFE_OFFSET_TAP1 = 1;
+ localparam XR_DFE_OFFSET_TAP2 = 2;
+ localparam XR_DFE_OFFSET_TAP3 = 3;
+ localparam XR_DFE_OFFSET_TAP4 = 4;
+ localparam XR_DFE_OFFSET_TAP5 = 5;
+ localparam XR_DFE_OFFSET_REF = 6;
+ localparam XR_DFE_OFFSET_STEP = 7;
+ localparam XR_DFE_OFFSET_DFE12 = 18;
+ localparam XR_DFE_OFFSET_DFE13 = 19;
+ localparam XR_DFE_OFFSET_DFE14 = 20;
+ localparam XR_DFE_OFFSET_DFE15 = 21;
+ localparam XR_DFE_OFFSET_CAL_PLL = 22;
+ localparam XR_DFE_OFFSET_CAL_TBUS = 23;
+ localparam XR_DFE_OFFSET_CAL_SAMPL = 24;
+ ////////////////////////////////////////////////////////
+ // Eyemon block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_LCH = t_xreconf_addr'(ADDR_XR_EYEMON_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_PCH = t_xreconf_addr'(ADDR_XR_EYEMON_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_STATUS = t_xreconf_addr'(ADDR_XR_EYEMON_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_OFFSET = t_xreconf_addr'(ADDR_XR_EYEMON_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_DATA = t_xreconf_addr'(ADDR_XR_EYEMON_BASE + 4);
+
+ // EYEMON internal register offsets
+ // These are to be written to the EYEMON offset address register, ADDR_XR_EYEMON_OFFSET
+ localparam XR_EYEMON_OFFSET_CTRL = 0;
+ localparam XR_EYEMON_OFFSET_HPHASE = 1;
+ localparam XR_EYEMON_OFFSET_VHEIGHT = 2;
+ localparam XR_EYEMON_OFFSET_EYEMON16 = 3;
+ localparam XR_EYEMON_OFFSET_EYEMON17 = 4;
+
+ ////////////////////////////////////////////////////////
+ // ADCE block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_LCH = t_xreconf_addr'(ADDR_XR_ADCE_BASE + 0); // Logical channel number
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_PCH = t_xreconf_addr'(ADDR_XR_ADCE_BASE + 1); // Physical channel number
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_STATUS = t_xreconf_addr'(ADDR_XR_ADCE_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_OFFSET = t_xreconf_addr'(ADDR_XR_ADCE_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_DATA = t_xreconf_addr'(ADDR_XR_ADCE_BASE + 4);
+
+ // ADCE internal register offsets
+ // These are to be written to the ADCE offset address register, ADDR_XR_ADCE_OFFSET
+ localparam XR_ADCE_OFFSET_CTRL = 0;
+ localparam XR_ADCE_OFFSET_RESULTS = 1; // Manual setting equivalent to ADCE results
+ localparam XR_ADCE_OFFSET_RADCE_ATT_0 = 9; // radce_att[15: 0]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_1 = 10; // radce_att[31:15]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_2 = 11; // radce_att[47:32]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_3 = 12; // radce_att[63:48]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_4 = 13; // radce_att[79:64]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_5 = 14; // radce_att[95:80]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_6 = 15; // radce_att[111:96]
+
+ ////////////////////////////////////////////////////////
+ // DCD block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_LCH = t_xreconf_addr'(ADDR_XR_DCD_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_PCH = t_xreconf_addr'(ADDR_XR_DCD_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_STATUS = t_xreconf_addr'(ADDR_XR_DCD_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_OFFSET = t_xreconf_addr'(ADDR_XR_DCD_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_DATA = t_xreconf_addr'(ADDR_XR_DCD_BASE + 4);
+
+ // DCD internal register offsets
+ // These are to be written to the DFE offset address register, ADDR_XR_DCD_OFFSET
+ localparam XR_DCD_OFFSET_CTRL = 0;
+
+ ////////////////////////////////////////////////////////
+ // MIF block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_LCH = t_xreconf_addr'(ADDR_XR_MIF_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_PCH = t_xreconf_addr'(ADDR_XR_MIF_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_STATUS = t_xreconf_addr'(ADDR_XR_MIF_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_OFFSET = t_xreconf_addr'(ADDR_XR_MIF_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_DATA = t_xreconf_addr'(ADDR_XR_MIF_BASE + 4);
+
+ ////////////////////////////////////////////////////////
+ // PLL block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_LCH = t_xreconf_addr'(ADDR_XR_PLL_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_PCH = t_xreconf_addr'(ADDR_XR_PLL_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_STATUS = t_xreconf_addr'(ADDR_XR_PLL_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_OFFSET = t_xreconf_addr'(ADDR_XR_PLL_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_DATA = t_xreconf_addr'(ADDR_XR_PLL_BASE + 4);
+
+
+
+
+ ////////////////////////////////////////////////////////
+ // Basic block addresses (internal, private addresses)
+ ////////////////////////////////////////////////////////
+ // The 'basic' interface block is the switch that routes requests to
+ // an appropriate physical reconfiguration interface. A logical channel
+ // number acts as a channel ID, which allows the basic block to find
+ // the corresponding physical reconfiguration interface, and a physical
+ // channel index within a physical interface.
+ //
+ // The Basic (B) block features are also available via the direct access block.
+ // All users of the basic block, including the direct access block, must
+ // acquire appropriate semaphores before using an interface, and release
+ // the semaphores when done, to avoid locking out other feature blocks.
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_MUTEX = t_xr_feature_addr'(0);
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_LOGICAL_CHANNEL = t_xr_feature_addr'(1);
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_PHYSICAL_CHANNEL = t_xr_feature_addr'(2);
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_CONTROL = t_xr_feature_addr'(3);
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_OFFSET_ADDR = t_xr_feature_addr'(4);
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_DATA = t_xr_feature_addr'(5);
+
+
+ ////////////////////////////////////////////////////////
+ // Direct Access & Basic block addresses
+ ////////////////////////////////////////////////////////
+ //
+ // The minimum steps to read & write a reconfiguration word are the following:
+ // Step 1 - acquire basic arbiter lock (write 1 to ADDR_XR_DIRECT_ARB_ACQ)
+ // Step 2 - write logical channel number to ADDR_XR_DIRECT_LCH
+ // Step 3 - acquire channel lock
+ // 3a - request channel lock (write XR_DIRECT_CONTROL_PHYS_LOCK_SET to ADDR_XR_DIRECT_CONTROL)
+ // 3b - confirm channel lock (read ADDR_XR_DIRECT_CONTROL, mask with XR_DIRECT_STATUS_BITMASK_PHYS_LOCK_GRANTED)
+ // -- repeat step 3b until result after applying mask is != 0
+ // Step 4 - write channel offset address to ADDR_XR_DIRECT_OFFSET
+ // Step 5 - read existing value from reconfig space, modify, then write back
+ // 5a (read cycle part 1) - write XR_DIRECT_CONTROL_RECONF_READ to ADDR_XR_DIRECT_CONTROL
+ // 5b (read cycle part 2) - read data from ADDR_XR_DIRECT_DATA
+ // 5c (write cycle part 1) - write modified value to ADDR_XR_DIRECT_DATA
+ // 5d (write cycle part 2) - write XR_DIRECT_CONTROL_RECONF_WRITE to ADDR_XR_DIRECT_CONTROL
+ // -- addtional read-modify-write cycles, repeat from step 2 or 4 (can skip step 3a)
+ // Step 6 - release channel lock (write XR_DIRECT_CONTROL_PHYS_LOCK_CLEAR to ADDR_XR_DIRECT_CONTROL)
+ // Step 7 - release basic arbiter lock (write 0 to ADDR_XR_DIRECT_ARB_ACQ)
+ //
+ // Direct/Basic register bitmap ---------------------------------------------------------
+ // word addr wr/rd description
+ // ------------------------------------------------------
+ // 0 wr basic arbiter, 1 to request access, 0 to release lock
+ // 1 wr/rd logical channel number
+ // 2 rd physical channel number. When lower 3 bits are 3'b111, means ch is not present
+ // 3 wr/rd status/control -- see XR_DIRECT_CONTROL_* opcodes and XR_DIRECT_STATUS_* bitfield definitions
+ // 4 wr/rd offset_addr -- for opcode-based reads & writes
+ // 5 wr/rd data -- for opcode-based reads & writes
+ // 6 -- reserved
+ // 7 -- reserved
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_ARB_ACQ = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + 0); // write 1 to request B access, 0 to release
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_LCH = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + ADDR_XCVR_RECONFIG_BASIC_LOGICAL_CHANNEL);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_PCH = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + ADDR_XCVR_RECONFIG_BASIC_PHYSICAL_CHANNEL);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_CONTROL = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + ADDR_XCVR_RECONFIG_BASIC_CONTROL);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_OFFSET = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + ADDR_XCVR_RECONFIG_BASIC_OFFSET_ADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_DATA = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + ADDR_XCVR_RECONFIG_BASIC_DATA);
+
+ // Opcode values for writes to control word, ADDR_XR_DIRECT_CONTROL
+ localparam XR_DIRECT_CONTROL_RECONF_WRITE = 32'b0000; // reconfig space: write current DATA to OFFSET addr (as physical addr or ch offset addr)
+ localparam XR_DIRECT_CONTROL_RECONF_READ = 32'b0001; // reconfig space: read from OFFSET_ADDR, save result in DATA
+ localparam XR_DIRECT_CONTROL_LADDR_SET = 32'b0010; // interpret OFFSET_ADDR as logical addr, with automatic ch addr offset
+ localparam XR_DIRECT_CONTROL_PADDR_SET = 32'b0011; // interpret OFFSET_ADDR as physical addr, with no automatic addr offset
+ localparam XR_DIRECT_CONTROL_PHYS_LOCK_CLEAR = 32'b0100; // clear lock request for current channel
+ localparam XR_DIRECT_CONTROL_PHYS_LOCK_SET = 32'b0101; // set lock request for current channel
+ localparam XR_DIRECT_CONTROL_ADDR_AUTO_INCR_CLEAR = 32'b0110; // clear auto-write-and-address-increment mode for data writes
+ localparam XR_DIRECT_CONTROL_ADDR_AUTO_INCR_SET = 32'b0111; // set auto-write-and-address-increment mode for data writes
+ localparam XR_DIRECT_CONTROL_INTERNAL_WRITE = 32'b1000; // Internal registers, mainly testbus control
+ //localparam XR_DIRECT_CONTROL_INTERNAL_READ = 32'b1001; // internal reg space: read from OFFSET_ADDR, save result in DATA
+ localparam XR_DIRECT_CONTROL_TABLE_READ = 32'b1011; // ROM table lookup, especially for PLL and clock mux remapping
+
+ // Read of control/status reg returns this bitfield data
+ localparam XR_DIRECT_STATUS_BITMASK_PHYS_LOCK_GRANTED = 32'b0001; // on read, bit 0 is grant status
+ localparam XR_DIRECT_STATUS_BITMASK_PHYS_LOCK_REQUESTED = 32'b0010; // on read, bit 1 is physical lock request flag
+ localparam XR_DIRECT_STATUS_BITMASK_USING_PHYS_ADDR = 32'b0100; // on read, bit 2 is physical addr mode indicator (0 mean logical addr)
+ localparam XR_DIRECT_STATUS_BITMASK_USING_ADDR_AUTO_INCR = 32'b1000; // on read, bit 3 is auto-write-and-addr-incr mode indicator
+
+ // Internal register addresses, for read/write via these opcodes: XR_DIRECT_CONTROL_INTERNAL_*
+ localparam XR_DIRECT_OFFSET_TESTBUS_SEL = 2'd0; // internal register for testbus sel
+
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_offset_cancellation.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_offset_cancellation.sv
new file mode 100644
index 0000000000000000000000000000000000000000..0dd5517bb661acbd542861fa584fe89ae3aa336c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_offset_cancellation.sv
@@ -0,0 +1,174 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_offset_cancellation
+#(
+ parameter device_family = "StratixV",
+ parameter number_of_reconfig_interfaces = 1
+)
+(
+ input wire reconfig_clk, // this will be the reconfig clk
+ input wire reset,
+
+ //avalon MM slave
+ input wire [2:0] offset_cancellation_address, // MM address
+ input wire [31:0] offset_cancellation_writedata,
+ input wire offset_cancellation_write,
+ input wire offset_cancellation_read,
+
+ //output MM slave
+ output wire [31:0] offset_cancellation_readdata, // from MM
+
+ output wire offset_cancellation_done,
+
+ // input from base_reconfig
+ input wire offset_cancellation_irq_from_base,
+ input wire offset_cancellation_waitrequest_from_base,
+ output wire offset_cancellation_waitrequest,
+
+ // output to base_reconfig
+ // Avalon MM Master
+ output wire [2:0] offset_cancellation_address_base, // 3 bit MM
+ output wire [31:0] offset_cancellation_writedata_base,
+ output wire offset_cancellation_write_base, // start write to GXB
+ output wire offset_cancellation_read_base, // start read from GXB
+
+ // input from base reconfig
+ input wire [31:0] offset_cancellation_readdata_base, // data from read command
+
+ // Avalon ST
+ input wire [number_of_reconfig_interfaces*16 - 1 : 0] testbus_data,
+
+ // external connect to switch fabric: request basic access from arbiter
+ output wire arb_req,
+ input wire arb_grant
+
+);
+
+import altera_xcvr_functions::*;
+localparam is_s4 = has_s4_style_hssi(device_family);
+localparam is_s5 = has_s5_style_hssi(device_family);
+localparam is_a5 = has_a5_style_hssi(device_family);
+
+
+generate
+ //Deepak - Namespace support for AII GX and CIVGX
+ if(is_s4)
+ begin
+ wire [4:0] w_tgx_offset_cancellation_address_base;
+ alt_xcvr_reconfig_offset_cancellation_tgx
+ #(
+ .device_family(device_family),
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces)
+ ) offset_cancellation_tgx
+ (
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .offset_cancellation_address(offset_cancellation_address),
+ .offset_cancellation_writedata(offset_cancellation_writedata),
+ .offset_cancellation_write(offset_cancellation_write),
+ .offset_cancellation_read(offset_cancellation_read),
+ .offset_cancellation_readdata(offset_cancellation_readdata),
+ .offset_cancellation_done(offset_cancellation_done),
+ .offset_cancellation_irq_from_base(offset_cancellation_irq_from_base),
+ .offset_cancellation_waitrequest_from_base(offset_cancellation_waitrequest_from_base),
+ .offset_cancellation_waitrequest(offset_cancellation_waitrequest),
+ .offset_cancellation_address_base(w_tgx_offset_cancellation_address_base),
+ .offset_cancellation_writedata_base(offset_cancellation_writedata_base),
+ .offset_cancellation_write_base(offset_cancellation_write_base),
+ .offset_cancellation_read_base(offset_cancellation_read_base),
+ .offset_cancellation_readdata_base(offset_cancellation_readdata_base),
+ .testbus_data(testbus_data)
+ );
+ assign offset_cancellation_address_base = w_tgx_offset_cancellation_address_base[4:2];
+ assign arb_req = 1'b0 & arb_grant; // not currently used in S4 architecture
+ end
+ else if (is_s5)
+ begin
+ alt_xcvr_reconfig_offset_cancellation_sv
+ #(
+ .device_family(device_family),
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces)
+ ) offset_cancellation_sv
+ (
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .offset_cancellation_address(offset_cancellation_address),
+ .offset_cancellation_writedata(offset_cancellation_writedata),
+ .offset_cancellation_write(offset_cancellation_write),
+ .offset_cancellation_read(offset_cancellation_read),
+ .offset_cancellation_readdata(offset_cancellation_readdata),
+ .offset_cancellation_done(offset_cancellation_done),
+ .offset_cancellation_irq_from_base(offset_cancellation_irq_from_base),
+ .offset_cancellation_waitrequest_from_base(offset_cancellation_waitrequest_from_base),
+ .offset_cancellation_waitrequest(offset_cancellation_waitrequest),
+ .offset_cancellation_address_base(offset_cancellation_address_base),
+ .offset_cancellation_writedata_base(offset_cancellation_writedata_base),
+ .offset_cancellation_write_base(offset_cancellation_write_base),
+ .offset_cancellation_read_base(offset_cancellation_read_base),
+ .offset_cancellation_readdata_base(offset_cancellation_readdata_base),
+ .testbus_data(testbus_data[7:0]), // testbus data is now provided on a per-channel basis from the 'B' - only need the lower 8 bits
+ .arb_req(arb_req),
+ .arb_grant(arb_grant)
+ );
+ end
+ else if (is_a5)
+ begin
+ alt_xcvr_reconfig_offset_cancellation_av
+ #(
+ .device_family(device_family),
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces)
+ ) offset_cancellation_av
+ (
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .offset_cancellation_address(offset_cancellation_address),
+ .offset_cancellation_writedata(offset_cancellation_writedata),
+ .offset_cancellation_write(offset_cancellation_write),
+ .offset_cancellation_read(offset_cancellation_read),
+ .offset_cancellation_readdata(offset_cancellation_readdata),
+ .offset_cancellation_done(offset_cancellation_done),
+ .offset_cancellation_irq_from_base(offset_cancellation_irq_from_base),
+ .offset_cancellation_waitrequest_from_base(offset_cancellation_waitrequest_from_base),
+ .offset_cancellation_waitrequest(offset_cancellation_waitrequest),
+ .offset_cancellation_address_base(offset_cancellation_address_base),
+ .offset_cancellation_writedata_base(offset_cancellation_writedata_base),
+ .offset_cancellation_write_base(offset_cancellation_write_base),
+ .offset_cancellation_read_base(offset_cancellation_read_base),
+ .offset_cancellation_readdata_base(offset_cancellation_readdata_base),
+ .testbus_data(testbus_data[7:0]), // testbus data is now provided on a per-channel basis from the 'B' - only need the lower 8 bits
+ .arb_req(arb_req),
+ .arb_grant(arb_grant)
+ );
+ end
+ else
+ begin
+ assign offset_cancellation_readdata = 32'd0;
+ assign offset_cancellation_done = 1'd0;
+ assign offset_cancellation_waitrequest = 1'd0;
+ assign offset_cancellation_address_base = 3'd0;
+ assign offset_cancellation_writedata_base = 32'd0;
+ assign offset_cancellation_write_base = 1'd0;
+ assign offset_cancellation_read_base = 1'd0;
+ assign arb_req = 1'd0;
+ end
+
+
+
+endgenerate
+
+endmodule
+
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_offset_cancellation_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_offset_cancellation_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..01ee1edc16393c8b5f525ce12734b754321f57b7
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_offset_cancellation_tgx.v
@@ -0,0 +1,581 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_offset_cancellation_tgx
+#(
+ parameter device_family = "StratixIV",
+ parameter number_of_reconfig_interfaces = 1
+)
+(
+ input wire reconfig_clk, // this will be the reconfig clk
+ input wire reset,
+
+ //avalon MM slave
+ input wire offset_cancellation_address, // MM address
+ input wire [31:0] offset_cancellation_writedata,
+ input wire offset_cancellation_write,
+ input wire offset_cancellation_read,
+
+ //output MM slave
+ output reg [31:0] offset_cancellation_readdata, // from MM
+
+ output reg offset_cancellation_done,
+
+ // input from base_reconfig
+ input wire offset_cancellation_irq_from_base,
+ input wire offset_cancellation_waitrequest_from_base,
+
+ output wire offset_cancellation_waitrequest,
+
+ // output to base_reconfig
+ // Avalon MM Master
+ output wire [4:0] offset_cancellation_address_base, // 3 bit MM
+ output wire [31:0] offset_cancellation_writedata_base,
+ output wire offset_cancellation_write_base, // start write to GXB
+ output wire offset_cancellation_read_base, // start read from GXB
+
+ // input from base reconfig
+ input wire [31:0] offset_cancellation_readdata_base, // data from read command
+
+ // Avalon ST
+ input wire [number_of_reconfig_interfaces*16 - 1 : 0] testbus_data
+);
+
+///////////////////////////////////////////////////////////////////
+// Memory map | wr/rd | Description
+//----------------------------------------------------------------
+// 0 | wr/rd | [31:10] Reserved
+// | | [9] Error
+// | | [8] Busy
+// | | [7:1] Reserved
+// | | [0] Start (hidden for QII 9.1)
+///////////////////////////////////////////////////////////////////
+
+//local parameters
+//state
+localparam IDLE_STATE = 4'b0000;
+localparam LOGICAL_ADDRESS_STATE = 4'b0001;
+localparam WRITE_DATA_STATE = 4'b0010;
+localparam CONTROL_STATE = 4'b0011;
+localparam BUSY_STATE = 4'b0100;
+localparam READ_PHY_ADDR_STATE = 4'b0101;
+localparam CHECK_PHY_ADDR_STATE = 4'b0110;
+localparam ADDRESS_OFFSET_STATE = 4'b0111;
+localparam BASE_BUSY_STATE = 4'b1000;
+localparam READ_DATA_STATE = 4'b1001;
+localparam WRITE_DONE_STATE = 4'b1010;
+
+localparam ILLEGAL_PHYSICAL_CHNL = 10'b1111111111;
+
+wire mutex_grant;
+wire [31:0] master_read_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [3:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg write_read_control;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_read;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [31:0] master_write_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [2:0] master_address;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg req_and_use_mutex;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg set_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_cal_error_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg wait_phy_addr_ready;
+
+wire [4:0] master_address_shifted;
+
+//alt_cal instantiation
+wire alt_cal_busy;
+wire [15:0] alt_cal_dprio_dataout;
+wire alt_cal_dprio_wren;
+wire alt_cal_dprio_rden;
+wire alt_cal_retain_addr;
+wire [(number_of_reconfig_interfaces*4-1) : 0] alt_cal_error;
+
+wire [number_of_reconfig_interfaces*16 - 1 : 0] alt_cal_testbuses;
+wire [15:0] alt_cal_dprio_addr;
+wire [8:0] alt_cal_quad_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [11:0] alt_cal_remap_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_cal_dprio_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_cal_dprio_busy_int;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] alt_cal_dprio_datain;
+
+function integer CLogB2;
+input integer Depth;
+integer i;
+begin
+i = Depth;
+for(CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1)
+i = i >> 1;
+end
+endfunction
+
+// Implement waitrequest to match previous implementation
+altera_wait_generate wait_gen(
+ .rst(reset),
+ .clk(reconfig_clk),
+ .launch_signal(offset_cancellation_read),
+ .wait_req(offset_cancellation_waitrequest)
+);
+
+// synopsys translate_off
+initial begin
+ state = 3'b000;
+ alt_cal_remap_addr = 12'h000;
+ req_and_use_mutex = 1'b0;
+ wait_phy_addr_ready = 1'b0;
+ // alt_cal_testbuses = 0;
+ alt_cal_dprio_datain = 16'h0000;
+ alt_cal_dprio_busy = 1'b0;
+ alt_cal_dprio_busy_int = 1'b0;
+
+ master_write = 1'b0;
+ master_read = 1'b0;
+ master_write_data = {32{1'b0}};
+ master_address = 3'h0;
+
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy = 1'b0; // 1 for assert busy, 0 for deassert busy
+
+ alt_cal_error_reg = 1'b0;
+ offset_cancellation_done = 1'b0;
+
+end
+// synopsys translate_on
+
+integer count;
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset)
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ master_write_data <= {32{1'b0}};
+ master_address <= 3'h0;
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ offset_cancellation_readdata[31:0] <= {32{1'b0}};
+ alt_cal_error_reg <= 1'b0;
+ req_and_use_mutex <= 1'b0;
+ wait_phy_addr_ready <= 1'b0;
+ alt_cal_dprio_busy_int<= 1'b0;
+ offset_cancellation_done <= 1'b0;
+ end
+ else begin
+ if(offset_cancellation_read == 1'b1)
+ begin
+ if(offset_cancellation_address == 1'b0)
+ begin
+ offset_cancellation_readdata <= {{22{1'b0}}, alt_cal_error_reg, alt_cal_busy , {8{1'b0}}};
+ end
+ end
+
+ for(count=0; count < (number_of_reconfig_interfaces*4); count=count+1)
+ begin
+ alt_cal_error_reg = alt_cal_error[count] | alt_cal_error_reg;
+ end
+
+ if(alt_cal_busy == 1'b0)
+ req_and_use_mutex <= 1'b0;
+ else
+ req_and_use_mutex <= 1'b1;
+
+ case (state)
+ IDLE_STATE:
+ begin
+ offset_cancellation_done <= 1'b0; // reset write/read done flag
+ //reset the signal
+ set_busy <= 1'b0;
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ alt_cal_remap_addr <= 12'h000;
+
+ //al_cal will not assert wren and rden at the same time
+ if((alt_cal_dprio_wren == 1'b1) || (alt_cal_dprio_rden == 1'b1))
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(alt_cal_dprio_wren == 1'b1)
+ write_read_control <= 1'b1; // 1 for write
+ else
+ write_read_control <= 1'b0; // 0 for read
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ else
+ state <= IDLE_STATE;
+ end
+ else if(alt_cal_retain_addr == 1'b1)
+ begin
+ if(mutex_grant == 1'b1)
+ state <= WRITE_DATA_STATE;
+ else
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ state <= IDLE_STATE;
+ end
+ end
+ LOGICAL_ADDRESS_STATE: //sending channel and quad address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h1;
+ master_write_data <= {{21{1'b0}}, alt_cal_quad_addr, alt_cal_dprio_addr[13:12]};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= READ_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ end
+ READ_PHY_ADDR_STATE: //read phsical address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h2;
+ master_read <= 1'b1;
+ master_write <= 1'b0;
+ if (wait_phy_addr_ready == 1'b1)
+ begin
+ wait_phy_addr_ready <= 1'b0;
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ wait_phy_addr_ready <= 1'b1;
+ state <= READ_PHY_ADDR_STATE;
+ //state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_PHY_ADDR_STATE;
+ end
+ end
+ CHECK_PHY_ADDR_STATE: //check physical address correct or not
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ if (master_read_data[9:0] == ILLEGAL_PHYSICAL_CHNL)
+ begin
+ // synopsys translate_off
+ $display ("Illegal physical address: 10'h%h", master_read_data);
+ $display ("Time: %0t Instance: %m", $time);
+ // synopsys translate_on
+ alt_cal_remap_addr <= 12'hfff;
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ alt_cal_remap_addr <= master_read_data[11:0];
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ else
+ begin
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ ADDRESS_OFFSET_STATE: // send address offset to alt_dprio
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h4;
+ master_write_data <= {{17{1'b0}}, alt_cal_dprio_addr[14:0]};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(write_read_control == 1'b1)
+ state <= WRITE_DATA_STATE;
+ else
+ state <= CONTROL_STATE;
+ end
+ else
+ begin
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ WRITE_DATA_STATE:
+ begin
+ master_address <= 3'h5;
+ master_write_data = {{16{1'b0}}, alt_cal_dprio_dataout};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= CONTROL_STATE;
+ end
+ CONTROL_STATE: // sending write/read command
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h3; // get ready to send control command to alt_dprio
+// master_write_data <= {{29{1'b0}}, (~write_read_control), write_read_control};
+ master_write_data <= {{27{1'b0}}, 1'b1, 1'b0, (~write_read_control), write_read_control}; // use absolute addressing
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ state <= BASE_BUSY_STATE;
+ end
+ else
+ begin
+ state <= CONTROL_STATE;
+ end
+ end
+ BASE_BUSY_STATE: // send busy to reconfig_togxb
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h7; // set offset cancellation busy to reconfig_togxb
+ master_write_data <= {{30{1'b0}}, alt_cal_busy};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(set_busy == 1'b0)
+ begin
+ set_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ else
+ begin
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= BASE_BUSY_STATE;
+ end
+ end
+ BUSY_STATE: // wait for write done
+ begin
+ if(offset_cancellation_irq_from_base == 1'b1)
+ begin
+ alt_cal_dprio_busy <= 1'b1;
+ if(write_read_control == 1'b0) //read
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_cal_dprio_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ end
+ WRITE_DONE_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(offset_cancellation_irq_from_base == 1'b1)
+ begin
+ if(alt_cal_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_cal_dprio_busy_int <= master_read_data[8];
+ alt_cal_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ else
+ begin
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ master_address <= 3'h3;
+ master_write_data <= {{16{1'b0}}, {16'h0000}}; //acknowledge write operation
+ alt_cal_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_cal_dprio_busy <= 1'b0;
+ offset_cancellation_done <= 1'b1; // write done
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ READ_DATA_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(offset_cancellation_irq_from_base == 1'b1)
+ begin
+ if(alt_cal_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_cal_dprio_busy_int <= master_read_data[8];
+ alt_cal_dprio_busy <= 1'b1;
+ end
+ else
+ begin
+ master_address <= 3'h5;
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ alt_cal_dprio_busy <= 1'b1;
+ end
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ offset_cancellation_done <= 1'b1; // read done
+ alt_cal_dprio_datain <= master_read_data[15:0];
+ alt_cal_dprio_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_DATA_STATE;
+ end
+ end
+ default:
+ begin
+ state <= IDLE_STATE;
+ end
+ endcase
+ end
+end
+
+
+
+generate
+
+//Deepak Use alt_cal_mm for SIV and AIIGX
+if((device_family=="Stratix IV") || (device_family=="Arria II GX") || (device_family=="Arria II GZ") || (device_family=="HardCopy IV"))
+begin
+ alt_cal_mm #(
+ .number_of_channels (number_of_reconfig_interfaces*4),
+ .channel_address_width (CLogB2(number_of_reconfig_interfaces*4))
+ )alt_cal_inst
+ (
+ .clock(reconfig_clk),
+ .reset(reset),
+ .start(),
+ .busy(alt_cal_busy),
+ .dprio_addr(alt_cal_dprio_addr), // only extract the logical channel address
+ .quad_addr(alt_cal_quad_addr),
+ .dprio_dataout(alt_cal_dprio_dataout),
+ .dprio_datain(alt_cal_dprio_datain),
+ .dprio_wren(alt_cal_dprio_wren),
+ .dprio_rden(alt_cal_dprio_rden),
+ .dprio_busy(alt_cal_dprio_busy),
+ .retain_addr(alt_cal_retain_addr),
+ .remap_addr(alt_cal_remap_addr),
+ .testbuses(alt_cal_testbuses),
+ .cal_error(alt_cal_error)
+ );
+end
+//Deepak: Use alt_cal_c3gxb for Cyclone IV GX
+if(device_family=="Cyclone IV GX")
+begin
+ alt_cal_c3gxb alt_cal_inst
+ (
+ .clock(reconfig_clk),
+ .reset(reset),
+ .start(),
+ .busy(alt_cal_busy),
+ .dprio_addr(alt_cal_dprio_addr), // only extract the logical channel address
+ .quad_addr(alt_cal_quad_addr),
+ .dprio_dataout(alt_cal_dprio_dataout),
+ .dprio_datain(alt_cal_dprio_datain),
+ .dprio_wren(alt_cal_dprio_wren),
+ .dprio_rden(alt_cal_dprio_rden),
+ .dprio_busy(alt_cal_dprio_busy),
+ .retain_addr(alt_cal_retain_addr),
+ .remap_addr(alt_cal_remap_addr),
+ .testbuses(alt_cal_testbuses),
+ .cal_error(alt_cal_error)
+ );
+defparam
+ alt_cal_inst.number_of_channels = number_of_reconfig_interfaces*4,
+ alt_cal_inst.channel_address_width = CLogB2(number_of_reconfig_interfaces*4);
+end
+endgenerate
+
+alt_mutex_acq #(
+ .mutex_wait_time(102), ///Thia: pick a different mutex wait time to avoid collision. Say 102. (since analog is already using 101)
+ .addr_width(5),
+ .data_width(32)
+)
+mutex_inst (
+ .clk(reconfig_clk),
+ .reset(reset),
+// inputs to the base that should be routed through the mutex
+ .address(master_address_shifted),
+ .writedata(master_write_data),
+ .write(master_write),
+ .read(master_read),
+// output from the mutex which is processed form of output from base
+ .waitrequest(),
+ .readdata(master_read_data),
+
+// outputs from mutex to be routed to the base
+ .master_address(offset_cancellation_address_base),
+ .master_writedata(offset_cancellation_writedata_base),
+ .master_write(offset_cancellation_write_base),
+ .master_read(offset_cancellation_read_base),
+
+// these ports are from the base routed to the mutex
+ .master_waitrequest(offset_cancellation_waitrequest_from_base),
+ .master_readdata(offset_cancellation_readdata_base), // from MM
+
+//request signal to the mutex should be kept high as long as the mutex is being used
+ .mutex_req(req_and_use_mutex),
+// output from mutex indicates whether you have mutex or not
+ .mutex_grant(mutex_grant)
+);
+
+//wire assignment
+assign alt_cal_testbuses = testbus_data;
+assign master_address_shifted = {master_address, {2'b00}};
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_siv.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_siv.sv
new file mode 100644
index 0000000000000000000000000000000000000000..727be748a008f29b2f9649fef902f9787b9b1f47
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_reconfig_siv.sv
@@ -0,0 +1,441 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Transceiver Reconfiguration Module for Stratix IV architectures
+//
+// Includes many function-specific sub-modules, such as:
+// - analog reconfig (alt_xcvr_reconfig_analog)
+// - offset cancellation (alt_xcvr_reconfig_offset_cancellation)
+// - ...
+
+// $Header$
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_reconfig_siv #(
+ parameter number_of_reconfig_interfaces = 1
+) (
+ input wire mgmt_clk_clk, // mgmt_clk.clk
+ input wire mgmt_rst_reset, // mgmt_rst.reset
+
+ // user reconfiguration management interface
+ input wire [6:0] reconfig_mgmt_address, // reconfig_mgmt.address
+ output reg reconfig_mgmt_waitrequest = 0, // .waitrequest
+ input wire reconfig_mgmt_read, // .read
+ output reg [31:0] reconfig_mgmt_readdata = ~0, // .readdata
+ input wire reconfig_mgmt_write, // .write
+ input wire [31:0] reconfig_mgmt_writedata, // .writedata
+ output wire reconfig_done, // reconfig_done.export
+
+ output wire [3:0] reconfig_togxb, // reconfig_togxb_data.data
+ input wire [number_of_reconfig_interfaces*17 - 1 : 0] reconfig_fromgxb // dprioout, testbus from altgx : (17+4 bits/quad)
+);
+
+ // master interface to basic reconfiguration block that interfaces to the transceiver channel
+ wire [2:0] basic_address; // basic.address // master interface must include 2 lower addr bits
+ wire basic_waitrequest; // .waitrequest
+ wire basic_irq; // .irq
+ wire basic_read; // .read
+ wire [31:0] basic_readdata; // .readdata
+ wire basic_write; // .write
+ wire [31:0] basic_writedata; // .writedata
+
+ // native testbus input
+ wire [15:0] testbus_data;
+
+ localparam l_dev_family = "Stratix IV";
+ localparam width_awa = 3; // word address width of interface to analog reconfig block
+ localparam width_bwa = 3; // word address width of interface to basic reconfig block
+ localparam arb_count = 4; // count of the total number of sub-components that can act
+ // as slaves to the mgmt interface, and masters to the 'basic' block
+ localparam arb_offset = 0;
+ localparam arb_analog = 1;
+ localparam arb_eyemon = 2;
+ localparam arb_dfe = 3;
+
+ // Analog controls output ports, mgmt facing
+ wire [31:0] sc_analog_readdata;
+ wire sc_analog_waitrequest;
+
+ // Offset cancellation output ports, mgmt facing
+ wire [31:0] sc_offset_readdata;
+ wire sc_offset_waitrequest;
+
+ // Eyemon output ports, mgmt facing
+ wire [31:0] sc_eyemon_readdata;
+ wire sc_eyemon_waitrequest;
+
+ // DFE output ports, mgmt facing
+ wire [31:0] sc_dfe_readdata;
+ wire sc_dfe_waitrequest;
+
+ ///////////////////////////////////////////////////////////////////////
+ // Decoder for multiple slaves of reconfig_mgmt interface
+ ///////////////////////////////////////////////////////////////////////
+ wire [arb_count-1:0] r_decode;
+ assign r_decode =
+ (reconfig_mgmt_address[6:width_awa] == arb_offset) ? (({arb_count-arb_offset{1'b0}} | 1'b1) << arb_offset)
+ : (reconfig_mgmt_address[6:width_awa] == arb_analog) ? (({arb_count-arb_analog{1'b0}} | 1'b1) << arb_analog)
+ : (reconfig_mgmt_address[6:width_awa] == arb_eyemon) ? (({arb_count-arb_eyemon{1'b0}} | 1'b1) << arb_eyemon)
+ : (reconfig_mgmt_address[6:width_awa] == arb_dfe) ? (({arb_count-arb_dfe{1'b0}} | 1'b1) << arb_dfe)
+ : {arb_count{1'b0}};
+
+ // reconfig_mgmt output generation is muxing of decoded slave output
+ always @(*) begin
+ case (reconfig_mgmt_address[6:width_awa])
+ arb_offset: begin
+ reconfig_mgmt_readdata = sc_offset_readdata;
+ reconfig_mgmt_waitrequest = sc_offset_waitrequest;
+ end
+ arb_analog: begin
+ reconfig_mgmt_readdata = sc_analog_readdata;
+ reconfig_mgmt_waitrequest = sc_analog_waitrequest;
+ end
+ arb_eyemon: begin
+ reconfig_mgmt_readdata = sc_eyemon_readdata;
+ reconfig_mgmt_waitrequest = sc_eyemon_waitrequest;
+ end
+ arb_dfe: begin
+ reconfig_mgmt_readdata = sc_dfe_readdata;
+ reconfig_mgmt_waitrequest = sc_dfe_waitrequest;
+ end
+ default: begin
+ reconfig_mgmt_readdata = -1;
+ reconfig_mgmt_waitrequest = 1'b0;
+ end
+ endcase
+ end
+
+ ///////////////////////////////////////////////////////////////////////
+ // Arbiter for multiple masters accessing 'basic' reconfig slave port
+ ///////////////////////////////////////////////////////////////////////
+ wire [arb_count-1:0] req; // req[0] is highest priority when current grantee is done
+ wire [arb_count-1:0] grant;
+
+ alt_xcvr_arbiter #(
+ .width(arb_count) // count total number of sub-components that act as masters to 'basic'
+ ) arbiter (
+ .clock(mgmt_clk_clk),
+ .req(req),
+ .grant(grant)
+ );
+
+ ////////////////////////////////////
+ // Sub-component: analog controls
+ // word address offset: +0
+ ////////////////////////////////////
+
+ // Analog controls output ports, mgmt facing
+ wire analog_reconfig_done;
+ // Analog controls output ports, basic slave facing
+ wire [width_bwa+1:0] scs_analog_address;
+ wire [31:0] scs_analog_writedata;
+ wire scs_analog_write;
+ wire scs_analog_read;
+
+ // Analog controls master-to-slave access fabric outputs
+ tri0 m2s_analog_read;
+ tri0 m2s_analog_write;
+ tri0 [width_bwa-1:0] m2s_analog_address;
+ tri0 [31:0] m2s_analog_writedata;
+ wire [31:0] m2s_analog_readdata;
+ wire m2s_analog_waitrequest;
+
+ alt_xcvr_reconfig_analog_tgx sc_analog (
+ .reconfig_clk(mgmt_clk_clk),
+ .reset(mgmt_rst_reset),
+ // external mgmt interface facing
+ .analog_reconfig_address(reconfig_mgmt_address[width_awa-1:0]),
+ .analog_reconfig_writedata(reconfig_mgmt_writedata),
+ .analog_reconfig_write(reconfig_mgmt_write & r_decode[arb_analog]),
+ .analog_reconfig_read(reconfig_mgmt_read & r_decode[arb_analog]),
+ .analog_reconfig_readdata(sc_analog_readdata),
+ .analog_reconfig_waitrequest(sc_analog_waitrequest),
+ .analog_reconfig_done(analog_reconfig_done),
+ // master-to-slave fabric facing, to basic reconfig
+ .analog_reconfig_irq_from_base(basic_irq),
+ .analog_reconfig_waitrequest_from_base(m2s_analog_waitrequest),
+ .analog_reconfig_readdata_base(m2s_analog_readdata),
+ .analog_reconfig_address_base(scs_analog_address),
+ .analog_reconfig_writedata_base(scs_analog_writedata),
+ .analog_reconfig_write_base(scs_analog_write),
+ .analog_reconfig_read_base(scs_analog_read)
+ );
+
+ // master-to-slave access module
+ alt_xcvr_m2s #(
+ .width_addr(width_bwa),
+ .width_data(32)
+ ) m2s_analog (
+ .clock(mgmt_clk_clk),
+ .req(req[arb_analog]),
+ .grant(grant[arb_analog]),
+ // master ports, facing basic reconfig block
+ .m_read(scs_analog_read),
+ .m_write(scs_analog_write),
+ .m_address(scs_analog_address[2 +: width_bwa]), // drop 2 lower addr bits
+ .m_writedata(scs_analog_writedata),
+ .m_readdata(m2s_analog_readdata),
+ .m_waitrequest(m2s_analog_waitrequest),
+ // slave-side ports, from basic reconfig block
+ .s_readdata(basic_readdata),
+ .s_waitrequest(basic_waitrequest),
+ .s_read(m2s_analog_read),
+ .s_write(m2s_analog_write),
+ .s_address(m2s_analog_address),
+ .s_writedata(m2s_analog_writedata)
+ );
+
+ ///////////////////////////////////////////
+ // Sub-component: offset cancellation
+ // word address offset: +8 (0x20 in bytes)
+ ///////////////////////////////////////////
+
+ // Offset cancellation output ports:
+ wire offset_cancellation_done;
+ wire [width_bwa-1:0] scs_offset_address;
+ wire [31:0] scs_offset_writedata;
+ wire scs_offset_write;
+ wire scs_offset_read;
+
+ // Offset cancellation master-to-slave access fabric outputs
+ tri0 m2s_offset_read;
+ tri0 m2s_offset_write;
+ tri0 [width_bwa-1:0] m2s_offset_address;
+ tri0 [31:0] m2s_offset_writedata;
+ wire [31:0] m2s_offset_readdata;
+ wire m2s_offset_waitrequest;
+
+ alt_xcvr_reconfig_offset_cancellation #(
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces),
+ .device_family(l_dev_family)
+ ) sc_offset (
+ .reconfig_clk(mgmt_clk_clk),
+ .reset(mgmt_rst_reset),
+ // external mgmt interface facing
+ .offset_cancellation_address(reconfig_mgmt_address[0]), // slave uses a single address bit
+ .offset_cancellation_writedata(reconfig_mgmt_writedata),
+ .offset_cancellation_write(reconfig_mgmt_write & r_decode[arb_offset]),
+ .offset_cancellation_read(reconfig_mgmt_read & r_decode[arb_offset]),
+ .offset_cancellation_readdata(sc_offset_readdata),
+ .offset_cancellation_waitrequest(sc_offset_waitrequest),
+ // master-to-slave fabric facing, to basic reconfig
+ .offset_cancellation_irq_from_base(basic_irq),
+ .offset_cancellation_waitrequest_from_base(m2s_offset_waitrequest),
+ .offset_cancellation_readdata_base(m2s_offset_readdata),
+ .testbus_data(testbus_data),
+ .offset_cancellation_done(offset_cancellation_done),
+ .offset_cancellation_address_base(scs_offset_address),
+ .offset_cancellation_writedata_base(scs_offset_writedata),
+ .offset_cancellation_write_base(scs_offset_write),
+ .offset_cancellation_read_base(scs_offset_read)
+ );
+
+ // master-to-slave access module
+ alt_xcvr_m2s #(
+ .width_addr(width_bwa),
+ .width_data(32)
+ ) m2s_offset (
+ .clock(mgmt_clk_clk),
+ .req(req[arb_offset]),
+ .grant(grant[arb_offset]),
+ // master ports, facing basic reconfig block
+ .m_read(scs_offset_read),
+ .m_write(scs_offset_write),
+ .m_address(scs_offset_address), // drop 2 lower addr bits
+ .m_writedata(scs_offset_writedata),
+ .m_readdata(m2s_offset_readdata),
+ .m_waitrequest(m2s_offset_waitrequest),
+ // slave-side ports, from basic reconfig block
+ .s_readdata(basic_readdata),
+ .s_waitrequest(basic_waitrequest),
+ .s_read(m2s_offset_read),
+ .s_write(m2s_offset_write),
+ .s_address(m2s_offset_address),
+ .s_writedata(m2s_offset_writedata)
+ );
+
+ ///////////////////////////////////////////
+ // Sub-component: "EyeQ" eye monitor
+ // word address offset: +16 (0x40 in bytes)
+ ///////////////////////////////////////////
+
+ // Eyemon output ports:
+ wire eyemon_done;
+ wire [width_bwa+1:0] scs_eyemon_address;
+ wire [31:0] scs_eyemon_writedata;
+ wire scs_eyemon_write;
+ wire scs_eyemon_read;
+
+ // eyemon master-to-slave access fabric outputs
+ tri0 m2s_eyemon_read;
+ tri0 m2s_eyemon_write;
+ tri0 [width_bwa-1:0] m2s_eyemon_address;
+ tri0 [31:0] m2s_eyemon_writedata;
+ wire [31:0] m2s_eyemon_readdata;
+ wire m2s_eyemon_waitrequest;
+
+ alt_xcvr_reconfig_eyemon_tgx #(
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces),
+ .device_family(l_dev_family)
+ ) sc_eyemon (
+ .reconfig_clk(mgmt_clk_clk),
+ .reset(mgmt_rst_reset),
+ // external mgmt interface facing
+ .eyemon_address(reconfig_mgmt_address[width_awa-1:0]), // slave uses a 3-bit address
+ .eyemon_writedata(reconfig_mgmt_writedata),
+ .eyemon_write(reconfig_mgmt_write & r_decode[arb_eyemon]),
+ .eyemon_read(reconfig_mgmt_read & r_decode[arb_eyemon]),
+ .eyemon_readdata(sc_eyemon_readdata),
+ .eyemon_waitrequest(sc_eyemon_waitrequest),
+ // master-to-slave fabric facing, to basic reconfig
+ .eyemon_irq_from_base(basic_irq),
+ .eyemon_waitrequest_from_base(m2s_eyemon_waitrequest),
+ .eyemon_readdata_base(m2s_eyemon_readdata),
+ .eyemon_irq(eyemon_done),
+ .eyemon_address_base(scs_eyemon_address),
+ .eyemon_writedata_base(scs_eyemon_writedata),
+ .eyemon_write_base(scs_eyemon_write),
+ .eyemon_read_base(scs_eyemon_read)
+ );
+
+ // master-to-slave access module
+ alt_xcvr_m2s #(
+ .width_addr(width_bwa),
+ .width_data(32)
+ ) m2s_eyemon (
+ .clock(mgmt_clk_clk),
+ .req(req[arb_eyemon]),
+ .grant(grant[arb_eyemon]),
+ // master ports, facing basic reconfig block
+ .m_read(scs_eyemon_read),
+ .m_write(scs_eyemon_write),
+ .m_address(scs_eyemon_address[2 +: width_bwa]), // drop 2 lower addr bits
+ .m_writedata(scs_eyemon_writedata),
+ .m_readdata(m2s_eyemon_readdata),
+ .m_waitrequest(m2s_eyemon_waitrequest),
+ // slave-side ports, from basic reconfig block
+ .s_readdata(basic_readdata),
+ .s_waitrequest(basic_waitrequest),
+ .s_read(m2s_eyemon_read),
+ .s_write(m2s_eyemon_write),
+ .s_address(m2s_eyemon_address),
+ .s_writedata(m2s_eyemon_writedata)
+ );
+
+ ///////////////////////////////////////////
+ // Sub-component: DFE
+ // word address offset: +24 (0x60 in bytes)
+ ///////////////////////////////////////////
+
+ // DFE output ports:
+ wire dfe_done;
+ wire [width_bwa-1:0] scs_dfe_address;
+ wire [31:0] scs_dfe_writedata;
+ wire scs_dfe_write;
+ wire scs_dfe_read;
+
+ // dfe master-to-slave access fabric outputs
+ tri0 m2s_dfe_read;
+ tri0 m2s_dfe_write;
+ tri0 [width_bwa-1:0] m2s_dfe_address;
+ tri0 [31:0] m2s_dfe_writedata;
+ wire [31:0] m2s_dfe_readdata;
+ wire m2s_dfe_waitrequest;
+
+ alt_xcvr_reconfig_dfe_tgx #(
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces),
+ .device_family(l_dev_family)
+ ) sc_dfe (
+ .reconfig_clk(mgmt_clk_clk),
+ .reset(mgmt_rst_reset),
+ // external mgmt interface facing
+ .dfe_address(reconfig_mgmt_address[width_awa-1:0]), // slave uses a 3-bit address
+ .dfe_writedata(reconfig_mgmt_writedata),
+ .dfe_write(reconfig_mgmt_write & r_decode[arb_dfe]),
+ .dfe_read(reconfig_mgmt_read & r_decode[arb_dfe]),
+ .dfe_readdata(sc_dfe_readdata),
+ .dfe_waitrequest(sc_dfe_waitrequest),
+ // master-to-slave fabric facing, to basic reconfig
+ .dfe_irq_from_base(basic_irq),
+ .dfe_waitrequest_from_base(m2s_dfe_waitrequest),
+ .dfe_readdata_base(m2s_dfe_readdata),
+ .dfe_irq(dfe_done),
+ .dfe_address_base(scs_dfe_address),
+ .dfe_writedata_base(scs_dfe_writedata),
+ .dfe_write_base(scs_dfe_write),
+ .dfe_read_base(scs_dfe_read)
+ );
+
+ // master-to-slave access module
+ alt_xcvr_m2s #(
+ .width_addr(width_bwa),
+ .width_data(32)
+ ) m2s_dfe (
+ .clock(mgmt_clk_clk),
+ .req(req[arb_dfe]),
+ .grant(grant[arb_dfe]),
+ // master ports, facing basic reconfig block
+ .m_read(scs_dfe_read),
+ .m_write(scs_dfe_write),
+ .m_address(scs_dfe_address),
+ .m_writedata(scs_dfe_writedata),
+ .m_readdata(m2s_dfe_readdata),
+ .m_waitrequest(m2s_dfe_waitrequest),
+ // slave-side ports, from basic reconfig block
+ .s_readdata(basic_readdata),
+ .s_waitrequest(basic_waitrequest),
+ .s_read(m2s_dfe_read),
+ .s_write(m2s_dfe_write),
+ .s_address(m2s_dfe_address),
+ .s_writedata(m2s_dfe_writedata)
+ );
+
+
+ ///////////////////////////////////////////
+ // Outputs to basic block
+ ///////////////////////////////////////////
+ assign basic_address = m2s_analog_address | m2s_offset_address | m2s_eyemon_address | m2s_dfe_address;
+ assign basic_read = m2s_analog_read | m2s_offset_read | m2s_eyemon_read | m2s_dfe_read;
+ assign basic_write = m2s_analog_write | m2s_offset_write | m2s_eyemon_write | m2s_dfe_write;
+ assign basic_writedata = m2s_analog_writedata | m2s_offset_writedata | m2s_eyemon_writedata | m2s_dfe_writedata;
+
+ wire [number_of_reconfig_interfaces*8 - 1 : 0] aeq_fromgxb_data=0;
+ wire [number_of_reconfig_interfaces*24 - 1 : 0] aeq_togxb_data;
+
+ alt_xcvr_reconfig_basic_tgx #(
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces)
+ ) sc_basic (
+ .reconfig_clk(mgmt_clk_clk),
+ .reset(mgmt_rst_reset),
+ .basic_reconfig_write(basic_write),
+ .basic_reconfig_read(basic_read),
+ .basic_reconfig_writedata(basic_writedata),
+ .basic_reconfig_address(basic_address),
+ .basic_reconfig_fromgxb_data(reconfig_fromgxb),
+ .aeq_fromgxb_data(aeq_fromgxb_data),
+ .basic_reconfig_readdata(basic_readdata),
+ .basic_reconfig_waitrequest(basic_waitrequest),
+ .basic_reconfig_togxb_data(reconfig_togxb),
+ .aeq_togxb_data(aeq_togxb_data),
+ .testbus_data(testbus_data),
+ .basic_reconfig_irq(basic_irq)
+ );
+
+
+ ///////////////////////////////////////////
+ // Status to external mgmt interface
+ ///////////////////////////////////////////
+ assign reconfig_done = analog_reconfig_done | offset_cancellation_done | eyemon_done | dfe_done;
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_resync.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_resync.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5c723372b22da2640f7283962c5acdd598a91dfa
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/alt_xcvr_resync.sv
@@ -0,0 +1,98 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Module: alt_xcvr_resync
+//
+// Description:
+// A general purpose resynchronization module.
+//
+// Parameters:
+// SYNC_CHAIN_LENGTH
+// - Specifies the length of the synchronizer chain for metastability
+// retiming.
+// WIDTH
+// - Specifies the number of bits you want to synchronize. Controls the width of the
+// d and q ports.
+// SLOW_CLOCK - USE WITH CAUTION.
+// - Leaving this setting at its default will create a standard resynch circuit that
+// merely passes the input data through a chain of flip-flops. This setting assumes
+// that the input data has a pulse width longer than one clock cycle sufficient to
+// satisfy setup and hold requirements on at least one clock edge.
+// - By setting this to 1 (USE CAUTION) you are creating an asynchronous
+// circuit that will capture the input data regardless of the pulse width and
+// its relationship to the clock. However it is more difficult to apply static
+// timing constraints as it ties the data input to the clock input of the flop.
+// This implementation assumes the data rate is slow enough
+// INIT_VALUE
+// - Specifies the initial values of the synchronization registers.
+//
+// Apply embedded false path timing constraint
+(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_resync*sync_r[0]]\"" *)
+
+`timescale 1ps/1ps
+
+module alt_xcvr_resync #(
+ parameter SYNC_CHAIN_LENGTH = 2, // Number of flip-flops for retiming
+ parameter WIDTH = 1, // Number of bits to resync
+ parameter SLOW_CLOCK = 0, // See description above
+ parameter INIT_VALUE = 0
+ ) (
+ input wire clk,
+ input wire reset,
+ input wire [WIDTH-1:0] d,
+ output wire [WIDTH-1:0] q
+ );
+
+localparam INT_LEN = (SYNC_CHAIN_LENGTH > 0) ? SYNC_CHAIN_LENGTH : 1;
+localparam [INT_LEN-1:0] L_INIT_VALUE = (INIT_VALUE == 1) ? {INT_LEN{1'b1}} : {INT_LEN{1'b0}};
+
+genvar ig;
+
+// Generate a synchronizer chain for each bit
+generate begin
+ for(ig=0;ig<WIDTH;ig=ig+1) begin : resync_chains
+ wire d_in; // Input to sychronization chain.
+ reg [INT_LEN-1:0] sync_r = L_INIT_VALUE;
+ wire [INT_LEN :0] next_r; // One larger than real chain
+
+ assign q[ig] = sync_r[INT_LEN-1]; // Output signal
+ assign next_r = {sync_r,d_in};
+
+ always @(posedge clk or posedge reset)
+ if(reset)
+ sync_r <= L_INIT_VALUE;
+ else
+ sync_r <= next_r[INT_LEN-1:0];
+
+ // Generate asynchronous capture circuit if specified.
+ if(SLOW_CLOCK == 0) begin
+ assign d_in = d[ig];
+ end else begin
+ wire d_clk;
+ reg d_r = L_INIT_VALUE[0];
+ wire clr_n;
+
+ assign d_clk = d[ig];
+ assign d_in = d_r;
+ assign clr_n = ~q[ig] | d_clk; // Clear when output is logic 1 and input is logic 0
+
+ // Asynchronously latch the input signal.
+ always @(posedge d_clk or negedge clr_n)
+ if(!clr_n) d_r <= 1'b0;
+ else if(d_clk) d_r <= 1'b1;
+ end // SLOW_CLOCK
+ end // for loop
+end // generate
+endgenerate
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/altera_wait_generate.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/altera_wait_generate.v
new file mode 100644
index 0000000000000000000000000000000000000000..d11ec7e154387185d9a1d14b39c0410608a6c6ed
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/altera_wait_generate.v
@@ -0,0 +1,38 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module altera_wait_generate
+//#(
+//This code only works when wait_cycle =1, if need other case, you need to modify this code.
+//please set wait_cycle default value as 1 to keep old design works.
+// parameter wait_cycle =1
+// )
+(
+ input wire rst,
+ input wire clk,
+ input wire launch_signal,
+ output wire wait_req
+ );
+reg launch_reg = 0;
+reg wait_reg = 0;
+always @ (posedge clk, posedge rst) begin
+ if(rst) launch_reg <= 1'b0;
+ else launch_reg <= launch_signal;
+end
+always @ (posedge clk, posedge rst) begin
+ if(rst) wait_reg <= 1'b0;
+ else wait_reg <= launch_signal & launch_reg & (! wait_reg & !wait_req);
+end
+assign wait_req = (launch_signal & ~launch_reg) | (wait_reg & launch_signal ) ;
+endmodule
\ No newline at end of file
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/altera_xcvr_functions.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/altera_xcvr_functions.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5ef175a54cc3ce30e9dded8e494731600eb6ffda
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/altera_xcvr_functions.sv
@@ -0,0 +1,746 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common functions for transceiver PHY IP
+//
+// $Header$
+//
+// PACKAGE DECLARATION
+package altera_xcvr_functions;
+ localparam integer MAX_CHARS = 32;
+ localparam integer MAX_STRS = 16;
+ localparam integer MAX_XCVR_CHANNELS = 64;
+
+ // Reconfiguration bundle widths per family
+ localparam integer W_S5_RECONFIG_BUNDLE_TO_XCVR = 70;
+ localparam integer W_S5_RECONFIG_BUNDLE_FROM_XCVR = 46;
+ localparam integer W_A5_RECONFIG_BUNDLE_TO_XCVR = 70;
+ localparam integer W_A5_RECONFIG_BUNDLE_FROM_XCVR = 46;
+ localparam integer W_S4_RECONFIG_BUNDLE_TO_XCVR = 4;
+ localparam integer W_S4_RECONFIG_BUNDLE_FROM_XCVR = 17;
+ localparam integer W_C4_RECONFIG_BUNDLE_TO_XCVR = 4;
+ localparam integer W_C4_RECONFIG_BUNDLE_FROM_XCVR = 17;
+
+ // Reconfiguration bundle widths per family
+ localparam integer W_S5_RECONFIG_BUNDLE_TO_GXB = W_S5_RECONFIG_BUNDLE_TO_XCVR;
+ localparam integer W_S5_RECONFIG_BUNDLE_FROM_GXB = W_S5_RECONFIG_BUNDLE_FROM_XCVR;
+ localparam integer W_A5_RECONFIG_BUNDLE_TO_GXB = W_A5_RECONFIG_BUNDLE_TO_XCVR;
+ localparam integer W_A5_RECONFIG_BUNDLE_FROM_GXB = W_A5_RECONFIG_BUNDLE_FROM_XCVR;
+ localparam integer W_S4_RECONFIG_BUNDLE_TO_GXB = W_S4_RECONFIG_BUNDLE_TO_XCVR;
+ localparam integer W_S4_RECONFIG_BUNDLE_FROM_GXB = W_S4_RECONFIG_BUNDLE_FROM_XCVR;
+ localparam integer W_C4_RECONFIG_BUNDLE_TO_GXB = W_C4_RECONFIG_BUNDLE_TO_XCVR;
+ localparam integer W_C4_RECONFIG_BUNDLE_FROM_GXB = W_C4_RECONFIG_BUNDLE_FROM_XCVR;
+
+ // convert frequency string into integer Hz. Fractional Hz are truncated
+ // Must remain a constant function - can't use string.atoi().
+ function time str2hz (
+ input [8*MAX_CHARS:1] s
+ );
+
+ integer i;
+ integer c; // temp char storage for frequency conversion
+ integer unit_tens; // assume already Hz
+ integer is_numeric;
+ integer saw_dot;
+
+ reg [8:1] c_dot; // = ".";
+ reg [8:1] c_space; // = " ";
+ reg [8:1] c_a; // = 8'h61; //"a";
+ reg [8:1] c_z; // = 8'h7a; //"z";
+ reg [8*4:1] s_unit;
+ reg [8*MAX_CHARS:1] s_shift;
+
+ begin
+ // frequency ratio calculations
+ str2hz = 0;
+ unit_tens = 0; // assume already Hz
+ is_numeric = 1;
+ saw_dot = 0;
+ s_unit = "";
+
+ // Modelsim optimizer bug forces us to initialize these non-statically
+ c_dot = ".";
+ c_space = " ";
+ c_a = "a";
+ c_z = "z";
+ for (i=(MAX_CHARS-1); i>=0; i=i-1) begin
+ s_shift = (s >> (i*8));
+ c = s_shift[8:1] & 8'hff;
+ if (c > 0) begin
+ //$display("[%d] => '%1s',", i, c);
+ if (c >= 8'h30 && c <= 8'h39 && is_numeric) begin
+ str2hz = (str2hz * 10) + (c & 8'h0f);
+ if (saw_dot) unit_tens = unit_tens - 1; // count digits after decimal point
+ end else if (c == c_dot) saw_dot = 1;
+ else if (c != c_space) begin
+ is_numeric = 0; // stop accepting new numeric digits in value
+ // if it's a-z, convert to upper case A-Z
+ if (c >= c_a && c <= c_z) c = (c & 8'h5f); // convert a-z (lower) to A-Z (upper)
+ s_unit = (s_unit << 8) | c;
+ end
+ end
+ end
+ //$display("numeric = %d x 10**(%2d), unit = '%0s'", str2hz, unit_tens, s_unit);
+
+ // account for frequency unit
+ if (s_unit == "GHZ" || s_unit == "GBPS") unit_tens = unit_tens + 9; // 10**9
+ else if (s_unit == "MHZ" || s_unit == "MBPS") unit_tens = unit_tens + 6; // 10**6
+ else if (s_unit == "KHZ" || s_unit == "KBPS") unit_tens = unit_tens + 3; // 10**3
+ else if (s_unit != "HZ" && s_unit != "BPS") begin
+ $display("Invalid frequency unit '%0s', assuming %d x 10**(%2d) 'Hz'", s_unit, str2hz, unit_tens);
+ end
+ //$display("numeric in Hz = %d x 10**(%2d)", str2hz, unit_tens);
+
+ // align numeric to Hz
+ if (unit_tens < 0) begin
+ //str2hz = str2hz / (10**(-unit_tens));
+ for (i=0; i>unit_tens; i=i-1) begin
+ str2hz = str2hz / 10;
+ end
+ end else begin
+ //str2hz = str2hz * (10**unit_tens);
+ for (i=0; i<unit_tens; i=i+1) begin
+ str2hz = str2hz * 10;
+ end
+ end
+ //$display("%d Hz", str2hz);
+ end
+ endfunction
+
+ // convert integer Hz to a frequency string
+ // integer Hz as type time, and the frequency string will use MHz units
+ // Must remain a constant function - can't use $sformat or string.itoa().
+ function [MAX_CHARS*8-1:0] hz2str (
+ input time hz
+ );
+ integer pos;
+ integer f_unit; // 10**f_unit is offset from Hz for larger unit
+ time hz_mod_10;
+ begin
+ hz2str = "0.000000 MHz"; // minimum string value
+ f_unit = 6; // MHz offsets Hz value by 6 decimal digits
+
+ // convert time back to string with frequency units
+ // char positions 3 to 0 are used by " MHz", so start with digits at pos 4
+ for (pos = 4; pos < MAX_CHARS && hz > 0; pos = pos + 1) begin
+ if (f_unit == 0) begin
+ hz2str[pos*8 +: 8] = 8'h2e; // add "." character
+ pos = pos + 1;
+ end
+ f_unit = f_unit - 1;
+ hz_mod_10 = (hz % 10);
+ hz2str[pos*8 +: 8] = hz_mod_10[7:0] | 8'h30;
+ hz = hz / 10;
+ //$display("hz2str() => so far '%s', pos (%d), f_unit(%d) ", hz2str, pos, f_unit);
+ end
+ //$display("hz2str() returns '%s'", hz2str);
+ end
+ endfunction
+
+ // Convert a string to an integer
+ // Uses pre-existing str2hz function
+ function integer str2int(
+ input [MAX_CHARS*8-1:0] instring
+ );
+ time temp;
+ temp = str2hz({instring,"Hz"});
+ str2int = temp[31:0];
+ endfunction
+
+
+ // Convert an integer to a string
+ function [MAX_CHARS*8-1:0] int2str(
+ input integer in_int
+ );
+ integer i;
+ integer this_char;
+ i = 0;
+ int2str = "";
+ do
+ begin
+ this_char = (in_int % 10) + 48;
+ int2str[i*8+:8] = this_char[7:0];
+ i=i+1;
+ in_int = in_int / 10;
+ end
+ while(in_int > 0);
+ endfunction
+
+ // function to convert at most 40-bit long string to binary
+ function [39 : 0] m_str_to_bin;
+ input [40*8 : 1] s;
+ reg [40*8 : 1] reg_s;
+ reg [40:1] res;
+
+ integer m;
+ begin
+
+ reg_s = s;
+ for (m = 40; m > 0; m = m-1 )
+ begin
+ res[m] = reg_s[313];
+ reg_s = reg_s << 8;
+ end
+
+ m_str_to_bin = res;
+ end
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Verify that the string value is contained in the legal set.
+ //
+ // The 'set' can consist of a single string with no delimiters, e.g. "individual",
+ // or multiple values, separated by commas, and surrounded by parens, e.g. "(one,two,three,four,five)"
+ //
+ // Returns 1 if the value is in the set, and 0 otherwise
+ function integer is_in_legal_set(
+ input [MAX_CHARS*8-1:0] value,
+ input [MAX_STRS*MAX_CHARS*8-1:0] set
+ );
+ if (value == "<auto_any>")
+ is_in_legal_set = 1;
+ else if (value == "<auto_single>")
+ is_in_legal_set = (set[7:0] == 8'h29) ? 0 : 1; // 8'h29 is closing parenthesis char
+ else if (value == set)
+ is_in_legal_set = 1; // value matches single value in set
+ else begin
+ // check value against each in set
+ integer close_pos; // end of string marker can be comma or closing paren
+ integer open_pos; // open paren is start of set, if appropriate
+ reg [MAX_STRS*MAX_CHARS*8-1:0] legalstr;
+
+ is_in_legal_set = 0;
+ open_pos = MAX_STRS*MAX_CHARS-1;
+ // Remove closing parenthesis if exists
+ if(set[7:0] == 8'h29) begin
+ set = (set >> 8);
+ set[(MAX_STRS*MAX_CHARS*8-1)-:8] = 8'h00;
+ end
+ // look for first non-null and non open paren character
+ while (open_pos > 0 && (set[open_pos*8 +: 8] == 8'h00 || set[open_pos*8 +: 8] == 8'h28)) // look for first non-null
+ open_pos = open_pos - 1;
+
+ while (is_in_legal_set == 0 && open_pos >= 0) begin
+ close_pos = open_pos;
+ while (close_pos > 0
+ && set[close_pos*8 +: 8] != 8'h2c) // look for comma (8'h2c)
+ close_pos = close_pos - 1;
+ if (close_pos >= 0) begin
+ close_pos = close_pos == 0 ? 0 : close_pos + 1;
+ legalstr = ((set & ((1'b1 << open_pos*8+8)-1)) >> close_pos*8);
+ if (value == legalstr)
+ is_in_legal_set = 1;
+ end
+ open_pos = close_pos-2; // prepare to look for next legal string
+ end
+ end
+ //$display("is_in_legal_set(): returns %d", is_in_legal_set);
+ endfunction
+
+
+ // Accepts a string list of comma seperated numbers and returns a binary
+ // field where each bit indicates whether the index corresponding to that bit
+ // was found in the legal set.
+ //
+ // @param count - The number of integer indexes to check for in the set
+ // or the highest integer minus 1.
+ // @param set - The list containing the integer values to search for
+ // @return - A bitfield where each bit indicates whether the corresponding
+ // integer was found in the legal set.
+ function [MAX_XCVR_CHANNELS-1:0] map_numerical_is_in_legal_set(
+ input integer count,
+ input [MAX_STRS*MAX_CHARS*8-1:0] set
+ );
+ integer index;
+ reg [MAX_XCVR_CHANNELS-1:0] retval;
+
+ // Validate count parameter
+ if(count > MAX_XCVR_CHANNELS)
+ $display("Error: [map_numerical_is_in_legal_set]: Invalid value for count: %0d",count);
+
+ map_numerical_is_in_legal_set = {MAX_XCVR_CHANNELS{1'b0}};
+ retval = {MAX_XCVR_CHANNELS{1'b0}};
+ for(index = 0; index < count; index = index + 1) begin
+ if(is_in_legal_set(int2str(index),set))
+ retval = retval | (({MAX_XCVR_CHANNELS{1'b0}} | 1'b1) << index);
+ end
+ map_numerical_is_in_legal_set = retval;
+ endfunction
+
+
+ // Accepts a string list of comma seperated numbers and returns a binary
+ // field where each byte contains the corresponding number found in the
+ // list.
+ //
+ // @param count - The number of elements in the list.
+ // @param set - The list containing the integer values.
+ // @return - A bitfield where each byte contains the corresponding number found
+ // at that location in the list.
+ function [MAX_XCVR_CHANNELS*8-1:0] map_numerical_legal_set(
+ input integer count,
+ input [MAX_STRS*MAX_CHARS*8-1:0] set
+ );
+ integer index;
+ reg [MAX_XCVR_CHANNELS-1:0] retval;
+ reg [MAX_CHARS*8-1:0] str_val;
+ reg [7:0] int_val;
+
+ // Validate count parameter
+ if(count > MAX_XCVR_CHANNELS || count > 256)
+ $display("Error: [map_numerical_legal_set]: Invalid value for count: %0d",count);
+
+ map_numerical_legal_set = {MAX_XCVR_CHANNELS{8'd0}};
+ retval = {MAX_XCVR_CHANNELS{8'd0}};
+ for(index = 0; index < count; index = index + 1) begin
+ str_val = get_value_at_index(index,set);
+ if(str_val != "NA") begin
+ int_val = str2int(str_val);
+ if(int_val > 255)
+ $display("Error: [map_numerical_legal_set]: Invalid string contains non-numerical item or value:%0d",int_val);
+ else begin
+ retval = retval | ( ( {MAX_XCVR_CHANNELS{8'd0}} | int_val ) << (index * 8));
+ end
+ end
+ end
+ map_numerical_legal_set = retval;
+ endfunction
+
+
+ // Accepts a comma separated list of string values and returns the element
+ // found at the specified index. If the index is invalid, "NA" is returned
+ //
+ // @param index - The index of the value to return within "set"
+ // @param set - A comma separated list of string values. The entire list may
+ // be surrounded by parenthesis("(item0,item1,item2)")
+ function [MAX_CHARS*8-1:0] get_value_at_index(
+ input integer index,
+ input [MAX_STRS*MAX_CHARS*8-1:0] set
+ );
+ // check value against each in set
+ integer close_pos; // end of string marker can be comma or closing paren
+ integer open_pos; // open paren is start of set, if appropriate
+ reg [MAX_STRS*MAX_CHARS*8-1:0] legalstr;
+ integer cur_index = 0;
+
+ get_value_at_index = "";
+ legalstr = "NA";
+ cur_index = 0;
+ open_pos = MAX_STRS*MAX_CHARS-1;
+ // Remove closing parenthesis if exists
+ if(set[7:0] == 8'h29) begin
+ set = (set >> 8);
+ set[(MAX_STRS*MAX_CHARS*8-1)-:8] = 8'h00;
+ end
+ // Find the start of the string
+ while (open_pos >= 1 && (set[open_pos*8 +: 8] == 8'h00 || set[open_pos*8 +: 8] == 8'h28)) // look for first non-null
+ open_pos = open_pos - 1;
+
+ // Iterate through list until the string is found or we've reached the end of the list
+ while (legalstr == "NA" && open_pos >= 0 && cur_index <= index) begin
+ close_pos = open_pos;
+ // Move the close iterator to the end of the current value (or end of string)
+ while (close_pos > 0
+ && set[close_pos*8 +: 8] != 8'h2c) // look for comma (8'h2c)
+ close_pos = close_pos - 1;
+ if (close_pos >= 0) begin
+ close_pos = close_pos == 0 ? 0 : close_pos + 1;
+ if(index == cur_index) begin
+ legalstr = ((set & ((1'b1 << open_pos*8+8)-1)) >> close_pos*8);
+ end
+ open_pos = close_pos-2; // prepare to look for next legal string
+ end
+ cur_index = cur_index + 1;
+ end
+
+ cur_index = 0;
+ while(legalstr[cur_index*8+:8] != 0) begin
+ get_value_at_index[cur_index*8+:8] = legalstr[cur_index*8+:8];
+ cur_index = cur_index + 1;
+ end
+
+ //$display("is_in_legal_set(): returns %d", is_in_legal_set);
+ endfunction
+
+
+ ////////////////////////////////////////////////////////////////////////
+ // Calculate the minimum number of bits needed to hold an integer value
+ //
+ // Returns ceil_log2() value
+ localparam integer MAX_PRECISION = 32; // VCS requires this declaration outside the function
+ function integer ceil_log2;
+ input [MAX_PRECISION-1:0] input_num;
+ integer i;
+ reg [MAX_PRECISION-1:0] try_result;
+ begin
+ i = 0;
+ try_result = 1;
+ while ((try_result << i) < input_num && i < MAX_PRECISION)
+ i = i + 1;
+ ceil_log2 = i;
+ end
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Return current device family string for display purposes
+ `ifndef XCVR_DEV_FAM
+ `ifdef ALTERA_RESERVED_QIS_FAMILY
+ `define XCVR_DEV_FAM `ALTERA_RESERVED_QIS_FAMILY // synthesis: use QIS-defined value
+ `else
+ `define XCVR_DEV_FAM device_family // simulation: use passed-in value
+ `endif
+ `endif
+ function [MAX_CHARS*8-1:0] current_device_family (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ current_device_family = `XCVR_DEV_FAM;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Match device family against standard family name strings
+ //
+ // Returns 1 if the names feature is present in the given device family
+ function integer has_s4_style_hssi (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ has_s4_style_hssi = ( (`XCVR_DEV_FAM == "Stratix IV")
+ || (`XCVR_DEV_FAM == "Arria II")
+ || (`XCVR_DEV_FAM == "Cyclone IV GX") // not exact, but close enough
+ || (`XCVR_DEV_FAM == "Arria II GX")
+ || (`XCVR_DEV_FAM == "Arria II GZ")
+ || (`XCVR_DEV_FAM == "HardCopy IV")
+ ) ? 1 : 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Match device family against standard family name strings
+ //
+ // Returns 1 if the names feature is present in the given device family
+ function integer has_s5_style_hssi (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ has_s5_style_hssi = ( (`XCVR_DEV_FAM == "Stratix V")
+ ) ? 1 : 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Match device family against standard family name strings
+ //
+ // Returns 1 if the names feature is present in the given device family
+ function integer has_a5_style_hssi (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ has_a5_style_hssi = ( (`XCVR_DEV_FAM == "Arria V")
+ ) ? 1 : 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Match device family against standard family name strings
+ //
+ // Returns 1 if the names feature is present in the given device family
+ function integer has_c5_style_hssi (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ has_c5_style_hssi = ( (`XCVR_DEV_FAM == "Cyclone V")
+ ) ? 1 : 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Match device family against standard family name strings
+ //
+ // Returns 1 if the names feature is present in the given device family
+ function integer has_c4_style_hssi (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ has_c4_style_hssi = ( (`XCVR_DEV_FAM == "Cyclone IV GX")
+ ) ? 1 : 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_to_gxb bundle width for specified device family
+ //
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_to_gxb bundle for that family
+ function integer get_reconfig_to_gxb_width (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family))
+ get_reconfig_to_gxb_width = W_S5_RECONFIG_BUNDLE_TO_XCVR;
+ else if (has_s4_style_hssi(device_family))
+ get_reconfig_to_gxb_width = W_S4_RECONFIG_BUNDLE_TO_XCVR;
+ else if (has_c4_style_hssi(device_family))
+ get_reconfig_to_gxb_width = W_C4_RECONFIG_BUNDLE_TO_XCVR;
+ else
+ get_reconfig_to_gxb_width = 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_from_gxb bundle width for specified device family
+ //
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_gxb bundle for that family
+ function integer get_reconfig_from_gxb_width (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family))
+ get_reconfig_from_gxb_width = W_S5_RECONFIG_BUNDLE_FROM_XCVR;
+ else if (has_s4_style_hssi(device_family))
+ get_reconfig_from_gxb_width = W_S4_RECONFIG_BUNDLE_FROM_XCVR;
+ else if (has_c4_style_hssi(device_family))
+ get_reconfig_from_gxb_width = W_C4_RECONFIG_BUNDLE_FROM_XCVR;
+ else
+ get_reconfig_from_gxb_width = 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_to_xcvr total port width for specified device family
+ //
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_to_xcvr port for that family
+ function integer get_reconfig_to_width (
+ input [MAX_CHARS*8-1:0] device_family,
+ input integer reconfig_interfaces
+ );
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family))
+ get_reconfig_to_width = get_s5_reconfig_to_width(reconfig_interfaces);
+ else if (has_s4_style_hssi(device_family))
+ get_reconfig_to_width = W_S4_RECONFIG_BUNDLE_TO_XCVR;
+ else if (has_c4_style_hssi(device_family))
+ get_reconfig_to_width = W_C4_RECONFIG_BUNDLE_TO_XCVR;
+ else
+ get_reconfig_to_width = 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_to_xcvr total port width for Stratix V device family
+ //
+ function integer get_s5_reconfig_to_width (
+ input integer reconfig_interfaces
+ );
+ get_s5_reconfig_to_width = reconfig_interfaces * get_reconfig_to_gxb_width("Stratix V");
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_from_xcvr total port width for specified device family
+ //
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_reconfig_from_width (
+ input [MAX_CHARS*8-1:0] device_family,
+ input integer reconfig_interfaces
+ );
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family))
+ get_reconfig_from_width = reconfig_interfaces * get_reconfig_from_gxb_width(device_family);
+ else if (has_s4_style_hssi(device_family))
+ get_reconfig_from_width = reconfig_interfaces * get_reconfig_from_gxb_width(device_family);
+ else if (has_c4_style_hssi(device_family))
+ get_reconfig_from_width = reconfig_interfaces * get_reconfig_from_gxb_width(device_family);
+ else
+ get_reconfig_from_width = 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_from_xcvr total port width for Stratix V device family
+ //
+ function integer get_s5_reconfig_from_width (
+ input integer reconfig_interfaces
+ );
+ get_s5_reconfig_from_width = reconfig_interfaces * get_reconfig_from_gxb_width("Stratix V");
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get number of reconfig interfaces for Custom PHY
+ // NOTE - !!Has since been used by other PHY IP!!
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // @param lanes - Number of channels
+ // @param plls - Number of TX plls (per channel)
+ // @param bonded_group_size - Size of bonded group (1 or lanes)
+ // @param data_path_type - Abuse of function by overloading for ATT support
+ // - Carry on the abuse
+ //
+ // @return 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_custom_reconfig_interfaces(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer lanes,
+ input integer plls,
+ input integer bonded_group_size,
+ input [MAX_CHARS*8-1:0] data_path_type = "",
+ input [MAX_CHARS*8-1:0] bonded_mode = "xN"
+ );
+ integer reconfig_interfaces;
+ reconfig_interfaces = 0;
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family)) begin
+ // ATT specific calculations
+ if( data_path_type == "ATT" ) begin
+ if((operation_mode == "RX_ONLY") || (operation_mode == "rx_only") || (operation_mode == "Rx") || (operation_mode == "RX") || (operation_mode == "rx")) begin
+ reconfig_interfaces = lanes;
+ end else if((operation_mode == "TX_ONLY") || (operation_mode == "tx_only") || (operation_mode == "Tx") || (operation_mode == "TX") || (operation_mode == "tx")) begin
+ reconfig_interfaces = 2*lanes;
+ end else begin
+ reconfig_interfaces = 3*lanes;
+ end
+ end else begin
+ // Custom PHY calculations
+ if((operation_mode == "RX") || (operation_mode == "Rx") || (operation_mode == "rx_only"))
+ reconfig_interfaces = lanes;
+ else begin
+ bonded_group_size = (bonded_mode == "fb_compensation") ? 1 : bonded_group_size;
+ reconfig_interfaces = lanes+(plls*(lanes/bonded_group_size));
+ end
+ end
+ end
+ get_custom_reconfig_interfaces = reconfig_interfaces;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_to_xcvr total port width for Custom PHY
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // @param lanes - Number of transceiver channels
+ // @param plls - Number of plls per bonded group
+ // @param bonded_group_size - Size of bonded group (1 or lanes)
+ // @param data_path_type - Abuse of function to support ATT
+ //
+ // @return - 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_custom_reconfig_to_width(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer lanes,
+ input integer plls,
+ input integer bonded_group_size,
+ input [MAX_CHARS*8-1:0] data_path_type = "",
+ input [MAX_CHARS*8-1:0] bonded_mode = "xN"
+ );
+ integer reconfig_interfaces;
+ reconfig_interfaces = get_custom_reconfig_interfaces(device_family,operation_mode,lanes,plls,bonded_group_size, data_path_type, bonded_mode );
+ get_custom_reconfig_to_width = get_s5_reconfig_to_width(reconfig_interfaces);
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_from_xcvr total port width for Custom PHY
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // @param lanes - Number of transceiver channels
+ // @param plls - Number of plls per bonded group
+ // @param bonded_group_size - Size of bonded group (1 or lanes)
+ // @param data_path_type - Abuse of function to support ATT
+ //
+ // @return - 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_custom_reconfig_from_width(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer lanes,
+ input integer plls,
+ input integer bonded_group_size,
+ input [MAX_CHARS*8-1:0] data_path_type = "",
+ input [MAX_CHARS*8-1:0] bonded_mode = "xN"
+ );
+ integer reconfig_interfaces;
+ reconfig_interfaces = get_custom_reconfig_interfaces(device_family,operation_mode,lanes,plls,bonded_group_size, data_path_type, bonded_mode);
+ get_custom_reconfig_from_width = get_s5_reconfig_from_width(reconfig_interfaces);
+ endfunction
+
+
+ ////////////////////////////////////////////////////////////////////
+ // Start Interlaken Specific functions for calculating reconfig interfaces
+ // and reconfig_to_gxb, reconfig_from_gxb widths
+
+ ////////////////////////////////////////////////////////////////////
+ // Get number of reconfig interfaces for Interlaken PHY
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_interlaken_reconfig_interfaces(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer bonded_group_size,
+ input integer lanes
+ );
+ integer reconfig_interfaces;
+ integer xslices;
+ integer xremain;
+ integer totalplls;
+
+ reconfig_interfaces = 0;
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family)) begin
+ if((operation_mode == "RX") || (operation_mode == "Rx") || (operation_mode == "rx_only"))
+ reconfig_interfaces = lanes;
+ else begin
+ xslices = lanes/bonded_group_size;
+ xremain = lanes % bonded_group_size;
+
+ if (xremain >0)
+ totalplls = xslices +1;
+ else
+ totalplls = xslices;
+ reconfig_interfaces = lanes+totalplls;
+ end // else: !if((operation_mode == "RX") || (operation_mode == "Rx") || (operation_mode == "rx_only"))
+ end // if (has_s5_style_hssi(device_family))
+ get_interlaken_reconfig_interfaces = reconfig_interfaces;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_to_xcvr total port width for Interlaken PHY
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // @param lanes - Number of transceiver channels
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_interlaken_reconfig_to_width(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer bonded_group_size,
+ input integer lanes
+ );
+ integer reconfig_interfaces;
+ reconfig_interfaces = get_interlaken_reconfig_interfaces(device_family,operation_mode,bonded_group_size,lanes);
+ get_interlaken_reconfig_to_width = get_s5_reconfig_to_width(reconfig_interfaces);
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_from_xcvr total port width for Custom PHY
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_interlaken_reconfig_from_width(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer bonded_group_size,
+ input integer lanes
+ );
+ integer reconfig_interfaces;
+ reconfig_interfaces = get_interlaken_reconfig_interfaces(device_family,operation_mode,bonded_group_size,lanes);
+ get_interlaken_reconfig_from_width = get_s5_reconfig_from_width(reconfig_interfaces);
+ endfunction
+
+ // End Interlaken specific functions
+ ////////////////////////////////////////////////////////////////////
+
+
+
+
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/altera_xcvr_xaui.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/altera_xcvr_xaui.sv
new file mode 100644
index 0000000000000000000000000000000000000000..f5731672ef25f5db829bfa5138a5ea5bee0aec5c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/altera_xcvr_xaui.sv
@@ -0,0 +1,510 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//-----------------------------------------------------------------------------
+//
+// Description: alt_xaui static verilog top level
+//
+// Authors: bauyeung 7-Sep-2010
+// Modified: ishimony 13-Dec-2010
+//
+// Copyright (c) Altera Corporation 1997 - 2010
+// All rights reserved.
+//
+//
+//-----------------------------------------------------------------------------
+
+// have separate generate statements for each component
+
+`timescale 1 ps / 1 ps
+import altera_xcvr_functions::*;
+(* altera_attribute = "-name IP_TOOL_NAME __ACDS_IP_CORE_NAME__; -name IP_TOOL_VERSION __ACDS_VERSION_SHORT__" *)
+module altera_xcvr_xaui #(
+ parameter device_family = "Stratix IV", // default Stratix IV
+ parameter starting_channel_number = 0, // only applies to SIV
+ parameter interface_type = "Hard XAUI",
+ parameter data_rate = "3125 Mbps",
+ parameter xaui_pll_type = "CMU",
+ parameter BASE_DATA_RATE = "3125 Mbps",
+ parameter use_control_and_status_ports = 0,
+ parameter external_pma_ctrl_reconf = 0,
+ parameter recovered_clk_out = 0,
+ parameter number_of_interfaces = 1,
+ parameter reconfig_interfaces = 1,
+ parameter use_rx_rate_match = 0,
+ parameter tx_termination = "OCT_150_OHMS",
+ parameter tx_vod_selection = 1,
+ parameter tx_preemp_pretap = 0,
+ parameter tx_preemp_pretap_inv = 0,
+ parameter tx_preemp_tap_1 = 5,
+ parameter tx_preemp_tap_2 = 0,
+ parameter tx_preemp_tap_2_inv = 0,
+ parameter rx_common_mode = "0.82v",
+ parameter rx_termination = "OCT_150_OHMS",
+ parameter rx_eq_dc_gain = 0,
+ parameter rx_eq_ctrl = 14,
+ parameter mgmt_clk_in_mhz = 50
+) (
+ input wire pll_ref_clk,
+ input wire xgmii_tx_clk,
+ output wire xgmii_rx_clk,
+ output wire tx_clk312_5, // dxaui: pma tx out clock, 312.5Mhz
+ input wire phy_mgmt_clk,
+ input wire phy_mgmt_clk_reset,
+ input wire [8:0] phy_mgmt_address,
+ output wire phy_mgmt_waitrequest,
+ input wire phy_mgmt_read,
+ output wire [31:0] phy_mgmt_readdata,
+ input wire phy_mgmt_write,
+ input wire [31:0] phy_mgmt_writedata,
+ input wire [71:0] xgmii_tx_dc,
+ output wire [71:0] xgmii_rx_dc,
+ output wire [3:0] xaui_tx_serial_data,
+ input wire [3:0] xaui_rx_serial_data,
+ output wire rx_ready,
+ output wire tx_ready,
+ output wire [3:0] rx_recovered_clk, // rx recovered clock from cdr
+
+// only used if use_control_and_status_ports is set
+ input tri0 rx_analogreset,
+ input tri0 rx_digitalreset,
+ input tri0 tx_digitalreset,
+ output tri0 rx_channelaligned,
+ input tri0 [3:0] rx_invpolarity,
+ input tri0 [3:0] rx_set_locktodata,
+ input tri0 [3:0] rx_set_locktoref,
+ input tri0 [3:0] rx_seriallpbken,
+ input tri0 [3:0] tx_invpolarity,
+ output tri1 [3:0] rx_is_lockedtodata,
+ output tri0 [3:0] rx_phase_comp_fifo_error,
+ output tri1 [3:0] rx_is_lockedtoref,
+ output tri0 [3:0] rx_rlv,
+ output tri0 [3:0] rx_rmfifoempty,
+ output tri0 [3:0] rx_rmfifofull,
+ output tri0 [3:0] tx_phase_comp_fifo_error,
+ output tri0 [7:0] rx_disperr,
+ output tri0 [7:0] rx_errdetect,
+ output tri0 [7:0] rx_patterndetect,
+ output tri0 [7:0] rx_rmfifodatadeleted,
+ output tri0 [7:0] rx_rmfifodatainserted,
+ output tri0 [7:0] rx_runningdisp,
+ output tri0 [7:0] rx_syncstatus,
+
+
+// only used if external_pma_ctrl_reconf is set
+ output tri0 [altera_xcvr_functions::get_reconfig_from_width(device_family,reconfig_interfaces)-1:0] reconfig_from_xcvr,
+ input tri0 [altera_xcvr_functions::get_reconfig_to_width(device_family,reconfig_interfaces) -1:0] reconfig_to_xcvr,
+ output tri0 pll_locked,
+ input tri0 cal_blk_powerdown,
+ input tri0 gxb_powerdown,
+ input tri0 pll_powerdown
+// need to add all possible port/param combinations
+// these should be set to tri0/1 where possible, so unused ports don't need to be terminated by the user
+);
+
+import altera_xcvr_functions::*;
+
+localparam reconfig_out_width = altera_xcvr_functions::get_reconfig_from_width(device_family,reconfig_interfaces);
+localparam reconfig_in_width = altera_xcvr_functions::get_reconfig_to_width(device_family,reconfig_interfaces);
+
+ wire [reconfig_out_width -1:0] l_reconfig_from_xcvr; // local reconfig_from_xcvr
+ wire [reconfig_in_width -1:0] l_reconfig_to_xcvr; // local reconfig_to_xcvr
+
+ wire [7:0] sc_phy_address; // mgmt.address
+ wire sc_phy_waitrequest; // .waitrequest
+ wire sc_phy_read; // .read
+ wire [31:0] sc_phy_readdata; // .readdata
+ wire sc_phy_write; // .write
+
+ wire [6:0] sc_reconf_address; // mgmt.address
+ wire sc_reconf_waitrequest; // .waitrequest
+ wire sc_reconf_read; // .read
+ wire [31:0] sc_reconf_readdata; // .readdata
+ wire sc_reconf_write; // .write
+
+///////////////////////////////////////////////////////////////////////
+// Custom decoder for multiple slaves of phy-reconfig interface
+///////////////////////////////////////////////////////////////////////
+// should be consistent across all device families
+ alt_xcvr_mgmt2dec_phyreconfig mgmtdec_phyreconfig (
+ .mgmt_clk_reset (phy_mgmt_clk_reset),
+ .mgmt_clk (phy_mgmt_clk),
+
+ .mgmt_address (phy_mgmt_address),
+ .mgmt_read (phy_mgmt_read),
+ .mgmt_write (phy_mgmt_write),
+ .mgmt_readdata (phy_mgmt_readdata),
+ .mgmt_waitrequest (phy_mgmt_waitrequest),
+
+ // internal interface to 'top' phy block
+ .sc_phy_readdata (sc_phy_readdata),
+ .sc_phy_waitrequest (sc_phy_waitrequest),
+ .sc_phy_address (sc_phy_address),
+ .sc_phy_read (sc_phy_read),
+ .sc_phy_write (sc_phy_write),
+
+ // internal interface to 'top' reconfig block
+ .sc_reconf_readdata (sc_reconf_readdata),
+ .sc_reconf_waitrequest (sc_reconf_waitrequest),
+ .sc_reconf_address (sc_reconf_address),
+ .sc_reconf_read (sc_reconf_read),
+ .sc_reconf_write (sc_reconf_write)
+ );
+
+
+///////////////////////////////////////////////////////////////////////
+// alt_xcvr_reconfig
+///////////////////////////////////////////////////////////////////////
+// add generate statement for this
+// need to account for external pma reconfig
+ generate
+ if (external_pma_ctrl_reconf == 1) begin
+ assign l_reconfig_to_xcvr = reconfig_to_xcvr;
+ assign reconfig_from_xcvr = l_reconfig_from_xcvr;
+ end else if ((interface_type == "Hard XAUI") && ((device_family == "Stratix IV") || (device_family == "HardCopy IV") || (device_family == "Arria II GX") || (device_family == "Arria II GX") || (device_family == "Arria II GZ"))) begin
+ alt_xcvr_reconfig_siv #(
+ .number_of_reconfig_interfaces (1)
+ ) alt_xcvr_reconfig_0 (
+ .mgmt_clk_clk (phy_mgmt_clk),
+ .mgmt_rst_reset (phy_mgmt_clk_reset),
+ .reconfig_mgmt_address (sc_reconf_address),
+ .reconfig_mgmt_waitrequest (sc_reconf_waitrequest),
+ .reconfig_mgmt_read (sc_reconf_read),
+ .reconfig_mgmt_readdata (sc_reconf_readdata),
+ .reconfig_mgmt_write (sc_reconf_write),
+ .reconfig_mgmt_writedata (phy_mgmt_writedata),
+ .reconfig_togxb (l_reconfig_to_xcvr),
+ .reconfig_fromgxb (l_reconfig_from_xcvr[16:0])
+ );
+ end else if ((interface_type == "Soft XAUI") && ((device_family == "Stratix IV") || (device_family == "HardCopy IV"))) begin // Arria II GX/GZ don't support soft xaui
+ alt_xcvr_reconfig_siv #(
+ .number_of_reconfig_interfaces (4)
+ ) alt_xcvr_reconfig_0 (
+ .mgmt_clk_clk (phy_mgmt_clk),
+ .mgmt_rst_reset (phy_mgmt_clk_reset),
+ .reconfig_mgmt_address (sc_reconf_address),
+ .reconfig_mgmt_waitrequest (sc_reconf_waitrequest),
+ .reconfig_mgmt_read (sc_reconf_read),
+ .reconfig_mgmt_readdata (sc_reconf_readdata),
+ .reconfig_mgmt_write (sc_reconf_write),
+ .reconfig_mgmt_writedata (phy_mgmt_writedata),
+ .reconfig_togxb (l_reconfig_to_xcvr),
+ .reconfig_fromgxb (l_reconfig_from_xcvr)
+ );
+ end else if ((interface_type == "DDR XAUI") && (device_family == "Stratix IV")) begin
+ // stub for now - nothing here
+ end else if (device_family == "Stratix V") begin
+ // stub for now - nothing here
+ assign l_reconfig_to_xcvr = reconfig_to_xcvr;
+ assign reconfig_from_xcvr = l_reconfig_from_xcvr;
+ end else if (device_family == "Cyclone IV GX") begin
+ alt_xcvr_reconfig_civ #(
+ .number_of_reconfig_interfaces (1)
+ ) alt_xcvr_reconfig_0 (
+ .reconfig_mgmt_clk_clk (phy_mgmt_clk),
+ .reconfig_mgmt_rst_reset (phy_mgmt_clk_reset),
+ .reconfig_mgmt_address (sc_reconf_address),
+ .reconfig_mgmt_waitrequest (sc_reconf_waitrequest),
+ .reconfig_mgmt_read (sc_reconf_read),
+ .reconfig_mgmt_readdata (sc_reconf_readdata),
+ .reconfig_mgmt_write (sc_reconf_write),
+ .reconfig_mgmt_writedata (phy_mgmt_writedata),
+ .reconfig_togxb (l_reconfig_to_xcvr),
+ .reconfig_fromgxb (l_reconfig_from_xcvr[16:0])
+ );
+ end
+ endgenerate
+
+///////////////////////////////////////////////////////////////////////
+// alt_xaui_phy - Integrates hxaui (i/f to hxaui_alt_c3gxb), csr, pma
+// controller and pma channel controller
+///////////////////////////////////////////////////////////////////////
+ generate
+ if (device_family == "Stratix V") begin
+ sv_xcvr_xaui #(
+ .device_family (device_family),
+ .starting_channel_number (starting_channel_number),
+ .interface_type (interface_type),
+ .reconfig_interfaces (reconfig_interfaces),
+ .sys_clk_in_mhz (mgmt_clk_in_mhz),
+ .data_rate (data_rate),
+ .xaui_pll_type (xaui_pll_type),
+ .BASE_DATA_RATE (BASE_DATA_RATE),
+ .use_control_and_status_ports (use_control_and_status_ports),
+ .tx_termination (tx_termination),
+ .rx_termination (rx_termination),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv (tx_preemp_pretap_inv),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv (tx_preemp_tap_2_inv),
+ .tx_vod_selection (tx_vod_selection),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .rx_common_mode (rx_common_mode),
+ .bonded_group_size (4), /// allowed values 1=> non-bonded 4=> bonded
+ .bonded_mode ("xN") /// allowed values "xN" and "fb_compensation"
+ ) alt_xaui_phy (
+ .pll_ref_clk (pll_ref_clk), // refclk.clk
+ .xgmii_tx_clk (xgmii_tx_clk), // xgmii_tx_clk.clk
+ .xgmii_rx_clk (xgmii_rx_clk), // xgmii_rx_clk.clk
+ .phy_mgmt_clk (phy_mgmt_clk), // mgmt_clk.clk
+ .phy_mgmt_clk_reset (phy_mgmt_clk_reset), // mgmt_clk_rst.reset_n
+ .phy_mgmt_address (sc_phy_address), // phy_mgmt.address
+ .phy_mgmt_waitrequest (sc_phy_waitrequest), // .waitrequest
+ .phy_mgmt_read (sc_phy_read), // .read
+ .phy_mgmt_readdata (sc_phy_readdata), // .readdata
+ .phy_mgmt_write (sc_phy_write), // .write
+ .phy_mgmt_writedata (phy_mgmt_writedata), // .writedata
+ .xgmii_tx_dc (xgmii_tx_dc), // xgmii_tx_dc.data
+ .xgmii_rx_dc (xgmii_rx_dc), // xgmii_rx_dc.data
+ .xaui_tx_serial_data (xaui_tx_serial_data), // xaui_tx_serial.export
+ .xaui_rx_serial_data (xaui_rx_serial_data), // xaui_rx_serial.export
+ .rx_digitalreset (rx_digitalreset), // rx_digitalreset.data
+ .tx_digitalreset (tx_digitalreset), // tx_digitalreset.data
+ .rx_channelaligned (rx_channelaligned), // rx_channelaligned.data
+ .rx_syncstatus (rx_syncstatus), // rx_syncstatus.data
+ .rx_disperr (rx_disperr), // rx_disperr.data
+ .rx_errdetect (rx_errdetect), // rx_errdetect.data
+ .rx_ready (rx_ready), // rx_pma_ready.data
+ .tx_ready (tx_ready), // tx_pma_ready.data
+ .reconfig_to_xcvr (l_reconfig_to_xcvr),
+ .reconfig_from_xcvr (l_reconfig_from_xcvr),
+ .rx_recovered_clk (rx_recovered_clk)
+ );
+ end else if ((interface_type == "DDR XAUI") && (device_family == "Stratix IV")) begin
+ dxaui_siv #(
+ .device_family (device_family),
+ .starting_channel_number (starting_channel_number),
+ .interface_type (interface_type),
+ .number_of_interfaces (1),
+ .reconfig_interfaces (reconfig_interfaces),
+ .sys_clk_in_mhz (mgmt_clk_in_mhz),
+ .xaui_pll_type (xaui_pll_type),
+ .use_control_and_status_ports (use_control_and_status_ports),
+ .external_pma_ctrl_reconf (external_pma_ctrl_reconf),
+ .tx_termination (tx_termination),
+ .tx_vod_selection (tx_vod_selection),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv (tx_preemp_pretap_inv),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv (tx_preemp_tap_2_inv),
+ .rx_common_mode (rx_common_mode),
+ .rx_termination (rx_termination),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .use_rx_rate_match (use_rx_rate_match)
+) dxaui_siv (
+ .pll_ref_clk (pll_ref_clk), // i
+ .xgmii_tx_clk (xgmii_tx_clk), // i
+ .xgmii_rx_clk (xgmii_rx_clk), // o
+ .tx_clk312_5 (tx_clk312_5), // o
+ .phy_mgmt_clk (phy_mgmt_clk), // i
+ .phy_mgmt_clk_reset (phy_mgmt_clk_reset), // i
+ .phy_mgmt_address (sc_phy_address), // i
+ .phy_mgmt_waitrequest (sc_phy_waitrequest), // o
+ .phy_mgmt_read (sc_phy_read), // i
+ .phy_mgmt_readdata (sc_phy_readdata), // o
+ .phy_mgmt_write (sc_phy_write), // i
+ .phy_mgmt_writedata (phy_mgmt_writedata), // i
+ .xgmii_tx_dc (xgmii_tx_dc), // i
+ .xgmii_rx_dc (xgmii_rx_dc), // o
+ .xaui_tx_serial_data (xaui_tx_serial_data), // o
+ .xaui_rx_serial_data (xaui_rx_serial_data), // i
+ .rx_ready (rx_ready), // o
+ .tx_ready (tx_ready), // o
+ .rx_recovered_clk (rx_recovered_clk), // o
+ .reconfig_from_xcvr (l_reconfig_from_xcvr), // o
+ .reconfig_to_xcvr (l_reconfig_to_xcvr), // i
+ .rx_analogreset (rx_analogreset), // i
+ .rx_digitalreset (rx_digitalreset), // i
+ .tx_digitalreset (tx_digitalreset), // i
+ .rx_channelaligned (rx_channelaligned), // o
+ .rx_invpolarity (rx_invpolarity), // i
+ .rx_set_locktodata (rx_set_locktodata), // i
+ .rx_set_locktoref (rx_set_locktoref), // i
+ .rx_seriallpbken (rx_seriallpbken), // i
+ .tx_invpolarity (tx_invpolarity), // i
+ .rx_is_lockedtodata (rx_is_lockedtodata), // o
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error), // o
+ .rx_is_lockedtoref (rx_is_lockedtoref), // o
+ .rx_rlv (rx_rlv), // o
+ .rx_rmfifoempty (rx_rmfifoempty), // o
+ .rx_rmfifofull (rx_rmfifofull), // o
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error), // o
+ .rx_disperr (rx_disperr), // o
+ .rx_errdetect (rx_errdetect), // o
+ .rx_patterndetect (rx_patterndetect), // o
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted), // o
+ .rx_rmfifodatainserted (rx_rmfifodatainserted), // o
+ .rx_runningdisp (rx_runningdisp), // o
+ .rx_syncstatus (rx_syncstatus), // o
+ .pll_locked (pll_locked), // o
+ .cal_blk_powerdown (cal_blk_powerdown), // i
+ .gxb_powerdown (gxb_powerdown), // i
+ .pll_powerdown (pll_powerdown) // i
+); // module dxaui_siv
+ end else if ((device_family == "Stratix IV") || (device_family == "HardCopy IV") ||(device_family == "Arria II GX") || (device_family == "Arria II GZ")) begin
+ siv_xcvr_xaui #(
+ .device_family (device_family),
+ .starting_channel_number (starting_channel_number),
+ .interface_type (interface_type),
+ .number_of_interfaces (1),
+ .reconfig_interfaces (reconfig_interfaces),
+ .sys_clk_in_mhz (mgmt_clk_in_mhz),
+ .xaui_pll_type (xaui_pll_type),
+ .use_control_and_status_ports (use_control_and_status_ports),
+ .external_pma_ctrl_reconf (external_pma_ctrl_reconf),
+ .tx_termination (tx_termination),
+ .rx_termination (rx_termination),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv (tx_preemp_pretap_inv),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv (tx_preemp_tap_2_inv),
+ .tx_vod_selection (tx_vod_selection),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .rx_common_mode (rx_common_mode)
+ ) xaui_phy (
+ .pll_ref_clk (pll_ref_clk),
+ .xgmii_rx_clk (xgmii_rx_clk),
+ .xgmii_tx_clk (xgmii_tx_clk),
+ .phy_mgmt_clk (phy_mgmt_clk),
+ .phy_mgmt_clk_reset (phy_mgmt_clk_reset),
+ .phy_mgmt_address (sc_phy_address),
+ .phy_mgmt_read (sc_phy_read),
+ .phy_mgmt_readdata (sc_phy_readdata),
+ .phy_mgmt_waitrequest (sc_phy_waitrequest),
+ .phy_mgmt_write (sc_phy_write),
+ .phy_mgmt_writedata (phy_mgmt_writedata),
+ .xaui_rx_serial_data (xaui_rx_serial_data),
+ .xaui_tx_serial_data (xaui_tx_serial_data),
+ .xgmii_rx_dc (xgmii_rx_dc),
+ .xgmii_tx_dc (xgmii_tx_dc),
+ .rx_ready (rx_ready),
+ .tx_ready (tx_ready),
+ .rx_recovered_clk (rx_recovered_clk), //o
+ .reconfig_from_xcvr (l_reconfig_from_xcvr),
+ .reconfig_to_xcvr (l_reconfig_to_xcvr),
+
+// optional control and status ports - will be terminated by tri0 if unconnected
+ .rx_analogreset (rx_analogreset), // input wire
+ .rx_digitalreset (rx_digitalreset), // input wire [3:0]
+ .tx_digitalreset (tx_digitalreset), // input wire [3:0]
+ .rx_channelaligned (rx_channelaligned), // output wire
+ .rx_invpolarity (rx_invpolarity), // input wire [3:0]
+ .rx_set_locktodata (rx_set_locktodata), // input wire [3:0]
+ .rx_set_locktoref (rx_set_locktoref), // input wire [3:0]
+ .rx_seriallpbken (rx_seriallpbken), // input wire [3:0]
+ .tx_invpolarity (tx_invpolarity), // input wire [3:0]
+ .rx_is_lockedtodata (rx_is_lockedtodata), // output wire [3:0]
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error), // output wire [3:0]
+ .rx_is_lockedtoref (rx_is_lockedtoref), // output wire [3:0]
+ .rx_rlv (rx_rlv), // output wire [3:0]
+ .rx_rmfifoempty (rx_rmfifoempty), // output wire [3:0]
+ .rx_rmfifofull (rx_rmfifofull), // output wire [3:0]
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error), // output wire [3:0]
+ .rx_disperr (rx_disperr), // output wire [7:0]
+ .rx_errdetect (rx_errdetect), // output wire [7:0]
+ .rx_patterndetect (rx_patterndetect), // output wire [7:0]
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted), // output wire [7:0]
+ .rx_rmfifodatainserted (rx_rmfifodatainserted), // output wire [7:0]
+ .rx_runningdisp (rx_runningdisp), // output wire [7:0]
+ .rx_syncstatus (rx_syncstatus), // output wire [7:0]
+
+// external_pma_ctrl_reconf
+ .pll_locked (pll_locked), // output wire
+ .cal_blk_powerdown (cal_blk_powerdown), // input wire
+ .gxb_powerdown (gxb_powerdown), // input wire
+ .pll_powerdown (pll_powerdown) // input wire
+ );
+ end else if (device_family == "Cyclone IV GX") begin
+// need to add the extra optional ports for c&s and ext_pma
+ civ_xcvr_xaui #(
+ .device_family (device_family),
+ .starting_channel_number (starting_channel_number),
+ .interface_type (interface_type),
+ .number_of_interfaces (1),
+ .sys_clk_in_mhz (mgmt_clk_in_mhz),
+ .xaui_pll_type (xaui_pll_type),
+ .use_control_and_status_ports (use_control_and_status_ports),
+ .tx_termination (tx_termination),
+ .rx_termination (rx_termination),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv (tx_preemp_pretap_inv),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv (tx_preemp_tap_2_inv),
+ .tx_vod_selection (tx_vod_selection),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .rx_common_mode (rx_common_mode)
+ ) xaui_phy (
+ .pll_ref_clk (pll_ref_clk),
+ .xgmii_rx_clk (xgmii_rx_clk),
+ .xgmii_tx_clk (xgmii_tx_clk),
+ .phy_mgmt_clk (phy_mgmt_clk),
+ .phy_mgmt_clk_reset (phy_mgmt_clk_reset),
+ .phy_mgmt_address (sc_phy_address),
+ .phy_mgmt_read (sc_phy_read),
+ .phy_mgmt_readdata (sc_phy_readdata),
+ .phy_mgmt_waitrequest (sc_phy_waitrequest),
+ .phy_mgmt_write (sc_phy_write),
+ .phy_mgmt_writedata (phy_mgmt_writedata),
+ .xaui_rx_serial_data (xaui_rx_serial_data),
+ .xaui_tx_serial_data (xaui_tx_serial_data),
+ .xgmii_rx_dc (xgmii_rx_dc),
+ .xgmii_tx_dc (xgmii_tx_dc),
+ .rx_ready (rx_ready),
+ .tx_ready (tx_ready),
+ .rx_recovered_clk (rx_recovered_clk), //o
+ .reconfig_from_xcvr (l_reconfig_from_xcvr[16:0]),
+ .reconfig_to_xcvr (l_reconfig_to_xcvr),
+
+// optional control and status ports - will be terminated by tri0 if unconnected
+ .rx_analogreset (rx_analogreset), // input wire
+ .rx_digitalreset (rx_digitalreset), // input wire [3:0]
+ .tx_digitalreset (tx_digitalreset), // input wire [3:0]
+ .rx_channelaligned (rx_channelaligned), // output wire
+ .rx_invpolarity (rx_invpolarity), // input wire [3:0]
+ .rx_set_locktodata (rx_set_locktodata), // input wire [3:0]
+ .rx_set_locktoref (rx_set_locktoref), // input wire [3:0]
+ .rx_seriallpbken (rx_seriallpbken), // input wire [3:0]
+ .tx_invpolarity (tx_invpolarity), // input wire [3:0]
+ .rx_is_lockedtodata (rx_is_lockedtodata), // output wire [3:0]
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error), // output wire [3:0]
+ .rx_is_lockedtoref (rx_is_lockedtoref), // output wire [3:0]
+ .rx_rlv (rx_rlv), // output wire [3:0]
+ .rx_rmfifoempty (rx_rmfifoempty), // output wire [3:0]
+ .rx_rmfifofull (rx_rmfifofull), // output wire [3:0]
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error), // output wire [3:0]
+ .rx_disperr (rx_disperr), // output wire [7:0]
+ .rx_errdetect (rx_errdetect), // output wire [7:0]
+ .rx_patterndetect (rx_patterndetect), // output wire [7:0]
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted), // output wire [7:0]
+ .rx_rmfifodatainserted (rx_rmfifodatainserted), // output wire [7:0]
+ .rx_runningdisp (rx_runningdisp), // output wire [7:0]
+ .rx_syncstatus (rx_syncstatus), // output wire [7:0]
+
+// external_pma_ctrl_reconf
+ .pll_locked (pll_locked), // output wire
+ .cal_blk_powerdown (cal_blk_powerdown), // input wire
+ .gxb_powerdown (gxb_powerdown), // input wire
+ .pll_powerdown (pll_powerdown) // input wire
+ );
+ end
+ endgenerate
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/hxaui_csr.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/hxaui_csr.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5ad633285f019d30350c678e518974f6621093e3
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/hxaui_csr.sv
@@ -0,0 +1,415 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// (C) 2001-2010 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+///////////////////////////////////////////////////////////////////////////////
+//
+//
+// Description: Hard xaui control and status registers
+//
+// Authors: ishimony 12-Jun-2009
+//
+// Copyright (c) Altera Corporation 1997 - 2009
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+//
+// TBD: unless synthesis is smart enough all synchronization flops will have
+// to be manually instantiated (altera_std_synchronizer)
+//
+
+`timescale 1 ps / 1 ps
+
+module hxaui_csr(
+ clk, reset, address, byteenable, read, readdata, write, writedata,
+ rx_patterndetect, rx_syncstatus, rx_runningdisp, rx_errdetect,
+ rx_disperr, rx_phase_comp_fifo_error, rx_rlv, rx_rmfifodatadeleted,
+ rx_rmfifodatainserted, rx_rmfifoempty, rx_rmfifofull,
+ tx_phase_comp_fifo_error, r_rx_invpolarity, r_tx_invpolarity,
+ r_rx_digitalreset, r_tx_digitalreset, simulation_flag
+); // module hxaui_csr
+import hxaui_csr_h::*;
+
+// ports -------------------------------------------------------------------
+
+// Avalon MM slave
+input clk;
+input reset;
+
+input [4:0] address;
+input [3:0] byteenable;
+
+input read;
+output [31:0] readdata;
+
+input write;
+input [31:0] writedata;
+
+// hard xaui control/status
+input [7:0] rx_patterndetect;
+input [7:0] rx_syncstatus;
+input [7:0] rx_runningdisp; // nc
+
+input [7:0] rx_errdetect;
+input [7:0] rx_disperr;
+
+input [3:0] rx_phase_comp_fifo_error;
+input [3:0] rx_rlv;
+
+input [7:0] rx_rmfifodatadeleted;
+input [7:0] rx_rmfifodatainserted;
+input [3:0] rx_rmfifoempty;
+input [3:0] rx_rmfifofull;
+
+input [3:0] tx_phase_comp_fifo_error;
+
+output [3:0] r_rx_invpolarity;
+output [3:0] r_tx_invpolarity;
+output r_rx_digitalreset;
+output r_tx_digitalreset;
+
+output simulation_flag; // '1' shortens reset and loss_timer length
+
+// ports -------------------------------------------------------------------
+wire clk;
+wire reset;
+wire [4:0] address;
+wire [6:0] addr;
+wire [3:0] byteenable;
+wire read;
+reg [31:0] readdata;
+wire write;
+wire [31:0] writedata;
+wire [3:0] rx_phase_comp_fifo_error;
+wire [3:0] rx_rlv;
+wire [3:0] rx_rmfifoempty;
+wire [3:0] rx_rmfifofull;
+wire [3:0] tx_phase_comp_fifo_error;
+wire [7:0] rx_disperr;
+wire [7:0] rx_errdetect;
+wire [7:0] rx_patterndetect;
+wire [7:0] rx_rmfifodatadeleted;
+wire [7:0] rx_rmfifodatainserted;
+wire [7:0] rx_runningdisp;
+wire [7:0] rx_syncstatus;
+wire [3:0] r_rx_invpolarity;
+wire [3:0] r_tx_invpolarity;
+wire r_rx_digitalreset;
+wire r_tx_digitalreset;
+wire simulation_flag;
+
+// locals ------------------------------------------------------------------
+reg [1:0] hxaui_csr_reset, hxaui_csr_reset0q;
+reg [3:0] hxaui_csr_rx_cntrl, hxaui_csr_rx_cntrl0q;
+reg [3:0] hxaui_csr_tx_cntrl, hxaui_csr_tx_cntrl0q;
+wire [31:0] hxaui_csr_rx_status_0;
+wire [31:0] hxaui_csr_rx_status_1;
+wire [31:0] hxaui_csr_rx_status_2;
+wire [31:0] hxaui_csr_rx_status_3;
+wire [31:0] hxaui_csr_rx_status_4;
+wire [31:0] hxaui_csr_tx_status_0;
+reg hxaui_csr_simulation_flag, hxaui_csr_simulation_flag0q;
+
+
+reg [7:0] rx_patterndetect_c; // rx_patterndetect synced to clk
+reg [7:0] rx_syncstatus_c; // rx_syncstatus synced to clk
+reg [7:0] rx_patterndetect_sr; // rx_patterndetect sr ff
+reg [7:0] rx_syncstatus_sr; // rx_syncstatus sr ff
+wire read_rx_status_0;
+
+reg [7:0] rx_errdetect_c; // rx_errdetect synced to clk
+reg [7:0] rx_disperr_c; // rx_disperr synced to clk
+reg [7:0] rx_errdetect_sr; // rx_errdetect sr ff
+reg [7:0] rx_disperr_sr; // rx_disperr sr ff
+wire read_rx_status_1;
+
+reg [3:0] rx_phase_comp_fifo_error_c; // rx_phase_comp_fifo_error synced
+reg [3:0] rx_rlv_c; // rx_rlv synced to clk
+reg [3:0] rx_phase_comp_fifo_error_sr; // rx_phase_comp_fifo_error sr ff
+reg [3:0] rx_rlv_sr; // rx_rlv sr ff
+wire read_rx_status_2;
+
+reg [7:0] rx_rmfifodatainserted_c; // rx_rmfifodatainserted synced to clk
+reg [7:0] rx_rmfifodatadeleted_c; // rx_rmfifodatadeleted synced to clk
+reg [7:0] rx_rmfifodatainserted_sr;// rx_rmfifodatainserted sr ff
+reg [7:0] rx_rmfifodatadeleted_sr; // rx_rmfifodatadeleted sr ff
+wire read_rx_status_3;
+
+reg [3:0] rx_rmfifofull_c; // rx_rmfifo_full synced
+reg [3:0] rx_rmfifoempty_c; // rx_rmfifoempty synced to clk
+reg [3:0] rx_rmfifofull_sr; // rx_rmfifo_full sr ff
+reg [3:0] rx_rmfifoempty_sr; // rx_rmfifoempty sr ff
+wire read_rx_status_4;
+
+wire read_rx_status_5;
+
+reg [3:0] tx_phase_comp_fifo_error_c; // tx_phase_comp_fifo_error synced
+reg [3:0] tx_phase_comp_fifo_error_sr; // tx_phase_comp_fifo_error sr ff
+wire read_tx_status_0;
+
+// body --------------------------------------------------------------------
+
+//--- readdata output latch ---
+// For easier address debug shift back 2 bits
+assign addr = {address[4:0], 2'b00};
+
+always @(*) begin
+ case (addr)
+ HXAUI_CSR_RESET_ADDR:
+ readdata <= hxaui_csr_reset0q;
+ HXAUI_CSR_RX_CNTRL_ADDR:
+ readdata <= hxaui_csr_rx_cntrl0q;
+ HXAUI_CSR_TX_CNTRL_ADDR:
+ readdata <= hxaui_csr_tx_cntrl0q;
+ HXAUI_CSR_RX_STATUS_0_ADDR:
+ readdata <= hxaui_csr_rx_status_0;
+ HXAUI_CSR_RX_STATUS_1_ADDR:
+ readdata <= hxaui_csr_rx_status_1;
+ HXAUI_CSR_RX_STATUS_2_ADDR:
+ readdata <= hxaui_csr_rx_status_2;
+ HXAUI_CSR_RX_STATUS_3_ADDR:
+ readdata <= hxaui_csr_rx_status_3;
+ HXAUI_CSR_RX_STATUS_4_ADDR:
+ readdata <= hxaui_csr_rx_status_4;
+ HXAUI_CSR_TX_STATUS_0_ADDR:
+ readdata <= hxaui_csr_tx_status_0;
+ HXAUI_CSR_SIMULATION_FLAG_ADDR:
+ readdata <= hxaui_csr_simulation_flag0q;
+ default:
+ readdata <= 32'h0;
+ endcase // case (addr)
+end
+
+always @ (posedge clk or posedge reset) begin
+ if (reset) begin
+ hxaui_csr_reset0q <= 2'b0;
+ hxaui_csr_rx_cntrl0q <= 4'b0;
+ hxaui_csr_tx_cntrl0q <= 4'b0;
+ hxaui_csr_simulation_flag0q <= 1'b0;
+ end else begin
+ hxaui_csr_reset0q <= hxaui_csr_reset;
+ hxaui_csr_rx_cntrl0q <= hxaui_csr_rx_cntrl;
+ hxaui_csr_tx_cntrl0q <= hxaui_csr_tx_cntrl;
+ hxaui_csr_simulation_flag0q <= hxaui_csr_simulation_flag;
+ end
+end
+
+
+always @ (*) begin
+ hxaui_csr_reset = hxaui_csr_reset0q;
+ hxaui_csr_rx_cntrl = hxaui_csr_rx_cntrl0q;
+ hxaui_csr_tx_cntrl = hxaui_csr_tx_cntrl0q;
+ hxaui_csr_simulation_flag = hxaui_csr_simulation_flag0q;
+ if (write) begin
+ case (addr)
+ HXAUI_CSR_RESET_ADDR:
+ hxaui_csr_reset = writedata[1:0];
+ HXAUI_CSR_RX_CNTRL_ADDR:
+ hxaui_csr_rx_cntrl = writedata[3:0];
+ HXAUI_CSR_TX_CNTRL_ADDR:
+ hxaui_csr_tx_cntrl = writedata[3:0];
+ HXAUI_CSR_SIMULATION_FLAG_ADDR:
+ hxaui_csr_simulation_flag = writedata[0];
+ default:;
+ endcase // case (addr)
+ end
+end
+
+assign {r_rx_digitalreset, r_tx_digitalreset} = hxaui_csr_reset0q[1:0];
+assign r_rx_invpolarity[3:0] = hxaui_csr_rx_cntrl0q[3:0];
+assign r_tx_invpolarity[3:0] = hxaui_csr_tx_cntrl0q[3:0];
+assign simulation_flag = hxaui_csr_simulation_flag0q;
+
+//--- rx_status_0 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ rx_patterndetect_c <= rx_patterndetect;
+ rx_syncstatus_c <= rx_syncstatus;
+end
+
+assign read_rx_status_0 = read && (addr == HXAUI_CSR_RX_STATUS_0_ADDR);
+
+// sticky bits implementation -
+// set: status signal
+// reset: read from register
+// Set has precedence over reset
+//
+// s r q nq
+// ------------
+// 0 0 x q
+// 0 1 x 0
+// 1 x x 1
+//
+// nq <= s + qr'
+//
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ rx_patterndetect_sr <= 8'h0;
+ rx_syncstatus_sr <= 8'h0;
+ end else begin
+ rx_patterndetect_sr <= rx_patterndetect_c |
+ (rx_patterndetect_sr & {8{read_rx_status_0}});
+ rx_syncstatus_sr <= rx_syncstatus_c |
+ (rx_syncstatus_sr & {8{read_rx_status_0}});
+ end
+end
+
+assign hxaui_csr_rx_status_0 = {rx_patterndetect_sr, rx_syncstatus_sr};
+
+//--- rx_status_1 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ rx_errdetect_c <= rx_errdetect;
+ rx_disperr_c <= rx_disperr;
+end
+
+assign read_rx_status_1 = read && (addr == HXAUI_CSR_RX_STATUS_1_ADDR);
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ rx_errdetect_sr <= 8'h0;
+ rx_disperr_sr <= 8'h0;
+ end else begin
+ rx_errdetect_sr <= rx_errdetect_c |
+ (rx_errdetect_sr & {8{read_rx_status_1}});
+ rx_disperr_sr <= rx_disperr_c |
+ (rx_disperr_sr & {8{read_rx_status_1}});
+ end
+end
+
+assign hxaui_csr_rx_status_1 = {rx_errdetect_sr, rx_disperr_sr};
+
+//--- rx_status_2 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ rx_phase_comp_fifo_error_c <= rx_phase_comp_fifo_error;
+ rx_rlv_c <= rx_rlv;
+end
+
+assign read_rx_status_2 = read && (addr == HXAUI_CSR_RX_STATUS_2_ADDR);
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ rx_phase_comp_fifo_error_sr <= 4'h0;
+ rx_rlv_sr <= 4'h0;
+ end else begin
+ rx_phase_comp_fifo_error_sr <= rx_phase_comp_fifo_error_c |
+ (rx_phase_comp_fifo_error_sr & {4{read_rx_status_2}});
+ rx_rlv_sr <= rx_rlv_c |
+ (rx_rlv_sr & {4{read_rx_status_2}});
+ end
+end
+
+assign hxaui_csr_rx_status_2 = {rx_phase_comp_fifo_error_sr, rx_rlv_sr};
+
+//--- rx_status_3 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ rx_rmfifodatainserted_c <= rx_rmfifodatainserted;
+ rx_rmfifodatadeleted_c <= rx_rmfifodatadeleted;
+end
+
+assign read_rx_status_3 = read && (addr == HXAUI_CSR_RX_STATUS_3_ADDR);
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ rx_rmfifodatainserted_sr <= 8'h0;
+ rx_rmfifodatadeleted_sr <= 8'h0;
+ end else begin
+ rx_rmfifodatainserted_sr <= rx_rmfifodatainserted_c |
+ (rx_rmfifodatainserted_sr & {8{read_rx_status_3}});
+ rx_rmfifodatadeleted_sr <= rx_rmfifodatadeleted_c |
+ (rx_rmfifodatadeleted_sr & {8{read_rx_status_3}});
+ end
+end
+
+assign hxaui_csr_rx_status_3 = {rx_rmfifodatainserted_sr,
+ rx_rmfifodatadeleted_sr};
+
+//--- rx_status_4 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ rx_rmfifoempty_c <= rx_rmfifoempty;
+ rx_rmfifofull_c <= rx_rmfifofull;
+end
+
+assign read_rx_status_4 = read && (addr == HXAUI_CSR_RX_STATUS_4_ADDR);
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ rx_rmfifoempty_sr <= 4'h0;
+ rx_rmfifofull_sr <= 4'h0;
+ end else begin
+ rx_rmfifoempty_sr <= rx_rmfifoempty_c |
+ (rx_rmfifoempty_sr & {4{read_rx_status_4}});
+ rx_rmfifofull_sr <= rx_rmfifofull_c |
+ (rx_rmfifofull_sr & {4{read_rx_status_4}});
+ end
+end
+
+assign hxaui_csr_rx_status_4 = {rx_rmfifoempty_sr, rx_rmfifofull_sr};
+
+//--- tx_status_0 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ tx_phase_comp_fifo_error_c <= tx_phase_comp_fifo_error;
+end
+
+assign read_tx_status_0 = read && (addr == HXAUI_CSR_TX_STATUS_0_ADDR);
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ tx_phase_comp_fifo_error_sr <= 4'h0;
+ end else begin
+ tx_phase_comp_fifo_error_sr <= tx_phase_comp_fifo_error_c |
+ (tx_phase_comp_fifo_error_sr & {4{read_tx_status_0}});
+ end
+end
+
+assign hxaui_csr_tx_status_0 = tx_phase_comp_fifo_error_sr;
+
+
+endmodule // hxaui_csr
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/hxaui_csr_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/hxaui_csr_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..b4856c0cf54dc1a394a545937fa14fa28b03a1ce
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/hxaui_csr_h.sv
@@ -0,0 +1,155 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// (C) 2001-2011 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+///////////////////////////////////////////////////////////////////////////////
+//
+//
+// Description: Hard xaui control and status registers header file
+//
+// Authors: ishimony 12-Jun-2009
+//
+// Copyright (c) Altera Corporation 1997 - 2009
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+`timescale 1 ps / 1 ps
+
+package hxaui_csr_h;
+
+
+// address map
+localparam [11:0]ALT_PMA_CONTROLLER_ADDR =12'h080;
+localparam [11:0]ALT_PMA_CH_CONTROLLER_ADDR =12'h180;
+//localparam ALT_PMA_ADDR 12'h080
+localparam [11:0]ALT_RECONFIG_ANALOG_ADDR =12'h400;
+localparam [11:0]ALT_RECONFIG_OC_ADDR =12'h408;
+localparam [11:0]HXAUI_CSR_ADDR =12'h200;
+
+
+// registers address -------------------------------------------------------
+// preserve 7'h00 for indirection register (future implementation)
+localparam [6:0]HXAUI_CSR_RESET_ADDR =7'h04;
+localparam [6:0]HXAUI_CSR_RX_CNTRL_ADDR =7'h08;
+localparam [6:0]HXAUI_CSR_TX_CNTRL_ADDR =7'h0C;
+localparam [6:0]HXAUI_CSR_RX_STATUS_0_ADDR =7'h10;
+localparam [6:0]HXAUI_CSR_RX_STATUS_1_ADDR =7'h14;
+localparam [6:0]HXAUI_CSR_RX_STATUS_2_ADDR =7'h18;
+localparam [6:0]HXAUI_CSR_RX_STATUS_3_ADDR =7'h1C;
+localparam [6:0]HXAUI_CSR_RX_STATUS_4_ADDR =7'h20;
+localparam [6:0]HXAUI_CSR_TX_STATUS_0_ADDR =7'h24;
+localparam [6:0]HXAUI_CSR_SIMULATION_FLAG_ADDR =7'h28;
+
+// register bitmap ---------------------------------------------------------
+localparam [32:0]HXAUI_CSR_RESET_RX_DIGITAL =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RESET_TX_DIGITAL =32'h0000_0002;
+
+localparam [32:0]HXAUI_CSR_RX_CNTRL_INVPOLARITY_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_CNTRL_INVPOLARITY_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_CNTRL_INVPOLARITY_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_CNTRL_INVPOLARITY_3 =32'h0000_0008;
+
+localparam [32:0]HXAUI_CSR_TX_CNTRL_INVPOLARITY_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_TX_CNTRL_INVPOLARITY_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_TX_CNTRL_INVPOLARITY_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_TX_CNTRL_INVPOLARITY_3 =32'h0000_0008;
+
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_3 =32'h0000_0008;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_4 =32'h0000_0010;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_5 =32'h0000_0020;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_6 =32'h0000_0040;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_7 =32'h0000_0080;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_0 =32'h0000_0100;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_1 =32'h0000_0200;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_2 =32'h0000_0400;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_3 =32'h0000_0800;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_4 =32'h0000_1000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_5 =32'h0000_2000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_6 =32'h0000_4000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_7 =32'h0000_8000;
+
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_3 =32'h0000_0008;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_4 =32'h0000_0010;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_5 =32'h0000_0020;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_6 =32'h0000_0040;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_7 =32'h0000_0080;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_0 =32'h0000_0100;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_1 =32'h0000_0200;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_2 =32'h0000_0400;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_3 =32'h0000_0800;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_4 =32'h0000_1000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_5 =32'h0000_2000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_6 =32'h0000_4000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_7 =32'h0000_8000;
+
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_RLV_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_RLV_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_RLV_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_RLV_3 =32'h0000_0008;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_PHASE_COMP_FIFO_ERROR_0 =32'h0000_0010;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_PHASE_COMP_FIFO_ERROR_1 =32'h0000_0020;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_PHASE_COMP_FIFO_ERROR_2 =32'h0000_0040;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_PHASE_COMP_FIFO_ERROR_3 =32'h0000_0080;
+
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_3 =32'h0000_0008;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_4 =32'h0000_0010;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_5 =32'h0000_0020;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_6 =32'h0000_0040;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_7 =32'h0000_0080;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_0 =32'h0000_0100;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_1 =32'h0000_0200;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_2 =32'h0000_0400;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_3 =32'h0000_0800;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_4 =32'h0000_1000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_5 =32'h0000_2000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_6 =32'h0000_4000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_7 =32'h0000_8000;
+
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOFULL_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOFULL_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOFULL_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOFULL_3 =32'h0000_0008;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOEMPTY_0 =32'h0000_0010;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOEMPTY_1 =32'h0000_0020;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOEMPTY_2 =32'h0000_0040;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOEMPTY_3 =32'h0000_0080;
+
+localparam [32:0]HXAUI_CSR_TX_STATUS_0_PHASE_COMP_FIFO_ERROR_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_TX_STATUS_0_PHASE_COMP_FIFO_ERROR_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_TX_STATUS_0_PHASE_COMP_FIFO_ERROR_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_TX_STATUS_0_PHASE_COMP_FIFO_ERROR_3 =32'h0000_0008;
+
+localparam [32:0]HXAUI_CSR_SIMULATION_FLAG =32'h0000_0001;
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/l_modules.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/l_modules.v
new file mode 100644
index 0000000000000000000000000000000000000000..2b3bf6b04c6c180d058b1f656e638fcde12640fe
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diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/plain_files.txt b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/plain_files.txt
new file mode 100644
index 0000000000000000000000000000000000000000..435f8d1eb9137f58d00894a7cd9aa819c97a62a2
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/plain_files.txt
@@ -0,0 +1,58 @@
+./altera_xcvr_functions.sv
+./alt_pma_functions.sv
+./altera_xcvr_xaui.sv
+./hxaui_csr_h.sv
+./hxaui_csr.sv
+./alt_xcvr_mgmt2dec_phyreconfig.sv
+./alt_xcvr_mgmt2dec_xaui.sv
+./alt_pma_ch_controller_tgx.v
+./alt_pma_controller_tgx.v
+./alt_reset_ctrl_lego.sv
+./alt_reset_ctrl_tgx_cdrauto.sv
+./alt_xcvr_resync.sv
+./alt_xcvr_csr_common_h.sv
+./alt_xcvr_csr_common.sv
+./alt_xcvr_csr_pcs8g_h.sv
+./alt_xcvr_csr_pcs8g.sv
+./alt_xcvr_csr_selector.sv
+./alt_xcvr_mgmt2dec.sv
+./altera_wait_generate.v
+./alt_soft_xaui_pcs.v
+./alt_soft_xaui_reset.v
+./alt_soft_xaui_rx.v
+./alt_soft_xaui_rx_8b10b_dec.v
+./alt_soft_xaui_rx_channel_synch.v
+./alt_soft_xaui_rx_deskew.v
+./alt_soft_xaui_rx_deskew_channel.v
+./alt_soft_xaui_rx_deskew_ram.v
+./alt_soft_xaui_rx_invalid_code_det.v
+./alt_soft_xaui_rx_parity.v
+./alt_soft_xaui_rx_parity_4b.v
+./alt_soft_xaui_rx_parity_6b.v
+./alt_soft_xaui_rx_rate_match.v
+./alt_soft_xaui_rx_rate_match_ram.v
+./alt_soft_xaui_rx_rl_chk_6g.v
+./alt_soft_xaui_rx_sm.v
+./alt_soft_xaui_tx.v
+./alt_soft_xaui_tx_8b10b_enc.v
+./alt_soft_xaui_tx_idle_conv.v
+./l_modules.v
+./serdes_4_unit_lc_siv.v
+./serdes_4_unit_siv.v
+./serdes_4unit.v
+./sxaui.v
+./siv_xcvr_low_latency_phy_nr.sv
+./siv_xcvr_xaui.sv
+./alt_xcvr_reconfig_h.sv
+./alt_xcvr_reconfig_siv.sv
+./alt_xcvr_reconfig_analog.sv
+./alt_xcvr_reconfig_analog_tgx.v
+./alt_xcvr_reconfig_offset_cancellation.sv
+./alt_xcvr_reconfig_offset_cancellation_tgx.v
+./alt_xcvr_reconfig_eyemon_tgx.sv
+./alt_xcvr_reconfig_dfe_tgx.sv
+./alt_xcvr_reconfig_basic_tgx.v
+./alt_mutex_acq.v
+./alt_dprio.v
+./alt_xcvr_arbiter.sv
+./alt_xcvr_m2s.sv
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/qencrypt_files.txt b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/qencrypt_files.txt
new file mode 100644
index 0000000000000000000000000000000000000000..435f8d1eb9137f58d00894a7cd9aa819c97a62a2
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/qencrypt_files.txt
@@ -0,0 +1,58 @@
+./altera_xcvr_functions.sv
+./alt_pma_functions.sv
+./altera_xcvr_xaui.sv
+./hxaui_csr_h.sv
+./hxaui_csr.sv
+./alt_xcvr_mgmt2dec_phyreconfig.sv
+./alt_xcvr_mgmt2dec_xaui.sv
+./alt_pma_ch_controller_tgx.v
+./alt_pma_controller_tgx.v
+./alt_reset_ctrl_lego.sv
+./alt_reset_ctrl_tgx_cdrauto.sv
+./alt_xcvr_resync.sv
+./alt_xcvr_csr_common_h.sv
+./alt_xcvr_csr_common.sv
+./alt_xcvr_csr_pcs8g_h.sv
+./alt_xcvr_csr_pcs8g.sv
+./alt_xcvr_csr_selector.sv
+./alt_xcvr_mgmt2dec.sv
+./altera_wait_generate.v
+./alt_soft_xaui_pcs.v
+./alt_soft_xaui_reset.v
+./alt_soft_xaui_rx.v
+./alt_soft_xaui_rx_8b10b_dec.v
+./alt_soft_xaui_rx_channel_synch.v
+./alt_soft_xaui_rx_deskew.v
+./alt_soft_xaui_rx_deskew_channel.v
+./alt_soft_xaui_rx_deskew_ram.v
+./alt_soft_xaui_rx_invalid_code_det.v
+./alt_soft_xaui_rx_parity.v
+./alt_soft_xaui_rx_parity_4b.v
+./alt_soft_xaui_rx_parity_6b.v
+./alt_soft_xaui_rx_rate_match.v
+./alt_soft_xaui_rx_rate_match_ram.v
+./alt_soft_xaui_rx_rl_chk_6g.v
+./alt_soft_xaui_rx_sm.v
+./alt_soft_xaui_tx.v
+./alt_soft_xaui_tx_8b10b_enc.v
+./alt_soft_xaui_tx_idle_conv.v
+./l_modules.v
+./serdes_4_unit_lc_siv.v
+./serdes_4_unit_siv.v
+./serdes_4unit.v
+./sxaui.v
+./siv_xcvr_low_latency_phy_nr.sv
+./siv_xcvr_xaui.sv
+./alt_xcvr_reconfig_h.sv
+./alt_xcvr_reconfig_siv.sv
+./alt_xcvr_reconfig_analog.sv
+./alt_xcvr_reconfig_analog_tgx.v
+./alt_xcvr_reconfig_offset_cancellation.sv
+./alt_xcvr_reconfig_offset_cancellation_tgx.v
+./alt_xcvr_reconfig_eyemon_tgx.sv
+./alt_xcvr_reconfig_dfe_tgx.sv
+./alt_xcvr_reconfig_basic_tgx.v
+./alt_mutex_acq.v
+./alt_dprio.v
+./alt_xcvr_arbiter.sv
+./alt_xcvr_m2s.sv
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/serdes_4_unit_lc_siv.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/serdes_4_unit_lc_siv.v
new file mode 100644
index 0000000000000000000000000000000000000000..c302341339a0d9a87ed9200659060fce42b22100
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diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/serdes_4_unit_siv.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/serdes_4_unit_siv.v
new file mode 100644
index 0000000000000000000000000000000000000000..9cc291483695bfeb8d07e6eb0de3ba607d6454cc
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diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/serdes_4unit.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/serdes_4unit.v
new file mode 100644
index 0000000000000000000000000000000000000000..02dd3cda58d2839ae60c84515f0cd5f3fd2e1c1d
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diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/siv_xcvr_low_latency_phy_nr.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/siv_xcvr_low_latency_phy_nr.sv
new file mode 100644
index 0000000000000000000000000000000000000000..de32c92263ec21c27299b5fa15160844b80dba64
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/siv_xcvr_low_latency_phy_nr.sv
@@ -0,0 +1,352 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// PMA-direct component for TGX-style transceiver architectures
+//
+// $Header$
+//
+`timescale 1 ps / 1 ps
+module siv_xcvr_low_latency_phy_nr
+#(
+
+ //reserved parameter, don't change them.
+ parameter device_family="Stratix IV",
+ intended_device_variant ="ANY",
+
+ //must have parameters
+ parameter number_of_channels = 1,
+ parameter number_of_reconfig_interface = 1,//it's number of quad for S4
+ parameter operation_mode = "DUPLEX", //TX, RX, DUPLEX
+ parameter phase_comp_fifo_mode = "NONE",//EMBEDDED, NONE
+ parameter serialization_factor = 16,//8,10,16,20,32,40
+ parameter data_rate = "3125 Mbps",
+ parameter pll_input_frequency = "156.25 MHz",
+
+ //additonal system parameters
+ parameter number_pll_inclks = 1,//reconfig may need more than one reference clock
+ parameter pll_inclk_select = 0,//0-number_of_ref_clks
+ parameter pll_type = "CMU",//ATX|CMU
+ parameter bonded_mode = "TRUE",
+ parameter starting_channel_number = 0,//0,4,8,12 ...
+ parameter support_reconfig = 1,
+ parameter rx_use_cruclk = "FALSE",
+
+ //analog parameters
+ parameter gx_analog_power = "AUTO",//AUTO|2.5v|3.0v|3.3v|3.9v
+
+ parameter pll_lock_speed = "AUTO",//AUTO|LOW|MEDIUM|HIGH
+ parameter tx_analog_power = "AUTO",//AUTO|1.4V|1.5V
+ parameter tx_slew_rate = "LOW",//AUTO,LOW,MEDIUM,HIGH
+ parameter tx_termination = "OCT_100_OHMS",//OCT_85_OHMS,OCT_100_OHMS,OCT_120_OHMS,OCT_150_OHMS
+ parameter tx_use_external_termination = "FALSE", //FALSE|TRUE
+ parameter tx_common_mode = "0.65V", //"0.65V"
+
+ parameter rx_pll_lock_speed = "AUTO",//AUTO|LOW|MEDIUM|HIGH
+ parameter rx_common_mode = "0.82v", //TRISTATE|0.82v|1.1v
+ parameter rx_signal_detect_threshold = 2,
+ parameter rx_ppmselect = 32,
+ parameter rx_termination = "OCT_100_OHMS", //OCT_85_OHMS,OCT_100_OHMS,OCT_120_OHMS,OCT_150_OHMS
+ parameter rx_use_external_termination = "FALSE", //FALSE|TRUE
+
+ parameter tx_preemp_pretap = 0,//0-7
+ parameter tx_preemp_pretap_inv = "FALSE",//TRUE” or FALSE”. Determine whether the pre-emphasis control signal for the pretap needed to be inverted or not.“true” – Invert the pre-emphasis control signal for the pre tap.“false” – Do not invert the pre-emphasis control signal for the pretap.
+ parameter tx_preemp_tap_1 = 5,//0-15
+ parameter tx_preemp_tap_2 = 0,//0-7
+ parameter tx_preemp_tap_2_inv = "FALSE",//TRUE” or FALSE”.
+ parameter tx_vod_selection = 1,//0-7
+
+ parameter rx_eq_dc_gain = 0, //0-4
+ parameter rx_eq_ctrl = 14,//0-16
+
+ parameter sys_clk_in_mhz = 150, // used to calculate reset controller delays as system clock cycle counts
+
+ parameter loopback_mode = "NONE"//NONE|SLB|PLB|PRECDR_RSLB|POSTCDR_RSLB|RPLB
+)
+(
+
+ // user data (avalon-MM slave interface) //for all the channel rst, powerdown, rx serilize loopback enable
+ input wire rst,
+ input wire clk,
+ input wire [5:0] ch_mgmt_address,
+ input wire ch_mgmt_read,
+ output wire [31:0] ch_mgmt_readdata,
+ input wire ch_mgmt_write,
+ input wire [31:0] ch_mgmt_writedata,
+ output wire ch_mgmt_waitrequest,
+
+ // avalon-ST interface with PMA controller
+ input wire cal_blk_clk,
+ input wire cal_blk_pdn,
+ input wire gx_pdn,//sync with clk
+ input wire tx_rst_digital, // digital reset
+ input wire rx_rst_digital, // digital reset
+ output wire tx_pma_ready, // pma tx pll_locked
+ output wire rx_pma_ready, // pma rx pll is locked to data
+
+ input wire pll_pdn, //sync with clk
+ output wire pll_locked, //conduit
+
+ // avalon-ST interface with reconfig controller
+ input wire reconfig_clk,
+ input wire [3:0] reconfig_to_gxb, //sync with reconfig_clk
+ output wire [17* number_of_reconfig_interface -1:0] reconfig_from_gxb, //sync with reconfig_clk. 17 bit per quad
+// input wire [24 * number_of_reconfig_interface -1 : 0] aeq_to_gxb, //sync with reconfig_clk
+// output wire [8*number_of_reconfig_interface -1:0] aeq_from_gxb, //sync with reconfig_clk.
+
+
+ //channel related avalon-clock interface
+ input wire [number_pll_inclks-1:0] pll_ref_clk,
+ input wire [number_of_channels-1:0] rx_cdr_ref_clk,
+
+ //channel related avalon-ST interface, tx
+ input wire [number_of_channels * serialization_factor -1:0] tx_parallel_data,// sync with tx_clkout_clk
+ output wire [number_of_channels-1:0] tx_serial_data, // canduit
+ output wire [number_of_channels-1:0] tx_out_clk,
+
+ //channel related AVALON-st INTERFACE, rx
+ input wire [number_of_channels-1:0] rx_serial_data,//canduit
+ output wire [number_of_channels * serialization_factor -1:0] rx_parallel_data,// sync with rx_clkout_clk
+ output wire [number_of_channels-1:0] rx_recovered_clk,
+
+ output wire [number_of_channels-1:0] rx_is_lockedtodata,//conduit
+ output wire [number_of_channels-1:0] rx_is_lockedtoref,//conduit
+
+ output wire [number_of_channels-1:0] tx_digital_rst, // output digital reset for soft PCS, this reset can be controlled in AVMM
+ output wire [number_of_channels-1:0] rx_digital_rst // output digital reset for soft PCS, this reset can be controlled in AVMM
+
+);
+
+// instantiate package with common functions
+import alt_pma_functions::*;
+
+//derived parameters
+localparam tx_inclk0_input_period_loc = freq2ps(pll_input_frequency) ;
+localparam use6g= (((mega2k(data_rate) > 1000000) && ((serialization_factor == 32) || (serialization_factor == 40))) || ((serialization_factor != 8) && (serialization_factor != 10)))? "TRUE" : "FALSE";
+localparam pma_serialization_factor = (phase_comp_fifo_mode != "EMBEDDED") ? serialization_factor :
+ ((serialization_factor>20)? (serialization_factor/2):
+ ((serialization_factor<16)? serialization_factor :
+ ((use6g == "TRUE")? serialization_factor : serialization_factor /2)));
+//localparam RX_INCLK_INPUT_PERIOD_LOC = ( RX_INCLK_INPUT_PERIOD == 0) ? freq2ps(RX_pll_input_frequency) : RX_INCLK_INPUT_PERIOD;
+//localparam rx_inclk_input_frequency_loc = ( operation_mode == "DUPLEX") ? ((RX_INCLK_INPUT_FREQUENCY == 0) ? INCLK_INPUT_FREQUENCY : RX_INCLK_INPUT_FREQUENCY) :0;
+localparam double_serialization_mode=(serialization_factor/pma_serialization_factor == 2) ? "TRUE":"FALSE";
+localparam rx_eqa_ctrl = (device_family=="Stratix IV") ? ((rx_eq_ctrl >10)? 7 :0) : ((rx_eq_ctrl >1)? 1:0);
+localparam rx_eqb_ctrl = (device_family=="Stratix IV") ? ((rx_eq_ctrl >6)? 7 :0) : ((rx_eq_ctrl >3)? 1:0);
+localparam rx_eqc_ctrl = (device_family=="Stratix IV") ? ((rx_eq_ctrl >3)? 7 :0) : 0;
+localparam rx_eqd_ctrl = (device_family=="Stratix IV") ? ((rx_eq_ctrl >0)? 7 :0) : 0;
+localparam rx_eqv_ctrl = (device_family=="Stratix IV") ?
+ ((rx_eq_ctrl==2 | rx_eq_ctrl==5 | rx_eq_ctrl==8 | rx_eq_ctrl==13)? 4 :
+ ((rx_eq_ctrl==3 | rx_eq_ctrl==6 | rx_eq_ctrl==10 | rx_eq_ctrl==15)? 7 :
+ ((rx_eq_ctrl==9 | rx_eq_ctrl==14 )? 5 :
+ (rx_eq_ctrl==12)? 3 : 0))) :
+ ((rx_eq_ctrl==0 | rx_eq_ctrl==2 | rx_eq_ctrl==4 )? 1 :0 );
+localparam number_of_ctrl_bus=(bonded_mode == "FALSE")? number_of_reconfig_interface : 1;
+
+localparam enable_lc_tx_pll_param = (pll_type == "CMU")? "FALSE" : "TRUE";
+localparam enable_pma_direct_param = (phase_comp_fifo_mode == "EMBEDDED")? "FALSE":"TRUE";
+localparam dwidth_factor = (use6g == "TRUE")? (double_serialization_mode == "TRUE" ? 4:2):(double_serialization_mode == "TRUE" ? 2:1);
+localparam reconfig_dprio_mode = (support_reconfig == 0)? 0 : 1;
+
+localparam control_signal_width = (bonded_mode == "TRUE") ? 1: number_of_channels;
+localparam pma_direct_xn = (phase_comp_fifo_mode == "NONE")? bonded_mode : "FALSE";
+localparam pma_bonding = (phase_comp_fifo_mode == "EMBEDDED")? bonded_mode : "FALSE";
+
+wire [control_signal_width-1:0] gxb_pdn_loc;
+generate
+genvar i;
+for (i=0; i<control_signal_width; i=i+1)
+begin: gxb_pdn_bus
+assign gxb_pdn_loc[i] = gx_pdn;
+end
+endgenerate
+
+wire [control_signal_width-1:0] pll_pdn_loc;
+generate
+genvar j;
+for (j=0; j<control_signal_width; j=j+1)
+begin: pll_pdn_bus
+assign pll_pdn_loc[j] = pll_pdn;
+end
+endgenerate
+
+wire [number_of_channels-1:0] rx_set_locktodata;
+wire [number_of_channels-1:0] rx_set_locktoref;
+
+wire [number_of_channels-1:0] rx_analog_rst;
+wire [number_of_channels-1:0] rx_seriallpbken;
+
+
+
+alt4gxb #(
+ .cbx_hdl_language ("Verilog"),
+ .enable_pma_xn_bonding (pma_direct_xn),
+ .cmu_pll_inclk_log_index (pll_inclk_select),
+ .cmu_pll_log_index (0),
+ .device_family (device_family),
+ .intended_device_variant (intended_device_variant),
+ .effective_data_rate (data_rate),
+ .enable_lc_tx_pll (enable_lc_tx_pll_param),
+ .enable_pma_direct (enable_pma_direct_param),
+ .enable_pll_inclk_drive_rx_cru((rx_use_cruclk == "FALSE")? "TRUE" : "FALSE"),
+ .equalizer_ctrl_a_setting (rx_eqa_ctrl),
+ .equalizer_ctrl_b_setting (rx_eqb_ctrl),
+ .equalizer_ctrl_c_setting (rx_eqc_ctrl),
+ .equalizer_ctrl_d_setting (rx_eqd_ctrl),
+ .equalizer_ctrl_v_setting (rx_eqv_ctrl),
+ .equalizer_dcgain_setting (rx_eq_dc_gain),
+ .gen_reconfig_pll ("FALSE"),
+ .gx_channel_type ("AUTO"),
+ .gxb_analog_power (gx_analog_power),
+ .gxb_powerdown_width (control_signal_width),
+ .input_clock_frequency (pll_input_frequency),
+ .loopback_mode (loopback_mode),
+ .number_of_channels (number_of_channels),
+ .number_of_quads (number_of_reconfig_interface),
+ .operation_mode (operation_mode),
+ .pll_control_width (number_of_ctrl_bus),
+ .protocol ("BASIC"),
+ .use_global_clk_divider (pma_bonding),
+ .receiver_termination (rx_termination),
+ .rx_use_external_termination (rx_use_external_termination),
+ .reconfig_calibration ("TRUE"),
+ .reconfig_dprio_mode (reconfig_dprio_mode),
+ .reconfig_fromgxb_port_width (17*number_of_reconfig_interface ),
+ .reconfig_pll_inclk_width ((support_reconfig == 0)? 1: number_pll_inclks),
+ .reconfig_protocol ("BASIC"),
+ .reconfig_togxb_port_width (4),
+ .rx_use_cruclk (rx_use_cruclk),
+ .rx_channel_width (serialization_factor),
+ .rx_common_mode (rx_common_mode),
+ .rx_cru_bandwidth_type (rx_pll_lock_speed),
+ .rx_digitalreset_port_width (number_of_channels),
+ .rx_enable_lock_to_data_sig ("true"),
+ .rx_enable_lock_to_refclk_sig ("true"),
+ .rx_ppmselect (rx_ppmselect),
+ .rx_reconfig_clk_scheme ("indv_clk_source"),
+ .rx_signal_detect_threshold (rx_signal_detect_threshold),
+ .rx_use_clkout ("TRUE"),
+ .rx_use_coreclk ("false"),
+ .rx_use_deserializer_double_data_mode(use6g),
+ .rx_use_double_data_mode (double_serialization_mode),
+ .starting_channel_number (starting_channel_number),
+ .transmitter_termination (tx_termination),
+ .tx_use_external_termination (tx_use_external_termination),
+ .tx_dwidth_factor (dwidth_factor),
+ .tx_analog_power (tx_analog_power),
+ .tx_channel_width (serialization_factor),
+ .tx_clkout_width (number_of_channels),
+ .tx_common_mode (tx_common_mode),
+ .tx_pll_bandwidth_type (pll_lock_speed),
+ .tx_pll_inclk0_period (tx_inclk0_input_period_loc),
+ .tx_pll_type (pll_type),
+ .tx_reconfig_clk_scheme ("tx_ch0_clk_source"),
+ .tx_slew_rate (tx_slew_rate),
+ .tx_transmit_protocol ("basic"),
+ .tx_use_coreclk ("false"),
+ .tx_use_double_data_mode (double_serialization_mode),
+ .tx_use_serializer_double_data_mode (use6g),
+ .preemphasis_ctrl_pretap_setting (tx_preemp_pretap),
+ .preemphasis_ctrl_pretap_inv_setting (tx_preemp_pretap_inv),
+ .preemphasis_ctrl_1stposttap_setting (tx_preemp_tap_1),
+ .preemphasis_ctrl_2ndposttap_setting (tx_preemp_tap_2),
+ .preemphasis_ctrl_2ndposttap_inv_setting (tx_preemp_tap_2_inv),
+ .use_calibration_block ("TRUE"),
+ .vod_ctrl_setting (tx_vod_selection),
+ .tx_digitalreset_port_width (number_of_channels),
+ .rx_use_align_state_machine ("true"),//must have
+ .tx_datapath_low_latency_mode ("true"),
+ .rx_use_deskew_fifo ("false"),
+ .rx_word_aligner_num_byte (2),
+ .rx_rate_match_fifo_mode ("none"),
+ .tx_enable_bit_reversal ("false"),
+ .tx_enable_self_test_mode ("false"),
+ .tx_flip_tx_in ("false"),
+ .rx_dwidth_factor (dwidth_factor),
+ .rx_8b_10b_mode ("none"),
+ .rx_allow_align_polarity_inversion ("false"),
+ .rx_allow_pipe_polarity_inversion ("false"),
+ .tx_bitslip_enable ("false"),
+ .rx_bitslip_enable ("true"),
+ .rx_byte_ordering_mode ("none"),
+ .rx_enable_self_test_mode ("false"),
+ .rx_flip_rx_out ("false"),
+ .rx_force_signal_detect ("true"),
+ .rx_phfiforegmode ("false"),
+ .rx_datapath_low_latency_mode ("true"),
+ .rx_datapath_protocol ("basic"),
+ .rx_enable_bit_reversal ("false"),
+ .rx_enable_deep_align_byte_swap("false")
+ ) pma_direct (
+ .cal_blk_clk (cal_blk_clk),
+ .cal_blk_powerdown (cal_blk_pdn),
+ .gxb_powerdown (gxb_pdn_loc),
+ .pll_inclk(pll_ref_clk),
+ //.pll_inclk_rx_cruclk((support_reconfig == 0)? 0 : pll_ref_clk),
+ .rx_cruclk ((rx_use_cruclk == "TRUE")? rx_cdr_ref_clk[number_of_channels - 1:0] : {number_of_channels{1'b0}}),
+ .pll_locked (pll_locked),
+ .pll_powerdown (pll_pdn_loc),
+ .reconfig_clk (reconfig_clk),
+ .reconfig_fromgxb (reconfig_from_gxb),
+ .reconfig_togxb (reconfig_to_gxb),
+ .rx_analogreset (rx_analog_rst[number_of_channels-1:0]),
+ .rx_seriallpbken ((loopback_mode == "SLB")? rx_seriallpbken[number_of_channels-1:0] : 0),
+ .tx_digitalreset ((phase_comp_fifo_mode == "EMBEDDED")? tx_digital_rst[number_of_channels-1:0] : {number_of_channels{1'b0}}),
+ .rx_digitalreset ((phase_comp_fifo_mode == "EMBEDDED")? rx_digital_rst[number_of_channels-1:0] : {number_of_channels{1'b0}}),
+ .rx_clkout (rx_recovered_clk[number_of_channels-1:0]),
+ .rx_datain (rx_serial_data[number_of_channels-1:0]),
+ .rx_dataout (rx_parallel_data[serialization_factor * number_of_channels-1:0]),
+ .rx_freqlocked (rx_is_lockedtodata[number_of_channels-1:0]),
+ .rx_locktodata (rx_set_locktodata[number_of_channels-1:0]),
+ .rx_locktorefclk (rx_set_locktoref[number_of_channels-1:0]),
+ .rx_pll_locked (rx_is_lockedtoref[number_of_channels-1:0]),
+ .tx_clkout (tx_out_clk[number_of_channels-1:0]),
+ .tx_datain (tx_parallel_data[serialization_factor * number_of_channels-1:0]),
+ .tx_dataout (tx_serial_data[number_of_channels-1:0])
+ );
+
+alt_pma_ch_controller_tgx #(
+ .number_of_channels (number_of_channels),
+ .sys_clk_in_mhz (sys_clk_in_mhz),
+ .sync_depth (2)
+) channel_ctrl (
+ .rst(rst),
+ .tx_rst_digital (tx_rst_digital), // tx_digitalreset
+ .rx_rst_digital (rx_rst_digital), // rx_digitalreset
+ .tx_pma_ready (tx_pma_ready), // pma tx pll_locked
+ .rx_pma_ready (rx_pma_ready), // pma rx pll is locked to data
+ .rx_cal_busy (reconfig_to_gxb[3]), // rx_ocilator busy
+ .tx_cal_busy (1'b0), // rx_ocilator busy
+ .pll_locked (pll_locked), // tx pll_is_locked
+
+ .ch_mgmt_address (ch_mgmt_address),
+ .ch_mgmt_read (ch_mgmt_read),
+ .ch_mgmt_readdata (ch_mgmt_readdata),
+ .ch_mgmt_write (ch_mgmt_write),
+ .ch_mgmt_writedata (ch_mgmt_writedata),
+ .clk (clk),
+ .ch_mgmt_waitrequest(ch_mgmt_waitrequest),
+
+ .rx_is_lockedtodata (rx_is_lockedtodata),
+ .rx_is_lockedtoref (rx_is_lockedtoref),
+
+ .rx_set_locktodata (rx_set_locktodata),
+ .rx_set_locktoref (rx_set_locktoref),
+
+ .rx_analog_rst (rx_analog_rst),
+ .rx_seriallpbken (rx_seriallpbken),
+ .tx_digital_rst (tx_digital_rst),
+ .rx_digital_rst (rx_digital_rst),
+ .pll_powerdown ()
+);
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/siv_xcvr_xaui.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/siv_xcvr_xaui.sv
new file mode 100644
index 0000000000000000000000000000000000000000..16ad2c9b0c247529918db040a9c41da5f8639e0c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/siv_xcvr_xaui.sv
@@ -0,0 +1,539 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//-----------------------------------------------------------------------------
+//
+// Description: hxaui static verilog for Stratix IV
+//
+// Authors: bauyeung 7-Sep-2010
+//
+// Copyright (c) Altera Corporation 1997 - 2010
+// All rights reserved.
+//
+//-----------------------------------------------------------------------------
+ /*ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"set_false_path -from [get_registers *hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component*] -to [get_registers *xaui_phy*hxaui_csr*tx_phase_comp_fifo_error_c[*]]\" " */
+
+module siv_xcvr_xaui #(
+ parameter device_family = "Stratix IV",
+ parameter starting_channel_number = 0,
+ parameter interface_type = "Hard XAUI",
+ parameter number_of_interfaces = 1,
+ parameter sys_clk_in_mhz = 50,
+ parameter xaui_pll_type = "CMU",
+ parameter reconfig_interfaces = 1,
+ parameter use_control_and_status_ports = 0,
+ parameter external_pma_ctrl_reconf = 0,
+ parameter tx_termination = "OCT_150_OHMS",
+ parameter tx_vod_selection = 1,
+ parameter tx_preemp_pretap = 0,
+ parameter tx_preemp_pretap_inv = 0,
+ parameter tx_preemp_tap_1 = 5,
+ parameter tx_preemp_tap_2 = 0,
+ parameter tx_preemp_tap_2_inv = 0,
+ parameter rx_common_mode = "0.82v",
+ parameter rx_termination = "OCT_150_OHMS",
+ parameter rx_eq_dc_gain = 0,
+ parameter rx_eq_ctrl = 14
+) (
+ input wire pll_ref_clk, // refclk.clk
+ input wire xgmii_tx_clk, // xgmii_tx_clk.clk
+ output wire xgmii_rx_clk, // xgmii_rx_clk.clk
+ input wire phy_mgmt_clk, // mgmt_clk.clk
+ input wire phy_mgmt_clk_reset, // mgmt_clk_rst.reset_n
+ input wire [7:0] phy_mgmt_address, // phy_mgmt.address
+ output wire phy_mgmt_waitrequest, // .waitrequest
+ input wire phy_mgmt_read, // .read
+ output wire [31:0] phy_mgmt_readdata, // .readdata
+ input wire phy_mgmt_write, // .write
+ input wire [31:0] phy_mgmt_writedata, // .writedata
+ input wire [71:0] xgmii_tx_dc, // xgmii_tx_dc.data
+ output wire [71:0] xgmii_rx_dc, // xgmii_rx_dc.data
+ output wire [3:0] xaui_tx_serial_data, // xaui_tx_serial.export
+ input wire [3:0] xaui_rx_serial_data, // xaui_rx_serial.export
+ output wire rx_ready, // rx_pma_ready.data
+ output wire tx_ready, // tx_pma_ready.data
+ output tri0 [altera_xcvr_functions::get_reconfig_from_width(device_family,reconfig_interfaces)-1:0] reconfig_from_xcvr,
+ input tri0 [altera_xcvr_functions::get_reconfig_to_width(device_family,reconfig_interfaces) -1:0] reconfig_to_xcvr,
+
+ output wire [3:0] rx_recovered_clk, // rx recovered clock from cdr
+// optional control and status ports
+ input wire rx_analogreset,
+ input wire rx_digitalreset,
+ input wire tx_digitalreset,
+ output wire rx_channelaligned,
+ input wire [3:0] rx_invpolarity,
+ input wire [3:0] rx_set_locktodata,
+ input wire [3:0] rx_set_locktoref,
+ input wire [3:0] rx_seriallpbken,
+ input wire [3:0] tx_invpolarity,
+ output wire [3:0] rx_is_lockedtodata,
+ output wire [3:0] rx_phase_comp_fifo_error,
+ output wire [3:0] rx_is_lockedtoref,
+ output wire [3:0] rx_rlv,
+ output wire [3:0] rx_rmfifoempty,
+ output wire [3:0] rx_rmfifofull,
+ output wire [3:0] tx_phase_comp_fifo_error,
+ output wire [7:0] rx_disperr,
+ output wire [7:0] rx_errdetect,
+ output wire [7:0] rx_patterndetect,
+ output wire [7:0] rx_rmfifodatadeleted,
+ output wire [7:0] rx_rmfifodatainserted,
+ output wire [7:0] rx_runningdisp,
+ output wire [7:0] rx_syncstatus,
+
+// external_pma_ctrl_reconf
+ output wire pll_locked,
+ input wire cal_blk_powerdown,
+ input wire gxb_powerdown,
+ input wire pll_powerdown
+);
+
+import altera_xcvr_functions::*;
+
+ wire alt_pma_controller_0_cal_blk_pdn_data;
+ wire alt_pma_controller_0_pll_pdn0_data;
+ wire alt_pma_controller_0_gx_pdn_data;
+ wire pll_locked_data;
+ wire [7:0] rx_disperr_data;
+ wire [7:0] rx_errdetect_data;
+ wire [7:0] rx_patterndetect_data;
+ wire [3:0] rx_phase_comp_fifo_error_data;
+ wire [3:0] rx_rlv_data;
+ wire [7:0] rx_rmfifodatadeleted_data;
+ wire [7:0] rx_rmfifodatainserted_data;
+ wire [3:0] rx_rmfifoempty_data;
+ wire [3:0] rx_rmfifofull_data;
+ wire [7:0] rx_runningdisp_data;
+ wire [7:0] rx_syncstatus_data;
+ wire [3:0] tx_phase_comp_fifo_error_data;
+ wire [3:0] alt_pma_ch_controller_0_rx_set_locktodata_data;
+ wire [3:0] alt_pma_ch_controller_0_rx_set_locktoref_data;
+ wire [3:0] alt_pma_ch_controller_0_rx_seriallpbken_data;
+ wire [3:0] alt_pma_ch_controller_0_rx_analog_rst_data;
+ wire [3:0] rx_is_lockedtodata_data;
+ wire [3:0] rx_is_lockedtoref_data;
+ wire [3:0] alt_pma_ch_controller_0_tx_digital_rst_data;
+ wire [3:0] alt_pma_ch_controller_0_rx_digital_rst_data;
+ wire hxaui_csr_r_rx_digitalreset_data;
+ wire [3:0] hxaui_csr_r_rx_invpolarity_data;
+ wire hxaui_csr_r_tx_digitalreset_data;
+ wire [3:0] hxaui_csr_r_tx_invpolarity_data;
+ wire hxaui_csr_simulation_flag_data;
+ wire alt_pma_controller_0_pll_pdn;
+ wire [3:0] alt_pma_0_tx_out_clk_clk;
+ wire [3:0] alt_pma_0_rx_recovered_clk_clk;
+ wire [79:0] sxaui_0_tx_parallel_data_data;
+ wire [79:0] alt_pma_0_rx_parallel_data_data;
+ wire [3:0] alt_pma_0_rx_is_lockedtodata_data;
+ wire rx_pma_ready;
+ wire sxaui_rst_done;
+
+
+ wire [5:0] sc_pma_ch_controller_address;
+ wire sc_pma_ch_controller_read;
+ wire [31:0] sc_pma_ch_controller_readdata;
+ wire sc_pma_ch_controller_waitrequest;
+ wire sc_pma_ch_controller_write;
+
+
+ wire [1:0] sc_pma_controller_address;
+ wire sc_pma_controller_read;
+ wire [31:0] sc_pma_controller_readdata;
+ wire sc_pma_controller_waitrequest;
+ wire sc_pma_controller_write;
+
+ wire [4:0] sc_csr_address;
+ wire sc_csr_read;
+ wire [31:0] sc_csr_readdata;
+ wire sc_csr_write;
+
+// assign output wires for status ports - whether or not they are used will be decided by the top level
+ assign rx_is_lockedtodata = rx_is_lockedtodata_data;
+ assign rx_phase_comp_fifo_error = rx_phase_comp_fifo_error_data;
+ assign rx_is_lockedtoref = rx_is_lockedtoref_data;
+ assign rx_rlv = rx_rlv_data;
+ assign rx_rmfifoempty = rx_rmfifoempty_data;
+ assign rx_rmfifofull = rx_rmfifofull_data;
+ assign tx_phase_comp_fifo_error = tx_phase_comp_fifo_error_data;
+ assign rx_disperr = rx_disperr_data;
+ assign rx_errdetect = rx_errdetect_data;
+ assign rx_patterndetect = rx_patterndetect_data;
+ assign rx_rmfifodatadeleted = rx_rmfifodatadeleted_data;
+ assign rx_rmfifodatainserted = rx_rmfifodatainserted_data;
+ assign rx_runningdisp = rx_runningdisp_data;
+ assign rx_syncstatus = rx_syncstatus_data;
+ assign rx_recovered_clk = alt_pma_0_rx_recovered_clk_clk;
+
+ // assign output wires for external pma_ctrl - whether or not they are used will be decided by the top level
+ assign pll_locked = pll_locked_data;
+ assign rx_ready = rx_pma_ready & sxaui_rst_done; // pma and PCS must be both ready
+
+ ///////////////////////////////////////////////////////////////////////
+ // Decoder for multiple slaves of pma_ch_control,pma_control,hxaui i/f
+ ///////////////////////////////////////////////////////////////////////
+ alt_xcvr_mgmt2dec_xaui mgmtdec_xaui (
+ .mgmt_clk_reset (phy_mgmt_clk_reset),
+ .mgmt_clk (phy_mgmt_clk),
+ .mgmt_address (phy_mgmt_address),
+ .mgmt_read (phy_mgmt_read),
+ .mgmt_write (phy_mgmt_write),
+ .mgmt_readdata (phy_mgmt_readdata),
+ .mgmt_waitrequest (phy_mgmt_waitrequest),
+
+ // internal interface to 'top' pma ch controller block
+ .sc_pma_ch_controller_readdata (sc_pma_ch_controller_readdata),
+ .sc_pma_ch_controller_waitrequest (sc_pma_ch_controller_waitrequest),
+ .sc_pma_ch_controller_address (sc_pma_ch_controller_address), //6 bit wide
+ .sc_pma_ch_controller_read (sc_pma_ch_controller_read),
+ .sc_pma_ch_controller_write (sc_pma_ch_controller_write),
+
+ // internal interface to 'top' pma controller block
+ .sc_pma_controller_readdata (sc_pma_controller_readdata),
+ .sc_pma_controller_waitrequest (sc_pma_controller_waitrequest),
+ .sc_pma_controller_address (sc_pma_controller_address), //2 bit wide
+ .sc_pma_controller_read (sc_pma_controller_read),
+ .sc_pma_controller_write (sc_pma_controller_write),
+
+ // internal interface to 'top' hxaui csr block
+ .sc_csr_readdata (sc_csr_readdata),
+ .sc_csr_waitrequest (1'b0), // PCS CSR is always ready
+ .sc_csr_address (sc_csr_address), //5 bit wide
+ .sc_csr_read (sc_csr_read),
+ .sc_csr_write (sc_csr_write)
+ );
+
+ ///////////////////////////////////////////////////////////////////////
+ // PMA Channel Controller - only for HXAUI
+ ///////////////////////////////////////////////////////////////////////
+// add generate for hxaui/sxaui - only use ch_controller for hxaui
+ generate
+ if (interface_type == "Hard XAUI") begin
+ alt_pma_ch_controller_tgx #(
+ .number_of_channels (4),
+ .sync_depth (2),
+ .sys_clk_in_mhz (sys_clk_in_mhz)
+ ) alt_pma_ch_controller_0 (
+ .clk (phy_mgmt_clk),
+ .rst (phy_mgmt_clk_reset),
+ .ch_mgmt_address (sc_pma_ch_controller_address),
+ .ch_mgmt_read (sc_pma_ch_controller_read),
+ .ch_mgmt_readdata (sc_pma_ch_controller_readdata),
+ .ch_mgmt_write (sc_pma_ch_controller_write),
+ .ch_mgmt_writedata (phy_mgmt_writedata),
+ .ch_mgmt_waitrequest (sc_pma_ch_controller_waitrequest),
+ .rx_pma_ready (rx_pma_ready),
+ .tx_pma_ready (tx_ready),
+ .rx_is_lockedtodata (rx_is_lockedtodata_data),
+ .rx_is_lockedtoref (rx_is_lockedtoref_data),
+ .rx_set_locktodata (alt_pma_ch_controller_0_rx_set_locktodata_data),
+ .rx_set_locktoref (alt_pma_ch_controller_0_rx_set_locktoref_data),
+ .rx_seriallpbken (alt_pma_ch_controller_0_rx_seriallpbken_data),
+ .rx_analog_rst (alt_pma_ch_controller_0_rx_analog_rst_data),
+ .tx_digital_rst (alt_pma_ch_controller_0_tx_digital_rst_data),
+ .rx_digital_rst (alt_pma_ch_controller_0_rx_digital_rst_data),
+ .rx_rst_digital (rx_digitalreset), // optional user triggered rx_digitalreset
+ .tx_rst_digital (tx_digitalreset), // optional user triggered tx_digitalreset
+ //reconfig_to_xcvr bit configuration
+ //Bit | Value
+ //-------------------------------------------
+ //3 | offset_cancellation_is_busy |
+ //2 | dprio_load |
+ //1 | dprio_disable |
+ //0 | dprio_in |
+ //-------------------------------------------
+ // .rx_oc_busy (reconfig_to_xcvr[3]), // rx_oc_busy.data
+ .rx_cal_busy (reconfig_to_xcvr[3]), // rx_oc_busy.data
+ .tx_cal_busy (1'b0), // rx_oc_busy.data
+ .pll_locked (pll_locked_data)
+ );
+ end else if (interface_type == "Soft XAUI") begin
+ siv_xcvr_low_latency_phy_nr #(
+ .device_family (device_family),
+ .intended_device_variant ("ANY"),
+ .number_of_channels (4),
+ .number_of_reconfig_interface (reconfig_interfaces),
+ .operation_mode ("DUPLEX"),
+ .phase_comp_fifo_mode ("NONE"),
+ .serialization_factor (20),
+ .data_rate ("3125 Mbps"),
+ .pll_input_frequency ("156.25 MHz"),
+ .number_pll_inclks (1),
+ .pll_inclk_select (0),
+ .pll_type (xaui_pll_type),
+ .starting_channel_number (starting_channel_number),
+ .bonded_mode ("TRUE"),
+ .sys_clk_in_mhz (sys_clk_in_mhz),
+ //.rx_bitslip_en (0),
+ //.tx_bitslip_en (0),
+ //.select_10g_pcs (0),
+ //.tx_use_coreclk (0),
+ //.rx_use_coreclk (0),
+ .gx_analog_power ("AUTO"),
+ .pll_lock_speed ("AUTO"),
+ .tx_analog_power ("AUTO"),
+ .tx_slew_rate ("OFF"),
+ .tx_termination (tx_termination),
+ .tx_common_mode ("0.65V"),
+ .rx_pll_lock_speed ("AUTO"),
+ .rx_common_mode (rx_common_mode),
+ .rx_signal_detect_threshold (2),
+ .rx_ppmselect (32),
+ .rx_termination (rx_termination),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv ((tx_preemp_pretap_inv==1)? "TRUE" : "FALSE"),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv ((tx_preemp_tap_2_inv==1)? "TRUE" : "FALSE"),
+ .tx_vod_selection (tx_vod_selection),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .rx_use_cruclk ("FALSE"),
+ .loopback_mode ("SLB")
+ ) alt_pma_0 (
+ .clk (phy_mgmt_clk),
+ .rst (phy_mgmt_clk_reset),
+ .gx_pdn (alt_pma_controller_0_gx_pdn_data),
+ .ch_mgmt_address (sc_pma_ch_controller_address),
+ .ch_mgmt_read (sc_pma_ch_controller_read),
+ .ch_mgmt_readdata (sc_pma_ch_controller_readdata),
+ .ch_mgmt_write (sc_pma_ch_controller_write),
+ .ch_mgmt_writedata (phy_mgmt_writedata),
+ .ch_mgmt_waitrequest (sc_pma_ch_controller_waitrequest),
+ .cal_blk_clk (phy_mgmt_clk),
+ .cal_blk_pdn (alt_pma_controller_0_cal_blk_pdn_data),
+ .pll_ref_clk (pll_ref_clk),
+ .tx_out_clk (alt_pma_0_tx_out_clk_clk),
+ .tx_parallel_data (sxaui_0_tx_parallel_data_data),
+ .tx_serial_data (xaui_tx_serial_data),
+ .tx_pma_ready (tx_ready),
+ .pll_pdn (alt_pma_controller_0_pll_pdn0_data),
+ .pll_locked (pll_locked_data),
+ .rx_is_lockedtodata (alt_pma_0_rx_is_lockedtodata_data),
+ .rx_is_lockedtoref (),
+ .rx_recovered_clk (alt_pma_0_rx_recovered_clk_clk),
+ .rx_serial_data (xaui_rx_serial_data),
+ .rx_parallel_data (alt_pma_0_rx_parallel_data_data),
+ .rx_cdr_ref_clk (),
+ .rx_pma_ready (rx_pma_ready),
+ .reconfig_clk (phy_mgmt_clk),
+ .reconfig_to_gxb (reconfig_to_xcvr),
+ .reconfig_from_gxb (reconfig_from_xcvr),
+ .rx_rst_digital (rx_digitalreset), //optional user triggered rx_digitalreset
+ .tx_rst_digital (tx_digitalreset), //optional user triggered tx_digitalreset
+ //.tx_bitslip (28'b0),
+ //.tx_coreclk (4'b0),
+ //.rx_offset_cancellation_done (1'b1),
+ //.rx_bitslip (4'b0),
+ //.rx_parallel_data_read (4'b0),
+ //.rx_coreclk (4'b0),
+ //.aeq_to_gxb (96'b0),
+ //.aeq_from_gxb (),
+ .tx_digital_rst (alt_pma_ch_controller_0_tx_digital_rst_data),
+ .rx_digital_rst (alt_pma_ch_controller_0_rx_digital_rst_data)
+ );
+ end
+ // don't instantiate anything if the interface type is invalid
+ endgenerate
+
+ ///////////////////////////////////////////////////////////////////////
+ // PMA Controller
+ ///////////////////////////////////////////////////////////////////////
+ generate
+ if (external_pma_ctrl_reconf == 0) begin
+ alt_pma_controller_tgx #(
+ .number_of_plls (1),
+ .sync_depth (2),
+ .tx_pll_reset_hold_time (20)
+ ) alt_pma_controller_0 (
+ .clk (phy_mgmt_clk),
+ .rst (phy_mgmt_clk_reset),
+ .pma_mgmt_address (sc_pma_controller_address),
+ .pma_mgmt_read (sc_pma_controller_read),
+ .pma_mgmt_readdata (sc_pma_controller_readdata),
+ .pma_mgmt_write (sc_pma_controller_write),
+ .pma_mgmt_writedata (phy_mgmt_writedata),
+ .pma_mgmt_waitrequest (sc_pma_controller_waitrequest),
+ .cal_blk_clk (phy_mgmt_clk),
+ .cal_blk_pdn (alt_pma_controller_0_cal_blk_pdn_data),
+ .tx_pll_ready (),
+ .gx_pdn (alt_pma_controller_0_gx_pdn_data),
+ .pll_pdn (alt_pma_controller_0_pll_pdn0_data),
+ .pll_locked (pll_locked_data)
+ );
+ end else begin
+ assign alt_pma_controller_0_cal_blk_pdn_data = cal_blk_powerdown;
+ assign alt_pma_controller_0_gx_pdn_data = gxb_powerdown;
+ assign alt_pma_controller_0_pll_pdn0_data = pll_powerdown;
+ end
+ endgenerate
+
+
+ ///////////////////////////////////////////////////////////////////////
+ // HXAUI CSR
+ ///////////////////////////////////////////////////////////////////////
+// should be consistent across all device families and interface types
+// -might need a generate statement for some of the connections that don't exist between hxaui/sxaui
+ hxaui_csr hxaui_csr (
+ .clk (phy_mgmt_clk),
+ .reset (phy_mgmt_clk_reset),
+ .address (sc_csr_address),
+ .byteenable (4'b1111), // .byteenable (Tie byteenable to all 1s)
+ .read (sc_csr_read),
+ .readdata (sc_csr_readdata),
+ .write (sc_csr_write),
+ .writedata (phy_mgmt_writedata),
+ .rx_patterndetect (rx_patterndetect_data),
+ .rx_syncstatus (rx_syncstatus_data),
+ .rx_runningdisp (rx_runningdisp_data),
+ .rx_errdetect (rx_errdetect_data),
+ .rx_disperr (rx_disperr_data),
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error_data),
+ .rx_rlv (rx_rlv_data),
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted_data),
+ .rx_rmfifodatainserted (rx_rmfifodatainserted_data),
+ .rx_rmfifoempty (rx_rmfifoempty_data),
+ .rx_rmfifofull (rx_rmfifofull_data),
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error_data),
+ .r_rx_invpolarity (hxaui_csr_r_rx_invpolarity_data),
+ .r_tx_invpolarity (hxaui_csr_r_tx_invpolarity_data),
+ .r_rx_digitalreset (hxaui_csr_r_rx_digitalreset_data),
+ .r_tx_digitalreset (hxaui_csr_r_tx_digitalreset_data),
+ .simulation_flag (hxaui_csr_simulation_flag_data) // only for soft_xaui
+ );
+
+
+ ///////////////////////////////////////////////////////////////////////
+ // HXAUI - Interface to alt4gxb megafunction block
+ ///////////////////////////////////////////////////////////////////////
+// need to add generate to pick between sxaui and hxaui
+ generate
+ if (interface_type == "Hard XAUI") begin
+ (* ALTERA_ATTRIBUTE = {"-name SDC_STATEMENT \"set_false_path -from [get_registers *hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component*fifo*flow] -to [get_registers *xaui_phy*hxaui_csr*tx_phase_comp_fifo_error_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers *hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component*] -to [get_registers *xaui_phy*hxaui_csr*rx*_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*siv_xcvr_xaui*hxaui_csr*hxaui_csr_reset0q[*]}] -to [get_registers {*xaui_phy*hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component|*digitalreset*}]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*siv_xcvr_xaui*alt_pma_ch_controller_0*rc*}] -to [get_registers {*xaui_phy*hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component|*digitalreset*}]\""} *)
+ hxaui #(
+ .device_family (device_family),
+ .starting_channel_number (starting_channel_number),
+ .xaui_pll_type (xaui_pll_type),
+ .use_control_and_status_ports (use_control_and_status_ports),
+ .external_pma_ctrl_reconf (external_pma_ctrl_reconf),
+ .tx_termination (tx_termination),
+ .rx_termination (rx_termination),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv (tx_preemp_pretap_inv),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv (tx_preemp_tap_2_inv),
+ .tx_vod_selection (tx_vod_selection),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .rx_common_mode (rx_common_mode)
+ ) hxaui_0 (
+ .xgmii_tx_clk (xgmii_tx_clk),
+ .xgmii_tx_dc (xgmii_tx_dc),
+ .xgmii_rx_clk (xgmii_rx_clk),
+ .xgmii_rx_dc (xgmii_rx_dc),
+ .refclk (pll_ref_clk),
+ .xaui_tx_serial (xaui_tx_serial_data),
+ .xaui_rx_serial (xaui_rx_serial_data),
+ .rx_analogreset (rx_analogreset), // use_cs_ports, input
+ .rx_digitalreset (alt_pma_ch_controller_0_rx_digital_rst_data),
+ .tx_digitalreset (alt_pma_ch_controller_0_tx_digital_rst_data),
+ .rx_channelaligned (rx_channelaligned), // use_cs_ports, output
+ .rx_invpolarity (rx_invpolarity), // use_cs_ports, input
+ .rx_set_locktodata (rx_set_locktodata), // use_cs_ports, input
+ .rx_set_locktoref (rx_set_locktoref), // use_cs_ports, input
+ .rx_seriallpbken (rx_seriallpbken), // use_cs_ports, input
+ .tx_invpolarity (tx_invpolarity), // use_cs_ports, input
+ .rx_is_lockedtodata (rx_is_lockedtodata_data), // use_cs_ports, output
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error_data), // use_cs_ports, output
+ .rx_is_lockedtoref (rx_is_lockedtoref_data), // use_cs_ports, output
+ .rx_rlv (rx_rlv_data), // use_cs_ports, output
+ .rx_rmfifoempty (rx_rmfifoempty_data), // use_cs_ports, output
+ .rx_rmfifofull (rx_rmfifofull_data), // use_cs_ports, output
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error_data), // use_cs_ports, output
+ .rx_disperr (rx_disperr_data), // use_cs_ports, output
+ .rx_errdetect (rx_errdetect_data), // use_cs_ports, output
+ .rx_patterndetect (rx_patterndetect_data), // use_cs_ports, output
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted_data), // use_cs_ports, output
+ .rx_rmfifodatainserted (rx_rmfifodatainserted_data), // use_cs_ports, output
+ .rx_runningdisp (rx_runningdisp_data), // use_cs_ports, output
+ .rx_syncstatus (rx_syncstatus_data), // use_cs_ports, output
+ .reconfig_clk (phy_mgmt_clk),
+ .reconfig_togxb (reconfig_to_xcvr), // external_pma_ctrl_reconf
+ .reconfig_fromgxb (reconfig_from_xcvr[16:0]), // external_pma_ctrl_reconf
+ .rx_recovered_clk (alt_pma_0_rx_recovered_clk_clk),
+ .cal_blk_clk (phy_mgmt_clk),
+ .cal_blk_powerdown (1'b0), // not used, should remove
+ .gxb_powerdown (1'b0), // not used, should remove
+ .pll_powerdown (1'b0), // not used, should remove
+ .pll_locked (pll_locked_data),
+ .r_cal_blk_powerdown (alt_pma_controller_0_cal_blk_pdn_data),
+ .r_gxb_powerdown (alt_pma_controller_0_gx_pdn_data),
+ .r_pll_powerdown (alt_pma_controller_0_pll_pdn0_data),
+ .r_rx_set_locktodata (alt_pma_ch_controller_0_rx_set_locktodata_data),
+ .r_rx_set_locktoref (alt_pma_ch_controller_0_rx_set_locktoref_data),
+ .r_rx_seriallpbken (alt_pma_ch_controller_0_rx_seriallpbken_data),
+ .r_rx_analogreset (alt_pma_ch_controller_0_rx_analog_rst_data),
+ .r_rx_digitalreset (hxaui_csr_r_rx_digitalreset_data),
+ .r_tx_digitalreset (hxaui_csr_r_tx_digitalreset_data),
+ .r_rx_invpolarity (hxaui_csr_r_rx_invpolarity_data),
+ .r_tx_invpolarity (hxaui_csr_r_tx_invpolarity_data)
+ );
+ assign sxaui_rst_done = 1'b1; // if using hard xaui, assign this to 1 to always be ready
+ end else if (interface_type == "Soft XAUI") begin
+ (* ALTERA_ATTRIBUTE = {" -name SDC_STATEMENT \"set_false_path -from [get_registers {*sxaui_0*alt_soft_xaui_pcs*xaui_rx*disp_err_delay[*]}] -to [get_registers *xaui_phy*hxaui_csr*rx*_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*sxaui_0*alt_soft_xaui_pcs*xaui_rx*pcs_rx_syncstatus[*]}] -to [get_registers *xaui_phy*hxaui_csr*rx*_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*sxaui_0*alt_soft_xaui_pcs*xaui_rx*channel_align_synchclk[*]}] -to [get_registers *xaui_phy*hxaui_csr*rx*_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*siv_xcvr_xaui*hxaui_csr*hxaui_csr_reset0q[1]}] -to [get_registers *sxaui_0*alt_soft_xaui_pcs*tx_reset*] \" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*siv_xcvr_xaui*hxaui_csr*hxaui_csr_reset0q[1]}] -to [get_registers *sxaui_0*alt_soft_xaui_pcs*rx_reset*] \" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*sxaui_0*alt_soft_xaui_pcs*xaui_rx*rd_ptr_latched_del[*]}] -to [get_registers *sxaui_0*alt_soft_xaui_pcs*xaui_rx*rd_ptr_wr[*]]\""} *)
+ sxaui #(
+ .starting_channel_number (starting_channel_number),
+ .xaui_pll_type (xaui_pll_type),
+ .use_control_and_status_ports (use_control_and_status_ports)
+ ) sxaui_0 (
+ .xgmii_tx_clk (xgmii_tx_clk), // xgmii_tx_clk.clk
+ .xgmii_tx_dc (xgmii_tx_dc), // xgmii_tx_dc.data
+ .xgmii_rx_clk (xgmii_rx_clk), // xgmii_rx_clk.clk
+ .xgmii_rx_dc (xgmii_rx_dc), // xgmii_rx_dc.data
+ .refclk (pll_ref_clk), // refclk.clk
+ .mgmt_clk (phy_mgmt_clk), // mgmt_clk.clk
+ .tx_out_clk (alt_pma_0_tx_out_clk_clk), // tx_out_clk.clk
+ .rx_recovered_clk (alt_pma_0_rx_recovered_clk_clk), // rx_recovered_clk.clk
+ .tx_parallel_data (sxaui_0_tx_parallel_data_data), // tx_parallel_data.data
+ .rx_parallel_data (alt_pma_0_rx_parallel_data_data), // rx_parallel_data.data
+ .rx_is_lockedtodata (alt_pma_0_rx_is_lockedtodata_data), // rx_is_lockedtodata.data
+ .rx_digitalreset (alt_pma_ch_controller_0_rx_digital_rst_data[0] ), // rx_digitalreset from cahnnel controller in alt_pma
+ .tx_digitalreset (alt_pma_ch_controller_0_tx_digital_rst_data[0] ), // tx_digitalreset from cahnnel controller in alt_pma
+ .pll_locked (pll_locked_data), // pll_locked.data
+ .rx_syncstatus (rx_syncstatus_data), // rx_syncstatus.data
+ .rx_channelaligned (rx_channelaligned), // rx_channelaligned.data
+ .rx_disperr (rx_disperr_data), // rx_disperr.data
+ .rx_errdetect (rx_errdetect_data), // rx_errdetect.data
+ .r_rx_digitalreset (hxaui_csr_r_rx_digitalreset_data), // r_rx_digitalreset.data
+ .r_tx_digitalreset (hxaui_csr_r_tx_digitalreset_data), // r_tx_digitalreset.data
+ .pma_stat_rst_done (sxaui_rst_done), // soft reset done
+ .simulation_flag (hxaui_csr_simulation_flag_data) // simulation_flag.data
+ );
+ assign rx_patterndetect_data = 8'b0; // not supported by soft PCS
+ assign rx_runningdisp_data = 8'b0; // not supported by soft PCS
+ assign rx_phase_comp_fifo_error_data = 4'b0; // not supported by soft PCS
+ assign rx_rlv_data = 4'b0; // not supported by soft PCS
+ assign rx_rmfifodatadeleted_data = 8'b0; // not supported by soft PCS
+ assign rx_rmfifodatainserted_data = 8'b0; // not supported by soft PCS
+ assign rx_rmfifoempty_data = 4'b0; // not supported by soft PCS
+ assign rx_rmfifofull_data = 4'b0; // not supported by soft PCS
+ assign tx_phase_comp_fifo_error_data = 4'b0; // not supported by soft PCS
+ assign hxaui_csr_r_rx_invpolarity_data = 4'b0; // not supported by soft PCS
+ assign hxaui_csr_r_tx_invpolarity_data = 4'b0; // not supported by soft PCS
+ assign rx_is_lockedtodata_data = 4'b0; // not supported by soft PCS
+ assign rx_is_lockedtoref_data = 4'b0; // not supported by soft PCS
+ end
+ // don't instantiate anything if the interface type is invalid
+ endgenerate
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/sxaui.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/sxaui.v
new file mode 100644
index 0000000000000000000000000000000000000000..d0832e15d12cf3ef8977dcce01ac2f75f7947cae
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft/sxaui.v
@@ -0,0 +1,230 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//-----------------------------------------------------------------------------
+//
+// Description: soft xaui pcs
+//
+// Authors: ishimony 14-Jan-2009
+//
+// Copyright (c) Altera Corporation 1997 - 2009
+// All rights reserved.
+//
+//
+//-----------------------------------------------------------------------------
+
+`timescale 1 ps / 1 ps
+
+module sxaui(
+ xgmii_tx_clk, xgmii_tx_dc, xgmii_rx_clk, xgmii_rx_dc, refclk, mgmt_clk, tx_out_clk,
+ rx_recovered_clk, tx_parallel_data, rx_parallel_data, rx_is_lockedtodata,
+ rx_digitalreset, tx_digitalreset, pll_locked,
+ rx_syncstatus, rx_channelaligned, rx_disperr, rx_errdetect,
+ r_rx_digitalreset, r_tx_digitalreset, pma_stat_rst_done, simulation_flag
+); // module sxaui
+
+// parameters --------------------------------------------------------------
+parameter starting_channel_number = 0;
+parameter xaui_pll_type = "CMU"; // values: CMU/LCTANK
+parameter use_control_and_status_ports = "true";
+
+// ports -------------------------------------------------------------------
+
+// xgmii
+input xgmii_tx_clk;
+input [71:0] xgmii_tx_dc;
+output xgmii_rx_clk;
+output [71:0] xgmii_rx_dc;
+
+// pma
+input refclk;
+input mgmt_clk;
+input [3:0] tx_out_clk;
+input [3:0] rx_recovered_clk;
+output [79:0] tx_parallel_data;
+input [79:0] rx_parallel_data;
+input [3:0] rx_is_lockedtodata;
+
+// ctrl_stat: control and status
+input rx_digitalreset;
+input tx_digitalreset; //nc in sxaui
+input pll_locked;
+output [7:0] rx_syncstatus;
+output rx_channelaligned;
+output [7:0] rx_disperr;
+output [7:0] rx_errdetect;
+
+// register file version
+input r_rx_digitalreset;
+input r_tx_digitalreset;
+output pma_stat_rst_done;
+
+input simulation_flag; // '1' shortens reset and loss_timer length
+
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+
+// ports -------------------------------------------------------------------
+wire xgmii_tx_clk;
+wire [71:0] xgmii_tx_dc;
+wire [71:0] xgmii_rx_dc;
+wire xgmii_rx_clk;
+wire [79:0] tx_parallel_data;
+wire [79:0] rx_parallel_data;
+wire [3:0] tx_out_clk;
+wire [3:0] rx_recovered_clk;
+wire [3:0] rx_is_lockedtodata;
+wire rx_digitalreset;
+wire tx_digitalreset;
+wire pll_locked;
+wire [7:0] rx_syncstatus;
+wire rx_channelaligned;
+wire [7:0] rx_disperr;
+wire [7:0] rx_errdetect;
+wire simulation_flag;
+
+// locals ------------------------------------------------------------------
+wire [7:0] xgmii_tx_c;
+wire [63:0] xgmii_tx_d;
+wire [7:0] xgmii_rx_c;
+wire [63:0] xgmii_rx_d;
+
+// local version
+wire l_rx_digitalreset;
+
+// register file version
+wire r_rx_digitalreset;
+wire r_tx_digitalreset;
+
+// soft xaui signals -------------------------------------------------------
+wire [63:0] xgmii_tx_datain; // input
+wire [7:0] xgmii_tx_ctrlin; // input
+wire [63:0] xgmii_rx_dataout; // output
+wire [7:0] xgmii_rx_ctrlout; // output
+wire reset_n; // input
+wire [3:0] pma_tx_dataout; // output
+//wire pma_gxb_powerdown; // input
+wire pma_pll_inclk; // input
+wire pma_reconfig_clk; // input
+wire [3:0] pma_reconfig_togxb; // input
+wire [16:0] pma_reconfig_fromgxb; // output
+wire pma_pll_locked; // output
+wire pma_stat_rst_done; // output
+wire [3:0] pma_rx_clkout; // output nc: ///
+wire [3:0] pma_tx_clkout; // output nc: ///
+wire pma_rx_analogreset;
+wire [79:0] pma_pcs_tx_data; //Data from TX soft PCS to PMA
+wire [79:0] pma_pcs_rx_data; //Data from PMA to RX soft PCS
+wire [3:0] pma_rx_is_lockedtodata;
+
+// output: this is high per lane if the synchronization has been met. As we
+// only have 4 lanes, we will double their value
+wire [7:0] pcs_rx_syncstatus;
+// output: this is high if the channel aligner (resynch) has aligned all
+// the lanes and the correct number of align characters have been received
+wire pcs_rx_channelaligned;
+// output: this is high if a disparity error has occured
+wire [7:0] pcs_rx_disperr;
+// output: this is high if an invalid character has been detected.
+wire [7:0] pcs_rx_errdetect;
+
+// body --------------------------------------------------------------------
+
+// Convert to/from Avalon Streaming Interface single bus to data + control
+genvar g;
+generate
+ for (g = 0; g < 8; g = g + 1) begin : st_to_dc_b
+ assign xgmii_tx_d [g*8 +: 8] = xgmii_tx_dc[g*9 +: 8];
+ assign xgmii_tx_c [g] = xgmii_tx_dc[g*9 + 8];
+ assign xgmii_rx_dc[g*9 +: 8] = xgmii_rx_d [g*8 +: 8];
+ assign xgmii_rx_dc[g*9 + 8] = xgmii_rx_c [g];
+ end
+endgenerate
+
+// Default values in case ports are not and without control/status registers
+generate
+ if (use_control_and_status_ports == "true") begin: use_cs_ports_true
+ assign l_rx_digitalreset = rx_digitalreset | r_rx_digitalreset;
+ end else begin: use_cs_ports_false
+ assign l_rx_digitalreset = r_rx_digitalreset;
+ end
+endgenerate
+
+// soft xaui ---------------------------------------------------------------
+
+ // translate signal names
+assign xgmii_tx_datain = xgmii_tx_d;
+assign xgmii_tx_ctrlin = xgmii_tx_c;
+assign xgmii_rx_d = xgmii_rx_dataout;
+assign xgmii_rx_c = xgmii_rx_ctrlout;
+assign pma_pll_inclk = refclk;
+
+assign tx_parallel_data = pma_pcs_tx_data;
+assign pma_pcs_rx_data = rx_parallel_data;
+assign pma_tx_clkout = tx_out_clk;
+assign pma_rx_clkout = rx_recovered_clk;
+assign pma_rx_is_lockedtodata = rx_is_lockedtodata;
+
+assign reset_n = ~l_rx_digitalreset;
+assign pma_pll_locked = pll_locked;
+
+assign rx_syncstatus = pcs_rx_syncstatus;
+assign rx_channelaligned = pcs_rx_channelaligned;
+assign rx_disperr = pcs_rx_disperr;
+assign rx_errdetect = pcs_rx_errdetect;
+
+//assign pma_gxb_powerdown = 1'b0;
+
+// soft pcs
+alt_soft_xaui_pcs alt_soft_xaui_pcs(
+ .xgmii_tx_datain (xgmii_tx_datain), // i
+ .xgmii_tx_ctrlin (xgmii_tx_ctrlin), // i
+ .xgmii_rx_dataout (xgmii_rx_dataout), // o
+ .xgmii_rx_ctrlout (xgmii_rx_ctrlout), // o
+ .xgmii_tx_clk (xgmii_tx_clk), // i - must be tied to xgmii_rx_clk at top level, only for interface consistency does this exist
+ .sysclk (xgmii_rx_clk), // o
+ .reset_n (reset_n), // i
+// .pma_rx_datain (pma_rx_datain), // i
+// .pma_tx_dataout (pma_tx_dataout), // o
+// .pma_cal_blk_clk (pma_cal_blk_clk), // i
+// .pma_gxb_powerdown (pma_gxb_powerdown), // i
+ .pma_pll_inclk (pma_pll_inclk), // i
+// .pma_reconfig_clk (pma_reconfig_clk), // i
+// .pma_reconfig_togxb (pma_reconfig_togxb), // i
+// .pma_reconfig_fromgxb (pma_reconfig_fromgxb), // o
+ .pma_pll_locked (pma_pll_locked), // i
+// .pma_rx_pll_locked (pma_rx_is_lockedtoref), // i
+ .pma_rx_freqlocked (pma_rx_is_lockedtodata), // i
+ .pma_stat_rst_done (pma_stat_rst_done), // o
+ .pma_rx_clkout (pma_rx_clkout), // i
+ .pma_tx_clkout (pma_tx_clkout), // i
+ .pcs_rx_syncstatus (pcs_rx_syncstatus), // o
+ .pcs_rx_channelaligned (pcs_rx_channelaligned), // o
+ .pcs_rx_disperr (pcs_rx_disperr), // o
+ .pcs_rx_errdetect (pcs_rx_errdetect), // o
+ .pma_rx_analogreset (pma_rx_analogreset), // o
+ .pma_pcs_tx_data (pma_pcs_tx_data), // o
+ .pma_pcs_rx_data (pma_pcs_rx_data), // i
+ .simulation_flag (simulation_flag) // i
+); // module alt_soft_xaui_pcs
+defparam
+ alt_soft_xaui_pcs.p_family_id = "df_stratixIV",
+ alt_soft_xaui_pcs.p_USE_GXB_RECONFIG = 0,
+ alt_soft_xaui_pcs.starting_channel_number= starting_channel_number,
+ alt_soft_xaui_pcs.reconfig_togxb_port_size = 4,
+ alt_soft_xaui_pcs.reconfig_fromgxb_port_size = 17,
+ alt_soft_xaui_pcs.p_SOFTXAUI_PLL = xaui_pll_type; // CMU/LCTANK
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/aldec_files.txt b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/aldec_files.txt
new file mode 100644
index 0000000000000000000000000000000000000000..4c25ca083f6ec1f6f001faabdca100f7abb426e2
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/aldec_files.txt
@@ -0,0 +1,59 @@
+./altera_xcvr_functions.sv
+./alt_pma_functions.sv
+./altera_xcvr_xaui.sv
+./hxaui_csr_h.sv
+./hxaui_csr.sv
+./alt_xcvr_mgmt2dec_phyreconfig.sv
+./alt_xcvr_mgmt2dec_xaui.sv
+./alt_pma_ch_controller_tgx.v
+./alt_pma_controller_tgx.v
+./alt_reset_ctrl_lego.sv
+./alt_reset_ctrl_tgx_cdrauto.sv
+./alt_xcvr_resync.sv
+./alt_xcvr_csr_common_h.sv
+./alt_xcvr_csr_common.sv
+./alt_xcvr_csr_pcs8g_h.sv
+./alt_xcvr_csr_pcs8g.sv
+./alt_xcvr_csr_selector.sv
+./alt_xcvr_mgmt2dec.sv
+./altera_wait_generate.v
+./aldec/alt_soft_xaui_pcs.v
+./aldec/alt_soft_xaui_reset.v
+./aldec/alt_soft_xaui_rx.v
+./aldec/alt_soft_xaui_rx_8b10b_dec.v
+./aldec/alt_soft_xaui_rx_channel_synch.v
+./aldec/alt_soft_xaui_rx_deskew.v
+./aldec/alt_soft_xaui_rx_deskew_channel.v
+./aldec/alt_soft_xaui_rx_deskew_ram.v
+./aldec/alt_soft_xaui_rx_invalid_code_det.v
+./aldec/alt_soft_xaui_rx_parity.v
+./aldec/alt_soft_xaui_rx_parity_4b.v
+./aldec/alt_soft_xaui_rx_parity_6b.v
+./aldec/alt_soft_xaui_rx_rate_match.v
+./aldec/alt_soft_xaui_rx_rate_match_ram.v
+./aldec/alt_soft_xaui_rx_rl_chk_6g.v
+./aldec/alt_soft_xaui_rx_sm.v
+./aldec/alt_soft_xaui_tx.v
+./aldec/alt_soft_xaui_tx_8b10b_enc.v
+./aldec/alt_soft_xaui_tx_idle_conv.v
+./aldec/l_modules.v
+./aldec/serdes_4_unit_lc_siv.v
+./aldec/serdes_4_unit_siv.v
+./aldec/serdes_4unit.v
+./sxaui.v
+./siv_xcvr_low_latency_phy_nr.sv
+./siv_xcvr_xaui.sv
+./alt4gxb_vo.v
+./alt_xcvr_reconfig_h.sv
+./alt_xcvr_reconfig_siv.sv
+./alt_xcvr_reconfig_analog.sv
+./alt_xcvr_reconfig_analog_tgx.v
+./alt_xcvr_reconfig_offset_cancellation.sv
+./alt_xcvr_reconfig_offset_cancellation_tgx.v
+./alt_xcvr_reconfig_eyemon_tgx.sv
+./alt_xcvr_reconfig_dfe_tgx.sv
+./alt_xcvr_reconfig_basic_tgx.v
+./alt_mutex_acq.v
+./alt_dprio.v
+./alt_xcvr_arbiter.sv
+./alt_xcvr_m2s.sv
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt4gxb_vo.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt4gxb_vo.v
new file mode 100644
index 0000000000000000000000000000000000000000..18c78e857a3f7b1886bc4a1d693468380383c42a
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt4gxb_vo.v
@@ -0,0 +1,23996 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Copyright (C) 1991-2010 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions
+// and other software and tools, and its AMPP partner logic
+// functions, and any output files from any of the foregoing
+// (including device programming or simulation files), and any
+// associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License
+// Subscription Agreement, Altera MegaCore Function License
+// Agreement, or other applicable license agreement, including,
+// without limitation, that your use is for the sole purpose of
+// programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus II"
+// VERSION "Version 9.1 Internal Build 294 12/28/2009 Service Pack 1 SJ Full Version"
+
+// DATE "12/30/2009 13:05:46"
+
+//
+// Device: Altera EP4SGX530NF45C2 Package FBGA1932
+//
+
+//
+// This Verilog file should be used for ModelSim-Altera (Verilog) only
+//
+
+`timescale 1 ps/ 1 ps
+
+module alt4gxb #(
+ parameter
+ cbx_hdl_language = "Verilog",
+ enable_pma_xn_bonding = "TRUE",
+ cmu_pll_inclk_log_index = 0,
+ cmu_pll_log_index = 0,
+ device_family = "Stratix IV",
+ effective_data_rate = "3125 Mbps",
+ enable_lc_tx_pll = "TRUE",
+ enable_pma_direct = "TRUE",
+ enable_pll_inclk_drive_rx_cru = "TRUE",
+ equalizer_ctrl_a_setting = 0,
+ equalizer_ctrl_b_setting = 0,
+ equalizer_ctrl_c_setting = 0,
+ equalizer_ctrl_d_setting = 0,
+ equalizer_ctrl_v_setting = 0,
+ equalizer_dcgain_setting = 0, //0-4
+ gen_reconfig_pll = "FALSE",
+ gx_channel_type = "AUTO",
+ gxb_analog_power = "AUTO",
+ gxb_powerdown_width = 1,
+ input_clock_frequency = "156.25 MHz",
+ intended_device_variant = "ANY",
+ loopback_mode = "NONE",
+ number_of_channels = 2,
+ number_of_quads = 1,
+ operation_mode = "DUPLEX", //TX, RX, DUPLEX
+ pll_control_width = 1,
+ protocol = "BASIC",
+ use_global_clk_divider = "TRUE",
+ receiver_termination = "OCT_100_OHMS", //OCT_85_OHMS,OCT_100_OHMS,OCT_120_OHMS,OCT_150_OHMS
+ reconfig_calibration = "TRUE",
+ reconfig_dprio_mode = 19,
+ reconfig_fromgxb_port_width = 17,
+ reconfig_pll_inclk_width = 1,//reconfig may need more than one reference clock
+ reconfig_protocol = "BASIC",
+ reconfig_togxb_port_width = 4,
+ rx_use_clkout = "TRUE",
+ rx_use_cruclk = "TRUE",
+ rx_use_coreclk = "FALSE",
+ rx_channel_width = 16,//8,10,16,20,32,40
+ rx_common_mode = "0.82v", //TRISTATE|0.82v|1.1v
+ rx_cru_bandwidth_type = "AUTO",//AUTO|LOW|MEDIUM|HIGH
+ rx_digitalreset_port_width = 2,
+ rx_enable_lock_to_data_sig = "true",
+ rx_enable_lock_to_refclk_sig = "true",
+ rx_ppmselect = 32,
+ rx_reconfig_clk_scheme = "indv_clk_source",
+ rx_signal_detect_threshold = 2,
+ rx_use_deserializer_double_data_mode = "TRUE",
+ rx_use_double_data_mode = "TRUE",
+ starting_channel_number = 0,//0,4,8,12 ...
+ transmitter_termination = "OCT_100_OHMS",//OCT_85_OHMS,OCT_100_OHMS,OCT_120_OHMS,OCT_150_OHMS
+ tx_dwidth_factor = "TRUE",
+ tx_analog_power = "AUTO",//AUTO|1.4V|1.5V
+ tx_channel_width = 16,//8,10,16,20,32,40
+ tx_clkout_width = 2,
+ tx_common_mode = "0.65V", //"0.65V"
+ tx_pll_bandwidth_type = "AUTO",//AUTO|LOW|MEDIUM|HIGH
+ tx_pll_inclk0_period = 100,
+ tx_pll_type = "CMU",//ATX|CMU
+ tx_reconfig_clk_scheme = "tx_ch0_clk_source",
+ tx_slew_rate = "LOW",//AUTO,LOW,MEDIUM,HIGH
+ tx_transmit_protocol = "basic",
+ tx_use_coreclk = "false",
+ tx_use_double_data_mode = "TRUE",
+ tx_use_serializer_double_data_mode = "TRUE",
+ preemphasis_ctrl_pretap_setting = 3,
+ preemphasis_ctrl_pretap_inv_setting = "false",
+ preemphasis_ctrl_1stposttap_setting = 2,
+ preemphasis_ctrl_2ndposttap_setting = 1, //??
+ preemphasis_ctrl_2ndposttap_inv_setting = "false",
+ use_calibration_block = "TRUE",
+ vod_ctrl_setting = 1,//0-7
+ tx_digitalreset_port_width = 2,
+ rx_use_align_state_machine = "true",//must have
+ tx_datapath_low_latency_mode = "true",
+ rx_use_deskew_fifo = "false",
+ rx_word_aligner_num_byte = 2,
+ rx_rate_match_fifo_mode = "none",
+ tx_enable_bit_reversal = "false",
+ tx_enable_self_test_mode = "false",
+ tx_flip_tx_in = "false",
+ rx_dwidth_factor = "TRUE",
+ rx_8b_10b_mode = "none",
+ rx_allow_align_polarity_inversion = "false",
+ rx_allow_pipe_polarity_inversion = "false",
+ rx_bitslip_enable = "true",
+ tx_bitslip_enable = "false",
+ rx_byte_ordering_mode = "none",
+ rx_enable_self_test_mode = "false",
+ rx_flip_rx_out = "false",
+ rx_force_signal_detect = "true",
+ rx_phfiforegmode = "false",
+ rx_datapath_low_latency_mode = "true",
+ rx_datapath_protocol = "basic",
+ rx_enable_bit_reversal = "false",
+ tx_use_external_termination= "false",
+ rx_use_external_termination= "false",
+ rx_enable_deep_align_byte_swap = "false"
+) (
+ rx_locktodata,
+ rx_analogreset,
+ rx_seriallpbken,
+ tx_digitalreset,
+ rx_digitalreset,
+ rx_locktorefclk,
+ rst,
+ clk,
+ ch_ctrl_address,
+ ch_ctrl_read,
+ ch_ctrl_readdata,
+ ch_ctrl_write,
+ ch_ctrl_writedata,
+ cal_blk_clk,
+ cal_blk_powerdown,
+ gxb_powerdown,
+ pll_powerdown,
+ pll_locked,
+ reconfig_clk,
+ reconfig_togxb,
+ reconfig_fromgxb,
+ aeq_to_gxb,
+ aeq_from_gxb,
+ pll_inclk,
+ rx_cruclk,
+ tx_datain,
+ tx_dataout,
+ tx_clkout,
+ rx_datain,
+ rx_dataout,
+ rx_clkout,
+ rx_freqlocked,
+ rx_pll_locked);
+input [31:0] rx_locktodata;
+input [31:0] rx_analogreset;
+input [31:0] rx_seriallpbken;
+input [31:0] tx_digitalreset;
+input [31:0] rx_digitalreset;
+input [31:0] rx_locktorefclk;
+input rst;
+input clk;
+input [2:0] ch_ctrl_address;
+input ch_ctrl_read;
+output [31:0] ch_ctrl_readdata;
+input ch_ctrl_write;
+input [31:0] ch_ctrl_writedata;
+input cal_blk_clk;
+input cal_blk_powerdown;
+input gxb_powerdown;
+input pll_powerdown;
+output pll_locked;
+input reconfig_clk;
+input [3:0] reconfig_togxb;
+output [67:0] reconfig_fromgxb;
+input [95:0] aeq_to_gxb;
+output [31:0] aeq_from_gxb;
+input [0:0] pll_inclk;
+input [3:0] rx_cruclk;
+input [79:0] tx_datain;
+output [3:0] tx_dataout;
+output [3:0] tx_clkout;
+input [3:0] rx_datain;
+output [79:0] rx_dataout;
+output [3:0] rx_clkout;
+output [3:0] rx_freqlocked;
+output [3:0] rx_pll_locked;
+
+// Design Ports Information
+// rx_locktodata[4] => Location: PIN_R13, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[5] => Location: PIN_F37, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[6] => Location: PIN_AH6, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[7] => Location: PIN_C14, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[8] => Location: PIN_W14, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[9] => Location: PIN_AT6, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[10] => Location: PIN_AC8, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[11] => Location: PIN_E13, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[12] => Location: PIN_AN11, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[13] => Location: PIN_G25, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[14] => Location: PIN_BB22, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[15] => Location: PIN_AU20, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[16] => Location: PIN_L11, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[17] => Location: PIN_R25, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[18] => Location: PIN_N34, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[19] => Location: PIN_L7, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[20] => Location: PIN_C25, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[21] => Location: PIN_BB23, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[22] => Location: PIN_AV18, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[23] => Location: PIN_T27, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[24] => Location: PIN_D20, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[25] => Location: PIN_AN14, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[26] => Location: PIN_AR13, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[27] => Location: PIN_AT11, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[28] => Location: PIN_Y12, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[29] => Location: PIN_J40, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[30] => Location: PIN_H38, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[31] => Location: PIN_AN24, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[4] => Location: PIN_N18, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[5] => Location: PIN_BC13, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[6] => Location: PIN_W31, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[7] => Location: PIN_D14, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[8] => Location: PIN_E32, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[9] => Location: PIN_H37, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[10] => Location: PIN_AT5, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[11] => Location: PIN_Y15, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[12] => Location: PIN_V9, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[13] => Location: PIN_E39, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[14] => Location: PIN_BC11, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[15] => Location: PIN_BA22, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[16] => Location: PIN_AM24, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[17] => Location: PIN_R28, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[18] => Location: PIN_K31, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[19] => Location: PIN_P22, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[20] => Location: PIN_AW15, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[21] => Location: PIN_K32, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[22] => Location: PIN_P8, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[23] => Location: PIN_H13, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[24] => Location: PIN_M9, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[25] => Location: PIN_F35, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[26] => Location: PIN_BD16, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[27] => Location: PIN_A23, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[28] => Location: PIN_T33, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[29] => Location: PIN_AB9, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[30] => Location: PIN_B14, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[31] => Location: PIN_AT13, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[0] => Location: PIN_J16, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[1] => Location: PIN_AK20, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[2] => Location: PIN_N40, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[3] => Location: PIN_AE8, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[4] => Location: PIN_AV13, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[5] => Location: PIN_E19, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[6] => Location: PIN_AD39, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[7] => Location: PIN_A25, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[8] => Location: PIN_BC19, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[9] => Location: PIN_AW17, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[10] => Location: PIN_C18, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[11] => Location: PIN_BD18, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[12] => Location: PIN_AK21, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[13] => Location: PIN_AV20, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[14] => Location: PIN_P9, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[15] => Location: PIN_R17, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[16] => Location: PIN_B23, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[17] => Location: PIN_AN26, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[18] => Location: PIN_AP6, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[19] => Location: PIN_U39, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[20] => Location: PIN_U14, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[21] => Location: PIN_AK24, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[22] => Location: PIN_E17, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[23] => Location: PIN_C26, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[24] => Location: PIN_M10, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[25] => Location: PIN_E7, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[26] => Location: PIN_AP17, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[27] => Location: PIN_K34, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[28] => Location: PIN_V36, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[29] => Location: PIN_AN20, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[30] => Location: PIN_M17, I/O Standard: 2.5 V, Current Strength: Default
+// rx_seriallpbken[31] => Location: PIN_AJ13, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[0] => Location: PIN_BA12, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[1] => Location: PIN_AB11, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[2] => Location: PIN_AC6, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[3] => Location: PIN_V8, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[4] => Location: PIN_M12, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[5] => Location: PIN_BC23, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[6] => Location: PIN_AW21, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[7] => Location: PIN_AY20, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[8] => Location: PIN_E25, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[9] => Location: PIN_C28, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[10] => Location: PIN_AJ5, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[11] => Location: PIN_N22, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[12] => Location: PIN_BA13, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[13] => Location: PIN_G10, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[14] => Location: PIN_D19, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[15] => Location: PIN_L40, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[16] => Location: PIN_AD7, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[17] => Location: PIN_AA9, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[18] => Location: PIN_AJ8, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[19] => Location: PIN_N16, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[20] => Location: PIN_T23, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[21] => Location: PIN_P34, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[22] => Location: PIN_V37, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[23] => Location: PIN_C12, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[24] => Location: PIN_E22, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[25] => Location: PIN_AU22, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[26] => Location: PIN_P6, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[27] => Location: PIN_P35, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[28] => Location: PIN_R24, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[29] => Location: PIN_AN6, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[30] => Location: PIN_A17, I/O Standard: 2.5 V, Current Strength: Default
+// tx_digitalreset[31] => Location: PIN_N5, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[0] => Location: PIN_D16, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[1] => Location: PIN_H40, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[2] => Location: PIN_F16, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[3] => Location: PIN_E34, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[4] => Location: PIN_K11, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[5] => Location: PIN_AN7, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[6] => Location: PIN_J25, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[7] => Location: PIN_AW14, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[8] => Location: PIN_AR19, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[9] => Location: PIN_G18, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[10] => Location: PIN_AL14, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[11] => Location: PIN_R31, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[12] => Location: PIN_V30, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[13] => Location: PIN_J33, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[14] => Location: PIN_AD15, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[15] => Location: PIN_F38, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[16] => Location: PIN_AA5, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[17] => Location: PIN_AC5, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[18] => Location: PIN_AP19, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[19] => Location: PIN_AR7, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[20] => Location: PIN_BB25, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[21] => Location: PIN_AL20, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[22] => Location: PIN_BD13, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[23] => Location: PIN_H9, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[24] => Location: PIN_J27, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[25] => Location: PIN_K26, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[26] => Location: PIN_AK11, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[27] => Location: PIN_AA15, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[28] => Location: PIN_N6, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[29] => Location: PIN_AT24, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[30] => Location: PIN_AW22, I/O Standard: 2.5 V, Current Strength: Default
+// rx_digitalreset[31] => Location: PIN_W30, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[4] => Location: PIN_R37, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[5] => Location: PIN_L16, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[6] => Location: PIN_AV16, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[7] => Location: PIN_J15, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[8] => Location: PIN_AD6, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[9] => Location: PIN_AV24, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[10] => Location: PIN_A16, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[11] => Location: PIN_BA20, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[12] => Location: PIN_Y6, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[13] => Location: PIN_AP16, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[14] => Location: PIN_AA8, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[15] => Location: PIN_E11, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[16] => Location: PIN_AU16, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[17] => Location: PIN_AT7, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[18] => Location: PIN_P32, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[19] => Location: PIN_AM6, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[20] => Location: PIN_M40, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[21] => Location: PIN_M28, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[22] => Location: PIN_AK10, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[23] => Location: PIN_R6, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[24] => Location: PIN_R18, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[25] => Location: PIN_V32, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[26] => Location: PIN_AH14, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[27] => Location: PIN_BD17, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[28] => Location: PIN_Y14, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[29] => Location: PIN_T15, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[30] => Location: PIN_AG13, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[31] => Location: PIN_W6, I/O Standard: 2.5 V, Current Strength: Default
+// rst => Location: PIN_F14, I/O Standard: 2.5 V, Current Strength: Default
+// clk => Location: PIN_K40, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_address[0] => Location: PIN_N25, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_address[1] => Location: PIN_AF15, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_address[2] => Location: PIN_G12, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_read => Location: PIN_E8, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[0] => Location: PIN_J5, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[1] => Location: PIN_K20, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[2] => Location: PIN_P38, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[3] => Location: PIN_BA18, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[4] => Location: PIN_U5, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[5] => Location: PIN_B13, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[6] => Location: PIN_T17, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[7] => Location: PIN_H7, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[8] => Location: PIN_AW24, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[9] => Location: PIN_BA23, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[10] => Location: PIN_A26, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[11] => Location: PIN_H11, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[12] => Location: PIN_AJ7, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[13] => Location: PIN_AV8, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[14] => Location: PIN_N29, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[15] => Location: PIN_L35, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[16] => Location: PIN_G29, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[17] => Location: PIN_D30, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[18] => Location: PIN_C10, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[19] => Location: PIN_D23, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[20] => Location: PIN_AR16, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[21] => Location: PIN_T39, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[22] => Location: PIN_H19, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[23] => Location: PIN_AR5, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[24] => Location: PIN_F24, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[25] => Location: PIN_M39, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[26] => Location: PIN_AY17, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[27] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[28] => Location: PIN_T25, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[29] => Location: PIN_BD10, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[30] => Location: PIN_AN15, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_readdata[31] => Location: PIN_N33, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_write => Location: PIN_BD21, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[0] => Location: PIN_BB12, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[1] => Location: PIN_G24, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[2] => Location: PIN_W5, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[3] => Location: PIN_AB10, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[4] => Location: PIN_D33, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[5] => Location: PIN_P13, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[6] => Location: PIN_D31, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[7] => Location: PIN_G31, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[8] => Location: PIN_AP11, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[9] => Location: PIN_F12, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[10] => Location: PIN_AN9, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[11] => Location: PIN_F5, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[12] => Location: PIN_U7, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[13] => Location: PIN_AL9, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[14] => Location: PIN_AF13, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[15] => Location: PIN_T19, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[16] => Location: PIN_AU17, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[17] => Location: PIN_AW25, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[18] => Location: PIN_AB8, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[19] => Location: PIN_N30, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[20] => Location: PIN_H28, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[21] => Location: PIN_AL13, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[22] => Location: PIN_AY14, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[23] => Location: PIN_J26, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[24] => Location: PIN_J36, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[25] => Location: PIN_J35, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[26] => Location: PIN_T30, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[27] => Location: PIN_K29, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[28] => Location: PIN_AU8, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[29] => Location: PIN_AL17, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[30] => Location: PIN_D32, I/O Standard: 2.5 V, Current Strength: Default
+// ch_ctrl_writedata[31] => Location: PIN_T31, I/O Standard: 2.5 V, Current Strength: Default
+// pll_locked => Location: PIN_AM28, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[0] => Location: PIN_H20, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[1] => Location: PIN_AR27, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[2] => Location: PIN_AH30, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[3] => Location: PIN_AT29, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[4] => Location: PIN_AY37, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[5] => Location: PIN_L9, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[6] => Location: PIN_B31, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[7] => Location: PIN_BC22, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[8] => Location: PIN_F19, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[9] => Location: PIN_AV10, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[10] => Location: PIN_F9, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[11] => Location: PIN_A12, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[12] => Location: PIN_M14, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[13] => Location: PIN_G14, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[14] => Location: PIN_N14, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[15] => Location: PIN_AG15, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[16] => Location: PIN_AF6, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[17] => Location: PIN_G20, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[18] => Location: PIN_AK30, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[19] => Location: PIN_AU35, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[20] => Location: PIN_AM31, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[21] => Location: PIN_AV38, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[22] => Location: PIN_R15, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[23] => Location: PIN_V12, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[24] => Location: PIN_BD19, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[25] => Location: PIN_AK16, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[26] => Location: PIN_F25, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[27] => Location: PIN_BA16, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[28] => Location: PIN_AM19, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[29] => Location: PIN_AR15, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[30] => Location: PIN_AD14, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[31] => Location: PIN_J37, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[32] => Location: PIN_L32, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[33] => Location: PIN_N19, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[34] => Location: PIN_G21, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[35] => Location: PIN_AY29, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[36] => Location: PIN_BB35, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[37] => Location: PIN_BD34, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[38] => Location: PIN_BC26, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[39] => Location: PIN_Y32, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[40] => Location: PIN_AW20, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[41] => Location: PIN_AK18, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[42] => Location: PIN_V14, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[43] => Location: PIN_F8, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[44] => Location: PIN_H32, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[45] => Location: PIN_F11, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[46] => Location: PIN_V6, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[47] => Location: PIN_AE5, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[48] => Location: PIN_AA30, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[49] => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[50] => Location: PIN_AA12, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[51] => Location: PIN_F20, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[52] => Location: PIN_AJ30, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[53] => Location: PIN_AY32, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[54] => Location: PIN_BD33, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[55] => Location: PIN_BC28, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[56] => Location: PIN_AU5, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[57] => Location: PIN_AE6, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[58] => Location: PIN_D24, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[59] => Location: PIN_AG7, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[60] => Location: PIN_G37, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[61] => Location: PIN_A13, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[62] => Location: PIN_BB15, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[63] => Location: PIN_D28, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[64] => Location: PIN_E29, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[65] => Location: PIN_H8, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[66] => Location: PIN_AT23, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_fromgxb[67] => Location: PIN_M33, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[0] => Location: PIN_G30, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[1] => Location: PIN_AM12, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[2] => Location: PIN_AM21, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[3] => Location: PIN_H5, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[4] => Location: PIN_V35, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[5] => Location: PIN_J28, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[6] => Location: PIN_AM17, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[7] => Location: PIN_G23, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[8] => Location: PIN_N39, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[9] => Location: PIN_T21, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[10] => Location: PIN_P16, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[11] => Location: PIN_K25, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[12] => Location: PIN_E6, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[13] => Location: PIN_R14, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[14] => Location: PIN_BA17, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[15] => Location: PIN_AA36, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[16] => Location: PIN_N20, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[17] => Location: PIN_AJ18, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[18] => Location: PIN_AK12, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[19] => Location: PIN_AE36, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[20] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[21] => Location: PIN_G8, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[22] => Location: PIN_K5, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[23] => Location: PIN_AY6, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[24] => Location: PIN_AN23, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[25] => Location: PIN_A19, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[26] => Location: PIN_P20, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[27] => Location: PIN_V7, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[28] => Location: PIN_H36, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[29] => Location: PIN_AM15, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[30] => Location: PIN_AK8, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[31] => Location: PIN_F39, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[32] => Location: PIN_V15, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[33] => Location: PIN_B35, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[34] => Location: PIN_AE16, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[35] => Location: PIN_P25, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[36] => Location: PIN_AY5, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[37] => Location: PIN_AR11, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[38] => Location: PIN_J12, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[39] => Location: PIN_A27, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[40] => Location: PIN_H6, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[41] => Location: PIN_J22, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[42] => Location: PIN_AL11, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[43] => Location: PIN_G33, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[44] => Location: PIN_AY11, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[45] => Location: PIN_D21, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[46] => Location: PIN_N23, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[47] => Location: PIN_P29, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[48] => Location: PIN_U9, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[49] => Location: PIN_AT21, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[50] => Location: PIN_J8, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[51] => Location: PIN_B11, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[52] => Location: PIN_A31, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[53] => Location: PIN_J6, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[54] => Location: PIN_F27, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[55] => Location: PIN_G28, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[56] => Location: PIN_AD40, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[57] => Location: PIN_F22, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[58] => Location: PIN_T6, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[59] => Location: PIN_H22, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[60] => Location: PIN_G15, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[61] => Location: PIN_F31, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[62] => Location: PIN_BD22, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[63] => Location: PIN_H14, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[64] => Location: PIN_B29, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[65] => Location: PIN_AF12, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[66] => Location: PIN_M29, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[67] => Location: PIN_AL8, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[68] => Location: PIN_P31, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[69] => Location: PIN_AU14, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[70] => Location: PIN_P17, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[71] => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[72] => Location: PIN_A29, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[73] => Location: PIN_AF9, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[74] => Location: PIN_C34, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[75] => Location: PIN_U37, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[76] => Location: PIN_L29, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[77] => Location: PIN_BD20, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[78] => Location: PIN_AV6, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[79] => Location: PIN_L26, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[80] => Location: PIN_N26, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[81] => Location: PIN_BA10, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[82] => Location: PIN_E35, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[83] => Location: PIN_BB20, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[84] => Location: PIN_AM16, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[85] => Location: PIN_G6, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[86] => Location: PIN_A24, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[87] => Location: PIN_AW8, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[88] => Location: PIN_H31, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[89] => Location: PIN_C20, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[90] => Location: PIN_J14, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[91] => Location: PIN_J13, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[92] => Location: PIN_B26, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[93] => Location: PIN_E20, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[94] => Location: PIN_AF11, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_to_gxb[95] => Location: PIN_A11, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[0] => Location: PIN_W33, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[1] => Location: PIN_M35, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[2] => Location: PIN_D29, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[3] => Location: PIN_M25, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[4] => Location: PIN_AA14, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[5] => Location: PIN_K15, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[6] => Location: PIN_N27, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[7] => Location: PIN_L20, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[8] => Location: PIN_AK9, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[9] => Location: PIN_L36, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[10] => Location: PIN_F28, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[11] => Location: PIN_R27, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[12] => Location: PIN_K13, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[13] => Location: PIN_AW16, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[14] => Location: PIN_R40, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[15] => Location: PIN_AN8, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[16] => Location: PIN_E16, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[17] => Location: PIN_J18, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[18] => Location: PIN_AE9, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[19] => Location: PIN_AT17, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[20] => Location: PIN_A21, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[21] => Location: PIN_J21, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[22] => Location: PIN_P7, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[23] => Location: PIN_AU9, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[24] => Location: PIN_U12, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[25] => Location: PIN_B10, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[26] => Location: PIN_AY22, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[27] => Location: PIN_AY13, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[28] => Location: PIN_AN5, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[29] => Location: PIN_BC16, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[30] => Location: PIN_N12, I/O Standard: 2.5 V, Current Strength: Default
+// aeq_from_gxb[31] => Location: PIN_R21, I/O Standard: 2.5 V, Current Strength: Default
+// rx_cruclk[0] => Location: PIN_AL25, I/O Standard: 2.5 V, Current Strength: Default
+// rx_cruclk[1] => Location: PIN_AG14, I/O Standard: 2.5 V, Current Strength: Default
+// rx_cruclk[2] => Location: PIN_AB6, I/O Standard: 2.5 V, Current Strength: Default
+// rx_cruclk[3] => Location: PIN_B34, I/O Standard: 2.5 V, Current Strength: Default
+// tx_dataout[0] => Location: PIN_BA38, I/O Standard: 1.4-V PCML, Current Strength: Default
+// tx_dataout[1] => Location: PIN_BA40, I/O Standard: 1.4-V PCML, Current Strength: Default
+// tx_dataout[2] => Location: PIN_AU41, I/O Standard: 1.4-V PCML, Current Strength: Default
+// tx_dataout[3] => Location: PIN_AR41, I/O Standard: 1.4-V PCML, Current Strength: Default
+// tx_clkout[0] => Location: PIN_AT25, I/O Standard: 2.5 V, Current Strength: Default
+// tx_clkout[1] => Location: PIN_BD24, I/O Standard: 2.5 V, Current Strength: Default
+// tx_clkout[2] => Location: PIN_AY23, I/O Standard: 2.5 V, Current Strength: Default
+// tx_clkout[3] => Location: PIN_AC39, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[0] => Location: PIN_AW31, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[1] => Location: PIN_BA26, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[2] => Location: PIN_BB30, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[3] => Location: PIN_AP34, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[4] => Location: PIN_BA28, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[5] => Location: PIN_BA30, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[6] => Location: PIN_BC25, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[7] => Location: PIN_AN31, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[8] => Location: PIN_BD29, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[9] => Location: PIN_BC32, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[10] => Location: PIN_AR31, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[11] => Location: PIN_AV33, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[12] => Location: PIN_AT33, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[13] => Location: PIN_AY28, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[14] => Location: PIN_BD25, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[15] => Location: PIN_AV27, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[16] => Location: PIN_AT32, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[17] => Location: PIN_BD30, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[18] => Location: PIN_AR26, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[19] => Location: PIN_AV26, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[20] => Location: PIN_AW33, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[21] => Location: PIN_AK27, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[22] => Location: PIN_BD35, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[23] => Location: PIN_AM30, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[24] => Location: PIN_AY26, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[25] => Location: PIN_AR32, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[26] => Location: PIN_AM26, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[27] => Location: PIN_BA29, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[28] => Location: PIN_BD32, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[29] => Location: PIN_AV31, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[30] => Location: PIN_AW29, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[31] => Location: PIN_BD27, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[32] => Location: PIN_BD28, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[33] => Location: PIN_AK26, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[34] => Location: PIN_AU29, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[35] => Location: PIN_AW26, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[36] => Location: PIN_AM27, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[37] => Location: PIN_AV34, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[38] => Location: PIN_AN30, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[39] => Location: PIN_AK28, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[40] => Location: PIN_AT37, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[41] => Location: PIN_AP36, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[42] => Location: PIN_AN33, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[43] => Location: PIN_W38, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[44] => Location: PIN_AN34, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[45] => Location: PIN_AN37, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[46] => Location: PIN_AP35, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[47] => Location: PIN_AG40, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[48] => Location: PIN_AK39, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[49] => Location: PIN_AR39, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[50] => Location: PIN_AA38, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[51] => Location: PIN_AF34, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[52] => Location: PIN_AB37, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[53] => Location: PIN_AA40, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[54] => Location: PIN_W37, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[55] => Location: PIN_AU39, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[56] => Location: PIN_AR35, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[57] => Location: PIN_AK38, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[58] => Location: PIN_AL36, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[59] => Location: PIN_AG32, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[60] => Location: PIN_AK34, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[61] => Location: PIN_AJ40, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[62] => Location: PIN_AN39, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[63] => Location: PIN_AT39, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[64] => Location: PIN_AR34, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[65] => Location: PIN_AL39, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[66] => Location: PIN_AM35, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[67] => Location: PIN_AT36, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[68] => Location: PIN_AP39, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[69] => Location: PIN_AM33, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[70] => Location: PIN_AN35, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[71] => Location: PIN_AJ36, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[72] => Location: PIN_AW37, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[73] => Location: PIN_AN40, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[74] => Location: PIN_AJ31, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[75] => Location: PIN_AR37, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[76] => Location: PIN_AL40, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[77] => Location: PIN_AW36, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[78] => Location: PIN_AN38, I/O Standard: 2.5 V, Current Strength: Default
+// rx_dataout[79] => Location: PIN_AJ37, I/O Standard: 2.5 V, Current Strength: Default
+// rx_clkout[0] => Location: PIN_AM25, I/O Standard: 2.5 V, Current Strength: Default
+// rx_clkout[1] => Location: PIN_AK23, I/O Standard: 2.5 V, Current Strength: Default
+// rx_clkout[2] => Location: PIN_AY25, I/O Standard: 2.5 V, Current Strength: Default
+// rx_clkout[3] => Location: PIN_AP25, I/O Standard: 2.5 V, Current Strength: Default
+// rx_freqlocked[0] => Location: PIN_AL32, I/O Standard: 2.5 V, Current Strength: Default
+// rx_freqlocked[1] => Location: PIN_BA34, I/O Standard: 2.5 V, Current Strength: Default
+// rx_freqlocked[2] => Location: PIN_BB31, I/O Standard: 2.5 V, Current Strength: Default
+// rx_freqlocked[3] => Location: PIN_AN29, I/O Standard: 2.5 V, Current Strength: Default
+// rx_pll_locked[0] => Location: PIN_AY38, I/O Standard: 2.5 V, Current Strength: Default
+// rx_pll_locked[1] => Location: PIN_AW34, I/O Standard: 2.5 V, Current Strength: Default
+// rx_pll_locked[2] => Location: PIN_AP10, I/O Standard: 2.5 V, Current Strength: Default
+// rx_pll_locked[3] => Location: PIN_AT31, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[0] => Location: PIN_AY34, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[1] => Location: PIN_AT30, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[2] => Location: PIN_AM29, I/O Standard: 2.5 V, Current Strength: Default
+// rx_analogreset[3] => Location: PIN_AK29, I/O Standard: 2.5 V, Current Strength: Default
+// pll_inclk[0] => Location: PIN_W40, I/O Standard: 2.5 V, Current Strength: Default
+// gxb_powerdown => Location: PIN_BC35, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_clk => Location: PIN_V39, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_togxb[0] => Location: PIN_R30, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_togxb[2] => Location: PIN_AV22, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_togxb[1] => Location: PIN_AR20, I/O Standard: 2.5 V, Current Strength: Default
+// reconfig_togxb[3] => Location: PIN_AL28, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktodata[0] => Location: PIN_BB32, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[0] => Location: PIN_BC31, I/O Standard: 2.5 V, Current Strength: Default
+// rx_datain[0] => Location: PIN_BC37, I/O Standard: 1.5-V PCML, Current Strength: Default
+// rx_locktodata[1] => Location: PIN_AR30, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[1] => Location: PIN_AU31, I/O Standard: 2.5 V, Current Strength: Default
+// rx_datain[1] => Location: PIN_BC39, I/O Standard: 1.5-V PCML, Current Strength: Default
+// rx_locktodata[2] => Location: PIN_AV35, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[2] => Location: PIN_BD31, I/O Standard: 2.5 V, Current Strength: Default
+// rx_datain[2] => Location: PIN_AV43, I/O Standard: 1.5-V PCML, Current Strength: Default
+// rx_locktodata[3] => Location: PIN_BA33, I/O Standard: 2.5 V, Current Strength: Default
+// rx_locktorefclk[3] => Location: PIN_AL29, I/O Standard: 2.5 V, Current Strength: Default
+// rx_datain[3] => Location: PIN_AT43, I/O Standard: 1.5-V PCML, Current Strength: Default
+// tx_datain[0] => Location: PIN_AV28, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[1] => Location: PIN_AL26, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[2] => Location: PIN_BD26, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[3] => Location: PIN_AT26, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[4] => Location: PIN_AW28, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[5] => Location: PIN_AN28, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[6] => Location: PIN_AV29, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[7] => Location: PIN_AP28, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[8] => Location: PIN_BD23, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[9] => Location: PIN_AW30, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[10] => Location: PIN_AU26, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[11] => Location: PIN_AV32, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[12] => Location: PIN_AR28, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[13] => Location: PIN_BA32, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[14] => Location: PIN_BB28, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[15] => Location: PIN_AU27, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[16] => Location: PIN_BB26, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[17] => Location: PIN_BC29, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[18] => Location: PIN_BA27, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[19] => Location: PIN_AU32, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[20] => Location: PIN_AD30, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[21] => Location: PIN_AE33, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[22] => Location: PIN_AD38, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[23] => Location: PIN_BA31, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[24] => Location: PIN_AV40, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[25] => Location: PIN_AU40, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[26] => Location: PIN_AE30, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[27] => Location: PIN_Y37, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[28] => Location: PIN_AF37, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[29] => Location: PIN_Y39, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[30] => Location: PIN_AG33, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[31] => Location: PIN_AY40, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[32] => Location: PIN_AY31, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[33] => Location: PIN_AG31, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[34] => Location: PIN_AD29, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[35] => Location: PIN_AC37, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[36] => Location: PIN_AV37, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[37] => Location: PIN_AY39, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[38] => Location: PIN_BB33, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[39] => Location: PIN_AM37, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[40] => Location: PIN_AF36, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[41] => Location: PIN_AE31, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[42] => Location: PIN_AF30, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[43] => Location: PIN_AF35, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[44] => Location: PIN_AU34, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[45] => Location: PIN_AH39, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[46] => Location: PIN_AA37, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[47] => Location: PIN_Y38, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[48] => Location: PIN_AF33, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[49] => Location: PIN_AB39, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[50] => Location: PIN_AL35, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[51] => Location: PIN_AJ32, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[52] => Location: PIN_AJ33, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[53] => Location: PIN_AF39, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[54] => Location: PIN_AH37, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[55] => Location: PIN_AE39, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[56] => Location: PIN_AG38, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[57] => Location: PIN_AP37, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[58] => Location: PIN_AJ39, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[59] => Location: PIN_AR40, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[60] => Location: PIN_AT40, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[61] => Location: PIN_AF38, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[62] => Location: PIN_AU36, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[63] => Location: PIN_AK31, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[64] => Location: PIN_AK33, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[65] => Location: PIN_AK35, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[66] => Location: PIN_AU37, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[67] => Location: PIN_AT38, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[68] => Location: PIN_AK36, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[69] => Location: PIN_AM39, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[70] => Location: PIN_AG39, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[71] => Location: PIN_AK32, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[72] => Location: PIN_AM38, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[73] => Location: PIN_AL34, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[74] => Location: PIN_AT34, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[75] => Location: PIN_AC38, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[76] => Location: PIN_AH31, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[77] => Location: PIN_AE40, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[78] => Location: PIN_AA39, I/O Standard: 2.5 V, Current Strength: Default
+// tx_datain[79] => Location: PIN_AF32, I/O Standard: 2.5 V, Current Strength: Default
+// pll_powerdown => Location: PIN_BC34, I/O Standard: 2.5 V, Current Strength: Default
+// cal_blk_clk => Location: PIN_AU28, I/O Standard: 2.5 V, Current Strength: Default
+// cal_blk_powerdown => Location: PIN_AR29, I/O Standard: 2.5 V, Current Strength: Default
+// ~ALTERA_DATA0~ => Location: PIN_AA33, I/O Standard: 1.8 V, Current Strength: Default
+// tx_dataout[0](n) => Location: PIN_BB38, I/O Standard: 1.4-V PCML, Current Strength: Default
+// tx_dataout[1](n) => Location: PIN_BB40, I/O Standard: 1.4-V PCML, Current Strength: Default
+// tx_dataout[2](n) => Location: PIN_AU42, I/O Standard: 1.4-V PCML, Current Strength: Default
+// tx_dataout[3](n) => Location: PIN_AR42, I/O Standard: 1.4-V PCML, Current Strength: Default
+// rx_datain[0](n) => Location: PIN_BD37, I/O Standard: 1.5-V PCML, Current Strength: Default
+// rx_datain[1](n) => Location: PIN_BD39, I/O Standard: 1.5-V PCML, Current Strength: Default
+// rx_datain[2](n) => Location: PIN_AV44, I/O Standard: 1.5-V PCML, Current Strength: Default
+// rx_datain[3](n) => Location: PIN_AT44, I/O Standard: 1.5-V PCML, Current Strength: Default
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+// synopsys translate_off
+// initial $sdf_annotate("alt4gxb_simgen_v.sdo");
+// synopsys translate_on
+
+wire \rx_datain[0](n)~padout ;
+wire \rx_datain[1](n)~padout ;
+wire \rx_datain[2](n)~padout ;
+wire \rx_datain[3](n)~padout ;
+wire \pma_direct|auto_generated|tx_pll_edge0~DATAOUT0 ;
+wire \pma_direct|auto_generated|tx_pll_edge0~DATAOUT1 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~DPRIOOUT ;
+wire \pma_direct|auto_generated|cal_blk0~calibrationstatus ;
+wire \pma_direct|auto_generated|cal_blk0~CALIBRATIONSTATUS1 ;
+wire \pma_direct|auto_generated|cal_blk0~CALIBRATIONSTATUS2 ;
+wire \pma_direct|auto_generated|cal_blk0~CALIBRATIONSTATUS3 ;
+wire \pma_direct|auto_generated|cal_blk0~CALIBRATIONSTATUS4 ;
+wire \pma_direct|auto_generated|central_clk_div0~coreclkout ;
+wire \rx_locktodata[4]~input_o ;
+wire \rx_locktodata[5]~input_o ;
+wire \rx_locktodata[6]~input_o ;
+wire \rx_locktodata[7]~input_o ;
+wire \rx_locktodata[8]~input_o ;
+wire \rx_locktodata[9]~input_o ;
+wire \rx_locktodata[10]~input_o ;
+wire \rx_locktodata[11]~input_o ;
+wire \rx_locktodata[12]~input_o ;
+wire \rx_locktodata[13]~input_o ;
+wire \rx_locktodata[14]~input_o ;
+wire \rx_locktodata[15]~input_o ;
+wire \rx_locktodata[16]~input_o ;
+wire \rx_locktodata[17]~input_o ;
+wire \rx_locktodata[18]~input_o ;
+wire \rx_locktodata[19]~input_o ;
+wire \rx_locktodata[20]~input_o ;
+wire \rx_locktodata[21]~input_o ;
+wire \rx_locktodata[22]~input_o ;
+wire \rx_locktodata[23]~input_o ;
+wire \rx_locktodata[24]~input_o ;
+wire \rx_locktodata[25]~input_o ;
+wire \rx_locktodata[26]~input_o ;
+wire \rx_locktodata[27]~input_o ;
+wire \rx_locktodata[28]~input_o ;
+wire \rx_locktodata[29]~input_o ;
+wire \rx_locktodata[30]~input_o ;
+wire \rx_locktodata[31]~input_o ;
+wire \rx_analogreset[4]~input_o ;
+wire \rx_analogreset[5]~input_o ;
+wire \rx_analogreset[6]~input_o ;
+wire \rx_analogreset[7]~input_o ;
+wire \rx_analogreset[8]~input_o ;
+wire \rx_analogreset[9]~input_o ;
+wire \rx_analogreset[10]~input_o ;
+wire \rx_analogreset[11]~input_o ;
+wire \rx_analogreset[12]~input_o ;
+wire \rx_analogreset[13]~input_o ;
+wire \rx_analogreset[14]~input_o ;
+wire \rx_analogreset[15]~input_o ;
+wire \rx_analogreset[16]~input_o ;
+wire \rx_analogreset[17]~input_o ;
+wire \rx_analogreset[18]~input_o ;
+wire \rx_analogreset[19]~input_o ;
+wire \rx_analogreset[20]~input_o ;
+wire \rx_analogreset[21]~input_o ;
+wire \rx_analogreset[22]~input_o ;
+wire \rx_analogreset[23]~input_o ;
+wire \rx_analogreset[24]~input_o ;
+wire \rx_analogreset[25]~input_o ;
+wire \rx_analogreset[26]~input_o ;
+wire \rx_analogreset[27]~input_o ;
+wire \rx_analogreset[28]~input_o ;
+wire \rx_analogreset[29]~input_o ;
+wire \rx_analogreset[30]~input_o ;
+wire \rx_analogreset[31]~input_o ;
+wire \rx_seriallpbken[0]~input_o ;
+wire \rx_seriallpbken[1]~input_o ;
+wire \rx_seriallpbken[2]~input_o ;
+wire \rx_seriallpbken[3]~input_o ;
+wire \rx_seriallpbken[4]~input_o ;
+wire \rx_seriallpbken[5]~input_o ;
+wire \rx_seriallpbken[6]~input_o ;
+wire \rx_seriallpbken[7]~input_o ;
+wire \rx_seriallpbken[8]~input_o ;
+wire \rx_seriallpbken[9]~input_o ;
+wire \rx_seriallpbken[10]~input_o ;
+wire \rx_seriallpbken[11]~input_o ;
+wire \rx_seriallpbken[12]~input_o ;
+wire \rx_seriallpbken[13]~input_o ;
+wire \rx_seriallpbken[14]~input_o ;
+wire \rx_seriallpbken[15]~input_o ;
+wire \rx_seriallpbken[16]~input_o ;
+wire \rx_seriallpbken[17]~input_o ;
+wire \rx_seriallpbken[18]~input_o ;
+wire \rx_seriallpbken[19]~input_o ;
+wire \rx_seriallpbken[20]~input_o ;
+wire \rx_seriallpbken[21]~input_o ;
+wire \rx_seriallpbken[22]~input_o ;
+wire \rx_seriallpbken[23]~input_o ;
+wire \rx_seriallpbken[24]~input_o ;
+wire \rx_seriallpbken[25]~input_o ;
+wire \rx_seriallpbken[26]~input_o ;
+wire \rx_seriallpbken[27]~input_o ;
+wire \rx_seriallpbken[28]~input_o ;
+wire \rx_seriallpbken[29]~input_o ;
+wire \rx_seriallpbken[30]~input_o ;
+wire \rx_seriallpbken[31]~input_o ;
+wire \tx_digitalreset[0]~input_o ;
+wire \tx_digitalreset[1]~input_o ;
+wire \tx_digitalreset[2]~input_o ;
+wire \tx_digitalreset[3]~input_o ;
+wire \tx_digitalreset[4]~input_o ;
+wire \tx_digitalreset[5]~input_o ;
+wire \tx_digitalreset[6]~input_o ;
+wire \tx_digitalreset[7]~input_o ;
+wire \tx_digitalreset[8]~input_o ;
+wire \tx_digitalreset[9]~input_o ;
+wire \tx_digitalreset[10]~input_o ;
+wire \tx_digitalreset[11]~input_o ;
+wire \tx_digitalreset[12]~input_o ;
+wire \tx_digitalreset[13]~input_o ;
+wire \tx_digitalreset[14]~input_o ;
+wire \tx_digitalreset[15]~input_o ;
+wire \tx_digitalreset[16]~input_o ;
+wire \tx_digitalreset[17]~input_o ;
+wire \tx_digitalreset[18]~input_o ;
+wire \tx_digitalreset[19]~input_o ;
+wire \tx_digitalreset[20]~input_o ;
+wire \tx_digitalreset[21]~input_o ;
+wire \tx_digitalreset[22]~input_o ;
+wire \tx_digitalreset[23]~input_o ;
+wire \tx_digitalreset[24]~input_o ;
+wire \tx_digitalreset[25]~input_o ;
+wire \tx_digitalreset[26]~input_o ;
+wire \tx_digitalreset[27]~input_o ;
+wire \tx_digitalreset[28]~input_o ;
+wire \tx_digitalreset[29]~input_o ;
+wire \tx_digitalreset[30]~input_o ;
+wire \tx_digitalreset[31]~input_o ;
+wire \rx_digitalreset[0]~input_o ;
+wire \rx_digitalreset[1]~input_o ;
+wire \rx_digitalreset[2]~input_o ;
+wire \rx_digitalreset[3]~input_o ;
+wire \rx_digitalreset[4]~input_o ;
+wire \rx_digitalreset[5]~input_o ;
+wire \rx_digitalreset[6]~input_o ;
+wire \rx_digitalreset[7]~input_o ;
+wire \rx_digitalreset[8]~input_o ;
+wire \rx_digitalreset[9]~input_o ;
+wire \rx_digitalreset[10]~input_o ;
+wire \rx_digitalreset[11]~input_o ;
+wire \rx_digitalreset[12]~input_o ;
+wire \rx_digitalreset[13]~input_o ;
+wire \rx_digitalreset[14]~input_o ;
+wire \rx_digitalreset[15]~input_o ;
+wire \rx_digitalreset[16]~input_o ;
+wire \rx_digitalreset[17]~input_o ;
+wire \rx_digitalreset[18]~input_o ;
+wire \rx_digitalreset[19]~input_o ;
+wire \rx_digitalreset[20]~input_o ;
+wire \rx_digitalreset[21]~input_o ;
+wire \rx_digitalreset[22]~input_o ;
+wire \rx_digitalreset[23]~input_o ;
+wire \rx_digitalreset[24]~input_o ;
+wire \rx_digitalreset[25]~input_o ;
+wire \rx_digitalreset[26]~input_o ;
+wire \rx_digitalreset[27]~input_o ;
+wire \rx_digitalreset[28]~input_o ;
+wire \rx_digitalreset[29]~input_o ;
+wire \rx_digitalreset[30]~input_o ;
+wire \rx_digitalreset[31]~input_o ;
+wire \rx_locktorefclk[4]~input_o ;
+wire \rx_locktorefclk[5]~input_o ;
+wire \rx_locktorefclk[6]~input_o ;
+wire \rx_locktorefclk[7]~input_o ;
+wire \rx_locktorefclk[8]~input_o ;
+wire \rx_locktorefclk[9]~input_o ;
+wire \rx_locktorefclk[10]~input_o ;
+wire \rx_locktorefclk[11]~input_o ;
+wire \rx_locktorefclk[12]~input_o ;
+wire \rx_locktorefclk[13]~input_o ;
+wire \rx_locktorefclk[14]~input_o ;
+wire \rx_locktorefclk[15]~input_o ;
+wire \rx_locktorefclk[16]~input_o ;
+wire \rx_locktorefclk[17]~input_o ;
+wire \rx_locktorefclk[18]~input_o ;
+wire \rx_locktorefclk[19]~input_o ;
+wire \rx_locktorefclk[20]~input_o ;
+wire \rx_locktorefclk[21]~input_o ;
+wire \rx_locktorefclk[22]~input_o ;
+wire \rx_locktorefclk[23]~input_o ;
+wire \rx_locktorefclk[24]~input_o ;
+wire \rx_locktorefclk[25]~input_o ;
+wire \rx_locktorefclk[26]~input_o ;
+wire \rx_locktorefclk[27]~input_o ;
+wire \rx_locktorefclk[28]~input_o ;
+wire \rx_locktorefclk[29]~input_o ;
+wire \rx_locktorefclk[30]~input_o ;
+wire \rx_locktorefclk[31]~input_o ;
+wire \rst~input_o ;
+wire \clk~input_o ;
+wire \ch_ctrl_address[0]~input_o ;
+wire \ch_ctrl_address[1]~input_o ;
+wire \ch_ctrl_address[2]~input_o ;
+wire \ch_ctrl_read~input_o ;
+wire \ch_ctrl_write~input_o ;
+wire \ch_ctrl_writedata[0]~input_o ;
+wire \ch_ctrl_writedata[1]~input_o ;
+wire \ch_ctrl_writedata[2]~input_o ;
+wire \ch_ctrl_writedata[3]~input_o ;
+wire \ch_ctrl_writedata[4]~input_o ;
+wire \ch_ctrl_writedata[5]~input_o ;
+wire \ch_ctrl_writedata[6]~input_o ;
+wire \ch_ctrl_writedata[7]~input_o ;
+wire \ch_ctrl_writedata[8]~input_o ;
+wire \ch_ctrl_writedata[9]~input_o ;
+wire \ch_ctrl_writedata[10]~input_o ;
+wire \ch_ctrl_writedata[11]~input_o ;
+wire \ch_ctrl_writedata[12]~input_o ;
+wire \ch_ctrl_writedata[13]~input_o ;
+wire \ch_ctrl_writedata[14]~input_o ;
+wire \ch_ctrl_writedata[15]~input_o ;
+wire \ch_ctrl_writedata[16]~input_o ;
+wire \ch_ctrl_writedata[17]~input_o ;
+wire \ch_ctrl_writedata[18]~input_o ;
+wire \ch_ctrl_writedata[19]~input_o ;
+wire \ch_ctrl_writedata[20]~input_o ;
+wire \ch_ctrl_writedata[21]~input_o ;
+wire \ch_ctrl_writedata[22]~input_o ;
+wire \ch_ctrl_writedata[23]~input_o ;
+wire \ch_ctrl_writedata[24]~input_o ;
+wire \ch_ctrl_writedata[25]~input_o ;
+wire \ch_ctrl_writedata[26]~input_o ;
+wire \ch_ctrl_writedata[27]~input_o ;
+wire \ch_ctrl_writedata[28]~input_o ;
+wire \ch_ctrl_writedata[29]~input_o ;
+wire \ch_ctrl_writedata[30]~input_o ;
+wire \ch_ctrl_writedata[31]~input_o ;
+wire \aeq_to_gxb[0]~input_o ;
+wire \aeq_to_gxb[1]~input_o ;
+wire \aeq_to_gxb[2]~input_o ;
+wire \aeq_to_gxb[3]~input_o ;
+wire \aeq_to_gxb[4]~input_o ;
+wire \aeq_to_gxb[5]~input_o ;
+wire \aeq_to_gxb[6]~input_o ;
+wire \aeq_to_gxb[7]~input_o ;
+wire \aeq_to_gxb[8]~input_o ;
+wire \aeq_to_gxb[9]~input_o ;
+wire \aeq_to_gxb[10]~input_o ;
+wire \aeq_to_gxb[11]~input_o ;
+wire \aeq_to_gxb[12]~input_o ;
+wire \aeq_to_gxb[13]~input_o ;
+wire \aeq_to_gxb[14]~input_o ;
+wire \aeq_to_gxb[15]~input_o ;
+wire \aeq_to_gxb[16]~input_o ;
+wire \aeq_to_gxb[17]~input_o ;
+wire \aeq_to_gxb[18]~input_o ;
+wire \aeq_to_gxb[19]~input_o ;
+wire \aeq_to_gxb[20]~input_o ;
+wire \aeq_to_gxb[21]~input_o ;
+wire \aeq_to_gxb[22]~input_o ;
+wire \aeq_to_gxb[23]~input_o ;
+wire \aeq_to_gxb[24]~input_o ;
+wire \aeq_to_gxb[25]~input_o ;
+wire \aeq_to_gxb[26]~input_o ;
+wire \aeq_to_gxb[27]~input_o ;
+wire \aeq_to_gxb[28]~input_o ;
+wire \aeq_to_gxb[29]~input_o ;
+wire \aeq_to_gxb[30]~input_o ;
+wire \aeq_to_gxb[31]~input_o ;
+wire \aeq_to_gxb[32]~input_o ;
+wire \aeq_to_gxb[33]~input_o ;
+wire \aeq_to_gxb[34]~input_o ;
+wire \aeq_to_gxb[35]~input_o ;
+wire \aeq_to_gxb[36]~input_o ;
+wire \aeq_to_gxb[37]~input_o ;
+wire \aeq_to_gxb[38]~input_o ;
+wire \aeq_to_gxb[39]~input_o ;
+wire \aeq_to_gxb[40]~input_o ;
+wire \aeq_to_gxb[41]~input_o ;
+wire \aeq_to_gxb[42]~input_o ;
+wire \aeq_to_gxb[43]~input_o ;
+wire \aeq_to_gxb[44]~input_o ;
+wire \aeq_to_gxb[45]~input_o ;
+wire \aeq_to_gxb[46]~input_o ;
+wire \aeq_to_gxb[47]~input_o ;
+wire \aeq_to_gxb[48]~input_o ;
+wire \aeq_to_gxb[49]~input_o ;
+wire \aeq_to_gxb[50]~input_o ;
+wire \aeq_to_gxb[51]~input_o ;
+wire \aeq_to_gxb[52]~input_o ;
+wire \aeq_to_gxb[53]~input_o ;
+wire \aeq_to_gxb[54]~input_o ;
+wire \aeq_to_gxb[55]~input_o ;
+wire \aeq_to_gxb[56]~input_o ;
+wire \aeq_to_gxb[57]~input_o ;
+wire \aeq_to_gxb[58]~input_o ;
+wire \aeq_to_gxb[59]~input_o ;
+wire \aeq_to_gxb[60]~input_o ;
+wire \aeq_to_gxb[61]~input_o ;
+wire \aeq_to_gxb[62]~input_o ;
+wire \aeq_to_gxb[63]~input_o ;
+wire \aeq_to_gxb[64]~input_o ;
+wire \aeq_to_gxb[65]~input_o ;
+wire \aeq_to_gxb[66]~input_o ;
+wire \aeq_to_gxb[67]~input_o ;
+wire \aeq_to_gxb[68]~input_o ;
+wire \aeq_to_gxb[69]~input_o ;
+wire \aeq_to_gxb[70]~input_o ;
+wire \aeq_to_gxb[71]~input_o ;
+wire \aeq_to_gxb[72]~input_o ;
+wire \aeq_to_gxb[73]~input_o ;
+wire \aeq_to_gxb[74]~input_o ;
+wire \aeq_to_gxb[75]~input_o ;
+wire \aeq_to_gxb[76]~input_o ;
+wire \aeq_to_gxb[77]~input_o ;
+wire \aeq_to_gxb[78]~input_o ;
+wire \aeq_to_gxb[79]~input_o ;
+wire \aeq_to_gxb[80]~input_o ;
+wire \aeq_to_gxb[81]~input_o ;
+wire \aeq_to_gxb[82]~input_o ;
+wire \aeq_to_gxb[83]~input_o ;
+wire \aeq_to_gxb[84]~input_o ;
+wire \aeq_to_gxb[85]~input_o ;
+wire \aeq_to_gxb[86]~input_o ;
+wire \aeq_to_gxb[87]~input_o ;
+wire \aeq_to_gxb[88]~input_o ;
+wire \aeq_to_gxb[89]~input_o ;
+wire \aeq_to_gxb[90]~input_o ;
+wire \aeq_to_gxb[91]~input_o ;
+wire \aeq_to_gxb[92]~input_o ;
+wire \aeq_to_gxb[93]~input_o ;
+wire \aeq_to_gxb[94]~input_o ;
+wire \aeq_to_gxb[95]~input_o ;
+wire \rx_cruclk[0]~input_o ;
+wire \rx_cruclk[1]~input_o ;
+wire \rx_cruclk[2]~input_o ;
+wire \rx_cruclk[3]~input_o ;
+wire \pll_inclk[0]~input_o ;
+wire \reconfig_clk~input_o ;
+wire \reconfig_togxb[0]~input_o ;
+wire \reconfig_togxb[2]~input_o ;
+wire \reconfig_togxb[1]~input_o ;
+wire \reconfig_togxb[3]~input_o ;
+wire \cal_blk_clk~input_o ;
+wire \ch_ctrl_readdata[0]~output_o ;
+wire \ch_ctrl_readdata[1]~output_o ;
+wire \ch_ctrl_readdata[2]~output_o ;
+wire \ch_ctrl_readdata[3]~output_o ;
+wire \ch_ctrl_readdata[4]~output_o ;
+wire \ch_ctrl_readdata[5]~output_o ;
+wire \ch_ctrl_readdata[6]~output_o ;
+wire \ch_ctrl_readdata[7]~output_o ;
+wire \ch_ctrl_readdata[8]~output_o ;
+wire \ch_ctrl_readdata[9]~output_o ;
+wire \ch_ctrl_readdata[10]~output_o ;
+wire \ch_ctrl_readdata[11]~output_o ;
+wire \ch_ctrl_readdata[12]~output_o ;
+wire \ch_ctrl_readdata[13]~output_o ;
+wire \ch_ctrl_readdata[14]~output_o ;
+wire \ch_ctrl_readdata[15]~output_o ;
+wire \ch_ctrl_readdata[16]~output_o ;
+wire \ch_ctrl_readdata[17]~output_o ;
+wire \ch_ctrl_readdata[18]~output_o ;
+wire \ch_ctrl_readdata[19]~output_o ;
+wire \ch_ctrl_readdata[20]~output_o ;
+wire \ch_ctrl_readdata[21]~output_o ;
+wire \ch_ctrl_readdata[22]~output_o ;
+wire \ch_ctrl_readdata[23]~output_o ;
+wire \ch_ctrl_readdata[24]~output_o ;
+wire \ch_ctrl_readdata[25]~output_o ;
+wire \ch_ctrl_readdata[26]~output_o ;
+wire \ch_ctrl_readdata[27]~output_o ;
+wire \ch_ctrl_readdata[28]~output_o ;
+wire \ch_ctrl_readdata[29]~output_o ;
+wire \ch_ctrl_readdata[30]~output_o ;
+wire \ch_ctrl_readdata[31]~output_o ;
+wire \pll_locked~output_o ;
+wire \reconfig_fromgxb[0]~output_o ;
+wire \reconfig_fromgxb[1]~output_o ;
+wire \reconfig_fromgxb[2]~output_o ;
+wire \reconfig_fromgxb[3]~output_o ;
+wire \reconfig_fromgxb[4]~output_o ;
+wire \reconfig_fromgxb[5]~output_o ;
+wire \reconfig_fromgxb[6]~output_o ;
+wire \reconfig_fromgxb[7]~output_o ;
+wire \reconfig_fromgxb[8]~output_o ;
+wire \reconfig_fromgxb[9]~output_o ;
+wire \reconfig_fromgxb[10]~output_o ;
+wire \reconfig_fromgxb[11]~output_o ;
+wire \reconfig_fromgxb[12]~output_o ;
+wire \reconfig_fromgxb[13]~output_o ;
+wire \reconfig_fromgxb[14]~output_o ;
+wire \reconfig_fromgxb[15]~output_o ;
+wire \reconfig_fromgxb[16]~output_o ;
+wire \reconfig_fromgxb[17]~output_o ;
+wire \reconfig_fromgxb[18]~output_o ;
+wire \reconfig_fromgxb[19]~output_o ;
+wire \reconfig_fromgxb[20]~output_o ;
+wire \reconfig_fromgxb[21]~output_o ;
+wire \reconfig_fromgxb[22]~output_o ;
+wire \reconfig_fromgxb[23]~output_o ;
+wire \reconfig_fromgxb[24]~output_o ;
+wire \reconfig_fromgxb[25]~output_o ;
+wire \reconfig_fromgxb[26]~output_o ;
+wire \reconfig_fromgxb[27]~output_o ;
+wire \reconfig_fromgxb[28]~output_o ;
+wire \reconfig_fromgxb[29]~output_o ;
+wire \reconfig_fromgxb[30]~output_o ;
+wire \reconfig_fromgxb[31]~output_o ;
+wire \reconfig_fromgxb[32]~output_o ;
+wire \reconfig_fromgxb[33]~output_o ;
+wire \reconfig_fromgxb[34]~output_o ;
+wire \reconfig_fromgxb[35]~output_o ;
+wire \reconfig_fromgxb[36]~output_o ;
+wire \reconfig_fromgxb[37]~output_o ;
+wire \reconfig_fromgxb[38]~output_o ;
+wire \reconfig_fromgxb[39]~output_o ;
+wire \reconfig_fromgxb[40]~output_o ;
+wire \reconfig_fromgxb[41]~output_o ;
+wire \reconfig_fromgxb[42]~output_o ;
+wire \reconfig_fromgxb[43]~output_o ;
+wire \reconfig_fromgxb[44]~output_o ;
+wire \reconfig_fromgxb[45]~output_o ;
+wire \reconfig_fromgxb[46]~output_o ;
+wire \reconfig_fromgxb[47]~output_o ;
+wire \reconfig_fromgxb[48]~output_o ;
+wire \reconfig_fromgxb[49]~output_o ;
+wire \reconfig_fromgxb[50]~output_o ;
+wire \reconfig_fromgxb[51]~output_o ;
+wire \reconfig_fromgxb[52]~output_o ;
+wire \reconfig_fromgxb[53]~output_o ;
+wire \reconfig_fromgxb[54]~output_o ;
+wire \reconfig_fromgxb[55]~output_o ;
+wire \reconfig_fromgxb[56]~output_o ;
+wire \reconfig_fromgxb[57]~output_o ;
+wire \reconfig_fromgxb[58]~output_o ;
+wire \reconfig_fromgxb[59]~output_o ;
+wire \reconfig_fromgxb[60]~output_o ;
+wire \reconfig_fromgxb[61]~output_o ;
+wire \reconfig_fromgxb[62]~output_o ;
+wire \reconfig_fromgxb[63]~output_o ;
+wire \reconfig_fromgxb[64]~output_o ;
+wire \reconfig_fromgxb[65]~output_o ;
+wire \reconfig_fromgxb[66]~output_o ;
+wire \reconfig_fromgxb[67]~output_o ;
+wire \aeq_from_gxb[0]~output_o ;
+wire \aeq_from_gxb[1]~output_o ;
+wire \aeq_from_gxb[2]~output_o ;
+wire \aeq_from_gxb[3]~output_o ;
+wire \aeq_from_gxb[4]~output_o ;
+wire \aeq_from_gxb[5]~output_o ;
+wire \aeq_from_gxb[6]~output_o ;
+wire \aeq_from_gxb[7]~output_o ;
+wire \aeq_from_gxb[8]~output_o ;
+wire \aeq_from_gxb[9]~output_o ;
+wire \aeq_from_gxb[10]~output_o ;
+wire \aeq_from_gxb[11]~output_o ;
+wire \aeq_from_gxb[12]~output_o ;
+wire \aeq_from_gxb[13]~output_o ;
+wire \aeq_from_gxb[14]~output_o ;
+wire \aeq_from_gxb[15]~output_o ;
+wire \aeq_from_gxb[16]~output_o ;
+wire \aeq_from_gxb[17]~output_o ;
+wire \aeq_from_gxb[18]~output_o ;
+wire \aeq_from_gxb[19]~output_o ;
+wire \aeq_from_gxb[20]~output_o ;
+wire \aeq_from_gxb[21]~output_o ;
+wire \aeq_from_gxb[22]~output_o ;
+wire \aeq_from_gxb[23]~output_o ;
+wire \aeq_from_gxb[24]~output_o ;
+wire \aeq_from_gxb[25]~output_o ;
+wire \aeq_from_gxb[26]~output_o ;
+wire \aeq_from_gxb[27]~output_o ;
+wire \aeq_from_gxb[28]~output_o ;
+wire \aeq_from_gxb[29]~output_o ;
+wire \aeq_from_gxb[30]~output_o ;
+wire \aeq_from_gxb[31]~output_o ;
+wire \tx_dataout[0]~output_o ;
+wire \tx_dataout[0]~0 ;
+wire \tx_dataout[1]~output_o ;
+wire \tx_dataout[1]~1 ;
+wire \tx_dataout[2]~output_o ;
+wire \tx_dataout[2]~2 ;
+wire \tx_dataout[3]~output_o ;
+wire \tx_dataout[3]~3 ;
+wire \tx_clkout[0]~output_o ;
+wire \tx_clkout[1]~output_o ;
+wire \tx_clkout[2]~output_o ;
+wire \tx_clkout[3]~output_o ;
+wire \rx_dataout[0]~output_o ;
+wire \rx_dataout[1]~output_o ;
+wire \rx_dataout[2]~output_o ;
+wire \rx_dataout[3]~output_o ;
+wire \rx_dataout[4]~output_o ;
+wire \rx_dataout[5]~output_o ;
+wire \rx_dataout[6]~output_o ;
+wire \rx_dataout[7]~output_o ;
+wire \rx_dataout[8]~output_o ;
+wire \rx_dataout[9]~output_o ;
+wire \rx_dataout[10]~output_o ;
+wire \rx_dataout[11]~output_o ;
+wire \rx_dataout[12]~output_o ;
+wire \rx_dataout[13]~output_o ;
+wire \rx_dataout[14]~output_o ;
+wire \rx_dataout[15]~output_o ;
+wire \rx_dataout[16]~output_o ;
+wire \rx_dataout[17]~output_o ;
+wire \rx_dataout[18]~output_o ;
+wire \rx_dataout[19]~output_o ;
+wire \rx_dataout[20]~output_o ;
+wire \rx_dataout[21]~output_o ;
+wire \rx_dataout[22]~output_o ;
+wire \rx_dataout[23]~output_o ;
+wire \rx_dataout[24]~output_o ;
+wire \rx_dataout[25]~output_o ;
+wire \rx_dataout[26]~output_o ;
+wire \rx_dataout[27]~output_o ;
+wire \rx_dataout[28]~output_o ;
+wire \rx_dataout[29]~output_o ;
+wire \rx_dataout[30]~output_o ;
+wire \rx_dataout[31]~output_o ;
+wire \rx_dataout[32]~output_o ;
+wire \rx_dataout[33]~output_o ;
+wire \rx_dataout[34]~output_o ;
+wire \rx_dataout[35]~output_o ;
+wire \rx_dataout[36]~output_o ;
+wire \rx_dataout[37]~output_o ;
+wire \rx_dataout[38]~output_o ;
+wire \rx_dataout[39]~output_o ;
+wire \rx_dataout[40]~output_o ;
+wire \rx_dataout[41]~output_o ;
+wire \rx_dataout[42]~output_o ;
+wire \rx_dataout[43]~output_o ;
+wire \rx_dataout[44]~output_o ;
+wire \rx_dataout[45]~output_o ;
+wire \rx_dataout[46]~output_o ;
+wire \rx_dataout[47]~output_o ;
+wire \rx_dataout[48]~output_o ;
+wire \rx_dataout[49]~output_o ;
+wire \rx_dataout[50]~output_o ;
+wire \rx_dataout[51]~output_o ;
+wire \rx_dataout[52]~output_o ;
+wire \rx_dataout[53]~output_o ;
+wire \rx_dataout[54]~output_o ;
+wire \rx_dataout[55]~output_o ;
+wire \rx_dataout[56]~output_o ;
+wire \rx_dataout[57]~output_o ;
+wire \rx_dataout[58]~output_o ;
+wire \rx_dataout[59]~output_o ;
+wire \rx_dataout[60]~output_o ;
+wire \rx_dataout[61]~output_o ;
+wire \rx_dataout[62]~output_o ;
+wire \rx_dataout[63]~output_o ;
+wire \rx_dataout[64]~output_o ;
+wire \rx_dataout[65]~output_o ;
+wire \rx_dataout[66]~output_o ;
+wire \rx_dataout[67]~output_o ;
+wire \rx_dataout[68]~output_o ;
+wire \rx_dataout[69]~output_o ;
+wire \rx_dataout[70]~output_o ;
+wire \rx_dataout[71]~output_o ;
+wire \rx_dataout[72]~output_o ;
+wire \rx_dataout[73]~output_o ;
+wire \rx_dataout[74]~output_o ;
+wire \rx_dataout[75]~output_o ;
+wire \rx_dataout[76]~output_o ;
+wire \rx_dataout[77]~output_o ;
+wire \rx_dataout[78]~output_o ;
+wire \rx_dataout[79]~output_o ;
+wire \rx_clkout[0]~output_o ;
+wire \rx_clkout[1]~output_o ;
+wire \rx_clkout[2]~output_o ;
+wire \rx_clkout[3]~output_o ;
+wire \rx_freqlocked[0]~output_o ;
+wire \rx_freqlocked[1]~output_o ;
+wire \rx_freqlocked[2]~output_o ;
+wire \rx_freqlocked[3]~output_o ;
+wire \rx_pll_locked[0]~output_o ;
+wire \rx_pll_locked[1]~output_o ;
+wire \rx_pll_locked[2]~output_o ;
+wire \rx_pll_locked[3]~output_o ;
+wire \gxb_powerdown~input_o ;
+wire \reconfig_clk~inputclkctrl_outclk ;
+wire \cal_blk_powerdown~input_o ;
+wire \pll_inclk[0]~inputclkctrl_outclk ;
+wire \pll_powerdown~input_o ;
+wire \rx_analogreset[0]~input_o ;
+wire \rx_analogreset[1]~input_o ;
+wire \rx_analogreset[2]~input_o ;
+wire \rx_analogreset[3]~input_o ;
+wire \rx_locktodata[0]~input_o ;
+wire \rx_locktorefclk[0]~input_o ;
+wire \pma_direct|auto_generated|comb~0_combout ;
+wire \rx_datain[0]~input_o ;
+wire \rx_locktodata[1]~input_o ;
+wire \rx_locktorefclk[1]~input_o ;
+wire \pma_direct|auto_generated|comb~1_combout ;
+wire \rx_datain[1]~input_o ;
+wire \rx_locktodata[2]~input_o ;
+wire \rx_locktorefclk[2]~input_o ;
+wire \pma_direct|auto_generated|comb~2_combout ;
+wire \rx_datain[2]~input_o ;
+wire \rx_locktodata[3]~input_o ;
+wire \rx_locktorefclk[3]~input_o ;
+wire \pma_direct|auto_generated|comb~3_combout ;
+wire \rx_datain[3]~input_o ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1196 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1197 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1198 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1199 ;
+wire \tx_datain[60]~input_o ;
+wire \tx_datain[61]~input_o ;
+wire \tx_datain[62]~input_o ;
+wire \tx_datain[63]~input_o ;
+wire \tx_datain[64]~input_o ;
+wire \tx_datain[65]~input_o ;
+wire \tx_datain[66]~input_o ;
+wire \tx_datain[67]~input_o ;
+wire \tx_datain[68]~input_o ;
+wire \tx_datain[69]~input_o ;
+wire \tx_datain[70]~input_o ;
+wire \tx_datain[71]~input_o ;
+wire \tx_datain[72]~input_o ;
+wire \tx_datain[73]~input_o ;
+wire \tx_datain[74]~input_o ;
+wire \tx_datain[75]~input_o ;
+wire \tx_datain[76]~input_o ;
+wire \tx_datain[77]~input_o ;
+wire \tx_datain[78]~input_o ;
+wire \tx_datain[79]~input_o ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1195 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1194 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1193 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1192 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1191 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1190 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1189 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1188 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1187 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1186 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1185 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1184 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1183 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1182 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1181 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1180 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1179 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1178 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1177 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1176 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1175 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1174 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1173 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1172 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1171 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1170 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1169 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1168 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1167 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1166 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1165 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1164 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1163 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1162 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1161 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1160 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1159 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1158 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1157 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1156 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1155 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1154 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1153 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1152 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1151 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1150 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1149 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1148 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1147 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1146 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1145 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1144 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1143 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1142 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1141 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1140 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1139 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1138 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1137 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1136 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1135 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1134 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1133 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1132 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1131 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1130 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1129 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1128 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1127 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1126 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1125 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1124 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1123 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1122 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1121 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1120 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1119 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1118 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1117 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1116 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1115 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1114 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1113 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1112 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1111 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1110 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1109 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1108 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1107 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1106 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1105 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1104 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1103 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1102 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1101 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1100 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1099 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1098 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1097 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1096 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1095 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1094 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1093 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1092 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1091 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1090 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1089 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1088 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1087 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1086 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1085 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1084 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1083 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1082 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1081 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1080 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1079 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1078 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1077 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1076 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1075 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1074 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1073 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1072 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1071 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1070 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1069 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1068 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1067 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1066 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1065 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1064 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1063 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1062 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1061 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1060 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1059 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1058 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1057 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1056 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1055 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1054 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1053 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1052 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1051 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1050 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1049 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1048 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1047 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1046 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1045 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1044 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1043 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1042 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1041 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1040 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1039 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1038 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1037 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1036 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1035 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1034 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1033 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1032 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1031 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1030 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1029 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1028 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1027 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1026 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1025 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1024 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1023 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1022 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1021 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1020 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1019 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1018 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1017 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1016 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1015 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1014 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1013 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1012 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1011 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1010 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1009 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1008 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1007 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1006 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1005 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1004 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1003 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1002 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1001 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1000 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT999 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT998 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT997 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT996 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT995 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT994 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT993 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT992 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT991 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT990 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT989 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT988 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT987 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT986 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT985 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT984 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT983 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT982 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT981 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT980 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT979 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT978 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT977 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT976 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT975 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT974 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT973 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT972 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT971 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT970 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT969 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT968 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT967 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT966 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT965 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT964 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT963 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT962 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT961 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT960 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT959 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT958 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT957 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT956 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT955 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT954 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT953 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT952 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT951 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT950 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT949 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT948 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT947 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT946 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT945 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT944 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT943 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT942 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT941 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT940 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT939 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT938 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT937 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT936 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT935 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT934 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT933 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT932 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT931 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT930 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT929 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT928 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT927 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT926 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT925 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT924 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT923 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT922 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT921 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT920 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT919 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT918 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT917 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT916 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT915 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT914 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT913 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT912 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT911 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT910 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT909 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT908 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT907 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT906 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT905 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT904 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT903 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT902 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT901 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT900 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXDETECTRXPOWERDN3 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXOBPOWERDN3 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXANALOGRESETOUT3 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT896 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT897 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT898 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT899 ;
+wire \tx_datain[40]~input_o ;
+wire \tx_datain[41]~input_o ;
+wire \tx_datain[42]~input_o ;
+wire \tx_datain[43]~input_o ;
+wire \tx_datain[44]~input_o ;
+wire \tx_datain[45]~input_o ;
+wire \tx_datain[46]~input_o ;
+wire \tx_datain[47]~input_o ;
+wire \tx_datain[48]~input_o ;
+wire \tx_datain[49]~input_o ;
+wire \tx_datain[50]~input_o ;
+wire \tx_datain[51]~input_o ;
+wire \tx_datain[52]~input_o ;
+wire \tx_datain[53]~input_o ;
+wire \tx_datain[54]~input_o ;
+wire \tx_datain[55]~input_o ;
+wire \tx_datain[56]~input_o ;
+wire \tx_datain[57]~input_o ;
+wire \tx_datain[58]~input_o ;
+wire \tx_datain[59]~input_o ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT895 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT894 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT893 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT892 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT891 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT890 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT889 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT888 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT887 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT886 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT885 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT884 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT883 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT882 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT881 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT880 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT879 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT878 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT877 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT876 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT875 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT874 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT873 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT872 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT871 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT870 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT869 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT868 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT867 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT866 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT865 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT864 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT863 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT862 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT861 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT860 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT859 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT858 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT857 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT856 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT855 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT854 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT853 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT852 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT851 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT850 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT849 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT848 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT847 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT846 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT845 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT844 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT843 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT842 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT841 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT840 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT839 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT838 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT837 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT836 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT835 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT834 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT833 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT832 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT831 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT830 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT829 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT828 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT827 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT826 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT825 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT824 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT823 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT822 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT821 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT820 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT819 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT818 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT817 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT816 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT815 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT814 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT813 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT812 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT811 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT810 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT809 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT808 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT807 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT806 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT805 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT804 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT803 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT802 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT801 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT800 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT799 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT798 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT797 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT796 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT795 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT794 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT793 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT792 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT791 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT790 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT789 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT788 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT787 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT786 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT785 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT784 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT783 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT782 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT781 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT780 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT779 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT778 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT777 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT776 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT775 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT774 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT773 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT772 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT771 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT770 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT769 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT768 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT767 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT766 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT765 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT764 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT763 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT762 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT761 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT760 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT759 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT758 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT757 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT756 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT755 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT754 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT753 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT752 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT751 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT750 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT749 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT748 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT747 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT746 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT745 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT744 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT743 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT742 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT741 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT740 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT739 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT738 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT737 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT736 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT735 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT734 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT733 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT732 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT731 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT730 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT729 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT728 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT727 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT726 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT725 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT724 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT723 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT722 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT721 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT720 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT719 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT718 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT717 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT716 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT715 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT714 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT713 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT712 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT711 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT710 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT709 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT708 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT707 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT706 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT705 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT704 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT703 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT702 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT701 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT700 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT699 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT698 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT697 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT696 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT695 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT694 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT693 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT692 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT691 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT690 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT689 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT688 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT687 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT686 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT685 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT684 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT683 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT682 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT681 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT680 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT679 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT678 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT677 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT676 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT675 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT674 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT673 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT672 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT671 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT670 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT669 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT668 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT667 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT666 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT665 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT664 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT663 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT662 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT661 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT660 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT659 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT658 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT657 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT656 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT655 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT654 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT653 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT652 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT651 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT650 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT649 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT648 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT647 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT646 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT645 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT644 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT643 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT642 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT641 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT640 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT639 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT638 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT637 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT636 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT635 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT634 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT633 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT632 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT631 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT630 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT629 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT628 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT627 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT626 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT625 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT624 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT623 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT622 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT621 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT620 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT619 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT618 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT617 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT616 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT615 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT614 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT613 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT612 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT611 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT610 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT609 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT608 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT607 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT606 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT605 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT604 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT603 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT602 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT601 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT600 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXDETECTRXPOWERDN2 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXOBPOWERDN2 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXANALOGRESETOUT2 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT596 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT597 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT598 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT599 ;
+wire \tx_datain[20]~input_o ;
+wire \tx_datain[21]~input_o ;
+wire \tx_datain[22]~input_o ;
+wire \tx_datain[23]~input_o ;
+wire \tx_datain[24]~input_o ;
+wire \tx_datain[25]~input_o ;
+wire \tx_datain[26]~input_o ;
+wire \tx_datain[27]~input_o ;
+wire \tx_datain[28]~input_o ;
+wire \tx_datain[29]~input_o ;
+wire \tx_datain[30]~input_o ;
+wire \tx_datain[31]~input_o ;
+wire \tx_datain[32]~input_o ;
+wire \tx_datain[33]~input_o ;
+wire \tx_datain[34]~input_o ;
+wire \tx_datain[35]~input_o ;
+wire \tx_datain[36]~input_o ;
+wire \tx_datain[37]~input_o ;
+wire \tx_datain[38]~input_o ;
+wire \tx_datain[39]~input_o ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT595 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT594 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT593 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT592 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT591 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT590 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT589 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT588 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT587 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT586 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT585 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT584 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT583 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT582 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT581 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT580 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT579 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT578 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT577 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT576 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT575 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT574 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT573 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT572 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT571 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT570 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT569 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT568 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT567 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT566 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT565 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT564 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT563 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT562 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT561 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT560 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT559 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT558 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT557 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT556 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT555 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT554 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT553 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT552 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT551 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT550 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT549 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT548 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT547 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT546 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT545 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT544 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT543 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT542 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT541 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT540 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT539 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT538 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT537 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT536 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT535 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT534 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT533 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT532 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT531 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT530 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT529 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT528 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT527 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT526 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT525 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT524 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT523 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT522 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT521 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT520 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT519 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT518 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT517 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT516 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT515 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT514 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT513 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT512 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT511 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT510 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT509 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT508 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT507 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT506 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT505 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT504 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT503 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT502 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT501 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT500 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT499 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT498 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT497 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT496 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT495 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT494 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT493 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT492 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT491 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT490 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT489 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT488 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT487 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT486 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT485 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT484 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT483 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT482 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT481 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT480 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT479 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT478 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT477 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT476 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT475 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT474 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT473 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT472 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT471 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT470 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT469 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT468 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT467 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT466 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT465 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT464 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT463 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT462 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT461 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT460 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT459 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT458 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT457 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT456 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT455 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT454 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT453 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT452 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT451 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT450 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT449 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT448 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT447 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT446 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT445 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT444 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT443 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT442 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT441 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT440 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT439 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT438 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT437 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT436 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT435 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT434 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT433 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT432 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT431 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT430 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT429 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT428 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT427 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT426 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT425 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT424 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT423 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT422 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT421 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT420 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT419 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT418 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT417 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT416 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT415 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT414 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT413 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT412 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT411 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT410 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT409 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT408 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT407 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT406 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT405 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT404 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT403 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT402 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT401 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT400 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT399 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT398 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT397 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT396 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT395 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT394 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT393 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT392 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT391 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT390 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT389 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT388 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT387 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT386 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT385 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT384 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT383 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT382 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT381 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT380 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT379 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT378 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT377 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT376 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT375 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT374 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT373 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT372 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT371 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT370 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT369 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT368 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT367 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT366 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT365 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT364 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT363 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT362 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT361 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT360 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT359 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT358 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT357 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT356 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT355 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT354 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT353 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT352 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT351 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT350 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT349 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT348 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT347 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT346 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT345 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT344 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT343 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT342 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT341 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT340 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT339 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT338 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT337 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT336 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT335 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT334 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT333 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT332 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT331 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT330 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT329 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT328 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT327 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT326 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT325 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT324 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT323 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT322 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT321 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT320 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT319 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT318 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT317 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT316 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT315 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT314 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT313 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT312 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT311 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT310 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT309 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT308 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT307 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT306 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT305 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT304 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT303 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT302 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT301 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT300 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXDETECTRXPOWERDN1 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXOBPOWERDN1 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXANALOGRESETOUT1 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT295 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT296 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT297 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT298 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT299 ;
+wire \tx_datain[0]~input_o ;
+wire \tx_datain[1]~input_o ;
+wire \tx_datain[2]~input_o ;
+wire \tx_datain[3]~input_o ;
+wire \tx_datain[4]~input_o ;
+wire \tx_datain[5]~input_o ;
+wire \tx_datain[6]~input_o ;
+wire \tx_datain[7]~input_o ;
+wire \tx_datain[8]~input_o ;
+wire \tx_datain[9]~input_o ;
+wire \tx_datain[10]~input_o ;
+wire \tx_datain[11]~input_o ;
+wire \tx_datain[12]~input_o ;
+wire \tx_datain[13]~input_o ;
+wire \tx_datain[14]~input_o ;
+wire \tx_datain[15]~input_o ;
+wire \tx_datain[16]~input_o ;
+wire \tx_datain[17]~input_o ;
+wire \tx_datain[18]~input_o ;
+wire \tx_datain[19]~input_o ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT294 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT293 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT292 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT291 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT290 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT289 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT288 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT287 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT286 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT285 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT284 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT283 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT282 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT281 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT280 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT279 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT278 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT277 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT276 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT275 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT274 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT273 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT272 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT271 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT270 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT269 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT268 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT267 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT266 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT265 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT264 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT263 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT262 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT261 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT260 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT259 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT258 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT257 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT256 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT255 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT254 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT253 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT252 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT251 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT250 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT249 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT248 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT247 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT246 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT245 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT244 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT243 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT242 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT241 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT240 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT239 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT238 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT237 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT236 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT235 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT234 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT233 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT232 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT231 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT230 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT229 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT228 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT227 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT226 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT225 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT224 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT223 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT222 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT221 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT220 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT219 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT218 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT217 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT216 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT215 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT214 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT213 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT212 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT211 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT210 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT209 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT208 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT207 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT206 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT205 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT204 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT203 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT202 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT201 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT200 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT199 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT198 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT197 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT196 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT195 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT194 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT193 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT192 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT191 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT190 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT189 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT188 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT187 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT186 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT185 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT184 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT183 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT182 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT181 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT180 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT179 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT178 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT177 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT176 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT175 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT174 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT173 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT172 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT171 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT170 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT169 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT168 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT167 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT166 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT165 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT164 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT163 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT162 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT161 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT160 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT159 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT158 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT157 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT156 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT155 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT154 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT153 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT152 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT151 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT150 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT149 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT148 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT147 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT146 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT145 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT144 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT143 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT142 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT141 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT140 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT139 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT138 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT137 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT136 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT135 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT134 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT133 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT132 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT131 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT130 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT129 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT128 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT127 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT126 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT125 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT124 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT123 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT122 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT121 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT120 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT119 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT118 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT117 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT116 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT115 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT114 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT113 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT112 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT111 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT110 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT109 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT108 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT107 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT106 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT105 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT104 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT103 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT102 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT101 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT100 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT99 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT98 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT97 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT96 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT95 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT94 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT93 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT92 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT91 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT90 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT89 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT88 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT87 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT86 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT85 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT84 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT83 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT82 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT81 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT80 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT79 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT78 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT77 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT76 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT75 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT74 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT73 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT72 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT71 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT70 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT69 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT68 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT67 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT66 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT65 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT64 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT63 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT62 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT61 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT60 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT59 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT58 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT57 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT56 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT55 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT54 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT53 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT52 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT51 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT50 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT49 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT48 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT47 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT46 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT45 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT44 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT43 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT42 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT41 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT40 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT39 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT38 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT37 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT36 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT35 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT34 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT33 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT32 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT31 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT30 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT29 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT28 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT27 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT26 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT25 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT24 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT23 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT22 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT21 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT20 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT19 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT18 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT17 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT16 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT15 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT14 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT13 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT12 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT11 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT10 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT9 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT8 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT7 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT6 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT5 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT4 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT3 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT2 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT0 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXDETECTRXPOWERDN0 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXOBPOWERDN0 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~TXANALOGRESETOUT0 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1197 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1198 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1199 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1196 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1195 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1194 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1193 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1192 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1191 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1190 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1189 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1188 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1187 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1186 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1185 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1184 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1183 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1182 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1181 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1180 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1179 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1178 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1177 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1176 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1175 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1174 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1173 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1172 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1171 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1170 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1169 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1168 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1167 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1166 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1165 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1164 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1163 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1162 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1161 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1160 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1159 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1158 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1157 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1156 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1155 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1154 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1153 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1152 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1151 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1150 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1149 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1148 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1147 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1146 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1145 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1144 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1143 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1142 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1141 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1140 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1139 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1138 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1137 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1136 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1135 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1134 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1133 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1132 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1131 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1130 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1129 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1128 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1127 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1126 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1125 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1124 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1123 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1122 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1121 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1120 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1119 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1118 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1117 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1116 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1115 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1114 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1113 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1112 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1111 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1110 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1109 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1108 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1107 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1106 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1105 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1104 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1103 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1102 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1101 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1100 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1099 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1098 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1097 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1096 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1095 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1094 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1093 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1092 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1091 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1090 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1089 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1088 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1087 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1086 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1085 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1084 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1083 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1082 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1081 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1080 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1079 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1078 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1077 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1076 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1075 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1074 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1073 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1072 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1071 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1070 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1069 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1068 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1067 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1066 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1065 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1064 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1063 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1062 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1061 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1060 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1059 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1058 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1057 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1056 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1055 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1054 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1053 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1052 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1051 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1050 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1049 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1048 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1047 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1046 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1045 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1044 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1043 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1042 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1041 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1040 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1039 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1038 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1037 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1036 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1035 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1034 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1033 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1032 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1031 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1030 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1029 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1028 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1027 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1026 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1025 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1024 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1023 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1022 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1021 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1020 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1019 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1018 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1017 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1016 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1015 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1014 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1013 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1012 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1011 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1010 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1009 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1008 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1007 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1006 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1005 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1004 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1003 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1002 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1001 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1000 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT999 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT998 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT997 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT996 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT995 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT994 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT993 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT992 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT991 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT990 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT989 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT988 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT987 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT986 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT985 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT984 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT983 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT982 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT981 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT980 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT979 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT978 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT977 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT976 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT975 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT974 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT973 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT972 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT971 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT970 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT969 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT968 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT967 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT966 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT965 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT964 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT963 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT962 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT961 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT960 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT959 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT958 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT957 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT956 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT955 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT954 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT953 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT952 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT951 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT950 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT949 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT948 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT947 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT946 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT945 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT944 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT943 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT942 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT941 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT940 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT939 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT938 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT937 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT936 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT935 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT934 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT933 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT932 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT931 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT930 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT929 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT928 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT927 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT926 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT925 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT924 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT923 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT922 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT921 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT920 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT919 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT918 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT917 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT916 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT915 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT914 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT913 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT912 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT911 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT910 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT909 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT908 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT907 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT906 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT905 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT904 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT903 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT902 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT901 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT900 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT897 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT898 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT899 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXCRUPOWERDN2 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXCRURESETOUT2 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT896 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT895 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT894 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT893 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT892 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT891 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT890 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT889 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT888 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT887 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT886 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT885 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT884 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT883 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT882 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT881 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT880 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT879 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT878 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT877 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT876 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT875 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT874 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT873 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT872 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT871 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT870 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT869 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT868 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT867 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT866 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT865 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT864 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT863 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT862 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT861 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT860 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT859 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT858 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT857 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT856 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT855 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT854 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT853 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT852 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT851 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT850 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT849 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT848 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT847 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT846 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT845 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT844 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT843 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT842 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT841 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT840 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT839 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT838 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT837 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT836 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT835 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT834 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT833 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT832 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT831 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT830 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT829 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT828 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT827 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT826 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT825 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT824 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT823 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT822 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT821 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT820 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT819 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT818 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT817 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT816 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT815 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT814 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT813 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT812 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT811 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT810 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT809 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT808 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT807 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT806 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT805 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT804 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT803 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT802 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT801 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT800 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT799 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT798 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT797 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT796 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT795 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT794 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT793 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT792 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT791 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT790 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT789 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT788 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT787 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT786 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT785 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT784 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT783 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT782 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT781 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT780 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT779 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT778 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT777 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT776 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT775 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT774 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT773 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT772 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT771 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT770 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT769 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT768 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT767 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT766 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT765 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT764 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT763 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT762 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT761 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT760 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT759 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT758 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT757 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT756 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT755 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT754 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT753 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT752 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT751 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT750 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT749 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT748 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT747 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT746 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT745 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT744 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT743 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT742 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT741 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT740 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT739 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT738 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT737 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT736 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT735 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT734 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT733 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT732 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT731 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT730 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT729 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT728 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT727 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT726 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT725 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT724 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT723 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT722 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT721 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT720 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT719 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT718 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT717 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT716 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT715 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT714 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT713 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT712 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT711 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT710 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT709 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT708 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT707 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT706 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT705 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT704 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT703 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT702 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT701 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT700 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT699 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT698 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT697 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT696 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT695 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT694 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT693 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT692 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT691 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT690 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT689 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT688 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT687 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT686 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT685 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT684 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT683 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT682 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT681 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT680 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT679 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT678 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT677 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT676 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT675 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT674 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT673 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT672 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT671 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT670 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT669 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT668 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT667 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT666 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT665 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT664 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT663 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT662 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT661 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT660 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT659 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT658 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT657 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT656 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT655 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT654 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT653 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT652 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT651 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT650 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT649 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT648 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT647 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT646 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT645 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT644 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT643 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT642 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT641 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT640 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT639 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT638 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT637 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT636 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT635 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT634 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT633 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT632 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT631 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT630 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT629 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT628 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT627 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT626 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT625 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT624 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT623 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT622 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT621 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT620 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT619 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT618 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT617 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT616 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT615 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT614 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT613 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT612 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT611 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT610 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT609 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT608 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT607 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT606 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT605 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT604 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT603 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT602 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT601 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT600 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXANALOGRESETOUT2 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXIBPOWERDN2 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT597 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT598 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT599 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXCRUPOWERDN1 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXCRURESETOUT1 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT596 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT595 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT594 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT593 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT592 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT591 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT590 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT589 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT588 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT587 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT586 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT585 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT584 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT583 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT582 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT581 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT580 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT579 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT578 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT577 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT576 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT575 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT574 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT573 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT572 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT571 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT570 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT569 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT568 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT567 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT566 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT565 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT564 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT563 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT562 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT561 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT560 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT559 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT558 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT557 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT556 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT555 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT554 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT553 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT552 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT551 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT550 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT549 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT548 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT547 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT546 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT545 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT544 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT543 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT542 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT541 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT540 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT539 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT538 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT537 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT536 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT535 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT534 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT533 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT532 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT531 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT530 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT529 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT528 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT527 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT526 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT525 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT524 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT523 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT522 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT521 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT520 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT519 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT518 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT517 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT516 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT515 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT514 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT513 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT512 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT511 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT510 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT509 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT508 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT507 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT506 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT505 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT504 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT503 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT502 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT501 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT500 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT499 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT498 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT497 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT496 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT495 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT494 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT493 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT492 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT491 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT490 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT489 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT488 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT487 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT486 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT485 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT484 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT483 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT482 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT481 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT480 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT479 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT478 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT477 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT476 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT475 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT474 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT473 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT472 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT471 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT470 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT469 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT468 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT467 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT466 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT465 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT464 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT463 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT462 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT461 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT460 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT459 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT458 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT457 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT456 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT455 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT454 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT453 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT452 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT451 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT450 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT449 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT448 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT447 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT446 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT445 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT444 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT443 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT442 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT441 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT440 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT439 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT438 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT437 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT436 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT435 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT434 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT433 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT432 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT431 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT430 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT429 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT428 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT427 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT426 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT425 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT424 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT423 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT422 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT421 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT420 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT419 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT418 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT417 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT416 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT415 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT414 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT413 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT412 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT411 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT410 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT409 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT408 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT407 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT406 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT405 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT404 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT403 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT402 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT401 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT400 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT399 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT398 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT397 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT396 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT395 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT394 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT393 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT392 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT391 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT390 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT389 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT388 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT387 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT386 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT385 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT384 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT383 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT382 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT381 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT380 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT379 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT378 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT377 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT376 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT375 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT374 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT373 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT372 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT371 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT370 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT369 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT368 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT367 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT366 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT365 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT364 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT363 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT362 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT361 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT360 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT359 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT358 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT357 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT356 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT355 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT354 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT353 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT352 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT351 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT350 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT349 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT348 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT347 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT346 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT345 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT344 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT343 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT342 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT341 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT340 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT339 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT338 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT337 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT336 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT335 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT334 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT333 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT332 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT331 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT330 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT329 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT328 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT327 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT326 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT325 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT324 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT323 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT322 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT321 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT320 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT319 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT318 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT317 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT316 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT315 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT314 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT313 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT312 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT311 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT310 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT309 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT308 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT307 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT306 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT305 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT304 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT303 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT302 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT301 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT300 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXANALOGRESETOUT1 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXIBPOWERDN1 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT297 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT298 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT299 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXCRUPOWERDN0 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXCRURESETOUT0 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT296 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT295 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT294 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT293 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT292 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT291 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT290 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT289 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT288 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT287 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT286 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT285 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT284 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT283 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT282 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT281 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT280 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT279 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT278 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT277 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT276 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT275 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT274 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT273 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT272 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT271 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT270 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT269 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT268 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT267 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT266 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT265 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT264 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT263 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT262 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT261 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT260 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT259 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT258 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT257 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT256 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT255 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT254 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT253 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT252 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT251 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT250 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT249 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT248 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT247 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT246 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT245 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT244 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT243 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT242 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT241 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT240 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT239 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT238 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT237 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT236 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT235 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT234 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT233 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT232 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT231 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT230 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT229 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT228 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT227 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT226 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT225 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT224 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT223 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT222 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT221 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT220 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT219 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT218 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT217 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT216 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT215 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT214 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT213 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT212 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT211 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT210 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT209 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT208 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT207 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT206 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT205 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT204 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT203 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT202 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT201 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT200 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT199 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT198 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT197 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT196 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT195 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT194 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT193 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT192 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT191 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT190 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT189 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT188 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT187 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT186 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT185 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT184 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT183 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT182 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT181 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT180 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT179 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT178 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT177 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT176 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT175 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT174 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT173 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT172 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT171 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT170 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT169 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT168 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT167 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT166 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT165 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT164 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT163 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT162 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT161 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT160 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT159 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT158 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT157 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT156 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT155 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT154 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT153 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT152 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT151 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT150 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT149 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT148 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT147 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT146 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT145 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT144 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT143 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT142 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT141 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT140 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT139 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT138 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT137 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT136 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT135 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT134 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT133 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT132 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT131 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT130 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT129 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT128 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT127 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT126 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT125 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT124 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT123 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT122 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT121 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT120 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT119 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT118 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT117 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT116 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT115 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT114 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT113 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT112 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT111 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT110 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT109 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT108 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT107 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT106 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT105 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT104 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT103 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT102 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT101 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT100 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT99 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT98 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT97 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT96 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT95 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT94 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT93 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT92 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT91 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT90 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT89 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT88 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT87 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT86 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT85 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT84 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT83 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT82 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT81 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT80 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT79 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT78 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT77 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT76 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT75 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT74 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT73 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT72 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT71 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT70 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT69 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT68 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT67 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT66 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT65 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT64 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT63 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT62 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT61 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT60 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT59 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT58 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT57 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT56 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT55 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT54 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT53 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT52 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT51 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT50 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT49 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT48 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT47 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT46 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT45 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT44 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT43 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT42 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT41 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT40 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT39 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT38 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT37 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT36 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT35 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT34 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT33 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT32 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT31 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT30 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT29 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT28 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT27 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT26 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT25 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT24 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT23 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT22 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT21 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT20 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT19 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT18 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT17 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT16 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT15 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT14 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT13 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT12 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT11 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT10 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT9 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT8 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT7 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT6 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT5 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT4 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT3 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT2 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT0 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXANALOGRESETOUT0 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXIBPOWERDN0 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXCRURESETOUT3 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXCRUPOWERDN3 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXANALOGRESETOUT3 ;
+wire \pma_direct|auto_generated|tx_pll_cent_unit0~RXIBPOWERDN3 ;
+wire \~QUARTUS_CREATED_GND~I_combout ;
+wire \pma_direct|auto_generated|wire_transmit_pma0_dataout ;
+wire \pma_direct|auto_generated|wire_transmit_pma1_dataout ;
+wire \pma_direct|auto_generated|wire_transmit_pma2_dataout ;
+wire \pma_direct|auto_generated|wire_transmit_pma3_dataout ;
+wire \pma_direct|auto_generated|wire_transmit_pma0_clockout ;
+wire \pma_direct|auto_generated|wire_transmit_pma0_clockout~clkctrl_outclk ;
+wire \pma_direct|auto_generated|wire_transmit_pma1_clockout ;
+wire \pma_direct|auto_generated|wire_transmit_pma1_clockout~clkctrl_outclk ;
+wire \pma_direct|auto_generated|wire_transmit_pma2_clockout ;
+wire \pma_direct|auto_generated|wire_transmit_pma2_clockout~clkctrl_outclk ;
+wire \pma_direct|auto_generated|wire_transmit_pma3_clockout ;
+wire \pma_direct|auto_generated|wire_transmit_pma3_clockout~clkctrl_outclk ;
+wire \pma_direct|auto_generated|wire_receive_pma0_clockout ;
+wire \pma_direct|auto_generated|wire_receive_pma0_clockout~clkctrl_outclk ;
+wire \pma_direct|auto_generated|wire_receive_pma1_clockout ;
+wire \pma_direct|auto_generated|wire_receive_pma1_clockout~clkctrl_outclk ;
+wire \pma_direct|auto_generated|wire_receive_pma2_clockout ;
+wire \pma_direct|auto_generated|wire_receive_pma2_clockout~clkctrl_outclk ;
+wire \pma_direct|auto_generated|wire_receive_pma3_clockout ;
+wire \pma_direct|auto_generated|wire_receive_pma3_clockout~clkctrl_outclk ;
+wire \pma_direct|auto_generated|wire_rx_cdr_pll0_freqlocked ;
+wire \pma_direct|auto_generated|wire_rx_cdr_pll1_freqlocked ;
+wire \pma_direct|auto_generated|wire_rx_cdr_pll2_freqlocked ;
+wire \pma_direct|auto_generated|wire_rx_cdr_pll3_freqlocked ;
+wire [1199:0] \pma_direct|auto_generated|cent_unit_txpmadprioin ;
+wire [0:0] \pma_direct|auto_generated|edge_cmu_clkdivpowerdn ;
+wire [0:0] \pma_direct|auto_generated|edge_pll_analogrefclkpulse ;
+wire [299:0] \pma_direct|auto_generated|edge_pll_cmuplldprioout ;
+wire [299:0] \pma_direct|auto_generated|edge_pll_dprioin ;
+wire [0:0] \pma_direct|auto_generated|edge_pllpowerdn_in ;
+wire [7199:0] \pma_direct|auto_generated|pll_cmuplldprioout ;
+wire [63:0] \pma_direct|auto_generated|wire_receive_pma0_recoverdataout ;
+wire [7:0] \pma_direct|auto_generated|wire_receive_pma1_analogtestbus ;
+wire [0:0] \pma_direct|auto_generated|edge_cmu_dpriodisableout ;
+wire [0:0] \pma_direct|auto_generated|edge_cmu_quadresetout ;
+wire [1:0] \pma_direct|auto_generated|edge_pll_analogfastrefclkout ;
+wire [1:0] \pma_direct|auto_generated|edge_pll_analogrefclkout ;
+wire [0:0] \pma_direct|auto_generated|edge_pllreset_in ;
+wire [3:0] \pma_direct|auto_generated|nonusertocmu_out ;
+wire [7:0] \pma_direct|auto_generated|pll_ch_dataout_wire ;
+wire [3:0] \pma_direct|auto_generated|rx_locktodata_wire ;
+wire [3:0] \pma_direct|auto_generated|rx_pll_locked ;
+wire [3:0] \pma_direct|auto_generated|rx_pll_pfdrefclkout_wire ;
+wire [3:0] \pma_direct|auto_generated|rx_plllocked_wire ;
+wire [3:0] \pma_direct|auto_generated|rx_pma_dataout ;
+wire [3:0] \pma_direct|auto_generated|rx_pma_locktorefout ;
+wire [63:0] \pma_direct|auto_generated|wire_receive_pma1_recoverdataout ;
+wire [63:0] \pma_direct|auto_generated|wire_receive_pma2_recoverdataout ;
+wire [7:0] \pma_direct|auto_generated|wire_receive_pma3_analogtestbus ;
+wire [63:0] \pma_direct|auto_generated|wire_receive_pma3_recoverdataout ;
+wire [1799:0] \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout ;
+wire [1199:0] \pma_direct|auto_generated|cent_unit_rxpmadprioin ;
+wire [3:0] \pma_direct|auto_generated|clock_divider_clk0in ;
+wire [599:0] \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin ;
+wire [99:0] \pma_direct|auto_generated|edge_cmu_cmudividerdprioout ;
+wire [0:0] \pma_direct|auto_generated|pll_locked ;
+wire [0:0] \pma_direct|auto_generated|refclk_pma_wire ;
+wire [23:0] \pma_direct|auto_generated|rx_analogreset_in ;
+wire [15:0] \pma_direct|auto_generated|rx_deserclock_in ;
+wire [3:0] \pma_direct|auto_generated|rx_freqlocked ;
+wire [7:0] \pma_direct|auto_generated|wire_receive_pma0_analogtestbus ;
+wire [7:0] \pma_direct|auto_generated|wire_receive_pma2_analogtestbus ;
+
+wire [1:0] \pma_direct|auto_generated|tx_pll_edge0_DATAOUT_bus ;
+wire [3:0] \pma_direct|auto_generated|tx_pll_edge0_CLK_bus ;
+wire [299:0] \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus ;
+wire [299:0] \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus ;
+wire [7:0] \pma_direct|auto_generated|receive_pma0_ANALOGTESTBUS_bus ;
+wire [63:0] \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus ;
+wire [299:0] \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus ;
+wire [7:0] \pma_direct|auto_generated|receive_pma1_ANALOGTESTBUS_bus ;
+wire [63:0] \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus ;
+wire [299:0] \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus ;
+wire [7:0] \pma_direct|auto_generated|receive_pma2_ANALOGTESTBUS_bus ;
+wire [63:0] \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus ;
+wire [299:0] \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus ;
+wire [7:0] \pma_direct|auto_generated|receive_pma3_ANALOGTESTBUS_bus ;
+wire [63:0] \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus ;
+wire [299:0] \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus ;
+wire [299:0] \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus ;
+wire [299:0] \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus ;
+wire [299:0] \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus ;
+wire [1:0] \pma_direct|auto_generated|rx_cdr_pll0_DATAOUT_bus ;
+wire [3:0] \pma_direct|auto_generated|rx_cdr_pll0_CLK_bus ;
+wire [1:0] \pma_direct|auto_generated|rx_cdr_pll1_DATAOUT_bus ;
+wire [3:0] \pma_direct|auto_generated|rx_cdr_pll1_CLK_bus ;
+wire [1:0] \pma_direct|auto_generated|rx_cdr_pll2_DATAOUT_bus ;
+wire [3:0] \pma_direct|auto_generated|rx_cdr_pll2_CLK_bus ;
+wire [1:0] \pma_direct|auto_generated|rx_cdr_pll3_DATAOUT_bus ;
+wire [3:0] \pma_direct|auto_generated|rx_cdr_pll3_CLK_bus ;
+wire [299:0] \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus ;
+wire [1:0] \pma_direct|auto_generated|tx_pll_cent_unit0_PLLRESETOUT_bus ;
+wire [5:0] \pma_direct|auto_generated|tx_pll_cent_unit0_TXANALOGRESETOUT_bus ;
+wire [5:0] \pma_direct|auto_generated|tx_pll_cent_unit0_RXANALOGRESETOUT_bus ;
+wire [1799:0] \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus ;
+wire [599:0] \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus ;
+wire [1799:0] \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus ;
+wire [1799:0] \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus ;
+wire [5:0] \pma_direct|auto_generated|tx_pll_cent_unit0_RXCRURESETOUT_bus ;
+wire [5:0] \pma_direct|auto_generated|tx_pll_cent_unit0_RXCRUPOWERDOWN_bus ;
+wire [5:0] \pma_direct|auto_generated|tx_pll_cent_unit0_RXIBPOWERDOWN_bus ;
+wire [5:0] \pma_direct|auto_generated|tx_pll_cent_unit0_TXOBPOWERDOWN_bus ;
+wire [5:0] \pma_direct|auto_generated|tx_pll_cent_unit0_TXDETECTRXPOWERDOWN_bus ;
+wire [1:0] \pma_direct|auto_generated|tx_pll_cent_unit0_CLKDIVPOWERDN_bus ;
+wire [1:0] \pma_direct|auto_generated|tx_pll_cent_unit0_PLLPOWERDN_bus ;
+wire [4:0] \pma_direct|auto_generated|cal_blk0_CALIBRATIONSTATUS_bus ;
+wire [99:0] \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus ;
+wire [1:0] \pma_direct|auto_generated|central_clk_div0_ANALOGREFCLKOUT_bus ;
+wire [1:0] \pma_direct|auto_generated|central_clk_div0_ANALOGFASTREFCLKOUT_bus ;
+
+assign \pma_direct|auto_generated|tx_pll_edge0~DATAOUT0 = \pma_direct|auto_generated|tx_pll_edge0_DATAOUT_bus [0];
+assign \pma_direct|auto_generated|tx_pll_edge0~DATAOUT1 = \pma_direct|auto_generated|tx_pll_edge0_DATAOUT_bus [1];
+
+assign \pma_direct|auto_generated|clock_divider_clk0in [0] = \pma_direct|auto_generated|tx_pll_edge0_CLK_bus [0];
+assign \pma_direct|auto_generated|clock_divider_clk0in [1] = \pma_direct|auto_generated|tx_pll_edge0_CLK_bus [1];
+assign \pma_direct|auto_generated|clock_divider_clk0in [2] = \pma_direct|auto_generated|tx_pll_edge0_CLK_bus [2];
+assign \pma_direct|auto_generated|clock_divider_clk0in [3] = \pma_direct|auto_generated|tx_pll_edge0_CLK_bus [3];
+
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [0] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [0];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [1] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [1];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [2] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [2];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [3] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [3];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [4] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [4];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [5] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [5];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [6] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [6];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [7] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [7];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [8] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [8];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [9] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [9];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [10] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [10];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [11] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [11];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [12] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [12];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [13] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [13];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [14] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [14];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [15] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [15];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [16] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [16];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [17] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [17];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [18] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [18];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [19] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [19];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [20] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [20];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [21] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [21];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [22] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [22];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [23] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [23];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [24] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [24];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [25] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [25];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [26] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [26];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [27] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [27];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [28] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [28];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [29] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [29];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [30] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [30];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [31] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [31];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [32] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [32];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [33] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [33];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [34] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [34];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [35] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [35];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [36] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [36];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [37] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [37];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [38] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [38];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [39] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [39];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [40] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [40];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [41] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [41];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [42] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [42];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [43] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [43];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [44] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [44];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [45] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [45];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [46] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [46];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [47] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [47];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [48] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [48];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [49] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [49];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [50] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [50];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [51] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [51];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [52] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [52];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [53] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [53];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [54] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [54];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [55] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [55];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [56] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [56];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [57] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [57];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [58] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [58];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [59] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [59];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [60] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [60];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [61] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [61];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [62] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [62];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [63] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [63];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [64] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [64];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [65] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [65];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [66] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [66];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [67] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [67];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [68] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [68];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [69] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [69];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [70] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [70];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [71] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [71];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [72] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [72];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [73] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [73];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [74] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [74];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [75] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [75];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [76] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [76];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [77] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [77];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [78] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [78];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [79] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [79];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [80] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [80];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [81] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [81];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [82] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [82];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [83] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [83];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [84] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [84];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [85] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [85];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [86] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [86];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [87] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [87];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [88] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [88];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [89] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [89];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [90] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [90];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [91] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [91];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [92] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [92];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [93] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [93];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [94] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [94];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [95] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [95];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [96] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [96];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [97] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [97];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [98] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [98];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [99] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [99];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [100] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [100];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [101] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [101];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [102] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [102];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [103] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [103];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [104] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [104];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [105] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [105];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [106] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [106];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [107] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [107];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [108] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [108];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [109] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [109];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [110] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [110];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [111] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [111];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [112] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [112];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [113] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [113];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [114] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [114];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [115] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [115];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [116] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [116];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [117] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [117];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [118] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [118];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [119] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [119];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [120] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [120];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [121] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [121];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [122] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [122];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [123] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [123];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [124] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [124];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [125] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [125];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [126] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [126];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [127] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [127];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [128] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [128];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [129] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [129];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [130] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [130];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [131] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [131];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [132] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [132];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [133] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [133];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [134] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [134];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [135] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [135];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [136] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [136];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [137] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [137];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [138] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [138];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [139] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [139];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [140] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [140];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [141] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [141];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [142] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [142];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [143] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [143];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [144] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [144];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [145] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [145];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [146] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [146];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [147] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [147];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [148] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [148];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [149] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [149];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [150] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [150];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [151] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [151];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [152] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [152];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [153] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [153];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [154] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [154];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [155] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [155];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [156] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [156];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [157] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [157];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [158] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [158];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [159] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [159];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [160] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [160];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [161] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [161];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [162] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [162];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [163] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [163];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [164] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [164];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [165] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [165];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [166] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [166];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [167] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [167];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [168] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [168];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [169] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [169];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [170] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [170];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [171] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [171];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [172] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [172];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [173] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [173];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [174] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [174];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [175] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [175];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [176] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [176];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [177] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [177];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [178] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [178];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [179] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [179];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [180] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [180];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [181] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [181];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [182] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [182];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [183] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [183];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [184] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [184];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [185] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [185];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [186] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [186];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [187] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [187];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [188] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [188];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [189] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [189];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [190] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [190];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [191] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [191];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [192] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [192];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [193] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [193];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [194] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [194];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [195] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [195];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [196] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [196];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [197] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [197];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [198] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [198];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [199] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [199];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [200] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [200];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [201] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [201];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [202] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [202];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [203] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [203];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [204] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [204];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [205] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [205];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [206] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [206];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [207] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [207];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [208] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [208];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [209] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [209];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [210] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [210];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [211] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [211];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [212] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [212];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [213] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [213];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [214] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [214];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [215] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [215];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [216] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [216];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [217] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [217];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [218] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [218];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [219] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [219];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [220] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [220];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [221] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [221];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [222] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [222];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [223] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [223];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [224] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [224];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [225] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [225];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [226] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [226];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [227] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [227];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [228] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [228];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [229] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [229];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [230] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [230];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [231] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [231];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [232] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [232];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [233] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [233];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [234] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [234];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [235] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [235];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [236] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [236];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [237] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [237];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [238] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [238];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [239] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [239];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [240] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [240];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [241] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [241];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [242] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [242];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [243] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [243];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [244] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [244];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [245] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [245];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [246] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [246];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [247] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [247];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [248] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [248];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [249] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [249];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [250] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [250];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [251] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [251];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [252] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [252];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [253] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [253];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [254] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [254];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [255] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [255];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [256] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [256];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [257] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [257];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [258] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [258];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [259] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [259];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [260] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [260];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [261] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [261];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [262] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [262];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [263] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [263];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [264] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [264];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [265] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [265];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [266] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [266];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [267] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [267];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [268] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [268];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [269] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [269];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [270] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [270];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [271] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [271];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [272] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [272];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [273] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [273];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [274] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [274];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [275] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [275];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [276] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [276];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [277] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [277];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [278] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [278];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [279] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [279];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [280] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [280];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [281] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [281];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [282] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [282];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [283] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [283];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [284] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [284];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [285] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [285];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [286] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [286];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [287] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [287];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [288] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [288];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [289] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [289];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [290] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [290];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [291] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [291];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [292] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [292];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [293] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [293];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [294] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [294];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [295] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [295];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [296] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [296];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [297] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [297];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [298] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [298];
+assign \pma_direct|auto_generated|edge_pll_cmuplldprioout [299] = \pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus [299];
+
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [0] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [0];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [1];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [2] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [2];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [3] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [3];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [4] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [4];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [5] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [5];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [6] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [6];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [7] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [7];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [8] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [8];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [9] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [9];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [10] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [10];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [11] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [11];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [12] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [12];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [13] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [13];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [14] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [14];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [15] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [15];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [16] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [16];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [17] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [17];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [18] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [18];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [19] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [19];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [20] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [20];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [21] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [21];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [22] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [22];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [23] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [23];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [24] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [24];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [25] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [25];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [26] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [26];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [27] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [27];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [28] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [28];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [29] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [29];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [30] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [30];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [31] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [31];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [32] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [32];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [33] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [33];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [34] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [34];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [35] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [35];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [36] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [36];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [37] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [37];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [38] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [38];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [39] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [39];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [40] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [40];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [41] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [41];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [42] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [42];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [43] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [43];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [44] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [44];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [45] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [45];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [46] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [46];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [47] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [47];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [48] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [48];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [49] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [49];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [50] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [50];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [51] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [51];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [52] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [52];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [53] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [53];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [54] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [54];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [55] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [55];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [56] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [56];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [57] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [57];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [58] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [58];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [59] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [59];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [60] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [60];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [61] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [61];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [62] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [62];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [63] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [63];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [64] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [64];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [65] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [65];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [66] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [66];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [67] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [67];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [68] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [68];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [69] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [69];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [70] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [70];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [71] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [71];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [72] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [72];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [73] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [73];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [74] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [74];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [75] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [75];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [76] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [76];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [77] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [77];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [78] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [78];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [79] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [79];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [80] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [80];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [81] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [81];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [82] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [82];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [83] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [83];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [84] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [84];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [85] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [85];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [86] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [86];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [87] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [87];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [88] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [88];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [89] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [89];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [90] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [90];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [91] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [91];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [92] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [92];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [93] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [93];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [94] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [94];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [95] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [95];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [96] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [96];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [97] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [97];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [98] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [98];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [99] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [99];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [100] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [100];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [101] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [101];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [102] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [102];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [103] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [103];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [104] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [104];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [105] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [105];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [106] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [106];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [107] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [107];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [108] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [108];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [109] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [109];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [110] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [110];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [111] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [111];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [112] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [112];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [113] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [113];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [114] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [114];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [115] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [115];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [116] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [116];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [117] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [117];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [118] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [118];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [119] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [119];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [120] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [120];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [121] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [121];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [122] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [122];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [123] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [123];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [124] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [124];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [125] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [125];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [126] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [126];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [127] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [127];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [128] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [128];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [129] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [129];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [130] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [130];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [131] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [131];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [132] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [132];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [133] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [133];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [134] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [134];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [135] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [135];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [136] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [136];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [137] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [137];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [138] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [138];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [139] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [139];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [140] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [140];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [141] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [141];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [142] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [142];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [143] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [143];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [144] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [144];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [145] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [145];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [146] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [146];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [147] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [147];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [148] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [148];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [149] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [149];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [150] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [150];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [151] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [151];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [152] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [152];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [153] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [153];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [154] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [154];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [155] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [155];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [156] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [156];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [157] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [157];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [158] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [158];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [159] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [159];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [160] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [160];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [161] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [161];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [162] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [162];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [163] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [163];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [164] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [164];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [165] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [165];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [166] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [166];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [167] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [167];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [168] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [168];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [169] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [169];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [170] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [170];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [171] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [171];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [172] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [172];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [173] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [173];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [174] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [174];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [175] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [175];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [176] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [176];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [177] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [177];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [178] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [178];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [179] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [179];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [180] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [180];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [181] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [181];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [182] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [182];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [183] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [183];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [184] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [184];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [185] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [185];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [186] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [186];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [187] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [187];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [188] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [188];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [189] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [189];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [190] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [190];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [191] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [191];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [192] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [192];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [193] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [193];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [194] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [194];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [195] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [195];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [196] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [196];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [197] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [197];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [198] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [198];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [199] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [199];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [200] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [200];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [201] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [201];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [202] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [202];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [203] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [203];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [204] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [204];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [205] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [205];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [206] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [206];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [207] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [207];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [208] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [208];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [209] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [209];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [210] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [210];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [211] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [211];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [212] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [212];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [213] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [213];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [214] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [214];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [215] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [215];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [216] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [216];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [217] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [217];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [218] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [218];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [219] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [219];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [220] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [220];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [221] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [221];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [222] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [222];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [223] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [223];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [224] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [224];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [225] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [225];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [226] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [226];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [227] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [227];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [228] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [228];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [229] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [229];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [230] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [230];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [231] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [231];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [232] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [232];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [233] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [233];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [234] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [234];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [235] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [235];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [236] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [236];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [237] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [237];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [238] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [238];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [239] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [239];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [240] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [240];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [241] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [241];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [242] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [242];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [243] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [243];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [244] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [244];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [245] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [245];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [246] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [246];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [247] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [247];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [248] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [248];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [249] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [249];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [250] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [250];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [251] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [251];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [252] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [252];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [253] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [253];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [254] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [254];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [255] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [255];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [256] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [256];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [257] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [257];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [258] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [258];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [259] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [259];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [260] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [260];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [261] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [261];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [262] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [262];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [263] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [263];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [264] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [264];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [265] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [265];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [266] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [266];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [267] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [267];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [268] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [268];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [269] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [269];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [270] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [270];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [271] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [271];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [272] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [272];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [273] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [273];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [274] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [274];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [275] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [275];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [276] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [276];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [277] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [277];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [278] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [278];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [279] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [279];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [280] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [280];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [281] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [281];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [282] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [282];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [283] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [283];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [284] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [284];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [285] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [285];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [286] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [286];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [287] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [287];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [288] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [288];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [289] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [289];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [290] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [290];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [291] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [291];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [292] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [292];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [293] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [293];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [294] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [294];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [295] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [295];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [296] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [296];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [297] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [297];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [298] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [298];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [299] = \pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus [299];
+
+assign \pma_direct|auto_generated|wire_receive_pma0_analogtestbus [2] = \pma_direct|auto_generated|receive_pma0_ANALOGTESTBUS_bus [2];
+assign \pma_direct|auto_generated|wire_receive_pma0_analogtestbus [3] = \pma_direct|auto_generated|receive_pma0_ANALOGTESTBUS_bus [3];
+assign \pma_direct|auto_generated|wire_receive_pma0_analogtestbus [4] = \pma_direct|auto_generated|receive_pma0_ANALOGTESTBUS_bus [4];
+assign \pma_direct|auto_generated|wire_receive_pma0_analogtestbus [5] = \pma_direct|auto_generated|receive_pma0_ANALOGTESTBUS_bus [5];
+
+assign \pma_direct|auto_generated|wire_receive_pma0_recoverdataout [0] = \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus [0];
+assign \pma_direct|auto_generated|wire_receive_pma0_recoverdataout [1] = \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus [1];
+assign \pma_direct|auto_generated|wire_receive_pma0_recoverdataout [2] = \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus [2];
+assign \pma_direct|auto_generated|wire_receive_pma0_recoverdataout [3] = \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus [3];
+assign \pma_direct|auto_generated|wire_receive_pma0_recoverdataout [4] = \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus [4];
+assign \pma_direct|auto_generated|wire_receive_pma0_recoverdataout [5] = \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus [5];
+assign \pma_direct|auto_generated|wire_receive_pma0_recoverdataout [6] = \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus [6];
+assign \pma_direct|auto_generated|wire_receive_pma0_recoverdataout [7] = \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus [7];
+assign \pma_direct|auto_generated|wire_receive_pma0_recoverdataout [8] = \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus [8];
+assign \pma_direct|auto_generated|wire_receive_pma0_recoverdataout [9] = \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus [9];
+assign \pma_direct|auto_generated|wire_receive_pma0_recoverdataout [10] = \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus [10];
+assign \pma_direct|auto_generated|wire_receive_pma0_recoverdataout [11] = \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus [11];
+assign \pma_direct|auto_generated|wire_receive_pma0_recoverdataout [12] = \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus [12];
+assign \pma_direct|auto_generated|wire_receive_pma0_recoverdataout [13] = \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus [13];
+assign \pma_direct|auto_generated|wire_receive_pma0_recoverdataout [14] = \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus [14];
+assign \pma_direct|auto_generated|wire_receive_pma0_recoverdataout [15] = \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus [15];
+assign \pma_direct|auto_generated|wire_receive_pma0_recoverdataout [16] = \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus [16];
+assign \pma_direct|auto_generated|wire_receive_pma0_recoverdataout [17] = \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus [17];
+assign \pma_direct|auto_generated|wire_receive_pma0_recoverdataout [18] = \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus [18];
+assign \pma_direct|auto_generated|wire_receive_pma0_recoverdataout [19] = \pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus [19];
+
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [300] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [0];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [301] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [1];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [302] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [2];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [303] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [3];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [304] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [4];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [305] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [5];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [306] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [6];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [307] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [7];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [308] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [8];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [309] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [9];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [310] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [10];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [311] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [11];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [312] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [12];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [313] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [13];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [314] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [14];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [315] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [15];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [316] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [16];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [317] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [17];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [318] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [18];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [319] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [19];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [320] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [20];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [321] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [21];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [322] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [22];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [323] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [23];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [324] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [24];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [325] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [25];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [326] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [26];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [327] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [27];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [328] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [28];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [329] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [29];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [330] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [30];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [331] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [31];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [332] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [32];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [333] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [33];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [334] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [34];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [335] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [35];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [336] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [36];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [337] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [37];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [338] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [38];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [339] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [39];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [340] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [40];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [341] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [41];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [342] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [42];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [343] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [43];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [344] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [44];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [345] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [45];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [346] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [46];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [347] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [47];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [348] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [48];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [349] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [49];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [350] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [50];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [351] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [51];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [352] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [52];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [353] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [53];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [354] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [54];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [355] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [55];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [356] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [56];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [357] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [57];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [358] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [58];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [359] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [59];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [360] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [60];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [361] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [61];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [362] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [62];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [363] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [63];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [364] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [64];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [365] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [65];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [366] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [66];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [367] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [67];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [368] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [68];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [369] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [69];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [370] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [70];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [371] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [71];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [372] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [72];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [373] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [73];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [374] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [74];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [375] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [75];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [376] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [76];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [377] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [77];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [378] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [78];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [379] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [79];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [380] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [80];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [381] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [81];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [382] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [82];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [383] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [83];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [384] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [84];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [385] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [85];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [386] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [86];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [387] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [87];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [388] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [88];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [389] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [89];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [390] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [90];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [391] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [91];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [392] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [92];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [393] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [93];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [394] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [94];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [395] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [95];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [396] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [96];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [397] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [97];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [398] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [98];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [399] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [99];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [400] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [100];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [401] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [101];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [402] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [102];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [403] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [103];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [404] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [104];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [405] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [105];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [406] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [106];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [407] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [107];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [408] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [108];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [409] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [109];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [410] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [110];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [411] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [111];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [412] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [112];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [413] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [113];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [414] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [114];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [415] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [115];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [416] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [116];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [417] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [117];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [418] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [118];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [419] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [119];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [420] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [120];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [421] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [121];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [422] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [122];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [423] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [123];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [424] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [124];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [425] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [125];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [426] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [126];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [427] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [127];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [428] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [128];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [429] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [129];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [430] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [130];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [431] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [131];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [432] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [132];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [433] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [133];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [434] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [134];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [435] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [135];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [436] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [136];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [437] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [137];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [438] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [138];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [439] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [139];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [440] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [140];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [441] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [141];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [442] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [142];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [443] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [143];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [444] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [144];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [445] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [145];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [446] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [146];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [447] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [147];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [448] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [148];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [449] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [149];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [450] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [150];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [451] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [151];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [452] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [152];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [453] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [153];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [454] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [154];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [455] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [155];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [456] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [156];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [457] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [157];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [458] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [158];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [459] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [159];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [460] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [160];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [461] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [161];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [462] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [162];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [463] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [163];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [464] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [164];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [465] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [165];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [466] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [166];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [467] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [167];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [468] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [168];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [469] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [169];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [470] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [170];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [471] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [171];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [472] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [172];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [473] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [173];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [474] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [174];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [475] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [175];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [476] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [176];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [477] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [177];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [478] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [178];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [479] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [179];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [480] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [180];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [481] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [181];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [482] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [182];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [483] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [183];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [484] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [184];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [485] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [185];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [486] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [186];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [487] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [187];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [488] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [188];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [489] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [189];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [490] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [190];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [491] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [191];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [492] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [192];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [493] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [193];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [494] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [194];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [495] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [195];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [496] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [196];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [497] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [197];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [498] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [198];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [499] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [199];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [500] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [200];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [501] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [201];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [502] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [202];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [503] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [203];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [504] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [204];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [505] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [205];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [506] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [206];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [507] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [207];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [508] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [208];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [509] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [209];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [510] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [210];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [511] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [211];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [512] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [212];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [513] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [213];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [514] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [214];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [515] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [215];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [516] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [216];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [517] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [217];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [518] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [218];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [519] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [219];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [520] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [220];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [521] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [221];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [522] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [222];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [523] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [223];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [524] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [224];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [525] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [225];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [526] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [226];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [527] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [227];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [528] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [228];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [529] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [229];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [530] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [230];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [531] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [231];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [532] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [232];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [533] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [233];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [534] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [234];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [535] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [235];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [536] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [236];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [537] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [237];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [538] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [238];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [539] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [239];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [540] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [240];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [541] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [241];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [542] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [242];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [543] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [243];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [544] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [244];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [545] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [245];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [546] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [246];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [547] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [247];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [548] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [248];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [549] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [249];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [550] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [250];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [551] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [251];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [552] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [252];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [553] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [253];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [554] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [254];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [555] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [255];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [556] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [256];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [557] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [257];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [558] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [258];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [559] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [259];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [560] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [260];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [561] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [261];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [562] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [262];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [563] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [263];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [564] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [264];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [565] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [265];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [566] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [266];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [567] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [267];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [568] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [268];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [569] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [269];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [570] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [270];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [571] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [271];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [572] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [272];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [573] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [273];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [574] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [274];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [575] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [275];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [576] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [276];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [577] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [277];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [578] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [278];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [579] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [279];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [580] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [280];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [581] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [281];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [582] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [282];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [583] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [283];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [584] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [284];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [585] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [285];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [586] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [286];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [587] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [287];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [588] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [288];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [589] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [289];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [590] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [290];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [591] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [291];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [592] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [292];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [593] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [293];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [594] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [294];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [595] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [295];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [596] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [296];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [597] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [297];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [598] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [298];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [599] = \pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus [299];
+
+assign \pma_direct|auto_generated|wire_receive_pma1_analogtestbus [2] = \pma_direct|auto_generated|receive_pma1_ANALOGTESTBUS_bus [2];
+assign \pma_direct|auto_generated|wire_receive_pma1_analogtestbus [3] = \pma_direct|auto_generated|receive_pma1_ANALOGTESTBUS_bus [3];
+assign \pma_direct|auto_generated|wire_receive_pma1_analogtestbus [4] = \pma_direct|auto_generated|receive_pma1_ANALOGTESTBUS_bus [4];
+assign \pma_direct|auto_generated|wire_receive_pma1_analogtestbus [5] = \pma_direct|auto_generated|receive_pma1_ANALOGTESTBUS_bus [5];
+
+assign \pma_direct|auto_generated|wire_receive_pma1_recoverdataout [0] = \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus [0];
+assign \pma_direct|auto_generated|wire_receive_pma1_recoverdataout [1] = \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus [1];
+assign \pma_direct|auto_generated|wire_receive_pma1_recoverdataout [2] = \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus [2];
+assign \pma_direct|auto_generated|wire_receive_pma1_recoverdataout [3] = \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus [3];
+assign \pma_direct|auto_generated|wire_receive_pma1_recoverdataout [4] = \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus [4];
+assign \pma_direct|auto_generated|wire_receive_pma1_recoverdataout [5] = \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus [5];
+assign \pma_direct|auto_generated|wire_receive_pma1_recoverdataout [6] = \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus [6];
+assign \pma_direct|auto_generated|wire_receive_pma1_recoverdataout [7] = \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus [7];
+assign \pma_direct|auto_generated|wire_receive_pma1_recoverdataout [8] = \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus [8];
+assign \pma_direct|auto_generated|wire_receive_pma1_recoverdataout [9] = \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus [9];
+assign \pma_direct|auto_generated|wire_receive_pma1_recoverdataout [10] = \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus [10];
+assign \pma_direct|auto_generated|wire_receive_pma1_recoverdataout [11] = \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus [11];
+assign \pma_direct|auto_generated|wire_receive_pma1_recoverdataout [12] = \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus [12];
+assign \pma_direct|auto_generated|wire_receive_pma1_recoverdataout [13] = \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus [13];
+assign \pma_direct|auto_generated|wire_receive_pma1_recoverdataout [14] = \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus [14];
+assign \pma_direct|auto_generated|wire_receive_pma1_recoverdataout [15] = \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus [15];
+assign \pma_direct|auto_generated|wire_receive_pma1_recoverdataout [16] = \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus [16];
+assign \pma_direct|auto_generated|wire_receive_pma1_recoverdataout [17] = \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus [17];
+assign \pma_direct|auto_generated|wire_receive_pma1_recoverdataout [18] = \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus [18];
+assign \pma_direct|auto_generated|wire_receive_pma1_recoverdataout [19] = \pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus [19];
+
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [600] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [0];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [601] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [1];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [602] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [2];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [603] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [3];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [604] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [4];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [605] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [5];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [606] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [6];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [607] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [7];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [608] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [8];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [609] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [9];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [610] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [10];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [611] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [11];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [612] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [12];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [613] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [13];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [614] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [14];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [615] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [15];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [616] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [16];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [617] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [17];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [618] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [18];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [619] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [19];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [620] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [20];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [621] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [21];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [622] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [22];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [623] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [23];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [624] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [24];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [625] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [25];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [626] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [26];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [627] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [27];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [628] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [28];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [629] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [29];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [630] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [30];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [631] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [31];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [632] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [32];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [633] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [33];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [634] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [34];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [635] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [35];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [636] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [36];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [637] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [37];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [638] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [38];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [639] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [39];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [640] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [40];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [641] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [41];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [642] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [42];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [643] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [43];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [644] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [44];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [645] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [45];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [646] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [46];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [647] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [47];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [648] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [48];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [649] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [49];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [650] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [50];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [651] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [51];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [652] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [52];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [653] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [53];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [654] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [54];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [655] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [55];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [656] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [56];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [657] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [57];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [658] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [58];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [659] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [59];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [660] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [60];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [661] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [61];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [662] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [62];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [663] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [63];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [664] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [64];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [665] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [65];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [666] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [66];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [667] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [67];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [668] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [68];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [669] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [69];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [670] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [70];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [671] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [71];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [672] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [72];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [673] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [73];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [674] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [74];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [675] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [75];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [676] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [76];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [677] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [77];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [678] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [78];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [679] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [79];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [680] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [80];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [681] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [81];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [682] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [82];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [683] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [83];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [684] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [84];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [685] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [85];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [686] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [86];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [687] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [87];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [688] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [88];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [689] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [89];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [690] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [90];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [691] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [91];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [692] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [92];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [693] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [93];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [694] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [94];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [695] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [95];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [696] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [96];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [697] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [97];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [698] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [98];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [699] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [99];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [700] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [100];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [701] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [101];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [702] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [102];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [703] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [103];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [704] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [104];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [705] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [105];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [706] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [106];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [707] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [107];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [708] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [108];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [709] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [109];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [710] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [110];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [711] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [111];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [712] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [112];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [713] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [113];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [714] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [114];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [715] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [115];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [716] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [116];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [717] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [117];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [718] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [118];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [719] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [119];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [720] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [120];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [721] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [121];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [722] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [122];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [723] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [123];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [724] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [124];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [725] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [125];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [726] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [126];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [727] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [127];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [728] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [128];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [729] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [129];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [730] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [130];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [731] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [131];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [732] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [132];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [733] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [133];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [734] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [134];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [735] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [135];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [736] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [136];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [737] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [137];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [738] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [138];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [739] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [139];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [740] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [140];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [741] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [141];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [742] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [142];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [743] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [143];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [744] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [144];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [745] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [145];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [746] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [146];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [747] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [147];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [748] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [148];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [749] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [149];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [750] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [150];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [751] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [151];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [752] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [152];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [753] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [153];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [754] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [154];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [755] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [155];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [756] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [156];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [757] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [157];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [758] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [158];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [759] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [159];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [760] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [160];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [761] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [161];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [762] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [162];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [763] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [163];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [764] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [164];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [765] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [165];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [766] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [166];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [767] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [167];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [768] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [168];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [769] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [169];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [770] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [170];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [771] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [171];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [772] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [172];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [773] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [173];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [774] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [174];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [775] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [175];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [776] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [176];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [777] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [177];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [778] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [178];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [779] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [179];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [780] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [180];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [781] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [181];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [782] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [182];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [783] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [183];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [784] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [184];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [785] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [185];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [786] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [186];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [787] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [187];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [788] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [188];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [789] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [189];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [790] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [190];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [791] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [191];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [792] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [192];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [793] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [193];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [794] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [194];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [795] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [195];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [796] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [196];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [797] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [197];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [798] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [198];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [799] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [199];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [800] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [200];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [801] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [201];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [802] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [202];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [803] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [203];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [804] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [204];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [805] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [205];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [806] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [206];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [807] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [207];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [808] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [208];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [809] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [209];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [810] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [210];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [811] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [211];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [812] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [212];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [813] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [213];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [814] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [214];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [815] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [215];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [816] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [216];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [817] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [217];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [818] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [218];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [819] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [219];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [820] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [220];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [821] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [221];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [822] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [222];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [823] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [223];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [824] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [224];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [825] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [225];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [826] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [226];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [827] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [227];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [828] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [228];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [829] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [229];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [830] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [230];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [831] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [231];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [832] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [232];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [833] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [233];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [834] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [234];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [835] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [235];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [836] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [236];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [837] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [237];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [838] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [238];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [839] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [239];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [840] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [240];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [841] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [241];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [842] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [242];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [843] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [243];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [844] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [244];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [845] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [245];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [846] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [246];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [847] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [247];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [848] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [248];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [849] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [249];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [850] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [250];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [851] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [251];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [852] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [252];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [853] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [253];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [854] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [254];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [855] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [255];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [856] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [256];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [857] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [257];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [858] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [258];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [859] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [259];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [860] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [260];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [861] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [261];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [862] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [262];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [863] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [263];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [864] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [264];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [865] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [265];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [866] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [266];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [867] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [267];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [868] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [268];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [869] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [269];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [870] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [270];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [871] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [271];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [872] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [272];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [873] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [273];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [874] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [274];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [875] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [275];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [876] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [276];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [877] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [277];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [878] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [278];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [879] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [279];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [880] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [280];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [881] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [281];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [882] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [282];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [883] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [283];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [884] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [284];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [885] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [285];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [886] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [286];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [887] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [287];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [888] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [288];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [889] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [289];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [890] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [290];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [891] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [291];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [892] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [292];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [893] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [293];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [894] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [294];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [895] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [295];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [896] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [296];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [897] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [297];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [898] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [298];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [899] = \pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus [299];
+
+assign \pma_direct|auto_generated|wire_receive_pma2_analogtestbus [2] = \pma_direct|auto_generated|receive_pma2_ANALOGTESTBUS_bus [2];
+assign \pma_direct|auto_generated|wire_receive_pma2_analogtestbus [3] = \pma_direct|auto_generated|receive_pma2_ANALOGTESTBUS_bus [3];
+assign \pma_direct|auto_generated|wire_receive_pma2_analogtestbus [4] = \pma_direct|auto_generated|receive_pma2_ANALOGTESTBUS_bus [4];
+assign \pma_direct|auto_generated|wire_receive_pma2_analogtestbus [5] = \pma_direct|auto_generated|receive_pma2_ANALOGTESTBUS_bus [5];
+
+assign \pma_direct|auto_generated|wire_receive_pma2_recoverdataout [0] = \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus [0];
+assign \pma_direct|auto_generated|wire_receive_pma2_recoverdataout [1] = \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus [1];
+assign \pma_direct|auto_generated|wire_receive_pma2_recoverdataout [2] = \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus [2];
+assign \pma_direct|auto_generated|wire_receive_pma2_recoverdataout [3] = \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus [3];
+assign \pma_direct|auto_generated|wire_receive_pma2_recoverdataout [4] = \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus [4];
+assign \pma_direct|auto_generated|wire_receive_pma2_recoverdataout [5] = \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus [5];
+assign \pma_direct|auto_generated|wire_receive_pma2_recoverdataout [6] = \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus [6];
+assign \pma_direct|auto_generated|wire_receive_pma2_recoverdataout [7] = \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus [7];
+assign \pma_direct|auto_generated|wire_receive_pma2_recoverdataout [8] = \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus [8];
+assign \pma_direct|auto_generated|wire_receive_pma2_recoverdataout [9] = \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus [9];
+assign \pma_direct|auto_generated|wire_receive_pma2_recoverdataout [10] = \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus [10];
+assign \pma_direct|auto_generated|wire_receive_pma2_recoverdataout [11] = \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus [11];
+assign \pma_direct|auto_generated|wire_receive_pma2_recoverdataout [12] = \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus [12];
+assign \pma_direct|auto_generated|wire_receive_pma2_recoverdataout [13] = \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus [13];
+assign \pma_direct|auto_generated|wire_receive_pma2_recoverdataout [14] = \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus [14];
+assign \pma_direct|auto_generated|wire_receive_pma2_recoverdataout [15] = \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus [15];
+assign \pma_direct|auto_generated|wire_receive_pma2_recoverdataout [16] = \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus [16];
+assign \pma_direct|auto_generated|wire_receive_pma2_recoverdataout [17] = \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus [17];
+assign \pma_direct|auto_generated|wire_receive_pma2_recoverdataout [18] = \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus [18];
+assign \pma_direct|auto_generated|wire_receive_pma2_recoverdataout [19] = \pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus [19];
+
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [900] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [0];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [901] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [1];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [902] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [2];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [903] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [3];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [904] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [4];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [905] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [5];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [906] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [6];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [907] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [7];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [908] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [8];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [909] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [9];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [910] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [10];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [911] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [11];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [912] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [12];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [913] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [13];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [914] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [14];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [915] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [15];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [916] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [16];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [917] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [17];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [918] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [18];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [919] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [19];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [920] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [20];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [921] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [21];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [922] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [22];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [923] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [23];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [924] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [24];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [925] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [25];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [926] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [26];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [927] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [27];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [928] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [28];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [929] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [29];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [930] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [30];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [931] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [31];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [932] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [32];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [933] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [33];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [934] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [34];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [935] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [35];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [936] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [36];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [937] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [37];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [938] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [38];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [939] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [39];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [940] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [40];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [941] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [41];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [942] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [42];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [943] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [43];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [944] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [44];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [945] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [45];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [946] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [46];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [947] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [47];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [948] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [48];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [949] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [49];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [950] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [50];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [951] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [51];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [952] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [52];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [953] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [53];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [954] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [54];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [955] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [55];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [956] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [56];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [957] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [57];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [958] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [58];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [959] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [59];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [960] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [60];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [961] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [61];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [962] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [62];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [963] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [63];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [964] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [64];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [965] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [65];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [966] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [66];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [967] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [67];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [968] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [68];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [969] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [69];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [970] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [70];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [971] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [71];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [972] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [72];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [973] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [73];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [974] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [74];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [975] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [75];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [976] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [76];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [977] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [77];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [978] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [78];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [979] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [79];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [980] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [80];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [981] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [81];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [982] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [82];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [983] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [83];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [984] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [84];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [985] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [85];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [986] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [86];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [987] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [87];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [988] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [88];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [989] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [89];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [990] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [90];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [991] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [91];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [992] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [92];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [993] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [93];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [994] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [94];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [995] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [95];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [996] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [96];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [997] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [97];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [998] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [98];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [999] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [99];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1000] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [100];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1001] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [101];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1002] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [102];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1003] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [103];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1004] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [104];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1005] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [105];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1006] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [106];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1007] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [107];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1008] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [108];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1009] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [109];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1010] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [110];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1011] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [111];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1012] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [112];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1013] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [113];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1014] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [114];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1015] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [115];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1016] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [116];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1017] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [117];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1018] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [118];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1019] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [119];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1020] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [120];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1021] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [121];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1022] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [122];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1023] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [123];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1024] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [124];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1025] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [125];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1026] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [126];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1027] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [127];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1028] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [128];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1029] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [129];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1030] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [130];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1031] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [131];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1032] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [132];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1033] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [133];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1034] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [134];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1035] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [135];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1036] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [136];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1037] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [137];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1038] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [138];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1039] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [139];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1040] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [140];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1041] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [141];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1042] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [142];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1043] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [143];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1044] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [144];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1045] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [145];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1046] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [146];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1047] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [147];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1048] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [148];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1049] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [149];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1050] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [150];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1051] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [151];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1052] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [152];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1053] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [153];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1054] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [154];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1055] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [155];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1056] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [156];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1057] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [157];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1058] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [158];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1059] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [159];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1060] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [160];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1061] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [161];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1062] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [162];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1063] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [163];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1064] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [164];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1065] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [165];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1066] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [166];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1067] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [167];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1068] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [168];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1069] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [169];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1070] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [170];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1071] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [171];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1072] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [172];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1073] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [173];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1074] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [174];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1075] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [175];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1076] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [176];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1077] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [177];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1078] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [178];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1079] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [179];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1080] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [180];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1081] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [181];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1082] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [182];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1083] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [183];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1084] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [184];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1085] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [185];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1086] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [186];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1087] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [187];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1088] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [188];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1089] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [189];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1090] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [190];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1091] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [191];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1092] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [192];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1093] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [193];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1094] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [194];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1095] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [195];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1096] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [196];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1097] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [197];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1098] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [198];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1099] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [199];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1100] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [200];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1101] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [201];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1102] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [202];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1103] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [203];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1104] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [204];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1105] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [205];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1106] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [206];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1107] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [207];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1108] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [208];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1109] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [209];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1110] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [210];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1111] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [211];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1112] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [212];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1113] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [213];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1114] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [214];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1115] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [215];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1116] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [216];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1117] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [217];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1118] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [218];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1119] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [219];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1120] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [220];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1121] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [221];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1122] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [222];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1123] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [223];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1124] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [224];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1125] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [225];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1126] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [226];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1127] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [227];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1128] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [228];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1129] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [229];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1130] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [230];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1131] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [231];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1132] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [232];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1133] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [233];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1134] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [234];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1135] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [235];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1136] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [236];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1137] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [237];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1138] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [238];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1139] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [239];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1140] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [240];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1141] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [241];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1142] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [242];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1143] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [243];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1144] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [244];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1145] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [245];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1146] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [246];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1147] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [247];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1148] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [248];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1149] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [249];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1150] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [250];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1151] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [251];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1152] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [252];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1153] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [253];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1154] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [254];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1155] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [255];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1156] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [256];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1157] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [257];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1158] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [258];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1159] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [259];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1160] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [260];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1161] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [261];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1162] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [262];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1163] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [263];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1164] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [264];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1165] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [265];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1166] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [266];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1167] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [267];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1168] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [268];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1169] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [269];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1170] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [270];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1171] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [271];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1172] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [272];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1173] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [273];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1174] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [274];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1175] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [275];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1176] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [276];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1177] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [277];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1178] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [278];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1179] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [279];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1180] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [280];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1181] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [281];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1182] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [282];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1183] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [283];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1184] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [284];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1185] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [285];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1186] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [286];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1187] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [287];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1188] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [288];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1189] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [289];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1190] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [290];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1191] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [291];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1192] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [292];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1193] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [293];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1194] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [294];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1195] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [295];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1196] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [296];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1197] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [297];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1198] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [298];
+assign \pma_direct|auto_generated|cent_unit_rxpmadprioin [1199] = \pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus [299];
+
+assign \pma_direct|auto_generated|wire_receive_pma3_analogtestbus [2] = \pma_direct|auto_generated|receive_pma3_ANALOGTESTBUS_bus [2];
+assign \pma_direct|auto_generated|wire_receive_pma3_analogtestbus [3] = \pma_direct|auto_generated|receive_pma3_ANALOGTESTBUS_bus [3];
+assign \pma_direct|auto_generated|wire_receive_pma3_analogtestbus [4] = \pma_direct|auto_generated|receive_pma3_ANALOGTESTBUS_bus [4];
+assign \pma_direct|auto_generated|wire_receive_pma3_analogtestbus [5] = \pma_direct|auto_generated|receive_pma3_ANALOGTESTBUS_bus [5];
+
+assign \pma_direct|auto_generated|wire_receive_pma3_recoverdataout [0] = \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus [0];
+assign \pma_direct|auto_generated|wire_receive_pma3_recoverdataout [1] = \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus [1];
+assign \pma_direct|auto_generated|wire_receive_pma3_recoverdataout [2] = \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus [2];
+assign \pma_direct|auto_generated|wire_receive_pma3_recoverdataout [3] = \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus [3];
+assign \pma_direct|auto_generated|wire_receive_pma3_recoverdataout [4] = \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus [4];
+assign \pma_direct|auto_generated|wire_receive_pma3_recoverdataout [5] = \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus [5];
+assign \pma_direct|auto_generated|wire_receive_pma3_recoverdataout [6] = \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus [6];
+assign \pma_direct|auto_generated|wire_receive_pma3_recoverdataout [7] = \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus [7];
+assign \pma_direct|auto_generated|wire_receive_pma3_recoverdataout [8] = \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus [8];
+assign \pma_direct|auto_generated|wire_receive_pma3_recoverdataout [9] = \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus [9];
+assign \pma_direct|auto_generated|wire_receive_pma3_recoverdataout [10] = \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus [10];
+assign \pma_direct|auto_generated|wire_receive_pma3_recoverdataout [11] = \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus [11];
+assign \pma_direct|auto_generated|wire_receive_pma3_recoverdataout [12] = \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus [12];
+assign \pma_direct|auto_generated|wire_receive_pma3_recoverdataout [13] = \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus [13];
+assign \pma_direct|auto_generated|wire_receive_pma3_recoverdataout [14] = \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus [14];
+assign \pma_direct|auto_generated|wire_receive_pma3_recoverdataout [15] = \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus [15];
+assign \pma_direct|auto_generated|wire_receive_pma3_recoverdataout [16] = \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus [16];
+assign \pma_direct|auto_generated|wire_receive_pma3_recoverdataout [17] = \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus [17];
+assign \pma_direct|auto_generated|wire_receive_pma3_recoverdataout [18] = \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus [18];
+assign \pma_direct|auto_generated|wire_receive_pma3_recoverdataout [19] = \pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus [19];
+
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [0] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [0];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [1];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [2] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [2];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [3] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [3];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [4] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [4];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [5] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [5];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [6] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [6];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [7] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [7];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [8] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [8];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [9] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [9];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [10] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [10];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [11] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [11];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [12] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [12];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [13] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [13];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [14] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [14];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [15] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [15];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [16] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [16];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [17] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [17];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [18] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [18];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [19] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [19];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [20] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [20];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [21] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [21];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [22] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [22];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [23] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [23];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [24] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [24];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [25] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [25];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [26] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [26];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [27] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [27];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [28] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [28];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [29] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [29];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [30] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [30];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [31] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [31];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [32] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [32];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [33] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [33];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [34] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [34];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [35] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [35];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [36] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [36];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [37] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [37];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [38] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [38];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [39] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [39];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [40] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [40];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [41] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [41];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [42] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [42];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [43] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [43];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [44] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [44];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [45] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [45];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [46] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [46];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [47] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [47];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [48] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [48];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [49] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [49];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [50] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [50];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [51] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [51];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [52] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [52];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [53] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [53];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [54] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [54];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [55] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [55];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [56] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [56];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [57] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [57];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [58] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [58];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [59] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [59];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [60] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [60];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [61] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [61];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [62] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [62];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [63] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [63];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [64] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [64];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [65] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [65];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [66] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [66];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [67] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [67];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [68] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [68];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [69] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [69];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [70] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [70];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [71] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [71];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [72] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [72];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [73] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [73];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [74] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [74];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [75] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [75];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [76] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [76];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [77] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [77];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [78] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [78];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [79] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [79];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [80] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [80];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [81] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [81];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [82] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [82];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [83] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [83];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [84] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [84];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [85] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [85];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [86] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [86];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [87] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [87];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [88] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [88];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [89] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [89];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [90] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [90];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [91] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [91];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [92] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [92];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [93] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [93];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [94] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [94];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [95] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [95];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [96] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [96];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [97] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [97];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [98] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [98];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [99] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [99];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [100] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [100];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [101] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [101];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [102] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [102];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [103] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [103];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [104] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [104];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [105] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [105];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [106] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [106];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [107] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [107];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [108] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [108];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [109] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [109];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [110] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [110];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [111] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [111];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [112] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [112];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [113] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [113];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [114] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [114];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [115] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [115];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [116] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [116];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [117] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [117];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [118] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [118];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [119] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [119];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [120] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [120];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [121] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [121];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [122] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [122];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [123] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [123];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [124] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [124];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [125] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [125];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [126] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [126];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [127] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [127];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [128] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [128];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [129] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [129];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [130] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [130];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [131] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [131];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [132] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [132];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [133] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [133];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [134] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [134];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [135] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [135];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [136] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [136];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [137] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [137];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [138] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [138];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [139] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [139];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [140] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [140];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [141] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [141];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [142] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [142];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [143] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [143];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [144] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [144];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [145] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [145];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [146] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [146];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [147] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [147];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [148] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [148];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [149] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [149];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [150] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [150];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [151] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [151];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [152] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [152];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [153] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [153];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [154] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [154];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [155] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [155];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [156] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [156];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [157] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [157];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [158] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [158];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [159] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [159];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [160] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [160];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [161] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [161];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [162] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [162];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [163] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [163];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [164] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [164];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [165] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [165];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [166] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [166];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [167] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [167];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [168] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [168];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [169] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [169];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [170] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [170];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [171] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [171];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [172] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [172];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [173] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [173];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [174] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [174];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [175] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [175];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [176] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [176];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [177] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [177];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [178] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [178];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [179] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [179];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [180] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [180];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [181] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [181];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [182] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [182];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [183] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [183];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [184] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [184];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [185] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [185];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [186] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [186];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [187] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [187];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [188] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [188];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [189] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [189];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [190] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [190];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [191] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [191];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [192] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [192];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [193] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [193];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [194] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [194];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [195] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [195];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [196] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [196];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [197] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [197];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [198] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [198];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [199] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [199];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [200] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [200];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [201] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [201];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [202] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [202];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [203] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [203];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [204] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [204];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [205] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [205];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [206] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [206];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [207] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [207];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [208] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [208];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [209] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [209];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [210] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [210];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [211] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [211];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [212] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [212];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [213] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [213];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [214] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [214];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [215] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [215];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [216] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [216];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [217] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [217];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [218] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [218];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [219] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [219];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [220] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [220];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [221] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [221];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [222] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [222];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [223] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [223];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [224] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [224];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [225] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [225];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [226] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [226];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [227] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [227];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [228] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [228];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [229] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [229];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [230] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [230];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [231] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [231];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [232] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [232];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [233] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [233];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [234] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [234];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [235] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [235];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [236] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [236];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [237] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [237];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [238] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [238];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [239] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [239];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [240] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [240];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [241] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [241];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [242] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [242];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [243] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [243];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [244] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [244];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [245] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [245];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [246] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [246];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [247] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [247];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [248] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [248];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [249] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [249];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [250] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [250];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [251] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [251];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [252] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [252];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [253] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [253];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [254] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [254];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [255] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [255];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [256] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [256];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [257] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [257];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [258] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [258];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [259] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [259];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [260] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [260];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [261] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [261];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [262] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [262];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [263] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [263];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [264] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [264];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [265] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [265];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [266] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [266];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [267] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [267];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [268] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [268];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [269] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [269];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [270] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [270];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [271] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [271];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [272] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [272];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [273] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [273];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [274] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [274];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [275] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [275];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [276] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [276];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [277] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [277];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [278] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [278];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [279] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [279];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [280] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [280];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [281] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [281];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [282] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [282];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [283] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [283];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [284] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [284];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [285] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [285];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [286] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [286];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [287] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [287];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [288] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [288];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [289] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [289];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [290] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [290];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [291] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [291];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [292] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [292];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [293] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [293];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [294] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [294];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [295] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [295];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [296] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [296];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [297] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [297];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [298] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [298];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [299] = \pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus [299];
+
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [300] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [0];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [301] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [1];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [302] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [2];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [303] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [3];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [304] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [4];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [305] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [5];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [306] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [6];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [307] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [7];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [308] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [8];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [309] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [9];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [310] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [10];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [311] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [11];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [312] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [12];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [313] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [13];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [314] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [14];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [315] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [15];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [316] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [16];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [317] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [17];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [318] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [18];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [319] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [19];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [320] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [20];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [321] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [21];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [322] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [22];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [323] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [23];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [324] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [24];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [325] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [25];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [326] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [26];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [327] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [27];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [328] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [28];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [329] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [29];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [330] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [30];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [331] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [31];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [332] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [32];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [333] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [33];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [334] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [34];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [335] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [35];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [336] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [36];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [337] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [37];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [338] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [38];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [339] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [39];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [340] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [40];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [341] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [41];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [342] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [42];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [343] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [43];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [344] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [44];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [345] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [45];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [346] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [46];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [347] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [47];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [348] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [48];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [349] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [49];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [350] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [50];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [351] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [51];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [352] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [52];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [353] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [53];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [354] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [54];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [355] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [55];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [356] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [56];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [357] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [57];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [358] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [58];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [359] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [59];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [360] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [60];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [361] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [61];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [362] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [62];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [363] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [63];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [364] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [64];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [365] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [65];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [366] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [66];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [367] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [67];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [368] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [68];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [369] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [69];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [370] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [70];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [371] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [71];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [372] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [72];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [373] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [73];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [374] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [74];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [375] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [75];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [376] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [76];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [377] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [77];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [378] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [78];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [379] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [79];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [380] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [80];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [381] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [81];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [382] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [82];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [383] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [83];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [384] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [84];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [385] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [85];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [386] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [86];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [387] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [87];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [388] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [88];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [389] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [89];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [390] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [90];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [391] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [91];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [392] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [92];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [393] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [93];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [394] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [94];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [395] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [95];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [396] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [96];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [397] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [97];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [398] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [98];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [399] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [99];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [400] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [100];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [401] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [101];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [402] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [102];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [403] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [103];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [404] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [104];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [405] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [105];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [406] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [106];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [407] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [107];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [408] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [108];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [409] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [109];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [410] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [110];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [411] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [111];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [412] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [112];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [413] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [113];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [414] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [114];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [415] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [115];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [416] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [116];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [417] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [117];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [418] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [118];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [419] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [119];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [420] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [120];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [421] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [121];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [422] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [122];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [423] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [123];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [424] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [124];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [425] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [125];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [426] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [126];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [427] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [127];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [428] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [128];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [429] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [129];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [430] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [130];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [431] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [131];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [432] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [132];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [433] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [133];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [434] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [134];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [435] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [135];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [436] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [136];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [437] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [137];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [438] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [138];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [439] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [139];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [440] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [140];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [441] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [141];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [442] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [142];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [443] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [143];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [444] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [144];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [445] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [145];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [446] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [146];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [447] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [147];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [448] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [148];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [449] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [149];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [450] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [150];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [451] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [151];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [452] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [152];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [453] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [153];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [454] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [154];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [455] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [155];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [456] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [156];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [457] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [157];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [458] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [158];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [459] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [159];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [460] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [160];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [461] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [161];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [462] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [162];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [463] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [163];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [464] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [164];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [465] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [165];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [466] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [166];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [467] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [167];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [468] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [168];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [469] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [169];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [470] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [170];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [471] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [171];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [472] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [172];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [473] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [173];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [474] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [174];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [475] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [175];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [476] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [176];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [477] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [177];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [478] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [178];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [479] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [179];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [480] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [180];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [481] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [181];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [482] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [182];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [483] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [183];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [484] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [184];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [485] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [185];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [486] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [186];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [487] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [187];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [488] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [188];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [489] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [189];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [490] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [190];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [491] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [191];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [492] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [192];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [493] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [193];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [494] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [194];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [495] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [195];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [496] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [196];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [497] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [197];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [498] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [198];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [499] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [199];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [500] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [200];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [501] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [201];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [502] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [202];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [503] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [203];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [504] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [204];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [505] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [205];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [506] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [206];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [507] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [207];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [508] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [208];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [509] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [209];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [510] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [210];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [511] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [211];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [512] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [212];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [513] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [213];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [514] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [214];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [515] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [215];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [516] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [216];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [517] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [217];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [518] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [218];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [519] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [219];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [520] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [220];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [521] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [221];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [522] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [222];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [523] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [223];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [524] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [224];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [525] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [225];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [526] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [226];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [527] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [227];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [528] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [228];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [529] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [229];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [530] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [230];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [531] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [231];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [532] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [232];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [533] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [233];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [534] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [234];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [535] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [235];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [536] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [236];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [537] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [237];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [538] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [238];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [539] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [239];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [540] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [240];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [541] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [241];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [542] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [242];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [543] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [243];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [544] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [244];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [545] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [245];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [546] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [246];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [547] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [247];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [548] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [248];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [549] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [249];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [550] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [250];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [551] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [251];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [552] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [252];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [553] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [253];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [554] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [254];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [555] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [255];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [556] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [256];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [557] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [257];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [558] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [258];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [559] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [259];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [560] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [260];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [561] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [261];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [562] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [262];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [563] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [263];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [564] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [264];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [565] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [265];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [566] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [266];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [567] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [267];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [568] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [268];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [569] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [269];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [570] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [270];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [571] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [271];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [572] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [272];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [573] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [273];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [574] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [274];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [575] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [275];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [576] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [276];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [577] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [277];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [578] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [278];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [579] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [279];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [580] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [280];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [581] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [281];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [582] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [282];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [583] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [283];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [584] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [284];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [585] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [285];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [586] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [286];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [587] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [287];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [588] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [288];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [589] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [289];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [590] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [290];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [591] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [291];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [592] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [292];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [593] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [293];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [594] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [294];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [595] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [295];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [596] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [296];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [597] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [297];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [598] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [298];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [599] = \pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus [299];
+
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [600] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [0];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [601] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [1];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [602] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [2];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [603] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [3];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [604] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [4];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [605] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [5];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [606] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [6];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [607] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [7];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [608] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [8];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [609] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [9];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [610] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [10];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [611] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [11];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [612] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [12];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [613] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [13];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [614] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [14];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [615] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [15];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [616] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [16];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [617] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [17];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [618] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [18];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [619] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [19];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [620] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [20];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [621] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [21];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [622] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [22];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [623] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [23];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [624] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [24];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [625] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [25];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [626] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [26];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [627] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [27];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [628] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [28];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [629] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [29];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [630] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [30];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [631] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [31];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [632] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [32];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [633] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [33];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [634] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [34];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [635] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [35];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [636] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [36];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [637] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [37];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [638] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [38];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [639] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [39];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [640] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [40];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [641] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [41];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [642] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [42];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [643] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [43];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [644] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [44];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [645] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [45];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [646] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [46];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [647] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [47];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [648] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [48];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [649] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [49];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [650] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [50];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [651] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [51];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [652] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [52];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [653] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [53];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [654] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [54];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [655] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [55];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [656] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [56];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [657] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [57];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [658] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [58];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [659] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [59];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [660] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [60];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [661] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [61];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [662] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [62];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [663] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [63];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [664] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [64];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [665] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [65];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [666] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [66];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [667] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [67];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [668] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [68];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [669] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [69];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [670] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [70];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [671] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [71];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [672] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [72];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [673] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [73];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [674] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [74];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [675] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [75];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [676] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [76];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [677] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [77];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [678] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [78];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [679] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [79];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [680] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [80];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [681] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [81];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [682] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [82];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [683] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [83];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [684] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [84];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [685] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [85];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [686] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [86];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [687] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [87];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [688] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [88];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [689] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [89];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [690] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [90];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [691] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [91];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [692] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [92];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [693] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [93];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [694] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [94];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [695] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [95];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [696] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [96];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [697] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [97];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [698] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [98];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [699] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [99];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [700] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [100];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [701] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [101];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [702] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [102];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [703] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [103];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [704] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [104];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [705] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [105];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [706] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [106];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [707] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [107];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [708] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [108];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [709] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [109];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [710] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [110];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [711] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [111];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [712] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [112];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [713] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [113];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [714] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [114];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [715] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [115];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [716] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [116];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [717] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [117];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [718] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [118];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [719] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [119];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [720] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [120];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [721] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [121];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [722] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [122];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [723] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [123];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [724] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [124];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [725] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [125];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [726] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [126];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [727] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [127];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [728] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [128];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [729] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [129];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [730] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [130];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [731] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [131];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [732] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [132];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [733] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [133];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [734] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [134];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [735] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [135];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [736] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [136];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [737] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [137];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [738] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [138];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [739] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [139];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [740] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [140];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [741] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [141];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [742] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [142];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [743] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [143];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [744] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [144];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [745] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [145];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [746] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [146];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [747] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [147];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [748] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [148];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [749] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [149];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [750] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [150];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [751] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [151];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [752] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [152];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [753] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [153];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [754] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [154];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [755] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [155];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [756] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [156];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [757] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [157];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [758] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [158];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [759] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [159];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [760] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [160];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [761] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [161];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [762] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [162];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [763] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [163];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [764] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [164];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [765] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [165];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [766] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [166];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [767] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [167];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [768] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [168];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [769] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [169];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [770] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [170];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [771] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [171];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [772] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [172];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [773] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [173];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [774] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [174];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [775] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [175];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [776] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [176];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [777] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [177];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [778] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [178];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [779] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [179];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [780] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [180];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [781] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [181];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [782] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [182];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [783] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [183];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [784] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [184];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [785] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [185];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [786] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [186];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [787] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [187];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [788] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [188];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [789] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [189];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [790] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [190];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [791] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [191];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [792] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [192];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [793] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [193];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [794] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [194];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [795] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [195];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [796] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [196];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [797] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [197];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [798] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [198];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [799] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [199];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [800] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [200];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [801] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [201];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [802] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [202];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [803] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [203];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [804] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [204];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [805] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [205];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [806] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [206];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [807] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [207];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [808] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [208];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [809] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [209];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [810] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [210];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [811] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [211];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [812] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [212];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [813] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [213];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [814] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [214];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [815] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [215];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [816] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [216];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [817] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [217];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [818] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [218];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [819] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [219];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [820] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [220];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [821] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [221];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [822] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [222];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [823] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [223];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [824] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [224];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [825] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [225];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [826] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [226];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [827] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [227];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [828] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [228];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [829] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [229];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [830] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [230];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [831] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [231];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [832] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [232];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [833] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [233];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [834] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [234];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [835] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [235];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [836] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [236];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [837] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [237];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [838] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [238];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [839] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [239];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [840] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [240];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [841] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [241];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [842] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [242];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [843] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [243];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [844] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [244];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [845] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [245];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [846] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [246];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [847] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [247];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [848] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [248];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [849] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [249];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [850] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [250];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [851] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [251];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [852] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [252];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [853] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [253];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [854] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [254];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [855] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [255];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [856] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [256];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [857] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [257];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [858] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [258];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [859] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [259];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [860] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [260];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [861] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [261];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [862] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [262];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [863] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [263];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [864] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [264];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [865] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [265];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [866] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [266];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [867] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [267];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [868] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [268];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [869] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [269];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [870] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [270];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [871] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [271];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [872] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [272];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [873] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [273];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [874] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [274];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [875] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [275];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [876] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [276];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [877] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [277];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [878] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [278];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [879] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [279];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [880] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [280];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [881] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [281];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [882] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [282];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [883] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [283];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [884] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [284];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [885] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [285];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [886] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [286];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [887] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [287];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [888] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [288];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [889] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [289];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [890] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [290];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [891] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [291];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [892] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [292];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [893] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [293];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [894] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [294];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [895] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [295];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [896] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [296];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [897] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [297];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [898] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [298];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [899] = \pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus [299];
+
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [900] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [0];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [901] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [1];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [902] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [2];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [903] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [3];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [904] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [4];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [905] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [5];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [906] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [6];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [907] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [7];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [908] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [8];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [909] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [9];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [910] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [10];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [911] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [11];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [912] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [12];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [913] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [13];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [914] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [14];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [915] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [15];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [916] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [16];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [917] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [17];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [918] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [18];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [919] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [19];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [920] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [20];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [921] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [21];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [922] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [22];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [923] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [23];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [924] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [24];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [925] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [25];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [926] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [26];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [927] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [27];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [928] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [28];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [929] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [29];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [930] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [30];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [931] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [31];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [932] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [32];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [933] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [33];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [934] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [34];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [935] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [35];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [936] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [36];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [937] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [37];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [938] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [38];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [939] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [39];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [940] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [40];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [941] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [41];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [942] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [42];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [943] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [43];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [944] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [44];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [945] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [45];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [946] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [46];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [947] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [47];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [948] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [48];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [949] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [49];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [950] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [50];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [951] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [51];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [952] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [52];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [953] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [53];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [954] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [54];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [955] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [55];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [956] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [56];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [957] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [57];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [958] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [58];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [959] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [59];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [960] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [60];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [961] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [61];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [962] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [62];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [963] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [63];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [964] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [64];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [965] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [65];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [966] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [66];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [967] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [67];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [968] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [68];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [969] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [69];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [970] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [70];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [971] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [71];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [972] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [72];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [973] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [73];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [974] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [74];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [975] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [75];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [976] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [76];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [977] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [77];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [978] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [78];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [979] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [79];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [980] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [80];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [981] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [81];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [982] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [82];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [983] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [83];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [984] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [84];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [985] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [85];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [986] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [86];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [987] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [87];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [988] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [88];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [989] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [89];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [990] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [90];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [991] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [91];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [992] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [92];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [993] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [93];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [994] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [94];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [995] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [95];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [996] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [96];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [997] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [97];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [998] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [98];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [999] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [99];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1000] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [100];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1001] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [101];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1002] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [102];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1003] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [103];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1004] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [104];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1005] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [105];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1006] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [106];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1007] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [107];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1008] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [108];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1009] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [109];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1010] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [110];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1011] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [111];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1012] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [112];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1013] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [113];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1014] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [114];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1015] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [115];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1016] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [116];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1017] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [117];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1018] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [118];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1019] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [119];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1020] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [120];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1021] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [121];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1022] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [122];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1023] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [123];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1024] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [124];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1025] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [125];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1026] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [126];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1027] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [127];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1028] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [128];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1029] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [129];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1030] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [130];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1031] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [131];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1032] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [132];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1033] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [133];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1034] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [134];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1035] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [135];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1036] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [136];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1037] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [137];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1038] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [138];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1039] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [139];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1040] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [140];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1041] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [141];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1042] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [142];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1043] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [143];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1044] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [144];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1045] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [145];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1046] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [146];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1047] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [147];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1048] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [148];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1049] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [149];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1050] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [150];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1051] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [151];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1052] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [152];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1053] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [153];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1054] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [154];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1055] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [155];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1056] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [156];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1057] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [157];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1058] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [158];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1059] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [159];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1060] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [160];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1061] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [161];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1062] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [162];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1063] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [163];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1064] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [164];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1065] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [165];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1066] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [166];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1067] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [167];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1068] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [168];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1069] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [169];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1070] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [170];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1071] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [171];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1072] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [172];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1073] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [173];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1074] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [174];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1075] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [175];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1076] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [176];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1077] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [177];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1078] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [178];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1079] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [179];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1080] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [180];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1081] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [181];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1082] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [182];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1083] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [183];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1084] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [184];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1085] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [185];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1086] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [186];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1087] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [187];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1088] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [188];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1089] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [189];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1090] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [190];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1091] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [191];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1092] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [192];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1093] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [193];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1094] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [194];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1095] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [195];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1096] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [196];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1097] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [197];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1098] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [198];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1099] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [199];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1100] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [200];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1101] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [201];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1102] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [202];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1103] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [203];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1104] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [204];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1105] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [205];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1106] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [206];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1107] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [207];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1108] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [208];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1109] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [209];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1110] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [210];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1111] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [211];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1112] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [212];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1113] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [213];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1114] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [214];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1115] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [215];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1116] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [216];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1117] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [217];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1118] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [218];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1119] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [219];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1120] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [220];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1121] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [221];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1122] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [222];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1123] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [223];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1124] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [224];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1125] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [225];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1126] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [226];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1127] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [227];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1128] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [228];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1129] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [229];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1130] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [230];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1131] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [231];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1132] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [232];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1133] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [233];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1134] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [234];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1135] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [235];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1136] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [236];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1137] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [237];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1138] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [238];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1139] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [239];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1140] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [240];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1141] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [241];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1142] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [242];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1143] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [243];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1144] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [244];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1145] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [245];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1146] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [246];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1147] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [247];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1148] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [248];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1149] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [249];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1150] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [250];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1151] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [251];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1152] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [252];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1153] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [253];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1154] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [254];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1155] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [255];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1156] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [256];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1157] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [257];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1158] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [258];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1159] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [259];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1160] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [260];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1161] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [261];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1162] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [262];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1163] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [263];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1164] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [264];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1165] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [265];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1166] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [266];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1167] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [267];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1168] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [268];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1169] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [269];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1170] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [270];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1171] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [271];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1172] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [272];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1173] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [273];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1174] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [274];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1175] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [275];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1176] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [276];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1177] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [277];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1178] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [278];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1179] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [279];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1180] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [280];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1181] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [281];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1182] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [282];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1183] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [283];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1184] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [284];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1185] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [285];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1186] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [286];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1187] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [287];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1188] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [288];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1189] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [289];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1190] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [290];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1191] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [291];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1192] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [292];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1193] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [293];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1194] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [294];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1195] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [295];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1196] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [296];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1197] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [297];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1198] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [298];
+assign \pma_direct|auto_generated|cent_unit_txpmadprioin [1199] = \pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus [299];
+
+assign \pma_direct|auto_generated|pll_ch_dataout_wire [0] = \pma_direct|auto_generated|rx_cdr_pll0_DATAOUT_bus [0];
+assign \pma_direct|auto_generated|pll_ch_dataout_wire [1] = \pma_direct|auto_generated|rx_cdr_pll0_DATAOUT_bus [1];
+
+assign \pma_direct|auto_generated|rx_deserclock_in [0] = \pma_direct|auto_generated|rx_cdr_pll0_CLK_bus [0];
+assign \pma_direct|auto_generated|rx_deserclock_in [1] = \pma_direct|auto_generated|rx_cdr_pll0_CLK_bus [1];
+assign \pma_direct|auto_generated|rx_deserclock_in [2] = \pma_direct|auto_generated|rx_cdr_pll0_CLK_bus [2];
+assign \pma_direct|auto_generated|rx_deserclock_in [3] = \pma_direct|auto_generated|rx_cdr_pll0_CLK_bus [3];
+
+assign \pma_direct|auto_generated|pll_ch_dataout_wire [2] = \pma_direct|auto_generated|rx_cdr_pll1_DATAOUT_bus [0];
+assign \pma_direct|auto_generated|pll_ch_dataout_wire [3] = \pma_direct|auto_generated|rx_cdr_pll1_DATAOUT_bus [1];
+
+assign \pma_direct|auto_generated|rx_deserclock_in [4] = \pma_direct|auto_generated|rx_cdr_pll1_CLK_bus [0];
+assign \pma_direct|auto_generated|rx_deserclock_in [5] = \pma_direct|auto_generated|rx_cdr_pll1_CLK_bus [1];
+assign \pma_direct|auto_generated|rx_deserclock_in [6] = \pma_direct|auto_generated|rx_cdr_pll1_CLK_bus [2];
+assign \pma_direct|auto_generated|rx_deserclock_in [7] = \pma_direct|auto_generated|rx_cdr_pll1_CLK_bus [3];
+
+assign \pma_direct|auto_generated|pll_ch_dataout_wire [4] = \pma_direct|auto_generated|rx_cdr_pll2_DATAOUT_bus [0];
+assign \pma_direct|auto_generated|pll_ch_dataout_wire [5] = \pma_direct|auto_generated|rx_cdr_pll2_DATAOUT_bus [1];
+
+assign \pma_direct|auto_generated|rx_deserclock_in [8] = \pma_direct|auto_generated|rx_cdr_pll2_CLK_bus [0];
+assign \pma_direct|auto_generated|rx_deserclock_in [9] = \pma_direct|auto_generated|rx_cdr_pll2_CLK_bus [1];
+assign \pma_direct|auto_generated|rx_deserclock_in [10] = \pma_direct|auto_generated|rx_cdr_pll2_CLK_bus [2];
+assign \pma_direct|auto_generated|rx_deserclock_in [11] = \pma_direct|auto_generated|rx_cdr_pll2_CLK_bus [3];
+
+assign \pma_direct|auto_generated|pll_ch_dataout_wire [6] = \pma_direct|auto_generated|rx_cdr_pll3_DATAOUT_bus [0];
+assign \pma_direct|auto_generated|pll_ch_dataout_wire [7] = \pma_direct|auto_generated|rx_cdr_pll3_DATAOUT_bus [1];
+
+assign \pma_direct|auto_generated|rx_deserclock_in [12] = \pma_direct|auto_generated|rx_cdr_pll3_CLK_bus [0];
+assign \pma_direct|auto_generated|rx_deserclock_in [13] = \pma_direct|auto_generated|rx_cdr_pll3_CLK_bus [1];
+assign \pma_direct|auto_generated|rx_deserclock_in [14] = \pma_direct|auto_generated|rx_cdr_pll3_CLK_bus [2];
+assign \pma_direct|auto_generated|rx_deserclock_in [15] = \pma_direct|auto_generated|rx_cdr_pll3_CLK_bus [3];
+
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5400] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [0];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5401] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [1];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5402] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [2];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5403] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [3];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5404] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [4];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5405] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [5];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5406] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [6];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5407] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [7];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5408] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [8];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5409] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [9];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5410] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [10];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5411] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [11];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5412] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [12];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5413] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [13];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5414] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [14];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5415] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [15];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5416] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [16];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5417] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [17];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5418] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [18];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5419] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [19];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5420] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [20];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5421] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [21];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5422] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [22];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5423] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [23];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5424] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [24];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5425] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [25];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5426] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [26];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5427] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [27];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5428] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [28];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5429] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [29];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5430] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [30];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5431] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [31];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5432] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [32];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5433] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [33];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5434] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [34];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5435] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [35];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5436] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [36];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5437] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [37];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5438] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [38];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5439] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [39];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5440] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [40];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5441] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [41];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5442] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [42];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5443] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [43];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5444] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [44];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5445] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [45];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5446] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [46];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5447] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [47];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5448] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [48];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5449] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [49];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5450] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [50];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5451] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [51];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5452] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [52];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5453] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [53];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5454] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [54];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5455] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [55];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5456] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [56];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5457] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [57];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5458] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [58];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5459] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [59];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5460] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [60];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5461] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [61];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5462] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [62];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5463] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [63];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5464] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [64];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5465] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [65];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5466] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [66];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5467] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [67];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5468] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [68];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5469] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [69];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5470] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [70];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5471] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [71];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5472] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [72];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5473] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [73];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5474] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [74];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5475] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [75];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5476] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [76];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5477] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [77];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5478] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [78];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5479] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [79];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5480] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [80];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5481] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [81];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5482] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [82];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5483] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [83];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5484] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [84];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5485] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [85];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5486] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [86];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5487] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [87];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5488] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [88];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5489] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [89];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5490] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [90];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5491] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [91];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5492] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [92];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5493] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [93];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5494] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [94];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5495] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [95];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5496] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [96];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5497] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [97];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5498] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [98];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5499] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [99];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5500] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [100];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5501] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [101];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5502] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [102];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5503] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [103];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5504] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [104];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5505] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [105];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5506] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [106];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5507] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [107];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5508] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [108];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5509] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [109];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5510] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [110];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5511] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [111];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5512] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [112];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5513] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [113];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5514] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [114];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5515] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [115];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5516] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [116];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5517] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [117];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5518] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [118];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5519] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [119];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5520] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [120];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5521] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [121];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5522] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [122];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5523] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [123];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5524] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [124];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5525] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [125];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5526] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [126];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5527] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [127];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5528] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [128];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5529] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [129];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5530] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [130];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5531] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [131];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5532] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [132];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5533] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [133];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5534] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [134];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5535] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [135];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5536] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [136];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5537] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [137];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5538] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [138];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5539] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [139];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5540] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [140];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5541] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [141];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5542] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [142];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5543] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [143];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5544] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [144];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5545] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [145];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5546] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [146];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5547] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [147];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5548] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [148];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5549] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [149];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5550] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [150];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5551] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [151];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5552] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [152];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5553] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [153];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5554] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [154];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5555] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [155];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5556] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [156];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5557] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [157];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5558] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [158];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5559] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [159];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5560] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [160];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5561] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [161];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5562] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [162];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5563] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [163];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5564] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [164];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5565] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [165];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5566] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [166];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5567] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [167];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5568] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [168];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5569] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [169];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5570] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [170];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5571] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [171];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5572] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [172];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5573] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [173];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5574] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [174];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5575] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [175];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5576] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [176];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5577] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [177];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5578] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [178];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5579] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [179];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5580] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [180];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5581] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [181];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5582] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [182];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5583] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [183];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5584] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [184];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5585] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [185];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5586] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [186];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5587] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [187];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5588] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [188];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5589] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [189];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5590] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [190];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5591] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [191];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5592] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [192];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5593] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [193];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5594] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [194];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5595] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [195];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5596] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [196];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5597] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [197];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5598] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [198];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5599] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [199];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5600] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [200];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5601] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [201];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5602] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [202];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5603] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [203];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5604] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [204];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5605] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [205];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5606] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [206];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5607] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [207];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5608] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [208];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5609] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [209];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5610] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [210];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5611] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [211];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5612] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [212];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5613] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [213];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5614] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [214];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5615] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [215];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5616] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [216];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5617] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [217];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5618] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [218];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5619] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [219];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5620] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [220];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5621] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [221];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5622] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [222];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5623] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [223];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5624] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [224];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5625] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [225];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5626] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [226];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5627] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [227];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5628] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [228];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5629] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [229];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5630] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [230];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5631] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [231];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5632] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [232];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5633] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [233];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5634] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [234];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5635] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [235];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5636] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [236];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5637] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [237];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5638] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [238];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5639] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [239];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5640] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [240];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5641] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [241];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5642] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [242];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5643] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [243];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5644] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [244];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5645] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [245];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5646] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [246];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5647] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [247];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5648] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [248];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5649] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [249];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5650] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [250];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5651] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [251];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5652] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [252];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5653] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [253];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5654] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [254];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5655] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [255];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5656] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [256];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5657] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [257];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5658] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [258];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5659] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [259];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5660] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [260];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5661] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [261];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5662] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [262];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5663] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [263];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5664] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [264];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5665] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [265];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5666] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [266];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5667] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [267];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5668] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [268];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5669] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [269];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5670] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [270];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5671] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [271];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5672] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [272];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5673] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [273];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5674] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [274];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5675] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [275];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5676] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [276];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5677] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [277];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5678] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [278];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5679] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [279];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5680] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [280];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5681] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [281];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5682] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [282];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5683] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [283];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5684] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [284];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5685] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [285];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5686] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [286];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5687] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [287];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5688] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [288];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5689] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [289];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5690] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [290];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5691] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [291];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5692] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [292];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5693] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [293];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5694] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [294];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5695] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [295];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5696] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [296];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5697] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [297];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5698] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [298];
+assign \pma_direct|auto_generated|pll_cmuplldprioout [5699] = \pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus [299];
+
+assign \pma_direct|auto_generated|edge_pllreset_in [0] = \pma_direct|auto_generated|tx_pll_cent_unit0_PLLRESETOUT_bus [0];
+
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXANALOGRESETOUT0 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXANALOGRESETOUT_bus [0];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXANALOGRESETOUT1 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXANALOGRESETOUT_bus [1];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXANALOGRESETOUT2 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXANALOGRESETOUT_bus [2];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXANALOGRESETOUT3 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXANALOGRESETOUT_bus [3];
+
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXANALOGRESETOUT0 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXANALOGRESETOUT_bus [0];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXANALOGRESETOUT1 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXANALOGRESETOUT_bus [1];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXANALOGRESETOUT2 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXANALOGRESETOUT_bus [2];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXANALOGRESETOUT3 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXANALOGRESETOUT_bus [3];
+
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [0] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [0];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [2] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [2];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [3] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [3];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [4] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [4];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [5] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [5];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [6] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [6];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [7] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [7];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [8] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [8];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [9] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [9];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [10] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [10];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [11] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [11];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [12] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [12];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [13] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [13];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [14] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [14];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [15] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [15];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [16] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [16];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [17] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [17];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [18] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [18];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [19] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [19];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [20] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [20];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [21] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [21];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [22] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [22];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [23] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [23];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [24] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [24];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [25] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [25];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [26] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [26];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [27] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [27];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [28] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [28];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [29] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [29];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [30] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [30];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [31] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [31];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [32] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [32];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [33] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [33];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [34] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [34];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [35] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [35];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [36] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [36];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [37] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [37];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [38] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [38];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [39] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [39];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [40] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [40];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [41] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [41];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [42] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [42];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [43] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [43];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [44] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [44];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [45] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [45];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [46] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [46];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [47] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [47];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [48] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [48];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [49] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [49];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [50] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [50];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [51] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [51];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [52] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [52];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [53] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [53];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [54] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [54];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [55] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [55];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [56] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [56];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [57] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [57];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [58] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [58];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [59] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [59];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [60] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [60];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [61] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [61];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [62] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [62];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [63] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [63];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [64] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [64];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [65] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [65];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [66] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [66];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [67] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [67];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [68] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [68];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [69] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [69];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [70] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [70];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [71] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [71];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [72] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [72];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [73] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [73];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [74] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [74];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [75] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [75];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [76] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [76];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [77] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [77];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [78] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [78];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [79] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [79];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [80] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [80];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [81] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [81];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [82] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [82];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [83] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [83];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [84] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [84];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [85] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [85];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [86] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [86];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [87] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [87];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [88] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [88];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [89] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [89];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [90] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [90];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [91] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [91];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [92] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [92];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [93] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [93];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [94] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [94];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [95] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [95];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [96] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [96];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [97] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [97];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [98] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [98];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [99] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [99];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [100] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [100];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [101] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [101];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [102] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [102];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [103] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [103];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [104] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [104];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [105] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [105];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [106] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [106];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [107] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [107];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [108] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [108];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [109] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [109];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [110] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [110];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [111] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [111];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [112] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [112];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [113] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [113];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [114] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [114];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [115] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [115];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [116] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [116];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [117] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [117];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [118] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [118];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [119] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [119];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [120] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [120];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [121] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [121];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [122] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [122];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [123] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [123];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [124] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [124];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [125] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [125];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [126] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [126];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [127] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [127];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [128] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [128];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [129] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [129];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [130] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [130];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [131] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [131];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [132] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [132];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [133] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [133];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [134] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [134];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [135] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [135];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [136] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [136];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [137] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [137];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [138] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [138];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [139] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [139];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [140] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [140];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [141] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [141];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [142] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [142];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [143] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [143];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [144] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [144];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [145] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [145];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [146] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [146];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [147] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [147];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [148] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [148];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [149] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [149];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [150] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [150];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [151] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [151];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [152] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [152];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [153] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [153];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [154] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [154];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [155] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [155];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [156] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [156];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [157] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [157];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [158] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [158];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [159] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [159];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [160] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [160];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [161] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [161];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [162] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [162];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [163] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [163];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [164] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [164];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [165] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [165];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [166] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [166];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [167] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [167];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [168] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [168];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [169] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [169];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [170] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [170];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [171] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [171];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [172] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [172];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [173] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [173];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [174] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [174];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [175] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [175];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [176] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [176];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [177] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [177];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [178] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [178];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [179] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [179];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [180] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [180];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [181] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [181];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [182] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [182];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [183] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [183];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [184] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [184];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [185] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [185];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [186] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [186];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [187] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [187];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [188] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [188];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [189] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [189];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [190] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [190];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [191] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [191];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [192] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [192];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [193] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [193];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [194] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [194];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [195] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [195];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [196] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [196];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [197] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [197];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [198] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [198];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [199] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [199];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [200] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [200];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [201] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [201];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [202] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [202];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [203] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [203];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [204] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [204];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [205] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [205];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [206] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [206];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [207] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [207];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [208] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [208];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [209] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [209];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [210] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [210];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [211] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [211];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [212] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [212];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [213] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [213];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [214] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [214];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [215] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [215];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [216] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [216];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [217] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [217];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [218] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [218];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [219] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [219];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [220] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [220];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [221] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [221];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [222] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [222];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [223] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [223];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [224] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [224];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [225] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [225];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [226] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [226];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [227] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [227];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [228] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [228];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [229] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [229];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [230] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [230];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [231] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [231];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [232] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [232];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [233] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [233];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [234] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [234];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [235] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [235];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [236] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [236];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [237] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [237];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [238] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [238];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [239] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [239];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [240] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [240];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [241] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [241];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [242] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [242];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [243] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [243];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [244] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [244];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [245] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [245];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [246] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [246];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [247] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [247];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [248] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [248];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [249] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [249];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [250] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [250];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [251] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [251];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [252] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [252];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [253] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [253];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [254] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [254];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [255] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [255];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [256] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [256];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [257] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [257];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [258] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [258];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [259] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [259];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [260] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [260];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [261] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [261];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [262] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [262];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [263] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [263];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [264] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [264];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [265] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [265];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [266] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [266];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [267] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [267];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [268] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [268];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [269] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [269];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [270] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [270];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [271] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [271];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [272] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [272];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [273] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [273];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [274] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [274];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [275] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [275];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [276] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [276];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [277] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [277];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [278] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [278];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [279] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [279];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [280] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [280];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [281] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [281];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [282] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [282];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [283] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [283];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [284] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [284];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [285] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [285];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [286] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [286];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [287] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [287];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [288] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [288];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [289] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [289];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [290] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [290];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [291] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [291];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [292] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [292];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [293] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [293];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [294] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [294];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [295] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [295];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [296] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [296];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [297] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [297];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [298] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [298];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [299] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [299];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [300] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [300];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [301] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [301];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [302] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [302];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [303] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [303];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [304] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [304];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [305] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [305];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [306] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [306];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [307] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [307];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [308] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [308];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [309] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [309];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [310] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [310];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [311] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [311];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [312] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [312];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [313] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [313];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [314] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [314];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [315] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [315];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [316] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [316];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [317] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [317];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [318] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [318];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [319] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [319];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [320] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [320];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [321] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [321];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [322] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [322];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [323] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [323];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [324] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [324];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [325] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [325];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [326] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [326];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [327] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [327];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [328] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [328];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [329] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [329];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [330] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [330];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [331] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [331];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [332] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [332];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [333] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [333];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [334] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [334];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [335] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [335];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [336] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [336];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [337] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [337];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [338] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [338];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [339] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [339];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [340] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [340];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [341] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [341];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [342] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [342];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [343] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [343];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [344] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [344];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [345] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [345];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [346] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [346];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [347] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [347];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [348] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [348];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [349] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [349];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [350] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [350];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [351] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [351];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [352] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [352];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [353] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [353];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [354] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [354];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [355] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [355];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [356] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [356];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [357] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [357];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [358] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [358];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [359] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [359];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [360] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [360];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [361] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [361];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [362] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [362];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [363] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [363];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [364] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [364];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [365] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [365];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [366] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [366];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [367] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [367];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [368] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [368];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [369] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [369];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [370] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [370];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [371] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [371];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [372] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [372];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [373] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [373];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [374] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [374];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [375] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [375];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [376] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [376];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [377] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [377];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [378] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [378];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [379] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [379];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [380] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [380];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [381] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [381];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [382] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [382];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [383] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [383];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [384] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [384];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [385] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [385];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [386] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [386];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [387] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [387];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [388] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [388];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [389] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [389];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [390] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [390];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [391] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [391];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [392] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [392];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [393] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [393];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [394] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [394];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [395] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [395];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [396] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [396];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [397] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [397];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [398] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [398];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [399] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [399];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [400] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [400];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [401] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [401];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [402] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [402];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [403] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [403];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [404] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [404];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [405] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [405];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [406] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [406];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [407] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [407];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [408] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [408];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [409] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [409];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [410] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [410];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [411] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [411];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [412] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [412];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [413] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [413];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [414] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [414];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [415] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [415];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [416] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [416];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [417] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [417];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [418] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [418];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [419] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [419];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [420] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [420];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [421] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [421];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [422] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [422];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [423] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [423];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [424] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [424];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [425] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [425];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [426] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [426];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [427] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [427];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [428] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [428];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [429] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [429];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [430] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [430];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [431] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [431];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [432] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [432];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [433] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [433];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [434] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [434];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [435] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [435];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [436] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [436];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [437] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [437];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [438] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [438];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [439] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [439];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [440] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [440];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [441] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [441];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [442] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [442];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [443] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [443];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [444] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [444];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [445] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [445];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [446] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [446];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [447] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [447];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [448] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [448];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [449] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [449];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [450] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [450];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [451] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [451];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [452] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [452];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [453] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [453];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [454] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [454];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [455] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [455];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [456] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [456];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [457] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [457];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [458] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [458];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [459] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [459];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [460] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [460];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [461] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [461];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [462] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [462];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [463] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [463];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [464] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [464];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [465] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [465];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [466] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [466];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [467] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [467];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [468] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [468];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [469] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [469];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [470] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [470];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [471] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [471];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [472] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [472];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [473] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [473];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [474] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [474];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [475] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [475];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [476] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [476];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [477] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [477];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [478] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [478];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [479] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [479];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [480] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [480];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [481] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [481];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [482] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [482];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [483] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [483];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [484] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [484];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [485] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [485];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [486] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [486];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [487] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [487];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [488] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [488];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [489] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [489];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [490] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [490];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [491] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [491];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [492] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [492];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [493] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [493];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [494] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [494];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [495] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [495];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [496] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [496];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [497] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [497];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [498] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [498];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [499] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [499];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [500] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [500];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [501] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [501];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [502] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [502];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [503] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [503];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [504] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [504];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [505] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [505];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [506] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [506];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [507] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [507];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [508] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [508];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [509] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [509];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [510] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [510];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [511] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [511];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [512] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [512];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [513] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [513];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [514] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [514];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [515] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [515];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [516] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [516];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [517] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [517];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [518] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [518];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [519] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [519];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [520] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [520];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [521] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [521];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [522] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [522];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [523] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [523];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [524] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [524];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [525] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [525];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [526] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [526];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [527] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [527];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [528] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [528];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [529] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [529];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [530] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [530];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [531] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [531];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [532] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [532];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [533] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [533];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [534] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [534];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [535] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [535];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [536] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [536];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [537] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [537];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [538] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [538];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [539] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [539];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [540] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [540];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [541] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [541];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [542] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [542];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [543] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [543];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [544] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [544];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [545] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [545];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [546] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [546];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [547] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [547];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [548] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [548];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [549] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [549];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [550] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [550];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [551] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [551];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [552] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [552];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [553] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [553];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [554] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [554];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [555] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [555];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [556] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [556];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [557] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [557];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [558] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [558];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [559] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [559];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [560] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [560];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [561] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [561];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [562] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [562];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [563] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [563];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [564] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [564];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [565] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [565];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [566] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [566];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [567] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [567];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [568] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [568];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [569] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [569];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [570] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [570];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [571] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [571];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [572] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [572];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [573] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [573];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [574] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [574];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [575] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [575];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [576] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [576];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [577] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [577];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [578] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [578];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [579] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [579];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [580] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [580];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [581] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [581];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [582] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [582];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [583] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [583];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [584] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [584];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [585] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [585];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [586] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [586];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [587] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [587];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [588] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [588];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [589] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [589];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [590] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [590];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [591] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [591];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [592] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [592];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [593] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [593];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [594] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [594];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [595] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [595];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [596] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [596];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [597] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [597];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [598] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [598];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [599] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [599];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [600] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [600];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [601] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [601];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [602] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [602];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [603] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [603];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [604] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [604];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [605] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [605];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [606] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [606];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [607] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [607];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [608] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [608];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [609] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [609];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [610] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [610];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [611] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [611];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [612] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [612];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [613] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [613];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [614] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [614];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [615] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [615];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [616] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [616];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [617] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [617];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [618] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [618];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [619] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [619];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [620] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [620];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [621] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [621];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [622] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [622];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [623] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [623];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [624] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [624];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [625] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [625];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [626] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [626];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [627] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [627];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [628] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [628];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [629] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [629];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [630] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [630];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [631] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [631];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [632] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [632];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [633] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [633];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [634] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [634];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [635] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [635];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [636] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [636];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [637] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [637];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [638] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [638];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [639] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [639];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [640] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [640];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [641] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [641];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [642] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [642];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [643] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [643];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [644] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [644];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [645] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [645];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [646] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [646];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [647] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [647];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [648] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [648];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [649] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [649];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [650] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [650];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [651] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [651];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [652] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [652];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [653] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [653];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [654] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [654];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [655] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [655];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [656] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [656];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [657] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [657];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [658] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [658];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [659] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [659];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [660] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [660];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [661] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [661];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [662] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [662];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [663] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [663];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [664] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [664];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [665] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [665];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [666] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [666];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [667] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [667];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [668] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [668];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [669] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [669];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [670] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [670];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [671] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [671];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [672] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [672];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [673] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [673];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [674] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [674];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [675] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [675];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [676] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [676];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [677] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [677];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [678] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [678];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [679] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [679];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [680] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [680];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [681] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [681];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [682] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [682];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [683] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [683];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [684] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [684];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [685] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [685];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [686] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [686];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [687] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [687];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [688] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [688];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [689] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [689];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [690] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [690];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [691] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [691];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [692] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [692];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [693] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [693];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [694] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [694];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [695] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [695];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [696] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [696];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [697] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [697];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [698] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [698];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [699] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [699];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [700] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [700];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [701] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [701];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [702] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [702];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [703] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [703];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [704] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [704];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [705] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [705];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [706] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [706];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [707] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [707];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [708] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [708];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [709] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [709];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [710] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [710];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [711] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [711];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [712] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [712];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [713] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [713];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [714] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [714];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [715] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [715];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [716] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [716];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [717] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [717];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [718] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [718];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [719] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [719];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [720] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [720];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [721] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [721];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [722] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [722];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [723] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [723];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [724] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [724];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [725] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [725];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [726] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [726];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [727] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [727];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [728] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [728];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [729] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [729];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [730] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [730];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [731] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [731];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [732] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [732];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [733] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [733];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [734] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [734];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [735] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [735];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [736] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [736];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [737] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [737];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [738] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [738];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [739] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [739];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [740] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [740];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [741] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [741];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [742] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [742];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [743] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [743];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [744] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [744];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [745] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [745];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [746] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [746];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [747] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [747];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [748] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [748];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [749] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [749];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [750] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [750];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [751] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [751];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [752] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [752];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [753] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [753];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [754] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [754];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [755] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [755];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [756] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [756];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [757] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [757];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [758] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [758];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [759] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [759];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [760] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [760];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [761] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [761];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [762] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [762];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [763] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [763];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [764] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [764];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [765] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [765];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [766] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [766];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [767] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [767];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [768] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [768];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [769] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [769];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [770] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [770];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [771] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [771];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [772] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [772];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [773] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [773];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [774] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [774];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [775] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [775];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [776] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [776];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [777] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [777];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [778] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [778];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [779] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [779];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [780] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [780];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [781] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [781];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [782] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [782];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [783] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [783];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [784] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [784];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [785] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [785];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [786] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [786];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [787] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [787];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [788] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [788];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [789] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [789];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [790] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [790];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [791] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [791];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [792] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [792];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [793] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [793];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [794] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [794];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [795] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [795];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [796] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [796];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [797] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [797];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [798] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [798];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [799] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [799];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [800] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [800];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [801] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [801];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [802] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [802];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [803] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [803];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [804] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [804];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [805] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [805];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [806] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [806];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [807] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [807];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [808] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [808];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [809] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [809];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [810] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [810];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [811] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [811];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [812] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [812];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [813] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [813];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [814] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [814];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [815] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [815];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [816] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [816];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [817] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [817];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [818] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [818];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [819] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [819];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [820] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [820];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [821] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [821];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [822] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [822];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [823] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [823];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [824] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [824];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [825] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [825];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [826] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [826];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [827] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [827];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [828] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [828];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [829] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [829];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [830] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [830];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [831] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [831];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [832] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [832];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [833] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [833];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [834] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [834];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [835] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [835];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [836] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [836];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [837] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [837];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [838] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [838];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [839] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [839];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [840] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [840];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [841] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [841];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [842] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [842];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [843] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [843];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [844] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [844];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [845] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [845];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [846] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [846];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [847] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [847];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [848] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [848];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [849] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [849];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [850] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [850];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [851] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [851];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [852] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [852];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [853] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [853];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [854] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [854];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [855] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [855];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [856] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [856];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [857] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [857];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [858] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [858];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [859] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [859];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [860] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [860];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [861] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [861];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [862] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [862];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [863] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [863];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [864] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [864];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [865] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [865];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [866] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [866];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [867] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [867];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [868] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [868];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [869] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [869];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [870] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [870];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [871] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [871];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [872] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [872];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [873] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [873];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [874] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [874];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [875] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [875];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [876] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [876];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [877] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [877];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [878] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [878];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [879] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [879];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [880] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [880];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [881] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [881];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [882] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [882];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [883] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [883];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [884] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [884];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [885] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [885];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [886] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [886];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [887] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [887];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [888] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [888];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [889] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [889];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [890] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [890];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [891] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [891];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [892] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [892];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [893] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [893];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [894] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [894];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [895] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [895];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [896] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [896];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [897] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [897];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [898] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [898];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [899] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [899];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [900] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [900];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [901] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [901];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [902] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [902];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [903] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [903];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [904] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [904];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [905] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [905];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [906] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [906];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [907] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [907];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [908] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [908];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [909] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [909];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [910] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [910];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [911] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [911];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [912] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [912];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [913] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [913];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [914] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [914];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [915] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [915];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [916] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [916];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [917] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [917];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [918] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [918];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [919] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [919];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [920] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [920];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [921] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [921];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [922] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [922];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [923] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [923];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [924] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [924];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [925] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [925];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [926] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [926];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [927] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [927];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [928] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [928];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [929] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [929];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [930] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [930];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [931] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [931];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [932] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [932];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [933] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [933];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [934] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [934];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [935] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [935];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [936] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [936];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [937] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [937];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [938] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [938];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [939] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [939];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [940] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [940];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [941] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [941];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [942] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [942];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [943] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [943];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [944] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [944];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [945] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [945];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [946] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [946];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [947] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [947];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [948] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [948];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [949] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [949];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [950] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [950];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [951] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [951];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [952] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [952];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [953] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [953];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [954] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [954];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [955] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [955];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [956] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [956];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [957] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [957];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [958] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [958];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [959] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [959];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [960] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [960];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [961] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [961];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [962] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [962];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [963] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [963];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [964] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [964];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [965] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [965];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [966] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [966];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [967] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [967];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [968] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [968];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [969] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [969];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [970] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [970];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [971] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [971];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [972] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [972];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [973] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [973];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [974] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [974];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [975] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [975];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [976] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [976];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [977] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [977];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [978] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [978];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [979] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [979];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [980] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [980];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [981] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [981];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [982] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [982];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [983] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [983];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [984] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [984];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [985] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [985];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [986] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [986];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [987] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [987];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [988] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [988];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [989] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [989];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [990] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [990];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [991] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [991];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [992] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [992];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [993] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [993];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [994] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [994];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [995] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [995];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [996] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [996];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [997] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [997];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [998] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [998];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [999] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [999];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1000] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1000];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1001] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1001];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1002] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1002];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1003] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1003];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1004] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1004];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1005] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1005];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1006] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1006];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1007] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1007];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1008] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1008];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1009] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1009];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1010] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1010];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1011] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1011];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1012] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1012];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1013] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1013];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1014] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1014];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1015] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1015];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1016] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1016];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1017] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1017];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1018] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1018];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1019] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1019];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1020] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1020];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1021] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1021];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1022] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1022];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1023] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1023];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1024] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1024];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1025] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1025];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1026] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1026];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1027] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1027];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1028] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1028];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1029] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1029];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1030] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1030];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1031] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1031];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1032] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1032];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1033] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1033];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1034] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1034];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1035] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1035];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1036] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1036];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1037] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1037];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1038] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1038];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1039] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1039];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1040] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1040];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1041] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1041];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1042] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1042];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1043] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1043];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1044] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1044];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1045] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1045];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1046] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1046];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1047] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1047];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1048] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1048];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1049] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1049];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1050] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1050];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1051] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1051];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1052] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1052];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1053] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1053];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1054] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1054];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1055] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1055];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1056] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1056];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1057] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1057];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1058] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1058];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1059] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1059];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1060] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1060];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1061] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1061];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1062] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1062];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1063] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1063];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1064] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1064];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1065] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1065];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1066] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1066];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1067] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1067];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1068] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1068];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1069] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1069];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1070] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1070];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1071] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1071];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1072] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1072];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1073] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1073];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1074] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1074];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1075] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1075];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1076] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1076];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1077] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1077];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1078] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1078];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1079] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1079];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1080] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1080];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1081] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1081];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1082] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1082];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1083] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1083];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1084] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1084];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1085] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1085];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1086] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1086];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1087] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1087];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1088] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1088];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1089] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1089];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1090] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1090];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1091] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1091];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1092] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1092];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1093] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1093];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1094] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1094];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1095] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1095];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1096] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1096];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1097] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1097];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1098] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1098];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1099] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1099];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1100] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1100];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1101] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1101];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1102] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1102];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1103] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1103];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1104] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1104];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1105] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1105];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1106] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1106];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1107] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1107];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1108] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1108];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1109] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1109];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1110] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1110];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1111] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1111];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1112] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1112];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1113] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1113];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1114] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1114];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1115] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1115];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1116] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1116];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1117] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1117];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1118] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1118];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1119] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1119];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1120] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1120];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1121] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1121];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1122] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1122];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1123] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1123];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1124] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1124];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1125] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1125];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1126] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1126];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1127] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1127];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1128] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1128];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1129] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1129];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1130] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1130];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1131] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1131];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1132] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1132];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1133] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1133];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1134] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1134];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1135] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1135];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1136] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1136];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1137] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1137];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1138] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1138];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1139] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1139];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1140] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1140];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1141] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1141];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1142] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1142];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1143] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1143];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1144] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1144];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1145] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1145];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1146] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1146];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1147] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1147];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1148] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1148];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1149] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1149];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1150] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1150];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1151] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1151];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1152] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1152];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1153] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1153];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1154] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1154];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1155] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1155];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1156] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1156];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1157] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1157];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1158] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1158];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1159] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1159];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1160] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1160];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1161] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1161];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1162] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1162];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1163] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1163];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1164] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1164];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1165] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1165];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1166] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1166];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1167] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1167];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1168] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1168];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1169] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1169];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1170] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1170];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1171] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1171];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1172] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1172];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1173] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1173];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1174] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1174];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1175] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1175];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1176] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1176];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1177] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1177];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1178] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1178];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1179] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1179];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1180] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1180];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1181] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1181];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1182] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1182];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1183] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1183];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1184] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1184];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1185] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1185];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1186] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1186];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1187] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1187];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1188] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1188];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1189] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1189];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1190] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1190];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1191] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1191];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1192] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1192];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1193] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1193];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1194] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1194];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1195] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1195];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1196] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1196];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1197] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1197];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1198] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1198];
+assign \pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1199] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1199];
+assign \pma_direct|auto_generated|edge_pll_dprioin [0] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1200];
+assign \pma_direct|auto_generated|edge_pll_dprioin [1] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1201];
+assign \pma_direct|auto_generated|edge_pll_dprioin [2] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1202];
+assign \pma_direct|auto_generated|edge_pll_dprioin [3] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1203];
+assign \pma_direct|auto_generated|edge_pll_dprioin [4] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1204];
+assign \pma_direct|auto_generated|edge_pll_dprioin [5] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1205];
+assign \pma_direct|auto_generated|edge_pll_dprioin [6] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1206];
+assign \pma_direct|auto_generated|edge_pll_dprioin [7] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1207];
+assign \pma_direct|auto_generated|edge_pll_dprioin [8] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1208];
+assign \pma_direct|auto_generated|edge_pll_dprioin [9] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1209];
+assign \pma_direct|auto_generated|edge_pll_dprioin [10] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1210];
+assign \pma_direct|auto_generated|edge_pll_dprioin [11] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1211];
+assign \pma_direct|auto_generated|edge_pll_dprioin [12] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1212];
+assign \pma_direct|auto_generated|edge_pll_dprioin [13] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1213];
+assign \pma_direct|auto_generated|edge_pll_dprioin [14] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1214];
+assign \pma_direct|auto_generated|edge_pll_dprioin [15] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1215];
+assign \pma_direct|auto_generated|edge_pll_dprioin [16] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1216];
+assign \pma_direct|auto_generated|edge_pll_dprioin [17] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1217];
+assign \pma_direct|auto_generated|edge_pll_dprioin [18] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1218];
+assign \pma_direct|auto_generated|edge_pll_dprioin [19] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1219];
+assign \pma_direct|auto_generated|edge_pll_dprioin [20] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1220];
+assign \pma_direct|auto_generated|edge_pll_dprioin [21] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1221];
+assign \pma_direct|auto_generated|edge_pll_dprioin [22] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1222];
+assign \pma_direct|auto_generated|edge_pll_dprioin [23] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1223];
+assign \pma_direct|auto_generated|edge_pll_dprioin [24] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1224];
+assign \pma_direct|auto_generated|edge_pll_dprioin [25] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1225];
+assign \pma_direct|auto_generated|edge_pll_dprioin [26] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1226];
+assign \pma_direct|auto_generated|edge_pll_dprioin [27] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1227];
+assign \pma_direct|auto_generated|edge_pll_dprioin [28] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1228];
+assign \pma_direct|auto_generated|edge_pll_dprioin [29] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1229];
+assign \pma_direct|auto_generated|edge_pll_dprioin [30] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1230];
+assign \pma_direct|auto_generated|edge_pll_dprioin [31] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1231];
+assign \pma_direct|auto_generated|edge_pll_dprioin [32] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1232];
+assign \pma_direct|auto_generated|edge_pll_dprioin [33] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1233];
+assign \pma_direct|auto_generated|edge_pll_dprioin [34] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1234];
+assign \pma_direct|auto_generated|edge_pll_dprioin [35] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1235];
+assign \pma_direct|auto_generated|edge_pll_dprioin [36] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1236];
+assign \pma_direct|auto_generated|edge_pll_dprioin [37] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1237];
+assign \pma_direct|auto_generated|edge_pll_dprioin [38] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1238];
+assign \pma_direct|auto_generated|edge_pll_dprioin [39] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1239];
+assign \pma_direct|auto_generated|edge_pll_dprioin [40] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1240];
+assign \pma_direct|auto_generated|edge_pll_dprioin [41] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1241];
+assign \pma_direct|auto_generated|edge_pll_dprioin [42] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1242];
+assign \pma_direct|auto_generated|edge_pll_dprioin [43] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1243];
+assign \pma_direct|auto_generated|edge_pll_dprioin [44] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1244];
+assign \pma_direct|auto_generated|edge_pll_dprioin [45] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1245];
+assign \pma_direct|auto_generated|edge_pll_dprioin [46] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1246];
+assign \pma_direct|auto_generated|edge_pll_dprioin [47] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1247];
+assign \pma_direct|auto_generated|edge_pll_dprioin [48] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1248];
+assign \pma_direct|auto_generated|edge_pll_dprioin [49] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1249];
+assign \pma_direct|auto_generated|edge_pll_dprioin [50] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1250];
+assign \pma_direct|auto_generated|edge_pll_dprioin [51] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1251];
+assign \pma_direct|auto_generated|edge_pll_dprioin [52] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1252];
+assign \pma_direct|auto_generated|edge_pll_dprioin [53] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1253];
+assign \pma_direct|auto_generated|edge_pll_dprioin [54] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1254];
+assign \pma_direct|auto_generated|edge_pll_dprioin [55] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1255];
+assign \pma_direct|auto_generated|edge_pll_dprioin [56] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1256];
+assign \pma_direct|auto_generated|edge_pll_dprioin [57] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1257];
+assign \pma_direct|auto_generated|edge_pll_dprioin [58] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1258];
+assign \pma_direct|auto_generated|edge_pll_dprioin [59] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1259];
+assign \pma_direct|auto_generated|edge_pll_dprioin [60] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1260];
+assign \pma_direct|auto_generated|edge_pll_dprioin [61] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1261];
+assign \pma_direct|auto_generated|edge_pll_dprioin [62] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1262];
+assign \pma_direct|auto_generated|edge_pll_dprioin [63] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1263];
+assign \pma_direct|auto_generated|edge_pll_dprioin [64] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1264];
+assign \pma_direct|auto_generated|edge_pll_dprioin [65] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1265];
+assign \pma_direct|auto_generated|edge_pll_dprioin [66] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1266];
+assign \pma_direct|auto_generated|edge_pll_dprioin [67] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1267];
+assign \pma_direct|auto_generated|edge_pll_dprioin [68] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1268];
+assign \pma_direct|auto_generated|edge_pll_dprioin [69] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1269];
+assign \pma_direct|auto_generated|edge_pll_dprioin [70] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1270];
+assign \pma_direct|auto_generated|edge_pll_dprioin [71] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1271];
+assign \pma_direct|auto_generated|edge_pll_dprioin [72] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1272];
+assign \pma_direct|auto_generated|edge_pll_dprioin [73] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1273];
+assign \pma_direct|auto_generated|edge_pll_dprioin [74] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1274];
+assign \pma_direct|auto_generated|edge_pll_dprioin [75] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1275];
+assign \pma_direct|auto_generated|edge_pll_dprioin [76] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1276];
+assign \pma_direct|auto_generated|edge_pll_dprioin [77] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1277];
+assign \pma_direct|auto_generated|edge_pll_dprioin [78] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1278];
+assign \pma_direct|auto_generated|edge_pll_dprioin [79] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1279];
+assign \pma_direct|auto_generated|edge_pll_dprioin [80] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1280];
+assign \pma_direct|auto_generated|edge_pll_dprioin [81] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1281];
+assign \pma_direct|auto_generated|edge_pll_dprioin [82] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1282];
+assign \pma_direct|auto_generated|edge_pll_dprioin [83] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1283];
+assign \pma_direct|auto_generated|edge_pll_dprioin [84] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1284];
+assign \pma_direct|auto_generated|edge_pll_dprioin [85] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1285];
+assign \pma_direct|auto_generated|edge_pll_dprioin [86] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1286];
+assign \pma_direct|auto_generated|edge_pll_dprioin [87] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1287];
+assign \pma_direct|auto_generated|edge_pll_dprioin [88] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1288];
+assign \pma_direct|auto_generated|edge_pll_dprioin [89] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1289];
+assign \pma_direct|auto_generated|edge_pll_dprioin [90] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1290];
+assign \pma_direct|auto_generated|edge_pll_dprioin [91] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1291];
+assign \pma_direct|auto_generated|edge_pll_dprioin [92] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1292];
+assign \pma_direct|auto_generated|edge_pll_dprioin [93] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1293];
+assign \pma_direct|auto_generated|edge_pll_dprioin [94] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1294];
+assign \pma_direct|auto_generated|edge_pll_dprioin [95] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1295];
+assign \pma_direct|auto_generated|edge_pll_dprioin [96] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1296];
+assign \pma_direct|auto_generated|edge_pll_dprioin [97] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1297];
+assign \pma_direct|auto_generated|edge_pll_dprioin [98] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1298];
+assign \pma_direct|auto_generated|edge_pll_dprioin [99] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1299];
+assign \pma_direct|auto_generated|edge_pll_dprioin [100] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1300];
+assign \pma_direct|auto_generated|edge_pll_dprioin [101] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1301];
+assign \pma_direct|auto_generated|edge_pll_dprioin [102] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1302];
+assign \pma_direct|auto_generated|edge_pll_dprioin [103] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1303];
+assign \pma_direct|auto_generated|edge_pll_dprioin [104] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1304];
+assign \pma_direct|auto_generated|edge_pll_dprioin [105] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1305];
+assign \pma_direct|auto_generated|edge_pll_dprioin [106] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1306];
+assign \pma_direct|auto_generated|edge_pll_dprioin [107] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1307];
+assign \pma_direct|auto_generated|edge_pll_dprioin [108] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1308];
+assign \pma_direct|auto_generated|edge_pll_dprioin [109] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1309];
+assign \pma_direct|auto_generated|edge_pll_dprioin [110] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1310];
+assign \pma_direct|auto_generated|edge_pll_dprioin [111] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1311];
+assign \pma_direct|auto_generated|edge_pll_dprioin [112] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1312];
+assign \pma_direct|auto_generated|edge_pll_dprioin [113] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1313];
+assign \pma_direct|auto_generated|edge_pll_dprioin [114] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1314];
+assign \pma_direct|auto_generated|edge_pll_dprioin [115] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1315];
+assign \pma_direct|auto_generated|edge_pll_dprioin [116] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1316];
+assign \pma_direct|auto_generated|edge_pll_dprioin [117] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1317];
+assign \pma_direct|auto_generated|edge_pll_dprioin [118] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1318];
+assign \pma_direct|auto_generated|edge_pll_dprioin [119] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1319];
+assign \pma_direct|auto_generated|edge_pll_dprioin [120] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1320];
+assign \pma_direct|auto_generated|edge_pll_dprioin [121] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1321];
+assign \pma_direct|auto_generated|edge_pll_dprioin [122] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1322];
+assign \pma_direct|auto_generated|edge_pll_dprioin [123] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1323];
+assign \pma_direct|auto_generated|edge_pll_dprioin [124] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1324];
+assign \pma_direct|auto_generated|edge_pll_dprioin [125] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1325];
+assign \pma_direct|auto_generated|edge_pll_dprioin [126] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1326];
+assign \pma_direct|auto_generated|edge_pll_dprioin [127] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1327];
+assign \pma_direct|auto_generated|edge_pll_dprioin [128] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1328];
+assign \pma_direct|auto_generated|edge_pll_dprioin [129] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1329];
+assign \pma_direct|auto_generated|edge_pll_dprioin [130] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1330];
+assign \pma_direct|auto_generated|edge_pll_dprioin [131] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1331];
+assign \pma_direct|auto_generated|edge_pll_dprioin [132] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1332];
+assign \pma_direct|auto_generated|edge_pll_dprioin [133] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1333];
+assign \pma_direct|auto_generated|edge_pll_dprioin [134] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1334];
+assign \pma_direct|auto_generated|edge_pll_dprioin [135] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1335];
+assign \pma_direct|auto_generated|edge_pll_dprioin [136] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1336];
+assign \pma_direct|auto_generated|edge_pll_dprioin [137] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1337];
+assign \pma_direct|auto_generated|edge_pll_dprioin [138] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1338];
+assign \pma_direct|auto_generated|edge_pll_dprioin [139] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1339];
+assign \pma_direct|auto_generated|edge_pll_dprioin [140] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1340];
+assign \pma_direct|auto_generated|edge_pll_dprioin [141] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1341];
+assign \pma_direct|auto_generated|edge_pll_dprioin [142] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1342];
+assign \pma_direct|auto_generated|edge_pll_dprioin [143] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1343];
+assign \pma_direct|auto_generated|edge_pll_dprioin [144] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1344];
+assign \pma_direct|auto_generated|edge_pll_dprioin [145] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1345];
+assign \pma_direct|auto_generated|edge_pll_dprioin [146] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1346];
+assign \pma_direct|auto_generated|edge_pll_dprioin [147] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1347];
+assign \pma_direct|auto_generated|edge_pll_dprioin [148] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1348];
+assign \pma_direct|auto_generated|edge_pll_dprioin [149] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1349];
+assign \pma_direct|auto_generated|edge_pll_dprioin [150] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1350];
+assign \pma_direct|auto_generated|edge_pll_dprioin [151] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1351];
+assign \pma_direct|auto_generated|edge_pll_dprioin [152] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1352];
+assign \pma_direct|auto_generated|edge_pll_dprioin [153] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1353];
+assign \pma_direct|auto_generated|edge_pll_dprioin [154] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1354];
+assign \pma_direct|auto_generated|edge_pll_dprioin [155] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1355];
+assign \pma_direct|auto_generated|edge_pll_dprioin [156] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1356];
+assign \pma_direct|auto_generated|edge_pll_dprioin [157] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1357];
+assign \pma_direct|auto_generated|edge_pll_dprioin [158] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1358];
+assign \pma_direct|auto_generated|edge_pll_dprioin [159] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1359];
+assign \pma_direct|auto_generated|edge_pll_dprioin [160] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1360];
+assign \pma_direct|auto_generated|edge_pll_dprioin [161] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1361];
+assign \pma_direct|auto_generated|edge_pll_dprioin [162] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1362];
+assign \pma_direct|auto_generated|edge_pll_dprioin [163] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1363];
+assign \pma_direct|auto_generated|edge_pll_dprioin [164] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1364];
+assign \pma_direct|auto_generated|edge_pll_dprioin [165] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1365];
+assign \pma_direct|auto_generated|edge_pll_dprioin [166] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1366];
+assign \pma_direct|auto_generated|edge_pll_dprioin [167] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1367];
+assign \pma_direct|auto_generated|edge_pll_dprioin [168] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1368];
+assign \pma_direct|auto_generated|edge_pll_dprioin [169] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1369];
+assign \pma_direct|auto_generated|edge_pll_dprioin [170] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1370];
+assign \pma_direct|auto_generated|edge_pll_dprioin [171] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1371];
+assign \pma_direct|auto_generated|edge_pll_dprioin [172] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1372];
+assign \pma_direct|auto_generated|edge_pll_dprioin [173] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1373];
+assign \pma_direct|auto_generated|edge_pll_dprioin [174] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1374];
+assign \pma_direct|auto_generated|edge_pll_dprioin [175] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1375];
+assign \pma_direct|auto_generated|edge_pll_dprioin [176] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1376];
+assign \pma_direct|auto_generated|edge_pll_dprioin [177] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1377];
+assign \pma_direct|auto_generated|edge_pll_dprioin [178] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1378];
+assign \pma_direct|auto_generated|edge_pll_dprioin [179] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1379];
+assign \pma_direct|auto_generated|edge_pll_dprioin [180] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1380];
+assign \pma_direct|auto_generated|edge_pll_dprioin [181] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1381];
+assign \pma_direct|auto_generated|edge_pll_dprioin [182] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1382];
+assign \pma_direct|auto_generated|edge_pll_dprioin [183] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1383];
+assign \pma_direct|auto_generated|edge_pll_dprioin [184] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1384];
+assign \pma_direct|auto_generated|edge_pll_dprioin [185] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1385];
+assign \pma_direct|auto_generated|edge_pll_dprioin [186] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1386];
+assign \pma_direct|auto_generated|edge_pll_dprioin [187] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1387];
+assign \pma_direct|auto_generated|edge_pll_dprioin [188] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1388];
+assign \pma_direct|auto_generated|edge_pll_dprioin [189] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1389];
+assign \pma_direct|auto_generated|edge_pll_dprioin [190] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1390];
+assign \pma_direct|auto_generated|edge_pll_dprioin [191] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1391];
+assign \pma_direct|auto_generated|edge_pll_dprioin [192] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1392];
+assign \pma_direct|auto_generated|edge_pll_dprioin [193] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1393];
+assign \pma_direct|auto_generated|edge_pll_dprioin [194] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1394];
+assign \pma_direct|auto_generated|edge_pll_dprioin [195] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1395];
+assign \pma_direct|auto_generated|edge_pll_dprioin [196] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1396];
+assign \pma_direct|auto_generated|edge_pll_dprioin [197] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1397];
+assign \pma_direct|auto_generated|edge_pll_dprioin [198] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1398];
+assign \pma_direct|auto_generated|edge_pll_dprioin [199] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1399];
+assign \pma_direct|auto_generated|edge_pll_dprioin [200] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1400];
+assign \pma_direct|auto_generated|edge_pll_dprioin [201] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1401];
+assign \pma_direct|auto_generated|edge_pll_dprioin [202] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1402];
+assign \pma_direct|auto_generated|edge_pll_dprioin [203] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1403];
+assign \pma_direct|auto_generated|edge_pll_dprioin [204] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1404];
+assign \pma_direct|auto_generated|edge_pll_dprioin [205] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1405];
+assign \pma_direct|auto_generated|edge_pll_dprioin [206] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1406];
+assign \pma_direct|auto_generated|edge_pll_dprioin [207] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1407];
+assign \pma_direct|auto_generated|edge_pll_dprioin [208] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1408];
+assign \pma_direct|auto_generated|edge_pll_dprioin [209] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1409];
+assign \pma_direct|auto_generated|edge_pll_dprioin [210] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1410];
+assign \pma_direct|auto_generated|edge_pll_dprioin [211] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1411];
+assign \pma_direct|auto_generated|edge_pll_dprioin [212] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1412];
+assign \pma_direct|auto_generated|edge_pll_dprioin [213] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1413];
+assign \pma_direct|auto_generated|edge_pll_dprioin [214] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1414];
+assign \pma_direct|auto_generated|edge_pll_dprioin [215] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1415];
+assign \pma_direct|auto_generated|edge_pll_dprioin [216] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1416];
+assign \pma_direct|auto_generated|edge_pll_dprioin [217] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1417];
+assign \pma_direct|auto_generated|edge_pll_dprioin [218] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1418];
+assign \pma_direct|auto_generated|edge_pll_dprioin [219] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1419];
+assign \pma_direct|auto_generated|edge_pll_dprioin [220] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1420];
+assign \pma_direct|auto_generated|edge_pll_dprioin [221] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1421];
+assign \pma_direct|auto_generated|edge_pll_dprioin [222] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1422];
+assign \pma_direct|auto_generated|edge_pll_dprioin [223] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1423];
+assign \pma_direct|auto_generated|edge_pll_dprioin [224] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1424];
+assign \pma_direct|auto_generated|edge_pll_dprioin [225] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1425];
+assign \pma_direct|auto_generated|edge_pll_dprioin [226] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1426];
+assign \pma_direct|auto_generated|edge_pll_dprioin [227] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1427];
+assign \pma_direct|auto_generated|edge_pll_dprioin [228] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1428];
+assign \pma_direct|auto_generated|edge_pll_dprioin [229] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1429];
+assign \pma_direct|auto_generated|edge_pll_dprioin [230] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1430];
+assign \pma_direct|auto_generated|edge_pll_dprioin [231] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1431];
+assign \pma_direct|auto_generated|edge_pll_dprioin [232] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1432];
+assign \pma_direct|auto_generated|edge_pll_dprioin [233] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1433];
+assign \pma_direct|auto_generated|edge_pll_dprioin [234] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1434];
+assign \pma_direct|auto_generated|edge_pll_dprioin [235] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1435];
+assign \pma_direct|auto_generated|edge_pll_dprioin [236] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1436];
+assign \pma_direct|auto_generated|edge_pll_dprioin [237] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1437];
+assign \pma_direct|auto_generated|edge_pll_dprioin [238] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1438];
+assign \pma_direct|auto_generated|edge_pll_dprioin [239] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1439];
+assign \pma_direct|auto_generated|edge_pll_dprioin [240] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1440];
+assign \pma_direct|auto_generated|edge_pll_dprioin [241] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1441];
+assign \pma_direct|auto_generated|edge_pll_dprioin [242] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1442];
+assign \pma_direct|auto_generated|edge_pll_dprioin [243] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1443];
+assign \pma_direct|auto_generated|edge_pll_dprioin [244] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1444];
+assign \pma_direct|auto_generated|edge_pll_dprioin [245] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1445];
+assign \pma_direct|auto_generated|edge_pll_dprioin [246] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1446];
+assign \pma_direct|auto_generated|edge_pll_dprioin [247] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1447];
+assign \pma_direct|auto_generated|edge_pll_dprioin [248] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1448];
+assign \pma_direct|auto_generated|edge_pll_dprioin [249] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1449];
+assign \pma_direct|auto_generated|edge_pll_dprioin [250] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1450];
+assign \pma_direct|auto_generated|edge_pll_dprioin [251] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1451];
+assign \pma_direct|auto_generated|edge_pll_dprioin [252] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1452];
+assign \pma_direct|auto_generated|edge_pll_dprioin [253] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1453];
+assign \pma_direct|auto_generated|edge_pll_dprioin [254] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1454];
+assign \pma_direct|auto_generated|edge_pll_dprioin [255] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1455];
+assign \pma_direct|auto_generated|edge_pll_dprioin [256] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1456];
+assign \pma_direct|auto_generated|edge_pll_dprioin [257] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1457];
+assign \pma_direct|auto_generated|edge_pll_dprioin [258] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1458];
+assign \pma_direct|auto_generated|edge_pll_dprioin [259] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1459];
+assign \pma_direct|auto_generated|edge_pll_dprioin [260] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1460];
+assign \pma_direct|auto_generated|edge_pll_dprioin [261] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1461];
+assign \pma_direct|auto_generated|edge_pll_dprioin [262] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1462];
+assign \pma_direct|auto_generated|edge_pll_dprioin [263] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1463];
+assign \pma_direct|auto_generated|edge_pll_dprioin [264] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1464];
+assign \pma_direct|auto_generated|edge_pll_dprioin [265] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1465];
+assign \pma_direct|auto_generated|edge_pll_dprioin [266] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1466];
+assign \pma_direct|auto_generated|edge_pll_dprioin [267] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1467];
+assign \pma_direct|auto_generated|edge_pll_dprioin [268] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1468];
+assign \pma_direct|auto_generated|edge_pll_dprioin [269] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1469];
+assign \pma_direct|auto_generated|edge_pll_dprioin [270] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1470];
+assign \pma_direct|auto_generated|edge_pll_dprioin [271] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1471];
+assign \pma_direct|auto_generated|edge_pll_dprioin [272] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1472];
+assign \pma_direct|auto_generated|edge_pll_dprioin [273] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1473];
+assign \pma_direct|auto_generated|edge_pll_dprioin [274] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1474];
+assign \pma_direct|auto_generated|edge_pll_dprioin [275] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1475];
+assign \pma_direct|auto_generated|edge_pll_dprioin [276] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1476];
+assign \pma_direct|auto_generated|edge_pll_dprioin [277] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1477];
+assign \pma_direct|auto_generated|edge_pll_dprioin [278] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1478];
+assign \pma_direct|auto_generated|edge_pll_dprioin [279] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1479];
+assign \pma_direct|auto_generated|edge_pll_dprioin [280] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1480];
+assign \pma_direct|auto_generated|edge_pll_dprioin [281] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1481];
+assign \pma_direct|auto_generated|edge_pll_dprioin [282] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1482];
+assign \pma_direct|auto_generated|edge_pll_dprioin [283] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1483];
+assign \pma_direct|auto_generated|edge_pll_dprioin [284] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1484];
+assign \pma_direct|auto_generated|edge_pll_dprioin [285] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1485];
+assign \pma_direct|auto_generated|edge_pll_dprioin [286] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1486];
+assign \pma_direct|auto_generated|edge_pll_dprioin [287] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1487];
+assign \pma_direct|auto_generated|edge_pll_dprioin [288] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1488];
+assign \pma_direct|auto_generated|edge_pll_dprioin [289] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1489];
+assign \pma_direct|auto_generated|edge_pll_dprioin [290] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1490];
+assign \pma_direct|auto_generated|edge_pll_dprioin [291] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1491];
+assign \pma_direct|auto_generated|edge_pll_dprioin [292] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1492];
+assign \pma_direct|auto_generated|edge_pll_dprioin [293] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1493];
+assign \pma_direct|auto_generated|edge_pll_dprioin [294] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1494];
+assign \pma_direct|auto_generated|edge_pll_dprioin [295] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1495];
+assign \pma_direct|auto_generated|edge_pll_dprioin [296] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1496];
+assign \pma_direct|auto_generated|edge_pll_dprioin [297] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1497];
+assign \pma_direct|auto_generated|edge_pll_dprioin [298] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1498];
+assign \pma_direct|auto_generated|edge_pll_dprioin [299] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus [1499];
+
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [0] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [400];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [1] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [401];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [2] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [402];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [3] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [403];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [4] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [404];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [5] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [405];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [6] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [406];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [7] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [407];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [8] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [408];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [9] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [409];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [10] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [410];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [11] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [411];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [12] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [412];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [13] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [413];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [14] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [414];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [15] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [415];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [16] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [416];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [17] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [417];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [18] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [418];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [19] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [419];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [20] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [420];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [21] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [421];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [22] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [422];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [23] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [423];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [24] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [424];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [25] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [425];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [26] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [426];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [27] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [427];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [28] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [428];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [29] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [429];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [30] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [430];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [31] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [431];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [32] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [432];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [33] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [433];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [34] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [434];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [35] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [435];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [36] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [436];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [37] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [437];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [38] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [438];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [39] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [439];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [40] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [440];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [41] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [441];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [42] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [442];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [43] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [443];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [44] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [444];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [45] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [445];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [46] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [446];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [47] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [447];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [48] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [448];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [49] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [449];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [50] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [450];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [51] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [451];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [52] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [452];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [53] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [453];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [54] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [454];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [55] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [455];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [56] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [456];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [57] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [457];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [58] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [458];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [59] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [459];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [60] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [460];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [61] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [461];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [62] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [462];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [63] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [463];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [64] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [464];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [65] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [465];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [66] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [466];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [67] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [467];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [68] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [468];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [69] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [469];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [70] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [470];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [71] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [471];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [72] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [472];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [73] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [473];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [74] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [474];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [75] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [475];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [76] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [476];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [77] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [477];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [78] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [478];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [79] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [479];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [80] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [480];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [81] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [481];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [82] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [482];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [83] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [483];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [84] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [484];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [85] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [485];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [86] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [486];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [87] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [487];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [88] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [488];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [89] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [489];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [90] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [490];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [91] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [491];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [92] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [492];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [93] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [493];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [94] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [494];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [95] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [495];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [96] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [496];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [97] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [497];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [98] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [498];
+assign \pma_direct|auto_generated|edge_cmu_cmudividerdprioout [99] = \pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus [499];
+
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT0 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [0];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT2 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [2];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT3 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [3];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT4 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [4];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT5 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [5];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT6 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [6];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT7 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [7];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT8 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [8];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT9 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [9];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT10 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [10];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT11 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [11];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT12 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [12];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT13 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [13];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT14 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [14];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT15 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [15];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT16 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [16];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT17 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [17];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT18 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [18];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT19 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [19];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT20 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [20];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT21 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [21];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT22 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [22];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT23 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [23];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT24 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [24];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT25 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [25];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT26 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [26];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT27 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [27];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT28 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [28];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT29 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [29];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT30 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [30];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT31 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [31];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT32 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [32];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT33 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [33];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT34 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [34];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT35 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [35];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT36 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [36];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT37 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [37];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT38 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [38];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT39 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [39];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT40 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [40];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT41 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [41];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT42 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [42];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT43 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [43];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT44 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [44];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT45 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [45];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT46 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [46];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT47 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [47];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT48 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [48];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT49 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [49];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT50 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [50];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT51 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [51];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT52 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [52];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT53 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [53];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT54 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [54];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT55 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [55];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT56 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [56];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT57 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [57];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT58 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [58];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT59 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [59];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT60 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [60];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT61 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [61];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT62 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [62];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT63 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [63];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT64 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [64];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT65 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [65];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT66 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [66];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT67 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [67];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT68 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [68];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT69 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [69];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT70 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [70];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT71 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [71];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT72 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [72];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT73 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [73];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT74 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [74];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT75 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [75];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT76 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [76];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT77 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [77];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT78 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [78];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT79 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [79];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT80 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [80];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT81 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [81];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT82 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [82];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT83 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [83];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT84 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [84];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT85 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [85];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT86 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [86];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT87 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [87];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT88 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [88];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT89 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [89];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT90 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [90];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT91 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [91];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT92 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [92];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT93 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [93];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT94 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [94];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT95 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [95];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT96 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [96];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT97 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [97];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT98 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [98];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT99 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [99];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT100 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [100];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT101 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [101];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT102 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [102];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT103 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [103];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT104 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [104];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT105 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [105];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT106 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [106];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT107 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [107];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT108 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [108];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT109 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [109];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT110 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [110];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT111 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [111];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT112 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [112];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT113 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [113];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT114 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [114];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT115 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [115];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT116 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [116];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT117 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [117];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT118 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [118];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT119 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [119];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT120 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [120];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT121 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [121];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT122 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [122];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT123 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [123];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT124 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [124];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT125 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [125];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT126 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [126];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT127 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [127];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT128 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [128];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT129 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [129];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT130 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [130];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT131 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [131];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT132 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [132];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT133 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [133];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT134 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [134];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT135 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [135];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT136 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [136];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT137 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [137];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT138 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [138];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT139 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [139];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT140 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [140];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT141 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [141];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT142 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [142];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT143 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [143];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT144 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [144];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT145 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [145];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT146 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [146];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT147 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [147];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT148 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [148];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT149 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [149];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT150 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [150];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT151 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [151];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT152 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [152];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT153 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [153];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT154 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [154];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT155 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [155];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT156 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [156];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT157 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [157];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT158 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [158];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT159 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [159];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT160 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [160];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT161 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [161];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT162 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [162];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT163 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [163];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT164 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [164];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT165 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [165];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT166 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [166];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT167 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [167];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT168 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [168];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT169 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [169];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT170 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [170];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT171 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [171];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT172 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [172];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT173 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [173];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT174 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [174];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT175 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [175];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT176 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [176];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT177 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [177];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT178 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [178];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT179 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [179];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT180 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [180];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT181 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [181];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT182 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [182];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT183 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [183];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT184 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [184];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT185 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [185];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT186 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [186];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT187 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [187];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT188 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [188];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT189 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [189];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT190 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [190];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT191 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [191];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT192 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [192];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT193 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [193];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT194 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [194];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT195 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [195];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT196 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [196];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT197 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [197];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT198 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [198];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT199 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [199];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT200 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [200];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT201 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [201];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT202 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [202];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT203 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [203];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT204 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [204];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT205 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [205];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT206 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [206];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT207 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [207];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT208 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [208];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT209 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [209];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT210 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [210];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT211 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [211];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT212 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [212];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT213 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [213];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT214 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [214];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT215 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [215];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT216 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [216];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT217 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [217];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT218 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [218];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT219 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [219];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT220 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [220];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT221 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [221];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT222 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [222];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT223 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [223];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT224 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [224];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT225 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [225];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT226 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [226];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT227 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [227];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT228 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [228];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT229 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [229];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT230 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [230];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT231 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [231];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT232 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [232];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT233 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [233];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT234 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [234];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT235 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [235];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT236 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [236];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT237 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [237];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT238 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [238];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT239 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [239];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT240 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [240];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT241 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [241];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT242 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [242];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT243 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [243];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT244 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [244];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT245 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [245];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT246 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [246];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT247 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [247];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT248 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [248];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT249 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [249];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT250 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [250];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT251 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [251];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT252 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [252];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT253 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [253];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT254 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [254];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT255 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [255];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT256 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [256];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT257 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [257];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT258 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [258];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT259 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [259];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT260 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [260];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT261 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [261];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT262 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [262];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT263 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [263];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT264 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [264];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT265 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [265];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT266 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [266];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT267 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [267];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT268 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [268];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT269 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [269];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT270 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [270];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT271 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [271];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT272 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [272];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT273 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [273];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT274 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [274];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT275 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [275];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT276 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [276];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT277 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [277];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT278 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [278];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT279 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [279];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT280 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [280];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT281 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [281];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT282 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [282];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT283 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [283];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT284 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [284];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT285 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [285];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT286 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [286];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT287 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [287];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT288 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [288];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT289 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [289];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT290 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [290];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT291 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [291];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT292 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [292];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT293 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [293];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT294 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [294];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT295 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [295];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT296 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [296];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT297 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [297];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT298 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [298];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT299 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [299];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT300 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [300];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT301 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [301];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT302 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [302];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT303 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [303];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT304 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [304];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT305 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [305];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT306 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [306];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT307 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [307];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT308 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [308];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT309 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [309];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT310 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [310];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT311 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [311];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT312 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [312];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT313 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [313];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT314 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [314];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT315 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [315];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT316 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [316];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT317 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [317];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT318 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [318];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT319 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [319];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT320 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [320];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT321 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [321];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT322 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [322];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT323 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [323];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT324 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [324];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT325 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [325];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT326 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [326];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT327 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [327];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT328 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [328];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT329 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [329];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT330 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [330];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT331 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [331];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT332 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [332];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT333 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [333];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT334 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [334];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT335 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [335];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT336 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [336];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT337 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [337];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT338 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [338];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT339 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [339];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT340 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [340];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT341 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [341];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT342 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [342];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT343 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [343];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT344 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [344];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT345 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [345];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT346 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [346];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT347 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [347];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT348 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [348];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT349 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [349];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT350 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [350];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT351 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [351];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT352 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [352];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT353 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [353];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT354 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [354];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT355 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [355];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT356 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [356];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT357 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [357];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT358 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [358];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT359 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [359];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT360 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [360];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT361 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [361];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT362 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [362];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT363 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [363];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT364 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [364];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT365 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [365];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT366 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [366];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT367 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [367];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT368 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [368];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT369 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [369];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT370 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [370];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT371 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [371];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT372 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [372];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT373 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [373];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT374 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [374];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT375 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [375];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT376 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [376];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT377 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [377];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT378 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [378];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT379 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [379];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT380 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [380];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT381 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [381];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT382 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [382];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT383 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [383];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT384 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [384];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT385 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [385];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT386 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [386];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT387 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [387];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT388 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [388];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT389 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [389];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT390 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [390];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT391 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [391];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT392 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [392];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT393 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [393];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT394 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [394];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT395 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [395];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT396 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [396];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT397 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [397];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT398 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [398];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT399 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [399];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT400 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [400];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT401 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [401];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT402 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [402];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT403 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [403];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT404 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [404];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT405 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [405];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT406 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [406];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT407 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [407];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT408 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [408];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT409 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [409];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT410 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [410];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT411 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [411];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT412 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [412];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT413 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [413];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT414 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [414];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT415 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [415];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT416 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [416];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT417 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [417];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT418 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [418];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT419 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [419];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT420 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [420];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT421 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [421];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT422 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [422];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT423 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [423];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT424 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [424];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT425 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [425];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT426 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [426];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT427 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [427];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT428 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [428];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT429 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [429];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT430 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [430];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT431 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [431];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT432 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [432];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT433 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [433];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT434 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [434];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT435 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [435];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT436 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [436];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT437 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [437];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT438 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [438];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT439 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [439];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT440 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [440];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT441 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [441];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT442 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [442];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT443 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [443];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT444 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [444];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT445 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [445];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT446 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [446];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT447 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [447];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT448 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [448];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT449 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [449];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT450 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [450];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT451 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [451];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT452 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [452];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT453 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [453];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT454 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [454];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT455 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [455];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT456 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [456];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT457 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [457];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT458 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [458];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT459 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [459];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT460 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [460];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT461 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [461];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT462 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [462];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT463 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [463];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT464 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [464];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT465 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [465];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT466 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [466];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT467 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [467];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT468 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [468];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT469 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [469];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT470 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [470];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT471 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [471];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT472 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [472];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT473 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [473];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT474 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [474];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT475 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [475];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT476 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [476];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT477 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [477];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT478 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [478];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT479 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [479];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT480 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [480];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT481 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [481];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT482 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [482];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT483 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [483];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT484 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [484];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT485 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [485];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT486 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [486];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT487 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [487];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT488 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [488];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT489 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [489];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT490 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [490];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT491 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [491];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT492 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [492];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT493 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [493];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT494 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [494];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT495 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [495];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT496 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [496];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT497 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [497];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT498 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [498];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT499 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [499];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT500 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [500];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT501 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [501];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT502 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [502];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT503 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [503];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT504 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [504];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT505 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [505];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT506 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [506];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT507 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [507];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT508 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [508];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT509 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [509];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT510 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [510];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT511 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [511];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT512 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [512];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT513 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [513];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT514 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [514];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT515 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [515];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT516 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [516];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT517 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [517];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT518 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [518];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT519 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [519];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT520 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [520];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT521 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [521];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT522 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [522];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT523 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [523];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT524 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [524];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT525 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [525];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT526 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [526];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT527 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [527];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT528 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [528];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT529 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [529];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT530 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [530];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT531 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [531];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT532 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [532];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT533 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [533];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT534 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [534];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT535 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [535];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT536 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [536];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT537 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [537];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT538 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [538];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT539 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [539];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT540 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [540];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT541 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [541];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT542 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [542];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT543 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [543];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT544 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [544];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT545 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [545];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT546 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [546];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT547 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [547];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT548 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [548];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT549 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [549];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT550 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [550];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT551 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [551];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT552 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [552];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT553 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [553];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT554 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [554];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT555 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [555];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT556 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [556];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT557 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [557];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT558 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [558];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT559 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [559];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT560 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [560];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT561 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [561];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT562 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [562];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT563 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [563];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT564 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [564];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT565 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [565];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT566 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [566];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT567 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [567];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT568 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [568];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT569 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [569];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT570 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [570];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT571 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [571];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT572 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [572];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT573 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [573];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT574 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [574];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT575 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [575];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT576 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [576];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT577 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [577];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT578 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [578];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT579 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [579];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT580 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [580];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT581 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [581];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT582 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [582];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT583 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [583];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT584 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [584];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT585 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [585];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT586 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [586];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT587 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [587];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT588 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [588];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT589 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [589];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT590 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [590];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT591 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [591];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT592 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [592];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT593 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [593];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT594 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [594];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT595 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [595];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT596 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [596];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT597 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [597];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT598 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [598];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT599 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [599];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT600 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [600];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT601 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [601];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT602 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [602];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT603 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [603];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT604 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [604];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT605 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [605];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT606 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [606];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT607 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [607];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT608 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [608];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT609 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [609];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT610 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [610];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT611 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [611];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT612 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [612];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT613 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [613];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT614 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [614];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT615 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [615];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT616 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [616];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT617 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [617];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT618 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [618];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT619 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [619];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT620 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [620];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT621 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [621];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT622 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [622];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT623 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [623];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT624 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [624];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT625 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [625];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT626 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [626];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT627 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [627];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT628 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [628];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT629 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [629];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT630 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [630];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT631 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [631];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT632 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [632];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT633 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [633];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT634 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [634];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT635 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [635];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT636 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [636];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT637 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [637];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT638 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [638];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT639 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [639];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT640 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [640];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT641 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [641];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT642 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [642];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT643 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [643];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT644 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [644];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT645 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [645];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT646 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [646];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT647 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [647];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT648 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [648];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT649 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [649];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT650 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [650];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT651 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [651];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT652 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [652];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT653 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [653];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT654 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [654];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT655 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [655];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT656 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [656];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT657 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [657];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT658 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [658];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT659 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [659];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT660 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [660];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT661 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [661];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT662 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [662];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT663 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [663];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT664 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [664];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT665 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [665];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT666 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [666];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT667 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [667];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT668 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [668];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT669 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [669];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT670 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [670];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT671 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [671];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT672 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [672];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT673 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [673];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT674 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [674];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT675 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [675];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT676 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [676];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT677 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [677];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT678 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [678];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT679 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [679];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT680 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [680];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT681 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [681];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT682 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [682];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT683 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [683];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT684 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [684];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT685 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [685];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT686 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [686];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT687 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [687];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT688 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [688];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT689 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [689];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT690 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [690];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT691 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [691];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT692 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [692];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT693 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [693];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT694 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [694];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT695 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [695];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT696 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [696];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT697 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [697];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT698 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [698];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT699 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [699];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT700 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [700];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT701 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [701];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT702 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [702];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT703 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [703];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT704 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [704];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT705 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [705];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT706 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [706];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT707 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [707];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT708 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [708];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT709 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [709];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT710 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [710];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT711 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [711];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT712 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [712];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT713 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [713];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT714 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [714];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT715 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [715];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT716 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [716];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT717 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [717];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT718 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [718];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT719 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [719];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT720 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [720];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT721 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [721];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT722 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [722];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT723 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [723];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT724 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [724];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT725 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [725];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT726 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [726];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT727 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [727];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT728 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [728];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT729 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [729];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT730 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [730];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT731 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [731];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT732 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [732];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT733 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [733];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT734 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [734];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT735 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [735];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT736 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [736];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT737 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [737];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT738 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [738];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT739 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [739];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT740 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [740];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT741 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [741];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT742 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [742];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT743 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [743];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT744 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [744];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT745 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [745];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT746 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [746];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT747 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [747];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT748 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [748];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT749 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [749];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT750 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [750];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT751 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [751];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT752 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [752];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT753 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [753];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT754 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [754];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT755 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [755];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT756 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [756];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT757 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [757];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT758 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [758];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT759 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [759];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT760 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [760];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT761 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [761];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT762 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [762];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT763 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [763];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT764 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [764];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT765 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [765];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT766 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [766];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT767 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [767];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT768 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [768];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT769 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [769];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT770 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [770];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT771 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [771];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT772 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [772];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT773 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [773];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT774 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [774];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT775 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [775];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT776 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [776];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT777 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [777];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT778 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [778];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT779 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [779];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT780 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [780];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT781 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [781];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT782 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [782];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT783 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [783];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT784 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [784];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT785 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [785];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT786 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [786];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT787 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [787];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT788 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [788];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT789 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [789];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT790 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [790];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT791 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [791];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT792 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [792];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT793 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [793];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT794 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [794];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT795 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [795];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT796 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [796];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT797 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [797];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT798 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [798];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT799 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [799];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT800 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [800];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT801 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [801];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT802 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [802];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT803 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [803];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT804 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [804];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT805 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [805];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT806 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [806];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT807 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [807];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT808 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [808];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT809 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [809];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT810 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [810];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT811 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [811];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT812 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [812];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT813 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [813];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT814 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [814];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT815 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [815];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT816 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [816];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT817 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [817];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT818 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [818];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT819 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [819];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT820 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [820];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT821 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [821];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT822 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [822];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT823 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [823];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT824 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [824];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT825 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [825];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT826 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [826];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT827 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [827];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT828 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [828];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT829 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [829];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT830 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [830];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT831 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [831];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT832 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [832];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT833 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [833];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT834 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [834];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT835 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [835];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT836 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [836];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT837 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [837];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT838 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [838];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT839 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [839];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT840 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [840];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT841 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [841];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT842 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [842];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT843 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [843];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT844 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [844];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT845 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [845];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT846 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [846];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT847 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [847];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT848 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [848];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT849 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [849];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT850 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [850];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT851 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [851];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT852 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [852];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT853 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [853];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT854 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [854];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT855 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [855];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT856 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [856];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT857 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [857];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT858 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [858];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT859 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [859];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT860 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [860];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT861 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [861];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT862 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [862];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT863 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [863];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT864 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [864];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT865 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [865];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT866 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [866];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT867 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [867];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT868 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [868];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT869 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [869];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT870 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [870];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT871 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [871];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT872 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [872];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT873 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [873];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT874 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [874];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT875 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [875];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT876 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [876];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT877 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [877];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT878 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [878];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT879 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [879];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT880 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [880];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT881 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [881];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT882 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [882];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT883 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [883];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT884 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [884];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT885 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [885];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT886 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [886];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT887 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [887];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT888 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [888];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT889 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [889];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT890 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [890];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT891 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [891];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT892 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [892];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT893 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [893];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT894 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [894];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT895 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [895];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT896 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [896];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT897 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [897];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT898 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [898];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT899 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [899];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT900 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [900];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT901 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [901];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT902 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [902];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT903 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [903];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT904 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [904];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT905 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [905];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT906 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [906];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT907 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [907];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT908 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [908];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT909 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [909];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT910 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [910];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT911 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [911];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT912 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [912];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT913 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [913];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT914 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [914];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT915 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [915];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT916 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [916];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT917 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [917];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT918 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [918];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT919 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [919];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT920 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [920];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT921 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [921];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT922 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [922];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT923 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [923];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT924 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [924];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT925 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [925];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT926 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [926];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT927 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [927];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT928 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [928];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT929 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [929];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT930 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [930];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT931 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [931];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT932 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [932];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT933 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [933];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT934 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [934];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT935 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [935];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT936 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [936];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT937 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [937];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT938 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [938];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT939 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [939];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT940 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [940];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT941 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [941];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT942 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [942];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT943 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [943];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT944 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [944];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT945 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [945];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT946 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [946];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT947 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [947];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT948 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [948];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT949 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [949];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT950 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [950];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT951 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [951];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT952 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [952];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT953 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [953];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT954 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [954];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT955 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [955];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT956 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [956];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT957 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [957];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT958 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [958];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT959 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [959];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT960 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [960];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT961 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [961];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT962 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [962];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT963 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [963];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT964 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [964];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT965 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [965];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT966 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [966];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT967 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [967];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT968 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [968];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT969 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [969];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT970 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [970];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT971 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [971];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT972 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [972];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT973 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [973];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT974 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [974];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT975 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [975];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT976 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [976];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT977 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [977];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT978 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [978];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT979 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [979];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT980 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [980];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT981 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [981];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT982 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [982];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT983 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [983];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT984 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [984];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT985 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [985];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT986 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [986];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT987 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [987];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT988 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [988];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT989 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [989];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT990 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [990];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT991 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [991];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT992 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [992];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT993 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [993];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT994 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [994];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT995 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [995];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT996 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [996];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT997 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [997];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT998 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [998];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT999 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [999];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1000 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1000];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1001 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1001];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1002 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1002];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1003 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1003];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1004 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1004];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1005 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1005];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1006 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1006];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1007 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1007];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1008 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1008];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1009 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1009];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1010 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1010];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1011 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1011];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1012 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1012];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1013 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1013];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1014 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1014];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1015 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1015];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1016 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1016];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1017 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1017];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1018 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1018];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1019 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1019];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1020 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1020];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1021 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1021];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1022 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1022];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1023 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1023];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1024 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1024];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1025 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1025];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1026 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1026];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1027 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1027];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1028 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1028];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1029 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1029];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1030 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1030];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1031 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1031];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1032 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1032];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1033 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1033];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1034 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1034];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1035 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1035];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1036 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1036];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1037 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1037];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1038 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1038];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1039 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1039];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1040 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1040];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1041 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1041];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1042 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1042];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1043 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1043];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1044 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1044];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1045 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1045];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1046 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1046];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1047 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1047];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1048 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1048];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1049 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1049];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1050 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1050];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1051 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1051];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1052 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1052];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1053 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1053];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1054 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1054];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1055 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1055];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1056 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1056];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1057 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1057];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1058 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1058];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1059 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1059];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1060 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1060];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1061 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1061];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1062 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1062];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1063 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1063];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1064 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1064];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1065 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1065];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1066 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1066];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1067 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1067];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1068 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1068];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1069 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1069];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1070 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1070];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1071 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1071];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1072 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1072];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1073 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1073];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1074 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1074];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1075 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1075];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1076 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1076];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1077 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1077];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1078 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1078];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1079 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1079];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1080 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1080];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1081 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1081];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1082 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1082];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1083 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1083];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1084 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1084];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1085 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1085];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1086 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1086];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1087 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1087];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1088 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1088];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1089 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1089];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1090 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1090];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1091 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1091];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1092 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1092];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1093 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1093];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1094 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1094];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1095 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1095];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1096 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1096];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1097 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1097];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1098 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1098];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1099 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1099];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1100 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1100];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1101 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1101];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1102 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1102];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1103 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1103];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1104 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1104];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1105 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1105];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1106 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1106];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1107 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1107];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1108 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1108];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1109 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1109];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1110 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1110];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1111 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1111];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1112 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1112];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1113 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1113];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1114 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1114];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1115 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1115];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1116 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1116];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1117 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1117];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1118 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1118];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1119 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1119];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1120 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1120];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1121 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1121];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1122 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1122];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1123 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1123];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1124 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1124];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1125 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1125];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1126 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1126];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1127 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1127];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1128 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1128];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1129 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1129];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1130 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1130];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1131 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1131];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1132 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1132];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1133 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1133];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1134 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1134];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1135 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1135];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1136 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1136];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1137 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1137];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1138 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1138];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1139 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1139];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1140 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1140];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1141 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1141];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1142 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1142];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1143 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1143];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1144 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1144];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1145 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1145];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1146 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1146];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1147 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1147];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1148 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1148];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1149 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1149];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1150 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1150];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1151 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1151];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1152 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1152];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1153 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1153];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1154 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1154];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1155 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1155];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1156 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1156];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1157 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1157];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1158 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1158];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1159 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1159];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1160 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1160];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1161 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1161];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1162 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1162];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1163 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1163];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1164 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1164];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1165 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1165];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1166 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1166];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1167 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1167];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1168 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1168];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1169 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1169];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1170 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1170];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1171 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1171];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1172 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1172];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1173 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1173];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1174 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1174];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1175 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1175];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1176 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1176];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1177 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1177];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1178 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1178];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1179 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1179];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1180 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1180];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1181 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1181];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1182 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1182];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1183 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1183];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1184 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1184];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1185 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1185];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1186 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1186];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1187 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1187];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1188 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1188];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1189 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1189];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1190 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1190];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1191 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1191];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1192 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1192];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1193 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1193];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1194 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1194];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1195 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1195];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1196 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1196];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1197 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1197];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1198 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1198];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1199 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus [1199];
+
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT0 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [0];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT2 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [2];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT3 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [3];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT4 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [4];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT5 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [5];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT6 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [6];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT7 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [7];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT8 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [8];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT9 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [9];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT10 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [10];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT11 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [11];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT12 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [12];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT13 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [13];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT14 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [14];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT15 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [15];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT16 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [16];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT17 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [17];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT18 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [18];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT19 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [19];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT20 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [20];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT21 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [21];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT22 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [22];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT23 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [23];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT24 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [24];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT25 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [25];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT26 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [26];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT27 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [27];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT28 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [28];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT29 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [29];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT30 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [30];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT31 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [31];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT32 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [32];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT33 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [33];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT34 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [34];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT35 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [35];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT36 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [36];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT37 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [37];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT38 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [38];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT39 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [39];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT40 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [40];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT41 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [41];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT42 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [42];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT43 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [43];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT44 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [44];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT45 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [45];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT46 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [46];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT47 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [47];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT48 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [48];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT49 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [49];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT50 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [50];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT51 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [51];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT52 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [52];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT53 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [53];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT54 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [54];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT55 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [55];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT56 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [56];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT57 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [57];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT58 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [58];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT59 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [59];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT60 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [60];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT61 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [61];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT62 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [62];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT63 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [63];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT64 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [64];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT65 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [65];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT66 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [66];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT67 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [67];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT68 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [68];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT69 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [69];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT70 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [70];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT71 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [71];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT72 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [72];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT73 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [73];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT74 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [74];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT75 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [75];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT76 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [76];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT77 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [77];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT78 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [78];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT79 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [79];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT80 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [80];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT81 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [81];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT82 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [82];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT83 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [83];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT84 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [84];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT85 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [85];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT86 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [86];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT87 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [87];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT88 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [88];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT89 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [89];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT90 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [90];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT91 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [91];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT92 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [92];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT93 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [93];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT94 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [94];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT95 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [95];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT96 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [96];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT97 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [97];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT98 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [98];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT99 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [99];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT100 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [100];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT101 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [101];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT102 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [102];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT103 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [103];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT104 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [104];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT105 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [105];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT106 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [106];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT107 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [107];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT108 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [108];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT109 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [109];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT110 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [110];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT111 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [111];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT112 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [112];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT113 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [113];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT114 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [114];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT115 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [115];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT116 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [116];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT117 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [117];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT118 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [118];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT119 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [119];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT120 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [120];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT121 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [121];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT122 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [122];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT123 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [123];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT124 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [124];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT125 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [125];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT126 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [126];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT127 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [127];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT128 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [128];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT129 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [129];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT130 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [130];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT131 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [131];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT132 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [132];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT133 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [133];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT134 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [134];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT135 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [135];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT136 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [136];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT137 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [137];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT138 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [138];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT139 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [139];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT140 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [140];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT141 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [141];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT142 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [142];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT143 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [143];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT144 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [144];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT145 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [145];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT146 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [146];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT147 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [147];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT148 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [148];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT149 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [149];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT150 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [150];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT151 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [151];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT152 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [152];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT153 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [153];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT154 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [154];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT155 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [155];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT156 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [156];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT157 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [157];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT158 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [158];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT159 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [159];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT160 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [160];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT161 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [161];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT162 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [162];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT163 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [163];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT164 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [164];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT165 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [165];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT166 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [166];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT167 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [167];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT168 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [168];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT169 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [169];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT170 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [170];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT171 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [171];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT172 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [172];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT173 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [173];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT174 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [174];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT175 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [175];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT176 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [176];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT177 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [177];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT178 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [178];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT179 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [179];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT180 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [180];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT181 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [181];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT182 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [182];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT183 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [183];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT184 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [184];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT185 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [185];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT186 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [186];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT187 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [187];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT188 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [188];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT189 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [189];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT190 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [190];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT191 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [191];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT192 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [192];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT193 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [193];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT194 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [194];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT195 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [195];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT196 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [196];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT197 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [197];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT198 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [198];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT199 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [199];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT200 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [200];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT201 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [201];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT202 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [202];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT203 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [203];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT204 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [204];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT205 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [205];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT206 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [206];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT207 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [207];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT208 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [208];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT209 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [209];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT210 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [210];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT211 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [211];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT212 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [212];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT213 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [213];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT214 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [214];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT215 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [215];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT216 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [216];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT217 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [217];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT218 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [218];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT219 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [219];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT220 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [220];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT221 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [221];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT222 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [222];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT223 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [223];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT224 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [224];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT225 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [225];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT226 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [226];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT227 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [227];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT228 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [228];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT229 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [229];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT230 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [230];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT231 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [231];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT232 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [232];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT233 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [233];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT234 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [234];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT235 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [235];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT236 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [236];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT237 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [237];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT238 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [238];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT239 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [239];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT240 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [240];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT241 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [241];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT242 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [242];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT243 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [243];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT244 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [244];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT245 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [245];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT246 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [246];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT247 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [247];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT248 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [248];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT249 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [249];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT250 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [250];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT251 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [251];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT252 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [252];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT253 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [253];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT254 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [254];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT255 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [255];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT256 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [256];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT257 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [257];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT258 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [258];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT259 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [259];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT260 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [260];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT261 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [261];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT262 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [262];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT263 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [263];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT264 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [264];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT265 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [265];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT266 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [266];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT267 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [267];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT268 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [268];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT269 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [269];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT270 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [270];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT271 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [271];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT272 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [272];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT273 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [273];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT274 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [274];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT275 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [275];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT276 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [276];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT277 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [277];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT278 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [278];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT279 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [279];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT280 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [280];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT281 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [281];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT282 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [282];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT283 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [283];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT284 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [284];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT285 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [285];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT286 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [286];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT287 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [287];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT288 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [288];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT289 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [289];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT290 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [290];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT291 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [291];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT292 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [292];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT293 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [293];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT294 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [294];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT295 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [295];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT296 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [296];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT297 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [297];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT298 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [298];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT299 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [299];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT300 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [300];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT301 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [301];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT302 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [302];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT303 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [303];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT304 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [304];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT305 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [305];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT306 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [306];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT307 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [307];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT308 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [308];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT309 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [309];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT310 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [310];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT311 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [311];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT312 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [312];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT313 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [313];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT314 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [314];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT315 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [315];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT316 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [316];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT317 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [317];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT318 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [318];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT319 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [319];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT320 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [320];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT321 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [321];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT322 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [322];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT323 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [323];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT324 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [324];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT325 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [325];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT326 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [326];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT327 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [327];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT328 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [328];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT329 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [329];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT330 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [330];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT331 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [331];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT332 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [332];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT333 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [333];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT334 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [334];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT335 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [335];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT336 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [336];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT337 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [337];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT338 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [338];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT339 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [339];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT340 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [340];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT341 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [341];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT342 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [342];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT343 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [343];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT344 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [344];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT345 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [345];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT346 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [346];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT347 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [347];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT348 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [348];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT349 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [349];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT350 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [350];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT351 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [351];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT352 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [352];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT353 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [353];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT354 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [354];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT355 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [355];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT356 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [356];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT357 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [357];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT358 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [358];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT359 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [359];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT360 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [360];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT361 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [361];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT362 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [362];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT363 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [363];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT364 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [364];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT365 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [365];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT366 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [366];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT367 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [367];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT368 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [368];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT369 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [369];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT370 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [370];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT371 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [371];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT372 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [372];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT373 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [373];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT374 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [374];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT375 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [375];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT376 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [376];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT377 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [377];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT378 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [378];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT379 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [379];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT380 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [380];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT381 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [381];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT382 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [382];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT383 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [383];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT384 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [384];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT385 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [385];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT386 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [386];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT387 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [387];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT388 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [388];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT389 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [389];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT390 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [390];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT391 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [391];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT392 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [392];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT393 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [393];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT394 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [394];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT395 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [395];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT396 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [396];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT397 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [397];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT398 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [398];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT399 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [399];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT400 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [400];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT401 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [401];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT402 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [402];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT403 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [403];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT404 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [404];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT405 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [405];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT406 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [406];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT407 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [407];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT408 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [408];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT409 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [409];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT410 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [410];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT411 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [411];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT412 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [412];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT413 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [413];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT414 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [414];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT415 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [415];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT416 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [416];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT417 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [417];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT418 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [418];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT419 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [419];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT420 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [420];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT421 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [421];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT422 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [422];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT423 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [423];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT424 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [424];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT425 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [425];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT426 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [426];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT427 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [427];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT428 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [428];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT429 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [429];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT430 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [430];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT431 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [431];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT432 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [432];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT433 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [433];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT434 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [434];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT435 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [435];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT436 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [436];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT437 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [437];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT438 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [438];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT439 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [439];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT440 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [440];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT441 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [441];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT442 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [442];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT443 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [443];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT444 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [444];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT445 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [445];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT446 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [446];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT447 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [447];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT448 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [448];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT449 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [449];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT450 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [450];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT451 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [451];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT452 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [452];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT453 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [453];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT454 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [454];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT455 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [455];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT456 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [456];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT457 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [457];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT458 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [458];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT459 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [459];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT460 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [460];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT461 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [461];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT462 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [462];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT463 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [463];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT464 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [464];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT465 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [465];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT466 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [466];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT467 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [467];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT468 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [468];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT469 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [469];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT470 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [470];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT471 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [471];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT472 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [472];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT473 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [473];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT474 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [474];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT475 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [475];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT476 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [476];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT477 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [477];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT478 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [478];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT479 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [479];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT480 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [480];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT481 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [481];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT482 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [482];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT483 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [483];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT484 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [484];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT485 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [485];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT486 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [486];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT487 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [487];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT488 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [488];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT489 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [489];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT490 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [490];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT491 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [491];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT492 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [492];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT493 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [493];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT494 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [494];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT495 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [495];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT496 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [496];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT497 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [497];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT498 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [498];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT499 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [499];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT500 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [500];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT501 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [501];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT502 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [502];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT503 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [503];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT504 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [504];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT505 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [505];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT506 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [506];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT507 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [507];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT508 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [508];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT509 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [509];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT510 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [510];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT511 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [511];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT512 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [512];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT513 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [513];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT514 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [514];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT515 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [515];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT516 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [516];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT517 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [517];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT518 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [518];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT519 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [519];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT520 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [520];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT521 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [521];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT522 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [522];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT523 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [523];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT524 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [524];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT525 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [525];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT526 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [526];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT527 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [527];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT528 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [528];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT529 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [529];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT530 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [530];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT531 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [531];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT532 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [532];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT533 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [533];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT534 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [534];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT535 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [535];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT536 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [536];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT537 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [537];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT538 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [538];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT539 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [539];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT540 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [540];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT541 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [541];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT542 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [542];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT543 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [543];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT544 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [544];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT545 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [545];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT546 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [546];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT547 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [547];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT548 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [548];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT549 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [549];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT550 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [550];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT551 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [551];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT552 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [552];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT553 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [553];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT554 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [554];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT555 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [555];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT556 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [556];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT557 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [557];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT558 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [558];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT559 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [559];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT560 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [560];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT561 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [561];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT562 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [562];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT563 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [563];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT564 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [564];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT565 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [565];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT566 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [566];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT567 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [567];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT568 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [568];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT569 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [569];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT570 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [570];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT571 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [571];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT572 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [572];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT573 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [573];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT574 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [574];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT575 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [575];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT576 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [576];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT577 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [577];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT578 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [578];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT579 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [579];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT580 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [580];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT581 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [581];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT582 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [582];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT583 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [583];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT584 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [584];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT585 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [585];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT586 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [586];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT587 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [587];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT588 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [588];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT589 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [589];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT590 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [590];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT591 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [591];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT592 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [592];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT593 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [593];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT594 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [594];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT595 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [595];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT596 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [596];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT597 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [597];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT598 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [598];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT599 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [599];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT600 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [600];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT601 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [601];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT602 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [602];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT603 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [603];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT604 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [604];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT605 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [605];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT606 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [606];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT607 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [607];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT608 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [608];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT609 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [609];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT610 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [610];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT611 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [611];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT612 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [612];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT613 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [613];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT614 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [614];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT615 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [615];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT616 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [616];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT617 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [617];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT618 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [618];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT619 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [619];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT620 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [620];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT621 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [621];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT622 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [622];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT623 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [623];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT624 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [624];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT625 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [625];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT626 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [626];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT627 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [627];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT628 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [628];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT629 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [629];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT630 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [630];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT631 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [631];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT632 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [632];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT633 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [633];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT634 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [634];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT635 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [635];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT636 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [636];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT637 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [637];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT638 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [638];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT639 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [639];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT640 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [640];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT641 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [641];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT642 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [642];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT643 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [643];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT644 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [644];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT645 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [645];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT646 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [646];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT647 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [647];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT648 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [648];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT649 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [649];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT650 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [650];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT651 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [651];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT652 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [652];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT653 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [653];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT654 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [654];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT655 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [655];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT656 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [656];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT657 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [657];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT658 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [658];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT659 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [659];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT660 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [660];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT661 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [661];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT662 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [662];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT663 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [663];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT664 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [664];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT665 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [665];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT666 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [666];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT667 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [667];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT668 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [668];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT669 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [669];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT670 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [670];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT671 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [671];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT672 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [672];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT673 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [673];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT674 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [674];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT675 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [675];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT676 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [676];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT677 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [677];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT678 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [678];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT679 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [679];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT680 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [680];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT681 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [681];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT682 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [682];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT683 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [683];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT684 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [684];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT685 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [685];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT686 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [686];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT687 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [687];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT688 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [688];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT689 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [689];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT690 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [690];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT691 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [691];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT692 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [692];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT693 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [693];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT694 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [694];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT695 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [695];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT696 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [696];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT697 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [697];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT698 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [698];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT699 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [699];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT700 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [700];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT701 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [701];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT702 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [702];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT703 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [703];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT704 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [704];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT705 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [705];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT706 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [706];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT707 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [707];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT708 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [708];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT709 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [709];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT710 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [710];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT711 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [711];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT712 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [712];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT713 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [713];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT714 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [714];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT715 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [715];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT716 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [716];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT717 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [717];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT718 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [718];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT719 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [719];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT720 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [720];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT721 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [721];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT722 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [722];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT723 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [723];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT724 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [724];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT725 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [725];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT726 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [726];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT727 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [727];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT728 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [728];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT729 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [729];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT730 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [730];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT731 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [731];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT732 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [732];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT733 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [733];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT734 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [734];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT735 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [735];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT736 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [736];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT737 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [737];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT738 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [738];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT739 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [739];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT740 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [740];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT741 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [741];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT742 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [742];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT743 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [743];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT744 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [744];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT745 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [745];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT746 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [746];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT747 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [747];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT748 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [748];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT749 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [749];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT750 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [750];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT751 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [751];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT752 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [752];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT753 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [753];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT754 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [754];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT755 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [755];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT756 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [756];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT757 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [757];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT758 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [758];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT759 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [759];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT760 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [760];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT761 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [761];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT762 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [762];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT763 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [763];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT764 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [764];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT765 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [765];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT766 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [766];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT767 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [767];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT768 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [768];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT769 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [769];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT770 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [770];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT771 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [771];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT772 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [772];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT773 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [773];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT774 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [774];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT775 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [775];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT776 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [776];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT777 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [777];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT778 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [778];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT779 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [779];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT780 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [780];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT781 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [781];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT782 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [782];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT783 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [783];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT784 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [784];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT785 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [785];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT786 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [786];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT787 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [787];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT788 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [788];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT789 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [789];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT790 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [790];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT791 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [791];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT792 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [792];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT793 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [793];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT794 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [794];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT795 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [795];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT796 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [796];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT797 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [797];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT798 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [798];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT799 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [799];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT800 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [800];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT801 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [801];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT802 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [802];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT803 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [803];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT804 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [804];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT805 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [805];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT806 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [806];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT807 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [807];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT808 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [808];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT809 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [809];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT810 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [810];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT811 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [811];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT812 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [812];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT813 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [813];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT814 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [814];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT815 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [815];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT816 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [816];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT817 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [817];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT818 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [818];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT819 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [819];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT820 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [820];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT821 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [821];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT822 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [822];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT823 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [823];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT824 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [824];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT825 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [825];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT826 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [826];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT827 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [827];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT828 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [828];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT829 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [829];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT830 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [830];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT831 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [831];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT832 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [832];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT833 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [833];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT834 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [834];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT835 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [835];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT836 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [836];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT837 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [837];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT838 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [838];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT839 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [839];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT840 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [840];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT841 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [841];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT842 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [842];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT843 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [843];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT844 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [844];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT845 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [845];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT846 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [846];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT847 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [847];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT848 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [848];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT849 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [849];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT850 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [850];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT851 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [851];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT852 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [852];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT853 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [853];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT854 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [854];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT855 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [855];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT856 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [856];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT857 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [857];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT858 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [858];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT859 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [859];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT860 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [860];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT861 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [861];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT862 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [862];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT863 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [863];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT864 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [864];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT865 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [865];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT866 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [866];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT867 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [867];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT868 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [868];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT869 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [869];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT870 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [870];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT871 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [871];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT872 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [872];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT873 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [873];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT874 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [874];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT875 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [875];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT876 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [876];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT877 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [877];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT878 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [878];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT879 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [879];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT880 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [880];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT881 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [881];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT882 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [882];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT883 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [883];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT884 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [884];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT885 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [885];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT886 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [886];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT887 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [887];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT888 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [888];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT889 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [889];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT890 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [890];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT891 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [891];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT892 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [892];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT893 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [893];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT894 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [894];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT895 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [895];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT896 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [896];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT897 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [897];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT898 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [898];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT899 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [899];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT900 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [900];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT901 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [901];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT902 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [902];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT903 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [903];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT904 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [904];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT905 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [905];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT906 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [906];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT907 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [907];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT908 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [908];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT909 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [909];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT910 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [910];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT911 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [911];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT912 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [912];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT913 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [913];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT914 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [914];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT915 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [915];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT916 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [916];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT917 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [917];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT918 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [918];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT919 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [919];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT920 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [920];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT921 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [921];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT922 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [922];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT923 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [923];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT924 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [924];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT925 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [925];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT926 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [926];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT927 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [927];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT928 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [928];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT929 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [929];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT930 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [930];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT931 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [931];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT932 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [932];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT933 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [933];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT934 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [934];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT935 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [935];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT936 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [936];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT937 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [937];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT938 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [938];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT939 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [939];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT940 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [940];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT941 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [941];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT942 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [942];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT943 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [943];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT944 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [944];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT945 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [945];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT946 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [946];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT947 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [947];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT948 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [948];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT949 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [949];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT950 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [950];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT951 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [951];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT952 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [952];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT953 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [953];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT954 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [954];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT955 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [955];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT956 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [956];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT957 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [957];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT958 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [958];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT959 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [959];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT960 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [960];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT961 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [961];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT962 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [962];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT963 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [963];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT964 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [964];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT965 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [965];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT966 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [966];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT967 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [967];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT968 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [968];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT969 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [969];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT970 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [970];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT971 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [971];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT972 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [972];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT973 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [973];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT974 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [974];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT975 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [975];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT976 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [976];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT977 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [977];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT978 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [978];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT979 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [979];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT980 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [980];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT981 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [981];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT982 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [982];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT983 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [983];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT984 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [984];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT985 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [985];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT986 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [986];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT987 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [987];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT988 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [988];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT989 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [989];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT990 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [990];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT991 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [991];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT992 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [992];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT993 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [993];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT994 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [994];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT995 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [995];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT996 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [996];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT997 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [997];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT998 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [998];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT999 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [999];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1000 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1000];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1001 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1001];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1002 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1002];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1003 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1003];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1004 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1004];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1005 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1005];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1006 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1006];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1007 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1007];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1008 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1008];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1009 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1009];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1010 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1010];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1011 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1011];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1012 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1012];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1013 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1013];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1014 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1014];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1015 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1015];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1016 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1016];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1017 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1017];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1018 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1018];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1019 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1019];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1020 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1020];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1021 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1021];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1022 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1022];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1023 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1023];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1024 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1024];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1025 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1025];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1026 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1026];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1027 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1027];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1028 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1028];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1029 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1029];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1030 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1030];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1031 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1031];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1032 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1032];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1033 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1033];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1034 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1034];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1035 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1035];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1036 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1036];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1037 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1037];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1038 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1038];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1039 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1039];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1040 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1040];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1041 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1041];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1042 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1042];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1043 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1043];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1044 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1044];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1045 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1045];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1046 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1046];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1047 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1047];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1048 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1048];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1049 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1049];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1050 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1050];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1051 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1051];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1052 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1052];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1053 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1053];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1054 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1054];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1055 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1055];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1056 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1056];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1057 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1057];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1058 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1058];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1059 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1059];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1060 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1060];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1061 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1061];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1062 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1062];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1063 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1063];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1064 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1064];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1065 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1065];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1066 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1066];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1067 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1067];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1068 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1068];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1069 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1069];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1070 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1070];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1071 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1071];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1072 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1072];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1073 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1073];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1074 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1074];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1075 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1075];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1076 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1076];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1077 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1077];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1078 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1078];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1079 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1079];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1080 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1080];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1081 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1081];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1082 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1082];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1083 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1083];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1084 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1084];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1085 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1085];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1086 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1086];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1087 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1087];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1088 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1088];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1089 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1089];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1090 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1090];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1091 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1091];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1092 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1092];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1093 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1093];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1094 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1094];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1095 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1095];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1096 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1096];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1097 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1097];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1098 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1098];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1099 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1099];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1100 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1100];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1101 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1101];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1102 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1102];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1103 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1103];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1104 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1104];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1105 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1105];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1106 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1106];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1107 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1107];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1108 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1108];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1109 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1109];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1110 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1110];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1111 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1111];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1112 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1112];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1113 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1113];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1114 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1114];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1115 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1115];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1116 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1116];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1117 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1117];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1118 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1118];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1119 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1119];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1120 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1120];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1121 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1121];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1122 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1122];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1123 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1123];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1124 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1124];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1125 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1125];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1126 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1126];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1127 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1127];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1128 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1128];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1129 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1129];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1130 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1130];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1131 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1131];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1132 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1132];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1133 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1133];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1134 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1134];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1135 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1135];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1136 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1136];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1137 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1137];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1138 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1138];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1139 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1139];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1140 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1140];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1141 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1141];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1142 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1142];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1143 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1143];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1144 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1144];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1145 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1145];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1146 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1146];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1147 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1147];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1148 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1148];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1149 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1149];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1150 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1150];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1151 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1151];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1152 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1152];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1153 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1153];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1154 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1154];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1155 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1155];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1156 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1156];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1157 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1157];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1158 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1158];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1159 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1159];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1160 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1160];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1161 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1161];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1162 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1162];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1163 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1163];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1164 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1164];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1165 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1165];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1166 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1166];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1167 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1167];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1168 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1168];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1169 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1169];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1170 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1170];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1171 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1171];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1172 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1172];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1173 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1173];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1174 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1174];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1175 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1175];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1176 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1176];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1177 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1177];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1178 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1178];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1179 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1179];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1180 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1180];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1181 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1181];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1182 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1182];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1183 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1183];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1184 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1184];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1185 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1185];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1186 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1186];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1187 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1187];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1188 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1188];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1189 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1189];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1190 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1190];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1191 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1191];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1192 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1192];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1193 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1193];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1194 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1194];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1195 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1195];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1196 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1196];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1197 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1197];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1198 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1198];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1199 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus [1199];
+
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXCRURESETOUT0 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXCRURESETOUT_bus [0];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXCRURESETOUT1 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXCRURESETOUT_bus [1];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXCRURESETOUT2 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXCRURESETOUT_bus [2];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXCRURESETOUT3 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXCRURESETOUT_bus [3];
+
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXCRUPOWERDN0 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXCRUPOWERDOWN_bus [0];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXCRUPOWERDN1 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXCRUPOWERDOWN_bus [1];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXCRUPOWERDN2 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXCRUPOWERDOWN_bus [2];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXCRUPOWERDN3 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXCRUPOWERDOWN_bus [3];
+
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXIBPOWERDN0 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXIBPOWERDOWN_bus [0];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXIBPOWERDN1 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXIBPOWERDOWN_bus [1];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXIBPOWERDN2 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXIBPOWERDOWN_bus [2];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~RXIBPOWERDN3 = \pma_direct|auto_generated|tx_pll_cent_unit0_RXIBPOWERDOWN_bus [3];
+
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXOBPOWERDN0 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXOBPOWERDOWN_bus [0];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXOBPOWERDN1 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXOBPOWERDOWN_bus [1];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXOBPOWERDN2 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXOBPOWERDOWN_bus [2];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXOBPOWERDN3 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXOBPOWERDOWN_bus [3];
+
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXDETECTRXPOWERDN0 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXDETECTRXPOWERDOWN_bus [0];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXDETECTRXPOWERDN1 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXDETECTRXPOWERDOWN_bus [1];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXDETECTRXPOWERDN2 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXDETECTRXPOWERDOWN_bus [2];
+assign \pma_direct|auto_generated|tx_pll_cent_unit0~TXDETECTRXPOWERDN3 = \pma_direct|auto_generated|tx_pll_cent_unit0_TXDETECTRXPOWERDOWN_bus [3];
+
+assign \pma_direct|auto_generated|edge_cmu_clkdivpowerdn [0] = \pma_direct|auto_generated|tx_pll_cent_unit0_CLKDIVPOWERDN_bus [0];
+
+assign \pma_direct|auto_generated|edge_pllpowerdn_in [0] = \pma_direct|auto_generated|tx_pll_cent_unit0_PLLPOWERDN_bus [0];
+
+assign \pma_direct|auto_generated|cal_blk0~calibrationstatus = \pma_direct|auto_generated|cal_blk0_CALIBRATIONSTATUS_bus [0];
+assign \pma_direct|auto_generated|cal_blk0~CALIBRATIONSTATUS1 = \pma_direct|auto_generated|cal_blk0_CALIBRATIONSTATUS_bus [1];
+assign \pma_direct|auto_generated|cal_blk0~CALIBRATIONSTATUS2 = \pma_direct|auto_generated|cal_blk0_CALIBRATIONSTATUS_bus [2];
+assign \pma_direct|auto_generated|cal_blk0~CALIBRATIONSTATUS3 = \pma_direct|auto_generated|cal_blk0_CALIBRATIONSTATUS_bus [3];
+assign \pma_direct|auto_generated|cal_blk0~CALIBRATIONSTATUS4 = \pma_direct|auto_generated|cal_blk0_CALIBRATIONSTATUS_bus [4];
+
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [400] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [0];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [401] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [1];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [402] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [2];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [403] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [3];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [404] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [4];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [405] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [5];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [406] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [6];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [407] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [7];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [408] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [8];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [409] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [9];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [410] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [10];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [411] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [11];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [412] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [12];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [413] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [13];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [414] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [14];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [415] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [15];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [416] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [16];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [417] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [17];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [418] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [18];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [419] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [19];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [420] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [20];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [421] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [21];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [422] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [22];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [423] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [23];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [424] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [24];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [425] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [25];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [426] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [26];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [427] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [27];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [428] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [28];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [429] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [29];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [430] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [30];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [431] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [31];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [432] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [32];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [433] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [33];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [434] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [34];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [435] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [35];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [436] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [36];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [437] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [37];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [438] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [38];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [439] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [39];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [440] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [40];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [441] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [41];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [442] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [42];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [443] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [43];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [444] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [44];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [445] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [45];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [446] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [46];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [447] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [47];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [448] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [48];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [449] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [49];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [450] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [50];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [451] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [51];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [452] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [52];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [453] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [53];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [454] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [54];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [455] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [55];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [456] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [56];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [457] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [57];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [458] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [58];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [459] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [59];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [460] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [60];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [461] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [61];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [462] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [62];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [463] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [63];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [464] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [64];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [465] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [65];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [466] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [66];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [467] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [67];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [468] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [68];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [469] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [69];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [470] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [70];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [471] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [71];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [472] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [72];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [473] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [73];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [474] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [74];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [475] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [75];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [476] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [76];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [477] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [77];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [478] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [78];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [479] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [79];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [480] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [80];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [481] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [81];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [482] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [82];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [483] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [83];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [484] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [84];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [485] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [85];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [486] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [86];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [487] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [87];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [488] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [88];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [489] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [89];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [490] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [90];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [491] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [91];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [492] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [92];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [493] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [93];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [494] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [94];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [495] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [95];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [496] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [96];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [497] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [97];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [498] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [98];
+assign \pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [499] = \pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus [99];
+
+assign \pma_direct|auto_generated|edge_pll_analogrefclkout [0] = \pma_direct|auto_generated|central_clk_div0_ANALOGREFCLKOUT_bus [0];
+assign \pma_direct|auto_generated|edge_pll_analogrefclkout [1] = \pma_direct|auto_generated|central_clk_div0_ANALOGREFCLKOUT_bus [1];
+
+assign \pma_direct|auto_generated|edge_pll_analogfastrefclkout [0] = \pma_direct|auto_generated|central_clk_div0_ANALOGFASTREFCLKOUT_bus [0];
+assign \pma_direct|auto_generated|edge_pll_analogfastrefclkout [1] = \pma_direct|auto_generated|central_clk_div0_ANALOGFASTREFCLKOUT_bus [1];
+
+// Location: IOIBUF_X0_Y68_N32
+stratixiv_io_ibuf \pll_inclk[0]~input (
+ .i(pll_inclk[0]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\pll_inclk[0]~input_o ));
+// synopsys translate_off
+defparam \pll_inclk[0]~input .bus_hold = "false";
+defparam \pll_inclk[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y68_N1
+stratixiv_io_ibuf \reconfig_clk~input (
+ .i(reconfig_clk),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\reconfig_clk~input_o ));
+// synopsys translate_off
+defparam \reconfig_clk~input .bus_hold = "false";
+defparam \reconfig_clk~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X36_Y0_N94
+stratixiv_io_ibuf \reconfig_togxb[3]~input (
+ .i(reconfig_togxb[3]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\reconfig_togxb[3]~input_o ));
+// synopsys translate_off
+defparam \reconfig_togxb[3]~input .bus_hold = "false";
+defparam \reconfig_togxb[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X57_Y0_N63
+stratixiv_io_ibuf \cal_blk_clk~input (
+ .i(cal_blk_clk),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\cal_blk_clk~input_o ));
+// synopsys translate_off
+defparam \cal_blk_clk~input .bus_hold = "false";
+defparam \cal_blk_clk~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y96_N95
+stratixiv_io_obuf \ch_ctrl_readdata[0]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[0]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[0]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[0]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X104_Y129_N95
+stratixiv_io_obuf \ch_ctrl_readdata[1]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[1]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[1]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[1]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y74_N113
+stratixiv_io_obuf \ch_ctrl_readdata[2]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[2]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[2]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[2]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X135_Y0_N20
+stratixiv_io_obuf \ch_ctrl_readdata[3]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[3]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[3]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[3]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y72_N113
+stratixiv_io_obuf \ch_ctrl_readdata[4]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[4]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[4]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[4]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X173_Y129_N20
+stratixiv_io_obuf \ch_ctrl_readdata[5]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[5]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[5]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[5]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X150_Y129_N20
+stratixiv_io_obuf \ch_ctrl_readdata[6]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[6]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[6]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[6]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y100_N113
+stratixiv_io_obuf \ch_ctrl_readdata[7]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[7]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[7]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[7]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[7]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X70_Y0_N51
+stratixiv_io_obuf \ch_ctrl_readdata[8]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[8]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[8]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[8]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[8]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X73_Y0_N82
+stratixiv_io_obuf \ch_ctrl_readdata[9]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[9]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[9]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[9]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[9]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X68_Y129_N113
+stratixiv_io_obuf \ch_ctrl_readdata[10]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[10]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[10]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[10]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[10]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y112_N51
+stratixiv_io_obuf \ch_ctrl_readdata[11]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[11]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[11]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[11]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[11]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y44_N20
+stratixiv_io_obuf \ch_ctrl_readdata[12]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[12]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[12]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[12]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[12]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y16_N20
+stratixiv_io_obuf \ch_ctrl_readdata[13]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[13]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[13]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[13]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[13]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X33_Y129_N51
+stratixiv_io_obuf \ch_ctrl_readdata[14]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[14]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[14]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[14]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[14]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y100_N82
+stratixiv_io_obuf \ch_ctrl_readdata[15]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[15]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[15]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[15]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[15]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X57_Y129_N82
+stratixiv_io_obuf \ch_ctrl_readdata[16]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[16]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[16]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[16]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[16]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X45_Y129_N82
+stratixiv_io_obuf \ch_ctrl_readdata[17]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[17]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[17]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[17]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[17]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X175_Y129_N51
+stratixiv_io_obuf \ch_ctrl_readdata[18]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[18]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[18]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[18]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[18]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X73_Y129_N113
+stratixiv_io_obuf \ch_ctrl_readdata[19]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[19]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[19]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[19]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[19]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X133_Y0_N51
+stratixiv_io_obuf \ch_ctrl_readdata[20]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[20]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[20]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[20]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[20]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y71_N20
+stratixiv_io_obuf \ch_ctrl_readdata[21]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[21]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[21]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[21]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[21]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X132_Y129_N20
+stratixiv_io_obuf \ch_ctrl_readdata[22]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[22]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[22]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[22]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[22]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y30_N113
+stratixiv_io_obuf \ch_ctrl_readdata[23]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[23]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[23]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[23]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[23]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X76_Y129_N51
+stratixiv_io_obuf \ch_ctrl_readdata[24]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[24]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[24]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[24]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[24]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y81_N20
+stratixiv_io_obuf \ch_ctrl_readdata[25]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[25]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[25]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[25]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[25]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X139_Y0_N113
+stratixiv_io_obuf \ch_ctrl_readdata[26]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[26]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[26]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[26]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[26]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X100_Y129_N64
+stratixiv_io_obuf \ch_ctrl_readdata[27]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[27]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[27]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[27]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[27]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X64_Y129_N82
+stratixiv_io_obuf \ch_ctrl_readdata[28]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[28]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[28]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[28]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[28]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X173_Y0_N51
+stratixiv_io_obuf \ch_ctrl_readdata[29]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[29]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[29]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[29]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[29]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X159_Y0_N51
+stratixiv_io_obuf \ch_ctrl_readdata[30]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[30]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[30]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[30]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[30]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y112_N51
+stratixiv_io_obuf \ch_ctrl_readdata[31]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\ch_ctrl_readdata[31]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \ch_ctrl_readdata[31]~output .bus_hold = "false";
+defparam \ch_ctrl_readdata[31]~output .open_drain_output = "false";
+defparam \ch_ctrl_readdata[31]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X62_Y0_N82
+stratixiv_io_obuf \pll_locked~output (
+ .i(\pma_direct|auto_generated|pll_locked [0]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\pll_locked~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \pll_locked~output .bus_hold = "false";
+defparam \pll_locked~output .open_drain_output = "false";
+defparam \pll_locked~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X113_Y129_N20
+stratixiv_io_obuf \reconfig_fromgxb[0]~output (
+ .i(\~QUARTUS_CREATED_GND~I_combout ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[0]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[0]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[0]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X60_Y0_N51
+stratixiv_io_obuf \reconfig_fromgxb[1]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_analogtestbus [2]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[1]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[1]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[1]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y15_N64
+stratixiv_io_obuf \reconfig_fromgxb[2]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_analogtestbus [3]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[2]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[2]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[2]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X54_Y0_N82
+stratixiv_io_obuf \reconfig_fromgxb[3]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_analogtestbus [4]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[3]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[3]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[3]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y15_N2
+stratixiv_io_obuf \reconfig_fromgxb[4]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_analogtestbus [5]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[4]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[4]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[4]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y98_N20
+stratixiv_io_obuf \reconfig_fromgxb[5]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[5]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[5]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[5]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X38_Y129_N82
+stratixiv_io_obuf \reconfig_fromgxb[6]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[6]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[6]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[6]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X113_Y0_N82
+stratixiv_io_obuf \reconfig_fromgxb[7]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[7]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[7]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[7]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[7]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X129_Y129_N113
+stratixiv_io_obuf \reconfig_fromgxb[8]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[8]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[8]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[8]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[8]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y18_N113
+stratixiv_io_obuf \reconfig_fromgxb[9]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[9]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[9]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[9]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[9]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y110_N20
+stratixiv_io_obuf \reconfig_fromgxb[10]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[10]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[10]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[10]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[10]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X175_Y129_N20
+stratixiv_io_obuf \reconfig_fromgxb[11]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[11]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[11]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[11]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[11]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X153_Y129_N113
+stratixiv_io_obuf \reconfig_fromgxb[12]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[12]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[12]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[12]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[12]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X162_Y129_N113
+stratixiv_io_obuf \reconfig_fromgxb[13]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[13]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[13]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[13]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[13]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X153_Y129_N20
+stratixiv_io_obuf \reconfig_fromgxb[14]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[14]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[14]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[14]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[14]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y24_N51
+stratixiv_io_obuf \reconfig_fromgxb[15]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[15]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[15]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[15]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[15]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y48_N20
+stratixiv_io_obuf \reconfig_fromgxb[16]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[16]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[16]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[16]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[16]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X113_Y129_N113
+stratixiv_io_obuf \reconfig_fromgxb[17]~output (
+ .i(\~QUARTUS_CREATED_GND~I_combout ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[17]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[17]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[17]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[17]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X36_Y0_N51
+stratixiv_io_obuf \reconfig_fromgxb[18]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_analogtestbus [2]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[18]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[18]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[18]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[18]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y16_N82
+stratixiv_io_obuf \reconfig_fromgxb[19]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_analogtestbus [3]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[19]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[19]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[19]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[19]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X31_Y0_N51
+stratixiv_io_obuf \reconfig_fromgxb[20]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_analogtestbus [4]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[20]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[20]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[20]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[20]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y16_N113
+stratixiv_io_obuf \reconfig_fromgxb[21]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_analogtestbus [5]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[21]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[21]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[21]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[21]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X152_Y129_N82
+stratixiv_io_obuf \reconfig_fromgxb[22]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[22]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[22]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[22]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[22]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y80_N82
+stratixiv_io_obuf \reconfig_fromgxb[23]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[23]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[23]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[23]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[23]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X119_Y0_N113
+stratixiv_io_obuf \reconfig_fromgxb[24]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[24]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[24]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[24]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[24]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X152_Y0_N51
+stratixiv_io_obuf \reconfig_fromgxb[25]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[25]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[25]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[25]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[25]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X76_Y129_N82
+stratixiv_io_obuf \reconfig_fromgxb[26]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[26]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[26]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[26]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[26]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X137_Y0_N82
+stratixiv_io_obuf \reconfig_fromgxb[27]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[27]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[27]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[27]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[27]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X127_Y0_N20
+stratixiv_io_obuf \reconfig_fromgxb[28]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[28]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[28]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[28]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[28]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X159_Y0_N113
+stratixiv_io_obuf \reconfig_fromgxb[29]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[29]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[29]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[29]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[29]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y48_N51
+stratixiv_io_obuf \reconfig_fromgxb[30]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[30]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[30]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[30]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[30]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y104_N113
+stratixiv_io_obuf \reconfig_fromgxb[31]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[31]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[31]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[31]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[31]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X25_Y129_N20
+stratixiv_io_obuf \reconfig_fromgxb[32]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[32]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[32]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[32]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[32]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X125_Y129_N20
+stratixiv_io_obuf \reconfig_fromgxb[33]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[33]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[33]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[33]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[33]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X113_Y129_N82
+stratixiv_io_obuf \reconfig_fromgxb[34]~output (
+ .i(\~QUARTUS_CREATED_GND~I_combout ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[34]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[34]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[34]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[34]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X45_Y0_N82
+stratixiv_io_obuf \reconfig_fromgxb[35]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_analogtestbus [2]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[35]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[35]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[35]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[35]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X9_Y0_N82
+stratixiv_io_obuf \reconfig_fromgxb[36]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_analogtestbus [3]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[36]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[36]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[36]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[36]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X11_Y0_N82
+stratixiv_io_obuf \reconfig_fromgxb[37]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_analogtestbus [4]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[37]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[37]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[37]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[37]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X42_Y0_N82
+stratixiv_io_obuf \reconfig_fromgxb[38]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_analogtestbus [5]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[38]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[38]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[38]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[38]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y74_N51
+stratixiv_io_obuf \reconfig_fromgxb[39]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[39]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[39]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[39]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[39]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X121_Y0_N20
+stratixiv_io_obuf \reconfig_fromgxb[40]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[40]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[40]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[40]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[40]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X150_Y0_N113
+stratixiv_io_obuf \reconfig_fromgxb[41]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[41]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[41]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[41]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[41]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y97_N82
+stratixiv_io_obuf \reconfig_fromgxb[42]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[42]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[42]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[42]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[42]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y104_N20
+stratixiv_io_obuf \reconfig_fromgxb[43]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[43]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[43]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[43]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[43]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X27_Y129_N82
+stratixiv_io_obuf \reconfig_fromgxb[44]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[44]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[44]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[44]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[44]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X167_Y129_N51
+stratixiv_io_obuf \reconfig_fromgxb[45]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[45]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[45]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[45]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[45]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y69_N95
+stratixiv_io_obuf \reconfig_fromgxb[46]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[46]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[46]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[46]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[46]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y56_N113
+stratixiv_io_obuf \reconfig_fromgxb[47]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[47]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[47]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[47]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[47]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y69_N64
+stratixiv_io_obuf \reconfig_fromgxb[48]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[48]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[48]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[48]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[48]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X36_Y129_N82
+stratixiv_io_obuf \reconfig_fromgxb[49]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[49]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[49]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[49]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[49]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y74_N82
+stratixiv_io_obuf \reconfig_fromgxb[50]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[50]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[50]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[50]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[50]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X113_Y129_N51
+stratixiv_io_obuf \reconfig_fromgxb[51]~output (
+ .i(\~QUARTUS_CREATED_GND~I_combout ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[51]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[51]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[51]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[51]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y15_N33
+stratixiv_io_obuf \reconfig_fromgxb[52]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_analogtestbus [2]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[52]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[52]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[52]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[52]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X22_Y0_N51
+stratixiv_io_obuf \reconfig_fromgxb[53]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_analogtestbus [3]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[53]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[53]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[53]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[53]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X11_Y0_N51
+stratixiv_io_obuf \reconfig_fromgxb[54]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_analogtestbus [4]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[54]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[54]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[54]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[54]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X39_Y0_N51
+stratixiv_io_obuf \reconfig_fromgxb[55]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_analogtestbus [5]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[55]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[55]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[55]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[55]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y28_N113
+stratixiv_io_obuf \reconfig_fromgxb[56]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[56]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[56]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[56]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[56]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y56_N20
+stratixiv_io_obuf \reconfig_fromgxb[57]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[57]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[57]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[57]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[57]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X73_Y129_N20
+stratixiv_io_obuf \reconfig_fromgxb[58]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[58]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[58]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[58]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[58]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y50_N113
+stratixiv_io_obuf \reconfig_fromgxb[59]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[59]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[59]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[59]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[59]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y106_N113
+stratixiv_io_obuf \reconfig_fromgxb[60]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[60]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[60]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[60]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[60]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X173_Y129_N113
+stratixiv_io_obuf \reconfig_fromgxb[61]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[61]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[61]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[61]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[61]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X145_Y0_N51
+stratixiv_io_obuf \reconfig_fromgxb[62]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[62]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[62]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[62]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[62]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X47_Y129_N51
+stratixiv_io_obuf \reconfig_fromgxb[63]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[63]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[63]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[63]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[63]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X45_Y129_N51
+stratixiv_io_obuf \reconfig_fromgxb[64]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[64]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[64]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[64]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[64]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y100_N20
+stratixiv_io_obuf \reconfig_fromgxb[65]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[65]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[65]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[65]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[65]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X78_Y0_N82
+stratixiv_io_obuf \reconfig_fromgxb[66]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[66]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[66]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[66]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[66]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y112_N82
+stratixiv_io_obuf \reconfig_fromgxb[67]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\reconfig_fromgxb[67]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \reconfig_fromgxb[67]~output .bus_hold = "false";
+defparam \reconfig_fromgxb[67]~output .open_drain_output = "false";
+defparam \reconfig_fromgxb[67]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y80_N51
+stratixiv_io_obuf \aeq_from_gxb[0]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[0]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[0]~output .bus_hold = "false";
+defparam \aeq_from_gxb[0]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y107_N82
+stratixiv_io_obuf \aeq_from_gxb[1]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[1]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[1]~output .bus_hold = "false";
+defparam \aeq_from_gxb[1]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X45_Y129_N20
+stratixiv_io_obuf \aeq_from_gxb[2]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[2]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[2]~output .bus_hold = "false";
+defparam \aeq_from_gxb[2]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X80_Y129_N33
+stratixiv_io_obuf \aeq_from_gxb[3]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[3]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[3]~output .bus_hold = "false";
+defparam \aeq_from_gxb[3]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y69_N64
+stratixiv_io_obuf \aeq_from_gxb[4]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[4]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[4]~output .bus_hold = "false";
+defparam \aeq_from_gxb[4]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X157_Y129_N20
+stratixiv_io_obuf \aeq_from_gxb[5]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[5]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[5]~output .bus_hold = "false";
+defparam \aeq_from_gxb[5]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X62_Y129_N82
+stratixiv_io_obuf \aeq_from_gxb[6]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[6]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[6]~output .bus_hold = "false";
+defparam \aeq_from_gxb[6]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X104_Y129_N2
+stratixiv_io_obuf \aeq_from_gxb[7]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[7]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[7]~output .bus_hold = "false";
+defparam \aeq_from_gxb[7]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[7]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y33_N113
+stratixiv_io_obuf \aeq_from_gxb[8]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[8]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[8]~output .bus_hold = "false";
+defparam \aeq_from_gxb[8]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[8]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y106_N82
+stratixiv_io_obuf \aeq_from_gxb[9]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[9]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[9]~output .bus_hold = "false";
+defparam \aeq_from_gxb[9]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[9]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X47_Y129_N20
+stratixiv_io_obuf \aeq_from_gxb[10]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[10]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[10]~output .bus_hold = "false";
+defparam \aeq_from_gxb[10]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[10]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X36_Y129_N113
+stratixiv_io_obuf \aeq_from_gxb[11]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[11]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[11]~output .bus_hold = "false";
+defparam \aeq_from_gxb[11]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[11]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X159_Y129_N51
+stratixiv_io_obuf \aeq_from_gxb[12]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[12]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[12]~output .bus_hold = "false";
+defparam \aeq_from_gxb[12]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[12]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X139_Y0_N82
+stratixiv_io_obuf \aeq_from_gxb[13]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[13]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[13]~output .bus_hold = "false";
+defparam \aeq_from_gxb[13]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[13]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y72_N113
+stratixiv_io_obuf \aeq_from_gxb[14]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[14]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[14]~output .bus_hold = "false";
+defparam \aeq_from_gxb[14]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[14]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y31_N82
+stratixiv_io_obuf \aeq_from_gxb[15]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[15]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[15]~output .bus_hold = "false";
+defparam \aeq_from_gxb[15]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[15]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X137_Y129_N51
+stratixiv_io_obuf \aeq_from_gxb[16]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[16]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[16]~output .bus_hold = "false";
+defparam \aeq_from_gxb[16]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[16]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X129_Y129_N51
+stratixiv_io_obuf \aeq_from_gxb[17]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[17]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[17]~output .bus_hold = "false";
+defparam \aeq_from_gxb[17]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[17]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y52_N51
+stratixiv_io_obuf \aeq_from_gxb[18]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[18]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[18]~output .bus_hold = "false";
+defparam \aeq_from_gxb[18]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[18]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X132_Y0_N51
+stratixiv_io_obuf \aeq_from_gxb[19]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[19]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[19]~output .bus_hold = "false";
+defparam \aeq_from_gxb[19]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[19]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X121_Y129_N51
+stratixiv_io_obuf \aeq_from_gxb[20]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[20]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[20]~output .bus_hold = "false";
+defparam \aeq_from_gxb[20]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[20]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X100_Y129_N2
+stratixiv_io_obuf \aeq_from_gxb[21]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[21]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[21]~output .bus_hold = "false";
+defparam \aeq_from_gxb[21]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[21]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y78_N20
+stratixiv_io_obuf \aeq_from_gxb[22]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[22]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[22]~output .bus_hold = "false";
+defparam \aeq_from_gxb[22]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[22]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y21_N20
+stratixiv_io_obuf \aeq_from_gxb[23]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[23]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[23]~output .bus_hold = "false";
+defparam \aeq_from_gxb[23]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[23]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y80_N51
+stratixiv_io_obuf \aeq_from_gxb[24]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[24]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[24]~output .bus_hold = "false";
+defparam \aeq_from_gxb[24]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[24]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X175_Y129_N82
+stratixiv_io_obuf \aeq_from_gxb[25]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[25]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[25]~output .bus_hold = "false";
+defparam \aeq_from_gxb[25]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[25]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X119_Y0_N51
+stratixiv_io_obuf \aeq_from_gxb[26]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[26]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[26]~output .bus_hold = "false";
+defparam \aeq_from_gxb[26]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[26]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X164_Y0_N20
+stratixiv_io_obuf \aeq_from_gxb[27]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[27]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[27]~output .bus_hold = "false";
+defparam \aeq_from_gxb[27]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[27]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y32_N95
+stratixiv_io_obuf \aeq_from_gxb[28]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[28]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[28]~output .bus_hold = "false";
+defparam \aeq_from_gxb[28]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[28]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X145_Y0_N82
+stratixiv_io_obuf \aeq_from_gxb[29]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[29]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[29]~output .bus_hold = "false";
+defparam \aeq_from_gxb[29]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[29]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y104_N51
+stratixiv_io_obuf \aeq_from_gxb[30]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[30]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[30]~output .bus_hold = "false";
+defparam \aeq_from_gxb[30]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[30]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X110_Y129_N95
+stratixiv_io_obuf \aeq_from_gxb[31]~output (
+ .i(gnd),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\aeq_from_gxb[31]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \aeq_from_gxb[31]~output .bus_hold = "false";
+defparam \aeq_from_gxb[31]~output .open_drain_output = "false";
+defparam \aeq_from_gxb[31]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y3_N142
+stratixiv_io_obuf \tx_dataout[0]~output (
+ .i(\pma_direct|auto_generated|wire_transmit_pma0_dataout ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\tx_dataout[0]~output_o ),
+ .obar(\tx_dataout[0]~0 ));
+// synopsys translate_off
+defparam \tx_dataout[0]~output .bus_hold = "false";
+defparam \tx_dataout[0]~output .open_drain_output = "false";
+defparam \tx_dataout[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y6_N142
+stratixiv_io_obuf \tx_dataout[1]~output (
+ .i(\pma_direct|auto_generated|wire_transmit_pma1_dataout ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\tx_dataout[1]~output_o ),
+ .obar(\tx_dataout[1]~1 ));
+// synopsys translate_off
+defparam \tx_dataout[1]~output .bus_hold = "false";
+defparam \tx_dataout[1]~output .open_drain_output = "false";
+defparam \tx_dataout[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y15_N142
+stratixiv_io_obuf \tx_dataout[2]~output (
+ .i(\pma_direct|auto_generated|wire_transmit_pma2_dataout ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\tx_dataout[2]~output_o ),
+ .obar(\tx_dataout[2]~2 ));
+// synopsys translate_off
+defparam \tx_dataout[2]~output .bus_hold = "false";
+defparam \tx_dataout[2]~output .open_drain_output = "false";
+defparam \tx_dataout[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y18_N142
+stratixiv_io_obuf \tx_dataout[3]~output (
+ .i(\pma_direct|auto_generated|wire_transmit_pma3_dataout ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\tx_dataout[3]~output_o ),
+ .obar(\tx_dataout[3]~3 ));
+// synopsys translate_off
+defparam \tx_dataout[3]~output .bus_hold = "false";
+defparam \tx_dataout[3]~output .open_drain_output = "false";
+defparam \tx_dataout[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X80_Y0_N95
+stratixiv_io_obuf \tx_clkout[0]~output (
+ .i(\pma_direct|auto_generated|wire_transmit_pma0_clockout~clkctrl_outclk ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\tx_clkout[0]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \tx_clkout[0]~output .bus_hold = "false";
+defparam \tx_clkout[0]~output .open_drain_output = "false";
+defparam \tx_clkout[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X70_Y0_N113
+stratixiv_io_obuf \tx_clkout[1]~output (
+ .i(\pma_direct|auto_generated|wire_transmit_pma1_clockout~clkctrl_outclk ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\tx_clkout[1]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \tx_clkout[1]~output .bus_hold = "false";
+defparam \tx_clkout[1]~output .open_drain_output = "false";
+defparam \tx_clkout[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X73_Y0_N51
+stratixiv_io_obuf \tx_clkout[2]~output (
+ .i(\pma_direct|auto_generated|wire_transmit_pma2_clockout~clkctrl_outclk ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\tx_clkout[2]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \tx_clkout[2]~output .bus_hold = "false";
+defparam \tx_clkout[2]~output .open_drain_output = "false";
+defparam \tx_clkout[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y59_N2
+stratixiv_io_obuf \tx_clkout[3]~output (
+ .i(\pma_direct|auto_generated|wire_transmit_pma3_clockout~clkctrl_outclk ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\tx_clkout[3]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \tx_clkout[3]~output .bus_hold = "false";
+defparam \tx_clkout[3]~output .open_drain_output = "false";
+defparam \tx_clkout[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X22_Y0_N113
+stratixiv_io_obuf \rx_dataout[0]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_recoverdataout [0]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[0]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[0]~output .bus_hold = "false";
+defparam \rx_dataout[0]~output .open_drain_output = "false";
+defparam \rx_dataout[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X50_Y0_N20
+stratixiv_io_obuf \rx_dataout[1]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_recoverdataout [1]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[1]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[1]~output .bus_hold = "false";
+defparam \rx_dataout[1]~output .open_drain_output = "false";
+defparam \rx_dataout[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X38_Y0_N20
+stratixiv_io_obuf \rx_dataout[2]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_recoverdataout [2]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[2]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[2]~output .bus_hold = "false";
+defparam \rx_dataout[2]~output .open_drain_output = "false";
+defparam \rx_dataout[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y22_N82
+stratixiv_io_obuf \rx_dataout[3]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_recoverdataout [3]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[3]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[3]~output .bus_hold = "false";
+defparam \rx_dataout[3]~output .open_drain_output = "false";
+defparam \rx_dataout[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X47_Y0_N20
+stratixiv_io_obuf \rx_dataout[4]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_recoverdataout [4]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[4]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[4]~output .bus_hold = "false";
+defparam \rx_dataout[4]~output .open_drain_output = "false";
+defparam \rx_dataout[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X45_Y0_N113
+stratixiv_io_obuf \rx_dataout[5]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_recoverdataout [5]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[5]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[5]~output .bus_hold = "false";
+defparam \rx_dataout[5]~output .open_drain_output = "false";
+defparam \rx_dataout[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X42_Y0_N20
+stratixiv_io_obuf \rx_dataout[6]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_recoverdataout [6]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[6]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[6]~output .bus_hold = "false";
+defparam \rx_dataout[6]~output .open_drain_output = "false";
+defparam \rx_dataout[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X31_Y0_N113
+stratixiv_io_obuf \rx_dataout[7]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_recoverdataout [7]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[7]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[7]~output .bus_hold = "false";
+defparam \rx_dataout[7]~output .open_drain_output = "false";
+defparam \rx_dataout[7]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X38_Y0_N51
+stratixiv_io_obuf \rx_dataout[8]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_recoverdataout [8]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[8]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[8]~output .bus_hold = "false";
+defparam \rx_dataout[8]~output .open_drain_output = "false";
+defparam \rx_dataout[8]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X11_Y0_N20
+stratixiv_io_obuf \rx_dataout[9]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_recoverdataout [9]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[9]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[9]~output .bus_hold = "false";
+defparam \rx_dataout[9]~output .open_drain_output = "false";
+defparam \rx_dataout[9]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X27_Y0_N20
+stratixiv_io_obuf \rx_dataout[10]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_recoverdataout [10]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[10]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[10]~output .bus_hold = "false";
+defparam \rx_dataout[10]~output .open_drain_output = "false";
+defparam \rx_dataout[10]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X25_Y0_N20
+stratixiv_io_obuf \rx_dataout[11]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_recoverdataout [11]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[11]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[11]~output .bus_hold = "false";
+defparam \rx_dataout[11]~output .open_drain_output = "false";
+defparam \rx_dataout[11]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X25_Y0_N82
+stratixiv_io_obuf \rx_dataout[12]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_recoverdataout [12]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[12]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[12]~output .bus_hold = "false";
+defparam \rx_dataout[12]~output .open_drain_output = "false";
+defparam \rx_dataout[12]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X45_Y0_N51
+stratixiv_io_obuf \rx_dataout[13]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_recoverdataout [13]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[13]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[13]~output .bus_hold = "false";
+defparam \rx_dataout[13]~output .open_drain_output = "false";
+defparam \rx_dataout[13]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X42_Y0_N113
+stratixiv_io_obuf \rx_dataout[14]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_recoverdataout [14]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[14]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[14]~output .bus_hold = "false";
+defparam \rx_dataout[14]~output .open_drain_output = "false";
+defparam \rx_dataout[14]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X57_Y0_N20
+stratixiv_io_obuf \rx_dataout[15]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_recoverdataout [15]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[15]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[15]~output .bus_hold = "false";
+defparam \rx_dataout[15]~output .open_drain_output = "false";
+defparam \rx_dataout[15]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X25_Y0_N51
+stratixiv_io_obuf \rx_dataout[16]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_recoverdataout [16]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[16]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[16]~output .bus_hold = "false";
+defparam \rx_dataout[16]~output .open_drain_output = "false";
+defparam \rx_dataout[16]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X38_Y0_N82
+stratixiv_io_obuf \rx_dataout[17]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_recoverdataout [17]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[17]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[17]~output .bus_hold = "false";
+defparam \rx_dataout[17]~output .open_drain_output = "false";
+defparam \rx_dataout[17]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X62_Y0_N51
+stratixiv_io_obuf \rx_dataout[18]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_recoverdataout [18]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[18]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[18]~output .bus_hold = "false";
+defparam \rx_dataout[18]~output .open_drain_output = "false";
+defparam \rx_dataout[18]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X59_Y0_N113
+stratixiv_io_obuf \rx_dataout[19]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_recoverdataout [19]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[19]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[19]~output .bus_hold = "false";
+defparam \rx_dataout[19]~output .open_drain_output = "false";
+defparam \rx_dataout[19]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X19_Y0_N82
+stratixiv_io_obuf \rx_dataout[20]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_recoverdataout [0]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[20]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[20]~output .bus_hold = "false";
+defparam \rx_dataout[20]~output .open_drain_output = "false";
+defparam \rx_dataout[20]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X62_Y0_N113
+stratixiv_io_obuf \rx_dataout[21]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_recoverdataout [1]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[21]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[21]~output .bus_hold = "false";
+defparam \rx_dataout[21]~output .open_drain_output = "false";
+defparam \rx_dataout[21]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X9_Y0_N113
+stratixiv_io_obuf \rx_dataout[22]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_recoverdataout [2]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[22]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[22]~output .bus_hold = "false";
+defparam \rx_dataout[22]~output .open_drain_output = "false";
+defparam \rx_dataout[22]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X31_Y0_N82
+stratixiv_io_obuf \rx_dataout[23]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_recoverdataout [3]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[23]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[23]~output .bus_hold = "false";
+defparam \rx_dataout[23]~output .open_drain_output = "false";
+defparam \rx_dataout[23]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X50_Y0_N82
+stratixiv_io_obuf \rx_dataout[24]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_recoverdataout [4]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[24]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[24]~output .bus_hold = "false";
+defparam \rx_dataout[24]~output .open_drain_output = "false";
+defparam \rx_dataout[24]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X27_Y0_N113
+stratixiv_io_obuf \rx_dataout[25]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_recoverdataout [5]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[25]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[25]~output .bus_hold = "false";
+defparam \rx_dataout[25]~output .open_drain_output = "false";
+defparam \rx_dataout[25]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X64_Y0_N20
+stratixiv_io_obuf \rx_dataout[26]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_recoverdataout [6]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[26]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[26]~output .bus_hold = "false";
+defparam \rx_dataout[26]~output .open_drain_output = "false";
+defparam \rx_dataout[26]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X45_Y0_N20
+stratixiv_io_obuf \rx_dataout[27]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_recoverdataout [7]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[27]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[27]~output .bus_hold = "false";
+defparam \rx_dataout[27]~output .open_drain_output = "false";
+defparam \rx_dataout[27]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X11_Y0_N113
+stratixiv_io_obuf \rx_dataout[28]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_recoverdataout [8]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[28]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[28]~output .bus_hold = "false";
+defparam \rx_dataout[28]~output .open_drain_output = "false";
+defparam \rx_dataout[28]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X22_Y0_N20
+stratixiv_io_obuf \rx_dataout[29]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_recoverdataout [9]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[29]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[29]~output .bus_hold = "false";
+defparam \rx_dataout[29]~output .open_drain_output = "false";
+defparam \rx_dataout[29]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X47_Y0_N82
+stratixiv_io_obuf \rx_dataout[30]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_recoverdataout [10]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[30]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[30]~output .bus_hold = "false";
+defparam \rx_dataout[30]~output .open_drain_output = "false";
+defparam \rx_dataout[30]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X39_Y0_N113
+stratixiv_io_obuf \rx_dataout[31]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_recoverdataout [11]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[31]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[31]~output .bus_hold = "false";
+defparam \rx_dataout[31]~output .open_drain_output = "false";
+defparam \rx_dataout[31]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X39_Y0_N82
+stratixiv_io_obuf \rx_dataout[32]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_recoverdataout [12]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[32]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[32]~output .bus_hold = "false";
+defparam \rx_dataout[32]~output .open_drain_output = "false";
+defparam \rx_dataout[32]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X62_Y0_N20
+stratixiv_io_obuf \rx_dataout[33]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_recoverdataout [13]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[33]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[33]~output .bus_hold = "false";
+defparam \rx_dataout[33]~output .open_drain_output = "false";
+defparam \rx_dataout[33]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X54_Y0_N20
+stratixiv_io_obuf \rx_dataout[34]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_recoverdataout [14]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[34]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[34]~output .bus_hold = "false";
+defparam \rx_dataout[34]~output .open_drain_output = "false";
+defparam \rx_dataout[34]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X50_Y0_N51
+stratixiv_io_obuf \rx_dataout[35]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_recoverdataout [15]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[35]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[35]~output .bus_hold = "false";
+defparam \rx_dataout[35]~output .open_drain_output = "false";
+defparam \rx_dataout[35]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X64_Y0_N82
+stratixiv_io_obuf \rx_dataout[36]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_recoverdataout [16]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[36]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[36]~output .bus_hold = "false";
+defparam \rx_dataout[36]~output .open_drain_output = "false";
+defparam \rx_dataout[36]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X25_Y0_N113
+stratixiv_io_obuf \rx_dataout[37]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_recoverdataout [17]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[37]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[37]~output .bus_hold = "false";
+defparam \rx_dataout[37]~output .open_drain_output = "false";
+defparam \rx_dataout[37]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X31_Y0_N20
+stratixiv_io_obuf \rx_dataout[38]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_recoverdataout [18]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[38]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[38]~output .bus_hold = "false";
+defparam \rx_dataout[38]~output .open_drain_output = "false";
+defparam \rx_dataout[38]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X36_Y0_N20
+stratixiv_io_obuf \rx_dataout[39]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_recoverdataout [19]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[39]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[39]~output .bus_hold = "false";
+defparam \rx_dataout[39]~output .open_drain_output = "false";
+defparam \rx_dataout[39]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y22_N20
+stratixiv_io_obuf \rx_dataout[40]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_recoverdataout [0]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[40]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[40]~output .bus_hold = "false";
+defparam \rx_dataout[40]~output .open_drain_output = "false";
+defparam \rx_dataout[40]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y30_N82
+stratixiv_io_obuf \rx_dataout[41]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_recoverdataout [1]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[41]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[41]~output .bus_hold = "false";
+defparam \rx_dataout[41]~output .open_drain_output = "false";
+defparam \rx_dataout[41]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y26_N51
+stratixiv_io_obuf \rx_dataout[42]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_recoverdataout [2]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[42]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[42]~output .bus_hold = "false";
+defparam \rx_dataout[42]~output .open_drain_output = "false";
+defparam \rx_dataout[42]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y52_N113
+stratixiv_io_obuf \rx_dataout[43]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_recoverdataout [3]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[43]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[43]~output .bus_hold = "false";
+defparam \rx_dataout[43]~output .open_drain_output = "false";
+defparam \rx_dataout[43]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y26_N82
+stratixiv_io_obuf \rx_dataout[44]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_recoverdataout [4]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[44]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[44]~output .bus_hold = "false";
+defparam \rx_dataout[44]~output .open_drain_output = "false";
+defparam \rx_dataout[44]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y30_N20
+stratixiv_io_obuf \rx_dataout[45]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_recoverdataout [5]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[45]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[45]~output .bus_hold = "false";
+defparam \rx_dataout[45]~output .open_drain_output = "false";
+defparam \rx_dataout[45]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y30_N51
+stratixiv_io_obuf \rx_dataout[46]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_recoverdataout [6]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[46]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[46]~output .bus_hold = "false";
+defparam \rx_dataout[46]~output .open_drain_output = "false";
+defparam \rx_dataout[46]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y47_N113
+stratixiv_io_obuf \rx_dataout[47]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_recoverdataout [7]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[47]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[47]~output .bus_hold = "false";
+defparam \rx_dataout[47]~output .open_drain_output = "false";
+defparam \rx_dataout[47]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y35_N113
+stratixiv_io_obuf \rx_dataout[48]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_recoverdataout [8]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[48]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[48]~output .bus_hold = "false";
+defparam \rx_dataout[48]~output .open_drain_output = "false";
+defparam \rx_dataout[48]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y31_N20
+stratixiv_io_obuf \rx_dataout[49]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_recoverdataout [9]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[49]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[49]~output .bus_hold = "false";
+defparam \rx_dataout[49]~output .open_drain_output = "false";
+defparam \rx_dataout[49]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y57_N20
+stratixiv_io_obuf \rx_dataout[50]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_recoverdataout [10]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[50]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[50]~output .bus_hold = "false";
+defparam \rx_dataout[50]~output .open_drain_output = "false";
+defparam \rx_dataout[50]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y52_N51
+stratixiv_io_obuf \rx_dataout[51]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_recoverdataout [11]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[51]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[51]~output .bus_hold = "false";
+defparam \rx_dataout[51]~output .open_drain_output = "false";
+defparam \rx_dataout[51]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y47_N82
+stratixiv_io_obuf \rx_dataout[52]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_recoverdataout [12]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[52]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[52]~output .bus_hold = "false";
+defparam \rx_dataout[52]~output .open_drain_output = "false";
+defparam \rx_dataout[52]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y54_N113
+stratixiv_io_obuf \rx_dataout[53]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_recoverdataout [13]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[53]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[53]~output .bus_hold = "false";
+defparam \rx_dataout[53]~output .open_drain_output = "false";
+defparam \rx_dataout[53]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y52_N20
+stratixiv_io_obuf \rx_dataout[54]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_recoverdataout [14]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[54]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[54]~output .bus_hold = "false";
+defparam \rx_dataout[54]~output .open_drain_output = "false";
+defparam \rx_dataout[54]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y26_N20
+stratixiv_io_obuf \rx_dataout[55]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_recoverdataout [15]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[55]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[55]~output .bus_hold = "false";
+defparam \rx_dataout[55]~output .open_drain_output = "false";
+defparam \rx_dataout[55]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y19_N51
+stratixiv_io_obuf \rx_dataout[56]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_recoverdataout [16]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[56]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[56]~output .bus_hold = "false";
+defparam \rx_dataout[56]~output .open_drain_output = "false";
+defparam \rx_dataout[56]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y35_N20
+stratixiv_io_obuf \rx_dataout[57]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_recoverdataout [17]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[57]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[57]~output .bus_hold = "false";
+defparam \rx_dataout[57]~output .open_drain_output = "false";
+defparam \rx_dataout[57]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y33_N20
+stratixiv_io_obuf \rx_dataout[58]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_recoverdataout [18]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[58]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[58]~output .bus_hold = "false";
+defparam \rx_dataout[58]~output .open_drain_output = "false";
+defparam \rx_dataout[58]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y35_N82
+stratixiv_io_obuf \rx_dataout[59]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_recoverdataout [19]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[59]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[59]~output .bus_hold = "false";
+defparam \rx_dataout[59]~output .open_drain_output = "false";
+defparam \rx_dataout[59]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y40_N51
+stratixiv_io_obuf \rx_dataout[60]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_recoverdataout [0]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[60]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[60]~output .bus_hold = "false";
+defparam \rx_dataout[60]~output .open_drain_output = "false";
+defparam \rx_dataout[60]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y40_N113
+stratixiv_io_obuf \rx_dataout[61]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_recoverdataout [1]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[61]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[61]~output .bus_hold = "false";
+defparam \rx_dataout[61]~output .open_drain_output = "false";
+defparam \rx_dataout[61]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y32_N2
+stratixiv_io_obuf \rx_dataout[62]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_recoverdataout [2]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[62]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[62]~output .bus_hold = "false";
+defparam \rx_dataout[62]~output .open_drain_output = "false";
+defparam \rx_dataout[62]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y26_N113
+stratixiv_io_obuf \rx_dataout[63]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_recoverdataout [3]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[63]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[63]~output .bus_hold = "false";
+defparam \rx_dataout[63]~output .open_drain_output = "false";
+defparam \rx_dataout[63]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y22_N51
+stratixiv_io_obuf \rx_dataout[64]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_recoverdataout [4]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[64]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[64]~output .bus_hold = "false";
+defparam \rx_dataout[64]~output .open_drain_output = "false";
+defparam \rx_dataout[64]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y38_N20
+stratixiv_io_obuf \rx_dataout[65]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_recoverdataout [5]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[65]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[65]~output .bus_hold = "false";
+defparam \rx_dataout[65]~output .open_drain_output = "false";
+defparam \rx_dataout[65]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y31_N82
+stratixiv_io_obuf \rx_dataout[66]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_recoverdataout [6]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[66]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[66]~output .bus_hold = "false";
+defparam \rx_dataout[66]~output .open_drain_output = "false";
+defparam \rx_dataout[66]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y19_N82
+stratixiv_io_obuf \rx_dataout[67]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_recoverdataout [7]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[67]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[67]~output .bus_hold = "false";
+defparam \rx_dataout[67]~output .open_drain_output = "false";
+defparam \rx_dataout[67]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y31_N113
+stratixiv_io_obuf \rx_dataout[68]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_recoverdataout [8]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[68]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[68]~output .bus_hold = "false";
+defparam \rx_dataout[68]~output .open_drain_output = "false";
+defparam \rx_dataout[68]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y28_N51
+stratixiv_io_obuf \rx_dataout[69]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_recoverdataout [9]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[69]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[69]~output .bus_hold = "false";
+defparam \rx_dataout[69]~output .open_drain_output = "false";
+defparam \rx_dataout[69]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y31_N51
+stratixiv_io_obuf \rx_dataout[70]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_recoverdataout [10]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[70]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[70]~output .bus_hold = "false";
+defparam \rx_dataout[70]~output .open_drain_output = "false";
+defparam \rx_dataout[70]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y38_N51
+stratixiv_io_obuf \rx_dataout[71]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_recoverdataout [11]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[71]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[71]~output .bus_hold = "false";
+defparam \rx_dataout[71]~output .open_drain_output = "false";
+defparam \rx_dataout[71]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y19_N113
+stratixiv_io_obuf \rx_dataout[72]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_recoverdataout [12]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[72]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[72]~output .bus_hold = "false";
+defparam \rx_dataout[72]~output .open_drain_output = "false";
+defparam \rx_dataout[72]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y32_N95
+stratixiv_io_obuf \rx_dataout[73]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_recoverdataout [13]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[73]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[73]~output .bus_hold = "false";
+defparam \rx_dataout[73]~output .open_drain_output = "false";
+defparam \rx_dataout[73]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y24_N51
+stratixiv_io_obuf \rx_dataout[74]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_recoverdataout [14]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[74]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[74]~output .bus_hold = "false";
+defparam \rx_dataout[74]~output .open_drain_output = "false";
+defparam \rx_dataout[74]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y24_N20
+stratixiv_io_obuf \rx_dataout[75]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_recoverdataout [15]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[75]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[75]~output .bus_hold = "false";
+defparam \rx_dataout[75]~output .open_drain_output = "false";
+defparam \rx_dataout[75]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y38_N113
+stratixiv_io_obuf \rx_dataout[76]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_recoverdataout [16]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[76]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[76]~output .bus_hold = "false";
+defparam \rx_dataout[76]~output .open_drain_output = "false";
+defparam \rx_dataout[76]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y19_N20
+stratixiv_io_obuf \rx_dataout[77]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_recoverdataout [17]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[77]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[77]~output .bus_hold = "false";
+defparam \rx_dataout[77]~output .open_drain_output = "false";
+defparam \rx_dataout[77]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y30_N113
+stratixiv_io_obuf \rx_dataout[78]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_recoverdataout [18]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[78]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[78]~output .bus_hold = "false";
+defparam \rx_dataout[78]~output .open_drain_output = "false";
+defparam \rx_dataout[78]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y38_N82
+stratixiv_io_obuf \rx_dataout[79]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_recoverdataout [19]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_dataout[79]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_dataout[79]~output .bus_hold = "false";
+defparam \rx_dataout[79]~output .open_drain_output = "false";
+defparam \rx_dataout[79]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X80_Y0_N64
+stratixiv_io_obuf \rx_clkout[0]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma0_clockout~clkctrl_outclk ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_clkout[0]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_clkout[0]~output .bus_hold = "false";
+defparam \rx_clkout[0]~output .open_drain_output = "false";
+defparam \rx_clkout[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X85_Y0_N64
+stratixiv_io_obuf \rx_clkout[1]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma1_clockout~clkctrl_outclk ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_clkout[1]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_clkout[1]~output .bus_hold = "false";
+defparam \rx_clkout[1]~output .open_drain_output = "false";
+defparam \rx_clkout[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X68_Y0_N20
+stratixiv_io_obuf \rx_clkout[2]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma2_clockout~clkctrl_outclk ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_clkout[2]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_clkout[2]~output .bus_hold = "false";
+defparam \rx_clkout[2]~output .open_drain_output = "false";
+defparam \rx_clkout[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X78_Y0_N2
+stratixiv_io_obuf \rx_clkout[3]~output (
+ .i(\pma_direct|auto_generated|wire_receive_pma3_clockout~clkctrl_outclk ),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_clkout[3]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_clkout[3]~output .bus_hold = "false";
+defparam \rx_clkout[3]~output .open_drain_output = "false";
+defparam \rx_clkout[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X33_Y0_N82
+stratixiv_io_obuf \rx_freqlocked[0]~output (
+ .i(\pma_direct|auto_generated|rx_freqlocked [0]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_freqlocked[0]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_freqlocked[0]~output .bus_hold = "false";
+defparam \rx_freqlocked[0]~output .open_drain_output = "false";
+defparam \rx_freqlocked[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X17_Y0_N113
+stratixiv_io_obuf \rx_freqlocked[1]~output (
+ .i(\pma_direct|auto_generated|rx_freqlocked [1]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_freqlocked[1]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_freqlocked[1]~output .bus_hold = "false";
+defparam \rx_freqlocked[1]~output .open_drain_output = "false";
+defparam \rx_freqlocked[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X14_Y0_N51
+stratixiv_io_obuf \rx_freqlocked[2]~output (
+ .i(\pma_direct|auto_generated|rx_freqlocked [2]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_freqlocked[2]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_freqlocked[2]~output .bus_hold = "false";
+defparam \rx_freqlocked[2]~output .open_drain_output = "false";
+defparam \rx_freqlocked[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X33_Y0_N51
+stratixiv_io_obuf \rx_freqlocked[3]~output (
+ .i(\pma_direct|auto_generated|rx_freqlocked [3]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_freqlocked[3]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_freqlocked[3]~output .bus_hold = "false";
+defparam \rx_freqlocked[3]~output .open_drain_output = "false";
+defparam \rx_freqlocked[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y15_N95
+stratixiv_io_obuf \rx_pll_locked[0]~output (
+ .i(\pma_direct|auto_generated|rx_pll_locked [0]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_pll_locked[0]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_pll_locked[0]~output .bus_hold = "false";
+defparam \rx_pll_locked[0]~output .open_drain_output = "false";
+defparam \rx_pll_locked[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X17_Y0_N82
+stratixiv_io_obuf \rx_pll_locked[1]~output (
+ .i(\pma_direct|auto_generated|rx_pll_locked [1]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_pll_locked[1]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_pll_locked[1]~output .bus_hold = "false";
+defparam \rx_pll_locked[1]~output .open_drain_output = "false";
+defparam \rx_pll_locked[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X185_Y15_N33
+stratixiv_io_obuf \rx_pll_locked[2]~output (
+ .i(\pma_direct|auto_generated|rx_pll_locked [2]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_pll_locked[2]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_pll_locked[2]~output .bus_hold = "false";
+defparam \rx_pll_locked[2]~output .open_drain_output = "false";
+defparam \rx_pll_locked[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X30_Y0_N82
+stratixiv_io_obuf \rx_pll_locked[3]~output (
+ .i(\pma_direct|auto_generated|rx_pll_locked [3]),
+ .oe(vcc),
+ .dynamicterminationcontrol(gnd),
+ .seriesterminationcontrol(14'b00000000000000),
+ .parallelterminationcontrol(14'b00000000000000),
+ .devoe(devoe),
+ .o(\rx_pll_locked[3]~output_o ),
+ .obar());
+// synopsys translate_off
+defparam \rx_pll_locked[3]~output .bus_hold = "false";
+defparam \rx_pll_locked[3]~output .open_drain_output = "false";
+defparam \rx_pll_locked[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X9_Y0_N32
+stratixiv_io_ibuf \gxb_powerdown~input (
+ .i(gxb_powerdown),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\gxb_powerdown~input_o ));
+// synopsys translate_off
+defparam \gxb_powerdown~input .bus_hold = "false";
+defparam \gxb_powerdown~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: CLKCTRL_G2
+stratixiv_clkena \reconfig_clk~inputclkctrl (
+ .inclk(\reconfig_clk~input_o ),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .outclk(\reconfig_clk~inputclkctrl_outclk ),
+ .enaout());
+// synopsys translate_off
+defparam \reconfig_clk~inputclkctrl .clock_type = "global clock";
+defparam \reconfig_clk~inputclkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: IOIBUF_X54_Y0_N32
+stratixiv_io_ibuf \cal_blk_powerdown~input (
+ .i(cal_blk_powerdown),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\cal_blk_powerdown~input_o ));
+// synopsys translate_off
+defparam \cal_blk_powerdown~input .bus_hold = "false";
+defparam \cal_blk_powerdown~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: CALIBRATIONBLOCK_X0_Y2_N135
+stratixiv_hssi_calibration_block \pma_direct|auto_generated|cal_blk0 (
+ .clk(\cal_blk_clk~input_o ),
+ .powerdn(\cal_blk_powerdown~input_o ),
+ .enabletestbus(vcc),
+ .testctrl(gnd),
+ .nonusertocmu(\pma_direct|auto_generated|nonusertocmu_out [0]),
+ .calibrationstatus(\pma_direct|auto_generated|cal_blk0_CALIBRATIONSTATUS_bus ));
+// synopsys translate_off
+defparam \pma_direct|auto_generated|cal_blk0 .cont_cal_mode = "false";
+defparam \pma_direct|auto_generated|cal_blk0 .enable_rx_cal_tw = "false";
+defparam \pma_direct|auto_generated|cal_blk0 .enable_tx_cal_tw = "false";
+defparam \pma_direct|auto_generated|cal_blk0 .rtest = "false";
+defparam \pma_direct|auto_generated|cal_blk0 .rx_cal_wt_value = 0;
+defparam \pma_direct|auto_generated|cal_blk0 .send_rx_cal_status = "false";
+defparam \pma_direct|auto_generated|cal_blk0 .tx_cal_wt_value = 1;
+// synopsys translate_on
+
+// Location: CLKCTRL_G3
+stratixiv_clkena \pll_inclk[0]~inputclkctrl (
+ .inclk(\pll_inclk[0]~input_o ),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .outclk(\pll_inclk[0]~inputclkctrl_outclk ),
+ .enaout());
+// synopsys translate_off
+defparam \pll_inclk[0]~inputclkctrl .clock_type = "global clock";
+defparam \pll_inclk[0]~inputclkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: HSSIPLL_X0_Y9_N135
+stratixiv_hssi_pll \pma_direct|auto_generated|tx_pll_edge0 (
+ .rateswitch(gnd),
+ .locktorefclk(vcc),
+ .datain(gnd),
+ .powerdown(\pma_direct|auto_generated|edge_pllpowerdn_in [0]),
+ .areset(\pma_direct|auto_generated|edge_pllreset_in [0]),
+ .dpriodisable(\pma_direct|auto_generated|edge_cmu_dpriodisableout [0]),
+ .earlyeios(gnd),
+ .pfdfbclk(gnd),
+ .inclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\pll_inclk[0]~inputclkctrl_outclk }),
+ .dprioin({\pma_direct|auto_generated|edge_pll_dprioin [299],\pma_direct|auto_generated|edge_pll_dprioin [298],\pma_direct|auto_generated|edge_pll_dprioin [297],\pma_direct|auto_generated|edge_pll_dprioin [296],\pma_direct|auto_generated|edge_pll_dprioin [295],
+\pma_direct|auto_generated|edge_pll_dprioin [294],\pma_direct|auto_generated|edge_pll_dprioin [293],\pma_direct|auto_generated|edge_pll_dprioin [292],\pma_direct|auto_generated|edge_pll_dprioin [291],\pma_direct|auto_generated|edge_pll_dprioin [290],
+\pma_direct|auto_generated|edge_pll_dprioin [289],\pma_direct|auto_generated|edge_pll_dprioin [288],\pma_direct|auto_generated|edge_pll_dprioin [287],\pma_direct|auto_generated|edge_pll_dprioin [286],\pma_direct|auto_generated|edge_pll_dprioin [285],
+\pma_direct|auto_generated|edge_pll_dprioin [284],\pma_direct|auto_generated|edge_pll_dprioin [283],\pma_direct|auto_generated|edge_pll_dprioin [282],\pma_direct|auto_generated|edge_pll_dprioin [281],\pma_direct|auto_generated|edge_pll_dprioin [280],
+\pma_direct|auto_generated|edge_pll_dprioin [279],\pma_direct|auto_generated|edge_pll_dprioin [278],\pma_direct|auto_generated|edge_pll_dprioin [277],\pma_direct|auto_generated|edge_pll_dprioin [276],\pma_direct|auto_generated|edge_pll_dprioin [275],
+\pma_direct|auto_generated|edge_pll_dprioin [274],\pma_direct|auto_generated|edge_pll_dprioin [273],\pma_direct|auto_generated|edge_pll_dprioin [272],\pma_direct|auto_generated|edge_pll_dprioin [271],\pma_direct|auto_generated|edge_pll_dprioin [270],
+\pma_direct|auto_generated|edge_pll_dprioin [269],\pma_direct|auto_generated|edge_pll_dprioin [268],\pma_direct|auto_generated|edge_pll_dprioin [267],\pma_direct|auto_generated|edge_pll_dprioin [266],\pma_direct|auto_generated|edge_pll_dprioin [265],
+\pma_direct|auto_generated|edge_pll_dprioin [264],\pma_direct|auto_generated|edge_pll_dprioin [263],\pma_direct|auto_generated|edge_pll_dprioin [262],\pma_direct|auto_generated|edge_pll_dprioin [261],\pma_direct|auto_generated|edge_pll_dprioin [260],
+\pma_direct|auto_generated|edge_pll_dprioin [259],\pma_direct|auto_generated|edge_pll_dprioin [258],\pma_direct|auto_generated|edge_pll_dprioin [257],\pma_direct|auto_generated|edge_pll_dprioin [256],\pma_direct|auto_generated|edge_pll_dprioin [255],
+\pma_direct|auto_generated|edge_pll_dprioin [254],\pma_direct|auto_generated|edge_pll_dprioin [253],\pma_direct|auto_generated|edge_pll_dprioin [252],\pma_direct|auto_generated|edge_pll_dprioin [251],\pma_direct|auto_generated|edge_pll_dprioin [250],
+\pma_direct|auto_generated|edge_pll_dprioin [249],\pma_direct|auto_generated|edge_pll_dprioin [248],\pma_direct|auto_generated|edge_pll_dprioin [247],\pma_direct|auto_generated|edge_pll_dprioin [246],\pma_direct|auto_generated|edge_pll_dprioin [245],
+\pma_direct|auto_generated|edge_pll_dprioin [244],\pma_direct|auto_generated|edge_pll_dprioin [243],\pma_direct|auto_generated|edge_pll_dprioin [242],\pma_direct|auto_generated|edge_pll_dprioin [241],\pma_direct|auto_generated|edge_pll_dprioin [240],
+\pma_direct|auto_generated|edge_pll_dprioin [239],\pma_direct|auto_generated|edge_pll_dprioin [238],\pma_direct|auto_generated|edge_pll_dprioin [237],\pma_direct|auto_generated|edge_pll_dprioin [236],\pma_direct|auto_generated|edge_pll_dprioin [235],
+\pma_direct|auto_generated|edge_pll_dprioin [234],\pma_direct|auto_generated|edge_pll_dprioin [233],\pma_direct|auto_generated|edge_pll_dprioin [232],\pma_direct|auto_generated|edge_pll_dprioin [231],\pma_direct|auto_generated|edge_pll_dprioin [230],
+\pma_direct|auto_generated|edge_pll_dprioin [229],\pma_direct|auto_generated|edge_pll_dprioin [228],\pma_direct|auto_generated|edge_pll_dprioin [227],\pma_direct|auto_generated|edge_pll_dprioin [226],\pma_direct|auto_generated|edge_pll_dprioin [225],
+\pma_direct|auto_generated|edge_pll_dprioin [224],\pma_direct|auto_generated|edge_pll_dprioin [223],\pma_direct|auto_generated|edge_pll_dprioin [222],\pma_direct|auto_generated|edge_pll_dprioin [221],\pma_direct|auto_generated|edge_pll_dprioin [220],
+\pma_direct|auto_generated|edge_pll_dprioin [219],\pma_direct|auto_generated|edge_pll_dprioin [218],\pma_direct|auto_generated|edge_pll_dprioin [217],\pma_direct|auto_generated|edge_pll_dprioin [216],\pma_direct|auto_generated|edge_pll_dprioin [215],
+\pma_direct|auto_generated|edge_pll_dprioin [214],\pma_direct|auto_generated|edge_pll_dprioin [213],\pma_direct|auto_generated|edge_pll_dprioin [212],\pma_direct|auto_generated|edge_pll_dprioin [211],\pma_direct|auto_generated|edge_pll_dprioin [210],
+\pma_direct|auto_generated|edge_pll_dprioin [209],\pma_direct|auto_generated|edge_pll_dprioin [208],\pma_direct|auto_generated|edge_pll_dprioin [207],\pma_direct|auto_generated|edge_pll_dprioin [206],\pma_direct|auto_generated|edge_pll_dprioin [205],
+\pma_direct|auto_generated|edge_pll_dprioin [204],\pma_direct|auto_generated|edge_pll_dprioin [203],\pma_direct|auto_generated|edge_pll_dprioin [202],\pma_direct|auto_generated|edge_pll_dprioin [201],\pma_direct|auto_generated|edge_pll_dprioin [200],
+\pma_direct|auto_generated|edge_pll_dprioin [199],\pma_direct|auto_generated|edge_pll_dprioin [198],\pma_direct|auto_generated|edge_pll_dprioin [197],\pma_direct|auto_generated|edge_pll_dprioin [196],\pma_direct|auto_generated|edge_pll_dprioin [195],
+\pma_direct|auto_generated|edge_pll_dprioin [194],\pma_direct|auto_generated|edge_pll_dprioin [193],\pma_direct|auto_generated|edge_pll_dprioin [192],\pma_direct|auto_generated|edge_pll_dprioin [191],\pma_direct|auto_generated|edge_pll_dprioin [190],
+\pma_direct|auto_generated|edge_pll_dprioin [189],\pma_direct|auto_generated|edge_pll_dprioin [188],\pma_direct|auto_generated|edge_pll_dprioin [187],\pma_direct|auto_generated|edge_pll_dprioin [186],\pma_direct|auto_generated|edge_pll_dprioin [185],
+\pma_direct|auto_generated|edge_pll_dprioin [184],\pma_direct|auto_generated|edge_pll_dprioin [183],\pma_direct|auto_generated|edge_pll_dprioin [182],\pma_direct|auto_generated|edge_pll_dprioin [181],\pma_direct|auto_generated|edge_pll_dprioin [180],
+\pma_direct|auto_generated|edge_pll_dprioin [179],\pma_direct|auto_generated|edge_pll_dprioin [178],\pma_direct|auto_generated|edge_pll_dprioin [177],\pma_direct|auto_generated|edge_pll_dprioin [176],\pma_direct|auto_generated|edge_pll_dprioin [175],
+\pma_direct|auto_generated|edge_pll_dprioin [174],\pma_direct|auto_generated|edge_pll_dprioin [173],\pma_direct|auto_generated|edge_pll_dprioin [172],\pma_direct|auto_generated|edge_pll_dprioin [171],\pma_direct|auto_generated|edge_pll_dprioin [170],
+\pma_direct|auto_generated|edge_pll_dprioin [169],\pma_direct|auto_generated|edge_pll_dprioin [168],\pma_direct|auto_generated|edge_pll_dprioin [167],\pma_direct|auto_generated|edge_pll_dprioin [166],\pma_direct|auto_generated|edge_pll_dprioin [165],
+\pma_direct|auto_generated|edge_pll_dprioin [164],\pma_direct|auto_generated|edge_pll_dprioin [163],\pma_direct|auto_generated|edge_pll_dprioin [162],\pma_direct|auto_generated|edge_pll_dprioin [161],\pma_direct|auto_generated|edge_pll_dprioin [160],
+\pma_direct|auto_generated|edge_pll_dprioin [159],\pma_direct|auto_generated|edge_pll_dprioin [158],\pma_direct|auto_generated|edge_pll_dprioin [157],\pma_direct|auto_generated|edge_pll_dprioin [156],\pma_direct|auto_generated|edge_pll_dprioin [155],
+\pma_direct|auto_generated|edge_pll_dprioin [154],\pma_direct|auto_generated|edge_pll_dprioin [153],\pma_direct|auto_generated|edge_pll_dprioin [152],\pma_direct|auto_generated|edge_pll_dprioin [151],\pma_direct|auto_generated|edge_pll_dprioin [150],
+\pma_direct|auto_generated|edge_pll_dprioin [149],\pma_direct|auto_generated|edge_pll_dprioin [148],\pma_direct|auto_generated|edge_pll_dprioin [147],\pma_direct|auto_generated|edge_pll_dprioin [146],\pma_direct|auto_generated|edge_pll_dprioin [145],
+\pma_direct|auto_generated|edge_pll_dprioin [144],\pma_direct|auto_generated|edge_pll_dprioin [143],\pma_direct|auto_generated|edge_pll_dprioin [142],\pma_direct|auto_generated|edge_pll_dprioin [141],\pma_direct|auto_generated|edge_pll_dprioin [140],
+\pma_direct|auto_generated|edge_pll_dprioin [139],\pma_direct|auto_generated|edge_pll_dprioin [138],\pma_direct|auto_generated|edge_pll_dprioin [137],\pma_direct|auto_generated|edge_pll_dprioin [136],\pma_direct|auto_generated|edge_pll_dprioin [135],
+\pma_direct|auto_generated|edge_pll_dprioin [134],\pma_direct|auto_generated|edge_pll_dprioin [133],\pma_direct|auto_generated|edge_pll_dprioin [132],\pma_direct|auto_generated|edge_pll_dprioin [131],\pma_direct|auto_generated|edge_pll_dprioin [130],
+\pma_direct|auto_generated|edge_pll_dprioin [129],\pma_direct|auto_generated|edge_pll_dprioin [128],\pma_direct|auto_generated|edge_pll_dprioin [127],\pma_direct|auto_generated|edge_pll_dprioin [126],\pma_direct|auto_generated|edge_pll_dprioin [125],
+\pma_direct|auto_generated|edge_pll_dprioin [124],\pma_direct|auto_generated|edge_pll_dprioin [123],\pma_direct|auto_generated|edge_pll_dprioin [122],\pma_direct|auto_generated|edge_pll_dprioin [121],\pma_direct|auto_generated|edge_pll_dprioin [120],
+\pma_direct|auto_generated|edge_pll_dprioin [119],\pma_direct|auto_generated|edge_pll_dprioin [118],\pma_direct|auto_generated|edge_pll_dprioin [117],\pma_direct|auto_generated|edge_pll_dprioin [116],\pma_direct|auto_generated|edge_pll_dprioin [115],
+\pma_direct|auto_generated|edge_pll_dprioin [114],\pma_direct|auto_generated|edge_pll_dprioin [113],\pma_direct|auto_generated|edge_pll_dprioin [112],\pma_direct|auto_generated|edge_pll_dprioin [111],\pma_direct|auto_generated|edge_pll_dprioin [110],
+\pma_direct|auto_generated|edge_pll_dprioin [109],\pma_direct|auto_generated|edge_pll_dprioin [108],\pma_direct|auto_generated|edge_pll_dprioin [107],\pma_direct|auto_generated|edge_pll_dprioin [106],\pma_direct|auto_generated|edge_pll_dprioin [105],
+\pma_direct|auto_generated|edge_pll_dprioin [104],\pma_direct|auto_generated|edge_pll_dprioin [103],\pma_direct|auto_generated|edge_pll_dprioin [102],\pma_direct|auto_generated|edge_pll_dprioin [101],\pma_direct|auto_generated|edge_pll_dprioin [100],
+\pma_direct|auto_generated|edge_pll_dprioin [99],\pma_direct|auto_generated|edge_pll_dprioin [98],\pma_direct|auto_generated|edge_pll_dprioin [97],\pma_direct|auto_generated|edge_pll_dprioin [96],\pma_direct|auto_generated|edge_pll_dprioin [95],
+\pma_direct|auto_generated|edge_pll_dprioin [94],\pma_direct|auto_generated|edge_pll_dprioin [93],\pma_direct|auto_generated|edge_pll_dprioin [92],\pma_direct|auto_generated|edge_pll_dprioin [91],\pma_direct|auto_generated|edge_pll_dprioin [90],
+\pma_direct|auto_generated|edge_pll_dprioin [89],\pma_direct|auto_generated|edge_pll_dprioin [88],\pma_direct|auto_generated|edge_pll_dprioin [87],\pma_direct|auto_generated|edge_pll_dprioin [86],\pma_direct|auto_generated|edge_pll_dprioin [85],
+\pma_direct|auto_generated|edge_pll_dprioin [84],\pma_direct|auto_generated|edge_pll_dprioin [83],\pma_direct|auto_generated|edge_pll_dprioin [82],\pma_direct|auto_generated|edge_pll_dprioin [81],\pma_direct|auto_generated|edge_pll_dprioin [80],
+\pma_direct|auto_generated|edge_pll_dprioin [79],\pma_direct|auto_generated|edge_pll_dprioin [78],\pma_direct|auto_generated|edge_pll_dprioin [77],\pma_direct|auto_generated|edge_pll_dprioin [76],\pma_direct|auto_generated|edge_pll_dprioin [75],
+\pma_direct|auto_generated|edge_pll_dprioin [74],\pma_direct|auto_generated|edge_pll_dprioin [73],\pma_direct|auto_generated|edge_pll_dprioin [72],\pma_direct|auto_generated|edge_pll_dprioin [71],\pma_direct|auto_generated|edge_pll_dprioin [70],
+\pma_direct|auto_generated|edge_pll_dprioin [69],\pma_direct|auto_generated|edge_pll_dprioin [68],\pma_direct|auto_generated|edge_pll_dprioin [67],\pma_direct|auto_generated|edge_pll_dprioin [66],\pma_direct|auto_generated|edge_pll_dprioin [65],
+\pma_direct|auto_generated|edge_pll_dprioin [64],\pma_direct|auto_generated|edge_pll_dprioin [63],\pma_direct|auto_generated|edge_pll_dprioin [62],\pma_direct|auto_generated|edge_pll_dprioin [61],\pma_direct|auto_generated|edge_pll_dprioin [60],
+\pma_direct|auto_generated|edge_pll_dprioin [59],\pma_direct|auto_generated|edge_pll_dprioin [58],\pma_direct|auto_generated|edge_pll_dprioin [57],\pma_direct|auto_generated|edge_pll_dprioin [56],\pma_direct|auto_generated|edge_pll_dprioin [55],
+\pma_direct|auto_generated|edge_pll_dprioin [54],\pma_direct|auto_generated|edge_pll_dprioin [53],\pma_direct|auto_generated|edge_pll_dprioin [52],\pma_direct|auto_generated|edge_pll_dprioin [51],\pma_direct|auto_generated|edge_pll_dprioin [50],
+\pma_direct|auto_generated|edge_pll_dprioin [49],\pma_direct|auto_generated|edge_pll_dprioin [48],\pma_direct|auto_generated|edge_pll_dprioin [47],\pma_direct|auto_generated|edge_pll_dprioin [46],\pma_direct|auto_generated|edge_pll_dprioin [45],
+\pma_direct|auto_generated|edge_pll_dprioin [44],\pma_direct|auto_generated|edge_pll_dprioin [43],\pma_direct|auto_generated|edge_pll_dprioin [42],\pma_direct|auto_generated|edge_pll_dprioin [41],\pma_direct|auto_generated|edge_pll_dprioin [40],
+\pma_direct|auto_generated|edge_pll_dprioin [39],\pma_direct|auto_generated|edge_pll_dprioin [38],\pma_direct|auto_generated|edge_pll_dprioin [37],\pma_direct|auto_generated|edge_pll_dprioin [36],\pma_direct|auto_generated|edge_pll_dprioin [35],
+\pma_direct|auto_generated|edge_pll_dprioin [34],\pma_direct|auto_generated|edge_pll_dprioin [33],\pma_direct|auto_generated|edge_pll_dprioin [32],\pma_direct|auto_generated|edge_pll_dprioin [31],\pma_direct|auto_generated|edge_pll_dprioin [30],
+\pma_direct|auto_generated|edge_pll_dprioin [29],\pma_direct|auto_generated|edge_pll_dprioin [28],\pma_direct|auto_generated|edge_pll_dprioin [27],\pma_direct|auto_generated|edge_pll_dprioin [26],\pma_direct|auto_generated|edge_pll_dprioin [25],
+\pma_direct|auto_generated|edge_pll_dprioin [24],\pma_direct|auto_generated|edge_pll_dprioin [23],\pma_direct|auto_generated|edge_pll_dprioin [22],\pma_direct|auto_generated|edge_pll_dprioin [21],\pma_direct|auto_generated|edge_pll_dprioin [20],
+\pma_direct|auto_generated|edge_pll_dprioin [19],\pma_direct|auto_generated|edge_pll_dprioin [18],\pma_direct|auto_generated|edge_pll_dprioin [17],\pma_direct|auto_generated|edge_pll_dprioin [16],\pma_direct|auto_generated|edge_pll_dprioin [15],
+\pma_direct|auto_generated|edge_pll_dprioin [14],\pma_direct|auto_generated|edge_pll_dprioin [13],\pma_direct|auto_generated|edge_pll_dprioin [12],\pma_direct|auto_generated|edge_pll_dprioin [11],\pma_direct|auto_generated|edge_pll_dprioin [10],
+\pma_direct|auto_generated|edge_pll_dprioin [9],\pma_direct|auto_generated|edge_pll_dprioin [8],\pma_direct|auto_generated|edge_pll_dprioin [7],\pma_direct|auto_generated|edge_pll_dprioin [6],\pma_direct|auto_generated|edge_pll_dprioin [5],
+\pma_direct|auto_generated|edge_pll_dprioin [4],\pma_direct|auto_generated|edge_pll_dprioin [3],\pma_direct|auto_generated|edge_pll_dprioin [2],\pma_direct|auto_generated|edge_pll_dprioin [1],\pma_direct|auto_generated|edge_pll_dprioin [0]}),
+ .extra10gin(6'b000000),
+ .pfdfbclkout(),
+ .pfdrefclkout(),
+ .vcobypassout(),
+ .locked(\pma_direct|auto_generated|pll_locked [0]),
+ .freqlocked(),
+ .clk(\pma_direct|auto_generated|tx_pll_edge0_CLK_bus ),
+ .dataout(\pma_direct|auto_generated|tx_pll_edge0_DATAOUT_bus ),
+ .dprioout(\pma_direct|auto_generated|tx_pll_edge0_DPRIOOUT_bus ));
+// synopsys translate_off
+defparam \pma_direct|auto_generated|tx_pll_edge0 .auto_settings = "true";
+defparam \pma_direct|auto_generated|tx_pll_edge0 .bandwidth_type = "high";
+defparam \pma_direct|auto_generated|tx_pll_edge0 .base_data_rate = "3125.0 mbps";
+defparam \pma_direct|auto_generated|tx_pll_edge0 .channel_num = 4;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .charge_pump_current_bits = 30;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .charge_pump_mode_bits = 0;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .charge_pump_test_enable = "false";
+defparam \pma_direct|auto_generated|tx_pll_edge0 .dprio_config_mode = 6'b000000;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .effective_data_rate = "0 ps";
+defparam \pma_direct|auto_generated|tx_pll_edge0 .enable_dynamic_divider = "false";
+defparam \pma_direct|auto_generated|tx_pll_edge0 .fast_lock_control = "false";
+defparam \pma_direct|auto_generated|tx_pll_edge0 .inclk0_input_period = 6400;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .inclk1_input_period = 0;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .inclk2_input_period = 0;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .inclk3_input_period = 0;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .inclk4_input_period = 0;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .inclk5_input_period = 0;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .inclk6_input_period = 0;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .inclk7_input_period = 0;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .inclk8_input_period = 0;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .inclk9_input_period = 0;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .input_clock_frequency = "156.25 mhz";
+defparam \pma_direct|auto_generated|tx_pll_edge0 .logical_channel_address = 16;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .logical_tx_pll_number = 0;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .loop_filter_c_bits = 0;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .loop_filter_r_bits = 3200;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .m = 10;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .n = 1;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .pd_charge_pump_current_bits = 5;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .pd_loop_filter_r_bits = 300;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .pfd_clk_select = 0;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .pfd_fb_select = "internal";
+defparam \pma_direct|auto_generated|tx_pll_edge0 .pll_type = "cmu";
+defparam \pma_direct|auto_generated|tx_pll_edge0 .sim_is_negative_ppm_drift = "false";
+defparam \pma_direct|auto_generated|tx_pll_edge0 .sim_net_ppm_variation = 0;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .test_charge_pump_current_down = "false";
+defparam \pma_direct|auto_generated|tx_pll_edge0 .test_charge_pump_current_up = "false";
+defparam \pma_direct|auto_generated|tx_pll_edge0 .vco_data_rate = 0;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .vco_post_scale = 2;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .vco_range = "high";
+defparam \pma_direct|auto_generated|tx_pll_edge0 .volt_reg_control_bits = 2;
+defparam \pma_direct|auto_generated|tx_pll_edge0 .volt_reg_output_bits = 0;
+// synopsys translate_on
+
+// Location: IOIBUF_X9_Y0_N1
+stratixiv_io_ibuf \pll_powerdown~input (
+ .i(pll_powerdown),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\pll_powerdown~input_o ));
+// synopsys translate_off
+defparam \pll_powerdown~input .bus_hold = "false";
+defparam \pll_powerdown~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X17_Y0_N1
+stratixiv_io_ibuf \rx_analogreset[0]~input (
+ .i(rx_analogreset[0]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[0]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[0]~input .bus_hold = "false";
+defparam \rx_analogreset[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X5_Y12_N18
+stratixiv_lcell_comb \pma_direct|auto_generated|rx_analogreset_in[0] (
+// Equation(s):
+// \pma_direct|auto_generated|rx_analogreset_in [0] = (!\reconfig_togxb[3]~input_o & \rx_analogreset[0]~input_o )
+
+ .dataa(!\reconfig_togxb[3]~input_o ),
+ .datab(gnd),
+ .datac(!\rx_analogreset[0]~input_o ),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\pma_direct|auto_generated|rx_analogreset_in [0]),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|rx_analogreset_in[0] .extended_lut = "off";
+defparam \pma_direct|auto_generated|rx_analogreset_in[0] .lut_mask = 64'h0A0A0A0A0A0A0A0A;
+defparam \pma_direct|auto_generated|rx_analogreset_in[0] .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X30_Y0_N94
+stratixiv_io_ibuf \rx_analogreset[1]~input (
+ .i(rx_analogreset[1]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[1]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[1]~input .bus_hold = "false";
+defparam \rx_analogreset[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X5_Y12_N16
+stratixiv_lcell_comb \pma_direct|auto_generated|rx_analogreset_in[1] (
+// Equation(s):
+// \pma_direct|auto_generated|rx_analogreset_in [1] = (!\reconfig_togxb[3]~input_o & \rx_analogreset[1]~input_o )
+
+ .dataa(!\reconfig_togxb[3]~input_o ),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\rx_analogreset[1]~input_o ),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\pma_direct|auto_generated|rx_analogreset_in [1]),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|rx_analogreset_in[1] .extended_lut = "off";
+defparam \pma_direct|auto_generated|rx_analogreset_in[1] .lut_mask = 64'h00AA00AA00AA00AA;
+defparam \pma_direct|auto_generated|rx_analogreset_in[1] .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X33_Y0_N94
+stratixiv_io_ibuf \rx_analogreset[2]~input (
+ .i(rx_analogreset[2]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[2]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[2]~input .bus_hold = "false";
+defparam \rx_analogreset[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X5_Y12_N10
+stratixiv_lcell_comb \pma_direct|auto_generated|rx_analogreset_in[2] (
+// Equation(s):
+// \pma_direct|auto_generated|rx_analogreset_in [2] = ( \rx_analogreset[2]~input_o & ( !\reconfig_togxb[3]~input_o ) )
+
+ .dataa(!\reconfig_togxb[3]~input_o ),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(!\rx_analogreset[2]~input_o ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\pma_direct|auto_generated|rx_analogreset_in [2]),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|rx_analogreset_in[2] .extended_lut = "off";
+defparam \pma_direct|auto_generated|rx_analogreset_in[2] .lut_mask = 64'h00000000AAAAAAAA;
+defparam \pma_direct|auto_generated|rx_analogreset_in[2] .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X36_Y0_N63
+stratixiv_io_ibuf \rx_analogreset[3]~input (
+ .i(rx_analogreset[3]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[3]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[3]~input .bus_hold = "false";
+defparam \rx_analogreset[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X5_Y12_N8
+stratixiv_lcell_comb \pma_direct|auto_generated|rx_analogreset_in[3] (
+// Equation(s):
+// \pma_direct|auto_generated|rx_analogreset_in [3] = (!\reconfig_togxb[3]~input_o & \rx_analogreset[3]~input_o )
+
+ .dataa(!\reconfig_togxb[3]~input_o ),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\rx_analogreset[3]~input_o ),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\pma_direct|auto_generated|rx_analogreset_in [3]),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|rx_analogreset_in[3] .extended_lut = "off";
+defparam \pma_direct|auto_generated|rx_analogreset_in[3] .lut_mask = 64'h00AA00AA00AA00AA;
+defparam \pma_direct|auto_generated|rx_analogreset_in[3] .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X14_Y0_N63
+stratixiv_io_ibuf \rx_locktodata[0]~input (
+ .i(rx_locktodata[0]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[0]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[0]~input .bus_hold = "false";
+defparam \rx_locktodata[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X5_Y12_N2
+stratixiv_lcell_comb \pma_direct|auto_generated|rx_locktodata_wire[0] (
+// Equation(s):
+// \pma_direct|auto_generated|rx_locktodata_wire [0] = (!\reconfig_togxb[3]~input_o & \rx_locktodata[0]~input_o )
+
+ .dataa(!\reconfig_togxb[3]~input_o ),
+ .datab(gnd),
+ .datac(!\rx_locktodata[0]~input_o ),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\pma_direct|auto_generated|rx_locktodata_wire [0]),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|rx_locktodata_wire[0] .extended_lut = "off";
+defparam \pma_direct|auto_generated|rx_locktodata_wire[0] .lut_mask = 64'h0A0A0A0A0A0A0A0A;
+defparam \pma_direct|auto_generated|rx_locktodata_wire[0] .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X14_Y0_N1
+stratixiv_io_ibuf \rx_locktorefclk[0]~input (
+ .i(rx_locktorefclk[0]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[0]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[0]~input .bus_hold = "false";
+defparam \rx_locktorefclk[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X5_Y12_N0
+stratixiv_lcell_comb \pma_direct|auto_generated|comb~0 (
+// Equation(s):
+// \pma_direct|auto_generated|comb~0_combout = ( \rx_locktorefclk[0]~input_o ) # ( !\rx_locktorefclk[0]~input_o & ( \reconfig_togxb[3]~input_o ) )
+
+ .dataa(!\reconfig_togxb[3]~input_o ),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(!\rx_locktorefclk[0]~input_o ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\pma_direct|auto_generated|comb~0_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|comb~0 .extended_lut = "off";
+defparam \pma_direct|auto_generated|comb~0 .lut_mask = 64'h55555555FFFFFFFF;
+defparam \pma_direct|auto_generated|comb~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y3_N146
+stratixiv_io_ibuf \rx_datain[0]~input (
+ .i(rx_datain[0]),
+ .ibar(\rx_datain[0](n)~padout ),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_datain[0]~input_o ));
+// synopsys translate_off
+defparam \rx_datain[0]~input .bus_hold = "false";
+defparam \rx_datain[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X30_Y0_N1
+stratixiv_io_ibuf \rx_locktodata[1]~input (
+ .i(rx_locktodata[1]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[1]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[1]~input .bus_hold = "false";
+defparam \rx_locktodata[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X5_Y12_N24
+stratixiv_lcell_comb \pma_direct|auto_generated|rx_locktodata_wire[1] (
+// Equation(s):
+// \pma_direct|auto_generated|rx_locktodata_wire [1] = (!\reconfig_togxb[3]~input_o & \rx_locktodata[1]~input_o )
+
+ .dataa(!\reconfig_togxb[3]~input_o ),
+ .datab(gnd),
+ .datac(!\rx_locktodata[1]~input_o ),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\pma_direct|auto_generated|rx_locktodata_wire [1]),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|rx_locktodata_wire[1] .extended_lut = "off";
+defparam \pma_direct|auto_generated|rx_locktodata_wire[1] .lut_mask = 64'h0A0A0A0A0A0A0A0A;
+defparam \pma_direct|auto_generated|rx_locktodata_wire[1] .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X30_Y0_N32
+stratixiv_io_ibuf \rx_locktorefclk[1]~input (
+ .i(rx_locktorefclk[1]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[1]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[1]~input .bus_hold = "false";
+defparam \rx_locktorefclk[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X5_Y12_N26
+stratixiv_lcell_comb \pma_direct|auto_generated|comb~1 (
+// Equation(s):
+// \pma_direct|auto_generated|comb~1_combout = (\rx_locktorefclk[1]~input_o ) # (\reconfig_togxb[3]~input_o )
+
+ .dataa(!\reconfig_togxb[3]~input_o ),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\rx_locktorefclk[1]~input_o ),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\pma_direct|auto_generated|comb~1_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|comb~1 .extended_lut = "off";
+defparam \pma_direct|auto_generated|comb~1 .lut_mask = 64'h55FF55FF55FF55FF;
+defparam \pma_direct|auto_generated|comb~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y6_N146
+stratixiv_io_ibuf \rx_datain[1]~input (
+ .i(rx_datain[1]),
+ .ibar(\rx_datain[1](n)~padout ),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_datain[1]~input_o ));
+// synopsys translate_off
+defparam \rx_datain[1]~input .bus_hold = "false";
+defparam \rx_datain[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y16_N32
+stratixiv_io_ibuf \rx_locktodata[2]~input (
+ .i(rx_locktodata[2]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[2]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[2]~input .bus_hold = "false";
+defparam \rx_locktodata[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X5_Y12_N34
+stratixiv_lcell_comb \pma_direct|auto_generated|rx_locktodata_wire[2] (
+// Equation(s):
+// \pma_direct|auto_generated|rx_locktodata_wire [2] = (!\reconfig_togxb[3]~input_o & \rx_locktodata[2]~input_o )
+
+ .dataa(!\reconfig_togxb[3]~input_o ),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\rx_locktodata[2]~input_o ),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\pma_direct|auto_generated|rx_locktodata_wire [2]),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|rx_locktodata_wire[2] .extended_lut = "off";
+defparam \pma_direct|auto_generated|rx_locktodata_wire[2] .lut_mask = 64'h00AA00AA00AA00AA;
+defparam \pma_direct|auto_generated|rx_locktodata_wire[2] .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X14_Y0_N94
+stratixiv_io_ibuf \rx_locktorefclk[2]~input (
+ .i(rx_locktorefclk[2]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[2]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[2]~input .bus_hold = "false";
+defparam \rx_locktorefclk[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X5_Y12_N32
+stratixiv_lcell_comb \pma_direct|auto_generated|comb~2 (
+// Equation(s):
+// \pma_direct|auto_generated|comb~2_combout = (\rx_locktorefclk[2]~input_o ) # (\reconfig_togxb[3]~input_o )
+
+ .dataa(!\reconfig_togxb[3]~input_o ),
+ .datab(gnd),
+ .datac(!\rx_locktorefclk[2]~input_o ),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\pma_direct|auto_generated|comb~2_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|comb~2 .extended_lut = "off";
+defparam \pma_direct|auto_generated|comb~2 .lut_mask = 64'h5F5F5F5F5F5F5F5F;
+defparam \pma_direct|auto_generated|comb~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y15_N146
+stratixiv_io_ibuf \rx_datain[2]~input (
+ .i(rx_datain[2]),
+ .ibar(\rx_datain[2](n)~padout ),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_datain[2]~input_o ));
+// synopsys translate_off
+defparam \rx_datain[2]~input .bus_hold = "false";
+defparam \rx_datain[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X17_Y0_N32
+stratixiv_io_ibuf \rx_locktodata[3]~input (
+ .i(rx_locktodata[3]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[3]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[3]~input .bus_hold = "false";
+defparam \rx_locktodata[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X5_Y12_N36
+stratixiv_lcell_comb \pma_direct|auto_generated|rx_locktodata_wire[3] (
+// Equation(s):
+// \pma_direct|auto_generated|rx_locktodata_wire [3] = (!\reconfig_togxb[3]~input_o & \rx_locktodata[3]~input_o )
+
+ .dataa(!\reconfig_togxb[3]~input_o ),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(!\rx_locktodata[3]~input_o ),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\pma_direct|auto_generated|rx_locktodata_wire [3]),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|rx_locktodata_wire[3] .extended_lut = "off";
+defparam \pma_direct|auto_generated|rx_locktodata_wire[3] .lut_mask = 64'h00AA00AA00AA00AA;
+defparam \pma_direct|auto_generated|rx_locktodata_wire[3] .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X33_Y0_N1
+stratixiv_io_ibuf \rx_locktorefclk[3]~input (
+ .i(rx_locktorefclk[3]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[3]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[3]~input .bus_hold = "false";
+defparam \rx_locktorefclk[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X5_Y12_N38
+stratixiv_lcell_comb \pma_direct|auto_generated|comb~3 (
+// Equation(s):
+// \pma_direct|auto_generated|comb~3_combout = ( \rx_locktorefclk[3]~input_o ) # ( !\rx_locktorefclk[3]~input_o & ( \reconfig_togxb[3]~input_o ) )
+
+ .dataa(!\reconfig_togxb[3]~input_o ),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(!\rx_locktorefclk[3]~input_o ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\pma_direct|auto_generated|comb~3_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|comb~3 .extended_lut = "off";
+defparam \pma_direct|auto_generated|comb~3 .lut_mask = 64'h55555555FFFFFFFF;
+defparam \pma_direct|auto_generated|comb~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y18_N146
+stratixiv_io_ibuf \rx_datain[3]~input (
+ .i(rx_datain[3]),
+ .ibar(\rx_datain[3](n)~padout ),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_datain[3]~input_o ));
+// synopsys translate_off
+defparam \rx_datain[3]~input .bus_hold = "false";
+defparam \rx_datain[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: CMU_X0_Y9_N139
+stratixiv_hssi_cmu \pma_direct|auto_generated|tx_pll_cent_unit0 (
+ .recovclk(gnd),
+ .rdenablesync(vcc),
+ .rxclk(gnd),
+ .txclk(gnd),
+ .quadreset(\gxb_powerdown~input_o ),
+ .dpclk(\reconfig_clk~inputclkctrl_outclk ),
+ .dprioin(gnd),
+ .dprioload(vcc),
+ .dpriodisable(vcc),
+ .nonuserfromcal(\pma_direct|auto_generated|nonusertocmu_out [0]),
+ .txphfiforeset(gnd),
+ .txcoreclk(gnd),
+ .txphfifowrenable(gnd),
+ .txphfiforddisable(gnd),
+ .rxphfiforeset(gnd),
+ .rxcoreclk(gnd),
+ .rxphfifowrdisable(gnd),
+ .rxphfifordenable(vcc),
+ .rateswitch(gnd),
+ .rateswitchdonein(gnd),
+ .scanclk(gnd),
+ .scanmode(gnd),
+ .scanshift(gnd),
+ .pmacramtest(gnd),
+ .adet(4'b0000),
+ .rdalign(4'b0000),
+ .syncstatus(4'b0000),
+ .rxdatavalid(4'b0000),
+ .rxdatain(32'b00000000000000000000000000000000),
+ .rxctrl(4'b0000),
+ .rxrunningdisp(4'b0000),
+ .txdatain(32'b00000000000000000000000000000000),
+ .txctrl(4'b0000),
+ .rxpmadprioin({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,\pma_direct|auto_generated|cent_unit_rxpmadprioin [1199],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1198],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1197],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1196],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1195],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1194],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1193],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1192],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1191],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1190],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1189],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1188],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1187],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1186],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1185],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1184],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1183],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1182],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1181],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1180],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1179],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1178],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1177],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1176],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1175],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1174],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1173],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1172],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1171],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1170],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1169],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1168],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1167],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1166],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1165],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1164],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1163],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1162],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1161],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1160],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1159],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1158],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1157],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1156],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1155],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1154],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1153],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1152],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1151],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1150],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1149],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1148],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1147],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1146],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1145],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1144],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1143],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1142],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1141],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1140],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1139],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1138],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1137],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1136],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1135],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1134],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1133],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1132],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1131],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1130],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1129],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1128],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1127],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1126],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1125],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1124],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1123],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1122],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1121],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1120],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1119],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1118],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1117],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1116],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1115],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1114],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1113],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1112],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1111],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1110],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1109],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1108],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1107],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1106],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1105],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1104],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1103],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1102],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1101],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1100],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1099],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1098],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1097],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1096],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1095],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1094],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1093],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1092],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1091],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1090],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1089],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1088],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1087],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1086],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1085],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1084],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1083],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1082],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1081],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1080],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1079],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1078],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1077],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1076],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1075],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1074],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1073],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1072],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1071],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1070],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1069],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1068],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1067],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1066],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1065],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1064],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1063],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1062],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1061],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1060],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1059],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1058],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1057],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1056],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1055],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1054],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1053],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1052],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1051],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1050],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1049],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1048],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1047],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1046],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1045],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1044],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1043],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1042],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1041],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1040],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1039],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1038],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1037],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1036],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1035],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1034],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1033],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1032],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1031],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1030],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1029],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1028],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1027],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1026],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1025],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1024],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1023],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1022],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1021],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1020],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1019],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1018],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1017],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1016],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1015],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1014],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1013],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1012],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1011],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [1010],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1009],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1008],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1007],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1006],
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+\pma_direct|auto_generated|cent_unit_rxpmadprioin [285],\pma_direct|auto_generated|cent_unit_rxpmadprioin [284],\pma_direct|auto_generated|cent_unit_rxpmadprioin [283],\pma_direct|auto_generated|cent_unit_rxpmadprioin [282],\pma_direct|auto_generated|cent_unit_rxpmadprioin [281],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [280],\pma_direct|auto_generated|cent_unit_rxpmadprioin [279],\pma_direct|auto_generated|cent_unit_rxpmadprioin [278],\pma_direct|auto_generated|cent_unit_rxpmadprioin [277],\pma_direct|auto_generated|cent_unit_rxpmadprioin [276],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [275],\pma_direct|auto_generated|cent_unit_rxpmadprioin [274],\pma_direct|auto_generated|cent_unit_rxpmadprioin [273],\pma_direct|auto_generated|cent_unit_rxpmadprioin [272],\pma_direct|auto_generated|cent_unit_rxpmadprioin [271],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [270],\pma_direct|auto_generated|cent_unit_rxpmadprioin [269],\pma_direct|auto_generated|cent_unit_rxpmadprioin [268],\pma_direct|auto_generated|cent_unit_rxpmadprioin [267],\pma_direct|auto_generated|cent_unit_rxpmadprioin [266],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [265],\pma_direct|auto_generated|cent_unit_rxpmadprioin [264],\pma_direct|auto_generated|cent_unit_rxpmadprioin [263],\pma_direct|auto_generated|cent_unit_rxpmadprioin [262],\pma_direct|auto_generated|cent_unit_rxpmadprioin [261],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [260],\pma_direct|auto_generated|cent_unit_rxpmadprioin [259],\pma_direct|auto_generated|cent_unit_rxpmadprioin [258],\pma_direct|auto_generated|cent_unit_rxpmadprioin [257],\pma_direct|auto_generated|cent_unit_rxpmadprioin [256],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [255],\pma_direct|auto_generated|cent_unit_rxpmadprioin [254],\pma_direct|auto_generated|cent_unit_rxpmadprioin [253],\pma_direct|auto_generated|cent_unit_rxpmadprioin [252],\pma_direct|auto_generated|cent_unit_rxpmadprioin [251],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [250],\pma_direct|auto_generated|cent_unit_rxpmadprioin [249],\pma_direct|auto_generated|cent_unit_rxpmadprioin [248],\pma_direct|auto_generated|cent_unit_rxpmadprioin [247],\pma_direct|auto_generated|cent_unit_rxpmadprioin [246],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [245],\pma_direct|auto_generated|cent_unit_rxpmadprioin [244],\pma_direct|auto_generated|cent_unit_rxpmadprioin [243],\pma_direct|auto_generated|cent_unit_rxpmadprioin [242],\pma_direct|auto_generated|cent_unit_rxpmadprioin [241],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [240],\pma_direct|auto_generated|cent_unit_rxpmadprioin [239],\pma_direct|auto_generated|cent_unit_rxpmadprioin [238],\pma_direct|auto_generated|cent_unit_rxpmadprioin [237],\pma_direct|auto_generated|cent_unit_rxpmadprioin [236],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [235],\pma_direct|auto_generated|cent_unit_rxpmadprioin [234],\pma_direct|auto_generated|cent_unit_rxpmadprioin [233],\pma_direct|auto_generated|cent_unit_rxpmadprioin [232],\pma_direct|auto_generated|cent_unit_rxpmadprioin [231],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [230],\pma_direct|auto_generated|cent_unit_rxpmadprioin [229],\pma_direct|auto_generated|cent_unit_rxpmadprioin [228],\pma_direct|auto_generated|cent_unit_rxpmadprioin [227],\pma_direct|auto_generated|cent_unit_rxpmadprioin [226],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [225],\pma_direct|auto_generated|cent_unit_rxpmadprioin [224],\pma_direct|auto_generated|cent_unit_rxpmadprioin [223],\pma_direct|auto_generated|cent_unit_rxpmadprioin [222],\pma_direct|auto_generated|cent_unit_rxpmadprioin [221],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [220],\pma_direct|auto_generated|cent_unit_rxpmadprioin [219],\pma_direct|auto_generated|cent_unit_rxpmadprioin [218],\pma_direct|auto_generated|cent_unit_rxpmadprioin [217],\pma_direct|auto_generated|cent_unit_rxpmadprioin [216],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [215],\pma_direct|auto_generated|cent_unit_rxpmadprioin [214],\pma_direct|auto_generated|cent_unit_rxpmadprioin [213],\pma_direct|auto_generated|cent_unit_rxpmadprioin [212],\pma_direct|auto_generated|cent_unit_rxpmadprioin [211],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [210],\pma_direct|auto_generated|cent_unit_rxpmadprioin [209],\pma_direct|auto_generated|cent_unit_rxpmadprioin [208],\pma_direct|auto_generated|cent_unit_rxpmadprioin [207],\pma_direct|auto_generated|cent_unit_rxpmadprioin [206],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [205],\pma_direct|auto_generated|cent_unit_rxpmadprioin [204],\pma_direct|auto_generated|cent_unit_rxpmadprioin [203],\pma_direct|auto_generated|cent_unit_rxpmadprioin [202],\pma_direct|auto_generated|cent_unit_rxpmadprioin [201],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [200],\pma_direct|auto_generated|cent_unit_rxpmadprioin [199],\pma_direct|auto_generated|cent_unit_rxpmadprioin [198],\pma_direct|auto_generated|cent_unit_rxpmadprioin [197],\pma_direct|auto_generated|cent_unit_rxpmadprioin [196],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [195],\pma_direct|auto_generated|cent_unit_rxpmadprioin [194],\pma_direct|auto_generated|cent_unit_rxpmadprioin [193],\pma_direct|auto_generated|cent_unit_rxpmadprioin [192],\pma_direct|auto_generated|cent_unit_rxpmadprioin [191],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [190],\pma_direct|auto_generated|cent_unit_rxpmadprioin [189],\pma_direct|auto_generated|cent_unit_rxpmadprioin [188],\pma_direct|auto_generated|cent_unit_rxpmadprioin [187],\pma_direct|auto_generated|cent_unit_rxpmadprioin [186],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [185],\pma_direct|auto_generated|cent_unit_rxpmadprioin [184],\pma_direct|auto_generated|cent_unit_rxpmadprioin [183],\pma_direct|auto_generated|cent_unit_rxpmadprioin [182],\pma_direct|auto_generated|cent_unit_rxpmadprioin [181],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [180],\pma_direct|auto_generated|cent_unit_rxpmadprioin [179],\pma_direct|auto_generated|cent_unit_rxpmadprioin [178],\pma_direct|auto_generated|cent_unit_rxpmadprioin [177],\pma_direct|auto_generated|cent_unit_rxpmadprioin [176],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [175],\pma_direct|auto_generated|cent_unit_rxpmadprioin [174],\pma_direct|auto_generated|cent_unit_rxpmadprioin [173],\pma_direct|auto_generated|cent_unit_rxpmadprioin [172],\pma_direct|auto_generated|cent_unit_rxpmadprioin [171],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [170],\pma_direct|auto_generated|cent_unit_rxpmadprioin [169],\pma_direct|auto_generated|cent_unit_rxpmadprioin [168],\pma_direct|auto_generated|cent_unit_rxpmadprioin [167],\pma_direct|auto_generated|cent_unit_rxpmadprioin [166],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [165],\pma_direct|auto_generated|cent_unit_rxpmadprioin [164],\pma_direct|auto_generated|cent_unit_rxpmadprioin [163],\pma_direct|auto_generated|cent_unit_rxpmadprioin [162],\pma_direct|auto_generated|cent_unit_rxpmadprioin [161],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [160],\pma_direct|auto_generated|cent_unit_rxpmadprioin [159],\pma_direct|auto_generated|cent_unit_rxpmadprioin [158],\pma_direct|auto_generated|cent_unit_rxpmadprioin [157],\pma_direct|auto_generated|cent_unit_rxpmadprioin [156],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [155],\pma_direct|auto_generated|cent_unit_rxpmadprioin [154],\pma_direct|auto_generated|cent_unit_rxpmadprioin [153],\pma_direct|auto_generated|cent_unit_rxpmadprioin [152],\pma_direct|auto_generated|cent_unit_rxpmadprioin [151],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [150],\pma_direct|auto_generated|cent_unit_rxpmadprioin [149],\pma_direct|auto_generated|cent_unit_rxpmadprioin [148],\pma_direct|auto_generated|cent_unit_rxpmadprioin [147],\pma_direct|auto_generated|cent_unit_rxpmadprioin [146],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [145],\pma_direct|auto_generated|cent_unit_rxpmadprioin [144],\pma_direct|auto_generated|cent_unit_rxpmadprioin [143],\pma_direct|auto_generated|cent_unit_rxpmadprioin [142],\pma_direct|auto_generated|cent_unit_rxpmadprioin [141],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [140],\pma_direct|auto_generated|cent_unit_rxpmadprioin [139],\pma_direct|auto_generated|cent_unit_rxpmadprioin [138],\pma_direct|auto_generated|cent_unit_rxpmadprioin [137],\pma_direct|auto_generated|cent_unit_rxpmadprioin [136],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [135],\pma_direct|auto_generated|cent_unit_rxpmadprioin [134],\pma_direct|auto_generated|cent_unit_rxpmadprioin [133],\pma_direct|auto_generated|cent_unit_rxpmadprioin [132],\pma_direct|auto_generated|cent_unit_rxpmadprioin [131],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [130],\pma_direct|auto_generated|cent_unit_rxpmadprioin [129],\pma_direct|auto_generated|cent_unit_rxpmadprioin [128],\pma_direct|auto_generated|cent_unit_rxpmadprioin [127],\pma_direct|auto_generated|cent_unit_rxpmadprioin [126],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [125],\pma_direct|auto_generated|cent_unit_rxpmadprioin [124],\pma_direct|auto_generated|cent_unit_rxpmadprioin [123],\pma_direct|auto_generated|cent_unit_rxpmadprioin [122],\pma_direct|auto_generated|cent_unit_rxpmadprioin [121],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [120],\pma_direct|auto_generated|cent_unit_rxpmadprioin [119],\pma_direct|auto_generated|cent_unit_rxpmadprioin [118],\pma_direct|auto_generated|cent_unit_rxpmadprioin [117],\pma_direct|auto_generated|cent_unit_rxpmadprioin [116],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [115],\pma_direct|auto_generated|cent_unit_rxpmadprioin [114],\pma_direct|auto_generated|cent_unit_rxpmadprioin [113],\pma_direct|auto_generated|cent_unit_rxpmadprioin [112],\pma_direct|auto_generated|cent_unit_rxpmadprioin [111],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [110],\pma_direct|auto_generated|cent_unit_rxpmadprioin [109],\pma_direct|auto_generated|cent_unit_rxpmadprioin [108],\pma_direct|auto_generated|cent_unit_rxpmadprioin [107],\pma_direct|auto_generated|cent_unit_rxpmadprioin [106],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [105],\pma_direct|auto_generated|cent_unit_rxpmadprioin [104],\pma_direct|auto_generated|cent_unit_rxpmadprioin [103],\pma_direct|auto_generated|cent_unit_rxpmadprioin [102],\pma_direct|auto_generated|cent_unit_rxpmadprioin [101],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [100],\pma_direct|auto_generated|cent_unit_rxpmadprioin [99],\pma_direct|auto_generated|cent_unit_rxpmadprioin [98],\pma_direct|auto_generated|cent_unit_rxpmadprioin [97],\pma_direct|auto_generated|cent_unit_rxpmadprioin [96],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [95],\pma_direct|auto_generated|cent_unit_rxpmadprioin [94],\pma_direct|auto_generated|cent_unit_rxpmadprioin [93],\pma_direct|auto_generated|cent_unit_rxpmadprioin [92],\pma_direct|auto_generated|cent_unit_rxpmadprioin [91],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [90],\pma_direct|auto_generated|cent_unit_rxpmadprioin [89],\pma_direct|auto_generated|cent_unit_rxpmadprioin [88],\pma_direct|auto_generated|cent_unit_rxpmadprioin [87],\pma_direct|auto_generated|cent_unit_rxpmadprioin [86],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [85],\pma_direct|auto_generated|cent_unit_rxpmadprioin [84],\pma_direct|auto_generated|cent_unit_rxpmadprioin [83],\pma_direct|auto_generated|cent_unit_rxpmadprioin [82],\pma_direct|auto_generated|cent_unit_rxpmadprioin [81],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [80],\pma_direct|auto_generated|cent_unit_rxpmadprioin [79],\pma_direct|auto_generated|cent_unit_rxpmadprioin [78],\pma_direct|auto_generated|cent_unit_rxpmadprioin [77],\pma_direct|auto_generated|cent_unit_rxpmadprioin [76],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [75],\pma_direct|auto_generated|cent_unit_rxpmadprioin [74],\pma_direct|auto_generated|cent_unit_rxpmadprioin [73],\pma_direct|auto_generated|cent_unit_rxpmadprioin [72],\pma_direct|auto_generated|cent_unit_rxpmadprioin [71],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [70],\pma_direct|auto_generated|cent_unit_rxpmadprioin [69],\pma_direct|auto_generated|cent_unit_rxpmadprioin [68],\pma_direct|auto_generated|cent_unit_rxpmadprioin [67],\pma_direct|auto_generated|cent_unit_rxpmadprioin [66],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [65],\pma_direct|auto_generated|cent_unit_rxpmadprioin [64],\pma_direct|auto_generated|cent_unit_rxpmadprioin [63],\pma_direct|auto_generated|cent_unit_rxpmadprioin [62],\pma_direct|auto_generated|cent_unit_rxpmadprioin [61],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [60],\pma_direct|auto_generated|cent_unit_rxpmadprioin [59],\pma_direct|auto_generated|cent_unit_rxpmadprioin [58],\pma_direct|auto_generated|cent_unit_rxpmadprioin [57],\pma_direct|auto_generated|cent_unit_rxpmadprioin [56],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [55],\pma_direct|auto_generated|cent_unit_rxpmadprioin [54],\pma_direct|auto_generated|cent_unit_rxpmadprioin [53],\pma_direct|auto_generated|cent_unit_rxpmadprioin [52],\pma_direct|auto_generated|cent_unit_rxpmadprioin [51],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [50],\pma_direct|auto_generated|cent_unit_rxpmadprioin [49],\pma_direct|auto_generated|cent_unit_rxpmadprioin [48],\pma_direct|auto_generated|cent_unit_rxpmadprioin [47],\pma_direct|auto_generated|cent_unit_rxpmadprioin [46],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [45],\pma_direct|auto_generated|cent_unit_rxpmadprioin [44],\pma_direct|auto_generated|cent_unit_rxpmadprioin [43],\pma_direct|auto_generated|cent_unit_rxpmadprioin [42],\pma_direct|auto_generated|cent_unit_rxpmadprioin [41],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [40],\pma_direct|auto_generated|cent_unit_rxpmadprioin [39],\pma_direct|auto_generated|cent_unit_rxpmadprioin [38],\pma_direct|auto_generated|cent_unit_rxpmadprioin [37],\pma_direct|auto_generated|cent_unit_rxpmadprioin [36],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [35],\pma_direct|auto_generated|cent_unit_rxpmadprioin [34],\pma_direct|auto_generated|cent_unit_rxpmadprioin [33],\pma_direct|auto_generated|cent_unit_rxpmadprioin [32],\pma_direct|auto_generated|cent_unit_rxpmadprioin [31],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [30],\pma_direct|auto_generated|cent_unit_rxpmadprioin [29],\pma_direct|auto_generated|cent_unit_rxpmadprioin [28],\pma_direct|auto_generated|cent_unit_rxpmadprioin [27],\pma_direct|auto_generated|cent_unit_rxpmadprioin [26],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [25],\pma_direct|auto_generated|cent_unit_rxpmadprioin [24],\pma_direct|auto_generated|cent_unit_rxpmadprioin [23],\pma_direct|auto_generated|cent_unit_rxpmadprioin [22],\pma_direct|auto_generated|cent_unit_rxpmadprioin [21],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [20],\pma_direct|auto_generated|cent_unit_rxpmadprioin [19],\pma_direct|auto_generated|cent_unit_rxpmadprioin [18],\pma_direct|auto_generated|cent_unit_rxpmadprioin [17],\pma_direct|auto_generated|cent_unit_rxpmadprioin [16],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [15],\pma_direct|auto_generated|cent_unit_rxpmadprioin [14],\pma_direct|auto_generated|cent_unit_rxpmadprioin [13],\pma_direct|auto_generated|cent_unit_rxpmadprioin [12],\pma_direct|auto_generated|cent_unit_rxpmadprioin [11],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [10],\pma_direct|auto_generated|cent_unit_rxpmadprioin [9],\pma_direct|auto_generated|cent_unit_rxpmadprioin [8],\pma_direct|auto_generated|cent_unit_rxpmadprioin [7],\pma_direct|auto_generated|cent_unit_rxpmadprioin [6],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [5],\pma_direct|auto_generated|cent_unit_rxpmadprioin [4],\pma_direct|auto_generated|cent_unit_rxpmadprioin [3],\pma_direct|auto_generated|cent_unit_rxpmadprioin [2],\pma_direct|auto_generated|cent_unit_rxpmadprioin [1],
+\pma_direct|auto_generated|cent_unit_rxpmadprioin [0]}),
+ .rxpcsdprioin(1600'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
+ .txpmadprioin({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
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+\pma_direct|auto_generated|cent_unit_txpmadprioin [140],\pma_direct|auto_generated|cent_unit_txpmadprioin [139],\pma_direct|auto_generated|cent_unit_txpmadprioin [138],\pma_direct|auto_generated|cent_unit_txpmadprioin [137],\pma_direct|auto_generated|cent_unit_txpmadprioin [136],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [135],\pma_direct|auto_generated|cent_unit_txpmadprioin [134],\pma_direct|auto_generated|cent_unit_txpmadprioin [133],\pma_direct|auto_generated|cent_unit_txpmadprioin [132],\pma_direct|auto_generated|cent_unit_txpmadprioin [131],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [130],\pma_direct|auto_generated|cent_unit_txpmadprioin [129],\pma_direct|auto_generated|cent_unit_txpmadprioin [128],\pma_direct|auto_generated|cent_unit_txpmadprioin [127],\pma_direct|auto_generated|cent_unit_txpmadprioin [126],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [125],\pma_direct|auto_generated|cent_unit_txpmadprioin [124],\pma_direct|auto_generated|cent_unit_txpmadprioin [123],\pma_direct|auto_generated|cent_unit_txpmadprioin [122],\pma_direct|auto_generated|cent_unit_txpmadprioin [121],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [120],\pma_direct|auto_generated|cent_unit_txpmadprioin [119],\pma_direct|auto_generated|cent_unit_txpmadprioin [118],\pma_direct|auto_generated|cent_unit_txpmadprioin [117],\pma_direct|auto_generated|cent_unit_txpmadprioin [116],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [115],\pma_direct|auto_generated|cent_unit_txpmadprioin [114],\pma_direct|auto_generated|cent_unit_txpmadprioin [113],\pma_direct|auto_generated|cent_unit_txpmadprioin [112],\pma_direct|auto_generated|cent_unit_txpmadprioin [111],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [110],\pma_direct|auto_generated|cent_unit_txpmadprioin [109],\pma_direct|auto_generated|cent_unit_txpmadprioin [108],\pma_direct|auto_generated|cent_unit_txpmadprioin [107],\pma_direct|auto_generated|cent_unit_txpmadprioin [106],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [105],\pma_direct|auto_generated|cent_unit_txpmadprioin [104],\pma_direct|auto_generated|cent_unit_txpmadprioin [103],\pma_direct|auto_generated|cent_unit_txpmadprioin [102],\pma_direct|auto_generated|cent_unit_txpmadprioin [101],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [100],\pma_direct|auto_generated|cent_unit_txpmadprioin [99],\pma_direct|auto_generated|cent_unit_txpmadprioin [98],\pma_direct|auto_generated|cent_unit_txpmadprioin [97],\pma_direct|auto_generated|cent_unit_txpmadprioin [96],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [95],\pma_direct|auto_generated|cent_unit_txpmadprioin [94],\pma_direct|auto_generated|cent_unit_txpmadprioin [93],\pma_direct|auto_generated|cent_unit_txpmadprioin [92],\pma_direct|auto_generated|cent_unit_txpmadprioin [91],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [90],\pma_direct|auto_generated|cent_unit_txpmadprioin [89],\pma_direct|auto_generated|cent_unit_txpmadprioin [88],\pma_direct|auto_generated|cent_unit_txpmadprioin [87],\pma_direct|auto_generated|cent_unit_txpmadprioin [86],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [85],\pma_direct|auto_generated|cent_unit_txpmadprioin [84],\pma_direct|auto_generated|cent_unit_txpmadprioin [83],\pma_direct|auto_generated|cent_unit_txpmadprioin [82],\pma_direct|auto_generated|cent_unit_txpmadprioin [81],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [80],\pma_direct|auto_generated|cent_unit_txpmadprioin [79],\pma_direct|auto_generated|cent_unit_txpmadprioin [78],\pma_direct|auto_generated|cent_unit_txpmadprioin [77],\pma_direct|auto_generated|cent_unit_txpmadprioin [76],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [75],\pma_direct|auto_generated|cent_unit_txpmadprioin [74],\pma_direct|auto_generated|cent_unit_txpmadprioin [73],\pma_direct|auto_generated|cent_unit_txpmadprioin [72],\pma_direct|auto_generated|cent_unit_txpmadprioin [71],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [70],\pma_direct|auto_generated|cent_unit_txpmadprioin [69],\pma_direct|auto_generated|cent_unit_txpmadprioin [68],\pma_direct|auto_generated|cent_unit_txpmadprioin [67],\pma_direct|auto_generated|cent_unit_txpmadprioin [66],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [65],\pma_direct|auto_generated|cent_unit_txpmadprioin [64],\pma_direct|auto_generated|cent_unit_txpmadprioin [63],\pma_direct|auto_generated|cent_unit_txpmadprioin [62],\pma_direct|auto_generated|cent_unit_txpmadprioin [61],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [60],\pma_direct|auto_generated|cent_unit_txpmadprioin [59],\pma_direct|auto_generated|cent_unit_txpmadprioin [58],\pma_direct|auto_generated|cent_unit_txpmadprioin [57],\pma_direct|auto_generated|cent_unit_txpmadprioin [56],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [55],\pma_direct|auto_generated|cent_unit_txpmadprioin [54],\pma_direct|auto_generated|cent_unit_txpmadprioin [53],\pma_direct|auto_generated|cent_unit_txpmadprioin [52],\pma_direct|auto_generated|cent_unit_txpmadprioin [51],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [50],\pma_direct|auto_generated|cent_unit_txpmadprioin [49],\pma_direct|auto_generated|cent_unit_txpmadprioin [48],\pma_direct|auto_generated|cent_unit_txpmadprioin [47],\pma_direct|auto_generated|cent_unit_txpmadprioin [46],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [45],\pma_direct|auto_generated|cent_unit_txpmadprioin [44],\pma_direct|auto_generated|cent_unit_txpmadprioin [43],\pma_direct|auto_generated|cent_unit_txpmadprioin [42],\pma_direct|auto_generated|cent_unit_txpmadprioin [41],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [40],\pma_direct|auto_generated|cent_unit_txpmadprioin [39],\pma_direct|auto_generated|cent_unit_txpmadprioin [38],\pma_direct|auto_generated|cent_unit_txpmadprioin [37],\pma_direct|auto_generated|cent_unit_txpmadprioin [36],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [35],\pma_direct|auto_generated|cent_unit_txpmadprioin [34],\pma_direct|auto_generated|cent_unit_txpmadprioin [33],\pma_direct|auto_generated|cent_unit_txpmadprioin [32],\pma_direct|auto_generated|cent_unit_txpmadprioin [31],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [30],\pma_direct|auto_generated|cent_unit_txpmadprioin [29],\pma_direct|auto_generated|cent_unit_txpmadprioin [28],\pma_direct|auto_generated|cent_unit_txpmadprioin [27],\pma_direct|auto_generated|cent_unit_txpmadprioin [26],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [25],\pma_direct|auto_generated|cent_unit_txpmadprioin [24],\pma_direct|auto_generated|cent_unit_txpmadprioin [23],\pma_direct|auto_generated|cent_unit_txpmadprioin [22],\pma_direct|auto_generated|cent_unit_txpmadprioin [21],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [20],\pma_direct|auto_generated|cent_unit_txpmadprioin [19],\pma_direct|auto_generated|cent_unit_txpmadprioin [18],\pma_direct|auto_generated|cent_unit_txpmadprioin [17],\pma_direct|auto_generated|cent_unit_txpmadprioin [16],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [15],\pma_direct|auto_generated|cent_unit_txpmadprioin [14],\pma_direct|auto_generated|cent_unit_txpmadprioin [13],\pma_direct|auto_generated|cent_unit_txpmadprioin [12],\pma_direct|auto_generated|cent_unit_txpmadprioin [11],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [10],\pma_direct|auto_generated|cent_unit_txpmadprioin [9],\pma_direct|auto_generated|cent_unit_txpmadprioin [8],\pma_direct|auto_generated|cent_unit_txpmadprioin [7],\pma_direct|auto_generated|cent_unit_txpmadprioin [6],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [5],\pma_direct|auto_generated|cent_unit_txpmadprioin [4],\pma_direct|auto_generated|cent_unit_txpmadprioin [3],\pma_direct|auto_generated|cent_unit_txpmadprioin [2],\pma_direct|auto_generated|cent_unit_txpmadprioin [1],
+\pma_direct|auto_generated|cent_unit_txpmadprioin [0]}),
+ .txpcsdprioin(600'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
+ .cmuplldprioin({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\pma_direct|auto_generated|edge_pll_cmuplldprioout [299],\pma_direct|auto_generated|edge_pll_cmuplldprioout [298],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [297],\pma_direct|auto_generated|edge_pll_cmuplldprioout [296],\pma_direct|auto_generated|edge_pll_cmuplldprioout [295],\pma_direct|auto_generated|edge_pll_cmuplldprioout [294],\pma_direct|auto_generated|edge_pll_cmuplldprioout [293],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [292],\pma_direct|auto_generated|edge_pll_cmuplldprioout [291],\pma_direct|auto_generated|edge_pll_cmuplldprioout [290],\pma_direct|auto_generated|edge_pll_cmuplldprioout [289],\pma_direct|auto_generated|edge_pll_cmuplldprioout [288],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [287],\pma_direct|auto_generated|edge_pll_cmuplldprioout [286],\pma_direct|auto_generated|edge_pll_cmuplldprioout [285],\pma_direct|auto_generated|edge_pll_cmuplldprioout [284],\pma_direct|auto_generated|edge_pll_cmuplldprioout [283],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [282],\pma_direct|auto_generated|edge_pll_cmuplldprioout [281],\pma_direct|auto_generated|edge_pll_cmuplldprioout [280],\pma_direct|auto_generated|edge_pll_cmuplldprioout [279],\pma_direct|auto_generated|edge_pll_cmuplldprioout [278],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [277],\pma_direct|auto_generated|edge_pll_cmuplldprioout [276],\pma_direct|auto_generated|edge_pll_cmuplldprioout [275],\pma_direct|auto_generated|edge_pll_cmuplldprioout [274],\pma_direct|auto_generated|edge_pll_cmuplldprioout [273],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [272],\pma_direct|auto_generated|edge_pll_cmuplldprioout [271],\pma_direct|auto_generated|edge_pll_cmuplldprioout [270],\pma_direct|auto_generated|edge_pll_cmuplldprioout [269],\pma_direct|auto_generated|edge_pll_cmuplldprioout [268],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [267],\pma_direct|auto_generated|edge_pll_cmuplldprioout [266],\pma_direct|auto_generated|edge_pll_cmuplldprioout [265],\pma_direct|auto_generated|edge_pll_cmuplldprioout [264],\pma_direct|auto_generated|edge_pll_cmuplldprioout [263],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [262],\pma_direct|auto_generated|edge_pll_cmuplldprioout [261],\pma_direct|auto_generated|edge_pll_cmuplldprioout [260],\pma_direct|auto_generated|edge_pll_cmuplldprioout [259],\pma_direct|auto_generated|edge_pll_cmuplldprioout [258],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [257],\pma_direct|auto_generated|edge_pll_cmuplldprioout [256],\pma_direct|auto_generated|edge_pll_cmuplldprioout [255],\pma_direct|auto_generated|edge_pll_cmuplldprioout [254],\pma_direct|auto_generated|edge_pll_cmuplldprioout [253],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [252],\pma_direct|auto_generated|edge_pll_cmuplldprioout [251],\pma_direct|auto_generated|edge_pll_cmuplldprioout [250],\pma_direct|auto_generated|edge_pll_cmuplldprioout [249],\pma_direct|auto_generated|edge_pll_cmuplldprioout [248],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [247],\pma_direct|auto_generated|edge_pll_cmuplldprioout [246],\pma_direct|auto_generated|edge_pll_cmuplldprioout [245],\pma_direct|auto_generated|edge_pll_cmuplldprioout [244],\pma_direct|auto_generated|edge_pll_cmuplldprioout [243],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [242],\pma_direct|auto_generated|edge_pll_cmuplldprioout [241],\pma_direct|auto_generated|edge_pll_cmuplldprioout [240],\pma_direct|auto_generated|edge_pll_cmuplldprioout [239],\pma_direct|auto_generated|edge_pll_cmuplldprioout [238],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [237],\pma_direct|auto_generated|edge_pll_cmuplldprioout [236],\pma_direct|auto_generated|edge_pll_cmuplldprioout [235],\pma_direct|auto_generated|edge_pll_cmuplldprioout [234],\pma_direct|auto_generated|edge_pll_cmuplldprioout [233],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [232],\pma_direct|auto_generated|edge_pll_cmuplldprioout [231],\pma_direct|auto_generated|edge_pll_cmuplldprioout [230],\pma_direct|auto_generated|edge_pll_cmuplldprioout [229],\pma_direct|auto_generated|edge_pll_cmuplldprioout [228],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [227],\pma_direct|auto_generated|edge_pll_cmuplldprioout [226],\pma_direct|auto_generated|edge_pll_cmuplldprioout [225],\pma_direct|auto_generated|edge_pll_cmuplldprioout [224],\pma_direct|auto_generated|edge_pll_cmuplldprioout [223],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [222],\pma_direct|auto_generated|edge_pll_cmuplldprioout [221],\pma_direct|auto_generated|edge_pll_cmuplldprioout [220],\pma_direct|auto_generated|edge_pll_cmuplldprioout [219],\pma_direct|auto_generated|edge_pll_cmuplldprioout [218],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [217],\pma_direct|auto_generated|edge_pll_cmuplldprioout [216],\pma_direct|auto_generated|edge_pll_cmuplldprioout [215],\pma_direct|auto_generated|edge_pll_cmuplldprioout [214],\pma_direct|auto_generated|edge_pll_cmuplldprioout [213],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [212],\pma_direct|auto_generated|edge_pll_cmuplldprioout [211],\pma_direct|auto_generated|edge_pll_cmuplldprioout [210],\pma_direct|auto_generated|edge_pll_cmuplldprioout [209],\pma_direct|auto_generated|edge_pll_cmuplldprioout [208],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [207],\pma_direct|auto_generated|edge_pll_cmuplldprioout [206],\pma_direct|auto_generated|edge_pll_cmuplldprioout [205],\pma_direct|auto_generated|edge_pll_cmuplldprioout [204],\pma_direct|auto_generated|edge_pll_cmuplldprioout [203],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [202],\pma_direct|auto_generated|edge_pll_cmuplldprioout [201],\pma_direct|auto_generated|edge_pll_cmuplldprioout [200],\pma_direct|auto_generated|edge_pll_cmuplldprioout [199],\pma_direct|auto_generated|edge_pll_cmuplldprioout [198],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [197],\pma_direct|auto_generated|edge_pll_cmuplldprioout [196],\pma_direct|auto_generated|edge_pll_cmuplldprioout [195],\pma_direct|auto_generated|edge_pll_cmuplldprioout [194],\pma_direct|auto_generated|edge_pll_cmuplldprioout [193],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [192],\pma_direct|auto_generated|edge_pll_cmuplldprioout [191],\pma_direct|auto_generated|edge_pll_cmuplldprioout [190],\pma_direct|auto_generated|edge_pll_cmuplldprioout [189],\pma_direct|auto_generated|edge_pll_cmuplldprioout [188],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [187],\pma_direct|auto_generated|edge_pll_cmuplldprioout [186],\pma_direct|auto_generated|edge_pll_cmuplldprioout [185],\pma_direct|auto_generated|edge_pll_cmuplldprioout [184],\pma_direct|auto_generated|edge_pll_cmuplldprioout [183],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [182],\pma_direct|auto_generated|edge_pll_cmuplldprioout [181],\pma_direct|auto_generated|edge_pll_cmuplldprioout [180],\pma_direct|auto_generated|edge_pll_cmuplldprioout [179],\pma_direct|auto_generated|edge_pll_cmuplldprioout [178],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [177],\pma_direct|auto_generated|edge_pll_cmuplldprioout [176],\pma_direct|auto_generated|edge_pll_cmuplldprioout [175],\pma_direct|auto_generated|edge_pll_cmuplldprioout [174],\pma_direct|auto_generated|edge_pll_cmuplldprioout [173],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [172],\pma_direct|auto_generated|edge_pll_cmuplldprioout [171],\pma_direct|auto_generated|edge_pll_cmuplldprioout [170],\pma_direct|auto_generated|edge_pll_cmuplldprioout [169],\pma_direct|auto_generated|edge_pll_cmuplldprioout [168],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [167],\pma_direct|auto_generated|edge_pll_cmuplldprioout [166],\pma_direct|auto_generated|edge_pll_cmuplldprioout [165],\pma_direct|auto_generated|edge_pll_cmuplldprioout [164],\pma_direct|auto_generated|edge_pll_cmuplldprioout [163],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [162],\pma_direct|auto_generated|edge_pll_cmuplldprioout [161],\pma_direct|auto_generated|edge_pll_cmuplldprioout [160],\pma_direct|auto_generated|edge_pll_cmuplldprioout [159],\pma_direct|auto_generated|edge_pll_cmuplldprioout [158],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [157],\pma_direct|auto_generated|edge_pll_cmuplldprioout [156],\pma_direct|auto_generated|edge_pll_cmuplldprioout [155],\pma_direct|auto_generated|edge_pll_cmuplldprioout [154],\pma_direct|auto_generated|edge_pll_cmuplldprioout [153],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [152],\pma_direct|auto_generated|edge_pll_cmuplldprioout [151],\pma_direct|auto_generated|edge_pll_cmuplldprioout [150],\pma_direct|auto_generated|edge_pll_cmuplldprioout [149],\pma_direct|auto_generated|edge_pll_cmuplldprioout [148],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [147],\pma_direct|auto_generated|edge_pll_cmuplldprioout [146],\pma_direct|auto_generated|edge_pll_cmuplldprioout [145],\pma_direct|auto_generated|edge_pll_cmuplldprioout [144],\pma_direct|auto_generated|edge_pll_cmuplldprioout [143],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [142],\pma_direct|auto_generated|edge_pll_cmuplldprioout [141],\pma_direct|auto_generated|edge_pll_cmuplldprioout [140],\pma_direct|auto_generated|edge_pll_cmuplldprioout [139],\pma_direct|auto_generated|edge_pll_cmuplldprioout [138],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [137],\pma_direct|auto_generated|edge_pll_cmuplldprioout [136],\pma_direct|auto_generated|edge_pll_cmuplldprioout [135],\pma_direct|auto_generated|edge_pll_cmuplldprioout [134],\pma_direct|auto_generated|edge_pll_cmuplldprioout [133],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [132],\pma_direct|auto_generated|edge_pll_cmuplldprioout [131],\pma_direct|auto_generated|edge_pll_cmuplldprioout [130],\pma_direct|auto_generated|edge_pll_cmuplldprioout [129],\pma_direct|auto_generated|edge_pll_cmuplldprioout [128],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [127],\pma_direct|auto_generated|edge_pll_cmuplldprioout [126],\pma_direct|auto_generated|edge_pll_cmuplldprioout [125],\pma_direct|auto_generated|edge_pll_cmuplldprioout [124],\pma_direct|auto_generated|edge_pll_cmuplldprioout [123],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [122],\pma_direct|auto_generated|edge_pll_cmuplldprioout [121],\pma_direct|auto_generated|edge_pll_cmuplldprioout [120],\pma_direct|auto_generated|edge_pll_cmuplldprioout [119],\pma_direct|auto_generated|edge_pll_cmuplldprioout [118],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [117],\pma_direct|auto_generated|edge_pll_cmuplldprioout [116],\pma_direct|auto_generated|edge_pll_cmuplldprioout [115],\pma_direct|auto_generated|edge_pll_cmuplldprioout [114],\pma_direct|auto_generated|edge_pll_cmuplldprioout [113],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [112],\pma_direct|auto_generated|edge_pll_cmuplldprioout [111],\pma_direct|auto_generated|edge_pll_cmuplldprioout [110],\pma_direct|auto_generated|edge_pll_cmuplldprioout [109],\pma_direct|auto_generated|edge_pll_cmuplldprioout [108],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [107],\pma_direct|auto_generated|edge_pll_cmuplldprioout [106],\pma_direct|auto_generated|edge_pll_cmuplldprioout [105],\pma_direct|auto_generated|edge_pll_cmuplldprioout [104],\pma_direct|auto_generated|edge_pll_cmuplldprioout [103],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [102],\pma_direct|auto_generated|edge_pll_cmuplldprioout [101],\pma_direct|auto_generated|edge_pll_cmuplldprioout [100],\pma_direct|auto_generated|edge_pll_cmuplldprioout [99],\pma_direct|auto_generated|edge_pll_cmuplldprioout [98],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [97],\pma_direct|auto_generated|edge_pll_cmuplldprioout [96],\pma_direct|auto_generated|edge_pll_cmuplldprioout [95],\pma_direct|auto_generated|edge_pll_cmuplldprioout [94],\pma_direct|auto_generated|edge_pll_cmuplldprioout [93],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [92],\pma_direct|auto_generated|edge_pll_cmuplldprioout [91],\pma_direct|auto_generated|edge_pll_cmuplldprioout [90],\pma_direct|auto_generated|edge_pll_cmuplldprioout [89],\pma_direct|auto_generated|edge_pll_cmuplldprioout [88],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [87],\pma_direct|auto_generated|edge_pll_cmuplldprioout [86],\pma_direct|auto_generated|edge_pll_cmuplldprioout [85],\pma_direct|auto_generated|edge_pll_cmuplldprioout [84],\pma_direct|auto_generated|edge_pll_cmuplldprioout [83],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [82],\pma_direct|auto_generated|edge_pll_cmuplldprioout [81],\pma_direct|auto_generated|edge_pll_cmuplldprioout [80],\pma_direct|auto_generated|edge_pll_cmuplldprioout [79],\pma_direct|auto_generated|edge_pll_cmuplldprioout [78],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [77],\pma_direct|auto_generated|edge_pll_cmuplldprioout [76],\pma_direct|auto_generated|edge_pll_cmuplldprioout [75],\pma_direct|auto_generated|edge_pll_cmuplldprioout [74],\pma_direct|auto_generated|edge_pll_cmuplldprioout [73],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [72],\pma_direct|auto_generated|edge_pll_cmuplldprioout [71],\pma_direct|auto_generated|edge_pll_cmuplldprioout [70],\pma_direct|auto_generated|edge_pll_cmuplldprioout [69],\pma_direct|auto_generated|edge_pll_cmuplldprioout [68],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [67],\pma_direct|auto_generated|edge_pll_cmuplldprioout [66],\pma_direct|auto_generated|edge_pll_cmuplldprioout [65],\pma_direct|auto_generated|edge_pll_cmuplldprioout [64],\pma_direct|auto_generated|edge_pll_cmuplldprioout [63],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [62],\pma_direct|auto_generated|edge_pll_cmuplldprioout [61],\pma_direct|auto_generated|edge_pll_cmuplldprioout [60],\pma_direct|auto_generated|edge_pll_cmuplldprioout [59],\pma_direct|auto_generated|edge_pll_cmuplldprioout [58],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [57],\pma_direct|auto_generated|edge_pll_cmuplldprioout [56],\pma_direct|auto_generated|edge_pll_cmuplldprioout [55],\pma_direct|auto_generated|edge_pll_cmuplldprioout [54],\pma_direct|auto_generated|edge_pll_cmuplldprioout [53],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [52],\pma_direct|auto_generated|edge_pll_cmuplldprioout [51],\pma_direct|auto_generated|edge_pll_cmuplldprioout [50],\pma_direct|auto_generated|edge_pll_cmuplldprioout [49],\pma_direct|auto_generated|edge_pll_cmuplldprioout [48],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [47],\pma_direct|auto_generated|edge_pll_cmuplldprioout [46],\pma_direct|auto_generated|edge_pll_cmuplldprioout [45],\pma_direct|auto_generated|edge_pll_cmuplldprioout [44],\pma_direct|auto_generated|edge_pll_cmuplldprioout [43],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [42],\pma_direct|auto_generated|edge_pll_cmuplldprioout [41],\pma_direct|auto_generated|edge_pll_cmuplldprioout [40],\pma_direct|auto_generated|edge_pll_cmuplldprioout [39],\pma_direct|auto_generated|edge_pll_cmuplldprioout [38],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [37],\pma_direct|auto_generated|edge_pll_cmuplldprioout [36],\pma_direct|auto_generated|edge_pll_cmuplldprioout [35],\pma_direct|auto_generated|edge_pll_cmuplldprioout [34],\pma_direct|auto_generated|edge_pll_cmuplldprioout [33],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [32],\pma_direct|auto_generated|edge_pll_cmuplldprioout [31],\pma_direct|auto_generated|edge_pll_cmuplldprioout [30],\pma_direct|auto_generated|edge_pll_cmuplldprioout [29],\pma_direct|auto_generated|edge_pll_cmuplldprioout [28],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [27],\pma_direct|auto_generated|edge_pll_cmuplldprioout [26],\pma_direct|auto_generated|edge_pll_cmuplldprioout [25],\pma_direct|auto_generated|edge_pll_cmuplldprioout [24],\pma_direct|auto_generated|edge_pll_cmuplldprioout [23],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [22],\pma_direct|auto_generated|edge_pll_cmuplldprioout [21],\pma_direct|auto_generated|edge_pll_cmuplldprioout [20],\pma_direct|auto_generated|edge_pll_cmuplldprioout [19],\pma_direct|auto_generated|edge_pll_cmuplldprioout [18],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [17],\pma_direct|auto_generated|edge_pll_cmuplldprioout [16],\pma_direct|auto_generated|edge_pll_cmuplldprioout [15],\pma_direct|auto_generated|edge_pll_cmuplldprioout [14],\pma_direct|auto_generated|edge_pll_cmuplldprioout [13],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [12],\pma_direct|auto_generated|edge_pll_cmuplldprioout [11],\pma_direct|auto_generated|edge_pll_cmuplldprioout [10],\pma_direct|auto_generated|edge_pll_cmuplldprioout [9],\pma_direct|auto_generated|edge_pll_cmuplldprioout [8],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [7],\pma_direct|auto_generated|edge_pll_cmuplldprioout [6],\pma_direct|auto_generated|edge_pll_cmuplldprioout [5],\pma_direct|auto_generated|edge_pll_cmuplldprioout [4],\pma_direct|auto_generated|edge_pll_cmuplldprioout [3],
+\pma_direct|auto_generated|edge_pll_cmuplldprioout [2],\pma_direct|auto_generated|edge_pll_cmuplldprioout [1],\pma_direct|auto_generated|edge_pll_cmuplldprioout [0],gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\pma_direct|auto_generated|pll_cmuplldprioout [5699],\pma_direct|auto_generated|pll_cmuplldprioout [5698],\pma_direct|auto_generated|pll_cmuplldprioout [5697],\pma_direct|auto_generated|pll_cmuplldprioout [5696],
+\pma_direct|auto_generated|pll_cmuplldprioout [5695],\pma_direct|auto_generated|pll_cmuplldprioout [5694],\pma_direct|auto_generated|pll_cmuplldprioout [5693],\pma_direct|auto_generated|pll_cmuplldprioout [5692],\pma_direct|auto_generated|pll_cmuplldprioout [5691],
+\pma_direct|auto_generated|pll_cmuplldprioout [5690],\pma_direct|auto_generated|pll_cmuplldprioout [5689],\pma_direct|auto_generated|pll_cmuplldprioout [5688],\pma_direct|auto_generated|pll_cmuplldprioout [5687],\pma_direct|auto_generated|pll_cmuplldprioout [5686],
+\pma_direct|auto_generated|pll_cmuplldprioout [5685],\pma_direct|auto_generated|pll_cmuplldprioout [5684],\pma_direct|auto_generated|pll_cmuplldprioout [5683],\pma_direct|auto_generated|pll_cmuplldprioout [5682],\pma_direct|auto_generated|pll_cmuplldprioout [5681],
+\pma_direct|auto_generated|pll_cmuplldprioout [5680],\pma_direct|auto_generated|pll_cmuplldprioout [5679],\pma_direct|auto_generated|pll_cmuplldprioout [5678],\pma_direct|auto_generated|pll_cmuplldprioout [5677],\pma_direct|auto_generated|pll_cmuplldprioout [5676],
+\pma_direct|auto_generated|pll_cmuplldprioout [5675],\pma_direct|auto_generated|pll_cmuplldprioout [5674],\pma_direct|auto_generated|pll_cmuplldprioout [5673],\pma_direct|auto_generated|pll_cmuplldprioout [5672],\pma_direct|auto_generated|pll_cmuplldprioout [5671],
+\pma_direct|auto_generated|pll_cmuplldprioout [5670],\pma_direct|auto_generated|pll_cmuplldprioout [5669],\pma_direct|auto_generated|pll_cmuplldprioout [5668],\pma_direct|auto_generated|pll_cmuplldprioout [5667],\pma_direct|auto_generated|pll_cmuplldprioout [5666],
+\pma_direct|auto_generated|pll_cmuplldprioout [5665],\pma_direct|auto_generated|pll_cmuplldprioout [5664],\pma_direct|auto_generated|pll_cmuplldprioout [5663],\pma_direct|auto_generated|pll_cmuplldprioout [5662],\pma_direct|auto_generated|pll_cmuplldprioout [5661],
+\pma_direct|auto_generated|pll_cmuplldprioout [5660],\pma_direct|auto_generated|pll_cmuplldprioout [5659],\pma_direct|auto_generated|pll_cmuplldprioout [5658],\pma_direct|auto_generated|pll_cmuplldprioout [5657],\pma_direct|auto_generated|pll_cmuplldprioout [5656],
+\pma_direct|auto_generated|pll_cmuplldprioout [5655],\pma_direct|auto_generated|pll_cmuplldprioout [5654],\pma_direct|auto_generated|pll_cmuplldprioout [5653],\pma_direct|auto_generated|pll_cmuplldprioout [5652],\pma_direct|auto_generated|pll_cmuplldprioout [5651],
+\pma_direct|auto_generated|pll_cmuplldprioout [5650],\pma_direct|auto_generated|pll_cmuplldprioout [5649],\pma_direct|auto_generated|pll_cmuplldprioout [5648],\pma_direct|auto_generated|pll_cmuplldprioout [5647],\pma_direct|auto_generated|pll_cmuplldprioout [5646],
+\pma_direct|auto_generated|pll_cmuplldprioout [5645],\pma_direct|auto_generated|pll_cmuplldprioout [5644],\pma_direct|auto_generated|pll_cmuplldprioout [5643],\pma_direct|auto_generated|pll_cmuplldprioout [5642],\pma_direct|auto_generated|pll_cmuplldprioout [5641],
+\pma_direct|auto_generated|pll_cmuplldprioout [5640],\pma_direct|auto_generated|pll_cmuplldprioout [5639],\pma_direct|auto_generated|pll_cmuplldprioout [5638],\pma_direct|auto_generated|pll_cmuplldprioout [5637],\pma_direct|auto_generated|pll_cmuplldprioout [5636],
+\pma_direct|auto_generated|pll_cmuplldprioout [5635],\pma_direct|auto_generated|pll_cmuplldprioout [5634],\pma_direct|auto_generated|pll_cmuplldprioout [5633],\pma_direct|auto_generated|pll_cmuplldprioout [5632],\pma_direct|auto_generated|pll_cmuplldprioout [5631],
+\pma_direct|auto_generated|pll_cmuplldprioout [5630],\pma_direct|auto_generated|pll_cmuplldprioout [5629],\pma_direct|auto_generated|pll_cmuplldprioout [5628],\pma_direct|auto_generated|pll_cmuplldprioout [5627],\pma_direct|auto_generated|pll_cmuplldprioout [5626],
+\pma_direct|auto_generated|pll_cmuplldprioout [5625],\pma_direct|auto_generated|pll_cmuplldprioout [5624],\pma_direct|auto_generated|pll_cmuplldprioout [5623],\pma_direct|auto_generated|pll_cmuplldprioout [5622],\pma_direct|auto_generated|pll_cmuplldprioout [5621],
+\pma_direct|auto_generated|pll_cmuplldprioout [5620],\pma_direct|auto_generated|pll_cmuplldprioout [5619],\pma_direct|auto_generated|pll_cmuplldprioout [5618],\pma_direct|auto_generated|pll_cmuplldprioout [5617],\pma_direct|auto_generated|pll_cmuplldprioout [5616],
+\pma_direct|auto_generated|pll_cmuplldprioout [5615],\pma_direct|auto_generated|pll_cmuplldprioout [5614],\pma_direct|auto_generated|pll_cmuplldprioout [5613],\pma_direct|auto_generated|pll_cmuplldprioout [5612],\pma_direct|auto_generated|pll_cmuplldprioout [5611],
+\pma_direct|auto_generated|pll_cmuplldprioout [5610],\pma_direct|auto_generated|pll_cmuplldprioout [5609],\pma_direct|auto_generated|pll_cmuplldprioout [5608],\pma_direct|auto_generated|pll_cmuplldprioout [5607],\pma_direct|auto_generated|pll_cmuplldprioout [5606],
+\pma_direct|auto_generated|pll_cmuplldprioout [5605],\pma_direct|auto_generated|pll_cmuplldprioout [5604],\pma_direct|auto_generated|pll_cmuplldprioout [5603],\pma_direct|auto_generated|pll_cmuplldprioout [5602],\pma_direct|auto_generated|pll_cmuplldprioout [5601],
+\pma_direct|auto_generated|pll_cmuplldprioout [5600],\pma_direct|auto_generated|pll_cmuplldprioout [5599],\pma_direct|auto_generated|pll_cmuplldprioout [5598],\pma_direct|auto_generated|pll_cmuplldprioout [5597],\pma_direct|auto_generated|pll_cmuplldprioout [5596],
+\pma_direct|auto_generated|pll_cmuplldprioout [5595],\pma_direct|auto_generated|pll_cmuplldprioout [5594],\pma_direct|auto_generated|pll_cmuplldprioout [5593],\pma_direct|auto_generated|pll_cmuplldprioout [5592],\pma_direct|auto_generated|pll_cmuplldprioout [5591],
+\pma_direct|auto_generated|pll_cmuplldprioout [5590],\pma_direct|auto_generated|pll_cmuplldprioout [5589],\pma_direct|auto_generated|pll_cmuplldprioout [5588],\pma_direct|auto_generated|pll_cmuplldprioout [5587],\pma_direct|auto_generated|pll_cmuplldprioout [5586],
+\pma_direct|auto_generated|pll_cmuplldprioout [5585],\pma_direct|auto_generated|pll_cmuplldprioout [5584],\pma_direct|auto_generated|pll_cmuplldprioout [5583],\pma_direct|auto_generated|pll_cmuplldprioout [5582],\pma_direct|auto_generated|pll_cmuplldprioout [5581],
+\pma_direct|auto_generated|pll_cmuplldprioout [5580],\pma_direct|auto_generated|pll_cmuplldprioout [5579],\pma_direct|auto_generated|pll_cmuplldprioout [5578],\pma_direct|auto_generated|pll_cmuplldprioout [5577],\pma_direct|auto_generated|pll_cmuplldprioout [5576],
+\pma_direct|auto_generated|pll_cmuplldprioout [5575],\pma_direct|auto_generated|pll_cmuplldprioout [5574],\pma_direct|auto_generated|pll_cmuplldprioout [5573],\pma_direct|auto_generated|pll_cmuplldprioout [5572],\pma_direct|auto_generated|pll_cmuplldprioout [5571],
+\pma_direct|auto_generated|pll_cmuplldprioout [5570],\pma_direct|auto_generated|pll_cmuplldprioout [5569],\pma_direct|auto_generated|pll_cmuplldprioout [5568],\pma_direct|auto_generated|pll_cmuplldprioout [5567],\pma_direct|auto_generated|pll_cmuplldprioout [5566],
+\pma_direct|auto_generated|pll_cmuplldprioout [5565],\pma_direct|auto_generated|pll_cmuplldprioout [5564],\pma_direct|auto_generated|pll_cmuplldprioout [5563],\pma_direct|auto_generated|pll_cmuplldprioout [5562],\pma_direct|auto_generated|pll_cmuplldprioout [5561],
+\pma_direct|auto_generated|pll_cmuplldprioout [5560],\pma_direct|auto_generated|pll_cmuplldprioout [5559],\pma_direct|auto_generated|pll_cmuplldprioout [5558],\pma_direct|auto_generated|pll_cmuplldprioout [5557],\pma_direct|auto_generated|pll_cmuplldprioout [5556],
+\pma_direct|auto_generated|pll_cmuplldprioout [5555],\pma_direct|auto_generated|pll_cmuplldprioout [5554],\pma_direct|auto_generated|pll_cmuplldprioout [5553],\pma_direct|auto_generated|pll_cmuplldprioout [5552],\pma_direct|auto_generated|pll_cmuplldprioout [5551],
+\pma_direct|auto_generated|pll_cmuplldprioout [5550],\pma_direct|auto_generated|pll_cmuplldprioout [5549],\pma_direct|auto_generated|pll_cmuplldprioout [5548],\pma_direct|auto_generated|pll_cmuplldprioout [5547],\pma_direct|auto_generated|pll_cmuplldprioout [5546],
+\pma_direct|auto_generated|pll_cmuplldprioout [5545],\pma_direct|auto_generated|pll_cmuplldprioout [5544],\pma_direct|auto_generated|pll_cmuplldprioout [5543],\pma_direct|auto_generated|pll_cmuplldprioout [5542],\pma_direct|auto_generated|pll_cmuplldprioout [5541],
+\pma_direct|auto_generated|pll_cmuplldprioout [5540],\pma_direct|auto_generated|pll_cmuplldprioout [5539],\pma_direct|auto_generated|pll_cmuplldprioout [5538],\pma_direct|auto_generated|pll_cmuplldprioout [5537],\pma_direct|auto_generated|pll_cmuplldprioout [5536],
+\pma_direct|auto_generated|pll_cmuplldprioout [5535],\pma_direct|auto_generated|pll_cmuplldprioout [5534],\pma_direct|auto_generated|pll_cmuplldprioout [5533],\pma_direct|auto_generated|pll_cmuplldprioout [5532],\pma_direct|auto_generated|pll_cmuplldprioout [5531],
+\pma_direct|auto_generated|pll_cmuplldprioout [5530],\pma_direct|auto_generated|pll_cmuplldprioout [5529],\pma_direct|auto_generated|pll_cmuplldprioout [5528],\pma_direct|auto_generated|pll_cmuplldprioout [5527],\pma_direct|auto_generated|pll_cmuplldprioout [5526],
+\pma_direct|auto_generated|pll_cmuplldprioout [5525],\pma_direct|auto_generated|pll_cmuplldprioout [5524],\pma_direct|auto_generated|pll_cmuplldprioout [5523],\pma_direct|auto_generated|pll_cmuplldprioout [5522],\pma_direct|auto_generated|pll_cmuplldprioout [5521],
+\pma_direct|auto_generated|pll_cmuplldprioout [5520],\pma_direct|auto_generated|pll_cmuplldprioout [5519],\pma_direct|auto_generated|pll_cmuplldprioout [5518],\pma_direct|auto_generated|pll_cmuplldprioout [5517],\pma_direct|auto_generated|pll_cmuplldprioout [5516],
+\pma_direct|auto_generated|pll_cmuplldprioout [5515],\pma_direct|auto_generated|pll_cmuplldprioout [5514],\pma_direct|auto_generated|pll_cmuplldprioout [5513],\pma_direct|auto_generated|pll_cmuplldprioout [5512],\pma_direct|auto_generated|pll_cmuplldprioout [5511],
+\pma_direct|auto_generated|pll_cmuplldprioout [5510],\pma_direct|auto_generated|pll_cmuplldprioout [5509],\pma_direct|auto_generated|pll_cmuplldprioout [5508],\pma_direct|auto_generated|pll_cmuplldprioout [5507],\pma_direct|auto_generated|pll_cmuplldprioout [5506],
+\pma_direct|auto_generated|pll_cmuplldprioout [5505],\pma_direct|auto_generated|pll_cmuplldprioout [5504],\pma_direct|auto_generated|pll_cmuplldprioout [5503],\pma_direct|auto_generated|pll_cmuplldprioout [5502],\pma_direct|auto_generated|pll_cmuplldprioout [5501],
+\pma_direct|auto_generated|pll_cmuplldprioout [5500],\pma_direct|auto_generated|pll_cmuplldprioout [5499],\pma_direct|auto_generated|pll_cmuplldprioout [5498],\pma_direct|auto_generated|pll_cmuplldprioout [5497],\pma_direct|auto_generated|pll_cmuplldprioout [5496],
+\pma_direct|auto_generated|pll_cmuplldprioout [5495],\pma_direct|auto_generated|pll_cmuplldprioout [5494],\pma_direct|auto_generated|pll_cmuplldprioout [5493],\pma_direct|auto_generated|pll_cmuplldprioout [5492],\pma_direct|auto_generated|pll_cmuplldprioout [5491],
+\pma_direct|auto_generated|pll_cmuplldprioout [5490],\pma_direct|auto_generated|pll_cmuplldprioout [5489],\pma_direct|auto_generated|pll_cmuplldprioout [5488],\pma_direct|auto_generated|pll_cmuplldprioout [5487],\pma_direct|auto_generated|pll_cmuplldprioout [5486],
+\pma_direct|auto_generated|pll_cmuplldprioout [5485],\pma_direct|auto_generated|pll_cmuplldprioout [5484],\pma_direct|auto_generated|pll_cmuplldprioout [5483],\pma_direct|auto_generated|pll_cmuplldprioout [5482],\pma_direct|auto_generated|pll_cmuplldprioout [5481],
+\pma_direct|auto_generated|pll_cmuplldprioout [5480],\pma_direct|auto_generated|pll_cmuplldprioout [5479],\pma_direct|auto_generated|pll_cmuplldprioout [5478],\pma_direct|auto_generated|pll_cmuplldprioout [5477],\pma_direct|auto_generated|pll_cmuplldprioout [5476],
+\pma_direct|auto_generated|pll_cmuplldprioout [5475],\pma_direct|auto_generated|pll_cmuplldprioout [5474],\pma_direct|auto_generated|pll_cmuplldprioout [5473],\pma_direct|auto_generated|pll_cmuplldprioout [5472],\pma_direct|auto_generated|pll_cmuplldprioout [5471],
+\pma_direct|auto_generated|pll_cmuplldprioout [5470],\pma_direct|auto_generated|pll_cmuplldprioout [5469],\pma_direct|auto_generated|pll_cmuplldprioout [5468],\pma_direct|auto_generated|pll_cmuplldprioout [5467],\pma_direct|auto_generated|pll_cmuplldprioout [5466],
+\pma_direct|auto_generated|pll_cmuplldprioout [5465],\pma_direct|auto_generated|pll_cmuplldprioout [5464],\pma_direct|auto_generated|pll_cmuplldprioout [5463],\pma_direct|auto_generated|pll_cmuplldprioout [5462],\pma_direct|auto_generated|pll_cmuplldprioout [5461],
+\pma_direct|auto_generated|pll_cmuplldprioout [5460],\pma_direct|auto_generated|pll_cmuplldprioout [5459],\pma_direct|auto_generated|pll_cmuplldprioout [5458],\pma_direct|auto_generated|pll_cmuplldprioout [5457],\pma_direct|auto_generated|pll_cmuplldprioout [5456],
+\pma_direct|auto_generated|pll_cmuplldprioout [5455],\pma_direct|auto_generated|pll_cmuplldprioout [5454],\pma_direct|auto_generated|pll_cmuplldprioout [5453],\pma_direct|auto_generated|pll_cmuplldprioout [5452],\pma_direct|auto_generated|pll_cmuplldprioout [5451],
+\pma_direct|auto_generated|pll_cmuplldprioout [5450],\pma_direct|auto_generated|pll_cmuplldprioout [5449],\pma_direct|auto_generated|pll_cmuplldprioout [5448],\pma_direct|auto_generated|pll_cmuplldprioout [5447],\pma_direct|auto_generated|pll_cmuplldprioout [5446],
+\pma_direct|auto_generated|pll_cmuplldprioout [5445],\pma_direct|auto_generated|pll_cmuplldprioout [5444],\pma_direct|auto_generated|pll_cmuplldprioout [5443],\pma_direct|auto_generated|pll_cmuplldprioout [5442],\pma_direct|auto_generated|pll_cmuplldprioout [5441],
+\pma_direct|auto_generated|pll_cmuplldprioout [5440],\pma_direct|auto_generated|pll_cmuplldprioout [5439],\pma_direct|auto_generated|pll_cmuplldprioout [5438],\pma_direct|auto_generated|pll_cmuplldprioout [5437],\pma_direct|auto_generated|pll_cmuplldprioout [5436],
+\pma_direct|auto_generated|pll_cmuplldprioout [5435],\pma_direct|auto_generated|pll_cmuplldprioout [5434],\pma_direct|auto_generated|pll_cmuplldprioout [5433],\pma_direct|auto_generated|pll_cmuplldprioout [5432],\pma_direct|auto_generated|pll_cmuplldprioout [5431],
+\pma_direct|auto_generated|pll_cmuplldprioout [5430],\pma_direct|auto_generated|pll_cmuplldprioout [5429],\pma_direct|auto_generated|pll_cmuplldprioout [5428],\pma_direct|auto_generated|pll_cmuplldprioout [5427],\pma_direct|auto_generated|pll_cmuplldprioout [5426],
+\pma_direct|auto_generated|pll_cmuplldprioout [5425],\pma_direct|auto_generated|pll_cmuplldprioout [5424],\pma_direct|auto_generated|pll_cmuplldprioout [5423],\pma_direct|auto_generated|pll_cmuplldprioout [5422],\pma_direct|auto_generated|pll_cmuplldprioout [5421],
+\pma_direct|auto_generated|pll_cmuplldprioout [5420],\pma_direct|auto_generated|pll_cmuplldprioout [5419],\pma_direct|auto_generated|pll_cmuplldprioout [5418],\pma_direct|auto_generated|pll_cmuplldprioout [5417],\pma_direct|auto_generated|pll_cmuplldprioout [5416],
+\pma_direct|auto_generated|pll_cmuplldprioout [5415],\pma_direct|auto_generated|pll_cmuplldprioout [5414],\pma_direct|auto_generated|pll_cmuplldprioout [5413],\pma_direct|auto_generated|pll_cmuplldprioout [5412],\pma_direct|auto_generated|pll_cmuplldprioout [5411],
+\pma_direct|auto_generated|pll_cmuplldprioout [5410],\pma_direct|auto_generated|pll_cmuplldprioout [5409],\pma_direct|auto_generated|pll_cmuplldprioout [5408],\pma_direct|auto_generated|pll_cmuplldprioout [5407],\pma_direct|auto_generated|pll_cmuplldprioout [5406],
+\pma_direct|auto_generated|pll_cmuplldprioout [5405],\pma_direct|auto_generated|pll_cmuplldprioout [5404],\pma_direct|auto_generated|pll_cmuplldprioout [5403],\pma_direct|auto_generated|pll_cmuplldprioout [5402],\pma_direct|auto_generated|pll_cmuplldprioout [5401],
+\pma_direct|auto_generated|pll_cmuplldprioout [5400]}),
+ .cmudividerdprioin({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [499],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [498],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [497],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [496],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [495],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [494],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [493],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [492],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [491],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [490],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [489],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [488],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [487],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [486],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [485],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [484],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [483],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [482],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [481],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [480],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [479],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [478],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [477],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [476],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [475],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [474],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [473],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [472],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [471],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [470],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [469],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [468],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [467],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [466],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [465],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [464],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [463],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [462],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [461],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [460],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [459],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [458],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [457],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [456],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [455],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [454],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [453],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [452],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [451],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [450],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [449],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [448],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [447],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [446],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [445],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [444],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [443],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [442],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [441],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [440],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [439],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [438],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [437],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [436],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [435],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [434],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [433],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [432],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [431],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [430],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [429],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [428],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [427],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [426],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [425],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [424],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [423],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [422],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [421],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [420],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [419],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [418],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [417],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [416],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [415],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [414],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [413],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [412],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [411],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [410],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [409],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [408],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [407],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [406],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [405],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [404],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [403],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [402],\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [401],
+\pma_direct|auto_generated|edge_clk_div_cmudividerdprioin [400],gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
+gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
+ .refclkdividerdprioin(2'b00),
+ .fixedclk({gnd,gnd,\reconfig_clk~inputclkctrl_outclk ,\reconfig_clk~inputclkctrl_outclk ,\reconfig_clk~inputclkctrl_outclk ,\reconfig_clk~inputclkctrl_outclk }),
+ .rxdigitalreset(4'b0000),
+ .txdigitalreset(4'b0000),
+ .rxanalogreset({gnd,gnd,\pma_direct|auto_generated|rx_analogreset_in [3],\pma_direct|auto_generated|rx_analogreset_in [2],\pma_direct|auto_generated|rx_analogreset_in [1],\pma_direct|auto_generated|rx_analogreset_in [0]}),
+ .rxpowerdown(6'b000000),
+ .txpllreset({gnd,\pll_powerdown~input_o }),
+ .testin(10000'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000),
+ .scanin(23'b00000000000000000000000),
+ .extra10gin(7'b0000000),
+ .lccmurtestbussel(3'b000),
+ .extra10gout(),
+ .alignstatus(),
+ .enabledeskew(),
+ .fiforesetrd(),
+ .quadresetout(\pma_direct|auto_generated|edge_cmu_quadresetout [0]),
+ .dprioout(\pma_direct|auto_generated|tx_pll_cent_unit0~DPRIOOUT ),
+ .dpriooe(),
+ .dpriodisableout(\pma_direct|auto_generated|edge_cmu_dpriodisableout [0]),
+ .txphfifox4wrenableout(),
+ .txphfifox4rdenableout(),
+ .txphfifox4byteselout(),
+ .txphfifox4rdclkout(),
+ .rxphfifox4wrenableout(),
+ .rxphfifox4rdenableout(),
+ .rxphfifox4byteselout(),
+ .rxphfifox4wrclkout(),
+ .autospdx4configsel(),
+ .autospdx4rateswitchout(),
+ .autospdx4spdchg(),
+ .phfifiox4ptrsreset(),
+ .lccmutestbus(),
+ .rxdataout(),
+ .rxctrlout(),
+ .txdataout(),
+ .txctrlout(),
+ .digitaltestout(),
+ .pllresetout(\pma_direct|auto_generated|tx_pll_cent_unit0_PLLRESETOUT_bus ),
+ .rxdigitalresetout(),
+ .txdigitalresetout(),
+ .rxanalogresetout(\pma_direct|auto_generated|tx_pll_cent_unit0_RXANALOGRESETOUT_bus ),
+ .txanalogresetout(\pma_direct|auto_generated|tx_pll_cent_unit0_TXANALOGRESETOUT_bus ),
+ .rxadceresetout(),
+ .rxcruresetout(\pma_direct|auto_generated|tx_pll_cent_unit0_RXCRURESETOUT_bus ),
+ .rxadcepowerdown(),
+ .rxcrupowerdown(\pma_direct|auto_generated|tx_pll_cent_unit0_RXCRUPOWERDOWN_bus ),
+ .rxibpowerdown(\pma_direct|auto_generated|tx_pll_cent_unit0_RXIBPOWERDOWN_bus ),
+ .txobpowerdown(\pma_direct|auto_generated|tx_pll_cent_unit0_TXOBPOWERDOWN_bus ),
+ .txdividerpowerdown(),
+ .txdetectrxpowerdown(\pma_direct|auto_generated|tx_pll_cent_unit0_TXDETECTRXPOWERDOWN_bus ),
+ .pllpowerdn(\pma_direct|auto_generated|tx_pll_cent_unit0_PLLPOWERDN_bus ),
+ .clkdivpowerdn(\pma_direct|auto_generated|tx_pll_cent_unit0_CLKDIVPOWERDN_bus ),
+ .rxpmadprioout(\pma_direct|auto_generated|tx_pll_cent_unit0_RXPMADPRIOOUT_bus ),
+ .rxpcsdprioout(),
+ .txpmadprioout(\pma_direct|auto_generated|tx_pll_cent_unit0_TXPMADPRIOOUT_bus ),
+ .txpcsdprioout(),
+ .cmuplldprioout(\pma_direct|auto_generated|tx_pll_cent_unit0_CMUPLLDPRIOOUT_bus ),
+ .cmudividerdprioout(\pma_direct|auto_generated|tx_pll_cent_unit0_CMUDIVIDERDPRIOOUT_bus ),
+ .refclkdividerdprioout(),
+ .testout(),
+ .scanout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .analog_test_bus_enable = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .auto_spd_deassert_ph_fifo_rst_count = 8;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .auto_spd_phystatus_notify_count = 14;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .bonded_quad_mode = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .bypass_bandgap = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .central_test_bus_select = 0;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .clkdiv0_inclk0_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .clkdiv0_inclk1_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .clkdiv1_inclk0_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .clkdiv1_inclk1_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .clkdiv2_inclk0_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .clkdiv2_inclk1_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .clkdiv3_inclk0_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .clkdiv3_inclk1_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .clkdiv4_inclk0_logical_to_physical_mapping = "pll0";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .clkdiv4_inclk1_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .clkdiv5_inclk0_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .clkdiv5_inclk1_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .cmu_type = "regular";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .devaddr = 1;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .dprio_config_mode = 6'b000000;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .in_xaui_mode = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .num_con_align_chars_for_align = 0;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .num_con_errors_for_align_loss = 0;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .num_con_good_data_for_align_approach = 0;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .offset_all_errors_align = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pipe_auto_speed_nego_enable = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pipe_freq_scale_mode = "frequency";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll0_inclk0_logical_to_physical_mapping = "pld_clk";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll0_inclk1_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll0_inclk2_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll0_inclk3_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll0_inclk4_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll0_inclk5_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll0_inclk6_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll0_inclk7_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll0_inclk8_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll0_inclk9_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll0_logical_to_physical_mapping = 0;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll1_inclk0_logical_to_physical_mapping = "pld_clk";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll1_inclk1_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll1_inclk2_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll1_inclk3_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll1_inclk4_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll1_inclk5_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll1_inclk6_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll1_inclk7_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll1_inclk8_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll1_inclk9_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll1_logical_to_physical_mapping = 1;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll2_inclk0_logical_to_physical_mapping = "pld_clk";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll2_inclk1_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll2_inclk2_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll2_inclk3_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll2_inclk4_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll2_inclk5_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll2_inclk6_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll2_inclk7_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll2_inclk8_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll2_inclk9_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll2_logical_to_physical_mapping = 2;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll3_inclk0_logical_to_physical_mapping = "pld_clk";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll3_inclk1_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll3_inclk2_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll3_inclk3_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll3_inclk4_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll3_inclk5_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll3_inclk6_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll3_inclk7_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll3_inclk8_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll3_inclk9_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll3_logical_to_physical_mapping = 3;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll4_inclk0_logical_to_physical_mapping = "pld_clk";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll4_inclk1_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll4_inclk2_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll4_inclk3_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll4_inclk4_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll4_inclk5_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll4_inclk6_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll4_inclk7_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll4_inclk8_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll4_inclk9_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll4_logical_to_physical_mapping = 4;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll5_inclk0_logical_to_physical_mapping = "clkrefclk0";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll5_inclk1_logical_to_physical_mapping = "clkrefclk1";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll5_inclk2_logical_to_physical_mapping = "iq2";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll5_inclk3_logical_to_physical_mapping = "iq3";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll5_inclk4_logical_to_physical_mapping = "iq4";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll5_inclk5_logical_to_physical_mapping = "iq5";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll5_inclk6_logical_to_physical_mapping = "iq6";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll5_inclk7_logical_to_physical_mapping = "iq7";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll5_inclk8_logical_to_physical_mapping = "pld_clk";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll5_inclk9_logical_to_physical_mapping = "gpll_clk";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pll5_logical_to_physical_mapping = 5;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .pma_done_count = 249950;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .portaddr = 1;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx0_auto_spd_self_switch_enable = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx0_channel_bonding = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx0_clk1_mux_select = "recovered clock";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx0_clk2_mux_select = "recovered clock";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx0_clk_pd_enable = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx0_logical_to_physical_mapping = 0;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx0_ph_fifo_reg_mode = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx0_ph_fifo_reset_enable = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx0_ph_fifo_user_ctrl_enable = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx0_phfifo_wait_cnt = 0;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx0_rd_clk_mux_select = "core clock";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx0_recovered_clk_mux_select = "recovered clock";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx0_reset_clock_output_during_digital_reset = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx0_use_double_data_mode = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx1_logical_to_physical_mapping = 1;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx2_logical_to_physical_mapping = 2;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx3_logical_to_physical_mapping = 3;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx4_logical_to_physical_mapping = 4;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx5_logical_to_physical_mapping = 5;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx_master_direction = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .rx_xaui_sm_backward_compatible_enable = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .test_mode = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx0_auto_spd_self_switch_enable = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx0_channel_bonding = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx0_clk_pd_enable = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx0_logical_to_physical_mapping = 0;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx0_ph_fifo_reg_mode = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx0_ph_fifo_reset_enable = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx0_ph_fifo_user_ctrl_enable = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx0_pma_inclk0_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx0_pma_inclk1_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx0_pma_inclk2_logical_to_physical_mapping = "x4";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx0_pma_inclk3_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx0_pma_inclk4_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx0_rd_clk_mux_select = "cmu_clock_divider";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx0_reset_clock_output_during_digital_reset = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx0_use_double_data_mode = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx0_wr_clk_mux_select = "core_clk";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx1_logical_to_physical_mapping = 1;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx1_pma_inclk0_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx1_pma_inclk1_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx1_pma_inclk2_logical_to_physical_mapping = "x4";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx1_pma_inclk3_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx1_pma_inclk4_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx2_logical_to_physical_mapping = 2;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx2_pma_inclk0_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx2_pma_inclk1_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx2_pma_inclk2_logical_to_physical_mapping = "x4";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx2_pma_inclk3_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx2_pma_inclk4_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx3_logical_to_physical_mapping = 3;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx3_pma_inclk0_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx3_pma_inclk1_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx3_pma_inclk2_logical_to_physical_mapping = "x4";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx3_pma_inclk3_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx3_pma_inclk4_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx4_logical_to_physical_mapping = 4;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx4_pma_inclk0_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx4_pma_inclk1_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx4_pma_inclk2_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx4_pma_inclk3_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx4_pma_inclk4_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx5_logical_to_physical_mapping = 5;
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx5_pma_inclk0_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx5_pma_inclk1_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx5_pma_inclk2_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx5_pma_inclk3_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx5_pma_inclk4_logical_to_physical_mapping = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx_master_direction = "none";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx_pll0_used_as_rx_cdr = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx_pll1_used_as_rx_cdr = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .tx_xaui_sm_backward_compatible_enable = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .use_deskew_fifo = "false";
+defparam \pma_direct|auto_generated|tx_pll_cent_unit0 .vcceh_voltage = "2.5v";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y28_N1
+stratixiv_io_ibuf \tx_datain[60]~input (
+ .i(tx_datain[60]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[60]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[60]~input .bus_hold = "false";
+defparam \tx_datain[60]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y54_N63
+stratixiv_io_ibuf \tx_datain[61]~input (
+ .i(tx_datain[61]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[61]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[61]~input .bus_hold = "false";
+defparam \tx_datain[61]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y21_N1
+stratixiv_io_ibuf \tx_datain[62]~input (
+ .i(tx_datain[62]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[62]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[62]~input .bus_hold = "false";
+defparam \tx_datain[62]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y21_N32
+stratixiv_io_ibuf \tx_datain[63]~input (
+ .i(tx_datain[63]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[63]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[63]~input .bus_hold = "false";
+defparam \tx_datain[63]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y32_N63
+stratixiv_io_ibuf \tx_datain[64]~input (
+ .i(tx_datain[64]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[64]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[64]~input .bus_hold = "false";
+defparam \tx_datain[64]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y40_N63
+stratixiv_io_ibuf \tx_datain[65]~input (
+ .i(tx_datain[65]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[65]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[65]~input .bus_hold = "false";
+defparam \tx_datain[65]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y21_N94
+stratixiv_io_ibuf \tx_datain[66]~input (
+ .i(tx_datain[66]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[66]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[66]~input .bus_hold = "false";
+defparam \tx_datain[66]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y22_N94
+stratixiv_io_ibuf \tx_datain[67]~input (
+ .i(tx_datain[67]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[67]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[67]~input .bus_hold = "false";
+defparam \tx_datain[67]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y37_N63
+stratixiv_io_ibuf \tx_datain[68]~input (
+ .i(tx_datain[68]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[68]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[68]~input .bus_hold = "false";
+defparam \tx_datain[68]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y37_N94
+stratixiv_io_ibuf \tx_datain[69]~input (
+ .i(tx_datain[69]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[69]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[69]~input .bus_hold = "false";
+defparam \tx_datain[69]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y45_N1
+stratixiv_io_ibuf \tx_datain[70]~input (
+ .i(tx_datain[70]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[70]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[70]~input .bus_hold = "false";
+defparam \tx_datain[70]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y21_N63
+stratixiv_io_ibuf \tx_datain[71]~input (
+ .i(tx_datain[71]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[71]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[71]~input .bus_hold = "false";
+defparam \tx_datain[71]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y37_N1
+stratixiv_io_ibuf \tx_datain[72]~input (
+ .i(tx_datain[72]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[72]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[72]~input .bus_hold = "false";
+defparam \tx_datain[72]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y28_N63
+stratixiv_io_ibuf \tx_datain[73]~input (
+ .i(tx_datain[73]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[73]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[73]~input .bus_hold = "false";
+defparam \tx_datain[73]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y18_N63
+stratixiv_io_ibuf \tx_datain[74]~input (
+ .i(tx_datain[74]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[74]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[74]~input .bus_hold = "false";
+defparam \tx_datain[74]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y48_N94
+stratixiv_io_ibuf \tx_datain[75]~input (
+ .i(tx_datain[75]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[75]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[75]~input .bus_hold = "false";
+defparam \tx_datain[75]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y35_N32
+stratixiv_io_ibuf \tx_datain[76]~input (
+ .i(tx_datain[76]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[76]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[76]~input .bus_hold = "false";
+defparam \tx_datain[76]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y50_N94
+stratixiv_io_ibuf \tx_datain[77]~input (
+ .i(tx_datain[77]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[77]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[77]~input .bus_hold = "false";
+defparam \tx_datain[77]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y56_N94
+stratixiv_io_ibuf \tx_datain[78]~input (
+ .i(tx_datain[78]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[78]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[78]~input .bus_hold = "false";
+defparam \tx_datain[78]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y48_N32
+stratixiv_io_ibuf \tx_datain[79]~input (
+ .i(tx_datain[79]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[79]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[79]~input .bus_hold = "false";
+defparam \tx_datain[79]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: CLOCKDIVIDER_X0_Y9_N136
+stratixiv_hssi_clock_divider \pma_direct|auto_generated|central_clk_div0 (
+ .rateswitch(gnd),
+ .powerdn(\pma_direct|auto_generated|edge_cmu_clkdivpowerdn [0]),
+ .quadreset(\pma_direct|auto_generated|edge_cmu_quadresetout [0]),
+ .dpriodisable(\pma_direct|auto_generated|edge_cmu_dpriodisableout [0]),
+ .refclkdig(gnd),
+ .vcobypassin(gnd),
+ .clk0in({\pma_direct|auto_generated|clock_divider_clk0in [3],\pma_direct|auto_generated|clock_divider_clk0in [2],\pma_direct|auto_generated|clock_divider_clk0in [1],\pma_direct|auto_generated|clock_divider_clk0in [0]}),
+ .clk1in(4'b0000),
+ .refclkin(2'b00),
+ .rateswitchdonein(2'b00),
+ .rateswitchbaseclkin(2'b00),
+ .dprioin({\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [99],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [98],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [97],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [96],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [95],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [94],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [93],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [92],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [91],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [90],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [89],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [88],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [87],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [86],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [85],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [84],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [83],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [82],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [81],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [80],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [79],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [78],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [77],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [76],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [75],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [74],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [73],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [72],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [71],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [70],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [69],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [68],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [67],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [66],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [65],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [64],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [63],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [62],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [61],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [60],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [59],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [58],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [57],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [56],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [55],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [54],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [53],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [52],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [51],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [50],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [49],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [48],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [47],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [46],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [45],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [44],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [43],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [42],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [41],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [40],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [39],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [38],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [37],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [36],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [35],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [34],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [33],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [32],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [31],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [30],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [29],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [28],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [27],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [26],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [25],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [24],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [23],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [22],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [21],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [20],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [19],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [18],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [17],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [16],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [15],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [14],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [13],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [12],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [11],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [10],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [9],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [8],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [7],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [6],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [5],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [4],
+\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [3],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [2],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [1],\pma_direct|auto_generated|edge_cmu_cmudividerdprioout [0]}),
+ .analogrefclkpulseshifted(),
+ .analogrefclkpulse(\pma_direct|auto_generated|edge_pll_analogrefclkpulse [0]),
+ .refclkout(\pma_direct|auto_generated|refclk_pma_wire [0]),
+ .coreclkout(\pma_direct|auto_generated|central_clk_div0~coreclkout ),
+ .rateswitchdone(),
+ .rateswitchbaseclock(),
+ .rateswitchout(),
+ .analogrefclkoutshifted(),
+ .analogfastrefclkoutshifted(),
+ .analogrefclkout(\pma_direct|auto_generated|central_clk_div0_ANALOGREFCLKOUT_bus ),
+ .analogfastrefclkout(\pma_direct|auto_generated|central_clk_div0_ANALOGFASTREFCLKOUT_bus ),
+ .dprioout(\pma_direct|auto_generated|central_clk_div0_DPRIOOUT_bus ));
+// synopsys translate_off
+defparam \pma_direct|auto_generated|central_clk_div0 .channel_num = 4;
+defparam \pma_direct|auto_generated|central_clk_div0 .coreclk_out_gated_by_quad_reset = "false";
+defparam \pma_direct|auto_generated|central_clk_div0 .data_rate = 0;
+defparam \pma_direct|auto_generated|central_clk_div0 .divide_by = 5;
+defparam \pma_direct|auto_generated|central_clk_div0 .divider_type = "central_enhanced";
+defparam \pma_direct|auto_generated|central_clk_div0 .dprio_config_mode = 6'b000000;
+defparam \pma_direct|auto_generated|central_clk_div0 .effective_data_rate = "3125.0 mbps";
+defparam \pma_direct|auto_generated|central_clk_div0 .enable_dynamic_divider = "false";
+defparam \pma_direct|auto_generated|central_clk_div0 .enable_refclk_out = "true";
+defparam \pma_direct|auto_generated|central_clk_div0 .inclk_select = 0;
+defparam \pma_direct|auto_generated|central_clk_div0 .logical_channel_address = 0;
+defparam \pma_direct|auto_generated|central_clk_div0 .pre_divide_by = 1;
+defparam \pma_direct|auto_generated|central_clk_div0 .rate_switch_base_clk_in_select = 0;
+defparam \pma_direct|auto_generated|central_clk_div0 .rate_switch_done_in_select = 0;
+defparam \pma_direct|auto_generated|central_clk_div0 .refclk_divide_by = 0;
+defparam \pma_direct|auto_generated|central_clk_div0 .refclk_multiply_by = 0;
+defparam \pma_direct|auto_generated|central_clk_div0 .refclkin_select = 0;
+defparam \pma_direct|auto_generated|central_clk_div0 .select_local_rate_switch_base_clock = "true";
+defparam \pma_direct|auto_generated|central_clk_div0 .select_local_rate_switch_done = "false";
+defparam \pma_direct|auto_generated|central_clk_div0 .select_local_refclk = "true";
+defparam \pma_direct|auto_generated|central_clk_div0 .select_refclk_dig = "false";
+defparam \pma_direct|auto_generated|central_clk_div0 .sim_analogfastrefclkout_phase_shift = 0;
+defparam \pma_direct|auto_generated|central_clk_div0 .sim_analogrefclkout_phase_shift = 0;
+defparam \pma_direct|auto_generated|central_clk_div0 .sim_coreclkout_phase_shift = 0;
+defparam \pma_direct|auto_generated|central_clk_div0 .sim_refclkout_phase_shift = 0;
+defparam \pma_direct|auto_generated|central_clk_div0 .use_coreclk_out_post_divider = "false";
+defparam \pma_direct|auto_generated|central_clk_div0 .use_refclk_post_divider = "true";
+defparam \pma_direct|auto_generated|central_clk_div0 .use_vco_bypass = "false";
+// synopsys translate_on
+
+// Location: TXPMA_X0_Y18_N138
+stratixiv_hssi_tx_pma \pma_direct|auto_generated|transmit_pma3 (
+ .dpriodisable(\pma_direct|auto_generated|edge_cmu_dpriodisableout [0]),
+ .txpmareset(\pma_direct|auto_generated|tx_pll_cent_unit0~TXANALOGRESETOUT3 ),
+ .powerdn(\pma_direct|auto_generated|tx_pll_cent_unit0~TXOBPOWERDN3 ),
+ .forceelecidle(gnd),
+ .rxdetecten(gnd),
+ .detectrxpowerdown(\pma_direct|auto_generated|tx_pll_cent_unit0~TXDETECTRXPOWERDN3 ),
+ .rxdetectclk(gnd),
+ .refclk0inpulse(gnd),
+ .refclk1inpulse(gnd),
+ .refclk2inpulse(\pma_direct|auto_generated|edge_pll_analogrefclkpulse [0]),
+ .refclk3inpulse(gnd),
+ .refclk4inpulse(gnd),
+ .revserialfdbk(gnd),
+ .dprioin({\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1199 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1198 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1197 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1196 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1195 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1194 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1193 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1192 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1191 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1190 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1189 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1188 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1187 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1186 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1185 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1184 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1183 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1182 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1181 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1180 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1179 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1178 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1177 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1176 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1175 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1174 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1173 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1172 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1171 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1170 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1169 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1168 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1167 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1166 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1165 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1164 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1163 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1162 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1161 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1160 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1159 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1158 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1157 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1156 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1155 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1154 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1153 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1152 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1151 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1150 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1149 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1148 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1147 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1146 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1145 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1144 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1143 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1142 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1141 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1140 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1139 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1138 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1137 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1136 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1135 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1134 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1133 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1132 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1131 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1130 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1129 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1128 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1127 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1126 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1125 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1124 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1123 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1122 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1121 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1120 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1119 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1118 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1117 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1116 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1115 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1114 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1113 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1112 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1111 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1110 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1109 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1108 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1107 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1106 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1105 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1104 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1103 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1102 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1101 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1100 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1099 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1098 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1097 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1096 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1095 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1094 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1093 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1092 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1091 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1090 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1089 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1088 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1087 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1086 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1085 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1084 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1083 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1082 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1081 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1080 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1079 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1078 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1077 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1076 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1075 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1074 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1073 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1072 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1071 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1070 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1069 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1068 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1067 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1066 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1065 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1064 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1063 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1062 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1061 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1060 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1059 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1058 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1057 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1056 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1055 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1054 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1053 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1052 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1051 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1050 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1049 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1048 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1047 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1046 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1045 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1044 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1043 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1042 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1041 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1040 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1039 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1038 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1037 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1036 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1035 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1034 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1033 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1032 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1031 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1030 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1029 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1028 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1027 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1026 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1025 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1024 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1023 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1022 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1021 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1020 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1019 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1018 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1017 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1016 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1015 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1014 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1013 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1012 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1011 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1010 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1009 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1008 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1007 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1006 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1005 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1004 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1003 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1002 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1001 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1000 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT999 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT998 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT997 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT996 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT995 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT994 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT993 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT992 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT991 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT990 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT989 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT988 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT987 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT986 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT985 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT984 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT983 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT982 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT981 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT980 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT979 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT978 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT977 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT976 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT975 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT974 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT973 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT972 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT971 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT970 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT969 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT968 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT967 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT966 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT965 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT964 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT963 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT962 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT961 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT960 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT959 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT958 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT957 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT956 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT955 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT954 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT953 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT952 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT951 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT950 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT949 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT948 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT947 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT946 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT945 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT944 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT943 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT942 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT941 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT940 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT939 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT938 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT937 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT936 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT935 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT934 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT933 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT932 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT931 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT930 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT929 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT928 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT927 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT926 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT925 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT924 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT923 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT922 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT921 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT920 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT919 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT918 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT917 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT916 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT915 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT914 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT913 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT912 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT911 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT910 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT909 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT908 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT907 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT906 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT905 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT904 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT903 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT902 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT901 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT900 }),
+ .datain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\tx_datain[79]~input_o ,\tx_datain[78]~input_o ,\tx_datain[77]~input_o ,\tx_datain[76]~input_o ,\tx_datain[75]~input_o ,
+\tx_datain[74]~input_o ,\tx_datain[73]~input_o ,\tx_datain[72]~input_o ,\tx_datain[71]~input_o ,\tx_datain[70]~input_o ,\tx_datain[69]~input_o ,\tx_datain[68]~input_o ,\tx_datain[67]~input_o ,\tx_datain[66]~input_o ,\tx_datain[65]~input_o ,\tx_datain[64]~input_o ,
+\tx_datain[63]~input_o ,\tx_datain[62]~input_o ,\tx_datain[61]~input_o ,\tx_datain[60]~input_o }),
+ .refclk0in(2'b00),
+ .fastrefclk0in(2'b00),
+ .refclk1in(2'b00),
+ .fastrefclk1in(2'b00),
+ .refclk2in({\pma_direct|auto_generated|edge_pll_analogrefclkout [1],\pma_direct|auto_generated|edge_pll_analogrefclkout [0]}),
+ .fastrefclk2in({\pma_direct|auto_generated|edge_pll_analogfastrefclkout [1],\pma_direct|auto_generated|edge_pll_analogfastrefclkout [0]}),
+ .refclk3in(2'b00),
+ .fastrefclk3in(2'b00),
+ .refclk4in(2'b00),
+ .fastrefclk4in(2'b00),
+ .pclk({gnd,gnd,\pma_direct|auto_generated|refclk_pma_wire [0],gnd,gnd}),
+ .extra10gin(11'b00000000000),
+ .datainfull(20'b00000000000000000000),
+ .rxdetectvalidout(),
+ .rxfoundout(),
+ .dataout(\pma_direct|auto_generated|wire_transmit_pma3_dataout ),
+ .clockout(\pma_direct|auto_generated|wire_transmit_pma3_clockout ),
+ .seriallpbkout(),
+ .dprioout(\pma_direct|auto_generated|transmit_pma3_DPRIOOUT_bus ),
+ .dftout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|transmit_pma3 .analog_power = "1.4v";
+defparam \pma_direct|auto_generated|transmit_pma3 .channel_number = 3;
+defparam \pma_direct|auto_generated|transmit_pma3 .channel_type = "regular";
+defparam \pma_direct|auto_generated|transmit_pma3 .clkin_select = 2;
+defparam \pma_direct|auto_generated|transmit_pma3 .clkmux_delay = "false";
+defparam \pma_direct|auto_generated|transmit_pma3 .common_mode = "0.65v";
+defparam \pma_direct|auto_generated|transmit_pma3 .dprio_config_mode = 6'b000001;
+defparam \pma_direct|auto_generated|transmit_pma3 .enable_reverse_serial_loopback = "false";
+defparam \pma_direct|auto_generated|transmit_pma3 .logical_channel_address = 12;
+defparam \pma_direct|auto_generated|transmit_pma3 .logical_protocol_hint_0 = "basic";
+defparam \pma_direct|auto_generated|transmit_pma3 .logical_protocol_hint_1 = "basic";
+defparam \pma_direct|auto_generated|transmit_pma3 .logical_protocol_hint_2 = "basic";
+defparam \pma_direct|auto_generated|transmit_pma3 .logical_protocol_hint_3 = "basic";
+defparam \pma_direct|auto_generated|transmit_pma3 .low_speed_test_select = 0;
+defparam \pma_direct|auto_generated|transmit_pma3 .physical_clkin0_mapping = "none";
+defparam \pma_direct|auto_generated|transmit_pma3 .physical_clkin1_mapping = "none";
+defparam \pma_direct|auto_generated|transmit_pma3 .physical_clkin2_mapping = "x4";
+defparam \pma_direct|auto_generated|transmit_pma3 .physical_clkin3_mapping = "none";
+defparam \pma_direct|auto_generated|transmit_pma3 .physical_clkin4_mapping = "none";
+defparam \pma_direct|auto_generated|transmit_pma3 .preemp_pretap = 0;
+defparam \pma_direct|auto_generated|transmit_pma3 .preemp_pretap_inv = "false";
+defparam \pma_direct|auto_generated|transmit_pma3 .preemp_tap_1 = 5;
+defparam \pma_direct|auto_generated|transmit_pma3 .preemp_tap_1_a = 0;
+defparam \pma_direct|auto_generated|transmit_pma3 .preemp_tap_1_b = 0;
+defparam \pma_direct|auto_generated|transmit_pma3 .preemp_tap_1_c = 0;
+defparam \pma_direct|auto_generated|transmit_pma3 .preemp_tap_2 = 0;
+defparam \pma_direct|auto_generated|transmit_pma3 .preemp_tap_2_inv = "false";
+defparam \pma_direct|auto_generated|transmit_pma3 .protocol_hint = "basic";
+defparam \pma_direct|auto_generated|transmit_pma3 .rx_detect = 0;
+defparam \pma_direct|auto_generated|transmit_pma3 .serialization_factor = 20;
+defparam \pma_direct|auto_generated|transmit_pma3 .slew_rate = "low";
+defparam \pma_direct|auto_generated|transmit_pma3 .termination = "oct 100 ohms";
+defparam \pma_direct|auto_generated|transmit_pma3 .use_external_termination = "false";
+defparam \pma_direct|auto_generated|transmit_pma3 .use_pclk = "true";
+defparam \pma_direct|auto_generated|transmit_pma3 .use_pma_direct = "true";
+defparam \pma_direct|auto_generated|transmit_pma3 .use_rx_detect = "false";
+defparam \pma_direct|auto_generated|transmit_pma3 .use_ser_double_data_mode = "true";
+defparam \pma_direct|auto_generated|transmit_pma3 .vod_selection = 1;
+defparam \pma_direct|auto_generated|transmit_pma3 .vod_selection_a = 0;
+defparam \pma_direct|auto_generated|transmit_pma3 .vod_selection_b = 0;
+defparam \pma_direct|auto_generated|transmit_pma3 .vod_selection_c = 0;
+defparam \pma_direct|auto_generated|transmit_pma3 .vod_selection_d = 0;
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y57_N32
+stratixiv_io_ibuf \tx_datain[40]~input (
+ .i(tx_datain[40]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[40]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[40]~input .bus_hold = "false";
+defparam \tx_datain[40]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y44_N63
+stratixiv_io_ibuf \tx_datain[41]~input (
+ .i(tx_datain[41]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[41]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[41]~input .bus_hold = "false";
+defparam \tx_datain[41]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y33_N32
+stratixiv_io_ibuf \tx_datain[42]~input (
+ .i(tx_datain[42]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[42]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[42]~input .bus_hold = "false";
+defparam \tx_datain[42]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y52_N63
+stratixiv_io_ibuf \tx_datain[43]~input (
+ .i(tx_datain[43]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[43]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[43]~input .bus_hold = "false";
+defparam \tx_datain[43]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y18_N32
+stratixiv_io_ibuf \tx_datain[44]~input (
+ .i(tx_datain[44]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[44]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[44]~input .bus_hold = "false";
+defparam \tx_datain[44]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y47_N1
+stratixiv_io_ibuf \tx_datain[45]~input (
+ .i(tx_datain[45]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[45]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[45]~input .bus_hold = "false";
+defparam \tx_datain[45]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y56_N32
+stratixiv_io_ibuf \tx_datain[46]~input (
+ .i(tx_datain[46]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[46]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[46]~input .bus_hold = "false";
+defparam \tx_datain[46]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y57_N94
+stratixiv_io_ibuf \tx_datain[47]~input (
+ .i(tx_datain[47]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[47]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[47]~input .bus_hold = "false";
+defparam \tx_datain[47]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y50_N32
+stratixiv_io_ibuf \tx_datain[48]~input (
+ .i(tx_datain[48]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[48]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[48]~input .bus_hold = "false";
+defparam \tx_datain[48]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y56_N1
+stratixiv_io_ibuf \tx_datain[49]~input (
+ .i(tx_datain[49]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[49]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[49]~input .bus_hold = "false";
+defparam \tx_datain[49]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y37_N32
+stratixiv_io_ibuf \tx_datain[50]~input (
+ .i(tx_datain[50]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[50]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[50]~input .bus_hold = "false";
+defparam \tx_datain[50]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y24_N63
+stratixiv_io_ibuf \tx_datain[51]~input (
+ .i(tx_datain[51]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[51]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[51]~input .bus_hold = "false";
+defparam \tx_datain[51]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y32_N32
+stratixiv_io_ibuf \tx_datain[52]~input (
+ .i(tx_datain[52]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[52]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[52]~input .bus_hold = "false";
+defparam \tx_datain[52]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y45_N94
+stratixiv_io_ibuf \tx_datain[53]~input (
+ .i(tx_datain[53]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[53]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[53]~input .bus_hold = "false";
+defparam \tx_datain[53]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y44_N1
+stratixiv_io_ibuf \tx_datain[54]~input (
+ .i(tx_datain[54]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[54]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[54]~input .bus_hold = "false";
+defparam \tx_datain[54]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y50_N1
+stratixiv_io_ibuf \tx_datain[55]~input (
+ .i(tx_datain[55]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[55]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[55]~input .bus_hold = "false";
+defparam \tx_datain[55]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y44_N94
+stratixiv_io_ibuf \tx_datain[56]~input (
+ .i(tx_datain[56]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[56]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[56]~input .bus_hold = "false";
+defparam \tx_datain[56]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y24_N94
+stratixiv_io_ibuf \tx_datain[57]~input (
+ .i(tx_datain[57]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[57]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[57]~input .bus_hold = "false";
+defparam \tx_datain[57]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y40_N1
+stratixiv_io_ibuf \tx_datain[58]~input (
+ .i(tx_datain[58]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[58]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[58]~input .bus_hold = "false";
+defparam \tx_datain[58]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y28_N94
+stratixiv_io_ibuf \tx_datain[59]~input (
+ .i(tx_datain[59]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[59]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[59]~input .bus_hold = "false";
+defparam \tx_datain[59]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: TXPMA_X0_Y15_N138
+stratixiv_hssi_tx_pma \pma_direct|auto_generated|transmit_pma2 (
+ .dpriodisable(\pma_direct|auto_generated|edge_cmu_dpriodisableout [0]),
+ .txpmareset(\pma_direct|auto_generated|tx_pll_cent_unit0~TXANALOGRESETOUT2 ),
+ .powerdn(\pma_direct|auto_generated|tx_pll_cent_unit0~TXOBPOWERDN2 ),
+ .forceelecidle(gnd),
+ .rxdetecten(gnd),
+ .detectrxpowerdown(\pma_direct|auto_generated|tx_pll_cent_unit0~TXDETECTRXPOWERDN2 ),
+ .rxdetectclk(gnd),
+ .refclk0inpulse(gnd),
+ .refclk1inpulse(gnd),
+ .refclk2inpulse(\pma_direct|auto_generated|edge_pll_analogrefclkpulse [0]),
+ .refclk3inpulse(gnd),
+ .refclk4inpulse(gnd),
+ .revserialfdbk(gnd),
+ .dprioin({\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT899 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT898 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT897 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT896 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT895 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT894 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT893 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT892 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT891 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT890 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT889 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT888 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT887 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT886 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT885 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT884 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT883 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT882 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT881 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT880 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT879 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT878 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT877 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT876 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT875 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT874 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT873 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT872 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT871 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT870 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT869 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT868 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT867 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT866 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT865 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT864 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT863 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT862 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT861 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT860 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT859 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT858 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT857 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT856 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT855 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT854 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT853 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT852 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT851 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT850 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT849 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT848 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT847 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT846 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT845 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT844 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT843 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT842 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT841 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT840 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT839 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT838 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT837 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT836 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT835 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT834 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT833 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT832 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT831 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT830 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT829 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT828 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT827 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT826 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT825 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT824 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT823 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT822 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT821 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT820 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT819 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT818 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT817 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT816 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT815 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT814 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT813 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT812 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT811 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT810 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT809 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT808 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT807 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT806 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT805 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT804 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT803 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT802 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT801 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT800 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT799 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT798 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT797 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT796 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT795 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT794 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT793 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT792 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT791 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT790 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT789 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT788 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT787 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT786 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT785 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT784 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT783 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT782 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT781 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT780 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT779 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT778 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT777 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT776 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT775 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT774 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT773 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT772 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT771 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT770 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT769 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT768 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT767 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT766 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT765 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT764 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT763 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT762 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT761 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT760 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT759 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT758 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT757 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT756 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT755 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT754 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT753 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT752 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT751 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT750 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT749 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT748 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT747 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT746 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT745 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT744 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT743 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT742 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT741 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT740 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT739 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT738 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT737 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT736 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT735 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT734 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT733 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT732 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT731 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT730 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT729 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT728 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT727 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT726 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT725 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT724 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT723 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT722 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT721 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT720 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT719 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT718 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT717 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT716 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT715 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT714 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT713 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT712 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT711 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT710 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT709 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT708 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT707 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT706 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT705 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT704 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT703 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT702 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT701 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT700 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT699 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT698 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT697 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT696 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT695 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT694 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT693 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT692 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT691 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT690 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT689 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT688 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT687 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT686 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT685 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT684 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT683 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT682 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT681 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT680 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT679 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT678 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT677 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT676 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT675 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT674 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT673 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT672 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT671 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT670 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT669 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT668 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT667 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT666 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT665 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT664 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT663 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT662 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT661 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT660 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT659 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT658 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT657 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT656 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT655 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT654 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT653 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT652 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT651 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT650 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT649 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT648 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT647 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT646 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT645 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT644 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT643 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT642 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT641 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT640 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT639 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT638 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT637 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT636 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT635 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT634 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT633 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT632 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT631 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT630 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT629 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT628 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT627 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT626 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT625 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT624 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT623 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT622 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT621 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT620 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT619 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT618 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT617 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT616 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT615 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT614 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT613 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT612 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT611 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT610 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT609 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT608 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT607 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT606 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT605 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT604 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT603 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT602 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT601 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT600 }),
+ .datain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\tx_datain[59]~input_o ,\tx_datain[58]~input_o ,\tx_datain[57]~input_o ,\tx_datain[56]~input_o ,\tx_datain[55]~input_o ,
+\tx_datain[54]~input_o ,\tx_datain[53]~input_o ,\tx_datain[52]~input_o ,\tx_datain[51]~input_o ,\tx_datain[50]~input_o ,\tx_datain[49]~input_o ,\tx_datain[48]~input_o ,\tx_datain[47]~input_o ,\tx_datain[46]~input_o ,\tx_datain[45]~input_o ,\tx_datain[44]~input_o ,
+\tx_datain[43]~input_o ,\tx_datain[42]~input_o ,\tx_datain[41]~input_o ,\tx_datain[40]~input_o }),
+ .refclk0in(2'b00),
+ .fastrefclk0in(2'b00),
+ .refclk1in(2'b00),
+ .fastrefclk1in(2'b00),
+ .refclk2in({\pma_direct|auto_generated|edge_pll_analogrefclkout [1],\pma_direct|auto_generated|edge_pll_analogrefclkout [0]}),
+ .fastrefclk2in({\pma_direct|auto_generated|edge_pll_analogfastrefclkout [1],\pma_direct|auto_generated|edge_pll_analogfastrefclkout [0]}),
+ .refclk3in(2'b00),
+ .fastrefclk3in(2'b00),
+ .refclk4in(2'b00),
+ .fastrefclk4in(2'b00),
+ .pclk({gnd,gnd,\pma_direct|auto_generated|refclk_pma_wire [0],gnd,gnd}),
+ .extra10gin(11'b00000000000),
+ .datainfull(20'b00000000000000000000),
+ .rxdetectvalidout(),
+ .rxfoundout(),
+ .dataout(\pma_direct|auto_generated|wire_transmit_pma2_dataout ),
+ .clockout(\pma_direct|auto_generated|wire_transmit_pma2_clockout ),
+ .seriallpbkout(),
+ .dprioout(\pma_direct|auto_generated|transmit_pma2_DPRIOOUT_bus ),
+ .dftout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|transmit_pma2 .analog_power = "1.4v";
+defparam \pma_direct|auto_generated|transmit_pma2 .channel_number = 2;
+defparam \pma_direct|auto_generated|transmit_pma2 .channel_type = "regular";
+defparam \pma_direct|auto_generated|transmit_pma2 .clkin_select = 2;
+defparam \pma_direct|auto_generated|transmit_pma2 .clkmux_delay = "false";
+defparam \pma_direct|auto_generated|transmit_pma2 .common_mode = "0.65v";
+defparam \pma_direct|auto_generated|transmit_pma2 .dprio_config_mode = 6'b000001;
+defparam \pma_direct|auto_generated|transmit_pma2 .enable_reverse_serial_loopback = "false";
+defparam \pma_direct|auto_generated|transmit_pma2 .logical_channel_address = 8;
+defparam \pma_direct|auto_generated|transmit_pma2 .logical_protocol_hint_0 = "basic";
+defparam \pma_direct|auto_generated|transmit_pma2 .logical_protocol_hint_1 = "basic";
+defparam \pma_direct|auto_generated|transmit_pma2 .logical_protocol_hint_2 = "basic";
+defparam \pma_direct|auto_generated|transmit_pma2 .logical_protocol_hint_3 = "basic";
+defparam \pma_direct|auto_generated|transmit_pma2 .low_speed_test_select = 0;
+defparam \pma_direct|auto_generated|transmit_pma2 .physical_clkin0_mapping = "none";
+defparam \pma_direct|auto_generated|transmit_pma2 .physical_clkin1_mapping = "none";
+defparam \pma_direct|auto_generated|transmit_pma2 .physical_clkin2_mapping = "x4";
+defparam \pma_direct|auto_generated|transmit_pma2 .physical_clkin3_mapping = "none";
+defparam \pma_direct|auto_generated|transmit_pma2 .physical_clkin4_mapping = "none";
+defparam \pma_direct|auto_generated|transmit_pma2 .preemp_pretap = 0;
+defparam \pma_direct|auto_generated|transmit_pma2 .preemp_pretap_inv = "false";
+defparam \pma_direct|auto_generated|transmit_pma2 .preemp_tap_1 = 5;
+defparam \pma_direct|auto_generated|transmit_pma2 .preemp_tap_1_a = 0;
+defparam \pma_direct|auto_generated|transmit_pma2 .preemp_tap_1_b = 0;
+defparam \pma_direct|auto_generated|transmit_pma2 .preemp_tap_1_c = 0;
+defparam \pma_direct|auto_generated|transmit_pma2 .preemp_tap_2 = 0;
+defparam \pma_direct|auto_generated|transmit_pma2 .preemp_tap_2_inv = "false";
+defparam \pma_direct|auto_generated|transmit_pma2 .protocol_hint = "basic";
+defparam \pma_direct|auto_generated|transmit_pma2 .rx_detect = 0;
+defparam \pma_direct|auto_generated|transmit_pma2 .serialization_factor = 20;
+defparam \pma_direct|auto_generated|transmit_pma2 .slew_rate = "low";
+defparam \pma_direct|auto_generated|transmit_pma2 .termination = "oct 100 ohms";
+defparam \pma_direct|auto_generated|transmit_pma2 .use_external_termination = "false";
+defparam \pma_direct|auto_generated|transmit_pma2 .use_pclk = "true";
+defparam \pma_direct|auto_generated|transmit_pma2 .use_pma_direct = "true";
+defparam \pma_direct|auto_generated|transmit_pma2 .use_rx_detect = "false";
+defparam \pma_direct|auto_generated|transmit_pma2 .use_ser_double_data_mode = "true";
+defparam \pma_direct|auto_generated|transmit_pma2 .vod_selection = 1;
+defparam \pma_direct|auto_generated|transmit_pma2 .vod_selection_a = 0;
+defparam \pma_direct|auto_generated|transmit_pma2 .vod_selection_b = 0;
+defparam \pma_direct|auto_generated|transmit_pma2 .vod_selection_c = 0;
+defparam \pma_direct|auto_generated|transmit_pma2 .vod_selection_d = 0;
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y45_N63
+stratixiv_io_ibuf \tx_datain[20]~input (
+ .i(tx_datain[20]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[20]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[20]~input .bus_hold = "false";
+defparam \tx_datain[20]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y50_N63
+stratixiv_io_ibuf \tx_datain[21]~input (
+ .i(tx_datain[21]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[21]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[21]~input .bus_hold = "false";
+defparam \tx_datain[21]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y48_N1
+stratixiv_io_ibuf \tx_datain[22]~input (
+ .i(tx_datain[22]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[22]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[22]~input .bus_hold = "false";
+defparam \tx_datain[22]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X19_Y0_N94
+stratixiv_io_ibuf \tx_datain[23]~input (
+ .i(tx_datain[23]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[23]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[23]~input .bus_hold = "false";
+defparam \tx_datain[23]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y18_N1
+stratixiv_io_ibuf \tx_datain[24]~input (
+ .i(tx_datain[24]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[24]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[24]~input .bus_hold = "false";
+defparam \tx_datain[24]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y18_N94
+stratixiv_io_ibuf \tx_datain[25]~input (
+ .i(tx_datain[25]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[25]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[25]~input .bus_hold = "false";
+defparam \tx_datain[25]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y44_N32
+stratixiv_io_ibuf \tx_datain[26]~input (
+ .i(tx_datain[26]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[26]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[26]~input .bus_hold = "false";
+defparam \tx_datain[26]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y56_N63
+stratixiv_io_ibuf \tx_datain[27]~input (
+ .i(tx_datain[27]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[27]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[27]~input .bus_hold = "false";
+defparam \tx_datain[27]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y54_N32
+stratixiv_io_ibuf \tx_datain[28]~input (
+ .i(tx_datain[28]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[28]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[28]~input .bus_hold = "false";
+defparam \tx_datain[28]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y54_N1
+stratixiv_io_ibuf \tx_datain[29]~input (
+ .i(tx_datain[29]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[29]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[29]~input .bus_hold = "false";
+defparam \tx_datain[29]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y48_N63
+stratixiv_io_ibuf \tx_datain[30]~input (
+ .i(tx_datain[30]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[30]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[30]~input .bus_hold = "false";
+defparam \tx_datain[30]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y13_N32
+stratixiv_io_ibuf \tx_datain[31]~input (
+ .i(tx_datain[31]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[31]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[31]~input .bus_hold = "false";
+defparam \tx_datain[31]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X19_Y0_N1
+stratixiv_io_ibuf \tx_datain[32]~input (
+ .i(tx_datain[32]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[32]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[32]~input .bus_hold = "false";
+defparam \tx_datain[32]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y33_N63
+stratixiv_io_ibuf \tx_datain[33]~input (
+ .i(tx_datain[33]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[33]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[33]~input .bus_hold = "false";
+defparam \tx_datain[33]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y45_N32
+stratixiv_io_ibuf \tx_datain[34]~input (
+ .i(tx_datain[34]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[34]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[34]~input .bus_hold = "false";
+defparam \tx_datain[34]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y47_N32
+stratixiv_io_ibuf \tx_datain[35]~input (
+ .i(tx_datain[35]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[35]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[35]~input .bus_hold = "false";
+defparam \tx_datain[35]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y16_N1
+stratixiv_io_ibuf \tx_datain[36]~input (
+ .i(tx_datain[36]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[36]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[36]~input .bus_hold = "false";
+defparam \tx_datain[36]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y13_N1
+stratixiv_io_ibuf \tx_datain[37]~input (
+ .i(tx_datain[37]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[37]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[37]~input .bus_hold = "false";
+defparam \tx_datain[37]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X19_Y0_N32
+stratixiv_io_ibuf \tx_datain[38]~input (
+ .i(tx_datain[38]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[38]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[38]~input .bus_hold = "false";
+defparam \tx_datain[38]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y33_N94
+stratixiv_io_ibuf \tx_datain[39]~input (
+ .i(tx_datain[39]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[39]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[39]~input .bus_hold = "false";
+defparam \tx_datain[39]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: TXPMA_X0_Y6_N138
+stratixiv_hssi_tx_pma \pma_direct|auto_generated|transmit_pma1 (
+ .dpriodisable(\pma_direct|auto_generated|edge_cmu_dpriodisableout [0]),
+ .txpmareset(\pma_direct|auto_generated|tx_pll_cent_unit0~TXANALOGRESETOUT1 ),
+ .powerdn(\pma_direct|auto_generated|tx_pll_cent_unit0~TXOBPOWERDN1 ),
+ .forceelecidle(gnd),
+ .rxdetecten(gnd),
+ .detectrxpowerdown(\pma_direct|auto_generated|tx_pll_cent_unit0~TXDETECTRXPOWERDN1 ),
+ .rxdetectclk(gnd),
+ .refclk0inpulse(gnd),
+ .refclk1inpulse(gnd),
+ .refclk2inpulse(\pma_direct|auto_generated|edge_pll_analogrefclkpulse [0]),
+ .refclk3inpulse(gnd),
+ .refclk4inpulse(gnd),
+ .revserialfdbk(gnd),
+ .dprioin({\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT599 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT598 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT597 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT596 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT595 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT594 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT593 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT592 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT591 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT590 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT589 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT588 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT587 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT586 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT585 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT584 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT583 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT582 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT581 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT580 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT579 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT578 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT577 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT576 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT575 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT574 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT573 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT572 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT571 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT570 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT569 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT568 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT567 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT566 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT565 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT564 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT563 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT562 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT561 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT560 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT559 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT558 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT557 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT556 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT555 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT554 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT553 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT552 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT551 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT550 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT549 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT548 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT547 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT546 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT545 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT544 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT543 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT542 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT541 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT540 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT539 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT538 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT537 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT536 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT535 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT534 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT533 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT532 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT531 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT530 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT529 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT528 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT527 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT526 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT525 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT524 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT523 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT522 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT521 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT520 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT519 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT518 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT517 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT516 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT515 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT514 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT513 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT512 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT511 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT510 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT509 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT508 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT507 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT506 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT505 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT504 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT503 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT502 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT501 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT500 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT499 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT498 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT497 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT496 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT495 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT494 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT493 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT492 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT491 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT490 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT489 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT488 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT487 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT486 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT485 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT484 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT483 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT482 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT481 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT480 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT479 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT478 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT477 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT476 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT475 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT474 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT473 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT472 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT471 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT470 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT469 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT468 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT467 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT466 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT465 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT464 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT463 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT462 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT461 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT460 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT459 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT458 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT457 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT456 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT455 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT454 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT453 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT452 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT451 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT450 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT449 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT448 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT447 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT446 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT445 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT444 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT443 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT442 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT441 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT440 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT439 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT438 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT437 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT436 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT435 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT434 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT433 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT432 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT431 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT430 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT429 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT428 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT427 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT426 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT425 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT424 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT423 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT422 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT421 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT420 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT419 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT418 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT417 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT416 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT415 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT414 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT413 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT412 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT411 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT410 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT409 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT408 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT407 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT406 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT405 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT404 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT403 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT402 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT401 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT400 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT399 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT398 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT397 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT396 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT395 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT394 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT393 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT392 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT391 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT390 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT389 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT388 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT387 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT386 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT385 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT384 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT383 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT382 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT381 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT380 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT379 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT378 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT377 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT376 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT375 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT374 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT373 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT372 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT371 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT370 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT369 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT368 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT367 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT366 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT365 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT364 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT363 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT362 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT361 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT360 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT359 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT358 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT357 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT356 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT355 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT354 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT353 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT352 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT351 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT350 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT349 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT348 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT347 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT346 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT345 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT344 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT343 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT342 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT341 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT340 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT339 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT338 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT337 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT336 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT335 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT334 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT333 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT332 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT331 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT330 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT329 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT328 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT327 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT326 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT325 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT324 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT323 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT322 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT321 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT320 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT319 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT318 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT317 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT316 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT315 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT314 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT313 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT312 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT311 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT310 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT309 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT308 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT307 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT306 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT305 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT304 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT303 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT302 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT301 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT300 }),
+ .datain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\tx_datain[39]~input_o ,\tx_datain[38]~input_o ,\tx_datain[37]~input_o ,\tx_datain[36]~input_o ,\tx_datain[35]~input_o ,
+\tx_datain[34]~input_o ,\tx_datain[33]~input_o ,\tx_datain[32]~input_o ,\tx_datain[31]~input_o ,\tx_datain[30]~input_o ,\tx_datain[29]~input_o ,\tx_datain[28]~input_o ,\tx_datain[27]~input_o ,\tx_datain[26]~input_o ,\tx_datain[25]~input_o ,\tx_datain[24]~input_o ,
+\tx_datain[23]~input_o ,\tx_datain[22]~input_o ,\tx_datain[21]~input_o ,\tx_datain[20]~input_o }),
+ .refclk0in(2'b00),
+ .fastrefclk0in(2'b00),
+ .refclk1in(2'b00),
+ .fastrefclk1in(2'b00),
+ .refclk2in({\pma_direct|auto_generated|edge_pll_analogrefclkout [1],\pma_direct|auto_generated|edge_pll_analogrefclkout [0]}),
+ .fastrefclk2in({\pma_direct|auto_generated|edge_pll_analogfastrefclkout [1],\pma_direct|auto_generated|edge_pll_analogfastrefclkout [0]}),
+ .refclk3in(2'b00),
+ .fastrefclk3in(2'b00),
+ .refclk4in(2'b00),
+ .fastrefclk4in(2'b00),
+ .pclk({gnd,gnd,\pma_direct|auto_generated|refclk_pma_wire [0],gnd,gnd}),
+ .extra10gin(11'b00000000000),
+ .datainfull(20'b00000000000000000000),
+ .rxdetectvalidout(),
+ .rxfoundout(),
+ .dataout(\pma_direct|auto_generated|wire_transmit_pma1_dataout ),
+ .clockout(\pma_direct|auto_generated|wire_transmit_pma1_clockout ),
+ .seriallpbkout(),
+ .dprioout(\pma_direct|auto_generated|transmit_pma1_DPRIOOUT_bus ),
+ .dftout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|transmit_pma1 .analog_power = "1.4v";
+defparam \pma_direct|auto_generated|transmit_pma1 .channel_number = 1;
+defparam \pma_direct|auto_generated|transmit_pma1 .channel_type = "regular";
+defparam \pma_direct|auto_generated|transmit_pma1 .clkin_select = 2;
+defparam \pma_direct|auto_generated|transmit_pma1 .clkmux_delay = "false";
+defparam \pma_direct|auto_generated|transmit_pma1 .common_mode = "0.65v";
+defparam \pma_direct|auto_generated|transmit_pma1 .dprio_config_mode = 6'b000001;
+defparam \pma_direct|auto_generated|transmit_pma1 .enable_reverse_serial_loopback = "false";
+defparam \pma_direct|auto_generated|transmit_pma1 .logical_channel_address = 4;
+defparam \pma_direct|auto_generated|transmit_pma1 .logical_protocol_hint_0 = "basic";
+defparam \pma_direct|auto_generated|transmit_pma1 .logical_protocol_hint_1 = "basic";
+defparam \pma_direct|auto_generated|transmit_pma1 .logical_protocol_hint_2 = "basic";
+defparam \pma_direct|auto_generated|transmit_pma1 .logical_protocol_hint_3 = "basic";
+defparam \pma_direct|auto_generated|transmit_pma1 .low_speed_test_select = 0;
+defparam \pma_direct|auto_generated|transmit_pma1 .physical_clkin0_mapping = "none";
+defparam \pma_direct|auto_generated|transmit_pma1 .physical_clkin1_mapping = "none";
+defparam \pma_direct|auto_generated|transmit_pma1 .physical_clkin2_mapping = "x4";
+defparam \pma_direct|auto_generated|transmit_pma1 .physical_clkin3_mapping = "none";
+defparam \pma_direct|auto_generated|transmit_pma1 .physical_clkin4_mapping = "none";
+defparam \pma_direct|auto_generated|transmit_pma1 .preemp_pretap = 0;
+defparam \pma_direct|auto_generated|transmit_pma1 .preemp_pretap_inv = "false";
+defparam \pma_direct|auto_generated|transmit_pma1 .preemp_tap_1 = 5;
+defparam \pma_direct|auto_generated|transmit_pma1 .preemp_tap_1_a = 0;
+defparam \pma_direct|auto_generated|transmit_pma1 .preemp_tap_1_b = 0;
+defparam \pma_direct|auto_generated|transmit_pma1 .preemp_tap_1_c = 0;
+defparam \pma_direct|auto_generated|transmit_pma1 .preemp_tap_2 = 0;
+defparam \pma_direct|auto_generated|transmit_pma1 .preemp_tap_2_inv = "false";
+defparam \pma_direct|auto_generated|transmit_pma1 .protocol_hint = "basic";
+defparam \pma_direct|auto_generated|transmit_pma1 .rx_detect = 0;
+defparam \pma_direct|auto_generated|transmit_pma1 .serialization_factor = 20;
+defparam \pma_direct|auto_generated|transmit_pma1 .slew_rate = "low";
+defparam \pma_direct|auto_generated|transmit_pma1 .termination = "oct 100 ohms";
+defparam \pma_direct|auto_generated|transmit_pma1 .use_external_termination = "false";
+defparam \pma_direct|auto_generated|transmit_pma1 .use_pclk = "true";
+defparam \pma_direct|auto_generated|transmit_pma1 .use_pma_direct = "true";
+defparam \pma_direct|auto_generated|transmit_pma1 .use_rx_detect = "false";
+defparam \pma_direct|auto_generated|transmit_pma1 .use_ser_double_data_mode = "true";
+defparam \pma_direct|auto_generated|transmit_pma1 .vod_selection = 1;
+defparam \pma_direct|auto_generated|transmit_pma1 .vod_selection_a = 0;
+defparam \pma_direct|auto_generated|transmit_pma1 .vod_selection_b = 0;
+defparam \pma_direct|auto_generated|transmit_pma1 .vod_selection_c = 0;
+defparam \pma_direct|auto_generated|transmit_pma1 .vod_selection_d = 0;
+// synopsys translate_on
+
+// Location: IOIBUF_X57_Y0_N32
+stratixiv_io_ibuf \tx_datain[0]~input (
+ .i(tx_datain[0]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[0]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[0]~input .bus_hold = "false";
+defparam \tx_datain[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X64_Y0_N32
+stratixiv_io_ibuf \tx_datain[1]~input (
+ .i(tx_datain[1]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[1]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[1]~input .bus_hold = "false";
+defparam \tx_datain[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X39_Y0_N1
+stratixiv_io_ibuf \tx_datain[2]~input (
+ .i(tx_datain[2]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[2]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[2]~input .bus_hold = "false";
+defparam \tx_datain[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X59_Y0_N32
+stratixiv_io_ibuf \tx_datain[3]~input (
+ .i(tx_datain[3]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[3]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[3]~input .bus_hold = "false";
+defparam \tx_datain[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X57_Y0_N94
+stratixiv_io_ibuf \tx_datain[4]~input (
+ .i(tx_datain[4]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[4]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[4]~input .bus_hold = "false";
+defparam \tx_datain[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X60_Y0_N63
+stratixiv_io_ibuf \tx_datain[5]~input (
+ .i(tx_datain[5]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[5]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[5]~input .bus_hold = "false";
+defparam \tx_datain[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X54_Y0_N94
+stratixiv_io_ibuf \tx_datain[6]~input (
+ .i(tx_datain[6]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[6]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[6]~input .bus_hold = "false";
+defparam \tx_datain[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X60_Y0_N1
+stratixiv_io_ibuf \tx_datain[7]~input (
+ .i(tx_datain[7]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[7]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[7]~input .bus_hold = "false";
+defparam \tx_datain[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X70_Y0_N1
+stratixiv_io_ibuf \tx_datain[8]~input (
+ .i(tx_datain[8]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[8]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[8]~input .bus_hold = "false";
+defparam \tx_datain[8]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X47_Y0_N32
+stratixiv_io_ibuf \tx_datain[9]~input (
+ .i(tx_datain[9]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[9]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[9]~input .bus_hold = "false";
+defparam \tx_datain[9]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X59_Y0_N1
+stratixiv_io_ibuf \tx_datain[10]~input (
+ .i(tx_datain[10]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[10]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[10]~input .bus_hold = "false";
+defparam \tx_datain[10]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X27_Y0_N32
+stratixiv_io_ibuf \tx_datain[11]~input (
+ .i(tx_datain[11]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[11]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[11]~input .bus_hold = "false";
+defparam \tx_datain[11]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X60_Y0_N94
+stratixiv_io_ibuf \tx_datain[12]~input (
+ .i(tx_datain[12]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[12]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[12]~input .bus_hold = "false";
+defparam \tx_datain[12]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X22_Y0_N63
+stratixiv_io_ibuf \tx_datain[13]~input (
+ .i(tx_datain[13]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[13]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[13]~input .bus_hold = "false";
+defparam \tx_datain[13]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X47_Y0_N94
+stratixiv_io_ibuf \tx_datain[14]~input (
+ .i(tx_datain[14]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[14]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[14]~input .bus_hold = "false";
+defparam \tx_datain[14]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X59_Y0_N63
+stratixiv_io_ibuf \tx_datain[15]~input (
+ .i(tx_datain[15]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[15]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[15]~input .bus_hold = "false";
+defparam \tx_datain[15]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X42_Y0_N32
+stratixiv_io_ibuf \tx_datain[16]~input (
+ .i(tx_datain[16]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[16]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[16]~input .bus_hold = "false";
+defparam \tx_datain[16]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X38_Y0_N94
+stratixiv_io_ibuf \tx_datain[17]~input (
+ .i(tx_datain[17]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[17]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[17]~input .bus_hold = "false";
+defparam \tx_datain[17]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X50_Y0_N94
+stratixiv_io_ibuf \tx_datain[18]~input (
+ .i(tx_datain[18]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[18]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[18]~input .bus_hold = "false";
+defparam \tx_datain[18]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X27_Y0_N63
+stratixiv_io_ibuf \tx_datain[19]~input (
+ .i(tx_datain[19]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_datain[19]~input_o ));
+// synopsys translate_off
+defparam \tx_datain[19]~input .bus_hold = "false";
+defparam \tx_datain[19]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: TXPMA_X0_Y3_N138
+stratixiv_hssi_tx_pma \pma_direct|auto_generated|transmit_pma0 (
+ .dpriodisable(\pma_direct|auto_generated|edge_cmu_dpriodisableout [0]),
+ .txpmareset(\pma_direct|auto_generated|tx_pll_cent_unit0~TXANALOGRESETOUT0 ),
+ .powerdn(\pma_direct|auto_generated|tx_pll_cent_unit0~TXOBPOWERDN0 ),
+ .forceelecidle(gnd),
+ .rxdetecten(gnd),
+ .detectrxpowerdown(\pma_direct|auto_generated|tx_pll_cent_unit0~TXDETECTRXPOWERDN0 ),
+ .rxdetectclk(gnd),
+ .refclk0inpulse(gnd),
+ .refclk1inpulse(gnd),
+ .refclk2inpulse(\pma_direct|auto_generated|edge_pll_analogrefclkpulse [0]),
+ .refclk3inpulse(gnd),
+ .refclk4inpulse(gnd),
+ .revserialfdbk(gnd),
+ .dprioin({\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT299 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT298 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT297 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT296 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT295 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT294 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT293 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT292 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT291 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT290 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT289 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT288 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT287 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT286 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT285 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT284 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT283 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT282 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT281 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT280 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT279 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT278 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT277 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT276 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT275 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT274 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT273 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT272 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT271 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT270 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT269 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT268 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT267 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT266 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT265 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT264 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT263 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT262 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT261 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT260 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT259 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT258 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT257 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT256 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT255 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT254 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT253 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT252 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT251 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT250 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT249 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT248 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT247 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT246 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT245 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT244 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT243 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT242 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT241 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT240 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT239 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT238 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT237 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT236 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT235 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT234 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT233 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT232 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT231 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT230 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT229 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT228 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT227 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT226 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT225 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT224 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT223 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT222 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT221 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT220 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT219 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT218 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT217 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT216 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT215 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT214 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT213 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT212 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT211 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT210 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT209 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT208 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT207 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT206 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT205 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT204 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT203 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT202 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT201 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT200 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT199 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT198 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT197 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT196 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT195 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT194 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT193 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT192 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT191 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT190 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT189 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT188 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT187 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT186 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT185 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT184 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT183 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT182 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT181 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT180 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT179 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT178 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT177 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT176 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT175 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT174 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT173 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT172 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT171 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT170 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT169 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT168 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT167 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT166 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT165 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT164 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT163 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT162 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT161 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT160 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT159 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT158 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT157 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT156 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT155 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT154 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT153 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT152 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT151 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT150 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT149 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT148 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT147 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT146 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT145 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT144 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT143 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT142 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT141 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT140 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT139 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT138 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT137 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT136 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT135 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT134 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT133 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT132 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT131 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT130 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT129 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT128 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT127 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT126 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT125 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT124 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT123 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT122 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT121 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT120 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT119 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT118 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT117 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT116 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT115 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT114 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT113 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT112 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT111 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT110 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT109 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT108 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT107 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT106 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT105 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT104 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT103 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT102 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT101 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT100 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT99 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT98 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT97 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT96 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT95 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT94 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT93 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT92 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT91 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT90 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT89 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT88 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT87 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT86 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT85 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT84 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT83 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT82 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT81 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT80 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT79 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT78 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT77 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT76 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT75 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT74 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT73 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT72 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT71 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT70 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT69 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT68 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT67 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT66 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT65 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT64 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT63 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT62 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT61 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT60 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT59 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT58 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT57 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT56 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT55 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT54 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT53 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT52 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT51 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT50 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT49 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT48 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT47 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT46 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT45 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT44 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT43 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT42 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT41 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT40 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT39 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT38 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT37 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT36 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT35 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT34 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT33 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT32 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT31 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT30 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT29 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT28 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT27 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT26 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT25 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT24 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT23 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT22 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT21 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT20 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT19 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT18 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT17 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT16 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT15 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT14 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT13 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT12 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT11 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT10 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT9 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT8 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT7 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT6 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT5 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT4 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT3 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT2 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT1 ,\pma_direct|auto_generated|tx_pll_cent_unit0~TXPMADPRIOOUT0 }),
+ .datain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\tx_datain[19]~input_o ,\tx_datain[18]~input_o ,\tx_datain[17]~input_o ,\tx_datain[16]~input_o ,\tx_datain[15]~input_o ,
+\tx_datain[14]~input_o ,\tx_datain[13]~input_o ,\tx_datain[12]~input_o ,\tx_datain[11]~input_o ,\tx_datain[10]~input_o ,\tx_datain[9]~input_o ,\tx_datain[8]~input_o ,\tx_datain[7]~input_o ,\tx_datain[6]~input_o ,\tx_datain[5]~input_o ,\tx_datain[4]~input_o ,
+\tx_datain[3]~input_o ,\tx_datain[2]~input_o ,\tx_datain[1]~input_o ,\tx_datain[0]~input_o }),
+ .refclk0in(2'b00),
+ .fastrefclk0in(2'b00),
+ .refclk1in(2'b00),
+ .fastrefclk1in(2'b00),
+ .refclk2in({\pma_direct|auto_generated|edge_pll_analogrefclkout [1],\pma_direct|auto_generated|edge_pll_analogrefclkout [0]}),
+ .fastrefclk2in({\pma_direct|auto_generated|edge_pll_analogfastrefclkout [1],\pma_direct|auto_generated|edge_pll_analogfastrefclkout [0]}),
+ .refclk3in(2'b00),
+ .fastrefclk3in(2'b00),
+ .refclk4in(2'b00),
+ .fastrefclk4in(2'b00),
+ .pclk({gnd,gnd,\pma_direct|auto_generated|refclk_pma_wire [0],gnd,gnd}),
+ .extra10gin(11'b00000000000),
+ .datainfull(20'b00000000000000000000),
+ .rxdetectvalidout(),
+ .rxfoundout(),
+ .dataout(\pma_direct|auto_generated|wire_transmit_pma0_dataout ),
+ .clockout(\pma_direct|auto_generated|wire_transmit_pma0_clockout ),
+ .seriallpbkout(),
+ .dprioout(\pma_direct|auto_generated|transmit_pma0_DPRIOOUT_bus ),
+ .dftout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|transmit_pma0 .analog_power = "1.4v";
+defparam \pma_direct|auto_generated|transmit_pma0 .channel_number = 0;
+defparam \pma_direct|auto_generated|transmit_pma0 .channel_type = "regular";
+defparam \pma_direct|auto_generated|transmit_pma0 .clkin_select = 2;
+defparam \pma_direct|auto_generated|transmit_pma0 .clkmux_delay = "false";
+defparam \pma_direct|auto_generated|transmit_pma0 .common_mode = "0.65v";
+defparam \pma_direct|auto_generated|transmit_pma0 .dprio_config_mode = 6'b000001;
+defparam \pma_direct|auto_generated|transmit_pma0 .enable_reverse_serial_loopback = "false";
+defparam \pma_direct|auto_generated|transmit_pma0 .logical_channel_address = 0;
+defparam \pma_direct|auto_generated|transmit_pma0 .logical_protocol_hint_0 = "basic";
+defparam \pma_direct|auto_generated|transmit_pma0 .logical_protocol_hint_1 = "basic";
+defparam \pma_direct|auto_generated|transmit_pma0 .logical_protocol_hint_2 = "basic";
+defparam \pma_direct|auto_generated|transmit_pma0 .logical_protocol_hint_3 = "basic";
+defparam \pma_direct|auto_generated|transmit_pma0 .low_speed_test_select = 0;
+defparam \pma_direct|auto_generated|transmit_pma0 .physical_clkin0_mapping = "none";
+defparam \pma_direct|auto_generated|transmit_pma0 .physical_clkin1_mapping = "none";
+defparam \pma_direct|auto_generated|transmit_pma0 .physical_clkin2_mapping = "x4";
+defparam \pma_direct|auto_generated|transmit_pma0 .physical_clkin3_mapping = "none";
+defparam \pma_direct|auto_generated|transmit_pma0 .physical_clkin4_mapping = "none";
+defparam \pma_direct|auto_generated|transmit_pma0 .preemp_pretap = 0;
+defparam \pma_direct|auto_generated|transmit_pma0 .preemp_pretap_inv = "false";
+defparam \pma_direct|auto_generated|transmit_pma0 .preemp_tap_1 = 5;
+defparam \pma_direct|auto_generated|transmit_pma0 .preemp_tap_1_a = 0;
+defparam \pma_direct|auto_generated|transmit_pma0 .preemp_tap_1_b = 0;
+defparam \pma_direct|auto_generated|transmit_pma0 .preemp_tap_1_c = 0;
+defparam \pma_direct|auto_generated|transmit_pma0 .preemp_tap_2 = 0;
+defparam \pma_direct|auto_generated|transmit_pma0 .preemp_tap_2_inv = "false";
+defparam \pma_direct|auto_generated|transmit_pma0 .protocol_hint = "basic";
+defparam \pma_direct|auto_generated|transmit_pma0 .rx_detect = 0;
+defparam \pma_direct|auto_generated|transmit_pma0 .serialization_factor = 20;
+defparam \pma_direct|auto_generated|transmit_pma0 .slew_rate = "low";
+defparam \pma_direct|auto_generated|transmit_pma0 .termination = "oct 100 ohms";
+defparam \pma_direct|auto_generated|transmit_pma0 .use_external_termination = "false";
+defparam \pma_direct|auto_generated|transmit_pma0 .use_pclk = "true";
+defparam \pma_direct|auto_generated|transmit_pma0 .use_pma_direct = "true";
+defparam \pma_direct|auto_generated|transmit_pma0 .use_rx_detect = "false";
+defparam \pma_direct|auto_generated|transmit_pma0 .use_ser_double_data_mode = "true";
+defparam \pma_direct|auto_generated|transmit_pma0 .vod_selection = 1;
+defparam \pma_direct|auto_generated|transmit_pma0 .vod_selection_a = 0;
+defparam \pma_direct|auto_generated|transmit_pma0 .vod_selection_b = 0;
+defparam \pma_direct|auto_generated|transmit_pma0 .vod_selection_c = 0;
+defparam \pma_direct|auto_generated|transmit_pma0 .vod_selection_d = 0;
+// synopsys translate_on
+
+// Location: HSSIPLL_X0_Y18_N135
+stratixiv_hssi_pll \pma_direct|auto_generated|rx_cdr_pll3 (
+ .rateswitch(gnd),
+ .locktorefclk(\pma_direct|auto_generated|rx_pma_locktorefout [3]),
+ .datain(\pma_direct|auto_generated|rx_pma_dataout [3]),
+ .powerdown(\pma_direct|auto_generated|tx_pll_cent_unit0~RXCRUPOWERDN3 ),
+ .areset(\pma_direct|auto_generated|tx_pll_cent_unit0~RXCRURESETOUT3 ),
+ .dpriodisable(\pma_direct|auto_generated|edge_cmu_dpriodisableout [0]),
+ .earlyeios(gnd),
+ .pfdfbclk(gnd),
+ .inclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\pll_inclk[0]~inputclkctrl_outclk }),
+ .dprioin({\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1199],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1198],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1197],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1196],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1195],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1194],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1193],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1192],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1191],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1190],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1189],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1188],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1187],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1186],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1185],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1184],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1183],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1182],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1181],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1180],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1179],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1178],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1177],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1176],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1175],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1174],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1173],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1172],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1171],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1170],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1169],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1168],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1167],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1166],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1165],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1164],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1163],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1162],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1161],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1160],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1159],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1158],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1157],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1156],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1155],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1154],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1153],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1152],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1151],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1150],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1149],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1148],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1147],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1146],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1145],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1144],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1143],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1142],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1141],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1140],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1139],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1138],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1137],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1136],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1135],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1134],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1133],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1132],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1131],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1130],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1129],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1128],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1127],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1126],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1125],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1124],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1123],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1122],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1121],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1120],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1119],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1118],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1117],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1116],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1115],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1114],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1113],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1112],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1111],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1110],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1109],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1108],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1107],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1106],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1105],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1104],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1103],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1102],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1101],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1100],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1099],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1098],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1097],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1096],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1095],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1094],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1093],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1092],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1091],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1090],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1089],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1088],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1087],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1086],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1085],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1084],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1083],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1082],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1081],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1080],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1079],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1078],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1077],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1076],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1075],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1074],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1073],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1072],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1071],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1070],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1069],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1068],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1067],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1066],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1065],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1064],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1063],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1062],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1061],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1060],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1059],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1058],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1057],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1056],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1055],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1054],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1053],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1052],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1051],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1050],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1049],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1048],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1047],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1046],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1045],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1044],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1043],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1042],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1041],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1040],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1039],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1038],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1037],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1036],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1035],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1034],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1033],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1032],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1031],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1030],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1029],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1028],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1027],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1026],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1025],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1024],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1023],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1022],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1021],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1020],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1019],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1018],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1017],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1016],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1015],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1014],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1013],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1012],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1011],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1010],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1009],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1008],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1007],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1006],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1005],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1004],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1003],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1002],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1001],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1000],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [999],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [998],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [997],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [996],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [995],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [994],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [993],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [992],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [991],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [990],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [989],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [988],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [987],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [986],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [985],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [984],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [983],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [982],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [981],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [980],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [979],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [978],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [977],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [976],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [975],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [974],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [973],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [972],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [971],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [970],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [969],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [968],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [967],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [966],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [965],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [964],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [963],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [962],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [961],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [960],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [959],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [958],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [957],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [956],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [955],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [954],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [953],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [952],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [951],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [950],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [949],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [948],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [947],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [946],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [945],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [944],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [943],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [942],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [941],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [940],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [939],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [938],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [937],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [936],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [935],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [934],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [933],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [932],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [931],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [930],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [929],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [928],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [927],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [926],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [925],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [924],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [923],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [922],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [921],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [920],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [919],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [918],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [917],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [916],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [915],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [914],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [913],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [912],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [911],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [910],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [909],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [908],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [907],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [906],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [905],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [904],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [903],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [902],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [901],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [900]}),
+ .extra10gin(6'b000000),
+ .pfdfbclkout(),
+ .pfdrefclkout(\pma_direct|auto_generated|rx_pll_pfdrefclkout_wire [3]),
+ .vcobypassout(),
+ .locked(\pma_direct|auto_generated|rx_plllocked_wire [3]),
+ .freqlocked(\pma_direct|auto_generated|wire_rx_cdr_pll3_freqlocked ),
+ .clk(\pma_direct|auto_generated|rx_cdr_pll3_CLK_bus ),
+ .dataout(\pma_direct|auto_generated|rx_cdr_pll3_DATAOUT_bus ),
+ .dprioout(\pma_direct|auto_generated|rx_cdr_pll3_DPRIOOUT_bus ));
+// synopsys translate_off
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .auto_settings = "true";
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .bandwidth_type = "high";
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .base_data_rate = "3125.0 mbps";
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .channel_num = 3;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .charge_pump_current_bits = 30;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .charge_pump_mode_bits = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .charge_pump_test_enable = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .dprio_config_mode = 6'b000000;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .effective_data_rate = "3125.0 mbps";
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .enable_dynamic_divider = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .fast_lock_control = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .inclk0_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .inclk1_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .inclk2_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .inclk3_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .inclk4_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .inclk5_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .inclk6_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .inclk7_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .inclk8_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .inclk9_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .input_clock_frequency = "156.25 mhz";
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .logical_channel_address = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .logical_tx_pll_number = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .loop_filter_c_bits = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .loop_filter_r_bits = 3200;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .m = 10;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .n = 1;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .pd_charge_pump_current_bits = 5;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .pd_loop_filter_r_bits = 300;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .pfd_clk_select = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .pfd_fb_select = "internal";
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .pll_type = "rx cdr";
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .sim_is_negative_ppm_drift = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .sim_net_ppm_variation = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .test_charge_pump_current_down = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .test_charge_pump_current_up = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .vco_data_rate = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .vco_post_scale = 2;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .vco_range = "high";
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .volt_reg_control_bits = 2;
+defparam \pma_direct|auto_generated|rx_cdr_pll3 .volt_reg_output_bits = 0;
+// synopsys translate_on
+
+// Location: RXPMA_X0_Y18_N137
+stratixiv_hssi_rx_pma \pma_direct|auto_generated|receive_pma3 (
+ .dpriodisable(\pma_direct|auto_generated|edge_cmu_dpriodisableout [0]),
+ .offsetcancellationen(gnd),
+ .powerdn(\pma_direct|auto_generated|tx_pll_cent_unit0~RXIBPOWERDN3 ),
+ .rxpmareset(\pma_direct|auto_generated|tx_pll_cent_unit0~RXANALOGRESETOUT3 ),
+ .plllocked(\pma_direct|auto_generated|rx_plllocked_wire [3]),
+ .ppmdetectrefclk(\pma_direct|auto_generated|rx_pll_pfdrefclkout_wire [3]),
+ .ppmdetectdividedclk(gnd),
+ .locktodata(\pma_direct|auto_generated|rx_locktodata_wire [3]),
+ .locktoref(\pma_direct|auto_generated|comb~3_combout ),
+ .freqlock(gnd),
+ .ignorephslck(gnd),
+ .datain(\rx_datain[3]~input_o ),
+ .seriallpbken(gnd),
+ .seriallpbkin(gnd),
+ .adcepowerdn(gnd),
+ .adcereset(gnd),
+ .adaptcapture(gnd),
+ .adcestandby(gnd),
+ .dprioin({\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1199 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1198 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1197 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1196 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1195 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1194 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1193 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1192 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1191 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1190 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1189 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1188 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1187 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1186 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1185 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1184 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1183 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1182 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1181 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1180 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1179 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1178 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1177 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1176 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1175 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1174 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1173 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1172 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1171 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1170 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1169 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1168 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1167 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1166 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1165 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1164 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1163 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1162 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1161 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1160 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1159 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1158 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1157 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1156 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1155 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1154 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1153 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1152 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1151 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1150 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1149 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1148 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1147 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1146 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1145 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1144 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1143 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1142 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1141 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1140 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1139 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1138 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1137 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1136 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1135 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1134 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1133 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1132 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1131 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1130 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1129 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1128 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1127 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1126 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1125 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1124 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1123 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1122 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1121 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1120 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1119 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1118 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1117 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1116 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1115 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1114 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1113 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1112 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1111 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1110 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1109 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1108 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1107 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1106 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1105 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1104 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1103 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1102 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1101 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1100 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1099 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1098 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1097 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1096 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1095 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1094 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1093 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1092 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1091 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1090 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1089 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1088 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1087 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1086 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1085 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1084 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1083 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1082 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1081 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1080 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1079 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1078 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1077 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1076 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1075 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1074 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1073 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1072 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1071 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1070 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1069 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1068 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1067 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1066 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1065 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1064 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1063 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1062 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1061 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1060 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1059 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1058 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1057 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1056 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1055 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1054 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1053 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1052 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1051 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1050 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1049 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1048 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1047 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1046 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1045 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1044 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1043 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1042 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1041 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1040 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1039 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1038 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1037 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1036 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1035 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1034 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1033 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1032 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1031 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1030 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1029 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1028 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1027 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1026 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1025 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1024 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1023 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1022 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1021 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1020 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1019 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1018 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1017 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1016 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1015 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1014 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1013 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1012 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1011 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1010 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1009 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1008 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1007 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1006 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1005 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1004 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1003 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1002 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1001 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1000 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT999 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT998 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT997 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT996 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT995 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT994 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT993 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT992 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT991 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT990 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT989 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT988 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT987 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT986 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT985 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT984 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT983 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT982 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT981 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT980 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT979 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT978 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT977 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT976 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT975 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT974 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT973 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT972 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT971 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT970 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT969 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT968 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT967 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT966 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT965 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT964 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT963 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT962 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT961 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT960 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT959 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT958 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT957 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT956 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT955 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT954 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT953 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT952 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT951 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT950 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT949 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT948 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT947 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT946 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT945 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT944 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT943 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT942 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT941 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT940 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT939 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT938 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT937 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT936 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT935 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT934 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT933 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT932 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT931 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT930 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT929 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT928 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT927 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT926 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT925 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT924 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT923 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT922 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT921 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT920 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT919 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT918 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT917 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT916 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT915 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT914 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT913 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT912 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT911 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT910 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT909 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT908 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT907 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT906 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT905 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT904 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT903 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT902 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT901 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT900 }),
+ .deserclock({\pma_direct|auto_generated|rx_deserclock_in [15],\pma_direct|auto_generated|rx_deserclock_in [14],\pma_direct|auto_generated|rx_deserclock_in [13],\pma_direct|auto_generated|rx_deserclock_in [12]}),
+ .recoverdatain({\pma_direct|auto_generated|pll_ch_dataout_wire [7],\pma_direct|auto_generated|pll_ch_dataout_wire [6]}),
+ .testbussel({gnd,vcc,vcc,gnd}),
+ .extra10gin(38'b00000000000000000000000000000000000000),
+ .signaldetect(),
+ .clockout(\pma_direct|auto_generated|wire_receive_pma3_clockout ),
+ .ppmdetectclkrel(),
+ .locktorefout(\pma_direct|auto_generated|rx_pma_locktorefout [3]),
+ .dataout(\pma_direct|auto_generated|rx_pma_dataout [3]),
+ .revserialfdbkout(),
+ .reverselpbkout(),
+ .adaptdone(),
+ .dprioout(\pma_direct|auto_generated|receive_pma3_DPRIOOUT_bus ),
+ .recoverdataout(\pma_direct|auto_generated|receive_pma3_RECOVERDATAOUT_bus ),
+ .analogtestbus(\pma_direct|auto_generated|receive_pma3_ANALOGTESTBUS_bus ),
+ .dataoutfull());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|receive_pma3 .adaptive_equalization_mode = "none";
+defparam \pma_direct|auto_generated|receive_pma3 .allow_serial_loopback = "false";
+defparam \pma_direct|auto_generated|receive_pma3 .allow_vco_bypass = 0;
+defparam \pma_direct|auto_generated|receive_pma3 .analog_power = "1.4v";
+defparam \pma_direct|auto_generated|receive_pma3 .channel_number = 3;
+defparam \pma_direct|auto_generated|receive_pma3 .channel_type = "regular";
+defparam \pma_direct|auto_generated|receive_pma3 .common_mode = "0.82v";
+defparam \pma_direct|auto_generated|receive_pma3 .deserialization_factor = 20;
+defparam \pma_direct|auto_generated|receive_pma3 .dfe_piclk_bandwidth = 5;
+defparam \pma_direct|auto_generated|receive_pma3 .dfe_piclk_phase = 16;
+defparam \pma_direct|auto_generated|receive_pma3 .dfe_piclk_sel = 8;
+defparam \pma_direct|auto_generated|receive_pma3 .dprio_config_mode = 6'b000001;
+defparam \pma_direct|auto_generated|receive_pma3 .enable_ltd = "true";
+defparam \pma_direct|auto_generated|receive_pma3 .enable_ltr = "true";
+defparam \pma_direct|auto_generated|receive_pma3 .eq_adapt_seq_control = 0;
+defparam \pma_direct|auto_generated|receive_pma3 .eq_dc_gain = 0;
+defparam \pma_direct|auto_generated|receive_pma3 .eq_max_gradient_control = 0;
+defparam \pma_direct|auto_generated|receive_pma3 .eqa_ctrl = 7;
+defparam \pma_direct|auto_generated|receive_pma3 .eqb_ctrl = 7;
+defparam \pma_direct|auto_generated|receive_pma3 .eqc_ctrl = 7;
+defparam \pma_direct|auto_generated|receive_pma3 .eqd_ctrl = 7;
+defparam \pma_direct|auto_generated|receive_pma3 .eqv_ctrl = 5;
+defparam \pma_direct|auto_generated|receive_pma3 .eyemon_bandwidth = 3;
+defparam \pma_direct|auto_generated|receive_pma3 .force_signal_detect = "true";
+defparam \pma_direct|auto_generated|receive_pma3 .ignore_lock_detect = "false";
+defparam \pma_direct|auto_generated|receive_pma3 .logical_channel_address = 12;
+defparam \pma_direct|auto_generated|receive_pma3 .low_speed_test_select = 0;
+defparam \pma_direct|auto_generated|receive_pma3 .offset_cancellation = 1;
+defparam \pma_direct|auto_generated|receive_pma3 .ppm_gen1_2_xcnt_en = 0;
+defparam \pma_direct|auto_generated|receive_pma3 .ppm_post_eidle = 0;
+defparam \pma_direct|auto_generated|receive_pma3 .ppmselect = 32;
+defparam \pma_direct|auto_generated|receive_pma3 .protocol_hint = "basic";
+defparam \pma_direct|auto_generated|receive_pma3 .send_direct_reverse_serial_loopback = "none";
+defparam \pma_direct|auto_generated|receive_pma3 .signal_detect_hysteresis = 2;
+defparam \pma_direct|auto_generated|receive_pma3 .signal_detect_hysteresis_valid_threshold = 14;
+defparam \pma_direct|auto_generated|receive_pma3 .signal_detect_loss_threshold = 9;
+defparam \pma_direct|auto_generated|receive_pma3 .termination = "oct 100 ohms";
+defparam \pma_direct|auto_generated|receive_pma3 .use_deser_double_data_width = "true";
+defparam \pma_direct|auto_generated|receive_pma3 .use_external_termination = "false";
+defparam \pma_direct|auto_generated|receive_pma3 .use_pma_direct = "true";
+// synopsys translate_on
+
+// Location: HSSIPLL_X0_Y15_N135
+stratixiv_hssi_pll \pma_direct|auto_generated|rx_cdr_pll2 (
+ .rateswitch(gnd),
+ .locktorefclk(\pma_direct|auto_generated|rx_pma_locktorefout [2]),
+ .datain(\pma_direct|auto_generated|rx_pma_dataout [2]),
+ .powerdown(\pma_direct|auto_generated|tx_pll_cent_unit0~RXCRUPOWERDN2 ),
+ .areset(\pma_direct|auto_generated|tx_pll_cent_unit0~RXCRURESETOUT2 ),
+ .dpriodisable(\pma_direct|auto_generated|edge_cmu_dpriodisableout [0]),
+ .earlyeios(gnd),
+ .pfdfbclk(gnd),
+ .inclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\pll_inclk[0]~inputclkctrl_outclk }),
+ .dprioin({\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [899],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [898],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [897],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [896],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [895],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [894],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [893],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [892],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [891],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [890],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [889],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [888],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [887],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [886],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [885],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [884],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [883],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [882],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [881],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [880],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [879],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [878],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [877],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [876],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [875],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [874],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [873],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [872],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [871],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [870],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [869],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [868],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [867],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [866],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [865],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [864],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [863],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [862],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [861],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [860],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [859],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [858],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [857],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [856],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [855],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [854],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [853],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [852],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [851],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [850],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [849],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [848],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [847],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [846],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [845],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [844],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [843],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [842],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [841],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [840],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [839],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [838],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [837],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [836],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [835],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [834],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [833],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [832],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [831],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [830],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [829],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [828],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [827],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [826],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [825],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [824],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [823],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [822],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [821],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [820],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [819],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [818],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [817],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [816],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [815],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [814],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [813],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [812],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [811],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [810],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [809],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [808],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [807],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [806],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [805],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [804],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [803],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [802],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [801],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [800],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [799],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [798],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [797],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [796],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [795],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [794],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [793],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [792],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [791],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [790],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [789],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [788],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [787],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [786],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [785],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [784],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [783],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [782],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [781],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [780],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [779],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [778],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [777],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [776],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [775],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [774],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [773],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [772],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [771],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [770],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [769],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [768],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [767],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [766],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [765],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [764],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [763],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [762],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [761],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [760],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [759],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [758],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [757],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [756],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [755],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [754],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [753],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [752],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [751],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [750],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [749],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [748],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [747],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [746],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [745],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [744],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [743],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [742],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [741],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [740],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [739],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [738],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [737],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [736],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [735],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [734],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [733],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [732],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [731],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [730],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [729],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [728],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [727],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [726],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [725],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [724],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [723],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [722],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [721],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [720],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [719],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [718],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [717],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [716],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [715],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [714],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [713],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [712],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [711],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [710],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [709],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [708],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [707],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [706],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [705],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [704],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [703],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [702],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [701],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [700],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [699],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [698],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [697],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [696],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [695],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [694],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [693],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [692],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [691],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [690],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [689],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [688],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [687],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [686],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [685],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [684],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [683],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [682],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [681],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [680],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [679],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [678],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [677],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [676],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [675],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [674],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [673],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [672],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [671],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [670],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [669],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [668],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [667],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [666],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [665],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [664],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [663],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [662],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [661],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [660],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [659],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [658],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [657],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [656],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [655],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [654],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [653],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [652],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [651],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [650],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [649],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [648],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [647],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [646],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [645],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [644],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [643],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [642],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [641],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [640],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [639],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [638],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [637],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [636],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [635],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [634],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [633],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [632],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [631],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [630],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [629],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [628],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [627],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [626],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [625],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [624],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [623],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [622],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [621],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [620],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [619],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [618],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [617],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [616],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [615],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [614],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [613],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [612],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [611],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [610],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [609],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [608],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [607],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [606],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [605],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [604],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [603],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [602],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [601],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [600]}),
+ .extra10gin(6'b000000),
+ .pfdfbclkout(),
+ .pfdrefclkout(\pma_direct|auto_generated|rx_pll_pfdrefclkout_wire [2]),
+ .vcobypassout(),
+ .locked(\pma_direct|auto_generated|rx_plllocked_wire [2]),
+ .freqlocked(\pma_direct|auto_generated|wire_rx_cdr_pll2_freqlocked ),
+ .clk(\pma_direct|auto_generated|rx_cdr_pll2_CLK_bus ),
+ .dataout(\pma_direct|auto_generated|rx_cdr_pll2_DATAOUT_bus ),
+ .dprioout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .auto_settings = "true";
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .bandwidth_type = "high";
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .base_data_rate = "3125.0 mbps";
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .channel_num = 2;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .charge_pump_current_bits = 30;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .charge_pump_mode_bits = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .charge_pump_test_enable = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .dprio_config_mode = 6'b000000;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .effective_data_rate = "3125.0 mbps";
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .enable_dynamic_divider = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .fast_lock_control = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .inclk0_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .inclk1_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .inclk2_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .inclk3_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .inclk4_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .inclk5_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .inclk6_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .inclk7_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .inclk8_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .inclk9_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .input_clock_frequency = "156.25 mhz";
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .logical_channel_address = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .logical_tx_pll_number = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .loop_filter_c_bits = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .loop_filter_r_bits = 3200;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .m = 10;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .n = 1;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .pd_charge_pump_current_bits = 5;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .pd_loop_filter_r_bits = 300;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .pfd_clk_select = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .pfd_fb_select = "internal";
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .pll_type = "rx cdr";
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .sim_is_negative_ppm_drift = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .sim_net_ppm_variation = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .test_charge_pump_current_down = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .test_charge_pump_current_up = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .vco_data_rate = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .vco_post_scale = 2;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .vco_range = "high";
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .volt_reg_control_bits = 2;
+defparam \pma_direct|auto_generated|rx_cdr_pll2 .volt_reg_output_bits = 0;
+// synopsys translate_on
+
+// Location: RXPMA_X0_Y15_N137
+stratixiv_hssi_rx_pma \pma_direct|auto_generated|receive_pma2 (
+ .dpriodisable(\pma_direct|auto_generated|edge_cmu_dpriodisableout [0]),
+ .offsetcancellationen(gnd),
+ .powerdn(\pma_direct|auto_generated|tx_pll_cent_unit0~RXIBPOWERDN2 ),
+ .rxpmareset(\pma_direct|auto_generated|tx_pll_cent_unit0~RXANALOGRESETOUT2 ),
+ .plllocked(\pma_direct|auto_generated|rx_plllocked_wire [2]),
+ .ppmdetectrefclk(\pma_direct|auto_generated|rx_pll_pfdrefclkout_wire [2]),
+ .ppmdetectdividedclk(gnd),
+ .locktodata(\pma_direct|auto_generated|rx_locktodata_wire [2]),
+ .locktoref(\pma_direct|auto_generated|comb~2_combout ),
+ .freqlock(gnd),
+ .ignorephslck(gnd),
+ .datain(\rx_datain[2]~input_o ),
+ .seriallpbken(gnd),
+ .seriallpbkin(gnd),
+ .adcepowerdn(gnd),
+ .adcereset(gnd),
+ .adaptcapture(gnd),
+ .adcestandby(gnd),
+ .dprioin({\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT899 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT898 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT897 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT896 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT895 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT894 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT893 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT892 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT891 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT890 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT889 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT888 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT887 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT886 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT885 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT884 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT883 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT882 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT881 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT880 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT879 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT878 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT877 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT876 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT875 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT874 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT873 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT872 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT871 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT870 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT869 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT868 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT867 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT866 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT865 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT864 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT863 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT862 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT861 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT860 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT859 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT858 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT857 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT856 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT855 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT854 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT853 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT852 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT851 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT850 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT849 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT848 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT847 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT846 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT845 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT844 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT843 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT842 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT841 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT840 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT839 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT838 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT837 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT836 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT835 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT834 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT833 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT832 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT831 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT830 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT829 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT828 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT827 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT826 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT825 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT824 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT823 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT822 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT821 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT820 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT819 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT818 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT817 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT816 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT815 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT814 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT813 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT812 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT811 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT810 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT809 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT808 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT807 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT806 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT805 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT804 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT803 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT802 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT801 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT800 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT799 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT798 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT797 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT796 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT795 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT794 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT793 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT792 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT791 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT790 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT789 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT788 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT787 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT786 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT785 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT784 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT783 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT782 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT781 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT780 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT779 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT778 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT777 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT776 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT775 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT774 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT773 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT772 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT771 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT770 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT769 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT768 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT767 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT766 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT765 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT764 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT763 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT762 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT761 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT760 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT759 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT758 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT757 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT756 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT755 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT754 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT753 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT752 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT751 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT750 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT749 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT748 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT747 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT746 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT745 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT744 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT743 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT742 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT741 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT740 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT739 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT738 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT737 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT736 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT735 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT734 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT733 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT732 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT731 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT730 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT729 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT728 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT727 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT726 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT725 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT724 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT723 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT722 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT721 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT720 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT719 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT718 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT717 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT716 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT715 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT714 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT713 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT712 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT711 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT710 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT709 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT708 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT707 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT706 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT705 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT704 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT703 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT702 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT701 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT700 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT699 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT698 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT697 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT696 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT695 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT694 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT693 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT692 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT691 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT690 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT689 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT688 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT687 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT686 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT685 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT684 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT683 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT682 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT681 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT680 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT679 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT678 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT677 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT676 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT675 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT674 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT673 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT672 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT671 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT670 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT669 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT668 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT667 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT666 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT665 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT664 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT663 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT662 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT661 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT660 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT659 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT658 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT657 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT656 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT655 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT654 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT653 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT652 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT651 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT650 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT649 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT648 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT647 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT646 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT645 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT644 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT643 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT642 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT641 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT640 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT639 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT638 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT637 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT636 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT635 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT634 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT633 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT632 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT631 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT630 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT629 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT628 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT627 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT626 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT625 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT624 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT623 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT622 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT621 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT620 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT619 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT618 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT617 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT616 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT615 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT614 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT613 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT612 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT611 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT610 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT609 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT608 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT607 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT606 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT605 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT604 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT603 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT602 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT601 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT600 }),
+ .deserclock({\pma_direct|auto_generated|rx_deserclock_in [11],\pma_direct|auto_generated|rx_deserclock_in [10],\pma_direct|auto_generated|rx_deserclock_in [9],\pma_direct|auto_generated|rx_deserclock_in [8]}),
+ .recoverdatain({\pma_direct|auto_generated|pll_ch_dataout_wire [5],\pma_direct|auto_generated|pll_ch_dataout_wire [4]}),
+ .testbussel({gnd,vcc,vcc,gnd}),
+ .extra10gin(38'b00000000000000000000000000000000000000),
+ .signaldetect(),
+ .clockout(\pma_direct|auto_generated|wire_receive_pma2_clockout ),
+ .ppmdetectclkrel(),
+ .locktorefout(\pma_direct|auto_generated|rx_pma_locktorefout [2]),
+ .dataout(\pma_direct|auto_generated|rx_pma_dataout [2]),
+ .revserialfdbkout(),
+ .reverselpbkout(),
+ .adaptdone(),
+ .dprioout(\pma_direct|auto_generated|receive_pma2_DPRIOOUT_bus ),
+ .recoverdataout(\pma_direct|auto_generated|receive_pma2_RECOVERDATAOUT_bus ),
+ .analogtestbus(\pma_direct|auto_generated|receive_pma2_ANALOGTESTBUS_bus ),
+ .dataoutfull());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|receive_pma2 .adaptive_equalization_mode = "none";
+defparam \pma_direct|auto_generated|receive_pma2 .allow_serial_loopback = "false";
+defparam \pma_direct|auto_generated|receive_pma2 .allow_vco_bypass = 0;
+defparam \pma_direct|auto_generated|receive_pma2 .analog_power = "1.4v";
+defparam \pma_direct|auto_generated|receive_pma2 .channel_number = 2;
+defparam \pma_direct|auto_generated|receive_pma2 .channel_type = "regular";
+defparam \pma_direct|auto_generated|receive_pma2 .common_mode = "0.82v";
+defparam \pma_direct|auto_generated|receive_pma2 .deserialization_factor = 20;
+defparam \pma_direct|auto_generated|receive_pma2 .dfe_piclk_bandwidth = 5;
+defparam \pma_direct|auto_generated|receive_pma2 .dfe_piclk_phase = 16;
+defparam \pma_direct|auto_generated|receive_pma2 .dfe_piclk_sel = 8;
+defparam \pma_direct|auto_generated|receive_pma2 .dprio_config_mode = 6'b000001;
+defparam \pma_direct|auto_generated|receive_pma2 .enable_ltd = "true";
+defparam \pma_direct|auto_generated|receive_pma2 .enable_ltr = "true";
+defparam \pma_direct|auto_generated|receive_pma2 .eq_adapt_seq_control = 0;
+defparam \pma_direct|auto_generated|receive_pma2 .eq_dc_gain = 0;
+defparam \pma_direct|auto_generated|receive_pma2 .eq_max_gradient_control = 0;
+defparam \pma_direct|auto_generated|receive_pma2 .eqa_ctrl = 7;
+defparam \pma_direct|auto_generated|receive_pma2 .eqb_ctrl = 7;
+defparam \pma_direct|auto_generated|receive_pma2 .eqc_ctrl = 7;
+defparam \pma_direct|auto_generated|receive_pma2 .eqd_ctrl = 7;
+defparam \pma_direct|auto_generated|receive_pma2 .eqv_ctrl = 5;
+defparam \pma_direct|auto_generated|receive_pma2 .eyemon_bandwidth = 3;
+defparam \pma_direct|auto_generated|receive_pma2 .force_signal_detect = "true";
+defparam \pma_direct|auto_generated|receive_pma2 .ignore_lock_detect = "false";
+defparam \pma_direct|auto_generated|receive_pma2 .logical_channel_address = 8;
+defparam \pma_direct|auto_generated|receive_pma2 .low_speed_test_select = 0;
+defparam \pma_direct|auto_generated|receive_pma2 .offset_cancellation = 1;
+defparam \pma_direct|auto_generated|receive_pma2 .ppm_gen1_2_xcnt_en = 0;
+defparam \pma_direct|auto_generated|receive_pma2 .ppm_post_eidle = 0;
+defparam \pma_direct|auto_generated|receive_pma2 .ppmselect = 32;
+defparam \pma_direct|auto_generated|receive_pma2 .protocol_hint = "basic";
+defparam \pma_direct|auto_generated|receive_pma2 .send_direct_reverse_serial_loopback = "none";
+defparam \pma_direct|auto_generated|receive_pma2 .signal_detect_hysteresis = 2;
+defparam \pma_direct|auto_generated|receive_pma2 .signal_detect_hysteresis_valid_threshold = 14;
+defparam \pma_direct|auto_generated|receive_pma2 .signal_detect_loss_threshold = 9;
+defparam \pma_direct|auto_generated|receive_pma2 .termination = "oct 100 ohms";
+defparam \pma_direct|auto_generated|receive_pma2 .use_deser_double_data_width = "true";
+defparam \pma_direct|auto_generated|receive_pma2 .use_external_termination = "false";
+defparam \pma_direct|auto_generated|receive_pma2 .use_pma_direct = "true";
+// synopsys translate_on
+
+// Location: HSSIPLL_X0_Y6_N135
+stratixiv_hssi_pll \pma_direct|auto_generated|rx_cdr_pll1 (
+ .rateswitch(gnd),
+ .locktorefclk(\pma_direct|auto_generated|rx_pma_locktorefout [1]),
+ .datain(\pma_direct|auto_generated|rx_pma_dataout [1]),
+ .powerdown(\pma_direct|auto_generated|tx_pll_cent_unit0~RXCRUPOWERDN1 ),
+ .areset(\pma_direct|auto_generated|tx_pll_cent_unit0~RXCRURESETOUT1 ),
+ .dpriodisable(\pma_direct|auto_generated|edge_cmu_dpriodisableout [0]),
+ .earlyeios(gnd),
+ .pfdfbclk(gnd),
+ .inclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\pll_inclk[0]~inputclkctrl_outclk }),
+ .dprioin({\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [599],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [598],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [597],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [596],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [595],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [594],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [593],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [592],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [591],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [590],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [589],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [588],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [587],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [586],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [585],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [584],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [583],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [582],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [581],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [580],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [579],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [578],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [577],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [576],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [575],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [574],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [573],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [572],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [571],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [570],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [569],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [568],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [567],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [566],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [565],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [564],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [563],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [562],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [561],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [560],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [559],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [558],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [557],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [556],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [555],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [554],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [553],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [552],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [551],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [550],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [549],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [548],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [547],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [546],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [545],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [544],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [543],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [542],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [541],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [540],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [539],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [538],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [537],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [536],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [535],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [534],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [533],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [532],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [531],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [530],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [529],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [528],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [527],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [526],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [525],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [524],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [523],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [522],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [521],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [520],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [519],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [518],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [517],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [516],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [515],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [514],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [513],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [512],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [511],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [510],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [509],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [508],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [507],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [506],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [505],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [504],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [503],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [502],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [501],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [500],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [499],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [498],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [497],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [496],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [495],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [494],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [493],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [492],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [491],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [490],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [489],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [488],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [487],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [486],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [485],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [484],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [483],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [482],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [481],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [480],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [479],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [478],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [477],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [476],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [475],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [474],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [473],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [472],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [471],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [470],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [469],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [468],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [467],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [466],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [465],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [464],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [463],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [462],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [461],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [460],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [459],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [458],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [457],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [456],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [455],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [454],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [453],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [452],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [451],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [450],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [449],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [448],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [447],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [446],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [445],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [444],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [443],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [442],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [441],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [440],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [439],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [438],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [437],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [436],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [435],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [434],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [433],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [432],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [431],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [430],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [429],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [428],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [427],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [426],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [425],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [424],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [423],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [422],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [421],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [420],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [419],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [418],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [417],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [416],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [415],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [414],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [413],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [412],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [411],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [410],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [409],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [408],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [407],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [406],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [405],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [404],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [403],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [402],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [401],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [400],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [399],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [398],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [397],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [396],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [395],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [394],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [393],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [392],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [391],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [390],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [389],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [388],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [387],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [386],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [385],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [384],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [383],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [382],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [381],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [380],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [379],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [378],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [377],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [376],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [375],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [374],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [373],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [372],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [371],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [370],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [369],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [368],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [367],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [366],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [365],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [364],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [363],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [362],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [361],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [360],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [359],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [358],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [357],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [356],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [355],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [354],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [353],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [352],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [351],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [350],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [349],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [348],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [347],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [346],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [345],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [344],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [343],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [342],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [341],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [340],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [339],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [338],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [337],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [336],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [335],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [334],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [333],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [332],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [331],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [330],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [329],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [328],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [327],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [326],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [325],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [324],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [323],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [322],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [321],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [320],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [319],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [318],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [317],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [316],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [315],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [314],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [313],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [312],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [311],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [310],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [309],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [308],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [307],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [306],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [305],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [304],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [303],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [302],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [301],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [300]}),
+ .extra10gin(6'b000000),
+ .pfdfbclkout(),
+ .pfdrefclkout(\pma_direct|auto_generated|rx_pll_pfdrefclkout_wire [1]),
+ .vcobypassout(),
+ .locked(\pma_direct|auto_generated|rx_plllocked_wire [1]),
+ .freqlocked(\pma_direct|auto_generated|wire_rx_cdr_pll1_freqlocked ),
+ .clk(\pma_direct|auto_generated|rx_cdr_pll1_CLK_bus ),
+ .dataout(\pma_direct|auto_generated|rx_cdr_pll1_DATAOUT_bus ),
+ .dprioout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .auto_settings = "true";
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .bandwidth_type = "high";
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .base_data_rate = "3125.0 mbps";
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .channel_num = 1;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .charge_pump_current_bits = 30;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .charge_pump_mode_bits = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .charge_pump_test_enable = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .dprio_config_mode = 6'b000000;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .effective_data_rate = "3125.0 mbps";
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .enable_dynamic_divider = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .fast_lock_control = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .inclk0_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .inclk1_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .inclk2_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .inclk3_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .inclk4_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .inclk5_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .inclk6_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .inclk7_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .inclk8_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .inclk9_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .input_clock_frequency = "156.25 mhz";
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .logical_channel_address = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .logical_tx_pll_number = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .loop_filter_c_bits = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .loop_filter_r_bits = 3200;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .m = 10;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .n = 1;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .pd_charge_pump_current_bits = 5;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .pd_loop_filter_r_bits = 300;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .pfd_clk_select = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .pfd_fb_select = "internal";
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .pll_type = "rx cdr";
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .sim_is_negative_ppm_drift = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .sim_net_ppm_variation = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .test_charge_pump_current_down = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .test_charge_pump_current_up = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .vco_data_rate = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .vco_post_scale = 2;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .vco_range = "high";
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .volt_reg_control_bits = 2;
+defparam \pma_direct|auto_generated|rx_cdr_pll1 .volt_reg_output_bits = 0;
+// synopsys translate_on
+
+// Location: RXPMA_X0_Y6_N137
+stratixiv_hssi_rx_pma \pma_direct|auto_generated|receive_pma1 (
+ .dpriodisable(\pma_direct|auto_generated|edge_cmu_dpriodisableout [0]),
+ .offsetcancellationen(gnd),
+ .powerdn(\pma_direct|auto_generated|tx_pll_cent_unit0~RXIBPOWERDN1 ),
+ .rxpmareset(\pma_direct|auto_generated|tx_pll_cent_unit0~RXANALOGRESETOUT1 ),
+ .plllocked(\pma_direct|auto_generated|rx_plllocked_wire [1]),
+ .ppmdetectrefclk(\pma_direct|auto_generated|rx_pll_pfdrefclkout_wire [1]),
+ .ppmdetectdividedclk(gnd),
+ .locktodata(\pma_direct|auto_generated|rx_locktodata_wire [1]),
+ .locktoref(\pma_direct|auto_generated|comb~1_combout ),
+ .freqlock(gnd),
+ .ignorephslck(gnd),
+ .datain(\rx_datain[1]~input_o ),
+ .seriallpbken(gnd),
+ .seriallpbkin(gnd),
+ .adcepowerdn(gnd),
+ .adcereset(gnd),
+ .adaptcapture(gnd),
+ .adcestandby(gnd),
+ .dprioin({\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT599 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT598 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT597 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT596 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT595 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT594 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT593 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT592 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT591 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT590 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT589 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT588 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT587 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT586 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT585 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT584 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT583 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT582 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT581 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT580 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT579 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT578 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT577 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT576 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT575 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT574 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT573 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT572 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT571 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT570 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT569 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT568 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT567 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT566 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT565 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT564 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT563 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT562 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT561 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT560 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT559 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT558 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT557 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT556 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT555 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT554 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT553 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT552 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT551 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT550 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT549 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT548 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT547 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT546 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT545 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT544 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT543 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT542 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT541 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT540 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT539 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT538 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT537 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT536 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT535 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT534 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT533 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT532 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT531 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT530 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT529 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT528 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT527 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT526 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT525 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT524 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT523 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT522 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT521 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT520 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT519 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT518 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT517 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT516 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT515 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT514 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT513 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT512 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT511 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT510 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT509 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT508 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT507 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT506 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT505 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT504 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT503 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT502 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT501 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT500 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT499 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT498 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT497 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT496 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT495 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT494 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT493 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT492 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT491 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT490 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT489 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT488 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT487 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT486 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT485 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT484 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT483 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT482 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT481 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT480 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT479 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT478 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT477 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT476 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT475 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT474 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT473 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT472 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT471 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT470 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT469 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT468 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT467 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT466 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT465 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT464 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT463 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT462 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT461 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT460 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT459 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT458 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT457 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT456 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT455 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT454 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT453 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT452 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT451 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT450 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT449 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT448 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT447 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT446 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT445 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT444 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT443 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT442 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT441 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT440 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT439 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT438 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT437 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT436 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT435 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT434 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT433 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT432 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT431 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT430 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT429 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT428 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT427 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT426 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT425 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT424 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT423 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT422 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT421 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT420 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT419 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT418 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT417 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT416 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT415 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT414 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT413 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT412 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT411 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT410 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT409 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT408 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT407 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT406 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT405 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT404 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT403 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT402 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT401 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT400 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT399 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT398 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT397 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT396 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT395 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT394 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT393 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT392 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT391 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT390 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT389 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT388 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT387 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT386 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT385 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT384 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT383 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT382 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT381 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT380 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT379 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT378 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT377 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT376 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT375 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT374 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT373 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT372 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT371 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT370 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT369 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT368 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT367 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT366 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT365 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT364 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT363 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT362 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT361 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT360 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT359 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT358 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT357 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT356 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT355 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT354 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT353 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT352 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT351 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT350 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT349 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT348 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT347 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT346 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT345 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT344 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT343 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT342 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT341 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT340 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT339 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT338 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT337 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT336 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT335 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT334 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT333 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT332 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT331 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT330 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT329 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT328 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT327 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT326 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT325 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT324 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT323 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT322 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT321 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT320 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT319 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT318 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT317 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT316 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT315 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT314 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT313 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT312 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT311 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT310 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT309 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT308 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT307 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT306 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT305 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT304 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT303 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT302 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT301 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT300 }),
+ .deserclock({\pma_direct|auto_generated|rx_deserclock_in [7],\pma_direct|auto_generated|rx_deserclock_in [6],\pma_direct|auto_generated|rx_deserclock_in [5],\pma_direct|auto_generated|rx_deserclock_in [4]}),
+ .recoverdatain({\pma_direct|auto_generated|pll_ch_dataout_wire [3],\pma_direct|auto_generated|pll_ch_dataout_wire [2]}),
+ .testbussel({gnd,vcc,vcc,gnd}),
+ .extra10gin(38'b00000000000000000000000000000000000000),
+ .signaldetect(),
+ .clockout(\pma_direct|auto_generated|wire_receive_pma1_clockout ),
+ .ppmdetectclkrel(),
+ .locktorefout(\pma_direct|auto_generated|rx_pma_locktorefout [1]),
+ .dataout(\pma_direct|auto_generated|rx_pma_dataout [1]),
+ .revserialfdbkout(),
+ .reverselpbkout(),
+ .adaptdone(),
+ .dprioout(\pma_direct|auto_generated|receive_pma1_DPRIOOUT_bus ),
+ .recoverdataout(\pma_direct|auto_generated|receive_pma1_RECOVERDATAOUT_bus ),
+ .analogtestbus(\pma_direct|auto_generated|receive_pma1_ANALOGTESTBUS_bus ),
+ .dataoutfull());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|receive_pma1 .adaptive_equalization_mode = "none";
+defparam \pma_direct|auto_generated|receive_pma1 .allow_serial_loopback = "false";
+defparam \pma_direct|auto_generated|receive_pma1 .allow_vco_bypass = 0;
+defparam \pma_direct|auto_generated|receive_pma1 .analog_power = "1.4v";
+defparam \pma_direct|auto_generated|receive_pma1 .channel_number = 1;
+defparam \pma_direct|auto_generated|receive_pma1 .channel_type = "regular";
+defparam \pma_direct|auto_generated|receive_pma1 .common_mode = "0.82v";
+defparam \pma_direct|auto_generated|receive_pma1 .deserialization_factor = 20;
+defparam \pma_direct|auto_generated|receive_pma1 .dfe_piclk_bandwidth = 5;
+defparam \pma_direct|auto_generated|receive_pma1 .dfe_piclk_phase = 16;
+defparam \pma_direct|auto_generated|receive_pma1 .dfe_piclk_sel = 8;
+defparam \pma_direct|auto_generated|receive_pma1 .dprio_config_mode = 6'b000001;
+defparam \pma_direct|auto_generated|receive_pma1 .enable_ltd = "true";
+defparam \pma_direct|auto_generated|receive_pma1 .enable_ltr = "true";
+defparam \pma_direct|auto_generated|receive_pma1 .eq_adapt_seq_control = 0;
+defparam \pma_direct|auto_generated|receive_pma1 .eq_dc_gain = 0;
+defparam \pma_direct|auto_generated|receive_pma1 .eq_max_gradient_control = 0;
+defparam \pma_direct|auto_generated|receive_pma1 .eqa_ctrl = 7;
+defparam \pma_direct|auto_generated|receive_pma1 .eqb_ctrl = 7;
+defparam \pma_direct|auto_generated|receive_pma1 .eqc_ctrl = 7;
+defparam \pma_direct|auto_generated|receive_pma1 .eqd_ctrl = 7;
+defparam \pma_direct|auto_generated|receive_pma1 .eqv_ctrl = 5;
+defparam \pma_direct|auto_generated|receive_pma1 .eyemon_bandwidth = 3;
+defparam \pma_direct|auto_generated|receive_pma1 .force_signal_detect = "true";
+defparam \pma_direct|auto_generated|receive_pma1 .ignore_lock_detect = "false";
+defparam \pma_direct|auto_generated|receive_pma1 .logical_channel_address = 4;
+defparam \pma_direct|auto_generated|receive_pma1 .low_speed_test_select = 0;
+defparam \pma_direct|auto_generated|receive_pma1 .offset_cancellation = 1;
+defparam \pma_direct|auto_generated|receive_pma1 .ppm_gen1_2_xcnt_en = 0;
+defparam \pma_direct|auto_generated|receive_pma1 .ppm_post_eidle = 0;
+defparam \pma_direct|auto_generated|receive_pma1 .ppmselect = 32;
+defparam \pma_direct|auto_generated|receive_pma1 .protocol_hint = "basic";
+defparam \pma_direct|auto_generated|receive_pma1 .send_direct_reverse_serial_loopback = "none";
+defparam \pma_direct|auto_generated|receive_pma1 .signal_detect_hysteresis = 2;
+defparam \pma_direct|auto_generated|receive_pma1 .signal_detect_hysteresis_valid_threshold = 14;
+defparam \pma_direct|auto_generated|receive_pma1 .signal_detect_loss_threshold = 9;
+defparam \pma_direct|auto_generated|receive_pma1 .termination = "oct 100 ohms";
+defparam \pma_direct|auto_generated|receive_pma1 .use_deser_double_data_width = "true";
+defparam \pma_direct|auto_generated|receive_pma1 .use_external_termination = "false";
+defparam \pma_direct|auto_generated|receive_pma1 .use_pma_direct = "true";
+// synopsys translate_on
+
+// Location: HSSIPLL_X0_Y3_N135
+stratixiv_hssi_pll \pma_direct|auto_generated|rx_cdr_pll0 (
+ .rateswitch(gnd),
+ .locktorefclk(\pma_direct|auto_generated|rx_pma_locktorefout [0]),
+ .datain(\pma_direct|auto_generated|rx_pma_dataout [0]),
+ .powerdown(\pma_direct|auto_generated|tx_pll_cent_unit0~RXCRUPOWERDN0 ),
+ .areset(\pma_direct|auto_generated|tx_pll_cent_unit0~RXCRURESETOUT0 ),
+ .dpriodisable(\pma_direct|auto_generated|edge_cmu_dpriodisableout [0]),
+ .earlyeios(gnd),
+ .pfdfbclk(gnd),
+ .inclk({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\pll_inclk[0]~inputclkctrl_outclk }),
+ .dprioin({\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [299],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [298],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [297],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [296],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [295],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [294],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [293],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [292],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [291],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [290],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [289],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [288],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [287],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [286],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [285],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [284],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [283],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [282],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [281],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [280],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [279],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [278],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [277],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [276],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [275],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [274],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [273],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [272],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [271],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [270],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [269],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [268],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [267],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [266],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [265],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [264],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [263],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [262],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [261],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [260],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [259],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [258],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [257],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [256],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [255],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [254],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [253],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [252],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [251],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [250],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [249],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [248],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [247],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [246],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [245],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [244],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [243],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [242],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [241],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [240],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [239],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [238],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [237],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [236],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [235],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [234],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [233],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [232],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [231],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [230],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [229],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [228],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [227],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [226],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [225],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [224],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [223],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [222],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [221],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [220],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [219],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [218],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [217],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [216],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [215],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [214],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [213],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [212],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [211],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [210],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [209],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [208],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [207],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [206],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [205],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [204],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [203],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [202],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [201],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [200],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [199],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [198],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [197],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [196],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [195],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [194],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [193],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [192],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [191],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [190],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [189],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [188],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [187],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [186],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [185],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [184],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [183],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [182],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [181],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [180],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [179],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [178],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [177],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [176],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [175],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [174],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [173],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [172],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [171],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [170],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [169],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [168],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [167],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [166],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [165],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [164],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [163],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [162],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [161],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [160],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [159],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [158],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [157],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [156],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [155],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [154],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [153],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [152],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [151],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [150],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [149],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [148],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [147],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [146],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [145],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [144],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [143],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [142],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [141],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [140],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [139],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [138],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [137],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [136],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [135],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [134],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [133],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [132],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [131],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [130],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [129],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [128],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [127],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [126],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [125],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [124],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [123],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [122],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [121],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [120],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [119],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [118],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [117],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [116],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [115],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [114],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [113],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [112],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [111],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [110],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [109],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [108],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [107],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [106],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [105],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [104],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [103],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [102],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [101],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [100],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [99],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [98],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [97],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [96],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [95],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [94],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [93],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [92],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [91],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [90],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [89],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [88],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [87],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [86],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [85],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [84],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [83],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [82],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [81],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [80],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [79],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [78],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [77],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [76],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [75],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [74],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [73],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [72],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [71],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [70],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [69],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [68],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [67],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [66],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [65],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [64],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [63],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [62],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [61],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [60],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [59],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [58],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [57],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [56],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [55],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [54],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [53],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [52],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [51],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [50],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [49],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [48],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [47],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [46],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [45],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [44],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [43],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [42],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [41],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [40],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [39],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [38],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [37],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [36],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [35],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [34],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [33],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [32],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [31],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [30],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [29],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [28],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [27],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [26],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [25],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [24],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [23],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [22],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [21],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [20],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [19],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [18],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [17],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [16],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [15],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [14],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [13],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [12],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [11],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [10],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [9],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [8],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [7],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [6],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [5],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [4],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [3],
+\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [2],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [1],\pma_direct|auto_generated|wire_tx_pll_cent_unit0_cmuplldprioout [0]}),
+ .extra10gin(6'b000000),
+ .pfdfbclkout(),
+ .pfdrefclkout(\pma_direct|auto_generated|rx_pll_pfdrefclkout_wire [0]),
+ .vcobypassout(),
+ .locked(\pma_direct|auto_generated|rx_plllocked_wire [0]),
+ .freqlocked(\pma_direct|auto_generated|wire_rx_cdr_pll0_freqlocked ),
+ .clk(\pma_direct|auto_generated|rx_cdr_pll0_CLK_bus ),
+ .dataout(\pma_direct|auto_generated|rx_cdr_pll0_DATAOUT_bus ),
+ .dprioout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .auto_settings = "true";
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .bandwidth_type = "high";
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .base_data_rate = "3125.0 mbps";
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .channel_num = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .charge_pump_current_bits = 30;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .charge_pump_mode_bits = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .charge_pump_test_enable = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .dprio_config_mode = 6'b000000;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .effective_data_rate = "3125.0 mbps";
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .enable_dynamic_divider = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .fast_lock_control = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .inclk0_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .inclk1_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .inclk2_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .inclk3_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .inclk4_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .inclk5_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .inclk6_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .inclk7_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .inclk8_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .inclk9_input_period = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .input_clock_frequency = "156.25 mhz";
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .logical_channel_address = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .logical_tx_pll_number = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .loop_filter_c_bits = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .loop_filter_r_bits = 3200;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .m = 10;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .n = 1;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .pd_charge_pump_current_bits = 5;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .pd_loop_filter_r_bits = 300;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .pfd_clk_select = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .pfd_fb_select = "internal";
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .pll_type = "rx cdr";
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .sim_is_negative_ppm_drift = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .sim_net_ppm_variation = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .test_charge_pump_current_down = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .test_charge_pump_current_up = "false";
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .vco_data_rate = 0;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .vco_post_scale = 2;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .vco_range = "high";
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .volt_reg_control_bits = 2;
+defparam \pma_direct|auto_generated|rx_cdr_pll0 .volt_reg_output_bits = 0;
+// synopsys translate_on
+
+// Location: RXPMA_X0_Y3_N137
+stratixiv_hssi_rx_pma \pma_direct|auto_generated|receive_pma0 (
+ .dpriodisable(\pma_direct|auto_generated|edge_cmu_dpriodisableout [0]),
+ .offsetcancellationen(gnd),
+ .powerdn(\pma_direct|auto_generated|tx_pll_cent_unit0~RXIBPOWERDN0 ),
+ .rxpmareset(\pma_direct|auto_generated|tx_pll_cent_unit0~RXANALOGRESETOUT0 ),
+ .plllocked(\pma_direct|auto_generated|rx_plllocked_wire [0]),
+ .ppmdetectrefclk(\pma_direct|auto_generated|rx_pll_pfdrefclkout_wire [0]),
+ .ppmdetectdividedclk(gnd),
+ .locktodata(\pma_direct|auto_generated|rx_locktodata_wire [0]),
+ .locktoref(\pma_direct|auto_generated|comb~0_combout ),
+ .freqlock(gnd),
+ .ignorephslck(gnd),
+ .datain(\rx_datain[0]~input_o ),
+ .seriallpbken(gnd),
+ .seriallpbkin(gnd),
+ .adcepowerdn(gnd),
+ .adcereset(gnd),
+ .adaptcapture(gnd),
+ .adcestandby(gnd),
+ .dprioin({\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT299 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT298 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT297 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT296 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT295 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT294 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT293 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT292 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT291 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT290 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT289 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT288 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT287 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT286 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT285 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT284 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT283 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT282 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT281 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT280 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT279 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT278 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT277 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT276 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT275 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT274 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT273 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT272 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT271 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT270 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT269 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT268 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT267 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT266 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT265 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT264 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT263 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT262 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT261 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT260 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT259 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT258 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT257 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT256 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT255 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT254 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT253 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT252 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT251 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT250 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT249 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT248 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT247 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT246 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT245 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT244 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT243 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT242 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT241 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT240 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT239 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT238 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT237 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT236 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT235 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT234 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT233 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT232 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT231 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT230 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT229 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT228 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT227 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT226 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT225 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT224 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT223 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT222 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT221 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT220 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT219 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT218 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT217 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT216 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT215 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT214 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT213 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT212 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT211 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT210 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT209 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT208 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT207 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT206 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT205 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT204 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT203 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT202 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT201 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT200 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT199 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT198 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT197 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT196 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT195 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT194 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT193 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT192 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT191 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT190 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT189 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT188 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT187 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT186 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT185 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT184 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT183 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT182 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT181 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT180 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT179 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT178 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT177 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT176 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT175 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT174 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT173 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT172 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT171 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT170 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT169 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT168 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT167 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT166 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT165 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT164 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT163 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT162 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT161 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT160 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT159 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT158 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT157 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT156 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT155 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT154 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT153 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT152 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT151 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT150 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT149 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT148 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT147 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT146 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT145 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT144 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT143 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT142 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT141 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT140 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT139 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT138 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT137 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT136 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT135 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT134 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT133 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT132 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT131 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT130 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT129 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT128 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT127 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT126 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT125 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT124 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT123 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT122 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT121 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT120 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT119 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT118 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT117 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT116 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT115 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT114 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT113 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT112 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT111 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT110 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT109 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT108 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT107 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT106 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT105 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT104 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT103 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT102 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT101 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT100 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT99 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT98 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT97 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT96 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT95 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT94 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT93 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT92 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT91 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT90 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT89 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT88 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT87 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT86 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT85 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT84 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT83 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT82 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT81 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT80 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT79 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT78 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT77 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT76 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT75 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT74 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT73 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT72 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT71 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT70 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT69 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT68 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT67 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT66 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT65 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT64 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT63 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT62 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT61 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT60 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT59 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT58 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT57 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT56 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT55 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT54 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT53 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT52 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT51 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT50 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT49 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT48 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT47 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT46 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT45 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT44 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT43 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT42 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT41 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT40 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT39 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT38 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT37 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT36 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT35 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT34 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT33 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT32 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT31 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT30 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT29 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT28 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT27 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT26 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT25 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT24 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT23 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT22 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT21 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT20 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT19 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT18 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT17 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT16 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT15 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT14 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT13 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT12 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT11 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT10 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT9 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT8 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT7 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT6 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT5 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT4 ,
+\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT3 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT2 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT1 ,\pma_direct|auto_generated|tx_pll_cent_unit0~RXPMADRPIOOUT0 }),
+ .deserclock({\pma_direct|auto_generated|rx_deserclock_in [3],\pma_direct|auto_generated|rx_deserclock_in [2],\pma_direct|auto_generated|rx_deserclock_in [1],\pma_direct|auto_generated|rx_deserclock_in [0]}),
+ .recoverdatain({\pma_direct|auto_generated|pll_ch_dataout_wire [1],\pma_direct|auto_generated|pll_ch_dataout_wire [0]}),
+ .testbussel({gnd,vcc,vcc,gnd}),
+ .extra10gin(38'b00000000000000000000000000000000000000),
+ .signaldetect(),
+ .clockout(\pma_direct|auto_generated|wire_receive_pma0_clockout ),
+ .ppmdetectclkrel(),
+ .locktorefout(\pma_direct|auto_generated|rx_pma_locktorefout [0]),
+ .dataout(\pma_direct|auto_generated|rx_pma_dataout [0]),
+ .revserialfdbkout(),
+ .reverselpbkout(),
+ .adaptdone(),
+ .dprioout(\pma_direct|auto_generated|receive_pma0_DPRIOOUT_bus ),
+ .recoverdataout(\pma_direct|auto_generated|receive_pma0_RECOVERDATAOUT_bus ),
+ .analogtestbus(\pma_direct|auto_generated|receive_pma0_ANALOGTESTBUS_bus ),
+ .dataoutfull());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|receive_pma0 .adaptive_equalization_mode = "none";
+defparam \pma_direct|auto_generated|receive_pma0 .allow_serial_loopback = "false";
+defparam \pma_direct|auto_generated|receive_pma0 .allow_vco_bypass = 0;
+defparam \pma_direct|auto_generated|receive_pma0 .analog_power = "1.4v";
+defparam \pma_direct|auto_generated|receive_pma0 .channel_number = 0;
+defparam \pma_direct|auto_generated|receive_pma0 .channel_type = "regular";
+defparam \pma_direct|auto_generated|receive_pma0 .common_mode = "0.82v";
+defparam \pma_direct|auto_generated|receive_pma0 .deserialization_factor = 20;
+defparam \pma_direct|auto_generated|receive_pma0 .dfe_piclk_bandwidth = 5;
+defparam \pma_direct|auto_generated|receive_pma0 .dfe_piclk_phase = 16;
+defparam \pma_direct|auto_generated|receive_pma0 .dfe_piclk_sel = 8;
+defparam \pma_direct|auto_generated|receive_pma0 .dprio_config_mode = 6'b000001;
+defparam \pma_direct|auto_generated|receive_pma0 .enable_ltd = "true";
+defparam \pma_direct|auto_generated|receive_pma0 .enable_ltr = "true";
+defparam \pma_direct|auto_generated|receive_pma0 .eq_adapt_seq_control = 0;
+defparam \pma_direct|auto_generated|receive_pma0 .eq_dc_gain = 0;
+defparam \pma_direct|auto_generated|receive_pma0 .eq_max_gradient_control = 0;
+defparam \pma_direct|auto_generated|receive_pma0 .eqa_ctrl = 7;
+defparam \pma_direct|auto_generated|receive_pma0 .eqb_ctrl = 7;
+defparam \pma_direct|auto_generated|receive_pma0 .eqc_ctrl = 7;
+defparam \pma_direct|auto_generated|receive_pma0 .eqd_ctrl = 7;
+defparam \pma_direct|auto_generated|receive_pma0 .eqv_ctrl = 5;
+defparam \pma_direct|auto_generated|receive_pma0 .eyemon_bandwidth = 3;
+defparam \pma_direct|auto_generated|receive_pma0 .force_signal_detect = "true";
+defparam \pma_direct|auto_generated|receive_pma0 .ignore_lock_detect = "false";
+defparam \pma_direct|auto_generated|receive_pma0 .logical_channel_address = 0;
+defparam \pma_direct|auto_generated|receive_pma0 .low_speed_test_select = 0;
+defparam \pma_direct|auto_generated|receive_pma0 .offset_cancellation = 1;
+defparam \pma_direct|auto_generated|receive_pma0 .ppm_gen1_2_xcnt_en = 0;
+defparam \pma_direct|auto_generated|receive_pma0 .ppm_post_eidle = 0;
+defparam \pma_direct|auto_generated|receive_pma0 .ppmselect = 32;
+defparam \pma_direct|auto_generated|receive_pma0 .protocol_hint = "basic";
+defparam \pma_direct|auto_generated|receive_pma0 .send_direct_reverse_serial_loopback = "none";
+defparam \pma_direct|auto_generated|receive_pma0 .signal_detect_hysteresis = 2;
+defparam \pma_direct|auto_generated|receive_pma0 .signal_detect_hysteresis_valid_threshold = 14;
+defparam \pma_direct|auto_generated|receive_pma0 .signal_detect_loss_threshold = 9;
+defparam \pma_direct|auto_generated|receive_pma0 .termination = "oct 100 ohms";
+defparam \pma_direct|auto_generated|receive_pma0 .use_deser_double_data_width = "true";
+defparam \pma_direct|auto_generated|receive_pma0 .use_external_termination = "false";
+defparam \pma_direct|auto_generated|receive_pma0 .use_pma_direct = "true";
+// synopsys translate_on
+
+// Location: LABCELL_X113_Y128_N0
+stratixiv_lcell_comb \~QUARTUS_CREATED_GND~I (
+// Equation(s):
+// \~QUARTUS_CREATED_GND~I_combout = GND
+
+ .dataa(gnd),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\~QUARTUS_CREATED_GND~I_combout ),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
+defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
+defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
+// synopsys translate_on
+
+// Location: CLKCTRL_X0_Y19_N127
+stratixiv_clkena \pma_direct|auto_generated|wire_transmit_pma0_clockout~clkctrl (
+ .inclk(\pma_direct|auto_generated|wire_transmit_pma0_clockout ),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .outclk(\pma_direct|auto_generated|wire_transmit_pma0_clockout~clkctrl_outclk ),
+ .enaout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|wire_transmit_pma0_clockout~clkctrl .clock_type = "periphery clock";
+defparam \pma_direct|auto_generated|wire_transmit_pma0_clockout~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: CLKCTRL_X0_Y22_N127
+stratixiv_clkena \pma_direct|auto_generated|wire_transmit_pma1_clockout~clkctrl (
+ .inclk(\pma_direct|auto_generated|wire_transmit_pma1_clockout ),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .outclk(\pma_direct|auto_generated|wire_transmit_pma1_clockout~clkctrl_outclk ),
+ .enaout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|wire_transmit_pma1_clockout~clkctrl .clock_type = "periphery clock";
+defparam \pma_direct|auto_generated|wire_transmit_pma1_clockout~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: CLKCTRL_X0_Y33_N127
+stratixiv_clkena \pma_direct|auto_generated|wire_transmit_pma2_clockout~clkctrl (
+ .inclk(\pma_direct|auto_generated|wire_transmit_pma2_clockout ),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .outclk(\pma_direct|auto_generated|wire_transmit_pma2_clockout~clkctrl_outclk ),
+ .enaout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|wire_transmit_pma2_clockout~clkctrl .clock_type = "periphery clock";
+defparam \pma_direct|auto_generated|wire_transmit_pma2_clockout~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: CLKCTRL_X0_Y37_N127
+stratixiv_clkena \pma_direct|auto_generated|wire_transmit_pma3_clockout~clkctrl (
+ .inclk(\pma_direct|auto_generated|wire_transmit_pma3_clockout ),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .outclk(\pma_direct|auto_generated|wire_transmit_pma3_clockout~clkctrl_outclk ),
+ .enaout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|wire_transmit_pma3_clockout~clkctrl .clock_type = "periphery clock";
+defparam \pma_direct|auto_generated|wire_transmit_pma3_clockout~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: CLKCTRL_X0_Y18_N127
+stratixiv_clkena \pma_direct|auto_generated|wire_receive_pma0_clockout~clkctrl (
+ .inclk(\pma_direct|auto_generated|wire_receive_pma0_clockout ),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .outclk(\pma_direct|auto_generated|wire_receive_pma0_clockout~clkctrl_outclk ),
+ .enaout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|wire_receive_pma0_clockout~clkctrl .clock_type = "periphery clock";
+defparam \pma_direct|auto_generated|wire_receive_pma0_clockout~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: CLKCTRL_X0_Y21_N127
+stratixiv_clkena \pma_direct|auto_generated|wire_receive_pma1_clockout~clkctrl (
+ .inclk(\pma_direct|auto_generated|wire_receive_pma1_clockout ),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .outclk(\pma_direct|auto_generated|wire_receive_pma1_clockout~clkctrl_outclk ),
+ .enaout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|wire_receive_pma1_clockout~clkctrl .clock_type = "periphery clock";
+defparam \pma_direct|auto_generated|wire_receive_pma1_clockout~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: CLKCTRL_X0_Y32_N127
+stratixiv_clkena \pma_direct|auto_generated|wire_receive_pma2_clockout~clkctrl (
+ .inclk(\pma_direct|auto_generated|wire_receive_pma2_clockout ),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .outclk(\pma_direct|auto_generated|wire_receive_pma2_clockout~clkctrl_outclk ),
+ .enaout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|wire_receive_pma2_clockout~clkctrl .clock_type = "periphery clock";
+defparam \pma_direct|auto_generated|wire_receive_pma2_clockout~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: CLKCTRL_X0_Y35_N127
+stratixiv_clkena \pma_direct|auto_generated|wire_receive_pma3_clockout~clkctrl (
+ .inclk(\pma_direct|auto_generated|wire_receive_pma3_clockout ),
+ .ena(vcc),
+ .devclrn(devclrn),
+ .devpor(devpor),
+ .outclk(\pma_direct|auto_generated|wire_receive_pma3_clockout~clkctrl_outclk ),
+ .enaout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|wire_receive_pma3_clockout~clkctrl .clock_type = "periphery clock";
+defparam \pma_direct|auto_generated|wire_receive_pma3_clockout~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LABCELL_X5_Y12_N22
+stratixiv_lcell_comb \pma_direct|auto_generated|rx_freqlocked[0] (
+// Equation(s):
+// \pma_direct|auto_generated|rx_freqlocked [0] = ( \pma_direct|auto_generated|wire_rx_cdr_pll0_freqlocked & ( !\rx_analogreset[0]~input_o ) )
+
+ .dataa(!\rx_analogreset[0]~input_o ),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(!\pma_direct|auto_generated|wire_rx_cdr_pll0_freqlocked ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\pma_direct|auto_generated|rx_freqlocked [0]),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|rx_freqlocked[0] .extended_lut = "off";
+defparam \pma_direct|auto_generated|rx_freqlocked[0] .lut_mask = 64'h00000000AAAAAAAA;
+defparam \pma_direct|auto_generated|rx_freqlocked[0] .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X5_Y12_N4
+stratixiv_lcell_comb \pma_direct|auto_generated|rx_freqlocked[1] (
+// Equation(s):
+// \pma_direct|auto_generated|rx_freqlocked [1] = (!\rx_analogreset[1]~input_o & \pma_direct|auto_generated|wire_rx_cdr_pll1_freqlocked )
+
+ .dataa(gnd),
+ .datab(!\rx_analogreset[1]~input_o ),
+ .datac(!\pma_direct|auto_generated|wire_rx_cdr_pll1_freqlocked ),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\pma_direct|auto_generated|rx_freqlocked [1]),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|rx_freqlocked[1] .extended_lut = "off";
+defparam \pma_direct|auto_generated|rx_freqlocked[1] .lut_mask = 64'h0C0C0C0C0C0C0C0C;
+defparam \pma_direct|auto_generated|rx_freqlocked[1] .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X5_Y12_N28
+stratixiv_lcell_comb \pma_direct|auto_generated|rx_freqlocked[2] (
+// Equation(s):
+// \pma_direct|auto_generated|rx_freqlocked [2] = (!\rx_analogreset[2]~input_o & \pma_direct|auto_generated|wire_rx_cdr_pll2_freqlocked )
+
+ .dataa(gnd),
+ .datab(!\rx_analogreset[2]~input_o ),
+ .datac(gnd),
+ .datad(!\pma_direct|auto_generated|wire_rx_cdr_pll2_freqlocked ),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\pma_direct|auto_generated|rx_freqlocked [2]),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|rx_freqlocked[2] .extended_lut = "off";
+defparam \pma_direct|auto_generated|rx_freqlocked[2] .lut_mask = 64'h00CC00CC00CC00CC;
+defparam \pma_direct|auto_generated|rx_freqlocked[2] .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X5_Y12_N12
+stratixiv_lcell_comb \pma_direct|auto_generated|rx_freqlocked[3] (
+// Equation(s):
+// \pma_direct|auto_generated|rx_freqlocked [3] = ( \pma_direct|auto_generated|wire_rx_cdr_pll3_freqlocked & ( !\rx_analogreset[3]~input_o ) )
+
+ .dataa(!\rx_analogreset[3]~input_o ),
+ .datab(gnd),
+ .datac(gnd),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(!\pma_direct|auto_generated|wire_rx_cdr_pll3_freqlocked ),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\pma_direct|auto_generated|rx_freqlocked [3]),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|rx_freqlocked[3] .extended_lut = "off";
+defparam \pma_direct|auto_generated|rx_freqlocked[3] .lut_mask = 64'h00000000AAAAAAAA;
+defparam \pma_direct|auto_generated|rx_freqlocked[3] .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X5_Y12_N20
+stratixiv_lcell_comb \pma_direct|auto_generated|rx_pll_locked[0] (
+// Equation(s):
+// \pma_direct|auto_generated|rx_pll_locked [0] = (!\rx_analogreset[0]~input_o & \pma_direct|auto_generated|rx_plllocked_wire [0])
+
+ .dataa(!\rx_analogreset[0]~input_o ),
+ .datab(gnd),
+ .datac(!\pma_direct|auto_generated|rx_plllocked_wire [0]),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\pma_direct|auto_generated|rx_pll_locked [0]),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|rx_pll_locked[0] .extended_lut = "off";
+defparam \pma_direct|auto_generated|rx_pll_locked[0] .lut_mask = 64'h0A0A0A0A0A0A0A0A;
+defparam \pma_direct|auto_generated|rx_pll_locked[0] .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X5_Y12_N6
+stratixiv_lcell_comb \pma_direct|auto_generated|rx_pll_locked[1] (
+// Equation(s):
+// \pma_direct|auto_generated|rx_pll_locked [1] = (!\rx_analogreset[1]~input_o & \pma_direct|auto_generated|rx_plllocked_wire [1])
+
+ .dataa(gnd),
+ .datab(!\rx_analogreset[1]~input_o ),
+ .datac(gnd),
+ .datad(!\pma_direct|auto_generated|rx_plllocked_wire [1]),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\pma_direct|auto_generated|rx_pll_locked [1]),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|rx_pll_locked[1] .extended_lut = "off";
+defparam \pma_direct|auto_generated|rx_pll_locked[1] .lut_mask = 64'h00CC00CC00CC00CC;
+defparam \pma_direct|auto_generated|rx_pll_locked[1] .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X5_Y12_N30
+stratixiv_lcell_comb \pma_direct|auto_generated|rx_pll_locked[2] (
+// Equation(s):
+// \pma_direct|auto_generated|rx_pll_locked [2] = (!\rx_analogreset[2]~input_o & \pma_direct|auto_generated|rx_plllocked_wire [2])
+
+ .dataa(gnd),
+ .datab(!\rx_analogreset[2]~input_o ),
+ .datac(!\pma_direct|auto_generated|rx_plllocked_wire [2]),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\pma_direct|auto_generated|rx_pll_locked [2]),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|rx_pll_locked[2] .extended_lut = "off";
+defparam \pma_direct|auto_generated|rx_pll_locked[2] .lut_mask = 64'h0C0C0C0C0C0C0C0C;
+defparam \pma_direct|auto_generated|rx_pll_locked[2] .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X5_Y12_N14
+stratixiv_lcell_comb \pma_direct|auto_generated|rx_pll_locked[3] (
+// Equation(s):
+// \pma_direct|auto_generated|rx_pll_locked [3] = (!\rx_analogreset[3]~input_o & \pma_direct|auto_generated|rx_plllocked_wire [3])
+
+ .dataa(!\rx_analogreset[3]~input_o ),
+ .datab(gnd),
+ .datac(!\pma_direct|auto_generated|rx_plllocked_wire [3]),
+ .datad(gnd),
+ .datae(gnd),
+ .dataf(gnd),
+ .datag(gnd),
+ .cin(gnd),
+ .sharein(gnd),
+ .combout(\pma_direct|auto_generated|rx_pll_locked [3]),
+ .sumout(),
+ .cout(),
+ .shareout());
+// synopsys translate_off
+defparam \pma_direct|auto_generated|rx_pll_locked[3] .extended_lut = "off";
+defparam \pma_direct|auto_generated|rx_pll_locked[3] .lut_mask = 64'h0A0A0A0A0A0A0A0A;
+defparam \pma_direct|auto_generated|rx_pll_locked[3] .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y102_N32
+stratixiv_io_ibuf \rx_locktodata[4]~input (
+ .i(rx_locktodata[4]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[4]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[4]~input .bus_hold = "false";
+defparam \rx_locktodata[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y113_N1
+stratixiv_io_ibuf \rx_locktodata[5]~input (
+ .i(rx_locktodata[5]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[5]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[5]~input .bus_hold = "false";
+defparam \rx_locktodata[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y45_N1
+stratixiv_io_ibuf \rx_locktodata[6]~input (
+ .i(rx_locktodata[6]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[6]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[6]~input .bus_hold = "false";
+defparam \rx_locktodata[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X169_Y129_N94
+stratixiv_io_ibuf \rx_locktodata[7]~input (
+ .i(rx_locktodata[7]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[7]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[7]~input .bus_hold = "false";
+defparam \rx_locktodata[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y83_N32
+stratixiv_io_ibuf \rx_locktodata[8]~input (
+ .i(rx_locktodata[8]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[8]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[8]~input .bus_hold = "false";
+defparam \rx_locktodata[8]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y26_N94
+stratixiv_io_ibuf \rx_locktodata[9]~input (
+ .i(rx_locktodata[9]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[9]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[9]~input .bus_hold = "false";
+defparam \rx_locktodata[9]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y54_N1
+stratixiv_io_ibuf \rx_locktodata[10]~input (
+ .i(rx_locktodata[10]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[10]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[10]~input .bus_hold = "false";
+defparam \rx_locktodata[10]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X162_Y129_N32
+stratixiv_io_ibuf \rx_locktodata[11]~input (
+ .i(rx_locktodata[11]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[11]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[11]~input .bus_hold = "false";
+defparam \rx_locktodata[11]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y21_N63
+stratixiv_io_ibuf \rx_locktodata[12]~input (
+ .i(rx_locktodata[12]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[12]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[12]~input .bus_hold = "false";
+defparam \rx_locktodata[12]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X80_Y129_N1
+stratixiv_io_ibuf \rx_locktodata[13]~input (
+ .i(rx_locktodata[13]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[13]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[13]~input .bus_hold = "false";
+defparam \rx_locktodata[13]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X110_Y0_N63
+stratixiv_io_ibuf \rx_locktodata[14]~input (
+ .i(rx_locktodata[14]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[14]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[14]~input .bus_hold = "false";
+defparam \rx_locktodata[14]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X108_Y0_N94
+stratixiv_io_ibuf \rx_locktodata[15]~input (
+ .i(rx_locktodata[15]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[15]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[15]~input .bus_hold = "false";
+defparam \rx_locktodata[15]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y113_N63
+stratixiv_io_ibuf \rx_locktodata[16]~input (
+ .i(rx_locktodata[16]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[16]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[16]~input .bus_hold = "false";
+defparam \rx_locktodata[16]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X64_Y129_N32
+stratixiv_io_ibuf \rx_locktodata[17]~input (
+ .i(rx_locktodata[17]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[17]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[17]~input .bus_hold = "false";
+defparam \rx_locktodata[17]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y98_N63
+stratixiv_io_ibuf \rx_locktodata[18]~input (
+ .i(rx_locktodata[18]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[18]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[18]~input .bus_hold = "false";
+defparam \rx_locktodata[18]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y83_N1
+stratixiv_io_ibuf \rx_locktodata[19]~input (
+ .i(rx_locktodata[19]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[19]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[19]~input .bus_hold = "false";
+defparam \rx_locktodata[19]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X68_Y129_N32
+stratixiv_io_ibuf \rx_locktodata[20]~input (
+ .i(rx_locktodata[20]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[20]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[20]~input .bus_hold = "false";
+defparam \rx_locktodata[20]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X73_Y0_N1
+stratixiv_io_ibuf \rx_locktodata[21]~input (
+ .i(rx_locktodata[21]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[21]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[21]~input .bus_hold = "false";
+defparam \rx_locktodata[21]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X129_Y0_N1
+stratixiv_io_ibuf \rx_locktodata[22]~input (
+ .i(rx_locktodata[22]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[22]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[22]~input .bus_hold = "false";
+defparam \rx_locktodata[22]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X36_Y129_N1
+stratixiv_io_ibuf \rx_locktodata[23]~input (
+ .i(rx_locktodata[23]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[23]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[23]~input .bus_hold = "false";
+defparam \rx_locktodata[23]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X119_Y129_N94
+stratixiv_io_ibuf \rx_locktodata[24]~input (
+ .i(rx_locktodata[24]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[24]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[24]~input .bus_hold = "false";
+defparam \rx_locktodata[24]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X159_Y0_N63
+stratixiv_io_ibuf \rx_locktodata[25]~input (
+ .i(rx_locktodata[25]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[25]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[25]~input .bus_hold = "false";
+defparam \rx_locktodata[25]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X157_Y0_N63
+stratixiv_io_ibuf \rx_locktodata[26]~input (
+ .i(rx_locktodata[26]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[26]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[26]~input .bus_hold = "false";
+defparam \rx_locktodata[26]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y19_N32
+stratixiv_io_ibuf \rx_locktodata[27]~input (
+ .i(rx_locktodata[27]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[27]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[27]~input .bus_hold = "false";
+defparam \rx_locktodata[27]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y74_N32
+stratixiv_io_ibuf \rx_locktodata[28]~input (
+ .i(rx_locktodata[28]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[28]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[28]~input .bus_hold = "false";
+defparam \rx_locktodata[28]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y102_N1
+stratixiv_io_ibuf \rx_locktodata[29]~input (
+ .i(rx_locktodata[29]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[29]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[29]~input .bus_hold = "false";
+defparam \rx_locktodata[29]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y98_N94
+stratixiv_io_ibuf \rx_locktodata[30]~input (
+ .i(rx_locktodata[30]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[30]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[30]~input .bus_hold = "false";
+defparam \rx_locktodata[30]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X80_Y0_N32
+stratixiv_io_ibuf \rx_locktodata[31]~input (
+ .i(rx_locktodata[31]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktodata[31]~input_o ));
+// synopsys translate_off
+defparam \rx_locktodata[31]~input .bus_hold = "false";
+defparam \rx_locktodata[31]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X125_Y129_N32
+stratixiv_io_ibuf \rx_analogreset[4]~input (
+ .i(rx_analogreset[4]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[4]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[4]~input .bus_hold = "false";
+defparam \rx_analogreset[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X169_Y0_N94
+stratixiv_io_ibuf \rx_analogreset[5]~input (
+ .i(rx_analogreset[5]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[5]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[5]~input .bus_hold = "false";
+defparam \rx_analogreset[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y102_N63
+stratixiv_io_ibuf \rx_analogreset[6]~input (
+ .i(rx_analogreset[6]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[6]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[6]~input .bus_hold = "false";
+defparam \rx_analogreset[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X169_Y129_N1
+stratixiv_io_ibuf \rx_analogreset[7]~input (
+ .i(rx_analogreset[7]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[7]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[7]~input .bus_hold = "false";
+defparam \rx_analogreset[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X19_Y129_N94
+stratixiv_io_ibuf \rx_analogreset[8]~input (
+ .i(rx_analogreset[8]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[8]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[8]~input .bus_hold = "false";
+defparam \rx_analogreset[8]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y106_N1
+stratixiv_io_ibuf \rx_analogreset[9]~input (
+ .i(rx_analogreset[9]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[9]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[9]~input .bus_hold = "false";
+defparam \rx_analogreset[9]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y28_N1
+stratixiv_io_ibuf \rx_analogreset[10]~input (
+ .i(rx_analogreset[10]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[10]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[10]~input .bus_hold = "false";
+defparam \rx_analogreset[10]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y72_N32
+stratixiv_io_ibuf \rx_analogreset[11]~input (
+ .i(rx_analogreset[11]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[11]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[11]~input .bus_hold = "false";
+defparam \rx_analogreset[11]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y76_N63
+stratixiv_io_ibuf \rx_analogreset[12]~input (
+ .i(rx_analogreset[12]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[12]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[12]~input .bus_hold = "false";
+defparam \rx_analogreset[12]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y115_N1
+stratixiv_io_ibuf \rx_analogreset[13]~input (
+ .i(rx_analogreset[13]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[13]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[13]~input .bus_hold = "false";
+defparam \rx_analogreset[13]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X175_Y0_N94
+stratixiv_io_ibuf \rx_analogreset[14]~input (
+ .i(rx_analogreset[14]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[14]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[14]~input .bus_hold = "false";
+defparam \rx_analogreset[14]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X110_Y0_N32
+stratixiv_io_ibuf \rx_analogreset[15]~input (
+ .i(rx_analogreset[15]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[15]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[15]~input .bus_hold = "false";
+defparam \rx_analogreset[15]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X84_Y0_N63
+stratixiv_io_ibuf \rx_analogreset[16]~input (
+ .i(rx_analogreset[16]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[16]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[16]~input .bus_hold = "false";
+defparam \rx_analogreset[16]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X33_Y129_N1
+stratixiv_io_ibuf \rx_analogreset[17]~input (
+ .i(rx_analogreset[17]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[17]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[17]~input .bus_hold = "false";
+defparam \rx_analogreset[17]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X25_Y129_N94
+stratixiv_io_ibuf \rx_analogreset[18]~input (
+ .i(rx_analogreset[18]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[18]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[18]~input .bus_hold = "false";
+defparam \rx_analogreset[18]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X108_Y129_N94
+stratixiv_io_ibuf \rx_analogreset[19]~input (
+ .i(rx_analogreset[19]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[19]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[19]~input .bus_hold = "false";
+defparam \rx_analogreset[19]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X139_Y0_N32
+stratixiv_io_ibuf \rx_analogreset[20]~input (
+ .i(rx_analogreset[20]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[20]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[20]~input .bus_hold = "false";
+defparam \rx_analogreset[20]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X25_Y129_N63
+stratixiv_io_ibuf \rx_analogreset[21]~input (
+ .i(rx_analogreset[21]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[21]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[21]~input .bus_hold = "false";
+defparam \rx_analogreset[21]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y81_N32
+stratixiv_io_ibuf \rx_analogreset[22]~input (
+ .i(rx_analogreset[22]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[22]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[22]~input .bus_hold = "false";
+defparam \rx_analogreset[22]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X157_Y129_N63
+stratixiv_io_ibuf \rx_analogreset[23]~input (
+ .i(rx_analogreset[23]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[23]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[23]~input .bus_hold = "false";
+defparam \rx_analogreset[23]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y107_N63
+stratixiv_io_ibuf \rx_analogreset[24]~input (
+ .i(rx_analogreset[24]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[24]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[24]~input .bus_hold = "false";
+defparam \rx_analogreset[24]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X17_Y129_N32
+stratixiv_io_ibuf \rx_analogreset[25]~input (
+ .i(rx_analogreset[25]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[25]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[25]~input .bus_hold = "false";
+defparam \rx_analogreset[25]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X148_Y0_N94
+stratixiv_io_ibuf \rx_analogreset[26]~input (
+ .i(rx_analogreset[26]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[26]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[26]~input .bus_hold = "false";
+defparam \rx_analogreset[26]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X73_Y129_N63
+stratixiv_io_ibuf \rx_analogreset[27]~input (
+ .i(rx_analogreset[27]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[27]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[27]~input .bus_hold = "false";
+defparam \rx_analogreset[27]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y81_N63
+stratixiv_io_ibuf \rx_analogreset[28]~input (
+ .i(rx_analogreset[28]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[28]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[28]~input .bus_hold = "false";
+defparam \rx_analogreset[28]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y54_N32
+stratixiv_io_ibuf \rx_analogreset[29]~input (
+ .i(rx_analogreset[29]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[29]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[29]~input .bus_hold = "false";
+defparam \rx_analogreset[29]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X169_Y129_N63
+stratixiv_io_ibuf \rx_analogreset[30]~input (
+ .i(rx_analogreset[30]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[30]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[30]~input .bus_hold = "false";
+defparam \rx_analogreset[30]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X157_Y0_N94
+stratixiv_io_ibuf \rx_analogreset[31]~input (
+ .i(rx_analogreset[31]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_analogreset[31]~input_o ));
+// synopsys translate_off
+defparam \rx_analogreset[31]~input .bus_hold = "false";
+defparam \rx_analogreset[31]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X133_Y129_N94
+stratixiv_io_ibuf \rx_seriallpbken[0]~input (
+ .i(rx_seriallpbken[0]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[0]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[0]~input .bus_hold = "false";
+defparam \rx_seriallpbken[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X125_Y0_N32
+stratixiv_io_ibuf \rx_seriallpbken[1]~input (
+ .i(rx_seriallpbken[1]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[1]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[1]~input .bus_hold = "false";
+defparam \rx_seriallpbken[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y76_N94
+stratixiv_io_ibuf \rx_seriallpbken[2]~input (
+ .i(rx_seriallpbken[2]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[2]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[2]~input .bus_hold = "false";
+defparam \rx_seriallpbken[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y52_N63
+stratixiv_io_ibuf \rx_seriallpbken[3]~input (
+ .i(rx_seriallpbken[3]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[3]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[3]~input .bus_hold = "false";
+defparam \rx_seriallpbken[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X164_Y0_N32
+stratixiv_io_ibuf \rx_seriallpbken[4]~input (
+ .i(rx_seriallpbken[4]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[4]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[4]~input .bus_hold = "false";
+defparam \rx_seriallpbken[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X135_Y129_N1
+stratixiv_io_ibuf \rx_seriallpbken[5]~input (
+ .i(rx_seriallpbken[5]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[5]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[5]~input .bus_hold = "false";
+defparam \rx_seriallpbken[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y60_N1
+stratixiv_io_ibuf \rx_seriallpbken[6]~input (
+ .i(rx_seriallpbken[6]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[6]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[6]~input .bus_hold = "false";
+defparam \rx_seriallpbken[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X68_Y129_N63
+stratixiv_io_ibuf \rx_seriallpbken[7]~input (
+ .i(rx_seriallpbken[7]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[7]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[7]~input .bus_hold = "false";
+defparam \rx_seriallpbken[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X119_Y0_N1
+stratixiv_io_ibuf \rx_seriallpbken[8]~input (
+ .i(rx_seriallpbken[8]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[8]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[8]~input .bus_hold = "false";
+defparam \rx_seriallpbken[8]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X137_Y0_N1
+stratixiv_io_ibuf \rx_seriallpbken[9]~input (
+ .i(rx_seriallpbken[9]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[9]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[9]~input .bus_hold = "false";
+defparam \rx_seriallpbken[9]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X142_Y129_N94
+stratixiv_io_ibuf \rx_seriallpbken[10]~input (
+ .i(rx_seriallpbken[10]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[10]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[10]~input .bus_hold = "false";
+defparam \rx_seriallpbken[10]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X145_Y0_N94
+stratixiv_io_ibuf \rx_seriallpbken[11]~input (
+ .i(rx_seriallpbken[11]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[11]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[11]~input .bus_hold = "false";
+defparam \rx_seriallpbken[11]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X100_Y0_N1
+stratixiv_io_ibuf \rx_seriallpbken[12]~input (
+ .i(rx_seriallpbken[12]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[12]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[12]~input .bus_hold = "false";
+defparam \rx_seriallpbken[12]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X121_Y0_N32
+stratixiv_io_ibuf \rx_seriallpbken[13]~input (
+ .i(rx_seriallpbken[13]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[13]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[13]~input .bus_hold = "false";
+defparam \rx_seriallpbken[13]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y98_N63
+stratixiv_io_ibuf \rx_seriallpbken[14]~input (
+ .i(rx_seriallpbken[14]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[14]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[14]~input .bus_hold = "false";
+defparam \rx_seriallpbken[14]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X150_Y129_N94
+stratixiv_io_ibuf \rx_seriallpbken[15]~input (
+ .i(rx_seriallpbken[15]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[15]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[15]~input .bus_hold = "false";
+defparam \rx_seriallpbken[15]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X70_Y129_N94
+stratixiv_io_ibuf \rx_seriallpbken[16]~input (
+ .i(rx_seriallpbken[16]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[16]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[16]~input .bus_hold = "false";
+defparam \rx_seriallpbken[16]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X64_Y0_N94
+stratixiv_io_ibuf \rx_seriallpbken[17]~input (
+ .i(rx_seriallpbken[17]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[17]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[17]~input .bus_hold = "false";
+defparam \rx_seriallpbken[17]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y31_N94
+stratixiv_io_ibuf \rx_seriallpbken[18]~input (
+ .i(rx_seriallpbken[18]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[18]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[18]~input .bus_hold = "false";
+defparam \rx_seriallpbken[18]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y69_N1
+stratixiv_io_ibuf \rx_seriallpbken[19]~input (
+ .i(rx_seriallpbken[19]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[19]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[19]~input .bus_hold = "false";
+defparam \rx_seriallpbken[19]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y96_N32
+stratixiv_io_ibuf \rx_seriallpbken[20]~input (
+ .i(rx_seriallpbken[20]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[20]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[20]~input .bus_hold = "false";
+defparam \rx_seriallpbken[20]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X85_Y0_N1
+stratixiv_io_ibuf \rx_seriallpbken[21]~input (
+ .i(rx_seriallpbken[21]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[21]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[21]~input .bus_hold = "false";
+defparam \rx_seriallpbken[21]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X137_Y129_N1
+stratixiv_io_ibuf \rx_seriallpbken[22]~input (
+ .i(rx_seriallpbken[22]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[22]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[22]~input .bus_hold = "false";
+defparam \rx_seriallpbken[22]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X42_Y129_N1
+stratixiv_io_ibuf \rx_seriallpbken[23]~input (
+ .i(rx_seriallpbken[23]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[23]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[23]~input .bus_hold = "false";
+defparam \rx_seriallpbken[23]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y106_N32
+stratixiv_io_ibuf \rx_seriallpbken[24]~input (
+ .i(rx_seriallpbken[24]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[24]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[24]~input .bus_hold = "false";
+defparam \rx_seriallpbken[24]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y112_N94
+stratixiv_io_ibuf \rx_seriallpbken[25]~input (
+ .i(rx_seriallpbken[25]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[25]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[25]~input .bus_hold = "false";
+defparam \rx_seriallpbken[25]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X125_Y0_N94
+stratixiv_io_ibuf \rx_seriallpbken[26]~input (
+ .i(rx_seriallpbken[26]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[26]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[26]~input .bus_hold = "false";
+defparam \rx_seriallpbken[26]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y112_N1
+stratixiv_io_ibuf \rx_seriallpbken[27]~input (
+ .i(rx_seriallpbken[27]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[27]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[27]~input .bus_hold = "false";
+defparam \rx_seriallpbken[27]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y76_N32
+stratixiv_io_ibuf \rx_seriallpbken[28]~input (
+ .i(rx_seriallpbken[28]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[28]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[28]~input .bus_hold = "false";
+defparam \rx_seriallpbken[28]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X110_Y0_N1
+stratixiv_io_ibuf \rx_seriallpbken[29]~input (
+ .i(rx_seriallpbken[29]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[29]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[29]~input .bus_hold = "false";
+defparam \rx_seriallpbken[29]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X127_Y129_N32
+stratixiv_io_ibuf \rx_seriallpbken[30]~input (
+ .i(rx_seriallpbken[30]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[30]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[30]~input .bus_hold = "false";
+defparam \rx_seriallpbken[30]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y37_N32
+stratixiv_io_ibuf \rx_seriallpbken[31]~input (
+ .i(rx_seriallpbken[31]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_seriallpbken[31]~input_o ));
+// synopsys translate_off
+defparam \rx_seriallpbken[31]~input .bus_hold = "false";
+defparam \rx_seriallpbken[31]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X164_Y0_N63
+stratixiv_io_ibuf \tx_digitalreset[0]~input (
+ .i(tx_digitalreset[0]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[0]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[0]~input .bus_hold = "false";
+defparam \tx_digitalreset[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y57_N32
+stratixiv_io_ibuf \tx_digitalreset[1]~input (
+ .i(tx_digitalreset[1]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[1]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[1]~input .bus_hold = "false";
+defparam \tx_digitalreset[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y57_N1
+stratixiv_io_ibuf \tx_digitalreset[2]~input (
+ .i(tx_digitalreset[2]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[2]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[2]~input .bus_hold = "false";
+defparam \tx_digitalreset[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y71_N63
+stratixiv_io_ibuf \tx_digitalreset[3]~input (
+ .i(tx_digitalreset[3]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[3]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[3]~input .bus_hold = "false";
+defparam \tx_digitalreset[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y100_N32
+stratixiv_io_ibuf \tx_digitalreset[4]~input (
+ .i(tx_digitalreset[4]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[4]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[4]~input .bus_hold = "false";
+defparam \tx_digitalreset[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X73_Y0_N94
+stratixiv_io_ibuf \tx_digitalreset[5]~input (
+ .i(tx_digitalreset[5]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[5]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[5]~input .bus_hold = "false";
+defparam \tx_digitalreset[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X121_Y0_N63
+stratixiv_io_ibuf \tx_digitalreset[6]~input (
+ .i(tx_digitalreset[6]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[6]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[6]~input .bus_hold = "false";
+defparam \tx_digitalreset[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X121_Y0_N94
+stratixiv_io_ibuf \tx_digitalreset[7]~input (
+ .i(tx_digitalreset[7]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[7]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[7]~input .bus_hold = "false";
+defparam \tx_digitalreset[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X76_Y129_N1
+stratixiv_io_ibuf \tx_digitalreset[8]~input (
+ .i(tx_digitalreset[8]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[8]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[8]~input .bus_hold = "false";
+defparam \tx_digitalreset[8]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X39_Y129_N1
+stratixiv_io_ibuf \tx_digitalreset[9]~input (
+ .i(tx_digitalreset[9]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[9]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[9]~input .bus_hold = "false";
+defparam \tx_digitalreset[9]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y47_N94
+stratixiv_io_ibuf \tx_digitalreset[10]~input (
+ .i(tx_digitalreset[10]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[10]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[10]~input .bus_hold = "false";
+defparam \tx_digitalreset[10]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X104_Y129_N63
+stratixiv_io_ibuf \tx_digitalreset[11]~input (
+ .i(tx_digitalreset[11]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[11]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[11]~input .bus_hold = "false";
+defparam \tx_digitalreset[11]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X164_Y0_N94
+stratixiv_io_ibuf \tx_digitalreset[12]~input (
+ .i(tx_digitalreset[12]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[12]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[12]~input .bus_hold = "false";
+defparam \tx_digitalreset[12]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y109_N1
+stratixiv_io_ibuf \tx_digitalreset[13]~input (
+ .i(tx_digitalreset[13]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[13]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[13]~input .bus_hold = "false";
+defparam \tx_digitalreset[13]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X135_Y129_N94
+stratixiv_io_ibuf \tx_digitalreset[14]~input (
+ .i(tx_digitalreset[14]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[14]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[14]~input .bus_hold = "false";
+defparam \tx_digitalreset[14]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y80_N1
+stratixiv_io_ibuf \tx_digitalreset[15]~input (
+ .i(tx_digitalreset[15]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[15]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[15]~input .bus_hold = "false";
+defparam \tx_digitalreset[15]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y54_N94
+stratixiv_io_ibuf \tx_digitalreset[16]~input (
+ .i(tx_digitalreset[16]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[16]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[16]~input .bus_hold = "false";
+defparam \tx_digitalreset[16]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y59_N32
+stratixiv_io_ibuf \tx_digitalreset[17]~input (
+ .i(tx_digitalreset[17]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[17]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[17]~input .bus_hold = "false";
+defparam \tx_digitalreset[17]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y44_N63
+stratixiv_io_ibuf \tx_digitalreset[18]~input (
+ .i(tx_digitalreset[18]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[18]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[18]~input .bus_hold = "false";
+defparam \tx_digitalreset[18]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X153_Y129_N63
+stratixiv_io_ibuf \tx_digitalreset[19]~input (
+ .i(tx_digitalreset[19]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[19]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[19]~input .bus_hold = "false";
+defparam \tx_digitalreset[19]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X84_Y129_N32
+stratixiv_io_ibuf \tx_digitalreset[20]~input (
+ .i(tx_digitalreset[20]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[20]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[20]~input .bus_hold = "false";
+defparam \tx_digitalreset[20]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y98_N32
+stratixiv_io_ibuf \tx_digitalreset[21]~input (
+ .i(tx_digitalreset[21]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[21]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[21]~input .bus_hold = "false";
+defparam \tx_digitalreset[21]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y76_N63
+stratixiv_io_ibuf \tx_digitalreset[22]~input (
+ .i(tx_digitalreset[22]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[22]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[22]~input .bus_hold = "false";
+defparam \tx_digitalreset[22]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X173_Y129_N63
+stratixiv_io_ibuf \tx_digitalreset[23]~input (
+ .i(tx_digitalreset[23]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[23]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[23]~input .bus_hold = "false";
+defparam \tx_digitalreset[23]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X117_Y129_N32
+stratixiv_io_ibuf \tx_digitalreset[24]~input (
+ .i(tx_digitalreset[24]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[24]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[24]~input .bus_hold = "false";
+defparam \tx_digitalreset[24]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X104_Y0_N32
+stratixiv_io_ibuf \tx_digitalreset[25]~input (
+ .i(tx_digitalreset[25]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[25]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[25]~input .bus_hold = "false";
+defparam \tx_digitalreset[25]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y74_N94
+stratixiv_io_ibuf \tx_digitalreset[26]~input (
+ .i(tx_digitalreset[26]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[26]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[26]~input .bus_hold = "false";
+defparam \tx_digitalreset[26]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y84_N32
+stratixiv_io_ibuf \tx_digitalreset[27]~input (
+ .i(tx_digitalreset[27]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[27]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[27]~input .bus_hold = "false";
+defparam \tx_digitalreset[27]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X84_Y129_N63
+stratixiv_io_ibuf \tx_digitalreset[28]~input (
+ .i(tx_digitalreset[28]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[28]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[28]~input .bus_hold = "false";
+defparam \tx_digitalreset[28]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y32_N1
+stratixiv_io_ibuf \tx_digitalreset[29]~input (
+ .i(tx_digitalreset[29]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[29]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[29]~input .bus_hold = "false";
+defparam \tx_digitalreset[29]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X145_Y129_N63
+stratixiv_io_ibuf \tx_digitalreset[30]~input (
+ .i(tx_digitalreset[30]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[30]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[30]~input .bus_hold = "false";
+defparam \tx_digitalreset[30]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y81_N94
+stratixiv_io_ibuf \tx_digitalreset[31]~input (
+ .i(tx_digitalreset[31]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\tx_digitalreset[31]~input_o ));
+// synopsys translate_off
+defparam \tx_digitalreset[31]~input .bus_hold = "false";
+defparam \tx_digitalreset[31]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X137_Y129_N63
+stratixiv_io_ibuf \rx_digitalreset[0]~input (
+ .i(rx_digitalreset[0]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[0]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[0]~input .bus_hold = "false";
+defparam \rx_digitalreset[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y102_N94
+stratixiv_io_ibuf \rx_digitalreset[1]~input (
+ .i(rx_digitalreset[1]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[1]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[1]~input .bus_hold = "false";
+defparam \rx_digitalreset[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X139_Y129_N63
+stratixiv_io_ibuf \rx_digitalreset[2]~input (
+ .i(rx_digitalreset[2]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[2]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[2]~input .bus_hold = "false";
+defparam \rx_digitalreset[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X17_Y129_N94
+stratixiv_io_ibuf \rx_digitalreset[3]~input (
+ .i(rx_digitalreset[3]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[3]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[3]~input .bus_hold = "false";
+defparam \rx_digitalreset[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y113_N32
+stratixiv_io_ibuf \rx_digitalreset[4]~input (
+ .i(rx_digitalreset[4]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[4]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[4]~input .bus_hold = "false";
+defparam \rx_digitalreset[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y31_N1
+stratixiv_io_ibuf \rx_digitalreset[5]~input (
+ .i(rx_digitalreset[5]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[5]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[5]~input .bus_hold = "false";
+defparam \rx_digitalreset[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X78_Y129_N94
+stratixiv_io_ibuf \rx_digitalreset[6]~input (
+ .i(rx_digitalreset[6]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[6]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[6]~input .bus_hold = "false";
+defparam \rx_digitalreset[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X162_Y0_N63
+stratixiv_io_ibuf \rx_digitalreset[7]~input (
+ .i(rx_digitalreset[7]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[7]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[7]~input .bus_hold = "false";
+defparam \rx_digitalreset[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X132_Y0_N1
+stratixiv_io_ibuf \rx_digitalreset[8]~input (
+ .i(rx_digitalreset[8]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[8]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[8]~input .bus_hold = "false";
+defparam \rx_digitalreset[8]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X132_Y129_N94
+stratixiv_io_ibuf \rx_digitalreset[9]~input (
+ .i(rx_digitalreset[9]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[9]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[9]~input .bus_hold = "false";
+defparam \rx_digitalreset[9]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X153_Y0_N32
+stratixiv_io_ibuf \rx_digitalreset[10]~input (
+ .i(rx_digitalreset[10]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[10]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[10]~input .bus_hold = "false";
+defparam \rx_digitalreset[10]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y110_N63
+stratixiv_io_ibuf \rx_digitalreset[11]~input (
+ .i(rx_digitalreset[11]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[11]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[11]~input .bus_hold = "false";
+defparam \rx_digitalreset[11]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y97_N32
+stratixiv_io_ibuf \rx_digitalreset[12]~input (
+ .i(rx_digitalreset[12]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[12]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[12]~input .bus_hold = "false";
+defparam \rx_digitalreset[12]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X25_Y129_N32
+stratixiv_io_ibuf \rx_digitalreset[13]~input (
+ .i(rx_digitalreset[13]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[13]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[13]~input .bus_hold = "false";
+defparam \rx_digitalreset[13]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y45_N63
+stratixiv_io_ibuf \rx_digitalreset[14]~input (
+ .i(rx_digitalreset[14]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[14]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[14]~input .bus_hold = "false";
+defparam \rx_digitalreset[14]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y107_N1
+stratixiv_io_ibuf \rx_digitalreset[15]~input (
+ .i(rx_digitalreset[15]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[15]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[15]~input .bus_hold = "false";
+defparam \rx_digitalreset[15]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y59_N94
+stratixiv_io_ibuf \rx_digitalreset[16]~input (
+ .i(rx_digitalreset[16]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[16]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[16]~input .bus_hold = "false";
+defparam \rx_digitalreset[16]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y57_N94
+stratixiv_io_ibuf \rx_digitalreset[17]~input (
+ .i(rx_digitalreset[17]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[17]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[17]~input .bus_hold = "false";
+defparam \rx_digitalreset[17]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X122_Y0_N94
+stratixiv_io_ibuf \rx_digitalreset[18]~input (
+ .i(rx_digitalreset[18]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[18]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[18]~input .bus_hold = "false";
+defparam \rx_digitalreset[18]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y22_N94
+stratixiv_io_ibuf \rx_digitalreset[19]~input (
+ .i(rx_digitalreset[19]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[19]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[19]~input .bus_hold = "false";
+defparam \rx_digitalreset[19]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X68_Y0_N63
+stratixiv_io_ibuf \rx_digitalreset[20]~input (
+ .i(rx_digitalreset[20]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[20]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[20]~input .bus_hold = "false";
+defparam \rx_digitalreset[20]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X125_Y0_N63
+stratixiv_io_ibuf \rx_digitalreset[21]~input (
+ .i(rx_digitalreset[21]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[21]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[21]~input .bus_hold = "false";
+defparam \rx_digitalreset[21]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X173_Y0_N94
+stratixiv_io_ibuf \rx_digitalreset[22]~input (
+ .i(rx_digitalreset[22]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[22]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[22]~input .bus_hold = "false";
+defparam \rx_digitalreset[22]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y107_N1
+stratixiv_io_ibuf \rx_digitalreset[23]~input (
+ .i(rx_digitalreset[23]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[23]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[23]~input .bus_hold = "false";
+defparam \rx_digitalreset[23]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X59_Y129_N63
+stratixiv_io_ibuf \rx_digitalreset[24]~input (
+ .i(rx_digitalreset[24]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[24]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[24]~input .bus_hold = "false";
+defparam \rx_digitalreset[24]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X62_Y129_N32
+stratixiv_io_ibuf \rx_digitalreset[25]~input (
+ .i(rx_digitalreset[25]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[25]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[25]~input .bus_hold = "false";
+defparam \rx_digitalreset[25]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y40_N63
+stratixiv_io_ibuf \rx_digitalreset[26]~input (
+ .i(rx_digitalreset[26]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[26]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[26]~input .bus_hold = "false";
+defparam \rx_digitalreset[26]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y72_N63
+stratixiv_io_ibuf \rx_digitalreset[27]~input (
+ .i(rx_digitalreset[27]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[27]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[27]~input .bus_hold = "false";
+defparam \rx_digitalreset[27]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y74_N1
+stratixiv_io_ibuf \rx_digitalreset[28]~input (
+ .i(rx_digitalreset[28]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[28]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[28]~input .bus_hold = "false";
+defparam \rx_digitalreset[28]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X80_Y0_N1
+stratixiv_io_ibuf \rx_digitalreset[29]~input (
+ .i(rx_digitalreset[29]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[29]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[29]~input .bus_hold = "false";
+defparam \rx_digitalreset[29]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X119_Y0_N63
+stratixiv_io_ibuf \rx_digitalreset[30]~input (
+ .i(rx_digitalreset[30]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[30]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[30]~input .bus_hold = "false";
+defparam \rx_digitalreset[30]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y102_N32
+stratixiv_io_ibuf \rx_digitalreset[31]~input (
+ .i(rx_digitalreset[31]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_digitalreset[31]~input_o ));
+// synopsys translate_off
+defparam \rx_digitalreset[31]~input .bus_hold = "false";
+defparam \rx_digitalreset[31]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y78_N1
+stratixiv_io_ibuf \rx_locktorefclk[4]~input (
+ .i(rx_locktorefclk[4]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[4]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[4]~input .bus_hold = "false";
+defparam \rx_locktorefclk[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X155_Y129_N94
+stratixiv_io_ibuf \rx_locktorefclk[5]~input (
+ .i(rx_locktorefclk[5]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[5]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[5]~input .bus_hold = "false";
+defparam \rx_locktorefclk[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X133_Y0_N94
+stratixiv_io_ibuf \rx_locktorefclk[6]~input (
+ .i(rx_locktorefclk[6]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[6]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[6]~input .bus_hold = "false";
+defparam \rx_locktorefclk[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X157_Y129_N94
+stratixiv_io_ibuf \rx_locktorefclk[7]~input (
+ .i(rx_locktorefclk[7]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[7]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[7]~input .bus_hold = "false";
+defparam \rx_locktorefclk[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y60_N1
+stratixiv_io_ibuf \rx_locktorefclk[8]~input (
+ .i(rx_locktorefclk[8]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[8]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[8]~input .bus_hold = "false";
+defparam \rx_locktorefclk[8]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X76_Y0_N1
+stratixiv_io_ibuf \rx_locktorefclk[9]~input (
+ .i(rx_locktorefclk[9]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[9]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[9]~input .bus_hold = "false";
+defparam \rx_locktorefclk[9]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X148_Y129_N94
+stratixiv_io_ibuf \rx_locktorefclk[10]~input (
+ .i(rx_locktorefclk[10]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[10]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[10]~input .bus_hold = "false";
+defparam \rx_locktorefclk[10]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X117_Y0_N32
+stratixiv_io_ibuf \rx_locktorefclk[11]~input (
+ .i(rx_locktorefclk[11]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[11]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[11]~input .bus_hold = "false";
+defparam \rx_locktorefclk[11]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y52_N1
+stratixiv_io_ibuf \rx_locktorefclk[12]~input (
+ .i(rx_locktorefclk[12]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[12]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[12]~input .bus_hold = "false";
+defparam \rx_locktorefclk[12]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X159_Y0_N1
+stratixiv_io_ibuf \rx_locktorefclk[13]~input (
+ .i(rx_locktorefclk[13]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[13]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[13]~input .bus_hold = "false";
+defparam \rx_locktorefclk[13]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y59_N63
+stratixiv_io_ibuf \rx_locktorefclk[14]~input (
+ .i(rx_locktorefclk[14]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[14]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[14]~input .bus_hold = "false";
+defparam \rx_locktorefclk[14]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X167_Y129_N63
+stratixiv_io_ibuf \rx_locktorefclk[15]~input (
+ .i(rx_locktorefclk[15]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[15]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[15]~input .bus_hold = "false";
+defparam \rx_locktorefclk[15]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X133_Y0_N1
+stratixiv_io_ibuf \rx_locktorefclk[16]~input (
+ .i(rx_locktorefclk[16]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[16]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[16]~input .bus_hold = "false";
+defparam \rx_locktorefclk[16]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y26_N1
+stratixiv_io_ibuf \rx_locktorefclk[17]~input (
+ .i(rx_locktorefclk[17]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[17]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[17]~input .bus_hold = "false";
+defparam \rx_locktorefclk[17]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y96_N32
+stratixiv_io_ibuf \rx_locktorefclk[18]~input (
+ .i(rx_locktorefclk[18]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[18]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[18]~input .bus_hold = "false";
+defparam \rx_locktorefclk[18]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y38_N94
+stratixiv_io_ibuf \rx_locktorefclk[19]~input (
+ .i(rx_locktorefclk[19]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[19]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[19]~input .bus_hold = "false";
+defparam \rx_locktorefclk[19]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y81_N94
+stratixiv_io_ibuf \rx_locktorefclk[20]~input (
+ .i(rx_locktorefclk[20]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[20]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[20]~input .bus_hold = "false";
+defparam \rx_locktorefclk[20]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X60_Y129_N1
+stratixiv_io_ibuf \rx_locktorefclk[21]~input (
+ .i(rx_locktorefclk[21]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[21]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[21]~input .bus_hold = "false";
+defparam \rx_locktorefclk[21]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y33_N1
+stratixiv_io_ibuf \rx_locktorefclk[22]~input (
+ .i(rx_locktorefclk[22]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[22]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[22]~input .bus_hold = "false";
+defparam \rx_locktorefclk[22]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y78_N94
+stratixiv_io_ibuf \rx_locktorefclk[23]~input (
+ .i(rx_locktorefclk[23]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[23]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[23]~input .bus_hold = "false";
+defparam \rx_locktorefclk[23]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X122_Y129_N1
+stratixiv_io_ibuf \rx_locktorefclk[24]~input (
+ .i(rx_locktorefclk[24]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[24]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[24]~input .bus_hold = "false";
+defparam \rx_locktorefclk[24]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y83_N32
+stratixiv_io_ibuf \rx_locktorefclk[25]~input (
+ .i(rx_locktorefclk[25]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[25]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[25]~input .bus_hold = "false";
+defparam \rx_locktorefclk[25]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y24_N63
+stratixiv_io_ibuf \rx_locktorefclk[26]~input (
+ .i(rx_locktorefclk[26]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[26]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[26]~input .bus_hold = "false";
+defparam \rx_locktorefclk[26]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X145_Y0_N1
+stratixiv_io_ibuf \rx_locktorefclk[27]~input (
+ .i(rx_locktorefclk[27]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[27]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[27]~input .bus_hold = "false";
+defparam \rx_locktorefclk[27]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y69_N32
+stratixiv_io_ibuf \rx_locktorefclk[28]~input (
+ .i(rx_locktorefclk[28]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[28]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[28]~input .bus_hold = "false";
+defparam \rx_locktorefclk[28]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y110_N32
+stratixiv_io_ibuf \rx_locktorefclk[29]~input (
+ .i(rx_locktorefclk[29]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[29]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[29]~input .bus_hold = "false";
+defparam \rx_locktorefclk[29]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y35_N63
+stratixiv_io_ibuf \rx_locktorefclk[30]~input (
+ .i(rx_locktorefclk[30]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[30]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[30]~input .bus_hold = "false";
+defparam \rx_locktorefclk[30]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y68_N1
+stratixiv_io_ibuf \rx_locktorefclk[31]~input (
+ .i(rx_locktorefclk[31]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_locktorefclk[31]~input_o ));
+// synopsys translate_off
+defparam \rx_locktorefclk[31]~input .bus_hold = "false";
+defparam \rx_locktorefclk[31]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X164_Y129_N1
+stratixiv_io_ibuf \rst~input (
+ .i(rst),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rst~input_o ));
+// synopsys translate_off
+defparam \rst~input .bus_hold = "false";
+defparam \rst~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y80_N94
+stratixiv_io_ibuf \clk~input (
+ .i(clk),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\clk~input_o ));
+// synopsys translate_off
+defparam \clk~input .bus_hold = "false";
+defparam \clk~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X64_Y129_N94
+stratixiv_io_ibuf \ch_ctrl_address[0]~input (
+ .i(ch_ctrl_address[0]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_address[0]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_address[0]~input .bus_hold = "false";
+defparam \ch_ctrl_address[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y33_N63
+stratixiv_io_ibuf \ch_ctrl_address[1]~input (
+ .i(ch_ctrl_address[1]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_address[1]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_address[1]~input .bus_hold = "false";
+defparam \ch_ctrl_address[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X157_Y129_N32
+stratixiv_io_ibuf \ch_ctrl_address[2]~input (
+ .i(ch_ctrl_address[2]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_address[2]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_address[2]~input .bus_hold = "false";
+defparam \ch_ctrl_address[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y112_N1
+stratixiv_io_ibuf \ch_ctrl_read~input (
+ .i(ch_ctrl_read),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_read~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_read~input .bus_hold = "false";
+defparam \ch_ctrl_read~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X113_Y0_N1
+stratixiv_io_ibuf \ch_ctrl_write~input (
+ .i(ch_ctrl_write),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_write~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_write~input .bus_hold = "false";
+defparam \ch_ctrl_write~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X169_Y0_N32
+stratixiv_io_ibuf \ch_ctrl_writedata[0]~input (
+ .i(ch_ctrl_writedata[0]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[0]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[0]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X80_Y129_N94
+stratixiv_io_ibuf \ch_ctrl_writedata[1]~input (
+ .i(ch_ctrl_writedata[1]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[1]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[1]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y68_N32
+stratixiv_io_ibuf \ch_ctrl_writedata[2]~input (
+ .i(ch_ctrl_writedata[2]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[2]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[2]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y57_N63
+stratixiv_io_ibuf \ch_ctrl_writedata[3]~input (
+ .i(ch_ctrl_writedata[3]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[3]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[3]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X14_Y129_N1
+stratixiv_io_ibuf \ch_ctrl_writedata[4]~input (
+ .i(ch_ctrl_writedata[4]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[4]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[4]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y109_N63
+stratixiv_io_ibuf \ch_ctrl_writedata[5]~input (
+ .i(ch_ctrl_writedata[5]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[5]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[5]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X22_Y129_N32
+stratixiv_io_ibuf \ch_ctrl_writedata[6]~input (
+ .i(ch_ctrl_writedata[6]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[6]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[6]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X27_Y129_N1
+stratixiv_io_ibuf \ch_ctrl_writedata[7]~input (
+ .i(ch_ctrl_writedata[7]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[7]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[7]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y26_N32
+stratixiv_io_ibuf \ch_ctrl_writedata[8]~input (
+ .i(ch_ctrl_writedata[8]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[8]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[8]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[8]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X164_Y129_N32
+stratixiv_io_ibuf \ch_ctrl_writedata[9]~input (
+ .i(ch_ctrl_writedata[9]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[9]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[9]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[9]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y31_N32
+stratixiv_io_ibuf \ch_ctrl_writedata[10]~input (
+ .i(ch_ctrl_writedata[10]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[10]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[10]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[10]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y113_N94
+stratixiv_io_ibuf \ch_ctrl_writedata[11]~input (
+ .i(ch_ctrl_writedata[11]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[11]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[11]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[11]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y71_N94
+stratixiv_io_ibuf \ch_ctrl_writedata[12]~input (
+ .i(ch_ctrl_writedata[12]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[12]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[12]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[12]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y37_N1
+stratixiv_io_ibuf \ch_ctrl_writedata[13]~input (
+ .i(ch_ctrl_writedata[13]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[13]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[13]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[13]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y38_N32
+stratixiv_io_ibuf \ch_ctrl_writedata[14]~input (
+ .i(ch_ctrl_writedata[14]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[14]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[14]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[14]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X122_Y129_N32
+stratixiv_io_ibuf \ch_ctrl_writedata[15]~input (
+ .i(ch_ctrl_writedata[15]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[15]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[15]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[15]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X132_Y0_N63
+stratixiv_io_ibuf \ch_ctrl_writedata[16]~input (
+ .i(ch_ctrl_writedata[16]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[16]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[16]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[16]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X68_Y0_N32
+stratixiv_io_ibuf \ch_ctrl_writedata[17]~input (
+ .i(ch_ctrl_writedata[17]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[17]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[17]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[17]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y54_N63
+stratixiv_io_ibuf \ch_ctrl_writedata[18]~input (
+ .i(ch_ctrl_writedata[18]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[18]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[18]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[18]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X33_Y129_N63
+stratixiv_io_ibuf \ch_ctrl_writedata[19]~input (
+ .i(ch_ctrl_writedata[19]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[19]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[19]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[19]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X57_Y129_N1
+stratixiv_io_ibuf \ch_ctrl_writedata[20]~input (
+ .i(ch_ctrl_writedata[20]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[20]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[20]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[20]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y28_N32
+stratixiv_io_ibuf \ch_ctrl_writedata[21]~input (
+ .i(ch_ctrl_writedata[21]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[21]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[21]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[21]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X162_Y0_N1
+stratixiv_io_ibuf \ch_ctrl_writedata[22]~input (
+ .i(ch_ctrl_writedata[22]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[22]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[22]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[22]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X59_Y129_N32
+stratixiv_io_ibuf \ch_ctrl_writedata[23]~input (
+ .i(ch_ctrl_writedata[23]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[23]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[23]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[23]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y109_N1
+stratixiv_io_ibuf \ch_ctrl_writedata[24]~input (
+ .i(ch_ctrl_writedata[24]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[24]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[24]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[24]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y110_N94
+stratixiv_io_ibuf \ch_ctrl_writedata[25]~input (
+ .i(ch_ctrl_writedata[25]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[25]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[25]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[25]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y104_N63
+stratixiv_io_ibuf \ch_ctrl_writedata[26]~input (
+ .i(ch_ctrl_writedata[26]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[26]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[26]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[26]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X30_Y129_N32
+stratixiv_io_ibuf \ch_ctrl_writedata[27]~input (
+ .i(ch_ctrl_writedata[27]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[27]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[27]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[27]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y21_N94
+stratixiv_io_ibuf \ch_ctrl_writedata[28]~input (
+ .i(ch_ctrl_writedata[28]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[28]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[28]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[28]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X152_Y0_N94
+stratixiv_io_ibuf \ch_ctrl_writedata[29]~input (
+ .i(ch_ctrl_writedata[29]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[29]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[29]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[29]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X14_Y129_N32
+stratixiv_io_ibuf \ch_ctrl_writedata[30]~input (
+ .i(ch_ctrl_writedata[30]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[30]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[30]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[30]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y110_N32
+stratixiv_io_ibuf \ch_ctrl_writedata[31]~input (
+ .i(ch_ctrl_writedata[31]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\ch_ctrl_writedata[31]~input_o ));
+// synopsys translate_off
+defparam \ch_ctrl_writedata[31]~input .bus_hold = "false";
+defparam \ch_ctrl_writedata[31]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X27_Y129_N94
+stratixiv_io_ibuf \aeq_to_gxb[0]~input (
+ .i(aeq_to_gxb[0]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[0]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[0]~input .bus_hold = "false";
+defparam \aeq_to_gxb[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y22_N32
+stratixiv_io_ibuf \aeq_to_gxb[1]~input (
+ .i(aeq_to_gxb[1]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[1]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[1]~input .bus_hold = "false";
+defparam \aeq_to_gxb[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X104_Y0_N1
+stratixiv_io_ibuf \aeq_to_gxb[2]~input (
+ .i(aeq_to_gxb[2]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[2]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[2]~input .bus_hold = "false";
+defparam \aeq_to_gxb[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y102_N94
+stratixiv_io_ibuf \aeq_to_gxb[3]~input (
+ .i(aeq_to_gxb[3]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[3]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[3]~input .bus_hold = "false";
+defparam \aeq_to_gxb[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y78_N32
+stratixiv_io_ibuf \aeq_to_gxb[4]~input (
+ .i(aeq_to_gxb[4]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[4]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[4]~input .bus_hold = "false";
+defparam \aeq_to_gxb[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X54_Y129_N32
+stratixiv_io_ibuf \aeq_to_gxb[5]~input (
+ .i(aeq_to_gxb[5]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[5]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[5]~input .bus_hold = "false";
+defparam \aeq_to_gxb[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X150_Y0_N63
+stratixiv_io_ibuf \aeq_to_gxb[6]~input (
+ .i(aeq_to_gxb[6]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[6]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[6]~input .bus_hold = "false";
+defparam \aeq_to_gxb[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X78_Y129_N32
+stratixiv_io_ibuf \aeq_to_gxb[7]~input (
+ .i(aeq_to_gxb[7]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[7]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[7]~input .bus_hold = "false";
+defparam \aeq_to_gxb[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y76_N1
+stratixiv_io_ibuf \aeq_to_gxb[8]~input (
+ .i(aeq_to_gxb[8]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[8]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[8]~input .bus_hold = "false";
+defparam \aeq_to_gxb[8]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X110_Y129_N1
+stratixiv_io_ibuf \aeq_to_gxb[9]~input (
+ .i(aeq_to_gxb[9]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[9]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[9]~input .bus_hold = "false";
+defparam \aeq_to_gxb[9]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X152_Y129_N94
+stratixiv_io_ibuf \aeq_to_gxb[10]~input (
+ .i(aeq_to_gxb[10]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[10]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[10]~input .bus_hold = "false";
+defparam \aeq_to_gxb[10]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X78_Y129_N1
+stratixiv_io_ibuf \aeq_to_gxb[11]~input (
+ .i(aeq_to_gxb[11]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[11]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[11]~input .bus_hold = "false";
+defparam \aeq_to_gxb[11]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y115_N1
+stratixiv_io_ibuf \aeq_to_gxb[12]~input (
+ .i(aeq_to_gxb[12]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[12]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[12]~input .bus_hold = "false";
+defparam \aeq_to_gxb[12]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y109_N32
+stratixiv_io_ibuf \aeq_to_gxb[13]~input (
+ .i(aeq_to_gxb[13]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[13]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[13]~input .bus_hold = "false";
+defparam \aeq_to_gxb[13]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X142_Y0_N63
+stratixiv_io_ibuf \aeq_to_gxb[14]~input (
+ .i(aeq_to_gxb[14]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[14]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[14]~input .bus_hold = "false";
+defparam \aeq_to_gxb[14]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y59_N63
+stratixiv_io_ibuf \aeq_to_gxb[15]~input (
+ .i(aeq_to_gxb[15]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[15]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[15]~input .bus_hold = "false";
+defparam \aeq_to_gxb[15]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X108_Y129_N32
+stratixiv_io_ibuf \aeq_to_gxb[16]~input (
+ .i(aeq_to_gxb[16]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[16]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[16]~input .bus_hold = "false";
+defparam \aeq_to_gxb[16]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X150_Y0_N1
+stratixiv_io_ibuf \aeq_to_gxb[17]~input (
+ .i(aeq_to_gxb[17]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[17]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[17]~input .bus_hold = "false";
+defparam \aeq_to_gxb[17]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y28_N63
+stratixiv_io_ibuf \aeq_to_gxb[18]~input (
+ .i(aeq_to_gxb[18]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[18]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[18]~input .bus_hold = "false";
+defparam \aeq_to_gxb[18]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y57_N63
+stratixiv_io_ibuf \aeq_to_gxb[19]~input (
+ .i(aeq_to_gxb[19]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[19]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[19]~input .bus_hold = "false";
+defparam \aeq_to_gxb[19]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y104_N94
+stratixiv_io_ibuf \aeq_to_gxb[20]~input (
+ .i(aeq_to_gxb[20]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[20]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[20]~input .bus_hold = "false";
+defparam \aeq_to_gxb[20]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y110_N94
+stratixiv_io_ibuf \aeq_to_gxb[21]~input (
+ .i(aeq_to_gxb[21]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[21]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[21]~input .bus_hold = "false";
+defparam \aeq_to_gxb[21]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y84_N94
+stratixiv_io_ibuf \aeq_to_gxb[22]~input (
+ .i(aeq_to_gxb[22]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[22]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[22]~input .bus_hold = "false";
+defparam \aeq_to_gxb[22]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y13_N1
+stratixiv_io_ibuf \aeq_to_gxb[23]~input (
+ .i(aeq_to_gxb[23]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[23]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[23]~input .bus_hold = "false";
+defparam \aeq_to_gxb[23]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X84_Y0_N94
+stratixiv_io_ibuf \aeq_to_gxb[24]~input (
+ .i(aeq_to_gxb[24]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[24]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[24]~input .bus_hold = "false";
+defparam \aeq_to_gxb[24]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X145_Y129_N1
+stratixiv_io_ibuf \aeq_to_gxb[25]~input (
+ .i(aeq_to_gxb[25]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[25]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[25]~input .bus_hold = "false";
+defparam \aeq_to_gxb[25]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X108_Y129_N63
+stratixiv_io_ibuf \aeq_to_gxb[26]~input (
+ .i(aeq_to_gxb[26]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[26]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[26]~input .bus_hold = "false";
+defparam \aeq_to_gxb[26]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y69_N1
+stratixiv_io_ibuf \aeq_to_gxb[27]~input (
+ .i(aeq_to_gxb[27]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[27]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[27]~input .bus_hold = "false";
+defparam \aeq_to_gxb[27]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y109_N94
+stratixiv_io_ibuf \aeq_to_gxb[28]~input (
+ .i(aeq_to_gxb[28]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[28]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[28]~input .bus_hold = "false";
+defparam \aeq_to_gxb[28]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X153_Y0_N94
+stratixiv_io_ibuf \aeq_to_gxb[29]~input (
+ .i(aeq_to_gxb[29]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[29]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[29]~input .bus_hold = "false";
+defparam \aeq_to_gxb[29]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y40_N1
+stratixiv_io_ibuf \aeq_to_gxb[30]~input (
+ .i(aeq_to_gxb[30]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[30]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[30]~input .bus_hold = "false";
+defparam \aeq_to_gxb[30]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y100_N1
+stratixiv_io_ibuf \aeq_to_gxb[31]~input (
+ .i(aeq_to_gxb[31]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[31]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[31]~input .bus_hold = "false";
+defparam \aeq_to_gxb[31]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y97_N32
+stratixiv_io_ibuf \aeq_to_gxb[32]~input (
+ .i(aeq_to_gxb[32]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[32]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[32]~input .bus_hold = "false";
+defparam \aeq_to_gxb[32]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X9_Y129_N94
+stratixiv_io_ibuf \aeq_to_gxb[33]~input (
+ .i(aeq_to_gxb[33]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[33]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[33]~input .bus_hold = "false";
+defparam \aeq_to_gxb[33]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y33_N32
+stratixiv_io_ibuf \aeq_to_gxb[34]~input (
+ .i(aeq_to_gxb[34]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[34]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[34]~input .bus_hold = "false";
+defparam \aeq_to_gxb[34]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X64_Y129_N1
+stratixiv_io_ibuf \aeq_to_gxb[35]~input (
+ .i(aeq_to_gxb[35]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[35]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[35]~input .bus_hold = "false";
+defparam \aeq_to_gxb[35]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y13_N32
+stratixiv_io_ibuf \aeq_to_gxb[36]~input (
+ .i(aeq_to_gxb[36]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[36]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[36]~input .bus_hold = "false";
+defparam \aeq_to_gxb[36]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y26_N63
+stratixiv_io_ibuf \aeq_to_gxb[37]~input (
+ .i(aeq_to_gxb[37]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[37]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[37]~input .bus_hold = "false";
+defparam \aeq_to_gxb[37]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X159_Y129_N94
+stratixiv_io_ibuf \aeq_to_gxb[38]~input (
+ .i(aeq_to_gxb[38]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[38]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[38]~input .bus_hold = "false";
+defparam \aeq_to_gxb[38]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X42_Y129_N32
+stratixiv_io_ibuf \aeq_to_gxb[39]~input (
+ .i(aeq_to_gxb[39]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[39]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[39]~input .bus_hold = "false";
+defparam \aeq_to_gxb[39]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y102_N1
+stratixiv_io_ibuf \aeq_to_gxb[40]~input (
+ .i(aeq_to_gxb[40]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[40]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[40]~input .bus_hold = "false";
+defparam \aeq_to_gxb[40]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X110_Y129_N32
+stratixiv_io_ibuf \aeq_to_gxb[41]~input (
+ .i(aeq_to_gxb[41]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[41]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[41]~input .bus_hold = "false";
+defparam \aeq_to_gxb[41]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y32_N32
+stratixiv_io_ibuf \aeq_to_gxb[42]~input (
+ .i(aeq_to_gxb[42]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[42]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[42]~input .bus_hold = "false";
+defparam \aeq_to_gxb[42]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X19_Y129_N63
+stratixiv_io_ibuf \aeq_to_gxb[43]~input (
+ .i(aeq_to_gxb[43]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[43]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[43]~input .bus_hold = "false";
+defparam \aeq_to_gxb[43]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X167_Y0_N94
+stratixiv_io_ibuf \aeq_to_gxb[44]~input (
+ .i(aeq_to_gxb[44]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[44]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[44]~input .bus_hold = "false";
+defparam \aeq_to_gxb[44]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X119_Y129_N1
+stratixiv_io_ibuf \aeq_to_gxb[45]~input (
+ .i(aeq_to_gxb[45]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[45]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[45]~input .bus_hold = "false";
+defparam \aeq_to_gxb[45]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X85_Y129_N63
+stratixiv_io_ibuf \aeq_to_gxb[46]~input (
+ .i(aeq_to_gxb[46]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[46]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[46]~input .bus_hold = "false";
+defparam \aeq_to_gxb[46]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X33_Y129_N94
+stratixiv_io_ibuf \aeq_to_gxb[47]~input (
+ .i(aeq_to_gxb[47]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[47]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[47]~input .bus_hold = "false";
+defparam \aeq_to_gxb[47]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y71_N32
+stratixiv_io_ibuf \aeq_to_gxb[48]~input (
+ .i(aeq_to_gxb[48]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[48]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[48]~input .bus_hold = "false";
+defparam \aeq_to_gxb[48]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X108_Y0_N32
+stratixiv_io_ibuf \aeq_to_gxb[49]~input (
+ .i(aeq_to_gxb[49]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[49]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[49]~input .bus_hold = "false";
+defparam \aeq_to_gxb[49]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y97_N1
+stratixiv_io_ibuf \aeq_to_gxb[50]~input (
+ .i(aeq_to_gxb[50]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[50]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[50]~input .bus_hold = "false";
+defparam \aeq_to_gxb[50]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X173_Y129_N32
+stratixiv_io_ibuf \aeq_to_gxb[51]~input (
+ .i(aeq_to_gxb[51]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[51]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[51]~input .bus_hold = "false";
+defparam \aeq_to_gxb[51]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X38_Y129_N1
+stratixiv_io_ibuf \aeq_to_gxb[52]~input (
+ .i(aeq_to_gxb[52]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[52]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[52]~input .bus_hold = "false";
+defparam \aeq_to_gxb[52]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y96_N1
+stratixiv_io_ibuf \aeq_to_gxb[53]~input (
+ .i(aeq_to_gxb[53]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[53]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[53]~input .bus_hold = "false";
+defparam \aeq_to_gxb[53]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X47_Y129_N94
+stratixiv_io_ibuf \aeq_to_gxb[54]~input (
+ .i(aeq_to_gxb[54]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[54]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[54]~input .bus_hold = "false";
+defparam \aeq_to_gxb[54]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X57_Y129_N94
+stratixiv_io_ibuf \aeq_to_gxb[55]~input (
+ .i(aeq_to_gxb[55]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[55]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[55]~input .bus_hold = "false";
+defparam \aeq_to_gxb[55]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y60_N32
+stratixiv_io_ibuf \aeq_to_gxb[56]~input (
+ .i(aeq_to_gxb[56]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[56]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[56]~input .bus_hold = "false";
+defparam \aeq_to_gxb[56]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X117_Y129_N63
+stratixiv_io_ibuf \aeq_to_gxb[57]~input (
+ .i(aeq_to_gxb[57]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[57]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[57]~input .bus_hold = "false";
+defparam \aeq_to_gxb[57]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y76_N1
+stratixiv_io_ibuf \aeq_to_gxb[58]~input (
+ .i(aeq_to_gxb[58]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[58]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[58]~input .bus_hold = "false";
+defparam \aeq_to_gxb[58]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X110_Y129_N63
+stratixiv_io_ibuf \aeq_to_gxb[59]~input (
+ .i(aeq_to_gxb[59]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[59]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[59]~input .bus_hold = "false";
+defparam \aeq_to_gxb[59]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X162_Y129_N1
+stratixiv_io_ibuf \aeq_to_gxb[60]~input (
+ .i(aeq_to_gxb[60]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[60]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[60]~input .bus_hold = "false";
+defparam \aeq_to_gxb[60]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X22_Y129_N1
+stratixiv_io_ibuf \aeq_to_gxb[61]~input (
+ .i(aeq_to_gxb[61]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[61]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[61]~input .bus_hold = "false";
+defparam \aeq_to_gxb[61]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X113_Y0_N94
+stratixiv_io_ibuf \aeq_to_gxb[62]~input (
+ .i(aeq_to_gxb[62]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[62]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[62]~input .bus_hold = "false";
+defparam \aeq_to_gxb[62]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X155_Y129_N63
+stratixiv_io_ibuf \aeq_to_gxb[63]~input (
+ .i(aeq_to_gxb[63]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[63]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[63]~input .bus_hold = "false";
+defparam \aeq_to_gxb[63]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X39_Y129_N63
+stratixiv_io_ibuf \aeq_to_gxb[64]~input (
+ .i(aeq_to_gxb[64]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[64]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[64]~input .bus_hold = "false";
+defparam \aeq_to_gxb[64]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y38_N63
+stratixiv_io_ibuf \aeq_to_gxb[65]~input (
+ .i(aeq_to_gxb[65]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[65]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[65]~input .bus_hold = "false";
+defparam \aeq_to_gxb[65]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X31_Y129_N63
+stratixiv_io_ibuf \aeq_to_gxb[66]~input (
+ .i(aeq_to_gxb[66]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[66]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[66]~input .bus_hold = "false";
+defparam \aeq_to_gxb[66]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y37_N94
+stratixiv_io_ibuf \aeq_to_gxb[67]~input (
+ .i(aeq_to_gxb[67]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[67]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[67]~input .bus_hold = "false";
+defparam \aeq_to_gxb[67]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y109_N63
+stratixiv_io_ibuf \aeq_to_gxb[68]~input (
+ .i(aeq_to_gxb[68]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[68]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[68]~input .bus_hold = "false";
+defparam \aeq_to_gxb[68]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X155_Y0_N1
+stratixiv_io_ibuf \aeq_to_gxb[69]~input (
+ .i(aeq_to_gxb[69]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[69]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[69]~input .bus_hold = "false";
+defparam \aeq_to_gxb[69]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X150_Y129_N32
+stratixiv_io_ibuf \aeq_to_gxb[70]~input (
+ .i(aeq_to_gxb[70]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[70]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[70]~input .bus_hold = "false";
+defparam \aeq_to_gxb[70]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X148_Y129_N63
+stratixiv_io_ibuf \aeq_to_gxb[71]~input (
+ .i(aeq_to_gxb[71]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[71]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[71]~input .bus_hold = "false";
+defparam \aeq_to_gxb[71]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X39_Y129_N32
+stratixiv_io_ibuf \aeq_to_gxb[72]~input (
+ .i(aeq_to_gxb[72]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[72]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[72]~input .bus_hold = "false";
+defparam \aeq_to_gxb[72]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y47_N32
+stratixiv_io_ibuf \aeq_to_gxb[73]~input (
+ .i(aeq_to_gxb[73]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[73]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[73]~input .bus_hold = "false";
+defparam \aeq_to_gxb[73]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X9_Y129_N1
+stratixiv_io_ibuf \aeq_to_gxb[74]~input (
+ .i(aeq_to_gxb[74]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[74]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[74]~input .bus_hold = "false";
+defparam \aeq_to_gxb[74]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y72_N32
+stratixiv_io_ibuf \aeq_to_gxb[75]~input (
+ .i(aeq_to_gxb[75]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[75]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[75]~input .bus_hold = "false";
+defparam \aeq_to_gxb[75]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X31_Y129_N32
+stratixiv_io_ibuf \aeq_to_gxb[76]~input (
+ .i(aeq_to_gxb[76]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[76]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[76]~input .bus_hold = "false";
+defparam \aeq_to_gxb[76]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X117_Y0_N94
+stratixiv_io_ibuf \aeq_to_gxb[77]~input (
+ .i(aeq_to_gxb[77]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[77]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[77]~input .bus_hold = "false";
+defparam \aeq_to_gxb[77]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y24_N1
+stratixiv_io_ibuf \aeq_to_gxb[78]~input (
+ .i(aeq_to_gxb[78]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[78]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[78]~input .bus_hold = "false";
+defparam \aeq_to_gxb[78]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X60_Y129_N32
+stratixiv_io_ibuf \aeq_to_gxb[79]~input (
+ .i(aeq_to_gxb[79]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[79]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[79]~input .bus_hold = "false";
+defparam \aeq_to_gxb[79]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X62_Y129_N94
+stratixiv_io_ibuf \aeq_to_gxb[80]~input (
+ .i(aeq_to_gxb[80]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[80]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[80]~input .bus_hold = "false";
+defparam \aeq_to_gxb[80]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X175_Y0_N32
+stratixiv_io_ibuf \aeq_to_gxb[81]~input (
+ .i(aeq_to_gxb[81]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[81]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[81]~input .bus_hold = "false";
+defparam \aeq_to_gxb[81]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X19_Y129_N32
+stratixiv_io_ibuf \aeq_to_gxb[82]~input (
+ .i(aeq_to_gxb[82]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[82]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[82]~input .bus_hold = "false";
+defparam \aeq_to_gxb[82]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X117_Y0_N63
+stratixiv_io_ibuf \aeq_to_gxb[83]~input (
+ .i(aeq_to_gxb[83]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[83]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[83]~input .bus_hold = "false";
+defparam \aeq_to_gxb[83]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X150_Y0_N32
+stratixiv_io_ibuf \aeq_to_gxb[84]~input (
+ .i(aeq_to_gxb[84]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[84]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[84]~input .bus_hold = "false";
+defparam \aeq_to_gxb[84]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y106_N1
+stratixiv_io_ibuf \aeq_to_gxb[85]~input (
+ .i(aeq_to_gxb[85]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[85]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[85]~input .bus_hold = "false";
+defparam \aeq_to_gxb[85]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X70_Y129_N32
+stratixiv_io_ibuf \aeq_to_gxb[86]~input (
+ .i(aeq_to_gxb[86]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[86]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[86]~input .bus_hold = "false";
+defparam \aeq_to_gxb[86]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y19_N94
+stratixiv_io_ibuf \aeq_to_gxb[87]~input (
+ .i(aeq_to_gxb[87]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[87]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[87]~input .bus_hold = "false";
+defparam \aeq_to_gxb[87]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X30_Y129_N94
+stratixiv_io_ibuf \aeq_to_gxb[88]~input (
+ .i(aeq_to_gxb[88]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[88]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[88]~input .bus_hold = "false";
+defparam \aeq_to_gxb[88]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X121_Y129_N1
+stratixiv_io_ibuf \aeq_to_gxb[89]~input (
+ .i(aeq_to_gxb[89]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[89]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[89]~input .bus_hold = "false";
+defparam \aeq_to_gxb[89]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X155_Y129_N32
+stratixiv_io_ibuf \aeq_to_gxb[90]~input (
+ .i(aeq_to_gxb[90]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[90]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[90]~input .bus_hold = "false";
+defparam \aeq_to_gxb[90]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X159_Y129_N1
+stratixiv_io_ibuf \aeq_to_gxb[91]~input (
+ .i(aeq_to_gxb[91]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[91]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[91]~input .bus_hold = "false";
+defparam \aeq_to_gxb[91]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X42_Y129_N94
+stratixiv_io_ibuf \aeq_to_gxb[92]~input (
+ .i(aeq_to_gxb[92]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[92]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[92]~input .bus_hold = "false";
+defparam \aeq_to_gxb[92]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X117_Y129_N94
+stratixiv_io_ibuf \aeq_to_gxb[93]~input (
+ .i(aeq_to_gxb[93]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[93]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[93]~input .bus_hold = "false";
+defparam \aeq_to_gxb[93]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y50_N32
+stratixiv_io_ibuf \aeq_to_gxb[94]~input (
+ .i(aeq_to_gxb[94]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[94]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[94]~input .bus_hold = "false";
+defparam \aeq_to_gxb[94]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X175_Y129_N94
+stratixiv_io_ibuf \aeq_to_gxb[95]~input (
+ .i(aeq_to_gxb[95]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\aeq_to_gxb[95]~input_o ));
+// synopsys translate_off
+defparam \aeq_to_gxb[95]~input .bus_hold = "false";
+defparam \aeq_to_gxb[95]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X85_Y0_N94
+stratixiv_io_ibuf \rx_cruclk[0]~input (
+ .i(rx_cruclk[0]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_cruclk[0]~input_o ));
+// synopsys translate_off
+defparam \rx_cruclk[0]~input .bus_hold = "false";
+defparam \rx_cruclk[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y35_N32
+stratixiv_io_ibuf \rx_cruclk[1]~input (
+ .i(rx_cruclk[1]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_cruclk[1]~input_o ));
+// synopsys translate_off
+defparam \rx_cruclk[1]~input .bus_hold = "false";
+defparam \rx_cruclk[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X185_Y59_N1
+stratixiv_io_ibuf \rx_cruclk[2]~input (
+ .i(rx_cruclk[2]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_cruclk[2]~input_o ));
+// synopsys translate_off
+defparam \rx_cruclk[2]~input .bus_hold = "false";
+defparam \rx_cruclk[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X11_Y129_N63
+stratixiv_io_ibuf \rx_cruclk[3]~input (
+ .i(rx_cruclk[3]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\rx_cruclk[3]~input_o ));
+// synopsys translate_off
+defparam \rx_cruclk[3]~input .bus_hold = "false";
+defparam \rx_cruclk[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y109_N32
+stratixiv_io_ibuf \reconfig_togxb[0]~input (
+ .i(reconfig_togxb[0]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\reconfig_togxb[0]~input_o ));
+// synopsys translate_off
+defparam \reconfig_togxb[0]~input .bus_hold = "false";
+defparam \reconfig_togxb[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X104_Y0_N63
+stratixiv_io_ibuf \reconfig_togxb[2]~input (
+ .i(reconfig_togxb[2]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\reconfig_togxb[2]~input_o ));
+// synopsys translate_off
+defparam \reconfig_togxb[2]~input .bus_hold = "false";
+defparam \reconfig_togxb[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X108_Y0_N63
+stratixiv_io_ibuf \reconfig_togxb[1]~input (
+ .i(reconfig_togxb[1]),
+ .ibar(gnd),
+ .dynamicterminationcontrol(gnd),
+ .o(\reconfig_togxb[1]~input_o ));
+// synopsys translate_off
+defparam \reconfig_togxb[1]~input .bus_hold = "false";
+defparam \reconfig_togxb[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+assign ch_ctrl_readdata[0] = \ch_ctrl_readdata[0]~output_o ;
+
+assign ch_ctrl_readdata[1] = \ch_ctrl_readdata[1]~output_o ;
+
+assign ch_ctrl_readdata[2] = \ch_ctrl_readdata[2]~output_o ;
+
+assign ch_ctrl_readdata[3] = \ch_ctrl_readdata[3]~output_o ;
+
+assign ch_ctrl_readdata[4] = \ch_ctrl_readdata[4]~output_o ;
+
+assign ch_ctrl_readdata[5] = \ch_ctrl_readdata[5]~output_o ;
+
+assign ch_ctrl_readdata[6] = \ch_ctrl_readdata[6]~output_o ;
+
+assign ch_ctrl_readdata[7] = \ch_ctrl_readdata[7]~output_o ;
+
+assign ch_ctrl_readdata[8] = \ch_ctrl_readdata[8]~output_o ;
+
+assign ch_ctrl_readdata[9] = \ch_ctrl_readdata[9]~output_o ;
+
+assign ch_ctrl_readdata[10] = \ch_ctrl_readdata[10]~output_o ;
+
+assign ch_ctrl_readdata[11] = \ch_ctrl_readdata[11]~output_o ;
+
+assign ch_ctrl_readdata[12] = \ch_ctrl_readdata[12]~output_o ;
+
+assign ch_ctrl_readdata[13] = \ch_ctrl_readdata[13]~output_o ;
+
+assign ch_ctrl_readdata[14] = \ch_ctrl_readdata[14]~output_o ;
+
+assign ch_ctrl_readdata[15] = \ch_ctrl_readdata[15]~output_o ;
+
+assign ch_ctrl_readdata[16] = \ch_ctrl_readdata[16]~output_o ;
+
+assign ch_ctrl_readdata[17] = \ch_ctrl_readdata[17]~output_o ;
+
+assign ch_ctrl_readdata[18] = \ch_ctrl_readdata[18]~output_o ;
+
+assign ch_ctrl_readdata[19] = \ch_ctrl_readdata[19]~output_o ;
+
+assign ch_ctrl_readdata[20] = \ch_ctrl_readdata[20]~output_o ;
+
+assign ch_ctrl_readdata[21] = \ch_ctrl_readdata[21]~output_o ;
+
+assign ch_ctrl_readdata[22] = \ch_ctrl_readdata[22]~output_o ;
+
+assign ch_ctrl_readdata[23] = \ch_ctrl_readdata[23]~output_o ;
+
+assign ch_ctrl_readdata[24] = \ch_ctrl_readdata[24]~output_o ;
+
+assign ch_ctrl_readdata[25] = \ch_ctrl_readdata[25]~output_o ;
+
+assign ch_ctrl_readdata[26] = \ch_ctrl_readdata[26]~output_o ;
+
+assign ch_ctrl_readdata[27] = \ch_ctrl_readdata[27]~output_o ;
+
+assign ch_ctrl_readdata[28] = \ch_ctrl_readdata[28]~output_o ;
+
+assign ch_ctrl_readdata[29] = \ch_ctrl_readdata[29]~output_o ;
+
+assign ch_ctrl_readdata[30] = \ch_ctrl_readdata[30]~output_o ;
+
+assign ch_ctrl_readdata[31] = \ch_ctrl_readdata[31]~output_o ;
+
+assign pll_locked = \pll_locked~output_o ;
+
+assign reconfig_fromgxb[0] = \reconfig_fromgxb[0]~output_o ;
+
+assign reconfig_fromgxb[1] = \reconfig_fromgxb[1]~output_o ;
+
+assign reconfig_fromgxb[2] = \reconfig_fromgxb[2]~output_o ;
+
+assign reconfig_fromgxb[3] = \reconfig_fromgxb[3]~output_o ;
+
+assign reconfig_fromgxb[4] = \reconfig_fromgxb[4]~output_o ;
+
+assign reconfig_fromgxb[5] = \reconfig_fromgxb[5]~output_o ;
+
+assign reconfig_fromgxb[6] = \reconfig_fromgxb[6]~output_o ;
+
+assign reconfig_fromgxb[7] = \reconfig_fromgxb[7]~output_o ;
+
+assign reconfig_fromgxb[8] = \reconfig_fromgxb[8]~output_o ;
+
+assign reconfig_fromgxb[9] = \reconfig_fromgxb[9]~output_o ;
+
+assign reconfig_fromgxb[10] = \reconfig_fromgxb[10]~output_o ;
+
+assign reconfig_fromgxb[11] = \reconfig_fromgxb[11]~output_o ;
+
+assign reconfig_fromgxb[12] = \reconfig_fromgxb[12]~output_o ;
+
+assign reconfig_fromgxb[13] = \reconfig_fromgxb[13]~output_o ;
+
+assign reconfig_fromgxb[14] = \reconfig_fromgxb[14]~output_o ;
+
+assign reconfig_fromgxb[15] = \reconfig_fromgxb[15]~output_o ;
+
+assign reconfig_fromgxb[16] = \reconfig_fromgxb[16]~output_o ;
+
+assign reconfig_fromgxb[17] = \reconfig_fromgxb[17]~output_o ;
+
+assign reconfig_fromgxb[18] = \reconfig_fromgxb[18]~output_o ;
+
+assign reconfig_fromgxb[19] = \reconfig_fromgxb[19]~output_o ;
+
+assign reconfig_fromgxb[20] = \reconfig_fromgxb[20]~output_o ;
+
+assign reconfig_fromgxb[21] = \reconfig_fromgxb[21]~output_o ;
+
+assign reconfig_fromgxb[22] = \reconfig_fromgxb[22]~output_o ;
+
+assign reconfig_fromgxb[23] = \reconfig_fromgxb[23]~output_o ;
+
+assign reconfig_fromgxb[24] = \reconfig_fromgxb[24]~output_o ;
+
+assign reconfig_fromgxb[25] = \reconfig_fromgxb[25]~output_o ;
+
+assign reconfig_fromgxb[26] = \reconfig_fromgxb[26]~output_o ;
+
+assign reconfig_fromgxb[27] = \reconfig_fromgxb[27]~output_o ;
+
+assign reconfig_fromgxb[28] = \reconfig_fromgxb[28]~output_o ;
+
+assign reconfig_fromgxb[29] = \reconfig_fromgxb[29]~output_o ;
+
+assign reconfig_fromgxb[30] = \reconfig_fromgxb[30]~output_o ;
+
+assign reconfig_fromgxb[31] = \reconfig_fromgxb[31]~output_o ;
+
+assign reconfig_fromgxb[32] = \reconfig_fromgxb[32]~output_o ;
+
+assign reconfig_fromgxb[33] = \reconfig_fromgxb[33]~output_o ;
+
+assign reconfig_fromgxb[34] = \reconfig_fromgxb[34]~output_o ;
+
+assign reconfig_fromgxb[35] = \reconfig_fromgxb[35]~output_o ;
+
+assign reconfig_fromgxb[36] = \reconfig_fromgxb[36]~output_o ;
+
+assign reconfig_fromgxb[37] = \reconfig_fromgxb[37]~output_o ;
+
+assign reconfig_fromgxb[38] = \reconfig_fromgxb[38]~output_o ;
+
+assign reconfig_fromgxb[39] = \reconfig_fromgxb[39]~output_o ;
+
+assign reconfig_fromgxb[40] = \reconfig_fromgxb[40]~output_o ;
+
+assign reconfig_fromgxb[41] = \reconfig_fromgxb[41]~output_o ;
+
+assign reconfig_fromgxb[42] = \reconfig_fromgxb[42]~output_o ;
+
+assign reconfig_fromgxb[43] = \reconfig_fromgxb[43]~output_o ;
+
+assign reconfig_fromgxb[44] = \reconfig_fromgxb[44]~output_o ;
+
+assign reconfig_fromgxb[45] = \reconfig_fromgxb[45]~output_o ;
+
+assign reconfig_fromgxb[46] = \reconfig_fromgxb[46]~output_o ;
+
+assign reconfig_fromgxb[47] = \reconfig_fromgxb[47]~output_o ;
+
+assign reconfig_fromgxb[48] = \reconfig_fromgxb[48]~output_o ;
+
+assign reconfig_fromgxb[49] = \reconfig_fromgxb[49]~output_o ;
+
+assign reconfig_fromgxb[50] = \reconfig_fromgxb[50]~output_o ;
+
+assign reconfig_fromgxb[51] = \reconfig_fromgxb[51]~output_o ;
+
+assign reconfig_fromgxb[52] = \reconfig_fromgxb[52]~output_o ;
+
+assign reconfig_fromgxb[53] = \reconfig_fromgxb[53]~output_o ;
+
+assign reconfig_fromgxb[54] = \reconfig_fromgxb[54]~output_o ;
+
+assign reconfig_fromgxb[55] = \reconfig_fromgxb[55]~output_o ;
+
+assign reconfig_fromgxb[56] = \reconfig_fromgxb[56]~output_o ;
+
+assign reconfig_fromgxb[57] = \reconfig_fromgxb[57]~output_o ;
+
+assign reconfig_fromgxb[58] = \reconfig_fromgxb[58]~output_o ;
+
+assign reconfig_fromgxb[59] = \reconfig_fromgxb[59]~output_o ;
+
+assign reconfig_fromgxb[60] = \reconfig_fromgxb[60]~output_o ;
+
+assign reconfig_fromgxb[61] = \reconfig_fromgxb[61]~output_o ;
+
+assign reconfig_fromgxb[62] = \reconfig_fromgxb[62]~output_o ;
+
+assign reconfig_fromgxb[63] = \reconfig_fromgxb[63]~output_o ;
+
+assign reconfig_fromgxb[64] = \reconfig_fromgxb[64]~output_o ;
+
+assign reconfig_fromgxb[65] = \reconfig_fromgxb[65]~output_o ;
+
+assign reconfig_fromgxb[66] = \reconfig_fromgxb[66]~output_o ;
+
+assign reconfig_fromgxb[67] = \reconfig_fromgxb[67]~output_o ;
+
+assign aeq_from_gxb[0] = \aeq_from_gxb[0]~output_o ;
+
+assign aeq_from_gxb[1] = \aeq_from_gxb[1]~output_o ;
+
+assign aeq_from_gxb[2] = \aeq_from_gxb[2]~output_o ;
+
+assign aeq_from_gxb[3] = \aeq_from_gxb[3]~output_o ;
+
+assign aeq_from_gxb[4] = \aeq_from_gxb[4]~output_o ;
+
+assign aeq_from_gxb[5] = \aeq_from_gxb[5]~output_o ;
+
+assign aeq_from_gxb[6] = \aeq_from_gxb[6]~output_o ;
+
+assign aeq_from_gxb[7] = \aeq_from_gxb[7]~output_o ;
+
+assign aeq_from_gxb[8] = \aeq_from_gxb[8]~output_o ;
+
+assign aeq_from_gxb[9] = \aeq_from_gxb[9]~output_o ;
+
+assign aeq_from_gxb[10] = \aeq_from_gxb[10]~output_o ;
+
+assign aeq_from_gxb[11] = \aeq_from_gxb[11]~output_o ;
+
+assign aeq_from_gxb[12] = \aeq_from_gxb[12]~output_o ;
+
+assign aeq_from_gxb[13] = \aeq_from_gxb[13]~output_o ;
+
+assign aeq_from_gxb[14] = \aeq_from_gxb[14]~output_o ;
+
+assign aeq_from_gxb[15] = \aeq_from_gxb[15]~output_o ;
+
+assign aeq_from_gxb[16] = \aeq_from_gxb[16]~output_o ;
+
+assign aeq_from_gxb[17] = \aeq_from_gxb[17]~output_o ;
+
+assign aeq_from_gxb[18] = \aeq_from_gxb[18]~output_o ;
+
+assign aeq_from_gxb[19] = \aeq_from_gxb[19]~output_o ;
+
+assign aeq_from_gxb[20] = \aeq_from_gxb[20]~output_o ;
+
+assign aeq_from_gxb[21] = \aeq_from_gxb[21]~output_o ;
+
+assign aeq_from_gxb[22] = \aeq_from_gxb[22]~output_o ;
+
+assign aeq_from_gxb[23] = \aeq_from_gxb[23]~output_o ;
+
+assign aeq_from_gxb[24] = \aeq_from_gxb[24]~output_o ;
+
+assign aeq_from_gxb[25] = \aeq_from_gxb[25]~output_o ;
+
+assign aeq_from_gxb[26] = \aeq_from_gxb[26]~output_o ;
+
+assign aeq_from_gxb[27] = \aeq_from_gxb[27]~output_o ;
+
+assign aeq_from_gxb[28] = \aeq_from_gxb[28]~output_o ;
+
+assign aeq_from_gxb[29] = \aeq_from_gxb[29]~output_o ;
+
+assign aeq_from_gxb[30] = \aeq_from_gxb[30]~output_o ;
+
+assign aeq_from_gxb[31] = \aeq_from_gxb[31]~output_o ;
+
+assign tx_dataout[0] = \tx_dataout[0]~output_o ;
+
+assign tx_dataout[1] = \tx_dataout[1]~output_o ;
+
+assign tx_dataout[2] = \tx_dataout[2]~output_o ;
+
+assign tx_dataout[3] = \tx_dataout[3]~output_o ;
+
+assign tx_clkout[0] = \tx_clkout[0]~output_o ;
+
+assign tx_clkout[1] = \tx_clkout[1]~output_o ;
+
+assign tx_clkout[2] = \tx_clkout[2]~output_o ;
+
+assign tx_clkout[3] = \tx_clkout[3]~output_o ;
+
+assign rx_dataout[0] = \rx_dataout[0]~output_o ;
+
+assign rx_dataout[1] = \rx_dataout[1]~output_o ;
+
+assign rx_dataout[2] = \rx_dataout[2]~output_o ;
+
+assign rx_dataout[3] = \rx_dataout[3]~output_o ;
+
+assign rx_dataout[4] = \rx_dataout[4]~output_o ;
+
+assign rx_dataout[5] = \rx_dataout[5]~output_o ;
+
+assign rx_dataout[6] = \rx_dataout[6]~output_o ;
+
+assign rx_dataout[7] = \rx_dataout[7]~output_o ;
+
+assign rx_dataout[8] = \rx_dataout[8]~output_o ;
+
+assign rx_dataout[9] = \rx_dataout[9]~output_o ;
+
+assign rx_dataout[10] = \rx_dataout[10]~output_o ;
+
+assign rx_dataout[11] = \rx_dataout[11]~output_o ;
+
+assign rx_dataout[12] = \rx_dataout[12]~output_o ;
+
+assign rx_dataout[13] = \rx_dataout[13]~output_o ;
+
+assign rx_dataout[14] = \rx_dataout[14]~output_o ;
+
+assign rx_dataout[15] = \rx_dataout[15]~output_o ;
+
+assign rx_dataout[16] = \rx_dataout[16]~output_o ;
+
+assign rx_dataout[17] = \rx_dataout[17]~output_o ;
+
+assign rx_dataout[18] = \rx_dataout[18]~output_o ;
+
+assign rx_dataout[19] = \rx_dataout[19]~output_o ;
+
+assign rx_dataout[20] = \rx_dataout[20]~output_o ;
+
+assign rx_dataout[21] = \rx_dataout[21]~output_o ;
+
+assign rx_dataout[22] = \rx_dataout[22]~output_o ;
+
+assign rx_dataout[23] = \rx_dataout[23]~output_o ;
+
+assign rx_dataout[24] = \rx_dataout[24]~output_o ;
+
+assign rx_dataout[25] = \rx_dataout[25]~output_o ;
+
+assign rx_dataout[26] = \rx_dataout[26]~output_o ;
+
+assign rx_dataout[27] = \rx_dataout[27]~output_o ;
+
+assign rx_dataout[28] = \rx_dataout[28]~output_o ;
+
+assign rx_dataout[29] = \rx_dataout[29]~output_o ;
+
+assign rx_dataout[30] = \rx_dataout[30]~output_o ;
+
+assign rx_dataout[31] = \rx_dataout[31]~output_o ;
+
+assign rx_dataout[32] = \rx_dataout[32]~output_o ;
+
+assign rx_dataout[33] = \rx_dataout[33]~output_o ;
+
+assign rx_dataout[34] = \rx_dataout[34]~output_o ;
+
+assign rx_dataout[35] = \rx_dataout[35]~output_o ;
+
+assign rx_dataout[36] = \rx_dataout[36]~output_o ;
+
+assign rx_dataout[37] = \rx_dataout[37]~output_o ;
+
+assign rx_dataout[38] = \rx_dataout[38]~output_o ;
+
+assign rx_dataout[39] = \rx_dataout[39]~output_o ;
+
+assign rx_dataout[40] = \rx_dataout[40]~output_o ;
+
+assign rx_dataout[41] = \rx_dataout[41]~output_o ;
+
+assign rx_dataout[42] = \rx_dataout[42]~output_o ;
+
+assign rx_dataout[43] = \rx_dataout[43]~output_o ;
+
+assign rx_dataout[44] = \rx_dataout[44]~output_o ;
+
+assign rx_dataout[45] = \rx_dataout[45]~output_o ;
+
+assign rx_dataout[46] = \rx_dataout[46]~output_o ;
+
+assign rx_dataout[47] = \rx_dataout[47]~output_o ;
+
+assign rx_dataout[48] = \rx_dataout[48]~output_o ;
+
+assign rx_dataout[49] = \rx_dataout[49]~output_o ;
+
+assign rx_dataout[50] = \rx_dataout[50]~output_o ;
+
+assign rx_dataout[51] = \rx_dataout[51]~output_o ;
+
+assign rx_dataout[52] = \rx_dataout[52]~output_o ;
+
+assign rx_dataout[53] = \rx_dataout[53]~output_o ;
+
+assign rx_dataout[54] = \rx_dataout[54]~output_o ;
+
+assign rx_dataout[55] = \rx_dataout[55]~output_o ;
+
+assign rx_dataout[56] = \rx_dataout[56]~output_o ;
+
+assign rx_dataout[57] = \rx_dataout[57]~output_o ;
+
+assign rx_dataout[58] = \rx_dataout[58]~output_o ;
+
+assign rx_dataout[59] = \rx_dataout[59]~output_o ;
+
+assign rx_dataout[60] = \rx_dataout[60]~output_o ;
+
+assign rx_dataout[61] = \rx_dataout[61]~output_o ;
+
+assign rx_dataout[62] = \rx_dataout[62]~output_o ;
+
+assign rx_dataout[63] = \rx_dataout[63]~output_o ;
+
+assign rx_dataout[64] = \rx_dataout[64]~output_o ;
+
+assign rx_dataout[65] = \rx_dataout[65]~output_o ;
+
+assign rx_dataout[66] = \rx_dataout[66]~output_o ;
+
+assign rx_dataout[67] = \rx_dataout[67]~output_o ;
+
+assign rx_dataout[68] = \rx_dataout[68]~output_o ;
+
+assign rx_dataout[69] = \rx_dataout[69]~output_o ;
+
+assign rx_dataout[70] = \rx_dataout[70]~output_o ;
+
+assign rx_dataout[71] = \rx_dataout[71]~output_o ;
+
+assign rx_dataout[72] = \rx_dataout[72]~output_o ;
+
+assign rx_dataout[73] = \rx_dataout[73]~output_o ;
+
+assign rx_dataout[74] = \rx_dataout[74]~output_o ;
+
+assign rx_dataout[75] = \rx_dataout[75]~output_o ;
+
+assign rx_dataout[76] = \rx_dataout[76]~output_o ;
+
+assign rx_dataout[77] = \rx_dataout[77]~output_o ;
+
+assign rx_dataout[78] = \rx_dataout[78]~output_o ;
+
+assign rx_dataout[79] = \rx_dataout[79]~output_o ;
+
+assign rx_clkout[0] = \rx_clkout[0]~output_o ;
+
+assign rx_clkout[1] = \rx_clkout[1]~output_o ;
+
+assign rx_clkout[2] = \rx_clkout[2]~output_o ;
+
+assign rx_clkout[3] = \rx_clkout[3]~output_o ;
+
+assign rx_freqlocked[0] = \rx_freqlocked[0]~output_o ;
+
+assign rx_freqlocked[1] = \rx_freqlocked[1]~output_o ;
+
+assign rx_freqlocked[2] = \rx_freqlocked[2]~output_o ;
+
+assign rx_freqlocked[3] = \rx_freqlocked[3]~output_o ;
+
+assign rx_pll_locked[0] = \rx_pll_locked[0]~output_o ;
+
+assign rx_pll_locked[1] = \rx_pll_locked[1]~output_o ;
+
+assign rx_pll_locked[2] = \rx_pll_locked[2]~output_o ;
+
+assign rx_pll_locked[3] = \rx_pll_locked[3]~output_o ;
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_dprio.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_dprio.v
new file mode 100644
index 0000000000000000000000000000000000000000..c8cb550d6c519e9fddf949f789fe95544e45690e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_dprio.v
@@ -0,0 +1,199 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"{-to addr_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to wr_out_data_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to rd_out_data_shift_reg[13]} DPRIO_INTERFACE_REG=ON;{-to in_data_shift_reg[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[1]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[2]} DPRIO_INTERFACE_REG=ON"} *)
+module alt_dprio (
+ input wire [15:0] address,
+ output wire busy,
+ input wire [15:0] datain,
+ output wire [15:0] dataout,
+ input wire dpclk,
+ output wire dpriodisable,
+ output wire dprioin,
+ output wire dprioload,
+ input wire dprioout,
+ input wire [6:0] quad_address,
+ input wire rden,
+ input wire wren,
+ input wire wren_data
+ );
+
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [31:0] addr_shift_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [15:0] in_data_shift_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [15:0] rd_out_data_shift_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [2:0] startup_cntr;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg [2:0] state_mc_reg;
+ (* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
+ reg [31:0] wr_out_data_shift_reg;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg [5:0] state_mc_counter_q;
+
+ wire pre_amble_cmpr_agb;
+ wire [7:0] state_mc_decode_eq;
+ wire dprioin_mux_dataout;
+ wire busy_state;
+ wire idle_state;
+ wire rd_addr_done;
+ wire rd_addr_state;
+ wire rd_data_done;
+ wire rd_data_input_state;
+ wire rd_data_output_state;
+ wire rd_data_state;
+ wire rdinc;
+ wire read_state;
+ wire s0_to_0;
+ wire s0_to_1;
+ wire s1_to_0;
+ wire s1_to_1;
+ wire s2_to_0;
+ wire s2_to_1;
+ wire startup_done;
+ wire startup_idle;
+ wire wr_addr_done;
+ wire wr_addr_state;
+ wire wr_data_done;
+ wire wr_data_state;
+ wire write_state;
+ wire [2:0] startup_cntr_d;
+ wire [2:0] startup_cntr_ena;
+
+ // synopsys translate_off
+ initial
+ begin
+ addr_shift_reg = 0;
+ in_data_shift_reg = 0;
+ rd_out_data_shift_reg = 0;
+ startup_cntr[2:0] = 3'b0;
+ state_mc_reg = 0;
+ wr_out_data_shift_reg = 0;
+ state_mc_counter_q = 6'b0;
+ end
+ // synopsys translate_on
+
+ always @ (posedge dpclk)
+ begin
+ if (state_mc_counter_q == 6'b011111)
+ begin
+ addr_shift_reg <= {{2{{2{1'b0}}}}, {3{1'b0}}, quad_address, 2'b10, address};
+ rd_out_data_shift_reg <= {{2{1'b0}}, {2{1'b1}}, {3{1'b0}}, quad_address, 2'b10};
+ wr_out_data_shift_reg <= {{2{1'b0}}, 2'b01, {3{1'b0}}, quad_address, 2'b10, datain};
+ end
+ else begin
+ addr_shift_reg <= {addr_shift_reg[30:0], 1'b0};
+ rd_out_data_shift_reg <= {rd_out_data_shift_reg[14:0], 1'b0};
+ wr_out_data_shift_reg <= {wr_out_data_shift_reg[30:0], 1'b0};
+ end
+
+ if (rd_data_input_state == 1'b1)
+ in_data_shift_reg <= {in_data_shift_reg[14:0], dprioout};
+ end
+
+ always @ (posedge dpclk)
+ begin
+ if (startup_cntr_ena[0] == 1'b1)
+ startup_cntr[0] <= startup_cntr_d[0];
+ if (startup_cntr_ena[1:1] == 1'b1)
+ startup_cntr[1] <= startup_cntr_d[1];
+ if (startup_cntr_ena[2:2] == 1'b1)
+ startup_cntr[2] <= startup_cntr_d[2];
+ end
+
+ assign startup_cntr_d = {(startup_cntr[2] ^ (startup_cntr[1] & startup_cntr[0])), (startup_cntr[0] ^ startup_cntr[1]), (~ startup_cntr[0])};
+ assign startup_cntr_ena = {3{((((rden | wren) | rdinc) | (~ startup_idle)) & (~ startup_done))}};
+
+ always @ ( posedge dpclk)
+ begin
+ state_mc_reg <= {(s2_to_1 | (((~ s2_to_0) & (~ s2_to_1)) & state_mc_reg[2])), (s1_to_1 | (((~ s1_to_0) & (~ s1_to_1)) & state_mc_reg[1])), (s0_to_1 | (((~ s0_to_0) & (~ s0_to_1)) & state_mc_reg[0]))};
+ end
+
+ always @(posedge dpclk)
+ begin
+ if (write_state | read_state)
+ begin
+ if (state_mc_counter_q == 6'b111111)
+ state_mc_counter_q <= 6'b0;
+ else
+ state_mc_counter_q <= state_mc_counter_q[5:0] + 6'b1;
+ end
+ end
+
+ lpm_decode #(
+ .lpm_decodes (8),
+ .lpm_width (3),
+ .lpm_type ("lpm_decode"))
+ state_mc_decode(
+ .data(state_mc_reg),
+ .eq(state_mc_decode_eq)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .clken(1'b1),
+ .clock(1'b0),
+ .enable(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+
+ or(dprioin_mux_dataout, ((((((wr_addr_state | rd_addr_state) & addr_shift_reg[31]) & pre_amble_cmpr_agb) | ((~ pre_amble_cmpr_agb) & (wr_addr_state | rd_addr_state))) | (((wr_data_state & wr_out_data_shift_reg[31]) & pre_amble_cmpr_agb) | ((~ pre_amble_cmpr_agb) & wr_data_state))) | (((rd_data_output_state & rd_out_data_shift_reg[15]) & pre_amble_cmpr_agb) | ((~ pre_amble_cmpr_agb) & rd_data_output_state))), ~(((write_state | rd_addr_state) | rd_data_output_state)));
+
+ assign
+ pre_amble_cmpr_agb = (state_mc_counter_q > 6'b011111),
+ busy = busy_state,
+ busy_state = (write_state | read_state),
+ dataout = in_data_shift_reg,
+ dpriodisable = (~ (startup_cntr[2] & (startup_cntr[0] | startup_cntr[1]))),
+ dprioin = dprioin_mux_dataout,
+ dprioload = (~ ((startup_cntr[0] ^ startup_cntr[1]) & (~ startup_cntr[2]))),
+ idle_state = state_mc_decode_eq[0],
+
+ rd_addr_done = (rd_addr_state & (state_mc_counter_q == 6'b111111)),
+
+ rd_addr_state = (state_mc_decode_eq[5] & startup_done),
+ rd_data_done = (rd_data_state & (state_mc_counter_q == 6'b111111)),
+
+ rd_data_input_state = ((state_mc_counter_q >= 6'b110000) & rd_data_state),
+
+ rd_data_output_state = (state_mc_counter_q < 6'b110000 & rd_data_state),
+ rd_data_state = (state_mc_decode_eq[7] & startup_done),
+ rdinc = 1'b0,
+ read_state = (rd_addr_state | rd_data_state),
+ s0_to_0 = ((wr_data_state & wr_data_done) | (rd_data_state & rd_data_done)),
+ s0_to_1 = (((idle_state & (wren | ((~ wren) & ((rden | rdinc) | wren_data)))) | (wr_addr_state & wr_addr_done)) | (rd_addr_state & rd_addr_done)),
+ s1_to_0 = (((wr_data_state & wr_data_done) | (rd_data_state & rd_data_done)) | (idle_state & (wren | (((~ wren) & (~ wren_data)) & rden)))),
+ s1_to_1 = (((idle_state & ((~ wren) & (rdinc | wren_data))) | (wr_addr_state & wr_addr_done)) | (rd_addr_state & rd_addr_done)),
+ s2_to_0 = ((((wr_addr_state & wr_addr_done) | (wr_data_state & wr_data_done)) | (rd_data_state & rd_data_done)) | (idle_state & (wren | wren_data))),
+ s2_to_1 = ((idle_state & (((~ wren) & (~ wren_data)) & (rdinc | rden))) | (rd_addr_state & rd_addr_done)),
+ startup_done = ((startup_cntr[2] & (~ startup_cntr[0])) & startup_cntr[1]),
+ startup_idle = ((~ startup_cntr[0]) & (~ (startup_cntr[2] ^ startup_cntr[1]))),
+
+ wr_addr_done = (wr_addr_state & (state_mc_counter_q == 6'b111111)),
+
+ wr_addr_state = (state_mc_decode_eq[1] & startup_done),
+
+ wr_data_done = (wr_data_state & (state_mc_counter_q == 6'b111111)),
+
+ wr_data_state = (state_mc_decode_eq[3] & startup_done),
+ write_state = (wr_addr_state | wr_data_state);
+endmodule //alt_dprio
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_mutex_acq.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_mutex_acq.v
new file mode 100644
index 0000000000000000000000000000000000000000..c5d020f703904fbb94916ef75bd1fda144424ba9
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_mutex_acq.v
@@ -0,0 +1,221 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_mutex_acq #(
+ parameter mutex_wait_time = 101,
+ parameter mutex_wait_time_cntr_width = 7, // do we need this parameter?
+ parameter addr_width = 5,
+ parameter data_width = 32,
+ parameter read_mutex_addr_offset = 0 // address of the mutex word
+)
+(
+
+input wire clk, // this will be the reconfig clk
+input wire reset,
+
+// Internal interface for the bigger controlling module, like analog reconfig
+input wire [addr_width-1:0] address, // MM address
+input wire [data_width-1:0] writedata,
+input wire write,
+input wire read,
+output reg waitrequest, // can use to tell internal master to wait when auto-request+release
+output wire [data_width-1:0] readdata,
+
+
+// MM master external interface, that connects to mutex-slave, like the reconfig_basic block
+output wire [addr_width-1:0] master_address, // MM address
+output wire [data_width-1:0] master_writedata,
+output wire master_write,
+output wire master_read,
+input wire master_waitrequest, // needed for a valid master interface
+input wire [data_width-1:0] master_readdata, // from mutex-slave
+
+
+
+// request mutex access and should be held high as long as mutex is used
+input wire mutex_req,
+// output indicating whether mutex access was granted or not
+output reg mutex_grant
+
+);
+
+
+
+localparam IDLE = 2'b00;
+localparam GET_MUTEX = 2'b01;
+localparam RELEASE_MUTEX = 2'b10;
+
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [9:0] mutex_timeout_cntr;
+
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *) // should we make this variable
+reg [mutex_wait_time_cntr_width-1:0] mutex_wait_cntr;
+
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [addr_width-1:0] mutex_int_address; // MM address
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [data_width-1:0] mutex_int_writedata;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg mutex_int_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg mutex_int_read;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg do_base_readwrite;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
+reg mutex_mux_ctrl;
+
+// synopsys translate_off
+initial
+begin
+ mutex_grant = 0;
+ mutex_mux_ctrl = 1'b1;
+ mutex_timeout_cntr = 0;
+ mutex_wait_cntr = 0;
+ mutex_int_address = 0;
+ mutex_int_writedata = 0;
+ mutex_int_read = 0;
+ mutex_int_write = 0;
+ waitrequest = 0;
+ do_base_readwrite = 0;
+ state = 0;
+end
+// synopsys translate_on
+
+always @(posedge clk or posedge reset)
+begin
+ if (reset === 1'b1)
+ begin
+ mutex_grant <= 0;
+ mutex_mux_ctrl <= 1'b1;
+ mutex_timeout_cntr <= 0;
+ mutex_wait_cntr <= 0;
+ mutex_int_address <= 'b0;
+ mutex_int_writedata <= 'b0;
+ mutex_int_read <= 'b0;
+ mutex_int_write <= 'b0;
+ waitrequest <= 'b0;
+ do_base_readwrite <= 'b0;
+ state <= 'b0;
+ end
+ else begin
+ case (state)
+ IDLE:begin
+// fix SPR:343567 - Avalon slaves are permitted to keep waitrequest asserted during idle cycles.
+// The state machine will still work correctly by simply removing this condition.
+// The next state is GET_MUTEX, and it will wait there if waitrequest is legitimately asserted.
+// if (master_waitrequest == 1'b1)
+// state <= IDLE; // wait till the waitrequest goes low
+// else if (mutex_grant == 0 &&
+ if (mutex_grant == 0 &&
+ (mutex_req == 1'b1 || write == 1'b1 || read == 1'b1))
+ begin
+ state <= GET_MUTEX;
+ mutex_int_read <= 1'b1;
+ mutex_int_address <= read_mutex_addr_offset;
+ mutex_int_write <= 1'b0;
+ mutex_wait_cntr <= 0;
+ mutex_mux_ctrl <= 1'b1;
+ waitrequest <= 1'b1; // pull the waitrequest high
+ if (write == 1'b1 || read == 1'b1)
+ do_base_readwrite <= 1'b1;
+ else
+ do_base_readwrite <= 1'b0;
+ end
+ else if (mutex_grant == 1'b1)
+ begin
+ do_base_readwrite <= 1'b0;
+ if (mutex_req == 1'b1 || write == 1'b1 || read == 1'b1)
+ begin
+ mutex_mux_ctrl <= 1'b0; // relinquish control of the mux
+ if (write == 1'b1 || read == 1'b1)
+ waitrequest <= master_waitrequest;
+ else
+ waitrequest <= 1'b0;
+ if (read == 1'b1 || write == 1'b1)
+ mutex_timeout_cntr <= 0;
+ else if (mutex_timeout_cntr == 10'd1000)
+ state <= RELEASE_MUTEX;
+ else
+ mutex_timeout_cntr <= mutex_timeout_cntr[9:0] + 10'b1;
+ end
+ else
+ state <= RELEASE_MUTEX;
+ end
+ else
+ begin
+ mutex_mux_ctrl <= 1'b1; // choke the inputs going to basic as mux is not available
+ mutex_int_read <= 1'b0;
+ mutex_int_write <= 1'b0;
+ waitrequest <= 1'b0;
+ end
+ end
+ RELEASE_MUTEX: begin
+ // release the mutex
+ mutex_mux_ctrl <= 1'b1;
+ mutex_int_read <= 1'b0;
+ mutex_int_write <= 1'b1;
+ mutex_int_address <= read_mutex_addr_offset;
+ mutex_int_writedata <= 16'b0;
+ mutex_grant <= 1'b0;
+ state <= IDLE;
+ mutex_timeout_cntr <= 0;
+ waitrequest <= 1'b0;
+ end
+ GET_MUTEX: begin
+ if (master_waitrequest == 1'b1) // wait in this state itself
+ begin
+ state <= GET_MUTEX;
+ end
+ else if (mutex_int_read == 1'b1 && master_readdata[0] == 1'b0) // check mutex bit
+ begin
+ mutex_grant <= 1; // mutex is available
+ state <= IDLE;
+ mutex_int_read <= 1'b0; // reset the read and mux ctrl bits
+ mutex_mux_ctrl <= 0;
+ if (do_base_readwrite == 1'b1)
+ waitrequest <= master_waitrequest;
+ else
+ waitrequest <= 1'b0;
+ end
+ else if (mutex_wait_cntr != mutex_wait_time)
+ begin // continue waiting till the wait time is hit
+ mutex_wait_cntr <= mutex_wait_cntr[mutex_wait_time_cntr_width-1:0] + 1;
+ mutex_int_read <= 1'b0; // pull down the read
+ state <= GET_MUTEX;
+ end
+ else // try and read again
+ begin
+ mutex_wait_cntr <= 0; // reset the wait cntr and try and read again
+ mutex_int_read <= 1'b1;
+ state <= GET_MUTEX;
+ end
+ end
+ default: begin
+ state <= IDLE;
+ end
+ endcase
+ end
+
+end
+
+
+assign master_address = mutex_mux_ctrl ? mutex_int_address : address;
+assign master_writedata = mutex_mux_ctrl ? mutex_int_writedata : writedata;
+assign master_write = mutex_mux_ctrl ? mutex_int_write : write;
+assign master_read = mutex_mux_ctrl ? mutex_int_read : read;
+assign readdata = master_readdata; // pipe the readdata out
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_pma_ch_controller_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_pma_ch_controller_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..6347c1ae0190510fae1e3cec2d4c58e3c11c0d34
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_pma_ch_controller_tgx.v
@@ -0,0 +1,164 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ns/10ps
+module alt_pma_ch_controller_tgx #(
+ parameter
+ number_of_channels = 4,
+ sys_clk_in_mhz = 50, // used to calculate internal delays in terms of system clock cycles
+ manual_reset = "false",
+ sync_depth =2
+ )
+ (
+ //controller standard interface to user
+ input tri0 rst, // controller logic reset
+// input wire powerdown_all, // save power
+ input tri0 rx_rst_digital, // tx_digitalreset
+ input tri0 tx_rst_digital, // rx_digitalreset
+ output wire tx_pma_ready, // pma tx pll_locked
+ output wire rx_pma_ready, // pma rx pll is locked to data
+ input tri0 tx_cal_busy, // tx calibration in progress
+ input tri0 rx_cal_busy, // rx calibration in progress
+ input tri1 pll_locked, // tx pll_locked
+
+ // user data (avalon-MM formatted)
+ input wire clk,
+ input tri0 [5:0] ch_mgmt_address,
+ input tri1 ch_mgmt_read,
+ output wire [31:0] ch_mgmt_readdata,
+ input tri0 ch_mgmt_write,
+ input tri0 [31:0] ch_mgmt_writedata,
+ output wire ch_mgmt_waitrequest,
+
+ input tri1 [number_of_channels-1:0] rx_is_lockedtodata,
+ input tri1 [number_of_channels-1:0] rx_is_lockedtoref,
+
+ output wire [number_of_channels-1:0] rx_set_locktodata,
+ output wire [number_of_channels-1:0] rx_set_locktoref,
+ output wire [number_of_channels-1:0] rx_seriallpbken,
+
+ output wire [number_of_channels-1:0] rx_analog_rst,
+ output wire [number_of_channels-1:0] tx_digital_rst,
+ output wire [number_of_channels-1:0] rx_digital_rst,
+ output wire pll_powerdown
+);
+ // reset controller outputs
+ wire reset_controller_tx_ready;
+ wire reset_controller_rx_ready;
+ wire reset_controller_pll_powerdown;
+ wire reset_controller_tx_digitalreset;
+ wire reset_controller_rx_analogreset;
+ wire reset_controller_rx_digitalreset;
+ wire reset_controller_manual_mode;
+
+ // Control & status register map (CSR) outputs
+ wire csr_reset_tx_digital; // to reset controller
+ wire csr_reset_rx_digital; // to reset controller
+ wire csr_reset_all; // to reset controller
+ wire csr_pll_powerdown;
+ wire [number_of_channels - 1 : 0] csr_tx_digitalreset; // to xcvr instance
+ wire [number_of_channels - 1 : 0] csr_rx_analogreset; // to xcvr instance
+ wire [number_of_channels - 1 : 0] csr_rx_digitalreset; // to xcvr instance
+ wire [number_of_channels - 1 : 0] csr_phy_loopback_serial; // to xcvr instance
+ wire [number_of_channels - 1 : 0] csr_rx_set_locktoref; // to xcvr instance
+ wire [number_of_channels - 1 : 0] csr_rx_set_locktodata; // to xcvr instance
+
+
+ ///////////////////////////////////////////////////////////////////
+
+ // Implement waitrequest to match previous implementation
+ altera_wait_generate wait_gen(
+ .rst(rst),
+ .clk(clk),
+ .launch_signal(ch_mgmt_read),
+ .wait_req(ch_mgmt_waitrequest)
+ );
+ // Instantiate memory map logic for given number of lanes & PLL's
+ // Includes all except PCS
+ alt_xcvr_csr_common #(
+ .lanes(number_of_channels),
+ .plls(1)
+ ) csr (
+ .clk(clk),
+ .reset(rst),
+ .address(8'h40 | ch_mgmt_address), // map word 0 of this module to word 64 of alt_xcvr_csr_common
+ .read(ch_mgmt_read),
+ .write(ch_mgmt_write),
+ .writedata(ch_mgmt_writedata),
+ .pll_locked(pll_locked),
+ .rx_is_lockedtoref(rx_is_lockedtoref),
+ .rx_is_lockedtodata(rx_is_lockedtodata),
+ .rx_signaldetect({number_of_channels{1'b0}}),
+ .reset_controller_tx_ready(reset_controller_tx_ready),
+ .reset_controller_rx_ready(reset_controller_rx_ready),
+ .reset_controller_pll_powerdown(reset_controller_pll_powerdown),
+ .reset_controller_tx_digitalreset(reset_controller_tx_digitalreset),
+ .reset_controller_rx_analogreset(reset_controller_rx_analogreset),
+ .reset_controller_rx_digitalreset(reset_controller_rx_digitalreset),
+ .readdata(ch_mgmt_readdata),
+ .csr_reset_tx_digital(csr_reset_tx_digital),
+ .csr_reset_rx_digital(csr_reset_rx_digital),
+ .csr_reset_all(csr_reset_all),
+ .csr_pll_powerdown(csr_pll_powerdown),
+ .csr_tx_digitalreset(csr_tx_digitalreset),
+ .csr_rx_analogreset(csr_rx_analogreset),
+ .csr_rx_digitalreset(csr_rx_digitalreset),
+ .csr_phy_loopback_serial(csr_phy_loopback_serial),
+ .csr_rx_set_locktoref(csr_rx_set_locktoref),
+ .csr_rx_set_locktodata(csr_rx_set_locktodata)
+ );
+
+
+ // Instantiate reset controller for PMA channels
+ alt_reset_ctrl_tgx_cdrauto #(
+ .sys_clk_in_mhz(sys_clk_in_mhz)
+ ) rc (
+ .clock(clk),
+ .reset_all(csr_reset_all),
+ .reset_tx_digital(csr_reset_tx_digital | tx_rst_digital),
+ .reset_rx_digital(csr_reset_rx_digital | rx_rst_digital),
+ .powerdown_all(rst),
+ .tx_ready(reset_controller_tx_ready),
+ .rx_ready(reset_controller_rx_ready),
+ .pll_powerdown (reset_controller_pll_powerdown),
+ .tx_digitalreset(reset_controller_tx_digitalreset),
+ .rx_analogreset(reset_controller_rx_analogreset),
+ .rx_digitalreset(reset_controller_rx_digitalreset),
+ .gxb_powerdown(),
+ .pll_is_locked(pll_locked),
+ .tx_cal_busy(tx_cal_busy),
+ .rx_cal_busy(rx_cal_busy),
+ .rx_is_lockedtodata(&rx_is_lockedtodata),
+ .manual_mode(reset_controller_manual_mode)
+ );
+
+ // Assign outputs from reset controller
+ assign tx_pma_ready = reset_controller_tx_ready;
+ assign rx_pma_ready = reset_controller_rx_ready;
+
+ // Assign outputs from CSR to channel control bits
+ assign rx_set_locktodata = csr_rx_set_locktodata;
+ assign rx_set_locktoref = csr_rx_set_locktoref;
+ assign rx_seriallpbken = csr_phy_loopback_serial;
+
+ assign rx_analog_rst = csr_rx_analogreset;
+ assign tx_digital_rst = csr_tx_digitalreset;
+ assign rx_digital_rst = csr_rx_digitalreset;
+
+ assign reset_controller_manual_mode = (manual_reset == "true") ? 1'b1
+ : (csr_rx_set_locktoref || csr_rx_set_locktodata);
+
+ assign pll_powerdown = csr_pll_powerdown;
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_pma_controller_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_pma_controller_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..614ad6278ca4a3cbbfa013d414c4e6c8410c156e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_pma_controller_tgx.v
@@ -0,0 +1,198 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ns/10ps
+module alt_pma_controller_tgx #(
+ parameter number_of_plls = 1,// One controller only control the possible merged pll. If more pll is needed, user can use multiplier controller for none share plls.
+ parameter tx_pll_reset_hold_time = 0,// ignored - now calculated according to system clock
+ parameter sync_depth = 2,
+ parameter sys_clk_in_mhz = 50 // needed for 1us and 4us delay timers
+)
+(
+ input rst, // controller logic reset
+ output tx_pll_ready,
+
+ // user data (avalon-MM formatted)
+ input wire clk,
+ input wire [1:0] pma_mgmt_address,
+ input wire pma_mgmt_read,
+ output reg [31:0] pma_mgmt_readdata,
+ input wire pma_mgmt_write,
+ input wire [31:0] pma_mgmt_writedata,
+ output wire pma_mgmt_waitrequest,
+
+ // user data (avalon-clock formatted)
+ input wire cal_blk_clk,
+
+ // user data: pll control (avalon-ST formatted)
+ output wire cal_blk_pdn,//sync with cal_blk_clk
+ output wire gx_pdn,//sync with clk
+ output wire [number_of_plls-1:0] pll_pdn, //sync with clk
+ input wire [number_of_plls-1:0] pll_locked //
+);
+
+localparam clk_in_mhz =
+`ifdef QUARTUS__SIMGEN
+ 2; // simulation-only value
+`elsif ALTERA_RESERVED_QIS
+ sys_clk_in_mhz; // use real counter lengths for normal Quartus synthesis
+`else
+ 2; // simulation-only value
+`endif
+localparam t_pll_powerdown = clk_in_mhz; // 1 us minimum
+localparam t_ltd_auto = clk_in_mhz*4; // 4 us minimum
+
+wire [number_of_plls-1:0] pll_locked_sync;
+reg cal_blk_pdn_reg;
+reg read_delay;
+reg gx_pdn_reg;
+reg pll_pdn_resetall_avmm;
+wire pll_pdn_int;
+reg pll_pdn_reg;
+
+wire gx_pdn_int;
+wire gx_pdn_done;
+
+altera_wait_generate wait_gen(
+ .rst(rst),
+.clk(clk),
+.launch_signal(pma_mgmt_read),
+.wait_req(pma_mgmt_waitrequest)
+ );
+
+alt_reset_ctrl_lego
+#(
+.reset_hold_cycles (t_pll_powerdown) // reset pulse length in clock cycles
+) pll_pdn_rst
+(
+.clock(clk),
+.start(1'b1 ),
+.reset(pll_pdn_int),
+.rdone(pll_locked), // reset done signal
+.aclr(rst),
+.sdone(tx_pll_ready) // sequence done for this lego
+);
+
+alt_reset_ctrl_lego
+#(
+.reset_hold_cycles (2) // reset pulse length in clock cycles
+) gx_pdn_rst
+(
+.clock(clk),
+.start(1'b1 ),
+.reset(gx_pdn_int),
+.rdone(1'b1), // reset done signal
+.aclr(rst),
+.sdone(gx_pdn_done) // sequence done for this lego
+);
+
+assign pll_pdn= pll_pdn_reg | {number_of_plls{pll_pdn_int}} ;
+
+initial
+begin
+ pll_pdn_reg <= 0;
+end
+always @ (posedge clk, posedge rst)
+begin
+ if(rst) begin
+ pll_pdn_reg <= 1'b0;
+ end
+ else if (pma_mgmt_write==1'b1 & pma_mgmt_address==2'b00) begin
+ pll_pdn_reg <= pma_mgmt_writedata[number_of_plls -1 :0];
+ end
+end
+
+initial
+begin
+ pma_mgmt_readdata <= 0;
+end
+always @ (posedge clk, posedge rst)
+begin
+ if(rst) begin
+ pma_mgmt_readdata <= 0;
+ end
+ else if (pma_mgmt_read==1'b1 & pma_mgmt_address==2'b00) begin
+ pma_mgmt_readdata[number_of_plls -1 :0] <= pll_pdn;
+ end
+ else if (pma_mgmt_read==1'b1 & pma_mgmt_address==2'b01) begin
+ pma_mgmt_readdata[0] <= cal_blk_pdn_reg;
+ pma_mgmt_readdata[1] <= gx_pdn;
+ end
+ else if (pma_mgmt_read==1'b1 & pma_mgmt_address==2'b10) begin
+ pma_mgmt_readdata[number_of_plls -1 :0] <= pll_locked_sync;
+ end
+ else
+ pma_mgmt_readdata <= 0;
+end
+
+generate
+genvar i;
+for (i=0; i<number_of_plls; i=i+1)
+begin: lock_sync
+ altera_std_synchronizer
+ #(
+ .depth (sync_depth) // reset pulse length in clock cycles
+ )stdsync
+ (
+ .clk(clk),
+ .din(pll_locked[i]),
+ .dout(pll_locked_sync[i]),
+ .reset_n((~ rst))
+ );
+end
+endgenerate
+
+initial
+begin
+ cal_blk_pdn_reg <= 0;
+end
+always @ (posedge clk, posedge rst)
+begin
+ if(rst) begin
+ cal_blk_pdn_reg <= 0;
+ end
+ else if (pma_mgmt_write==1'b1 & pma_mgmt_address==2'b01) begin
+ cal_blk_pdn_reg <= pma_mgmt_writedata[0];
+ end
+end
+altera_std_synchronizer
+#(
+ .depth (sync_depth) // reset pulse length in clock cycles
+)stdsync
+(
+ .clk(cal_blk_clk),
+ .din(cal_blk_pdn_reg),
+ .dout(cal_blk_pdn),
+ .reset_n((~ rst))
+);
+
+assign gx_pdn = gx_pdn_reg | gx_pdn_int;
+initial
+begin
+ gx_pdn_reg <= 0;
+end
+always @ (posedge clk, posedge rst)
+begin
+ if(rst) begin
+ gx_pdn_reg <= 0;
+ end
+ else if (pma_mgmt_write==1'b1 & pma_mgmt_address==2'b01) begin
+ gx_pdn_reg <= pma_mgmt_writedata[1];
+ end
+ else begin
+ gx_pdn_reg <= gx_pdn_reg;
+ end
+
+end
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_pma_functions.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_pma_functions.sv
new file mode 100644
index 0000000000000000000000000000000000000000..3b2ad149729abe8a029617dbbf1964bb6ce925dc
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_pma_functions.sv
@@ -0,0 +1,73 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common functions for PMA serdes
+//
+// $Header$
+//
+// PACKAGE DECLARATION
+package alt_pma_functions;
+
+ // convert "xx.xxx MHz" to ps
+ function integer freq2ps;
+ input [8*16:1] s;
+
+ integer in_freq_khz;
+ integer period_ps;
+
+ in_freq_khz = mega2k(s);
+ freq2ps = 1000000000/(in_freq_khz);
+ endfunction
+
+
+ // convert "xx.xxx MHz" string to integer with hz as unit
+ function integer mega2k;
+ input [8*16:1] s;
+
+ reg [8*16:1] reg_s;
+ reg [8:1] digit;
+ reg [8:1] tmp;
+ integer m, magnitude;
+ integer final_mag;
+ integer unit_mag;
+ integer point_pos;
+
+ begin
+ magnitude = 0;
+ reg_s = s;
+ unit_mag = 1000000;
+ point_pos = 0;
+ for (m=1; m<=16; m=m+1)
+ begin
+ tmp = reg_s[128:121];
+ digit = tmp & 8'b00001111;
+ reg_s = reg_s << 8;
+ // Accumulate ascii digits 0-9 only.
+ if (tmp == 77)
+ unit_mag = 1000; // Found a 'M' character, Mhz
+ if (tmp == 46)
+ point_pos = 1; // Found a '.' character, point
+ if ((tmp>=48) && (tmp<=57)) begin
+ magnitude = (magnitude * 10) + digit;
+ point_pos = point_pos *10;
+ end
+ end
+ if(point_pos > 0)
+ mega2k = magnitude*unit_mag/point_pos;
+ else
+ mega2k = magnitude*unit_mag;
+ end
+ endfunction
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_reset_ctrl_lego.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_reset_ctrl_lego.sv
new file mode 100644
index 0000000000000000000000000000000000000000..38d99a0658aa5380a62046e68a3b66cb9158881b
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_reset_ctrl_lego.sv
@@ -0,0 +1,265 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Reset controller building block.
+//
+// Handles a single reset stage. Can be daisy-chained with other blocks for purely sequential resets.
+// Options include reset pulse length in clock cycles, and a counter for sdone stability checking.
+//
+// $Header$
+//
+
+`timescale 1 ns / 1 ns
+
+module alt_reset_ctrl_lego
+#(
+ parameter reset_hold_til_rdone = 0, // 1 means reset stays high until rdone arrives
+ // 0 means fixed pulse length, defined by reset_hold_cycles
+ parameter reset_hold_cycles = 1, // reset pulse length in clock cycles
+ parameter sdone_delay_cycles = 0, // optional delay from rdone received til sdone sent to next block
+ parameter rdone_is_edge_sensitive = 0 // default is level sensitive rdone
+)
+(
+ // clocks and PLLs
+ input wire clock,
+ input wire start,
+ input tri0 aclr, // active-high asynchronous reset
+ output wire reset,
+ input tri1 rdone, // reset done signal
+ output reg sdone // sequence done for this lego
+);
+ localparam max_precision = 32; // VCS requires this declaration outside the function
+ function integer ceil_log2;
+ input [max_precision-1:0] input_num;
+ integer i;
+ reg [max_precision-1:0] try_result;
+ begin
+ i = 0;
+ try_result = 1;
+ while ((try_result << i) < input_num && i < max_precision)
+ i = i + 1;
+ ceil_log2 = i;
+ end
+ endfunction
+
+ // How many bits are needed for 'reset_hold_cycles' counter?
+ localparam rhc_bits = ceil_log2(reset_hold_cycles);
+ localparam rhc_load_constant = (1 << rhc_bits) | (reset_hold_cycles-1);
+ // How many bits are needed for 'sdone_delay_cycles' counter?
+ localparam sdc_bits = ceil_log2(sdone_delay_cycles);
+ localparam sdc_load_constant = (1 << sdc_bits)
+ | ((rdone_is_edge_sensitive == 1 && sdone_delay_cycles > 1) ? sdone_delay_cycles-2 : sdone_delay_cycles-1);
+ localparam sdone_stable_cycles = (sdone_delay_cycles > 1 ? sdone_delay_cycles+1 : 0);
+
+ wire spulse; // synchronous detection of 'start' 0-to-1 transition
+ wire rhold;
+ wire timed_reset_in_progress;
+ wire rinit_next; // combinatorial input to rinit DFF
+ wire rdonei; // internal selector between rdone and rdsave (rdone_is_edge_sensitive==1)
+ wire rdpulse; // synchronous detection of 'rdone' 0-to-1 transition, when rdone_is_edge_sensitive==1
+
+ reg zstart = 0; // delayed value of 'start' input, used for detection of 0-to-1 transition
+ reg rinit = 0; // state bit that indicates sequence is in progress
+
+ initial begin
+ sdone = 0; // 1 indicates sequence is done
+ end
+
+
+ // 'start' input, detect 0-to-1 transition that triggers sequence
+ assign spulse = start & ~zstart;
+ always @(posedge clock or posedge aclr)
+ if (aclr == 1'b1)
+ zstart <= 0;
+ else
+ zstart <= start;
+
+ // rinit state bit, triggered by spulse, waits while rhold = 1
+ assign rinit_next = spulse | (rinit & (rhold | ~rdonei | rdpulse)) | timed_reset_in_progress;
+ always @(posedge clock or posedge aclr)
+ if (aclr == 1'b1)
+ rinit <= 0;
+ else
+ rinit <= rinit_next;
+
+ // optional internal 'rdone' generation logic, if rdone_is_edge_sensitive==1
+ generate
+ if (rdone_is_edge_sensitive == 0) begin
+ assign rdpulse = 0;
+ assign rdonei = rdone;
+ end
+ else begin
+ // instantiate synchronous edge-detection logic for rdone
+ reg zrdone = 0; // for edge-sensitive rdone, detect 0-to-1 transition synchronously
+ reg rdsave = 0; // for edge-sensitive rdone, use this as internal rdone
+ always @(posedge clock or posedge aclr) begin
+ if (aclr == 1'b1) begin
+ zrdone <= 0;
+ rdsave <= 0;
+ end
+ else begin
+ zrdone <= rdone; // previous value of rdone for synchronous edge detection
+ rdsave <= ~spulse & (rdpulse | rdsave);
+ end
+ end
+ assign rdpulse = rdone & ~zrdone;
+ assign rdonei = rdsave;
+ end
+ endgenerate
+
+ // rhold depends on sdone_delay_cycles and rdone_is_edge_sensitive
+ generate
+ if (sdone_delay_cycles == 0 || (sdone_delay_cycles == 1 && rdone_is_edge_sensitive == 1))
+ assign rhold = ~rdonei; // sdone_delay_cycles=0
+ else begin
+ // declare only when needed to avoid Quartus synthesis warnings
+ reg [sdc_bits:0] rhold_reg = 0; // for sdone_delay_cycles > 0
+ if (sdone_delay_cycles == 1) begin
+ always @(posedge clock or posedge aclr) begin
+ if (aclr == 1'b1)
+ rhold_reg <= 0;
+ else
+ rhold_reg <= ~(rinit & rdonei);
+ end
+ assign rhold = rhold_reg[0]; // sdone_delay_cycles=1
+ end
+ else begin
+ // need to count cycles to make sure rdone is stable
+ always @(posedge clock or posedge aclr)
+ begin
+ if (aclr == 1'b1)
+ rhold_reg <= 0;
+ else if ((rinit & rdonei & ~rdpulse) == 0)
+ // keep load value until rinit & rdone both high, and no new rdone pulses
+ rhold_reg <= sdc_load_constant[sdc_bits:0];
+ else
+ rhold_reg <= rhold_reg - 1'b1;
+ end
+ assign rhold = rhold_reg[sdc_bits]; // sdone_delay_cycles > 1
+ end
+ end
+ endgenerate
+
+ // sdone state bit indicates that reset sequence completed. Clear again on 'start'
+ always @(posedge clock or posedge aclr)
+ if (aclr == 1'b1)
+ sdone <= 0;
+ else
+ sdone <= ~spulse & (sdone | (rinit & ~rinit_next));
+
+ // reset pulse generation logic depends on 2 parameters
+ generate
+ if (reset_hold_til_rdone == 1) begin
+ assign reset = rinit;
+ assign timed_reset_in_progress = 0;
+ end
+ else if (reset_hold_cycles < 1) begin // 0 is legal, but catch negative (illegal) values too
+ assign reset = spulse;
+ assign timed_reset_in_progress = 0;
+ end
+ else begin
+ // declare only when needed to avoid Quartus synthesis warnings
+ reg [rhc_bits:0] zspulse = 0; // bits for reset pulse if fixed length
+ assign timed_reset_in_progress = zspulse[rhc_bits];
+ assign reset = zspulse[rhc_bits];
+
+ if (reset_hold_cycles == 1)
+ // a single-cycle reset pulse needs 1 register
+ always @(posedge clock or posedge aclr)
+ if (aclr == 1'b1)
+ zspulse <= 0;
+ else
+ zspulse <= spulse;
+ else begin
+ // multi-cycle reset pulse needs a counter
+ always @(posedge clock or posedge aclr)
+ begin
+ if (aclr == 1'b1)
+ zspulse <= 0;
+ else if (spulse == 1)
+ zspulse <= rhc_load_constant[rhc_bits:0];
+ else if (zspulse[rhc_bits] == 1)
+ zspulse <= zspulse - 1'b1;
+ end
+ end
+ end
+ endgenerate
+
+// generate
+// case (reset_hold_til_rdone)
+// 0 : m1 U1 (a, b, c);
+// 2 : m2 U1 (a, b, c);
+// default : m3 U1 (a, b, c);
+// endcase
+// endgenerate
+
+ // general assertions
+ //synopsys translate_off
+ // vlog/vcs/ncverilog: +define+ALTERA_XCVR_ASSERTIONS
+`ifdef ALTERA_XCVR_ASSERTIONS
+ // when rdone is edge sensitive, last rdone +ve edge triggers sdone +ve edge,
+ // 'sdone_delay_cycles' later. "##1 1" is an always-true cycle to match $rise(sdone)
+ sequence rdone_last_edge;
+ @(posedge clock) $rose(rdone) ##1 !$rose(rdone) [*sdone_delay_cycles] ##1 1;
+ endsequence
+
+ // when rdone is level sensitive, stable rdone for 'sdone_delay_cycles' consecutive cycles
+ // triggers sdone +ve edge. "##1 1" is an always-true cycle to match $rise(sdone)
+ sequence rdone_stable_level;
+ @(posedge clock) rdone [*(sdone_delay_cycles+1)] ##1 1;
+ endsequence
+
+// Most assertions aren't valid when 'aclr' is active
+//`define assert_awake(arg) assert property (disable iff (aclr) arg )
+ always @(aclr)
+ if (aclr) $assertkill;
+ else $asserton;
+
+ generate
+ always @(posedge clock) begin
+ // A rising edge on start will result in reset high within 1 clock cycle
+ assert property ($rose(start & ~aclr) |-> ##[0:1] reset);
+ // A rising edge on reset will result in sdone low within 1 clock cycle
+ assert property ($rose(reset) |-> ##[0:1] !sdone);
+
+ // assertions for optional behavior: reset pulse length options
+ if (reset_hold_til_rdone == 0 && reset_hold_cycles > 1)
+ // Verify fixed-length reset pulse option
+ assert property ($rose(reset) |-> reset [*reset_hold_cycles] ##1 !reset)
+ else $error("Reset pulse length should be %d", reset_hold_cycles);
+ if (reset_hold_til_rdone == 0 && reset_hold_cycles == 1)
+ // Verify fixed 1-length reset pulse option
+ assert property ($rose(reset) |=> !reset);
+ if (reset_hold_til_rdone == 0 && reset_hold_cycles == 0)
+ // Verify minimal-length reset pulse option, which mirrors 'start' edge detection
+ assert property ($rose(start & ~aclr) |-> reset ##1 !reset);
+ if (reset_hold_til_rdone == 1) begin
+ // with hold-til-rdone, reset should not deassert until after rdone asserts, then deassert immediately
+ assert property ($rose(reset) && !rdone |=> $stable(reset) [*0:$] ##1 (reset && rdone) ##1 !reset);
+ assert property ($rose(reset) && rdone ##1 rdone [*sdone_delay_cycles] |=> !reset); // rdone was already high
+ //assert property ($rose(reset) && !rdone |-> ##[0:$] rdone ##1 !reset);
+ end
+
+ // assertions for optional behavior: sdone delay options and rdone edge sensitive option
+ if (rdone_is_edge_sensitive == 1)
+ // rdone edge-sensitive option only has an effect when sdone_delay_cycles > 0
+ assert property ($rose(sdone) |-> rdone_last_edge.ended);
+ if (rdone_is_edge_sensitive == 0)
+ // rdone defaults to level-sensitive
+ assert property ($rose(sdone) |-> (rdone_stable_level.ended or $past($fell(reset),1)));
+ end
+ endgenerate
+`endif // ALTERA_XCVR_ASSERTIONS
+ //synopsys translate_on
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_reset_ctrl_tgx_cdrauto.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_reset_ctrl_tgx_cdrauto.sv
new file mode 100644
index 0000000000000000000000000000000000000000..d785de6ee8eb397584ea1833c7e8a7ddf5c3b045
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_reset_ctrl_tgx_cdrauto.sv
@@ -0,0 +1,201 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Reset controller for Stratix IV transceivers with RX CDR in auto-lock mode.
+//
+// Uses alt_reset_ctrl_lego to handle each reset stage, with 3 required for the overall sequence.
+// Parameter defaults for pll-powerdown and lock-to-data-auto timers assume 50 MHz system clock
+//
+// $Header$
+//
+
+`timescale 1 ns / 1 ns
+
+(* altera_attribute = "-name MERGE_TX_PLL_DRIVEN_BY_REGISTERS_WITH_SAME_CLEAR ON -to \"alt_reset_ctrl_lego:lego_pll_powerdown|zspulse\" " *)
+module alt_reset_ctrl_tgx_cdrauto
+#(
+ parameter sys_clk_in_mhz = 50 // needed for 1us and 4us delay timers
+)
+(
+ // User inputs and outputs
+ input wire clock,
+ input wire reset_all,
+ input tri0 reset_tx_digital,
+ input tri0 reset_rx_digital,
+ input wire powerdown_all,
+ output wire tx_ready,
+ output wire rx_ready,
+
+ // I/O to Stratix IV transceiver control & status
+ output wire pll_powerdown, // reset TX PLL
+ output wire tx_digitalreset, // reset TX PCS
+ output wire rx_analogreset, // reset RX PMA
+ output wire rx_digitalreset, // reset RX PCS
+ output wire gxb_powerdown, // powerdown whole quad
+ input wire pll_is_locked, // TX PLL is locked status
+ input tri0 tx_cal_busy, // TX channel calibration status
+ input tri0 rx_cal_busy, // RX channel calibration status
+ input tri1 rx_is_lockedtodata, // RX CDR PLL is locked to data status
+ input tri0 manual_mode // 0=Automatically reset RX after loss of rx_is_lockedtodata
+);
+
+localparam clk_in_mhz =
+`ifdef QUARTUS__SIMGEN
+ 2; // simulation-only value
+`elsif ALTERA_RESERVED_QIS
+ sys_clk_in_mhz; // use real counter lengths for normal Quartus synthesis
+`else
+ 2; // simulation-only value
+`endif
+localparam t_pll_powerdown = clk_in_mhz; // 1 us minimum
+localparam t_ltd_auto = clk_in_mhz*4; // 4 us minimum
+
+
+wire pll_is_locked_r; // pll_is_locked resynchronized
+wire tx_cal_busy_r; // tx_cal_busy resynchronized
+wire rx_cal_busy_r; // rx_cal_busy resynchronized
+wire rx_is_lockedtodata_r; // rx_is_lockedtodata resynchronized
+
+wire sdone_lego_pll_powerdown; // 'sequence done' output of pll_powerdown lego
+wire sdone_lego_tx_digitalreset;// 'sequence done' output of tx_digitalreset lego
+wire sdone_lego_rx_digitalreset;// 'sequence done' output of rx_digitalreset lego
+wire sdone_lego_rx_analogreset; // 'sequence done' output of rx_analogreset lego
+wire wire_tx_digital_only_reset;// reset output for TX digital-only
+wire wire_rx_digital_only_reset;// reset output for RX digital-only
+wire wire_tx_digitalreset; // TX digital full-reset source
+wire wire_rx_digitalreset; // RX digital full-reset source
+wire wire_rx_digital_retrigger; // Trigger new RX digital sequence after main sequence completes, and lose lock-to-data
+
+// Resynchronize input signals
+alt_xcvr_resync #(
+ .WIDTH(2)
+ ) alt_xcvr_resync_inst_0 (
+ .clk (clock),
+ .reset (1'b0),
+ .d ({pll_is_locked ,rx_is_lockedtodata }),
+ .q ({pll_is_locked_r,rx_is_lockedtodata_r})
+);
+
+alt_xcvr_resync #(
+ .WIDTH(2),
+ .INIT_VALUE(1)
+ ) alt_xcvr_resync_inst_1 (
+ .clk (clock),
+ .reset (1'b0),
+ .d ({rx_cal_busy,tx_cal_busy}),
+ .q ({rx_cal_busy_r,tx_cal_busy_r})
+);
+
+// First reset ctrl sequencer lego is for pll_powerdown generation
+alt_reset_ctrl_lego #(
+ .reset_hold_cycles(t_pll_powerdown) // hold pll_powerdown for 1us
+ ) lego_pll_powerdown ( .clock(clock),
+ .start(reset_all), // Do not use resynched version of reset_all here
+ .aclr(powerdown_all),
+ .reset(pll_powerdown),
+ .rdone(pll_is_locked_r),
+ .sdone(sdone_lego_pll_powerdown));
+
+// next reset ctrl sequencer lego is for tx_digitalreset generation
+alt_reset_ctrl_lego #(
+ .reset_hold_til_rdone(1) // hold until rdone arrives for this test case
+ ) lego_tx_digitalreset ( .clock(clock),
+ .start(reset_all),
+ .aclr(powerdown_all),
+ .reset(wire_tx_digitalreset),
+ .rdone(sdone_lego_pll_powerdown & ~tx_cal_busy_r),
+ .sdone(sdone_lego_tx_digitalreset));
+
+// next reset ctrl sequencer lego is for rx_analogreset generation
+alt_reset_ctrl_lego #(
+ .reset_hold_til_rdone(1), // hold until rdone arrives for this test case
+ .sdone_delay_cycles(2) // hold rx_analogreset 2 parallel_clock cycles after offset cancellation done
+ ) lego_rx_analogreset ( .clock(clock),
+ .start(reset_all),
+ .aclr(powerdown_all),
+ .reset(rx_analogreset),
+ .rdone(sdone_lego_tx_digitalreset & ~rx_cal_busy_r),
+ .sdone(sdone_lego_rx_analogreset));
+
+// last reset ctrl sequencer lego is for rx_digitalreset generation
+alt_reset_ctrl_lego #(
+ .reset_hold_til_rdone(1), // hold until rdone arrives for this test case
+ .sdone_delay_cycles(t_ltd_auto) // hold rx_digitalreset for 4us
+ ) lego_rx_digitalreset ( .clock(clock),
+ .start(~manual_mode & reset_all | wire_rx_digital_retrigger),
+ .aclr(powerdown_all),
+ .reset(wire_rx_digitalreset),
+ .rdone(sdone_lego_rx_analogreset & rx_is_lockedtodata_r),
+ .sdone(sdone_lego_rx_digitalreset));
+
+//////////// digital-only reset ////////////
+// separate reset ctrl sequencer lego for digital-only reset generation
+alt_reset_ctrl_lego #(
+ .reset_hold_cycles(3) // hold 2 parallel clock cycles (assumes sysclk slower or same freq as parallel clock)
+ ) lego_tx_digitalonly ( .clock(clock),
+ .start(reset_tx_digital | reset_all),
+ .aclr(powerdown_all),
+ .reset(wire_tx_digital_only_reset),
+ .rdone(sdone_lego_tx_digitalreset),
+ .sdone(tx_ready)); // TX status indicator for user
+
+alt_reset_ctrl_lego #(
+ .reset_hold_cycles(3) // hold 2 parallel clock cycles (assumes sysclk slower or same freq as parallel clock)
+ ) lego_rx_digitalonly ( .clock(clock),
+ .start(reset_rx_digital | (reset_all & ~manual_mode) | wire_rx_digital_retrigger),
+ .aclr(powerdown_all),
+ .reset(wire_rx_digital_only_reset),
+ .rdone(sdone_lego_rx_digitalreset),
+ .sdone(rx_ready)); // RX status indicator for user
+
+// digital resets have 2 possible sources: full-reset or digital-only
+assign tx_digitalreset = wire_tx_digitalreset | wire_tx_digital_only_reset;
+assign rx_digitalreset = wire_rx_digitalreset | wire_rx_digital_only_reset;
+
+// re-trigger RX digital sequence when main sequence is complete (indicated by sdone_lego_rx_digitalreset)
+// not manual mode, and lose lock-to-data
+assign wire_rx_digital_retrigger = ~manual_mode & sdone_lego_rx_digitalreset & ~rx_is_lockedtodata_r;
+
+// Quad power-down
+assign gxb_powerdown = powerdown_all;
+
+
+////////////////////////
+// general assertions
+//synopsys translate_off
+// vlog/vcs/ncverilog: +define+ALTERA_XCVR_ASSERTIONS
+`ifdef ALTERA_XCVR_ASSERTIONS
+always @(posedge clock) begin
+ // reset_all starts by triggering CMU PLL powerdown
+ assert property ($rose(reset_all) |=> $rose(pll_powerdown));
+ // While CMU PLL powerdown is asserted, all other resets must be asserted
+ assert property (pll_powerdown |-> (tx_digitalreset & rx_analogreset & rx_digitalreset));
+ // While rx_analogreset is asserted, rx_digitalreset must be asserted
+ assert property (rx_analogreset |-> rx_digitalreset);
+ // When pll_is_locked is asserted, tx_digitalreset must be deasserted
+ assert property ($rose(pll_is_locked_r) |-> ##[0:2] !tx_digitalreset);
+ // During a reset, rx_digitalreset should remain high for t_ltd_auto after rx_is_lockedtodata rising edge
+ assert property ($rose(rx_is_lockedtodata_r) & ~manual_mode|-> rx_digitalreset [*(t_ltd_auto+1)] ##1 !rx_digitalreset);
+ assert property ($rose(rx_is_lockedtodata_r) & manual_mode|->!rx_digitalreset);
+ // reset_tx_digital results in only a brief pulse on tx_digitalreset
+ assert property ($rose(reset_tx_digital) |=> tx_digitalreset [*3] );
+ assert property ($rose(reset_tx_digital) & tx_ready |=> tx_digitalreset [*3] ##1 ~tx_digitalreset ##1 $rose(tx_ready) );
+ // reset_rx_digital results in only a brief pulse on rx_digitalreset
+ assert property ($rose(reset_rx_digital) |=> rx_digitalreset [*3] );
+ assert property ($rose(reset_rx_digital) & rx_ready |=> rx_digitalreset [*3] ##1 ~rx_digitalreset ##1 $rose(rx_ready) );
+end
+`endif
+//synopsys translate_on
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_arbiter.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_arbiter.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5b0e914d4dea0be5e022a29a6df73240a4f4f29e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_arbiter.sv
@@ -0,0 +1,64 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Clocked priority encoder with state
+//
+// On each clock cycle, updates state to show which request is granted.
+// Most recent grant holder is always the highest priority.
+// If current grant holder is not making a request, while others are,
+// then new grant holder is always the requester with lowest bit number.
+// If no requests, current grant holder retains grant state
+
+// $Header$
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_arbiter #(
+ parameter width = 2
+) (
+ input wire clock,
+ input wire [width-1:0] req, // req[n] requests for this cycle
+ output reg [width-1:0] grant // grant[n] means requester n is grantee in this cycle
+);
+
+ wire idle; // idle when no requests
+ wire [width-1:0] keep; // keep[n] means requester n is requesting, and already has the grant
+ // Note: current grantee is always highest priority for next grant
+ wire [width-1:0] take; // take[n] means requester n is requesting, and there are no higher-priority requests
+
+ assign keep = req & grant; // current grantee is always highest priority for next grant
+ assign idle = ~| req; // idle when no requests
+
+ initial begin
+ grant = 0;
+ end
+
+ // grant next state depends on current grant and take priority
+ always @(posedge clock) begin
+ grant <= keep // if current grantee is requesting, gets to keep grant
+ | ({width{idle}} & grant) // if no requests, grant state remains unchanged
+ | take; // take applies only if current grantee is not requesting
+ end
+
+ // 'take' bus encodes priority. Request with lowest bit number wins when current grantee not requesting
+ assign take[0] = req[0]
+ & (~| (keep & ({width{1'b1}} << 1))); // no 'keep' from lower-priority inputs
+ genvar i;
+ generate
+ for (i=1; i < width; i = i + 1) begin : arb
+ assign take[i] = req[i]
+ & (~| (keep & ({width{1'b1}} << (i+1)))) // no 'keep' from lower-priority inputs
+ & (~| (req & {i{1'b1}})); // no 'req' from higher-priority inputs
+ end
+ endgenerate
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_csr_common.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_csr_common.sv
new file mode 100644
index 0000000000000000000000000000000000000000..dbe3e5a5fcf1db4a9ce64efc08efa2005e19cbe8
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_csr_common.sv
@@ -0,0 +1,209 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common control & status register map for transceiver PHY IP
+// Applies to Stratix V-generation basic PHY components
+//
+// $Header$
+//
+
+`timescale 1 ps / 1 ps
+
+module alt_xcvr_csr_common #(
+ parameter lanes = 1,
+ parameter plls = 1
+)
+(
+ // user data (avalon-MM formatted)
+ input wire clk,
+ input tri0 reset,
+ input wire [7:0] address,
+ input tri1 read,
+ output reg [31:0] readdata = 0,
+ input tri0 write,
+ input wire [31:0] writedata,
+
+ // transceiver status inputs to this CSR
+ input wire [plls - 1 : 0] pll_locked,
+ input wire [lanes - 1 : 0] rx_is_lockedtoref,
+ input wire [lanes - 1 : 0] rx_is_lockedtodata,
+ input wire [lanes - 1 : 0] rx_signaldetect,
+
+ // reset controller outputs
+ input wire reset_controller_tx_ready,
+ input wire reset_controller_rx_ready,
+ input wire reset_controller_pll_powerdown,
+ input wire reset_controller_tx_digitalreset,
+ input wire reset_controller_rx_analogreset,
+ input wire reset_controller_rx_digitalreset,
+
+ // read/write control registers
+ // to reset controller
+ output reg csr_reset_tx_digital = 0,
+ output reg csr_reset_rx_digital = 0,
+ output reg csr_reset_all = 1, // power-up to 1 to trigger auto-init sequence
+ // to PMA and PCS reset inputs
+ output wire csr_pll_powerdown, // reset controller or manual
+ output wire [lanes - 1 : 0] csr_tx_digitalreset, // reset controller or manual
+ output wire [lanes - 1 : 0] csr_rx_analogreset, // reset controller or manual
+ output wire [lanes - 1 : 0] csr_rx_digitalreset, // reset controller or manual
+ // common PMA controls
+ output reg [lanes - 1 : 0] csr_phy_loopback_serial = 0,
+ output reg [lanes - 1 : 0] csr_rx_set_locktoref = 0,
+ output reg [lanes - 1 : 0] csr_rx_set_locktodata = 0
+);
+ import alt_xcvr_csr_common_h::*;
+
+ localparam sync_stages = 2; // number of sync stages for transceiver status signals
+ localparam sync_stages_str = "2"; // number of sync stages specified as string (for timing constraints)
+ integer stage;
+
+ // Parameter strings for embedded timing constraints
+ localparam CSR_PLLLOCKED_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_common*csr_pll_locked*[",sync_stages_str,"]*]\""};
+ localparam CSR_RXISLOCKED_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_common*csr_rx_is_locked*[",sync_stages_str,"]*]\""};
+ localparam CSR_RXSIGNALDET_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_common*csr_rx_signaldetect*[",sync_stages_str,"]*]\""};
+ localparam SDC_CONSTRAINTS = {CSR_PLLLOCKED_CONSTRAINT,";",CSR_RXISLOCKED_CONSTRAINT,";",CSR_RXSIGNALDET_CONSTRAINT};
+
+ // internal control registers
+ reg [lanes - 1 : 0] csr_interrupt_ch_bitmask = {lanes{1'b1}};
+ // fine reset control. 'OR' with reset controller equivalent signals
+ reg csr_reset_or_pll_powerdown = 0; // fine reset control
+ reg csr_reset_or_reset_tx_digital = 0; // fine reset control
+ reg csr_reset_or_reset_rx_analog = 0; // fine reset control
+ reg csr_reset_or_reset_rx_digital = 0; // fine reset control
+ reg [lanes - 1 : 0] csr_reset_ch_bitmask = {lanes{1'b1}};
+
+ // read-only status registers
+ // These are synchronized forms of transceiver status signals
+ // async inputs go to reg [sync_stages], and come out synchronized at reg [1]
+ (* altera_attribute = SDC_CONSTRAINTS *) // Apply timing constraints (does not matter which node)
+ reg [plls - 1 : 0] csr_pll_locked [sync_stages:1];
+ reg [lanes - 1 : 0] csr_rx_is_lockedtoref [sync_stages:1];
+ reg [lanes - 1 : 0] csr_rx_is_lockedtodata [sync_stages:1];
+ reg [lanes - 1 : 0] csr_rx_signaldetect [sync_stages:1];
+
+ always @(posedge clk or posedge reset) begin
+ if (reset == 1) begin
+ readdata <= 0;
+ csr_interrupt_ch_bitmask <= {lanes{1'b1}};
+
+ csr_reset_tx_digital <= 0;
+ csr_reset_rx_digital <= 0;
+ csr_reset_all <= 1; // reset to 1 to trigger auto-init sequence
+ csr_reset_ch_bitmask <= {lanes{1'b1}};
+ csr_reset_or_pll_powerdown <= 0; // fine reset control
+ csr_reset_or_reset_tx_digital <= 0; // fine reset control
+ csr_reset_or_reset_rx_analog <= 0; // fine reset control
+ csr_reset_or_reset_rx_digital <= 0; // fine reset control
+
+ csr_phy_loopback_serial <= 0;
+ csr_rx_set_locktoref <= 0;
+ csr_rx_set_locktodata <= 0;
+ end
+ else begin
+ // decode read & write for each supported address
+ case (address)
+ // interrupt control
+ ADDR_INTERRUPT_CH_BITMASK: begin
+ readdata <= (32'd0 | csr_interrupt_ch_bitmask);
+ if (write) csr_interrupt_ch_bitmask <= writedata[lanes-1:0];
+ end
+
+ // reset control
+ ADDR_RESET_CONTROL: begin
+ // on read, returns two bits: bit0: TX ready, bit1: RX ready
+ readdata <= (32'd0 | {reset_controller_rx_ready, reset_controller_tx_ready});
+ // on write, bit0 is 'reset_tx_digital', bit1 is 'reset_rx_digital', bit2 is 'reset_all'
+ //if (write) begin
+ // reset_all write side-effect: when write a '1', force all reset_ch_bitmask bits to '1'
+ // csr_reset_ch_bitmask <= csr_reset_ch_bitmask | {(lanes){writedata[2]}};
+ //end
+ end
+ ADDR_RESET_CH_BITMASK: begin
+ readdata <= (32'd0 | csr_reset_ch_bitmask);
+ if (write) csr_reset_ch_bitmask <= writedata[lanes-1:0];
+ end
+
+ // loopback control
+ ADDR_PHY_LOOPBACK_SERIAL,
+ ADDR_PMA_LOOPBACK_SERIAL: begin
+ readdata <= (32'd0 | csr_phy_loopback_serial);
+ if (write) csr_phy_loopback_serial <= writedata[lanes-1:0];
+ end
+
+ // PMA control and status
+ ADDR_PMA_RX_SET_LOCKTOREF: begin
+ readdata <= (32'd0 | csr_rx_set_locktoref);
+ if (write) csr_rx_set_locktoref <= writedata[lanes-1:0];
+ end
+ ADDR_PMA_RX_SET_LOCKTODATA: begin
+ readdata <= (32'd0 | csr_rx_set_locktodata);
+ if (write) csr_rx_set_locktodata <= writedata[lanes-1:0];
+ end
+ // PMA status (read-only)
+ ADDR_PMA_PLL_IS_LOCKED: readdata <= (32'd0 | csr_pll_locked[1]);
+ ADDR_PMA_RX_IS_LOCKEDTOREF: readdata <= (32'd0 | csr_rx_is_lockedtoref[1]);
+ ADDR_PMA_RX_IS_LOCKEDTODATA: readdata <= (32'd0 | csr_rx_is_lockedtodata[1]);
+ ADDR_PMA_RX_SIGNALDETECT: readdata <= (32'd0 | csr_rx_signaldetect[1]);
+
+ // Fine reset control - device dependent
+ ADDR_RESET_FINE_CONTROL: begin
+ // bit 0: 'pll_powerdown', 1: 'reset_tx_digital', 2: 'reset_rx_analog', 3: 'reset_rx_digital'
+
+ readdata <= (32'd0 | {csr_reset_or_reset_rx_digital, csr_reset_or_reset_rx_analog,
+ csr_reset_or_reset_tx_digital, csr_reset_or_pll_powerdown});
+ if (write) begin
+ csr_reset_or_pll_powerdown <= writedata[0]; // fine reset control
+ csr_reset_or_reset_tx_digital <= writedata[1]; // fine reset control
+ csr_reset_or_reset_rx_analog <= writedata[2]; // fine reset control
+ csr_reset_or_reset_rx_digital <= writedata[3]; // fine reset control
+ end
+ end
+
+
+ default: readdata <= ~ 32'd0; // use too many LEs?
+ endcase
+
+ // special handling for registers that must auto-clear on cycle after a write
+ // reset control. on write, bit0 is 'reset_tx_digital', bit1 is 'reset_rx_digital', bit2 is 'reset_all'
+ csr_reset_tx_digital <= (address == ADDR_RESET_CONTROL) & write & writedata[0];
+ csr_reset_rx_digital <= (address == ADDR_RESET_CONTROL) & write & writedata[1];
+ csr_reset_all <= (address == ADDR_RESET_CONTROL) & write & writedata[2];
+
+ // synchronization registers for status signals from transceivers
+ csr_pll_locked[sync_stages] <= pll_locked; // input from transceiver
+ csr_rx_is_lockedtoref[sync_stages] <= rx_is_lockedtoref;
+ csr_rx_is_lockedtodata[sync_stages] <= rx_is_lockedtodata;
+ csr_rx_signaldetect[sync_stages] <= rx_signaldetect;
+ for (stage=2; stage <= sync_stages; stage = stage + 1) begin
+ // additional sync stages
+ csr_pll_locked[stage-1] <= csr_pll_locked[stage];
+ csr_rx_is_lockedtoref[stage-1] <= csr_rx_is_lockedtoref[stage];
+ csr_rx_is_lockedtodata[stage-1] <= csr_rx_is_lockedtodata[stage];
+ csr_rx_signaldetect[stage-1] <= csr_rx_signaldetect[stage];
+ end
+ end
+ end
+
+ // combine reset controller and CSR manual reset control settings
+ assign csr_pll_powerdown = reset_controller_pll_powerdown; // cut manual PLL reset path
+ // | csr_reset_or_pll_powerdown;
+ assign csr_tx_digitalreset = csr_reset_ch_bitmask & {(lanes)
+ {reset_controller_tx_digitalreset | csr_reset_or_reset_tx_digital}};
+ assign csr_rx_analogreset = csr_reset_ch_bitmask & {(lanes)
+ {reset_controller_rx_analogreset | csr_reset_or_reset_rx_analog}};
+ assign csr_rx_digitalreset = csr_reset_ch_bitmask & {(lanes)
+ {reset_controller_rx_digitalreset | csr_reset_or_reset_rx_digital}};
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_csr_common_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_csr_common_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..a323c0a2a16722d20880e2fd2d694fe5031fe780
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_csr_common_h.sv
@@ -0,0 +1,61 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common control & status register map for transceiver PHY IP
+// Applies to Stratix V-generation basic PHY components
+//
+// $Header$
+//
+// PACKAGE DECLARATION
+
+`timescale 1 ps / 1 ps
+
+package alt_xcvr_csr_common_h;
+
+ localparam alt_xcvr_csr_addr_width = 8;
+
+ // register bitmap ---------------------------------------------------------
+ // common blocks, interrupt control
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_INTERRUPT_CH_BITMASK = 1;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_INTERRUPT_ENABLE_BITMASK = 2;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_INTERRUPT_SOURCE = 3;
+
+ // common blocks, loopback control
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PHY_LOOPBACK_SERIAL = 6;
+
+ // common blocks, reset control
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_RESET_CONTROL_BASE = 64;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_RESET_CH_BITMASK = ADDR_RESET_CONTROL_BASE + 8'd1;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_RESET_CONTROL = ADDR_RESET_CONTROL_BASE + 8'd2;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_RESET_FINE_CONTROL = ADDR_RESET_CONTROL_BASE + 8'd4;
+
+ // common blocks, PMA common control & status
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_COMMON_BASE = 32;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_PLL_IS_LOCKED = ADDR_PMA_COMMON_BASE + 8'd2;
+ // common blocks, PMA channel control & status
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_CHANNEL_BASE = 96;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_LOOPBACK_SERIAL = ADDR_PMA_CHANNEL_BASE + 8'd1;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_RX_SIGNALDETECT = ADDR_PMA_CHANNEL_BASE + 8'd3;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_RX_SET_LOCKTODATA = ADDR_PMA_CHANNEL_BASE + 8'd4;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_RX_SET_LOCKTOREF = ADDR_PMA_CHANNEL_BASE + 8'd5;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_RX_IS_LOCKEDTODATA = ADDR_PMA_CHANNEL_BASE + 8'd6;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PMA_RX_IS_LOCKEDTOREF = ADDR_PMA_CHANNEL_BASE + 8'd7;
+
+ // external block for PCS control & status
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS_BASE = 128; // 128-255
+
+ // First word in every PCS CSR is lane # (or lane group # as appropriate)
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS_LANE_GROUP = ADDR_PCS_BASE + 8'd0;
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_csr_pcs8g.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_csr_pcs8g.sv
new file mode 100644
index 0000000000000000000000000000000000000000..62ddfa2dce74f10cf83c30cd54f72573bbf216be
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_csr_pcs8g.sv
@@ -0,0 +1,350 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common control & status register map for transceiver PHY IP
+// Applies to Stratix V-generation basic PHY components
+//
+// $Header$
+//
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_csr_pcs8g #(
+ parameter lanes = 1,
+ parameter words = 2 // for status bits that are per-word, like 8B10B status
+)
+(
+ // user data (avalon-MM formatted)
+ input wire clk,
+ input tri0 reset,
+ input wire [7:0] address,
+ input tri1 read,
+ output reg [31:0] readdata = 0,
+ input tri0 write,
+ input wire [31:0] writedata,
+
+ input wire rx_clk, // to synchronize rx control outputs
+ input wire tx_clk, // to synchronize tx control outputs
+
+ // transceiver status inputs to this CSR
+ input wire [lanes*words - 1 : 0] rx_patterndetect,
+ input wire [lanes*words - 1 : 0] rx_syncstatus,
+ input wire [lanes*words - 1 : 0] rx_errdetect,
+ input wire [lanes*words - 1 : 0] rx_disperr,
+ input wire [lanes - 1 : 0] rx_phase_comp_fifo_error,
+ input wire [lanes - 1 : 0] tx_phase_comp_fifo_error,
+ input wire [lanes*5 - 1: 0] rx_bitslipboundaryselectout,
+ input wire [lanes - 1 : 0] rlv,
+ input wire [lanes*words - 1 : 0] rx_a1a2sizeout,
+
+ // read/write control outputs
+ // PCS controls
+ output wire [lanes - 1 : 0] csr_tx_invpolarity,
+ output wire [lanes*5 - 1 : 0] csr_tx_bitslipboundaryselect,
+ output wire [lanes - 1 : 0] csr_rx_invpolarity,
+ output wire [lanes - 1 : 0] csr_rx_enapatternalign,
+ output wire [lanes - 1 : 0] csr_rx_bitreversalenable,
+ output wire [lanes - 1 : 0] csr_rx_bytereversalenable,
+ output wire [lanes - 1 : 0] csr_rx_bitslip,
+ output wire [lanes - 1 : 0] csr_rx_a1a2size
+);
+ import alt_xcvr_csr_common_h::*;
+ import alt_xcvr_csr_pcs8g_h::*;
+
+ localparam sync_stages = 2; // number of sync stages for transceiver status signals
+ localparam sync_stages_str = "2"; // number of sync stages specified as string (for timing constraints)
+ localparam LANE_REGW = 5;
+
+ // Parameter strings for embedded timing constraints
+ localparam SYNC_RX_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_pcs8g*sync_rx_*[",sync_stages_str,"]*]\""};
+ localparam SYNC_TX_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_pcs8g*sync_tx_*[",sync_stages_str,"]*]\""};
+ localparam CSR_REG_CONSTRAINT = {"-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_csr_pcs8g*csr_indexed_read_only_reg*sreg[",sync_stages_str,"]*]\""};
+ localparam SDC_CONSTRAINTS = {SYNC_RX_CONSTRAINT,";",SYNC_TX_CONSTRAINT,";",CSR_REG_CONSTRAINT};
+
+ // internal registers
+ reg [LANE_REGW-1:0] reg_lane_number = 0; // lane or group number for indirection
+
+ ////////////////////////////////////////////////////////
+ // Read/Write CSR registers with lane indirection
+ ////////////////////////////////////////////////////////
+ // Apply false path timing constraints to synchronization registers. (It does not matter as to which node these are applied).
+ (* altera_attribute = SDC_CONSTRAINTS *)
+ reg [lanes - 1 : 0] reg_tx_invpolarity = 0;
+ reg [lanes - 1 : 0] sync_tx_invpolarity [sync_stages:1]; // synchronize to tx_clk
+ wire [lanes - 1 : 0] write_tx_invpolarity; // indexed write group muxed in
+ wire [0 : 0] lane_tx_invpolarity; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_tx_invpolarity(.in_narrow(writedata[0]),
+ .in_wide(reg_tx_invpolarity), .sel(reg_lane_number),
+ .out_narrow(lane_tx_invpolarity), .out_wide(write_tx_invpolarity));
+
+ reg [lanes*5 - 1 : 0] reg_tx_bitslipboundaryselect = 0;
+ reg [lanes*5 - 1 : 0] sync_tx_bitslipboundaryselect [sync_stages:1]; //synchronize to tx_clk
+ wire [lanes*5 - 1 : 0] write_tx_bitslipboundaryselect; //indexed write group muxed in
+ wire [4:0] lane_tx_bitslipboundaryselect; //selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(5), .sel_size(LANE_REGW), .init_value(0))
+ wmux_tx_bitslipboundaryselect(.in_narrow(writedata[5:1]),
+ .in_wide(reg_tx_bitslipboundaryselect), .sel(reg_lane_number),
+ .out_narrow(lane_tx_bitslipboundaryselect), .out_wide(write_tx_bitslipboundaryselect));
+
+ reg [lanes - 1 : 0] reg_rx_invpolarity = 0;
+ reg [lanes - 1 : 0] sync_rx_invpolarity [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_invpolarity; // indexed write group muxed in
+ wire [0 : 0] lane_rx_invpolarity; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_invpolarity(.in_narrow(writedata[0]),
+ .in_wide(reg_rx_invpolarity), .sel(reg_lane_number),
+ .out_narrow(lane_rx_invpolarity), .out_wide(write_rx_invpolarity));
+
+ reg [lanes - 1 : 0] reg_rx_enapatternalign = 0;
+ reg [lanes - 1 : 0] sync_rx_enapatternalign [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_enapatternalign; // indexed write group muxed in
+ wire [0 : 0] lane_rx_enapatternalign; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_enapatternalign(.in_narrow(writedata[0]),
+ .in_wide(reg_rx_enapatternalign), .sel(reg_lane_number),
+ .out_narrow(lane_rx_enapatternalign), .out_wide(write_rx_enapatternalign));
+
+ reg [lanes - 1 : 0] reg_rx_bitreversalenable = 0;
+ reg [lanes - 1 : 0] sync_rx_bitreversalenable [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_bitreversalenable; // indexed write group muxed in
+ wire [0 : 0] lane_rx_bitreversalenable; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_bitreversalenable(.in_narrow(writedata[1]),
+ .in_wide(reg_rx_bitreversalenable), .sel(reg_lane_number),
+ .out_narrow(lane_rx_bitreversalenable), .out_wide(write_rx_bitreversalenable));
+
+ reg [lanes - 1 : 0] reg_rx_bytereversalenable = 0;
+ reg [lanes - 1 : 0] sync_rx_bytereversalenable [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_bytereversalenable; // indexed write group muxed in
+ wire [0 : 0] lane_rx_bytereversalenable; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_bytereversalenable(.in_narrow(writedata[2]),
+ .in_wide(reg_rx_bytereversalenable), .sel(reg_lane_number),
+ .out_narrow(lane_rx_bytereversalenable), .out_wide(write_rx_bytereversalenable));
+
+ reg [lanes - 1 : 0] reg_rx_bitslip = 0;
+ reg [lanes - 1 : 0] sync_rx_bitslip [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_bitslip; // indexed write group muxed in
+ wire [0 : 0] lane_rx_bitslip; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_bitslip(.in_narrow(writedata[3]),
+ .in_wide(reg_rx_bitslip), .sel(reg_lane_number),
+ .out_narrow(lane_rx_bitslip), .out_wide(write_rx_bitslip));
+
+ reg [lanes - 1 : 0] reg_rx_a1a2size = 0;
+ reg [lanes - 1 : 0] sync_rx_a1a2size [sync_stages:1]; // synchronize to rx_clk
+ wire [lanes - 1 : 0] write_rx_a1a2size; // indexed write group muxed in
+ wire [0 : 0] lane_rx_a1a2size; // selected group indexed for output
+ csr_indexed_write_mux #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .init_value(0))
+ wmux_rx_a1a2size(.in_narrow(writedata[3]),
+ .in_wide(reg_rx_a1a2size), .sel(reg_lane_number),
+ .out_narrow(lane_rx_a1a2size), .out_wide(write_rx_a1a2size));
+
+ ////////////////////////////////////////////////////////
+ // Read-only CSR registers with lane indirection
+ ////////////////////////////////////////////////////////
+ // read-only status registers are synchronized forms of transceiver status signals
+ // async inputs go to reg [sync_stages], and come out synchronized at reg [1]
+ ////////////////////////////////////////////////////////
+ // read selectors (muxes) that index using the indirect lane (group) number
+ wire [words-1 : 0] lane_rx_patterndetect;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(words), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_patterndetect(.clk(clk), .async_in_wide(rx_patterndetect),
+ .sel(reg_lane_number), .out_narrow(lane_rx_patterndetect));
+
+ wire [words-1 : 0] lane_rx_syncstatus;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(words), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_syncstatus(.clk(clk), .async_in_wide(rx_syncstatus),
+ .sel(reg_lane_number), .out_narrow(lane_rx_syncstatus));
+
+ wire [words-1 : 0] lane_rx_errdetect;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(words), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_errdetect(.clk(clk), .async_in_wide(rx_errdetect),
+ .sel(reg_lane_number), .out_narrow(lane_rx_errdetect));
+
+ wire [words-1 : 0] lane_rx_disperr;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(words), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_disperr(.clk(clk), .async_in_wide(rx_disperr),
+ .sel(reg_lane_number), .out_narrow(lane_rx_disperr));
+
+ wire [words-1 : 0] lane_rx_a1a2sizeout;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(words), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_a1a2sizeout(.clk(clk), .async_in_wide(rx_a1a2sizeout),
+ .sel(reg_lane_number), .out_narrow(lane_rx_a1a2sizeout));
+
+ wire [0 : 0] lane_rx_phase_comp_fifo_error;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_phase_comp_fifo_error(.clk(clk), .async_in_wide(rx_phase_comp_fifo_error),
+ .sel(reg_lane_number), .out_narrow(lane_rx_phase_comp_fifo_error));
+
+ wire [4 : 0] lane_rx_bitslipboundaryselectout;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(5), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rx_bitslipboundaryselectout(.clk(clk), .async_in_wide(rx_bitslipboundaryselectout),
+ .sel(reg_lane_number), .out_narrow(lane_rx_bitslipboundaryselectout));
+
+ wire [0 : 0] lane_tx_phase_comp_fifo_error;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_tx_phase_comp_fifo_error(.clk(clk), .async_in_wide(tx_phase_comp_fifo_error),
+ .sel(reg_lane_number), .out_narrow(lane_tx_phase_comp_fifo_error));
+
+ wire [0 : 0] lane_rlv;
+ csr_indexed_read_only_reg #(.groups(lanes), .grp_size(1), .sel_size(LANE_REGW), .sync_stages(sync_stages))
+ mux_rlv(.clk(clk), .async_in_wide(rlv),
+ .sel(reg_lane_number), .out_narrow(lane_rlv));
+
+
+ always @(posedge clk or posedge reset) begin
+ if (reset == 1) begin
+ readdata <= 0;
+ reg_lane_number <= 0;
+ reg_tx_invpolarity <= 0;
+ reg_tx_bitslipboundaryselect <= 0;
+ reg_rx_invpolarity <= 0;
+ reg_rx_enapatternalign <= 0;
+ reg_rx_bitreversalenable <= 0;
+ reg_rx_bytereversalenable <= 0;
+ reg_rx_bitslip <= 0;
+ reg_rx_a1a2size <= 0;
+
+ // no need to clear synchronization registers, since they do not store state
+ end
+ else begin
+ // decode read & write for each supported address
+ case (address)
+ // lane or group number for indirection
+ ADDR_PCS_LANE_GROUP: begin
+ readdata <= (32'd0 | reg_lane_number);
+ if (write) reg_lane_number <= writedata[LANE_REGW-1:0];
+ end
+
+ // offset + 1, read-only RX status bits
+ // bit 0, rx_phase_comp_fifo_error
+ // bit 5:1, rx_bitslipboundaryselectout
+ ADDR_PCS8G_RX_STATUS: begin
+ readdata <= (32'd0 |
+ {lane_rx_bitslipboundaryselectout, //bit 5-1
+ lane_rx_phase_comp_fifo_error}); // bit 0
+ end
+
+ // offset + 2, read-only TX status bits
+ // bit 0, tx_phase_comp_fifo_error
+ ADDR_PCS8G_TX_STATUS: begin
+ readdata <= (32'd0 | lane_tx_phase_comp_fifo_error); // bit 0
+ end
+
+ // offset + 3, read/write TX control bits
+ // bit 0, tx_invpolarity
+ // bit 5:1, tx_bitslipboundaryselect
+ ADDR_PCS8G_TX_CONTROL: begin
+ readdata <= (32'd0 | {lane_tx_bitslipboundaryselect, lane_tx_invpolarity});
+ if (write)
+ begin
+ reg_tx_invpolarity <= write_tx_invpolarity;
+ reg_tx_bitslipboundaryselect <= write_tx_bitslipboundaryselect;
+ end
+ end
+
+ // offset + 4, read/write RX control bits
+ // bit 0, rx_invpolarity
+ ADDR_PCS8G_RX_CONTROL: begin
+ readdata <= (32'd0 | lane_rx_invpolarity);
+ if (write) reg_rx_invpolarity <= write_rx_invpolarity;
+ end
+
+ // offset + 5, read/write RX WA control bits
+ // bit 0, rx_enapatternalign
+ // bit 1, rx_bitreversalenable
+ // bit 2, rx_bytereversalenable
+ // bit 3, rx_bitslip
+ // bit 4, rx_a1a2size
+ ADDR_PCS8G_RX_WA_CONTROL: begin
+ readdata <= (32'd0 | { lane_rx_a1a2size, // bit 4
+ lane_rx_bitslip, // bit 3
+ lane_rx_bytereversalenable, // bit 2
+ lane_rx_bitreversalenable, // bit 1
+ lane_rx_enapatternalign}); // bit 0
+ if (write)
+ begin
+ reg_rx_enapatternalign <= write_rx_enapatternalign;
+ reg_rx_bitreversalenable <= write_rx_bitreversalenable;
+ reg_rx_bytereversalenable <= write_rx_bytereversalenable;
+ reg_rx_bitslip <= write_rx_bitslip;
+ reg_rx_a1a2size <= write_rx_a1a2size;
+ end
+ end
+
+ // offset + 5, read RX WA status bits
+ // bit 3:0, rx_errdetect
+ // bit 7:4, rx_syncstatus
+ // bit 11:8, rx_disperr
+ // bit 15:12, rx_patterndetect
+ // bit 16, rlv
+ // bit 23:20, rx_a1a2sizeout
+ ADDR_PCS8G_RX_WA_STATUS: begin
+ readdata <= (32'd0 | {(4'b0 | lane_rx_a1a2sizeout), // bit 23:20
+ (4'b0 | lane_rlv), // bit 16
+ (4'b0 | lane_rx_patterndetect), // bit 15:12
+ (4'b0 | lane_rx_disperr), // bit 11:8
+ (4'b0 | lane_rx_syncstatus), // bit 7:4
+ (4'b0 | lane_rx_errdetect)}); // bit 3:0
+ end
+
+ default: readdata <= ~ 32'd0; // use too many LEs?
+ endcase
+ end
+ end
+
+ // synchronize TX controls to tx_clk before generating output
+ // sysclk-sync'ed input enters at [sync_stages], and tx_clk-sync'ed output exist at [1]
+ integer stage;
+ always @(posedge tx_clk) begin
+ sync_tx_invpolarity[sync_stages] <= reg_tx_invpolarity;
+ sync_tx_bitslipboundaryselect[sync_stages] <= reg_tx_bitslipboundaryselect;
+ for (stage=2; stage <= sync_stages; stage = stage + 1) begin
+ // additional sync stages
+ sync_tx_invpolarity[stage-1] <= sync_tx_invpolarity[stage];
+ sync_tx_bitslipboundaryselect[stage-1] <= sync_tx_bitslipboundaryselect[stage];
+ end
+ end
+ assign csr_tx_invpolarity = sync_tx_invpolarity[1];
+ assign csr_tx_bitslipboundaryselect = sync_tx_bitslipboundaryselect[1];
+
+ // synchronize RX controls to rx_clk before generating output
+ // sysclk-sync'ed input enters at [sync_stages], and rx_clk-sync'ed output exist at [1]
+ always @(posedge rx_clk) begin
+ sync_rx_invpolarity[sync_stages] <= reg_rx_invpolarity;
+ sync_rx_enapatternalign[sync_stages] <= reg_rx_enapatternalign;
+ sync_rx_bitreversalenable[sync_stages] <= reg_rx_bitreversalenable;
+ sync_rx_bytereversalenable[sync_stages] <= reg_rx_bytereversalenable;
+ sync_rx_bitslip[sync_stages] <= reg_rx_bitslip;
+ sync_rx_a1a2size[sync_stages] <= reg_rx_a1a2size;
+ for (stage=2; stage <= sync_stages; stage = stage + 1) begin
+ // additional sync stages
+ sync_rx_invpolarity[stage-1] <= sync_rx_invpolarity[stage];
+ sync_rx_enapatternalign[stage-1] <= sync_rx_enapatternalign[stage];
+ sync_rx_bitreversalenable[stage-1] <= sync_rx_bitreversalenable[stage];
+ sync_rx_bytereversalenable[stage-1] <= sync_rx_bytereversalenable[stage];
+ sync_rx_bitslip[stage-1] <= sync_rx_bitslip[stage];
+ sync_rx_a1a2size[stage-1] <= sync_rx_a1a2size[stage];
+ end
+ end
+ assign csr_rx_invpolarity = sync_rx_invpolarity[1];
+ assign csr_rx_enapatternalign = sync_rx_enapatternalign[1];
+ assign csr_rx_bitreversalenable = sync_rx_bitreversalenable[1];
+ assign csr_rx_bytereversalenable = sync_rx_bytereversalenable[1];
+ assign csr_rx_bitslip = sync_rx_bitslip[1];
+ assign csr_rx_a1a2size = sync_rx_a1a2size[1];
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_csr_pcs8g_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_csr_pcs8g_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..09f65ef3aee3227b1f9f9ba7d3359a300eb092ac
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_csr_pcs8g_h.sv
@@ -0,0 +1,33 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common control & status register map for transceiver PHY IP
+// Applies to Stratix V-generation basic PHY components
+//
+// $Header$
+//
+// PACKAGE DECLARATION
+package alt_xcvr_csr_pcs8g_h;
+
+ import alt_xcvr_csr_common_h::*;
+
+ // 8G PCS, a.k.a. "Standard PCS", control and status bits
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_RX_STATUS = ADDR_PCS_BASE + 8'd1;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_TX_STATUS = ADDR_PCS_BASE + 8'd2;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_TX_CONTROL = ADDR_PCS_BASE + 8'd3;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_RX_CONTROL = ADDR_PCS_BASE + 8'd4;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_RX_WA_CONTROL = ADDR_PCS_BASE + 8'd5;
+ localparam [alt_xcvr_csr_addr_width-1:0] ADDR_PCS8G_RX_WA_STATUS = ADDR_PCS_BASE + 8'd6;
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_csr_selector.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_csr_selector.sv
new file mode 100644
index 0000000000000000000000000000000000000000..2e843e4597c8292f41a2d244cf5bb2dae2d70abc
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_csr_selector.sv
@@ -0,0 +1,116 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Select a sub-group from a wide register
+// Useful for indirection indexing
+//
+// $Header$
+//
+
+`timescale 1 ns / 1 ns
+
+module csr_mux #(
+ parameter groups = 2,
+ parameter grp_size = 1,
+ parameter sel_size = 1
+)
+(
+ input wire [groups*grp_size-1:0] in_wide,
+ input tri0 [sel_size-1:0] sel,
+ output wire [grp_size-1:0] out_narrow
+);
+// lpm_mux #(.lpm_size(groups), .lpm_width(grp_size), .lpm_widths(sel_size))
+// mux (.data(in_wide), .sel(sel), .result(out_narrow));
+ wire [grp_size-1:0] in_groups [groups-1:0];
+
+ // a synthesizable mux, with a parameterized number of inputs
+ genvar i;
+ assign in_groups[0] = in_wide[grp_size-1:0] & {grp_size{sel == 0}};
+ generate for (i=1; i<groups; i = i+1) begin: mux
+ assign in_groups[i] = in_groups[i-1] | in_wide[i*grp_size +: grp_size] & {grp_size{sel == i}};
+ end
+ endgenerate
+ assign out_narrow = in_groups[groups-1];
+endmodule
+
+//
+// write to a sub-group of a wide register
+// Useful for indirection indexing on write
+//
+module csr_indexed_write_mux #(
+ parameter groups = 2,
+ parameter grp_size = 1,
+ parameter sel_size = 1,
+ parameter init_value = 0
+)
+(
+ input wire [grp_size-1:0] in_narrow,
+ input tri0 [sel_size-1:0] sel,
+ output wire [grp_size-1:0] out_narrow, // for read back to mgmt interface
+ input wire [groups*grp_size-1:0] in_wide, // full-width control reg state
+ output wire [groups*grp_size-1:0] out_wide // to write to full-width control reg
+);
+ wire [groups*grp_size-1:0] wire_wide [groups-1:0];
+
+ // in_narrow is output in the group position indicated by .sel() input
+ genvar i;
+ assign wire_wide[0] = (in_wide & {grp_size{sel != 0}}) | (in_narrow & {grp_size{sel == 0}});
+ generate for (i=1; i<groups; i = i+1) begin: mux
+ assign wire_wide[i] = wire_wide[i-1]
+ | (in_wide & {{grp_size{sel != i}}, {(grp_size*i){1'b0}}})
+ | ({in_narrow & {grp_size{sel == i}}, {(grp_size*i){1'b0}}});
+ end
+ endgenerate
+ assign out_wide = wire_wide[groups-1];
+
+ // generate out_narrow as ordinary mux of in_wide
+ csr_mux #(.groups(groups), .grp_size(grp_size), .sel_size(sel_size))
+ o_narrow(.in_wide(in_wide), .sel(sel), .out_narrow(out_narrow));
+
+endmodule
+
+//
+// read from a sub-group of a wide, async status input
+// Creates synchronization logic to sample in local clock domain
+// Useful for indirection indexing on read-only status bits
+//
+module csr_indexed_read_only_reg #(
+ parameter groups = 2,
+ parameter grp_size = 1,
+ parameter sel_size = 1,
+ parameter sync_stages = 2
+)
+(
+ input wire clk,
+ input tri0 [sel_size-1:0] sel,
+ output wire [grp_size-1:0] out_narrow, // for read back to mgmt interface
+ input wire [groups*grp_size-1:0] async_in_wide // full-width async status inputs
+);
+ // read-only status registers are synchronized forms of async status signals
+ // async inputs go to sreg [sync_stages], and come out synchronized at sreg [1]
+ reg [groups*grp_size-1:0] sreg [sync_stages:1];
+ integer stage;
+ always @(posedge clk) begin
+ sreg[sync_stages] <= async_in_wide;
+ for (stage=2; stage <= sync_stages; stage = stage + 1) begin
+ // additional sync stages
+ sreg[stage-1] <= sreg[stage];
+ end
+ end
+
+ // generate out_narrow as ordinary mux of out_wide
+ csr_mux #(.groups(groups), .grp_size(grp_size), .sel_size(sel_size))
+ o_narrow(.in_wide(sreg[1]), .sel(sel), .out_narrow(out_narrow));
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_m2s.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_m2s.sv
new file mode 100644
index 0000000000000000000000000000000000000000..143f8260ab27069cf2eb8fd54be2d08f84f018ec
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_m2s.sv
@@ -0,0 +1,61 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Master-to-slave access fabric
+//
+// Combined with external multi-master arbitration, this block gates
+// master read, write, address, and writedata outputs, and generates
+// a waitrequest when arbiter indicates access is not granted
+
+// $Header$
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_m2s #(
+ parameter width_addr = 3,
+ parameter width_data = 32
+) (
+ input wire clock,
+ output wire req, // request to arbiter for slave access
+ input wire grant,
+
+ // signals from/to master
+ input wire m_read,
+ input wire m_write,
+ input wire [width_addr-1:0] m_address,
+ input wire [width_data-1:0] m_writedata,
+ output wire [width_data-1:0] m_readdata,
+ output wire m_waitrequest,
+
+ // signals from/to slave
+ output wire s_read,
+ output wire s_write,
+ output wire [width_addr-1:0] s_address,
+ output wire [width_data-1:0] s_writedata,
+ input wire [width_data-1:0] s_readdata,
+ input wire s_waitrequest
+);
+
+ // If master is requesting access, generate waitreq until granted
+ assign req = m_read | m_write; // master access requests
+ assign m_waitrequest = grant ? s_waitrequest : req;
+
+ // gate outputs to slave with grant signal
+ assign s_read = m_read & grant;
+ assign s_write = m_write & grant;
+ assign s_address = m_address & {width_addr{grant}};
+ assign s_writedata = m_writedata & {width_data{grant}};
+
+ // slave data outputs pass through directly
+ assign m_readdata = s_readdata;
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_mgmt2dec.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_mgmt2dec.sv
new file mode 100644
index 0000000000000000000000000000000000000000..93ce24e6bb50518c47c242026699fb45dcee975a
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_mgmt2dec.sv
@@ -0,0 +1,90 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Management interface address decoder for Altera Transceiver PHY
+//
+// Addresses common case of 2 modules to be stitched together:
+// - 'top' PHY channel blocks (includes reset control, CSR, ...)
+// - dynamic reconfiguration block
+
+// $Header$
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_mgmt2dec (
+
+ // user-visible external management interface
+ input wire mgmt_clk_reset,
+ input wire mgmt_clk,
+
+ input wire [8:0] mgmt_address,
+ input wire mgmt_read,
+ output reg [31:0] mgmt_readdata = ~32'd0,
+ output reg mgmt_waitrequest = 0,
+ input wire mgmt_write,
+
+ // internal interface to 'top' csr block
+ output wire [7:0] topcsr_address,
+ output wire topcsr_read,
+ input wire [31:0] topcsr_readdata,
+ input wire topcsr_waitrequest,
+ output wire topcsr_write,
+
+ // internal interface to 'top' csr block
+ output wire [7:0] reconf_address,
+ output wire reconf_read,
+ input wire [31:0] reconf_readdata,
+ input wire reconf_waitrequest,
+ output wire reconf_write
+);
+ localparam width_swa = 7; // word address width of interface to slaves (2 for top.CSR and 1 for reconfig)
+ localparam dec_count = 2; // count of the total number of sub-components that can act
+ // as slaves to the mgmt interface
+ localparam dec_topcsr = 0; // uses 2 128-word address blocks
+ localparam dec_reconf = 1; // uses 1 128-word address block
+
+
+ ///////////////////////////////////////////////////////////////////////
+ // Decoder for multiple slaves of reconfig_mgmt interface
+ ///////////////////////////////////////////////////////////////////////
+ wire [dec_count-1:0] r_decode;
+ assign r_decode =
+ (mgmt_address[8:width_swa+1] == dec_topcsr) ? (({dec_count-dec_topcsr{1'b0}} | 1'b1) << dec_topcsr)
+ : (mgmt_address[8:width_swa] == 2'd2) ? (({dec_count-dec_reconf{1'b0}} | 1'b1) << dec_reconf)
+ : {dec_count{1'b0}};
+
+ // reconfig_mgmt output generation is muxing of decoded slave output
+ always @(*) begin
+ if (r_decode[dec_topcsr] == 1'b1) begin
+ mgmt_readdata = topcsr_readdata;
+ mgmt_waitrequest = topcsr_waitrequest;
+ end else if (r_decode[dec_reconf] == 1'b1) begin
+ mgmt_readdata = reconf_readdata;
+ mgmt_waitrequest = reconf_waitrequest;
+ end else begin
+ mgmt_readdata = -1;
+ mgmt_waitrequest = 1'b0;
+ end
+ end
+
+ // internal interface to 'top' csr block
+ assign topcsr_address = mgmt_address[width_swa:0]; // top.csr uses 2 128-word blocks
+ assign topcsr_read = mgmt_read & r_decode[dec_topcsr];
+ assign topcsr_write = mgmt_write & r_decode[dec_topcsr];
+
+ // internal interface to 'top' csr block
+ assign reconf_address = mgmt_address[width_swa-1:0]; // reconfig uses 1 128-word block
+ assign reconf_read = mgmt_read & r_decode[dec_reconf];
+ assign reconf_write = mgmt_write & r_decode[dec_reconf];
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_mgmt2dec_phyreconfig.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_mgmt2dec_phyreconfig.sv
new file mode 100644
index 0000000000000000000000000000000000000000..3993651a7280e45e8ed8823d62ce37b8836861c2
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_mgmt2dec_phyreconfig.sv
@@ -0,0 +1,110 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//-----------------------------------------------------------------------------
+//
+// Description: Custom management interface address decoder for Altera
+// transciever PHY. Addresses common case of 2 modules to be stitched together:
+// - 'top' PHY channel blocks (includes reset control, CSR, ...)
+// - dynamic reconfiguration block
+//
+// Authors: dunnikri 19-Aug-2010
+//
+// Copyright (c) Altera Corporation 1997 - 2010
+// All rights reserved.
+//
+//
+//-----------------------------------------------------------------------------
+
+//`timescale 1 ns / 1 ns
+
+module alt_xcvr_mgmt2dec_phyreconfig (
+
+ // user-visible external management interface
+ input wire mgmt_clk_reset,
+ input wire mgmt_clk,
+
+ input wire [8:0] mgmt_address,
+ input wire mgmt_read,
+ output reg [31:0] mgmt_readdata = ~32'd0,
+ output reg mgmt_waitrequest = 0,
+ input wire mgmt_write,
+
+ // internal interface to xaui phy block
+ output wire [7:0] sc_phy_address,
+ output wire sc_phy_read,
+ input wire [31:0] sc_phy_readdata,
+ input wire sc_phy_waitrequest,
+ output wire sc_phy_write,
+
+ // internal interface to reconfig block
+ output wire [6:0] sc_reconf_address,
+ output wire sc_reconf_read,
+ input wire [31:0] sc_reconf_readdata,
+ input wire sc_reconf_waitrequest,
+ output wire sc_reconf_write
+);
+ localparam width_swa = 7; // word address width of interface to slaves (2 for phy and 1 for reconfig)
+ localparam dec_count = 2; // count of the total number of sub-components that can act
+ // as slaves to the mgmt interface
+ localparam dec_sc_phy = 0; //
+ localparam dec_reconf = 1; //
+
+ ///////////////////////////////////////////////////////////////////////
+ // Decoder for multiple slaves of reconfig_mgmt interface
+ ///////////////////////////////////////////////////////////////////////
+ wire [dec_count-1:0] r_decode; //1-hot encoding
+
+ //-----------------------Memory Map Reference-------------------------
+ //--------------------------------------------------------------------
+ //Block | Word Address | Byte Address |
+ //-------------------------------------------------------------------
+ //PHY Common | 0x0 | 0x0 |
+ //PMA Controller | 0x20 | 0x80 |
+ //Reset Controller | 0x40 | 0x100 |
+ //PMA Channel Controller | 0x60 | 0x180 |
+ //PCS | 0x80 | 0x200 |
+ //XCVR Reconfig | 0x100 | 0x400 |
+ //--------------------------------------------------------------------
+
+ //Decoding is based on memory map word address
+ assign r_decode =
+ (mgmt_address[8:width_swa+1] == dec_sc_phy) ? (({dec_count-dec_sc_phy{1'b0}} | 1'b1) << dec_sc_phy)
+ : (mgmt_address[8:width_swa] == 2'd2) ? (({dec_count-dec_reconf{1'b0}} | 1'b1) << dec_reconf)
+ : {dec_count{1'b0}};
+
+ // reconfig_mgmt output generation is muxing of decoded slave output
+ always @(*) begin
+ if (r_decode[dec_sc_phy] == 1'b1) begin
+ mgmt_readdata = sc_phy_readdata;
+ mgmt_waitrequest = sc_phy_waitrequest;
+ end else if (r_decode[dec_reconf] == 1'b1) begin
+ mgmt_readdata = sc_reconf_readdata;
+ mgmt_waitrequest = sc_reconf_waitrequest;
+ end else begin
+ mgmt_readdata = -1;
+ mgmt_waitrequest = 1'b0;
+ end
+ end
+
+ // internal interface to 'top' phy block
+ assign sc_phy_address = mgmt_address[width_swa:0];
+ assign sc_phy_read = mgmt_read & r_decode[dec_sc_phy];
+ assign sc_phy_write = mgmt_write & r_decode[dec_sc_phy];
+
+ // internal interface to 'top' reconfig block
+ assign sc_reconf_address = mgmt_address[width_swa-1:0];
+ assign sc_reconf_read = mgmt_read & r_decode[dec_reconf];
+ assign sc_reconf_write = mgmt_write & r_decode[dec_reconf];
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_mgmt2dec_xaui.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_mgmt2dec_xaui.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5720dddc8ee64986827d0db95c96c90eec94cdf3
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_mgmt2dec_xaui.sv
@@ -0,0 +1,134 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//-----------------------------------------------------------------------------
+//
+// Description: Custom management interface address decoder for Altera
+// transciever PHY. Addresses common case of 3 modules to be stitched together:
+// - CSR, Alt_PMA controller, Alt_PMA_Channel controller
+//
+// Authors: dunnikri 19-Aug-2010
+//
+// Copyright (c) Altera Corporation 1997 - 2010
+// All rights reserved.
+//
+//
+//-----------------------------------------------------------------------------
+
+`timescale 1 ps / 1 ps
+
+module alt_xcvr_mgmt2dec_xaui (
+
+ // user-visible external management interface
+ input wire mgmt_clk_reset,
+ input wire mgmt_clk,
+
+ input wire [7:0] mgmt_address,
+ input wire mgmt_read,
+ output reg [31:0] mgmt_readdata = ~32'd0,
+ output reg mgmt_waitrequest = 0,
+ input wire mgmt_write,
+
+ // internal interface to xaui pma channel controller
+ output wire [5:0] sc_pma_ch_controller_address,
+ output wire sc_pma_ch_controller_read,
+ input wire [31:0] sc_pma_ch_controller_readdata,
+ input wire sc_pma_ch_controller_waitrequest,
+ output wire sc_pma_ch_controller_write,
+
+ // internal interface to pma controller block
+ output wire [1:0] sc_pma_controller_address,
+ output wire sc_pma_controller_read,
+ input wire [31:0] sc_pma_controller_readdata,
+ input wire sc_pma_controller_waitrequest,
+ output wire sc_pma_controller_write,
+
+ // internal interface to hxaui csr block
+ output wire [4:0] sc_csr_address,
+ output wire sc_csr_read,
+ input wire [31:0] sc_csr_readdata,
+ input wire sc_csr_waitrequest,
+ output wire sc_csr_write
+);
+ localparam width_swa = 7; // word address width of interface to slaves (2 for phy and 1 for reconfig)
+ localparam dec_count = 3; // count of the total number of sub-components that can act
+ // as slaves to the mgmt interface
+
+ localparam dec_pma_control = 0;
+ localparam dec_csr = 1;
+ localparam dec_pma_ch_control = 2;
+
+ //--------------------------------------------------------------------
+ //Block | Word Address | Byte Address |
+ //-------------------------------------------------------------------
+ //PHY Common | 0x0 | 0x0 |
+ //PMA Controller | 0x20 | 0x80 |
+ //Reset Controller | 0x40 | 0x100 |
+ //PMA Channel Controller | 0x60 | 0x180 |
+ //PCS | 0x80 | 0x200 |
+ //XCVR Reconfig | 0x100 | 0x400 |
+ //-------------------------------------------------------------------
+
+
+ ///////////////////////////////////////////////////////////////////////
+ // Decoder for multiple slaves of reconfig_mgmt interface
+ ///////////////////////////////////////////////////////////////////////
+ wire [dec_count-1:0] r_decode; //1-hot encoding
+
+ //PMA Controller - 0x20 (0010 0000)
+ //Reset Controller - 0x40 (0100 0000)
+ //Channel Controller - 0x60 (0110 0000)
+ //PCS - 0x80 (1000 0000)
+ //Consider first 3 MSBs for decoding
+ /*assign r_decode =
+ (mgmt_address[7:5] == 3'd1) ? (({dec_count-dec_pma_control{1'b0}} | 1'b1) << dec_pma_control)
+ : (mgmt_address[7:5] == 3'd4) ? (({dec_count-dec_csr{1'b0}} | 1'b1) << dec_csr)
+ : (mgmt_address[7:5] == 3'd3) ? (({dec_count-dec_pma_ch_control{1'b0}} | 1'b1) << dec_pma_ch_control)
+ : {dec_count{1'b0}};*/
+
+ assign r_decode[0] = (!mgmt_address[7]) & (!mgmt_address[6]) & (mgmt_address[5]);
+ assign r_decode[1] = (mgmt_address[7]) & (!mgmt_address[6]) & (!mgmt_address[5]);
+ assign r_decode[2] = (!mgmt_address[7]) & (mgmt_address[6]);
+
+
+ always @(*) begin
+ if (r_decode[dec_pma_ch_control] == 1'b1) begin
+ mgmt_readdata = sc_pma_ch_controller_readdata;
+ mgmt_waitrequest = sc_pma_ch_controller_waitrequest;
+ end else if (r_decode[dec_pma_control] == 1'b1) begin
+ mgmt_readdata = sc_pma_controller_readdata;
+ mgmt_waitrequest = sc_pma_controller_waitrequest;
+ end else if (r_decode[dec_csr] == 1'b1) begin
+ mgmt_readdata = sc_csr_readdata;
+ mgmt_waitrequest = sc_csr_waitrequest;
+ end else begin
+ mgmt_readdata = -1;
+ mgmt_waitrequest = 1'b0;
+ end
+ end
+
+ // internal interface to alt_pma_ch_control block
+ assign sc_pma_ch_controller_address = mgmt_address[5:0]; //6 bit address
+ assign sc_pma_ch_controller_read = mgmt_read & r_decode[dec_pma_ch_control];
+ assign sc_pma_ch_controller_write = mgmt_write & r_decode[dec_pma_ch_control];
+
+ // internal interface to pma_control block
+ assign sc_pma_controller_address = mgmt_address[1:0]; // 2 bit address
+ assign sc_pma_controller_read = mgmt_read & r_decode[dec_pma_control];
+ assign sc_pma_controller_write = mgmt_write & r_decode[dec_pma_control];
+
+ // internal interface to csr block
+ assign sc_csr_address = mgmt_address[4:0]; // 5 bit address
+ assign sc_csr_read = mgmt_read & r_decode[dec_csr];
+ assign sc_csr_write = mgmt_write & r_decode[dec_csr];
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_analog.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_analog.sv
new file mode 100644
index 0000000000000000000000000000000000000000..c11f7aa371601873a1d6fc77d0c67623f66bff56
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_analog.sv
@@ -0,0 +1,146 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_analog #(
+ parameter device_family = "Stratix V"
+)
+(
+
+input wire reconfig_clk, // this will be the reconfig clk
+input wire reset,
+
+//avalon MM slave
+input wire [2:0] analog_reconfig_address, // MM address
+input wire [31:0] analog_reconfig_writedata,
+input wire analog_reconfig_write,
+input wire analog_reconfig_read,
+
+//output MM slave
+output wire [31:0] analog_reconfig_readdata, // from MM
+output wire analog_reconfig_waitrequest,
+//output wire analog_reconfig_error,
+output wire analog_reconfig_done,
+
+// input from base_reconfig
+input wire analog_reconfig_irq_from_base,
+input wire analog_reconfig_waitrequest_from_base,
+
+
+// output to base_reconfig
+// Avalon MM Master
+output wire [2:0] analog_reconfig_address_base, // 3 bit MM
+output wire [31:0] analog_reconfig_writedata_base,
+output wire analog_reconfig_write_base, // start write to GXB
+output wire analog_reconfig_read_base, // start read from GXB
+
+// input from base reconfig
+input wire [31:0] analog_reconfig_readdata_base, // data from read command
+ output wire arb_req,
+ input wire arb_grant
+);
+
+//parameter device_family = "StratixIV"; // or ArriaII
+
+
+generate
+ //Deepak - added namespace support for CIVGX and AII GX
+ if((device_family == "Stratix IV") || (device_family == "Arria II") || (device_family == "Cyclone IV GX") || (device_family == "Arria II GX") || (device_family == "Arria II GZ") || (device_family == "HardCopy IV"))
+ begin
+ wire [4:0] w_tgx_analog_reconfig_address_base;
+ alt_xcvr_reconfig_analog_tgx reconfig_analog_tgx(
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .analog_reconfig_address(analog_reconfig_address),
+ .analog_reconfig_writedata(analog_reconfig_writedata),
+ .analog_reconfig_write(analog_reconfig_write),
+ .analog_reconfig_read(analog_reconfig_read),
+ .analog_reconfig_readdata(analog_reconfig_readdata),
+ .analog_reconfig_waitrequest(analog_reconfig_waitrequest),
+ .analog_reconfig_done(analog_reconfig_done),
+ .analog_reconfig_irq_from_base(analog_reconfig_irq_from_base),
+ .analog_reconfig_waitrequest_from_base(analog_reconfig_waitrequest_from_base),
+ .analog_reconfig_address_base(analog_reconfig_address_base),
+ .analog_reconfig_writedata_base(analog_reconfig_writedata_base),
+ .analog_reconfig_write_base(analog_reconfig_write_base),
+ .analog_reconfig_read_base(analog_reconfig_read_base),
+ .analog_reconfig_readdata_base(analog_reconfig_readdata_base)
+ );
+ assign analog_reconfig_address_base = w_tgx_analog_reconfig_address_base[4:2];
+ assign arb_req = 1'b0 & arb_grant; // not currently used in S4 architecture
+ end
+ else if(device_family == "Stratix V")
+ begin
+ alt_xcvr_reconfig_analog_sv reconfig_analog_sv(
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .analog_reconfig_address(analog_reconfig_address),
+ .analog_reconfig_writedata(analog_reconfig_writedata),
+ .analog_reconfig_write(analog_reconfig_write),
+ .analog_reconfig_read(analog_reconfig_read),
+ .analog_reconfig_readdata(analog_reconfig_readdata),
+ .analog_reconfig_waitrequest(analog_reconfig_waitrequest),
+ .analog_reconfig_done(analog_reconfig_done),
+ .analog_reconfig_irq_from_base(analog_reconfig_irq_from_base),
+ .analog_reconfig_waitrequest_from_base(analog_reconfig_waitrequest_from_base),
+ .analog_reconfig_address_base(analog_reconfig_address_base),
+ .analog_reconfig_writedata_base(analog_reconfig_writedata_base),
+ .analog_reconfig_write_base(analog_reconfig_write_base),
+ .analog_reconfig_read_base(analog_reconfig_read_base),
+ .analog_reconfig_readdata_base(analog_reconfig_readdata_base),
+ .arb_req(arb_req),
+ .arb_grant(arb_grant)
+
+ );
+ end
+ else if(device_family == "Arria V")
+ begin
+ alt_xcvr_reconfig_analog_av reconfig_analog_av(
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .analog_reconfig_address(analog_reconfig_address),
+ .analog_reconfig_writedata(analog_reconfig_writedata),
+ .analog_reconfig_write(analog_reconfig_write),
+ .analog_reconfig_read(analog_reconfig_read),
+ .analog_reconfig_readdata(analog_reconfig_readdata),
+ .analog_reconfig_waitrequest(analog_reconfig_waitrequest),
+ .analog_reconfig_done(analog_reconfig_done),
+ .analog_reconfig_irq_from_base(analog_reconfig_irq_from_base),
+ .analog_reconfig_waitrequest_from_base(analog_reconfig_waitrequest_from_base),
+ .analog_reconfig_address_base(analog_reconfig_address_base),
+ .analog_reconfig_writedata_base(analog_reconfig_writedata_base),
+ .analog_reconfig_write_base(analog_reconfig_write_base),
+ .analog_reconfig_read_base(analog_reconfig_read_base),
+ .analog_reconfig_readdata_base(analog_reconfig_readdata_base),
+ .arb_req(arb_req),
+ .arb_grant(arb_grant)
+
+ );
+ end
+ else
+ begin
+ assign analog_reconfig_readdata = 32'd0;
+ assign analog_reconfig_waitrequest = 1'd0;
+ assign analog_reconfig_done = 1'd1;
+ assign analog_reconfig_address_base = 3'd0;
+ assign analog_reconfig_writedata_base = 32'd0;
+ assign analog_reconfig_write_base = 1'd0;
+ assign analog_reconfig_read_base = 1'd0;
+ assign arb_req = 1'd0;
+ end
+
+endgenerate
+
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_analog_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_analog_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..b124cab8495ba45a26198a9b5ab25318441e6f01
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_analog_tgx.v
@@ -0,0 +1,763 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_analog_tgx (
+
+input wire reconfig_clk, // this will be the reconfig clk
+input wire reset,
+
+//avalon MM slave
+input wire [2:0] analog_reconfig_address, // MM address
+input wire [31:0] analog_reconfig_writedata,
+input wire analog_reconfig_write,
+input wire analog_reconfig_read,
+
+//output MM slave
+output reg [31:0] analog_reconfig_readdata, // from MM
+output wire analog_reconfig_waitrequest,
+//output wire analog_reconfig_error,
+output reg analog_reconfig_done,
+
+// input from base_reconfig
+ input wire analog_reconfig_irq_from_base,
+ input wire analog_reconfig_waitrequest_from_base,
+
+
+// output to base_reconfig
+// Avalon MM Master
+output wire [4:0] analog_reconfig_address_base, // 3 bit MM
+output wire [31:0] analog_reconfig_writedata_base,
+output wire analog_reconfig_write_base, // start write to GXB
+output wire analog_reconfig_read_base, // start read from GXB
+
+// input from base reconfig
+input wire [31:0] analog_reconfig_readdata_base // data from read command
+);
+
+parameter device_family = "Stratix IV"; // or ArriaII
+
+// new memory map -- register indirection
+//----------------------------------------------
+// address data[15:0]
+// 0 wr/rd logical_channel_address
+// 1 rd physical_chnl
+// 2 wr/rd control (write, read) / status (error, datavalid, busy)
+// 3 wr/rd addr_offset
+// 4 wr/rd data
+//
+// addr_offset ( upto 16 bits)
+// 0-15 TX parameters : vod, preemph_0t, preemph_1t, preemph_2t
+// 16-31 RX parameters : dcgain, eqctrl
+
+//local parameters
+localparam ADDR_WIDTH = 3;
+
+localparam IDLE = 4'b0000;
+localparam READ_FROM_GXB = 4'b0001;
+localparam WRITE_TO_GXB = 4'b0010;
+localparam SET_INFO_ON_BASIC = 4'b0011;
+localparam WRITE_DONE = 4'b0100;
+localparam READ_FROM_BASIC = 4'b0101;
+localparam READ_FROM_BASIC_DONE = 4'b0110;
+localparam READ_IDLE = 4'b0111;
+localparam GET_MUTEX = 4'b1000;
+localparam WRITE_CHL_ADDR = 4'b1001;
+localparam READ_OR_SET_INFO = 4'b1010;
+
+localparam ILLEGAL_PHYSICAL_CHNL = 12'b111111111111;
+
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [3:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+//reg [3:0] prev_state;
+genvar i;
+integer j;
+wire [(2**ADDR_WIDTH)-1:0] address_decode;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [4:0] master_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_read;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [31:0] master_writedata;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] chnl_addr_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [11:0] phys_chnl_addr_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg logical_chnl_addr_updated;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] status_reg;
+reg [1:0] control_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] data_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg needs_second_access;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [4:0] addr_offset;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg needs_second_write_access;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg do_read_before_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg set_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg have_mutex;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg req_and_use_mutex;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg do_read_phys_chnl;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg do_write_chnl_addr;
+
+wire mutex_grant;
+wire mutex_acq_waitrequest;
+wire [31:0] mutex_acq_readdata;
+wire accessing_rxeqctrl;
+wire accessing_rxdcgain;
+wire accessing_vod;
+wire accessing_preemph1t;
+wire accessing_preemph0t;
+wire accessing_preemph2t;
+
+// Implement waitrequest to match previous implementation
+altera_wait_generate wait_gen(
+ .rst(reset),
+ .clk(reconfig_clk),
+ .launch_signal(analog_reconfig_read),
+ .wait_req(analog_reconfig_waitrequest)
+);
+
+// synopsys translate_off
+initial begin
+ state <= 3'b000;
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ master_writedata <= 16'b0;
+ master_addr <= 5'b0;
+ status_reg <= 2'b0;
+ control_reg <= 2'b0;
+ data_reg <= 16'b0;
+ needs_second_access <= 1'b0;
+ do_read_before_write <= 1'b0;
+ addr_offset <= 5'b0;
+ set_addr <= 1'b0;
+ needs_second_write_access <= 1'b0;
+ have_mutex <= 0;
+ req_and_use_mutex <= 0;
+ do_read_phys_chnl <= 0;
+ do_write_chnl_addr <= 0;
+ logical_chnl_addr_updated <= 0;
+end
+// synopsys translate_on
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset)
+ begin
+ state <= IDLE;
+ analog_reconfig_readdata[31:0] <= 32'b0;
+ analog_reconfig_done <= 1'b0;
+ status_reg <= 2'b0;
+ control_reg <= 2'b0;
+ needs_second_access <= 1'b0;
+ needs_second_write_access <= 1'b0;
+ set_addr <= 1'b0;
+ do_read_before_write <= 1'b0;
+ data_reg <= 16'b0;
+ have_mutex <= 0;
+ req_and_use_mutex <= 0;
+ do_read_phys_chnl <= 0;
+ do_write_chnl_addr <= 0;
+ logical_chnl_addr_updated <= 0;
+ end
+ else begin
+ have_mutex <= mutex_grant;
+ if (analog_reconfig_read == 1'b1) // allow status read during GX read
+ begin
+ if (analog_reconfig_address == 3'b000) // logical channel address
+ analog_reconfig_readdata <= {{16{1'b0}}, chnl_addr_reg};
+ else if (analog_reconfig_address == 3'b001) // physical channel address
+ analog_reconfig_readdata <= {{20{1'b0}}, phys_chnl_addr_reg};
+ else if (analog_reconfig_address == 3'b010) // status
+ analog_reconfig_readdata <= {{22{1'b0}}, status_reg[1:0], {8{1'b0}}};
+ else if (analog_reconfig_address == 3'b011) // TX/RX offset
+ analog_reconfig_readdata <= {{16{1'b0}}, addr_offset};
+ else if (analog_reconfig_address == 3'b100) // previously read data
+ analog_reconfig_readdata <= {{16{1'b0}}, data_reg};
+ else
+ analog_reconfig_readdata <= {32{1'b0}};
+ end
+ case (state)
+ IDLE: begin
+ needs_second_access <= 1'b0;
+ if (analog_reconfig_address == 3'b0)
+ begin
+ if (analog_reconfig_write == 1'b1)
+ begin
+ chnl_addr_reg <= {{4{1'b0}},analog_reconfig_writedata[11:0]}; // write logical_ch_addr
+ logical_chnl_addr_updated <= 1'b1;
+ end
+ end
+ else if (analog_reconfig_write == 1'b1 && analog_reconfig_address == 3'b011) // addr_offset
+ begin
+ addr_offset <= analog_reconfig_writedata[4:0];
+ end
+ else if (analog_reconfig_address == 3'b100) // DPRIO write data
+ begin
+ if (analog_reconfig_write == 1'b1)
+ data_reg[15:0] <= analog_reconfig_writedata[15:0];
+ end
+ else if (analog_reconfig_read == 1'b1 && analog_reconfig_address == 3'b001) // physical chnl
+ begin
+ if (logical_chnl_addr_updated == 1'b1) // if logical chnl addr was updated from the last time we read the phys addr, go do the read again
+ begin
+ status_reg <= {1'b0, 1'b1}; //set busy bit
+ if (have_mutex)
+ begin
+ state <= WRITE_CHL_ADDR;
+ do_read_phys_chnl <= 1;
+ end
+ else begin
+ state <= READ_IDLE;
+ req_and_use_mutex <= 1'b1;
+ do_write_chnl_addr <= 1'b1;
+ do_read_phys_chnl <= 1;
+ end
+ logical_chnl_addr_updated <= 1'b0;
+ end
+ end
+ else if (analog_reconfig_address == 3'b010 && analog_reconfig_write == 1'b1) // control reg bit 1 rd, bit 0 wr
+ begin
+ status_reg <= {1'b0, 1'b1}; // set busy bit
+ control_reg <= analog_reconfig_writedata[1:0];
+ if (analog_reconfig_writedata[0] == 1'b1)
+ do_read_before_write <= 1'b1;
+ if (have_mutex)
+ begin
+ state <= WRITE_CHL_ADDR;
+ end
+ else begin
+ state <= READ_IDLE;
+ req_and_use_mutex <= 1'b1;
+ do_write_chnl_addr <= 1'b1;
+ status_reg <= {1'b0, 1'b1}; // set busy bit
+ end
+ end
+ else if (analog_reconfig_address > 3'b100 && analog_reconfig_write == 1'b1) //
+ begin
+ // synopsys translate_off
+ $display ("Illegal operation to reserved address %h", analog_reconfig_address);
+ $display ("Time: %0t Instance: %m", $time);
+ // synopsys translate_on
+ end
+ else if (have_mutex == 1'b1)
+ begin
+ // holding the mutex in idle state, release it
+ req_and_use_mutex <= 1'b0;
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ end
+ end
+ WRITE_CHL_ADDR: begin
+ master_addr <= 5'b00100;
+ master_write <= 1'b1;
+ master_writedata <= chnl_addr_reg;
+ state <= READ_OR_SET_INFO;
+ end
+ READ_OR_SET_INFO: begin
+ if (analog_reconfig_waitrequest_from_base == 1'b1)
+ state <= READ_OR_SET_INFO;
+ else
+ begin
+ master_write <= 1'b0;
+ if (do_read_phys_chnl)
+ begin
+ state <= READ_FROM_BASIC;
+ // do_read_phys_chnl = 0;
+ end
+ else begin
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ master_read <= 0;
+ end
+ end
+ end
+ GET_MUTEX:
+ begin
+ if (have_mutex == 1'b1)
+ begin
+ if (do_write_chnl_addr == 1'b1)
+ state <= WRITE_CHL_ADDR;
+ else
+ state <= READ_OR_SET_INFO;
+ end
+ else
+ begin
+ state <= GET_MUTEX;
+ end
+ end
+ READ_FROM_BASIC: begin
+ if (analog_reconfig_waitrequest == 1'b0)
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ if (analog_reconfig_irq_from_base == 1'b1) // start read access to data reg. of base_reconfig
+ begin
+ master_addr <= 5'b10100;
+ end
+ else begin
+ master_addr <= 5'b01000;
+ end
+ state <= READ_IDLE;
+ end
+ else
+ begin
+ state <= READ_FROM_BASIC;
+ end
+ end
+ READ_IDLE: begin
+ if (analog_reconfig_waitrequest == 1'b0)
+ begin
+ if (have_mutex)
+ state <= READ_FROM_BASIC_DONE;
+ else
+ begin
+ state <= GET_MUTEX;
+ end
+ end
+ else
+ begin
+ state <= READ_IDLE;
+ end
+ end
+ READ_FROM_BASIC_DONE: begin
+ if (analog_reconfig_waitrequest == 1'b0)
+ begin
+ master_read <= 1'b0;
+ if (do_read_phys_chnl)
+ begin
+ do_read_phys_chnl <= 0;
+ phys_chnl_addr_reg <= mutex_acq_readdata[11:0];
+ if (mutex_acq_readdata[11:0] == ILLEGAL_PHYSICAL_CHNL)
+ begin
+ //set error bit
+ status_reg <= {1'b1, 1'b0};
+ // error message for sim
+ //$display();
+ //$display();
+ end
+ else begin
+ // unset busy bit
+ status_reg <= 2'b0;
+ end
+ state <= IDLE;
+ end
+ else if (accessing_vod)
+ begin
+
+ // This is for Stratix IV only
+ //////////////////////////////////////////////////
+ //Port | DPRIO CRAM bit value
+ //2..0 | 2..0
+ //////////////////////////////////////////////////
+ //000 | 000
+ //001 | 001
+ //010 | 010
+ //011 | 110
+ //100 | 011
+ //101 | 111
+ //110 | 100
+ //111 | 101
+ /////////////////////////////////////////////////
+ if (control_reg[0] == 1'b1) // this was a write cycle to begin with
+ begin
+ master_writedata[31:16] <= {16{1'b0}};
+ master_writedata[15:13] <= {(data_reg[2] & data_reg[1]) | (data_reg[2] & data_reg[0]) | (data_reg[1] & data_reg[0]), data_reg[2] ^ data_reg[1], (~data_reg[1] & data_reg[0]) | (data_reg[2] & data_reg[0]) | (data_reg[2] & ~data_reg[1])};
+ master_writedata[12:0] <= mutex_acq_readdata[12:0];
+ master_addr <= 5'b10100;
+ master_write <= 1'b1;
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ end
+ else begin
+ data_reg <= {{13{1'b0}}, (mutex_acq_readdata[15] & ~mutex_acq_readdata[14]) | (mutex_acq_readdata[14] & mutex_acq_readdata[13]), (mutex_acq_readdata[15] & ~mutex_acq_readdata[14]) | (mutex_acq_readdata[14] & ~mutex_acq_readdata[13]), (~mutex_acq_readdata[14] & mutex_acq_readdata[13]) | (mutex_acq_readdata[15] & mutex_acq_readdata[14])};
+ // unset busy bit
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ else if (accessing_rxdcgain)
+ begin
+ // This is for Stratix IV only
+ //////////////////////////////////////////////////
+ //Port | DRIO CRAM bit value
+ //2..0 | 10..7
+ //////////////////////////////////////////////////
+ //000 | 0000
+ //001 | 0001
+ //010 | 0011
+ //011 | 0111
+ //100 | 1111
+ //Others | Assume to be 1's
+ /////////////////////////////////////////////////
+
+ // This is for Arria II only
+ //////////////////////////////////////////////////
+ //Port | DRIO CRAM bit value
+ //1..0 | 10..7
+ //////////////////////////////////////////////////
+ //00 | 0000
+ //01 | 0001
+ //10 | 0011
+ //Others | Assume to be 1's
+ /////////////////////////////////////////////////
+ if (control_reg[0] == 1'b1)
+ begin
+ if ((device_family == "Stratix IV") || (device_family == "HardCopy IV"))
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:11], data_reg[2], data_reg[1] & data_reg[0] | data_reg[2], data_reg[2] | data_reg[1], data_reg[2] | data_reg[1] | data_reg[0], mutex_acq_readdata[6:0]};
+ else
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:11], 1'b0, 1'b0, data_reg[1], data_reg[1] | data_reg[0], mutex_acq_readdata[6:0]};
+ master_addr <= 5'b10100;
+ master_write <= 1'b1;
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ end
+ else begin
+ if ((device_family == "Stratix IV") || (device_family == "HardCopy IV"))
+ data_reg <= {{13{1'b0}}, mutex_acq_readdata[10], ~mutex_acq_readdata[10] & mutex_acq_readdata[8], mutex_acq_readdata[10] ^ mutex_acq_readdata[9] ^ mutex_acq_readdata[8] ^ mutex_acq_readdata[7]};
+ else
+ data_reg <= {{14{1'b0}}, mutex_acq_readdata[8], mutex_acq_readdata[7] ^ mutex_acq_readdata[8]};
+ // unset busy bit
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ else if (accessing_rxeqctrl) // encode/decode rx_eqctrl
+ begin
+ ////////////////////////////////////////
+ // Wiz A B C D V
+ // 3210 EDC BA9 876 543 210
+ // 0000 000 000 000 000 000
+ // L0 0001 011 000 000 000 111
+ // L1 0010 100 000 000 000 000
+ // L2 0011 111 000 000 000 000
+ // L3 0100 111 000 000 000 111
+ // L4 0101 101 101 000 000 000
+ // M0 0110 111 111 000 000 000
+ // M1 0111 111 111 000 000 100
+ // M2 1000 111 111 000 000 111
+ // M3 1001 111 111 111 000 001
+ // M4 1010 111 111 111 000 100
+ // H0 1011 111 111 111 111 000
+ // H1 1100 111 111 111 111 001
+ // H2 1101 111 111 111 111 100
+ // H3 1110 111 111 111 111 110
+ // H4 1111 111 111 111 111 111
+ ////////////////////////////////////////
+ if (control_reg[0] == 1'b1)
+ begin
+ master_writedata[31:16] <= 0;
+ master_writedata[15] <= mutex_acq_readdata[15];
+ if (data_reg[3:0] > 4'b1010)
+ master_writedata[14:3] <= {12{1'b1}};
+ else if (data_reg[3:0] > 4'b0110)
+ master_writedata[14:3] <= {{3{1'b0}}, {9{1'b1}}};
+ else if (data_reg[3:0] > 4'b0011)
+ master_writedata[14:3] <= {{6{1'b0}}, {6{1'b1}}};
+ else if (data_reg[3:0] > 4'b0)
+ master_writedata[14:3] <= {{9{1'b0}}, {3{1'b1}}};
+ else
+ master_writedata[14:3] <= {12{1'b0}};
+ master_writedata[2] <= (data_reg[1] & ~data_reg[0]) | (~data_reg[3] & ~data_reg[2] & data_reg[1]) | (data_reg[2] & ~data_reg[1] & data_reg[0] | (data_reg[3] & data_reg[2] & data_reg[0]) | (data_reg[3] & ~data_reg[2] & ~data_reg[1]));
+ master_writedata[1] <= ( data_reg[1] & (data_reg[0] ^ (data_reg[2] ^ data_reg[3]))) | (data_reg[3] & data_reg[2] & ~data_reg[1] & ~data_reg[0]);
+ master_writedata[0] <= (~(data_reg[3] ^ data_reg[2]) & data_reg[1] & data_reg[0]) | (data_reg[2] & data_reg[1] & ~data_reg[0]) | (data_reg[3] & data_reg[1] & ~data_reg[0]) | (data_reg[3] & data_reg[2] & ~data_reg[0]) | (data_reg[3] & ~data_reg[2] & ~data_reg[1] & data_reg[0]);
+
+ master_addr <= 5'b10100;
+ master_write <= 1'b1;
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ end
+ else begin
+ if (mutex_acq_readdata[14:12] == 3'b111) // > 10
+ data_reg <= {{12{1'b0}}, 1'b1, (mutex_acq_readdata[1] & mutex_acq_readdata[0]) | (mutex_acq_readdata[2] & ~mutex_acq_readdata[1]), (mutex_acq_readdata[2] & mutex_acq_readdata[0]) | (~mutex_acq_readdata[0] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[2]), (~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]) | (mutex_acq_readdata[2] & mutex_acq_readdata[1] & mutex_acq_readdata[0])};
+ else if (mutex_acq_readdata[11:9] == 3'b111) // > 6 only
+ data_reg <= {{12{1'b0}}, mutex_acq_readdata[2], ~mutex_acq_readdata[2], (mutex_acq_readdata[2] & mutex_acq_readdata[1] & mutex_acq_readdata[0]) | (~mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]), (~mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]) | (mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & mutex_acq_readdata[0])};
+ else if (mutex_acq_readdata[8:6] == 3'b111) // > 3 only
+ data_reg <= {{12{1'b0}}, 1'b0, 1'b1, mutex_acq_readdata[2] & mutex_acq_readdata[1] & mutex_acq_readdata[0], mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]};
+ else if (mutex_acq_readdata[5:3] == 3'b111) // > 0 only
+ data_reg <= {{12{1'b0}}, {2{1'b0}}, (mutex_acq_readdata[2] & mutex_acq_readdata[1] & mutex_acq_readdata[0]) | (mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]), (mutex_acq_readdata[2] & mutex_acq_readdata[1] & mutex_acq_readdata[0]) | (~mutex_acq_readdata[2] & ~mutex_acq_readdata[1] & ~mutex_acq_readdata[0]) };
+ else
+ data_reg <= {16{1'b0}};
+
+ // unset busy bit
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ else if (accessing_preemph1t)
+ begin
+ // This is for Arria II only
+ //////////////////////////////////////////////////
+ //Port | DRIO CRAM bit value
+ //4..0 | 15..11
+ //////////////////////////////////////////////////
+ //00000 | 00000
+ //00001 | 00001
+ //00010 | 00101
+ //00011 | 01001
+ //00100 | 01101
+ //00101 | 10001
+ //00110 | 10101
+ //Others | Assume to be 1's
+ /////////////////////////////////////////////////
+ if (control_reg[0] == 1'b1)
+ begin
+ if (device_family == "Stratix IV")
+ master_writedata <= {{16{1'b0}}, data_reg[4:0], mutex_acq_readdata[10:0]};
+ else
+ master_writedata <= {{16{1'b0}}, data_reg[2] & data_reg[1] ^ data_reg[0], data_reg[2] & ~data_reg[1] & ~data_reg[0] | (data_reg[1] & data_reg[0]), (data_reg[2] | data_reg[1]) & ~data_reg[0], 1'b0, (data_reg[2] | data_reg[1] | data_reg[0]), mutex_acq_readdata[10:0]};
+ master_addr <= 5'b10100;
+ master_write <= 1'b1;
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ end
+ else begin
+ if (device_family == "Stratix IV")
+ data_reg <= {{11{1'b0}}, mutex_acq_readdata[15:11]};
+ else
+ data_reg <= {{11{1'b0}}, 1'b0, 1'b0, mutex_acq_readdata[15] | (mutex_acq_readdata[14] & mutex_acq_readdata[13]), mutex_acq_readdata[14] ^ mutex_acq_readdata[13], mutex_acq_readdata[13] ^ mutex_acq_readdata[11]};
+ // unset busy bit
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ else if (accessing_preemph0t || accessing_preemph2t)
+ begin
+ if (control_reg[0] == 1'b1)
+ begin
+ if (accessing_preemph0t)
+ begin
+ if (needs_second_write_access)
+ begin
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:5], ~data_reg[4], mutex_acq_readdata[3:0]};
+ end
+ else begin
+ if (data_reg[4] == 1'b0)
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:4], 4'b0000 - data_reg[3:0]};
+ else
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:4], data_reg[3:0]};
+ end
+ end
+ else if (accessing_preemph2t)
+ begin
+ if (needs_second_write_access)
+ begin
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:4], ~data_reg[4], mutex_acq_readdata[2:0]};
+ end
+ else begin
+ if (data_reg[4] == 1'b0)
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:8], 4'b0000 - data_reg[3:0], mutex_acq_readdata[3:0]};
+ else
+ master_writedata <= {{16{1'b0}}, mutex_acq_readdata[15:8], data_reg[3:0], mutex_acq_readdata[3:0]};
+ end
+ end
+ master_addr <= 5'b10100;
+ master_write <= 1'b1;
+ state <= SET_INFO_ON_BASIC;
+ set_addr <= 1'b1;
+ end
+ else begin
+ if (needs_second_access)
+ begin
+ data_reg <= mutex_acq_readdata[15:0];
+ master_write <= 1'b1; // start access for INV bit
+ master_addr <= 5'b10000;
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {8{1'b0}}, 2'b11}; // DPRIO register address
+ state <= SET_INFO_ON_BASIC;
+ needs_second_access <= 1'b0;
+ end
+ else begin
+ if (accessing_preemph0t)
+ begin
+ if (mutex_acq_readdata[4] == 1'b1)
+ data_reg <= {{11{1'b0}}, 1'b0, 4'b0000 - data_reg[3:0]};
+ else
+ data_reg <= {{11{1'b0}}, 1'b1, data_reg[3:0]};
+ end
+ else begin
+ if (mutex_acq_readdata[3] == 1'b1)
+ data_reg <= {{11{1'b0}}, 1'b0, 4'b0000 - data_reg[7:4]};
+ else
+ data_reg <= {{11{1'b0}}, 1'b1, data_reg[7:4]};
+ end
+ // unset busy
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ end
+ else begin // dont know what the operation is
+ analog_reconfig_readdata <= mutex_acq_readdata;
+ // unset busy bit
+ status_reg <= 2'b0;
+ state <= IDLE;
+ end
+ end
+ else
+ begin
+ state <= READ_FROM_BASIC_DONE;
+ end
+ end
+ SET_INFO_ON_BASIC: begin
+ if (set_addr)
+ begin
+ master_addr <= 5'b10000;
+ master_write <= 1'b1;
+ if (accessing_vod)
+ begin
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {10{1'b0}}};
+ end
+ else if (accessing_preemph1t)
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {8{1'b0}}, 2'b01};
+ else if (accessing_rxdcgain)
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b11, 10'b0};
+ else if (accessing_rxeqctrl)
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b11, 10'b0000001011};
+ else if (accessing_preemph0t || accessing_preemph2t)
+ begin
+ if (needs_second_write_access)
+ begin
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {8{1'b0}}, 2'b11};
+ end
+ else
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {8{1'b0}}, 2'b10};
+ if (control_reg[1] == 1'b1) // pure read cycle
+ needs_second_access <= 1'b1;
+ end
+ set_addr <= 1'b0;
+ end
+ else if (control_reg[1] == 1'b1 || (control_reg[0] == 1'b1 & do_read_before_write)) // read
+ begin
+ master_addr <= 5'b01100;
+ master_write <= 1'b1;
+ master_writedata <= {{16{1'b0}}, {14{1'b0}}, 2'b10}; // initiate read first
+ state <= READ_FROM_GXB;
+ do_read_before_write <= 1'b0;
+ end
+ else if (control_reg[0] == 1'b1) // actual write
+ begin
+ master_write <= 1'b1;
+ master_addr <= 5'b01100;
+ master_writedata <= {{16{1'b0}}, {14{1'b0}}, 2'b01}; // issue write to basic's control_reg to start WRITE
+ state <= WRITE_TO_GXB;
+ end
+ end
+ READ_FROM_GXB: begin
+ master_write <= 1'b0;
+ if (analog_reconfig_irq_from_base == 1'b1)
+ state <= READ_FROM_BASIC;
+ end
+ WRITE_TO_GXB: begin
+ master_write <= 1'b0;
+ if (analog_reconfig_irq_from_base == 1'b1)
+ begin
+ //start access to clear interrupt control reg. on slave
+ master_addr <= 5'b01100;
+ master_write <= 1'b1;
+ master_writedata <= {{16{1'b0}}, {13{1'b0}}, 3'b000};
+ state <= WRITE_DONE;
+ end
+ end
+ WRITE_DONE: begin
+ master_write <= 1'b0;
+ if (analog_reconfig_irq_from_base == 1'b1)
+ begin
+ if ((accessing_preemph0t || accessing_preemph2t) & (!needs_second_write_access))
+ begin
+ needs_second_write_access <= 1'b1;
+ do_read_before_write <= 1'b1;
+ master_write <= 1'b1;
+ master_addr <= 5'b10000;
+ master_writedata <= {{16{1'b0}}, {4{1'b0}}, 2'b10, {8{1'b0}}, 2'b11}; // DPRIO register address for INV
+ state <= SET_INFO_ON_BASIC;
+ end
+ else begin
+ needs_second_write_access <= 1'b0;
+ status_reg <= {1'b0, 1'b0}; // unset busy
+ analog_reconfig_done <= 1'b1; // send INTERRUPT
+ state <= IDLE;
+ end
+ end
+ end
+ default:begin
+ state <= IDLE;
+ end
+ endcase
+ end
+// prev_state <= state;
+end
+
+assign accessing_vod = (addr_offset[4:0] == 5'b0);
+assign accessing_preemph0t = (addr_offset[4:0] == 5'b00001);
+assign accessing_preemph1t = (addr_offset[4:0] == 5'b00010);
+assign accessing_preemph2t = (addr_offset[4:0] == 5'b00011);
+assign accessing_rxdcgain = (addr_offset[4] == 1'b1 && addr_offset[3:0] == 4'b0000);
+assign accessing_rxeqctrl = (addr_offset[4] == 1'b1 && addr_offset[3:0] == 4'b0001);
+
+//assign analog_reconfig_address_base = master_addr;
+//assign analog_reconfig_write_base = master_write;
+//assign analog_reconfig_read_base = master_read;
+//assign analog_reconfig_writedata_base = master_writedata;
+
+
+ alt_mutex_acq #(
+ .mutex_wait_time(101),
+ .addr_width(5),
+ .data_width(32)
+ )
+ mutex_inst (
+ .clk(reconfig_clk),
+ .reset(reset),
+ // inputs to the base that should be routed through the mutex
+ .address(master_addr),
+ .writedata(master_writedata),
+ .write(master_write),
+ .read(master_read),
+ // output from the mutex which is processed form of output from base
+ .waitrequest(mutex_acq_waitrequest),
+ .readdata(mutex_acq_readdata),
+
+
+ // outputs from mutex to be routed to the base
+ .master_address(analog_reconfig_address_base),
+ .master_writedata(analog_reconfig_writedata_base),
+ .master_write(analog_reconfig_write_base),
+ .master_read(analog_reconfig_read_base),
+
+ // these ports are from the base routed to the mutex
+ .master_waitrequest(analog_reconfig_waitrequest_from_base),
+ .master_readdata(analog_reconfig_readdata_base), // from MM
+
+ //request signal to the mutex should be kept high as long as the mutex is being used
+ .mutex_req(req_and_use_mutex),
+ // output from mutex indicates whether you have mutex or not
+ .mutex_grant(mutex_grant)
+ );
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_basic_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_basic_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..2c4f79b384db04a1ab6911dc33951886c61d0f08
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_basic_tgx.v
@@ -0,0 +1,367 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+(* ALTERA_ATTRIBUTE = {"{-to address_pres_reg[11]} DPRIO_CHANNEL_NUM=11;{-to address_pres_reg[10]} DPRIO_CHANNEL_NUM=10;{-to address_pres_reg[9]} DPRIO_CHANNEL_NUM=9;{-to address_pres_reg[8]} DPRIO_CHANNEL_NUM=8;{-to address_pres_reg[7]} DPRIO_CHANNEL_NUM=7;{-to address_pres_reg[6]} DPRIO_CHANNEL_NUM=6;{-to address_pres_reg[5]} DPRIO_CHANNEL_NUM=5;{-to address_pres_reg[4]} DPRIO_CHANNEL_NUM=4;{-to address_pres_reg[3]} DPRIO_CHANNEL_NUM=3;{-to address_pres_reg[2]} DPRIO_CHANNEL_NUM=2;{-to address_pres_reg[1]} DPRIO_CHANNEL_NUM=1;{-to address_pres_reg[0]} DPRIO_CHANNEL_NUM=0; disable_da_rule=\"S102,R102\""} *)
+module alt_xcvr_reconfig_basic_tgx
+#( parameter number_of_reconfig_interfaces = 1
+ )
+(
+ // avalon clock interface
+ input wire reconfig_clk,
+ input wire reset,
+
+ // avalon MM
+ input wire basic_reconfig_write,
+ input wire basic_reconfig_read,
+ input wire [31:0] basic_reconfig_writedata,
+ input wire [2:0] basic_reconfig_address, // address to MM described below
+
+ output reg [31:0] basic_reconfig_readdata, // reconfig_fromgxb_data
+ output wire basic_reconfig_waitrequest,
+
+ // avalon MM
+// output wire reconfig_write_base,
+// output wire reconfig_read_base,
+// output wire [31:0] reconfig_writedata_base,
+// output wire [4:0] reconfig_address_base, // address to MM described below
+
+// input wire [31:0] reconfig_readdata_base, // reconfig_fromgxb_data
+// input wire reconfig_waitrequest_from_base,
+
+
+ // avalon ST interface
+ input wire [number_of_reconfig_interfaces*17 - 1 : 0] basic_reconfig_fromgxb_data, // dprioout, testbus from altgx : (17+4 bits/quad)
+ input wire [number_of_reconfig_interfaces*8 - 1 : 0] aeq_fromgxb_data, // for ADCE dprio
+ output wire [3:0] basic_reconfig_togxb_data, // busy, dprioin, dprioload, dpriodisable and aeq to altgx
+ output reg [number_of_reconfig_interfaces*24 - 1 : 0] aeq_togxb_data, // for ADCE
+ output reg [number_of_reconfig_interfaces*16 - 1 : 0] testbus_data,
+
+ output reg basic_reconfig_irq // interrupt to Master
+);
+
+//assign reconfig_write_base = 1'b0;
+//assign reconfig_read_base = 1'b0;
+//assign reconfig_writedata_base = 32'd0;
+//assign reconfig_address_base = 5'd0;
+
+
+// Memeory Map for register indirection
+// addr wr/rd description
+// ------------------------------------------------------
+// 0 wr/rd mutex : bit[0]
+// 1 wr/rd logical_ch_addr (10 bits)
+// 2 rd physical_chnl_map
+// 3 rd/wr status/control -- bit 0 busy/bit 1 read, bit 0 write, bit 3 = absolute addressing
+// 4 wr/rd DPRIO addr_offset
+// 5 wr/rd DPRIO data
+// 6 rd/wr adce_standby, adce_capture, testbussel : bit 7 -- adcedone, bit 6 -- adcetestbus, bits 5,4 -- adce, 3 to 0 -- bussel
+// 7 rd/wr offset cancellation busy output to GX bit 0
+
+//local parameters
+localparam quad_address_width = 9;
+localparam IDLE_STATE = 2'b00;
+localparam WRITE_STATE = 2'b01;
+localparam READ_STATE = 2'b10;
+
+
+(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON"} *)
+reg [11:0] address_pres_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [11:0] logical_channel_addr_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [14:0] dprio_table_addr_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] pma_pcs_id_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg dprio_busy_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] data_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [5:0] testbussel;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] adce_testdata;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [1:0] control_reg;
+// mutex
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg mutex_value;
+//reg [15:0] mutex_owner;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [10:0] mutex_timeout_cntr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg offset_cancellation_busy;
+
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg basic_reconfig_absolute_addressing;
+
+
+wire [quad_address_width-1:0] quad_address;
+wire [quad_address_width-1:0] dprio_quad_address;
+
+wire busy_state;
+wire [15:0] dprio_address;
+wire dprio_busy;
+wire [15:0] dprio_datain;
+wire [15:0] dprio_dataout;
+wire dprio_dprioout;
+wire dprio_rden;
+wire dprio_pulse;
+wire rd_pulse;
+wire read_done;
+wire read_word_done;
+wire reset_system;
+wire dprio_wren;
+wire write_done;
+wire wr_pulse;
+wire read_data_valid;
+wire write_word_done;
+
+integer i,j;
+
+
+assign basic_reconfig_waitrequest = 1'b0;
+
+// synopsys translate_off
+initial
+begin
+ state = 2'b00;
+ basic_reconfig_irq = 1'b0;
+ logical_channel_addr_reg = 12'b0;
+ testbussel = 0;
+ control_reg = 0;
+ mutex_value = 0;
+ mutex_timeout_cntr = 0;
+ offset_cancellation_busy = 0;
+ data_reg = 16'h0000;
+ dprio_table_addr_reg = 15'h0000;
+ pma_pcs_id_reg = 2'b00;
+
+end
+// synopsys translate_on
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset === 1'b1)
+ adce_testdata <= 0;
+ else begin
+ for (i=0; i<=1; i=i+1)
+ begin
+ adce_testdata[i] <= aeq_fromgxb_data[(logical_channel_addr_reg) + i];
+ end
+ end
+end
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset === 1'b1)
+ begin
+ state <= IDLE_STATE;
+ basic_reconfig_readdata <= 16'b0;
+ basic_reconfig_irq <= 1'b0;
+ testbussel <= 0;
+ control_reg <= 0;
+ // mutex registers
+ mutex_value <= 0;
+ mutex_timeout_cntr <= 0;
+ end
+ else begin
+ // mutex
+ if (basic_reconfig_address == 3'b0)
+ begin
+ //read first only update the mutex_value
+ if (basic_reconfig_read == 1'b1)
+ begin
+ basic_reconfig_readdata <= {{31{1'b0}}, mutex_value};
+ // if (basic_reconfig_waitrequest == 1'b0)
+ if (mutex_value == 1'b0) // mutex is free, so grant access
+ mutex_value <= 1'b1;
+ end
+ else if (basic_reconfig_write == 1'b1)
+ begin
+ mutex_value <= 0;
+ end
+ end
+
+ case (state)
+ IDLE_STATE: begin
+ if (basic_reconfig_write == 1'b1)
+ begin
+ mutex_timeout_cntr <= 0; // reset the mutex_timeout counter
+ if (basic_reconfig_address == 3'b001)
+ begin
+ logical_channel_addr_reg <= basic_reconfig_writedata[11:0];
+ address_pres_reg <= {basic_reconfig_writedata[10:2], 1'b0, basic_reconfig_writedata[1:0]}; //chestan
+ end
+ else if (basic_reconfig_address == 3'b100)
+ begin
+ dprio_table_addr_reg <= basic_reconfig_writedata[14:0];
+ pma_pcs_id_reg <= basic_reconfig_writedata[11:10];
+ end
+ else if (basic_reconfig_address == 3'b011) // control reg
+ begin
+ if (basic_reconfig_writedata[0] == 1'b1) // write
+ begin
+ state <= WRITE_STATE;
+ control_reg <= 2'b01;
+ end
+ else if (basic_reconfig_writedata[1] == 1'b1) // read
+ begin
+ state <= READ_STATE;
+ control_reg <= 2'b10;
+ end
+ if (basic_reconfig_writedata[2] == 1'b0) begin
+ basic_reconfig_irq <= 1'b0; // clear WRITE interrupt
+ end
+ basic_reconfig_absolute_addressing <= basic_reconfig_writedata[3]; // use the full address from dprio_addr, not the derived address
+ end
+ else if (basic_reconfig_address == 3'b101) // data
+ begin
+ data_reg <= basic_reconfig_writedata[15:0];
+ end
+ else if (basic_reconfig_address == 3'b110) // testbussel
+ testbussel <= basic_reconfig_writedata[5:0];
+ else if (basic_reconfig_address == 3'b111)
+ offset_cancellation_busy <= basic_reconfig_writedata[0];
+ begin
+ end
+ end
+ else if (basic_reconfig_read == 1'b1)
+ begin
+ if (basic_reconfig_address == 3'b001)
+ basic_reconfig_readdata <= {{20{1'b0}}, logical_channel_addr_reg};
+ else if (basic_reconfig_address == 3'b010) // physical chnl
+ basic_reconfig_readdata <= {{21{1'b0}}, address_pres_reg[11:3], address_pres_reg[1:0]}; // check this
+ else if (basic_reconfig_address == 3'b011) // status
+ basic_reconfig_readdata <= {{23{1'b0}}, busy_state, {5{1'b0}}, basic_reconfig_irq, control_reg};
+ else if (basic_reconfig_address == 3'b100)
+ basic_reconfig_readdata <= {{20{1'b0}}, pma_pcs_id_reg, dprio_table_addr_reg};
+ else if (basic_reconfig_address == 3'b101) // DPRIO readdata
+ begin
+ basic_reconfig_readdata <= {{16{1'b0}}, data_reg};
+ basic_reconfig_irq <= 1'b0; // clear READ interrupt
+ end
+ else if (basic_reconfig_address == 3'b110)
+ basic_reconfig_readdata <= {{24{1'b0}}, adce_testdata, testbussel};
+ else if (basic_reconfig_address == 3'b111) // testbusdata
+ basic_reconfig_readdata <= {{31{1'b0}}, offset_cancellation_busy};
+ if (basic_reconfig_address != 3'b0) // if not reading the mutex val
+ mutex_timeout_cntr <= 0; // reset the mutex counter
+ end
+ else if (mutex_value == 1'b1) // if mutex was granted to someone
+ if (mutex_timeout_cntr == 10'd1000) // and they didnt do anything for 1000 cycles
+ begin
+ mutex_value <= 1'b0; // reset the mutex and give it to the next person
+ mutex_timeout_cntr <= 0;
+ end
+ else
+ mutex_timeout_cntr <= mutex_timeout_cntr[9:0] + 10'b1; // count up the timer from the last access
+ end
+ WRITE_STATE: begin
+ if (write_done)
+ begin
+ state <= IDLE_STATE;
+ basic_reconfig_irq <= 1'b1; // send interrupt to master
+ end
+ // allow status_register read here
+ if (basic_reconfig_read == 1'b1 && basic_reconfig_address == 3'b011)
+ basic_reconfig_readdata <= {{23{1'b0}}, busy_state, {5{1'b0}}, basic_reconfig_irq, control_reg};
+ end
+ READ_STATE: begin
+ if (read_word_done == 1'b1)
+ begin
+ data_reg <= dprio_dataout;
+ basic_reconfig_irq <= 1'b1; // send interrupt
+ state <= IDLE_STATE;
+ end
+ // allow status_register read here
+ if (basic_reconfig_read == 1'b1 && basic_reconfig_address == 3'b011)
+ basic_reconfig_readdata <= {{23{1'b0}}, busy_state, {5{1'b0}}, basic_reconfig_irq, control_reg};
+ end
+ default: begin
+ state <= IDLE_STATE;
+ end
+ endcase
+ end
+end
+
+// synopsys translate_off
+initial address_pres_reg = 0;
+// synopsys translate_on
+
+assign quad_address = logical_channel_addr_reg[10:2];
+assign dprio_address[15:0] = basic_reconfig_absolute_addressing ? {1'b0, dprio_table_addr_reg[14:0]} : {1'b0, address_pres_reg[2], address_pres_reg[1:0], pma_pcs_id_reg[1:0], dprio_table_addr_reg[9:0]};
+assign dprio_quad_address = address_pres_reg[11:3];
+assign dprio_dprioout = basic_reconfig_fromgxb_data[quad_address * 17];
+assign dprio_datain = data_reg;
+assign dprio_rden = rd_pulse;
+assign rd_pulse = (state == READ_STATE) & ~dprio_pulse & ~read_done;
+assign read_done = read_word_done | reset_system;
+assign read_word_done = (state == READ_STATE) & read_data_valid;
+assign read_data_valid = (state == READ_STATE) & dprio_pulse;
+assign dprio_wren = wr_pulse;
+assign wr_pulse = (state == WRITE_STATE) & ~dprio_pulse & ~write_done;
+assign write_done = write_word_done | reset_system;
+assign write_word_done = (state == WRITE_STATE) & dprio_pulse;
+assign reset_system = reset;
+assign busy_state = (state == READ_STATE) | (state == WRITE_STATE);
+
+// synopsys translate_off
+initial dprio_busy_reg = 0;
+// synopsys translate_on
+
+always @(posedge reconfig_clk) dprio_busy_reg <= dprio_busy;
+assign dprio_pulse = (dprio_busy_reg ^ dprio_busy) & (~dprio_busy);
+
+alt_dprio inst_alt_dprio (.dpclk(reconfig_clk),
+ .datain(dprio_datain),
+ .address(dprio_address),
+ .wren(dprio_wren),
+ .rden(dprio_rden),
+// .rdinc(),
+ .wren_data(1'b0),
+ .dprioout(dprio_dprioout), // reconfig_fromgxb_data[0]
+ .quad_address(dprio_quad_address),
+ // outputs
+ .dprioin(basic_reconfig_togxb_data[0]),
+ .dpriodisable(basic_reconfig_togxb_data[1]),
+ .dprioload(basic_reconfig_togxb_data[2]),
+ .dataout(dprio_dataout),
+ .busy(dprio_busy)
+ );
+
+//assign testbus_data = (testbussel == 3'b110) ? basic_reconfig_fromgxb_data : 'b0;
+
+assign basic_reconfig_togxb_data[3] = offset_cancellation_busy;
+
+always @(basic_reconfig_fromgxb_data)
+begin
+ for (i=0; i<number_of_reconfig_interfaces; i=i+1)
+ begin
+ for (j=0; j<= 15; j=j+1)
+ begin
+ testbus_data[(i*16) + j] = basic_reconfig_fromgxb_data[(i*17) + j+1];
+ end
+ end
+end
+
+always @(logical_channel_addr_reg or testbussel)
+begin
+ aeq_togxb_data = {number_of_reconfig_interfaces*24{1'b0}};
+ for (i=0; i<=5; i=i+1)
+ begin
+ aeq_togxb_data[(logical_channel_addr_reg*6) + i] = testbussel[i];
+ end
+end
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_dfe_tgx.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_dfe_tgx.sv
new file mode 100644
index 0000000000000000000000000000000000000000..107fa27aa9d4e7684eaf3ff65891450a40db21ac
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_dfe_tgx.sv
@@ -0,0 +1,502 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_dfe_tgx
+#(
+ parameter device_family = "StratixIV",
+ parameter number_of_reconfig_interfaces = 1
+)
+(
+ input wire reconfig_clk, // this will be the reconfig clk
+ input wire reset,
+
+ //avalon MM slave
+ input wire [2:0] dfe_address, // Check this! fix me!
+ input wire [31:0] dfe_writedata,
+ input wire dfe_write,
+ input wire dfe_read,
+
+ //output MM slave
+ output wire [31:0] dfe_readdata, // from MM
+ output wire dfe_waitrequest, // from MM
+
+ output reg dfe_irq,
+
+ // input from base_reconfig
+ input wire dfe_irq_from_base,
+ input wire dfe_waitrequest_from_base,
+
+ // output to base_reconfig
+ // Avalon MM Master
+ output wire [2:0] dfe_address_base, // 3 bit MM
+ output wire [31:0] dfe_writedata_base,
+ output wire dfe_write_base, // start write to GXB
+ output wire dfe_read_base, // start read from GXB
+
+ // input from base reconfig
+ input wire [31:0] dfe_readdata_base // data from read command
+
+);
+
+//local parameters
+//state
+localparam IDLE_STATE = 4'b0000;
+localparam LOGICAL_ADDRESS_STATE = 4'b0001;
+localparam WRITE_DATA_STATE = 4'b0010;
+localparam CONTROL_STATE = 4'b0011;
+localparam BUSY_STATE = 4'b0100;
+localparam READ_PHY_ADDR_STATE = 4'b0101;
+localparam CHECK_PHY_ADDR_STATE = 4'b0110;
+localparam ADDRESS_OFFSET_STATE = 4'b0111;
+localparam BASE_BUSY_STATE = 4'b1000;
+localparam READ_DATA_STATE = 4'b1001;
+localparam WRITE_DONE_STATE = 4'b1010;
+
+localparam ILLEGAL_PHYSICAL_CHNL = 10'b1111111111;
+wire [4:0] dfe_addr_all; // 5 bit MM
+
+wire mutex_grant;
+wire [31:0] master_read_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [3:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg write_read_control;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_read;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [31:0] master_write_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [2:0] master_address;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg req_and_use_mutex;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg set_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg wait_phy_addr_ready;
+
+wire [4:0] master_address_shifted;
+
+//alt_dfe instantiation
+wire alt_dfe_busy;
+wire [15:0] alt_dfe_dprio_dataout;
+wire alt_dfe_dprio_wren;
+wire alt_dfe_dprio_rden;
+wire [(number_of_reconfig_interfaces*4-1) : 0] alt_dfe_error;
+
+wire [15:0] alt_dfe_dprio_addr;
+wire [8:0] alt_dfe_quad_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [11:0] alt_dfe_remap_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_dfe_dprio_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_dfe_dprio_busy_int;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] alt_dfe_dprio_datain;
+
+function integer CLogB2;
+input integer Depth;
+integer i;
+begin
+i = Depth;
+for(CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1)
+i = i >> 1;
+end
+endfunction
+
+// synopsys translate_off
+initial begin
+ state = 3'b000;
+ alt_dfe_remap_addr = 12'h000;
+ req_and_use_mutex = 1'b0;
+ wait_phy_addr_ready = 1'b0;
+ alt_dfe_dprio_datain = 16'h0000;
+ alt_dfe_dprio_busy = 1'b0;
+ alt_dfe_dprio_busy_int = 1'b0;
+
+ master_write = 1'b0;
+ master_read = 1'b0;
+ master_write_data = {32{1'b0}};
+ master_address = 3'h0;
+
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy = 1'b0; // 1 for assert busy, 0 for deassert busy
+
+ dfe_irq = 1'b0;
+
+end
+// synopsys translate_on
+
+integer count;
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset)
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ master_write_data <= {32{1'b0}};
+ master_address <= 3'h0;
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ req_and_use_mutex <= 1'b0;
+ wait_phy_addr_ready <= 1'b0;
+ alt_dfe_dprio_busy_int<= 1'b0;
+ dfe_irq <= 1'b0;
+ end
+ else begin
+ if(alt_dfe_busy == 1'b0)
+ req_and_use_mutex <= 1'b0;
+ else
+ req_and_use_mutex <= 1'b1;
+
+ case (state)
+ IDLE_STATE:
+ begin
+ dfe_irq <= 1'b0; // reset write/read done flag
+ //reset the signal
+ set_busy <= 1'b0;
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ alt_dfe_remap_addr <= 12'h000;
+
+ //alt_dfe will not assert wren and rden at the same time
+ if((alt_dfe_dprio_wren == 1'b1) || (alt_dfe_dprio_rden == 1'b1))
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(alt_dfe_dprio_wren == 1'b1)
+ write_read_control <= 1'b1; // 1 for write
+ else
+ write_read_control <= 1'b0; // 0 for read
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ else
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ state <= IDLE_STATE;
+ end
+ end
+ LOGICAL_ADDRESS_STATE: //sending channel and quad address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h1;
+ master_write_data <= {{21{1'b0}}, alt_dfe_quad_addr, alt_dfe_dprio_addr[13:12]};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= READ_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ end
+ READ_PHY_ADDR_STATE: //read phsical address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h2;
+ master_read <= 1'b1;
+ master_write <= 1'b0;
+ if (wait_phy_addr_ready == 1'b1)
+ begin
+ wait_phy_addr_ready <= 1'b0;
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ wait_phy_addr_ready <= 1'b1;
+ state <= READ_PHY_ADDR_STATE;
+ //state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_PHY_ADDR_STATE;
+ end
+ end
+ CHECK_PHY_ADDR_STATE: //check physical address correct or not
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ if (master_read_data[9:0] == ILLEGAL_PHYSICAL_CHNL)
+ begin
+ // synopsys translate_off
+ $display ("Illegal physical address: 10'h%h", master_read_data);
+ $display ("Time: %0t Instance: %m", $time);
+ // synopsys translate_on
+ alt_dfe_remap_addr <= 12'hfff;
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ alt_dfe_remap_addr <= master_read_data[11:0];
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ else
+ begin
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ ADDRESS_OFFSET_STATE: // send address offset to alt_dprio
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h4;
+ master_write_data <= {{20{1'b0}}, alt_dfe_dprio_addr[11:0]};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(write_read_control == 1'b1)
+ state <= WRITE_DATA_STATE;
+ else
+ state <= CONTROL_STATE;
+ end
+ else
+ begin
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ WRITE_DATA_STATE:
+ begin
+ master_address <= 3'h5;
+ master_write_data = {{16{1'b0}}, alt_dfe_dprio_dataout};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= CONTROL_STATE;
+ end
+ CONTROL_STATE: // sending write/read command
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h3; // get ready to send control command to alt_dprio
+ master_write_data <= {{29{1'b0}}, (~write_read_control), write_read_control};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ state <= BASE_BUSY_STATE;
+ end
+ else
+ begin
+ state <= CONTROL_STATE;
+ end
+ end
+ BASE_BUSY_STATE: // send busy to reconfig_togxb
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h7; // set offset cancellation busy to reconfig_togxb
+ master_write_data <= {{30{1'b0}}, alt_dfe_busy};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(set_busy == 1'b0)
+ begin
+ set_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ else
+ begin
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= BASE_BUSY_STATE;
+ end
+ end
+ BUSY_STATE: // wait for write done
+ begin
+ if(dfe_irq_from_base == 1'b1)
+ begin
+ alt_dfe_dprio_busy <= 1'b1;
+ if(write_read_control == 1'b0) //read
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_dfe_dprio_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ end
+ WRITE_DONE_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(dfe_irq_from_base == 1'b1)
+ begin
+ if(alt_dfe_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_dfe_dprio_busy_int <= master_read_data[8];
+ alt_dfe_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ else
+ begin
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ master_address <= 3'h3;
+ master_write_data <= {{16{1'b0}}, {16'h0000}}; //acknowledge write operation
+ alt_dfe_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_dfe_dprio_busy <= 1'b0;
+ dfe_irq <= 1'b1; // write done
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ READ_DATA_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(dfe_irq_from_base == 1'b1)
+ begin
+ if(alt_dfe_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_dfe_dprio_busy_int <= master_read_data[8];
+ alt_dfe_dprio_busy <= 1'b1;
+ end
+ else
+ begin
+ master_address <= 3'h5;
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ alt_dfe_dprio_busy <= 1'b1;
+ end
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ dfe_irq <= 1'b1; // read done
+ alt_dfe_dprio_datain <= master_read_data[15:0];
+ alt_dfe_dprio_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_DATA_STATE;
+ end
+ end
+ default:
+ begin
+ state <= IDLE_STATE;
+ end
+ endcase
+ end
+end
+
+alt_dfe #(
+ .channel_address_width (CLogB2(number_of_reconfig_interfaces*4)),
+ .avmm_slave_addr_width (3),
+ .avmm_slave_rdata_width ( 32),
+ .avmm_slave_wdata_width (32)
+)alt_dfe_inst(
+ .i_resetn (~reset),
+ .i_avmm_clk (reconfig_clk),
+ .i_avmm_saddress (dfe_address),
+ .i_avmm_sread (dfe_read),
+ .i_avmm_swrite (dfe_write),
+ .i_avmm_swritedata (dfe_writedata),
+//. i_avmm_sbegintransfer,
+ .o_avmm_sreaddata (dfe_readdata),
+ .o_avmm_swaitrequest (dfe_waitrequest),
+
+ .i_remap_address (alt_dfe_remap_addr),
+ .o_quad_address (alt_dfe_quad_addr),
+ .o_reconfig_busy (alt_dfe_busy),
+
+ .i_dprio_busy (alt_dfe_dprio_busy),
+ .i_dprio_in (alt_dfe_dprio_datain),
+ .o_dprio_wren (alt_dfe_dprio_wren),
+ .o_dprio_rden (alt_dfe_dprio_rden),
+ .o_dprio_addr (alt_dfe_dprio_addr),
+ .o_dprio_data (alt_dfe_dprio_dataout)
+);
+alt_mutex_acq #(
+ .mutex_wait_time(103), //analog uses 101, offset cancellation uses 102
+ .addr_width(5),
+ .data_width(32)
+)
+mutex_inst (
+ .clk(reconfig_clk),
+ .reset(reset),
+// inputs to the base that should be routed through the mutex
+ .address(master_address_shifted),
+ .writedata(master_write_data),
+ .write(master_write),
+ .read(master_read),
+// output from the mutex which is processed form of output from base
+ .waitrequest(),
+ .readdata(master_read_data),
+
+// outputs from mutex to be routed to the base
+ .master_address(dfe_addr_all),
+ .master_writedata(dfe_writedata_base),
+ .master_write(dfe_write_base),
+ .master_read(dfe_read_base),
+
+// these ports are from the base routed to the mutex
+ .master_waitrequest(dfe_waitrequest_from_base),
+ .master_readdata(dfe_readdata_base), // from MM
+
+//request signal to the mutex should be kept high as long as the mutex is being used
+ .mutex_req(req_and_use_mutex),
+// output from mutex indicates whether you have mutex or not
+ .mutex_grant(mutex_grant)
+);
+assign dfe_address_base = dfe_addr_all[ 4:2];
+//wire assignment
+assign master_address_shifted = {master_address, {2'b00}};
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_eyemon_tgx.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_eyemon_tgx.sv
new file mode 100644
index 0000000000000000000000000000000000000000..cb0a8d147058a8522ece5c1f9b7c0eb17b8ec6bc
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_eyemon_tgx.sv
@@ -0,0 +1,504 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_eyemon_tgx
+#(
+ parameter device_family = "StratixIV",
+ parameter number_of_reconfig_interfaces = 1
+)
+(
+ input wire reconfig_clk, // this will be the reconfig clk
+ input wire reset,
+
+ //avalon MM slave
+ input wire [2:0] eyemon_address, // Check this! fix me!
+ input wire [31:0] eyemon_writedata,
+ input wire eyemon_write,
+ input wire eyemon_read,
+
+ //output MM slave
+ output wire [31:0] eyemon_readdata, // from MM
+ output wire eyemon_waitrequest, // from MM
+
+ output reg eyemon_irq,
+
+ // input from base_reconfig
+ input wire eyemon_irq_from_base,
+ input wire eyemon_waitrequest_from_base,
+
+ // output to base_reconfig
+ // Avalon MM Master
+ output wire [2:0] eyemon_address_base, // 3 bit MM
+ output wire [31:0] eyemon_writedata_base,
+ output wire eyemon_write_base, // start write to GXB
+ output wire eyemon_read_base, // start read from GXB
+
+ // input from base reconfig
+ input wire [31:0] eyemon_readdata_base // data from read command
+
+);
+
+//local parameters
+//state
+localparam IDLE_STATE = 4'b0000;
+localparam LOGICAL_ADDRESS_STATE = 4'b0001;
+localparam WRITE_DATA_STATE = 4'b0010;
+localparam CONTROL_STATE = 4'b0011;
+localparam BUSY_STATE = 4'b0100;
+localparam READ_PHY_ADDR_STATE = 4'b0101;
+localparam CHECK_PHY_ADDR_STATE = 4'b0110;
+localparam ADDRESS_OFFSET_STATE = 4'b0111;
+localparam BASE_BUSY_STATE = 4'b1000;
+localparam READ_DATA_STATE = 4'b1001;
+localparam WRITE_DONE_STATE = 4'b1010;
+
+localparam ILLEGAL_PHYSICAL_CHNL = 10'b1111111111;
+
+wire [4:0] eyemon_address_all; // 5 bit MM
+wire mutex_grant;
+wire [31:0] master_read_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [3:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg write_read_control;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_read;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [31:0] master_write_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [2:0] master_address;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg req_and_use_mutex;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg set_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg wait_phy_addr_ready;
+
+wire [4:0] master_address_shifted;
+
+//alt_eyemon instantiation
+wire alt_eyemon_busy;
+wire [15:0] alt_eyemon_dprio_dataout;
+wire alt_eyemon_dprio_wren;
+wire alt_eyemon_dprio_rden;
+wire [(number_of_reconfig_interfaces*4-1) : 0] alt_eyemon_error;
+
+wire [15:0] alt_eyemon_dprio_addr;
+wire [8:0] alt_eyemon_quad_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [11:0] alt_eyemon_remap_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_eyemon_dprio_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_eyemon_dprio_busy_int;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] alt_eyemon_dprio_datain;
+
+function integer CLogB2;
+input integer Depth;
+integer i;
+begin
+i = Depth;
+for(CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1)
+i = i >> 1;
+end
+endfunction
+
+// synopsys translate_off
+initial begin
+ state = 3'b000;
+ alt_eyemon_remap_addr = 12'h000;
+ req_and_use_mutex = 1'b0;
+ wait_phy_addr_ready = 1'b0;
+ alt_eyemon_dprio_datain = 16'h0000;
+ alt_eyemon_dprio_busy = 1'b0;
+ alt_eyemon_dprio_busy_int = 1'b0;
+
+ master_write = 1'b0;
+ master_read = 1'b0;
+ master_write_data = {32{1'b0}};
+ master_address = 3'h0;
+
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy = 1'b0; // 1 for assert busy, 0 for deassert busy
+
+ eyemon_irq = 1'b0;
+
+end
+// synopsys translate_on
+
+integer count;
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset)
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ master_write_data <= {32{1'b0}};
+ master_address <= 3'h0;
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ req_and_use_mutex <= 1'b0;
+ wait_phy_addr_ready <= 1'b0;
+ alt_eyemon_dprio_busy_int<= 1'b0;
+ eyemon_irq <= 1'b0;
+ end
+ else begin
+ if(alt_eyemon_busy == 1'b0)
+ req_and_use_mutex <= 1'b0;
+ else
+ req_and_use_mutex <= 1'b1;
+
+ case (state)
+ IDLE_STATE:
+ begin
+ eyemon_irq <= 1'b0; // reset write/read done flag
+ //reset the signal
+ set_busy <= 1'b0;
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ alt_eyemon_remap_addr <= 12'h000;
+
+ //alt_eyemon will not assert wren and rden at the same time
+ if((alt_eyemon_dprio_wren == 1'b1) || (alt_eyemon_dprio_rden == 1'b1))
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(alt_eyemon_dprio_wren == 1'b1)
+ write_read_control <= 1'b1; // 1 for write
+ else
+ write_read_control <= 1'b0; // 0 for read
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ else
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ state <= IDLE_STATE;
+ end
+ end
+ LOGICAL_ADDRESS_STATE: //sending channel and quad address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h1;
+ master_write_data <= {{21{1'b0}}, alt_eyemon_quad_addr, alt_eyemon_dprio_addr[13:12]};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= READ_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ end
+ READ_PHY_ADDR_STATE: //read phsical address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h2;
+ master_read <= 1'b1;
+ master_write <= 1'b0;
+ if (wait_phy_addr_ready == 1'b1)
+ begin
+ wait_phy_addr_ready <= 1'b0;
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ wait_phy_addr_ready <= 1'b1;
+ state <= READ_PHY_ADDR_STATE;
+ //state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_PHY_ADDR_STATE;
+ end
+ end
+ CHECK_PHY_ADDR_STATE: //check physical address correct or not
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ if (master_read_data[9:0] == ILLEGAL_PHYSICAL_CHNL)
+ begin
+ // synopsys translate_off
+ $display ("Illegal physical address: 10'h%h", master_read_data);
+ $display ("Time: %0t Instance: %m", $time);
+ // synopsys translate_on
+ alt_eyemon_remap_addr <= 12'hfff;
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ alt_eyemon_remap_addr <= master_read_data[11:0];
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ else
+ begin
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ ADDRESS_OFFSET_STATE: // send address offset to alt_dprio
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h4;
+ master_write_data <= {{20{1'b0}}, alt_eyemon_dprio_addr[11:0]};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(write_read_control == 1'b1)
+ state <= WRITE_DATA_STATE;
+ else
+ state <= CONTROL_STATE;
+ end
+ else
+ begin
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ WRITE_DATA_STATE:
+ begin
+ master_address <= 3'h5;
+ master_write_data = {{16{1'b0}}, alt_eyemon_dprio_dataout};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= CONTROL_STATE;
+ end
+ CONTROL_STATE: // sending write/read command
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h3; // get ready to send control command to alt_dprio
+ master_write_data <= {{29{1'b0}}, (~write_read_control), write_read_control};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ state <= BASE_BUSY_STATE;
+ end
+ else
+ begin
+ state <= CONTROL_STATE;
+ end
+ end
+ BASE_BUSY_STATE: // send busy to reconfig_togxb
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h7; // set offset cancellation busy to reconfig_togxb
+ master_write_data <= {{30{1'b0}}, alt_eyemon_busy};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(set_busy == 1'b0)
+ begin
+ set_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ else
+ begin
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= BASE_BUSY_STATE;
+ end
+ end
+ BUSY_STATE: // wait for write done
+ begin
+ if(eyemon_irq_from_base == 1'b1)
+ begin
+ alt_eyemon_dprio_busy <= 1'b1;
+ if(write_read_control == 1'b0) //read
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_eyemon_dprio_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ end
+ WRITE_DONE_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(eyemon_irq_from_base == 1'b1)
+ begin
+ if(alt_eyemon_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_eyemon_dprio_busy_int <= master_read_data[8];
+ alt_eyemon_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ else
+ begin
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ master_address <= 3'h3;
+ master_write_data <= {{16{1'b0}}, {16'h0000}}; //acknowledge write operation
+ alt_eyemon_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_eyemon_dprio_busy <= 1'b0;
+ eyemon_irq <= 1'b1; // write done
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ READ_DATA_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(eyemon_irq_from_base == 1'b1)
+ begin
+ if(alt_eyemon_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_eyemon_dprio_busy_int <= master_read_data[8];
+ alt_eyemon_dprio_busy <= 1'b1;
+ end
+ else
+ begin
+ master_address <= 3'h5;
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ alt_eyemon_dprio_busy <= 1'b1;
+ end
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ eyemon_irq <= 1'b1; // read done
+ alt_eyemon_dprio_datain <= master_read_data[15:0];
+ alt_eyemon_dprio_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_DATA_STATE;
+ end
+ end
+ default:
+ begin
+ state <= IDLE_STATE;
+ end
+ endcase
+ end
+end
+
+alt_eyemon #(
+ .channel_address_width (CLogB2(number_of_reconfig_interfaces*4)),
+ .avmm_slave_addr_width (3),
+ .avmm_slave_rdata_width ( 32),
+ .avmm_slave_wdata_width (32)
+)alt_eyemon_inst(
+ .i_resetn (~reset),
+ .i_avmm_clk (reconfig_clk),
+ .i_avmm_saddress (eyemon_address),
+ .i_avmm_sread (eyemon_read),
+ .i_avmm_swrite (eyemon_write),
+ .i_avmm_swritedata (eyemon_writedata),
+//. i_avmm_sbegintransfer,
+ .o_avmm_sreaddata (eyemon_readdata),
+ .o_avmm_swaitrequest (eyemon_waitrequest),
+
+ .i_remap_phase (1'b1), // need to figure out best way to control this - for now, always remap - fix me!
+ .i_remap_address (alt_eyemon_remap_addr),
+ .o_quad_address (alt_eyemon_quad_addr),
+ .o_reconfig_busy (alt_eyemon_busy),
+
+ .i_dprio_busy (alt_eyemon_dprio_busy),
+ .i_dprio_in (alt_eyemon_dprio_datain),
+ .o_dprio_wren (alt_eyemon_dprio_wren),
+ .o_dprio_rden (alt_eyemon_dprio_rden),
+ .o_dprio_addr (alt_eyemon_dprio_addr),
+ .o_dprio_data (alt_eyemon_dprio_dataout)
+);
+alt_mutex_acq #(
+ .mutex_wait_time(103), //analog uses 101, offset cancellation uses 102
+ .addr_width(5),
+ .data_width(32)
+)
+mutex_inst (
+ .clk(reconfig_clk),
+ .reset(reset),
+// inputs to the base that should be routed through the mutex
+ .address(master_address_shifted),
+ .writedata(master_write_data),
+ .write(master_write),
+ .read(master_read),
+// output from the mutex which is processed form of output from base
+ .waitrequest(),
+ .readdata(master_read_data),
+
+// outputs from mutex to be routed to the base
+ .master_address({eyemon_address_all}),
+ .master_writedata(eyemon_writedata_base),
+ .master_write(eyemon_write_base),
+ .master_read(eyemon_read_base),
+
+// these ports are from the base routed to the mutex
+ .master_waitrequest(eyemon_waitrequest_from_base),
+ .master_readdata(eyemon_readdata_base), // from MM
+
+//request signal to the mutex should be kept high as long as the mutex is being used
+ .mutex_req(req_and_use_mutex),
+// output from mutex indicates whether you have mutex or not
+ .mutex_grant(mutex_grant)
+);
+
+//wire assignment
+assign eyemon_address_base = eyemon_address_all[4:2];
+assign master_address_shifted = {master_address, {2'b00}};
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..102856f4162133620df696f7e6ccb75bc2dca7f4
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_h.sv
@@ -0,0 +1,266 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Top-level definitions for transceiver reconfig IP
+//
+// $Header$
+//
+// PACKAGE DECLARATION
+package alt_xcvr_reconfig_h;
+
+ ////////////////////////////////////////////////////////
+ // Top-level register map for transceiver reconfig IP
+ ////////////////////////////////////////////////////////
+ localparam W_XR_ADDR = 7; // address width on mgmt interface
+ localparam W_XR_FEATURE_LADDR = 3; // address width of standard feature block, and basic logical interface
+ typedef bit [W_XR_ADDR -1:0] t_xreconf_addr;
+ typedef bit [W_XR_FEATURE_LADDR-1:0] t_xr_feature_addr;
+
+ // Feature block indices (used for address decoding for each block)
+ localparam INDEX_XR_OFFSET = 0;
+ localparam INDEX_XR_ANALOG = 1;
+ localparam INDEX_XR_EYEMON = 2;
+ localparam INDEX_XR_DFE = 3;
+ localparam INDEX_XR_DIRECT = 4;
+ localparam INDEX_XR_ADCE = 5;
+ localparam INDEX_XR_LC = 6;
+ localparam INDEX_XR_MIF = 7;
+ localparam INDEX_XR_PLL = 8;
+ localparam INDEX_XR_DCD = 9;
+ localparam INDEX_XR_END = 10; // must always mark end of address space
+
+ // Each feature block is allocated an 8-word address range
+ localparam [W_XR_ADDR-1:0] ADDR_XR_OFFSET_BASE = t_xreconf_addr'(INDEX_XR_OFFSET << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_BASE = t_xreconf_addr'(INDEX_XR_ANALOG << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_BASE = t_xreconf_addr'(INDEX_XR_EYEMON << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_BASE = t_xreconf_addr'(INDEX_XR_DFE << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_BASE = t_xreconf_addr'(INDEX_XR_DIRECT << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_BASE = t_xreconf_addr'(INDEX_XR_ADCE << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_LC_BASE = t_xreconf_addr'(INDEX_XR_LC << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_BASE = t_xreconf_addr'(INDEX_XR_MIF << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_BASE = t_xreconf_addr'(INDEX_XR_PLL << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_BASE = t_xreconf_addr'(INDEX_XR_DCD << W_XR_FEATURE_LADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_END_BASE = t_xreconf_addr'(INDEX_XR_END << W_XR_FEATURE_LADDR); // must always mark end of address space
+
+ localparam [W_XR_FEATURE_LADDR-1:0] XR_STATUS_OFST = t_xr_feature_addr'(2);
+ localparam XR_STATUS_OFST_COMB_BUSY = 8;
+
+ ////////////////////////////////////////////////////////
+ // Offset Cancellation block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_OFFSET_STATUS = t_xreconf_addr'(ADDR_XR_OFFSET_BASE + 2);
+
+
+ ////////////////////////////////////////////////////////
+ // Analog block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_LCH = t_xreconf_addr'(ADDR_XR_ANALOG_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_PCH = t_xreconf_addr'(ADDR_XR_ANALOG_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_STATUS = t_xreconf_addr'(ADDR_XR_ANALOG_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_OFFSET = t_xreconf_addr'(ADDR_XR_ANALOG_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ANALOG_DATA = t_xreconf_addr'(ADDR_XR_ANALOG_BASE + 4);
+
+ // Analog internal register offsets
+ // These are to be written to the analog offset address register, ADDR_XR_ANALOG_OFFSET
+ localparam XR_ANALOG_OFFSET_VOD = 0;
+ localparam XR_ANALOG_OFFSET_PREEMPH0T = 1;
+ localparam XR_ANALOG_OFFSET_PREEMPH1T = 2;
+ localparam XR_ANALOG_OFFSET_PREEMPH2T = 3;
+ localparam XR_ANALOG_OFFSET_RXDCGAIN = 16;
+ localparam XR_ANALOG_OFFSET_RXEQCTRL = 17;
+ localparam XR_ANALOG_OFFSET_PRECDRLPBK = 32;
+ localparam XR_ANALOG_OFFSET_POSTCDRLPBK = 33;
+
+ ////////////////////////////////////////////////////////
+ // DFE block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_LCH = t_xreconf_addr'(ADDR_XR_DFE_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_PCH = t_xreconf_addr'(ADDR_XR_DFE_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_STATUS = t_xreconf_addr'(ADDR_XR_DFE_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_OFFSET = t_xreconf_addr'(ADDR_XR_DFE_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DFE_DATA = t_xreconf_addr'(ADDR_XR_DFE_BASE + 4);
+
+ // DFE internal register offsets
+ // These are to be written to the DFE offset address register, ADDR_XR_DFE_OFFSET
+ localparam XR_DFE_OFFSET_CTRL = 0;
+ localparam XR_DFE_OFFSET_TAP1 = 1;
+ localparam XR_DFE_OFFSET_TAP2 = 2;
+ localparam XR_DFE_OFFSET_TAP3 = 3;
+ localparam XR_DFE_OFFSET_TAP4 = 4;
+ localparam XR_DFE_OFFSET_TAP5 = 5;
+ localparam XR_DFE_OFFSET_REF = 6;
+ localparam XR_DFE_OFFSET_STEP = 7;
+ localparam XR_DFE_OFFSET_DFE12 = 18;
+ localparam XR_DFE_OFFSET_DFE13 = 19;
+ localparam XR_DFE_OFFSET_DFE14 = 20;
+ localparam XR_DFE_OFFSET_DFE15 = 21;
+ localparam XR_DFE_OFFSET_CAL_PLL = 22;
+ localparam XR_DFE_OFFSET_CAL_TBUS = 23;
+ localparam XR_DFE_OFFSET_CAL_SAMPL = 24;
+ ////////////////////////////////////////////////////////
+ // Eyemon block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_LCH = t_xreconf_addr'(ADDR_XR_EYEMON_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_PCH = t_xreconf_addr'(ADDR_XR_EYEMON_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_STATUS = t_xreconf_addr'(ADDR_XR_EYEMON_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_OFFSET = t_xreconf_addr'(ADDR_XR_EYEMON_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_EYEMON_DATA = t_xreconf_addr'(ADDR_XR_EYEMON_BASE + 4);
+
+ // EYEMON internal register offsets
+ // These are to be written to the EYEMON offset address register, ADDR_XR_EYEMON_OFFSET
+ localparam XR_EYEMON_OFFSET_CTRL = 0;
+ localparam XR_EYEMON_OFFSET_HPHASE = 1;
+ localparam XR_EYEMON_OFFSET_VHEIGHT = 2;
+ localparam XR_EYEMON_OFFSET_EYEMON16 = 3;
+ localparam XR_EYEMON_OFFSET_EYEMON17 = 4;
+
+ ////////////////////////////////////////////////////////
+ // ADCE block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_LCH = t_xreconf_addr'(ADDR_XR_ADCE_BASE + 0); // Logical channel number
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_PCH = t_xreconf_addr'(ADDR_XR_ADCE_BASE + 1); // Physical channel number
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_STATUS = t_xreconf_addr'(ADDR_XR_ADCE_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_OFFSET = t_xreconf_addr'(ADDR_XR_ADCE_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_ADCE_DATA = t_xreconf_addr'(ADDR_XR_ADCE_BASE + 4);
+
+ // ADCE internal register offsets
+ // These are to be written to the ADCE offset address register, ADDR_XR_ADCE_OFFSET
+ localparam XR_ADCE_OFFSET_CTRL = 0;
+ localparam XR_ADCE_OFFSET_RESULTS = 1; // Manual setting equivalent to ADCE results
+ localparam XR_ADCE_OFFSET_RADCE_ATT_0 = 9; // radce_att[15: 0]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_1 = 10; // radce_att[31:15]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_2 = 11; // radce_att[47:32]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_3 = 12; // radce_att[63:48]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_4 = 13; // radce_att[79:64]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_5 = 14; // radce_att[95:80]
+ localparam XR_ADCE_OFFSET_RADCE_ATT_6 = 15; // radce_att[111:96]
+
+ ////////////////////////////////////////////////////////
+ // DCD block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_LCH = t_xreconf_addr'(ADDR_XR_DCD_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_PCH = t_xreconf_addr'(ADDR_XR_DCD_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_STATUS = t_xreconf_addr'(ADDR_XR_DCD_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_OFFSET = t_xreconf_addr'(ADDR_XR_DCD_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DCD_DATA = t_xreconf_addr'(ADDR_XR_DCD_BASE + 4);
+
+ // DCD internal register offsets
+ // These are to be written to the DFE offset address register, ADDR_XR_DCD_OFFSET
+ localparam XR_DCD_OFFSET_CTRL = 0;
+
+ ////////////////////////////////////////////////////////
+ // MIF block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_LCH = t_xreconf_addr'(ADDR_XR_MIF_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_PCH = t_xreconf_addr'(ADDR_XR_MIF_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_STATUS = t_xreconf_addr'(ADDR_XR_MIF_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_OFFSET = t_xreconf_addr'(ADDR_XR_MIF_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_MIF_DATA = t_xreconf_addr'(ADDR_XR_MIF_BASE + 4);
+
+ ////////////////////////////////////////////////////////
+ // PLL block addresses
+ ////////////////////////////////////////////////////////
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_LCH = t_xreconf_addr'(ADDR_XR_PLL_BASE + 0);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_PCH = t_xreconf_addr'(ADDR_XR_PLL_BASE + 1);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_STATUS = t_xreconf_addr'(ADDR_XR_PLL_BASE + 2);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_OFFSET = t_xreconf_addr'(ADDR_XR_PLL_BASE + 3);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_PLL_DATA = t_xreconf_addr'(ADDR_XR_PLL_BASE + 4);
+
+
+
+
+ ////////////////////////////////////////////////////////
+ // Basic block addresses (internal, private addresses)
+ ////////////////////////////////////////////////////////
+ // The 'basic' interface block is the switch that routes requests to
+ // an appropriate physical reconfiguration interface. A logical channel
+ // number acts as a channel ID, which allows the basic block to find
+ // the corresponding physical reconfiguration interface, and a physical
+ // channel index within a physical interface.
+ //
+ // The Basic (B) block features are also available via the direct access block.
+ // All users of the basic block, including the direct access block, must
+ // acquire appropriate semaphores before using an interface, and release
+ // the semaphores when done, to avoid locking out other feature blocks.
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_MUTEX = t_xr_feature_addr'(0);
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_LOGICAL_CHANNEL = t_xr_feature_addr'(1);
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_PHYSICAL_CHANNEL = t_xr_feature_addr'(2);
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_CONTROL = t_xr_feature_addr'(3);
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_OFFSET_ADDR = t_xr_feature_addr'(4);
+ localparam [W_XR_FEATURE_LADDR-1:0] ADDR_XCVR_RECONFIG_BASIC_DATA = t_xr_feature_addr'(5);
+
+
+ ////////////////////////////////////////////////////////
+ // Direct Access & Basic block addresses
+ ////////////////////////////////////////////////////////
+ //
+ // The minimum steps to read & write a reconfiguration word are the following:
+ // Step 1 - acquire basic arbiter lock (write 1 to ADDR_XR_DIRECT_ARB_ACQ)
+ // Step 2 - write logical channel number to ADDR_XR_DIRECT_LCH
+ // Step 3 - acquire channel lock
+ // 3a - request channel lock (write XR_DIRECT_CONTROL_PHYS_LOCK_SET to ADDR_XR_DIRECT_CONTROL)
+ // 3b - confirm channel lock (read ADDR_XR_DIRECT_CONTROL, mask with XR_DIRECT_STATUS_BITMASK_PHYS_LOCK_GRANTED)
+ // -- repeat step 3b until result after applying mask is != 0
+ // Step 4 - write channel offset address to ADDR_XR_DIRECT_OFFSET
+ // Step 5 - read existing value from reconfig space, modify, then write back
+ // 5a (read cycle part 1) - write XR_DIRECT_CONTROL_RECONF_READ to ADDR_XR_DIRECT_CONTROL
+ // 5b (read cycle part 2) - read data from ADDR_XR_DIRECT_DATA
+ // 5c (write cycle part 1) - write modified value to ADDR_XR_DIRECT_DATA
+ // 5d (write cycle part 2) - write XR_DIRECT_CONTROL_RECONF_WRITE to ADDR_XR_DIRECT_CONTROL
+ // -- addtional read-modify-write cycles, repeat from step 2 or 4 (can skip step 3a)
+ // Step 6 - release channel lock (write XR_DIRECT_CONTROL_PHYS_LOCK_CLEAR to ADDR_XR_DIRECT_CONTROL)
+ // Step 7 - release basic arbiter lock (write 0 to ADDR_XR_DIRECT_ARB_ACQ)
+ //
+ // Direct/Basic register bitmap ---------------------------------------------------------
+ // word addr wr/rd description
+ // ------------------------------------------------------
+ // 0 wr basic arbiter, 1 to request access, 0 to release lock
+ // 1 wr/rd logical channel number
+ // 2 rd physical channel number. When lower 3 bits are 3'b111, means ch is not present
+ // 3 wr/rd status/control -- see XR_DIRECT_CONTROL_* opcodes and XR_DIRECT_STATUS_* bitfield definitions
+ // 4 wr/rd offset_addr -- for opcode-based reads & writes
+ // 5 wr/rd data -- for opcode-based reads & writes
+ // 6 -- reserved
+ // 7 -- reserved
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_ARB_ACQ = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + 0); // write 1 to request B access, 0 to release
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_LCH = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + ADDR_XCVR_RECONFIG_BASIC_LOGICAL_CHANNEL);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_PCH = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + ADDR_XCVR_RECONFIG_BASIC_PHYSICAL_CHANNEL);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_CONTROL = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + ADDR_XCVR_RECONFIG_BASIC_CONTROL);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_OFFSET = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + ADDR_XCVR_RECONFIG_BASIC_OFFSET_ADDR);
+ localparam [W_XR_ADDR-1:0] ADDR_XR_DIRECT_DATA = t_xreconf_addr'(ADDR_XR_DIRECT_BASE + ADDR_XCVR_RECONFIG_BASIC_DATA);
+
+ // Opcode values for writes to control word, ADDR_XR_DIRECT_CONTROL
+ localparam XR_DIRECT_CONTROL_RECONF_WRITE = 32'b0000; // reconfig space: write current DATA to OFFSET addr (as physical addr or ch offset addr)
+ localparam XR_DIRECT_CONTROL_RECONF_READ = 32'b0001; // reconfig space: read from OFFSET_ADDR, save result in DATA
+ localparam XR_DIRECT_CONTROL_LADDR_SET = 32'b0010; // interpret OFFSET_ADDR as logical addr, with automatic ch addr offset
+ localparam XR_DIRECT_CONTROL_PADDR_SET = 32'b0011; // interpret OFFSET_ADDR as physical addr, with no automatic addr offset
+ localparam XR_DIRECT_CONTROL_PHYS_LOCK_CLEAR = 32'b0100; // clear lock request for current channel
+ localparam XR_DIRECT_CONTROL_PHYS_LOCK_SET = 32'b0101; // set lock request for current channel
+ localparam XR_DIRECT_CONTROL_ADDR_AUTO_INCR_CLEAR = 32'b0110; // clear auto-write-and-address-increment mode for data writes
+ localparam XR_DIRECT_CONTROL_ADDR_AUTO_INCR_SET = 32'b0111; // set auto-write-and-address-increment mode for data writes
+ localparam XR_DIRECT_CONTROL_INTERNAL_WRITE = 32'b1000; // Internal registers, mainly testbus control
+ //localparam XR_DIRECT_CONTROL_INTERNAL_READ = 32'b1001; // internal reg space: read from OFFSET_ADDR, save result in DATA
+ localparam XR_DIRECT_CONTROL_TABLE_READ = 32'b1011; // ROM table lookup, especially for PLL and clock mux remapping
+
+ // Read of control/status reg returns this bitfield data
+ localparam XR_DIRECT_STATUS_BITMASK_PHYS_LOCK_GRANTED = 32'b0001; // on read, bit 0 is grant status
+ localparam XR_DIRECT_STATUS_BITMASK_PHYS_LOCK_REQUESTED = 32'b0010; // on read, bit 1 is physical lock request flag
+ localparam XR_DIRECT_STATUS_BITMASK_USING_PHYS_ADDR = 32'b0100; // on read, bit 2 is physical addr mode indicator (0 mean logical addr)
+ localparam XR_DIRECT_STATUS_BITMASK_USING_ADDR_AUTO_INCR = 32'b1000; // on read, bit 3 is auto-write-and-addr-incr mode indicator
+
+ // Internal register addresses, for read/write via these opcodes: XR_DIRECT_CONTROL_INTERNAL_*
+ localparam XR_DIRECT_OFFSET_TESTBUS_SEL = 2'd0; // internal register for testbus sel
+
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_offset_cancellation.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_offset_cancellation.sv
new file mode 100644
index 0000000000000000000000000000000000000000..0dd5517bb661acbd542861fa584fe89ae3aa336c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_offset_cancellation.sv
@@ -0,0 +1,174 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_offset_cancellation
+#(
+ parameter device_family = "StratixV",
+ parameter number_of_reconfig_interfaces = 1
+)
+(
+ input wire reconfig_clk, // this will be the reconfig clk
+ input wire reset,
+
+ //avalon MM slave
+ input wire [2:0] offset_cancellation_address, // MM address
+ input wire [31:0] offset_cancellation_writedata,
+ input wire offset_cancellation_write,
+ input wire offset_cancellation_read,
+
+ //output MM slave
+ output wire [31:0] offset_cancellation_readdata, // from MM
+
+ output wire offset_cancellation_done,
+
+ // input from base_reconfig
+ input wire offset_cancellation_irq_from_base,
+ input wire offset_cancellation_waitrequest_from_base,
+ output wire offset_cancellation_waitrequest,
+
+ // output to base_reconfig
+ // Avalon MM Master
+ output wire [2:0] offset_cancellation_address_base, // 3 bit MM
+ output wire [31:0] offset_cancellation_writedata_base,
+ output wire offset_cancellation_write_base, // start write to GXB
+ output wire offset_cancellation_read_base, // start read from GXB
+
+ // input from base reconfig
+ input wire [31:0] offset_cancellation_readdata_base, // data from read command
+
+ // Avalon ST
+ input wire [number_of_reconfig_interfaces*16 - 1 : 0] testbus_data,
+
+ // external connect to switch fabric: request basic access from arbiter
+ output wire arb_req,
+ input wire arb_grant
+
+);
+
+import altera_xcvr_functions::*;
+localparam is_s4 = has_s4_style_hssi(device_family);
+localparam is_s5 = has_s5_style_hssi(device_family);
+localparam is_a5 = has_a5_style_hssi(device_family);
+
+
+generate
+ //Deepak - Namespace support for AII GX and CIVGX
+ if(is_s4)
+ begin
+ wire [4:0] w_tgx_offset_cancellation_address_base;
+ alt_xcvr_reconfig_offset_cancellation_tgx
+ #(
+ .device_family(device_family),
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces)
+ ) offset_cancellation_tgx
+ (
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .offset_cancellation_address(offset_cancellation_address),
+ .offset_cancellation_writedata(offset_cancellation_writedata),
+ .offset_cancellation_write(offset_cancellation_write),
+ .offset_cancellation_read(offset_cancellation_read),
+ .offset_cancellation_readdata(offset_cancellation_readdata),
+ .offset_cancellation_done(offset_cancellation_done),
+ .offset_cancellation_irq_from_base(offset_cancellation_irq_from_base),
+ .offset_cancellation_waitrequest_from_base(offset_cancellation_waitrequest_from_base),
+ .offset_cancellation_waitrequest(offset_cancellation_waitrequest),
+ .offset_cancellation_address_base(w_tgx_offset_cancellation_address_base),
+ .offset_cancellation_writedata_base(offset_cancellation_writedata_base),
+ .offset_cancellation_write_base(offset_cancellation_write_base),
+ .offset_cancellation_read_base(offset_cancellation_read_base),
+ .offset_cancellation_readdata_base(offset_cancellation_readdata_base),
+ .testbus_data(testbus_data)
+ );
+ assign offset_cancellation_address_base = w_tgx_offset_cancellation_address_base[4:2];
+ assign arb_req = 1'b0 & arb_grant; // not currently used in S4 architecture
+ end
+ else if (is_s5)
+ begin
+ alt_xcvr_reconfig_offset_cancellation_sv
+ #(
+ .device_family(device_family),
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces)
+ ) offset_cancellation_sv
+ (
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .offset_cancellation_address(offset_cancellation_address),
+ .offset_cancellation_writedata(offset_cancellation_writedata),
+ .offset_cancellation_write(offset_cancellation_write),
+ .offset_cancellation_read(offset_cancellation_read),
+ .offset_cancellation_readdata(offset_cancellation_readdata),
+ .offset_cancellation_done(offset_cancellation_done),
+ .offset_cancellation_irq_from_base(offset_cancellation_irq_from_base),
+ .offset_cancellation_waitrequest_from_base(offset_cancellation_waitrequest_from_base),
+ .offset_cancellation_waitrequest(offset_cancellation_waitrequest),
+ .offset_cancellation_address_base(offset_cancellation_address_base),
+ .offset_cancellation_writedata_base(offset_cancellation_writedata_base),
+ .offset_cancellation_write_base(offset_cancellation_write_base),
+ .offset_cancellation_read_base(offset_cancellation_read_base),
+ .offset_cancellation_readdata_base(offset_cancellation_readdata_base),
+ .testbus_data(testbus_data[7:0]), // testbus data is now provided on a per-channel basis from the 'B' - only need the lower 8 bits
+ .arb_req(arb_req),
+ .arb_grant(arb_grant)
+ );
+ end
+ else if (is_a5)
+ begin
+ alt_xcvr_reconfig_offset_cancellation_av
+ #(
+ .device_family(device_family),
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces)
+ ) offset_cancellation_av
+ (
+ .reconfig_clk(reconfig_clk),
+ .reset(reset),
+ .offset_cancellation_address(offset_cancellation_address),
+ .offset_cancellation_writedata(offset_cancellation_writedata),
+ .offset_cancellation_write(offset_cancellation_write),
+ .offset_cancellation_read(offset_cancellation_read),
+ .offset_cancellation_readdata(offset_cancellation_readdata),
+ .offset_cancellation_done(offset_cancellation_done),
+ .offset_cancellation_irq_from_base(offset_cancellation_irq_from_base),
+ .offset_cancellation_waitrequest_from_base(offset_cancellation_waitrequest_from_base),
+ .offset_cancellation_waitrequest(offset_cancellation_waitrequest),
+ .offset_cancellation_address_base(offset_cancellation_address_base),
+ .offset_cancellation_writedata_base(offset_cancellation_writedata_base),
+ .offset_cancellation_write_base(offset_cancellation_write_base),
+ .offset_cancellation_read_base(offset_cancellation_read_base),
+ .offset_cancellation_readdata_base(offset_cancellation_readdata_base),
+ .testbus_data(testbus_data[7:0]), // testbus data is now provided on a per-channel basis from the 'B' - only need the lower 8 bits
+ .arb_req(arb_req),
+ .arb_grant(arb_grant)
+ );
+ end
+ else
+ begin
+ assign offset_cancellation_readdata = 32'd0;
+ assign offset_cancellation_done = 1'd0;
+ assign offset_cancellation_waitrequest = 1'd0;
+ assign offset_cancellation_address_base = 3'd0;
+ assign offset_cancellation_writedata_base = 32'd0;
+ assign offset_cancellation_write_base = 1'd0;
+ assign offset_cancellation_read_base = 1'd0;
+ assign arb_req = 1'd0;
+ end
+
+
+
+endgenerate
+
+endmodule
+
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_offset_cancellation_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_offset_cancellation_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..01ee1edc16393c8b5f525ce12734b754321f57b7
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_offset_cancellation_tgx.v
@@ -0,0 +1,581 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module alt_xcvr_reconfig_offset_cancellation_tgx
+#(
+ parameter device_family = "StratixIV",
+ parameter number_of_reconfig_interfaces = 1
+)
+(
+ input wire reconfig_clk, // this will be the reconfig clk
+ input wire reset,
+
+ //avalon MM slave
+ input wire offset_cancellation_address, // MM address
+ input wire [31:0] offset_cancellation_writedata,
+ input wire offset_cancellation_write,
+ input wire offset_cancellation_read,
+
+ //output MM slave
+ output reg [31:0] offset_cancellation_readdata, // from MM
+
+ output reg offset_cancellation_done,
+
+ // input from base_reconfig
+ input wire offset_cancellation_irq_from_base,
+ input wire offset_cancellation_waitrequest_from_base,
+
+ output wire offset_cancellation_waitrequest,
+
+ // output to base_reconfig
+ // Avalon MM Master
+ output wire [4:0] offset_cancellation_address_base, // 3 bit MM
+ output wire [31:0] offset_cancellation_writedata_base,
+ output wire offset_cancellation_write_base, // start write to GXB
+ output wire offset_cancellation_read_base, // start read from GXB
+
+ // input from base reconfig
+ input wire [31:0] offset_cancellation_readdata_base, // data from read command
+
+ // Avalon ST
+ input wire [number_of_reconfig_interfaces*16 - 1 : 0] testbus_data
+);
+
+///////////////////////////////////////////////////////////////////
+// Memory map | wr/rd | Description
+//----------------------------------------------------------------
+// 0 | wr/rd | [31:10] Reserved
+// | | [9] Error
+// | | [8] Busy
+// | | [7:1] Reserved
+// | | [0] Start (hidden for QII 9.1)
+///////////////////////////////////////////////////////////////////
+
+//local parameters
+//state
+localparam IDLE_STATE = 4'b0000;
+localparam LOGICAL_ADDRESS_STATE = 4'b0001;
+localparam WRITE_DATA_STATE = 4'b0010;
+localparam CONTROL_STATE = 4'b0011;
+localparam BUSY_STATE = 4'b0100;
+localparam READ_PHY_ADDR_STATE = 4'b0101;
+localparam CHECK_PHY_ADDR_STATE = 4'b0110;
+localparam ADDRESS_OFFSET_STATE = 4'b0111;
+localparam BASE_BUSY_STATE = 4'b1000;
+localparam READ_DATA_STATE = 4'b1001;
+localparam WRITE_DONE_STATE = 4'b1010;
+
+localparam ILLEGAL_PHYSICAL_CHNL = 10'b1111111111;
+
+wire mutex_grant;
+wire [31:0] master_read_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [3:0] state;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg write_read_control;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_write;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg master_read;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [31:0] master_write_data;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [2:0] master_address;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg req_and_use_mutex;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg set_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_cal_error_reg;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg wait_phy_addr_ready;
+
+wire [4:0] master_address_shifted;
+
+//alt_cal instantiation
+wire alt_cal_busy;
+wire [15:0] alt_cal_dprio_dataout;
+wire alt_cal_dprio_wren;
+wire alt_cal_dprio_rden;
+wire alt_cal_retain_addr;
+wire [(number_of_reconfig_interfaces*4-1) : 0] alt_cal_error;
+
+wire [number_of_reconfig_interfaces*16 - 1 : 0] alt_cal_testbuses;
+wire [15:0] alt_cal_dprio_addr;
+wire [8:0] alt_cal_quad_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [11:0] alt_cal_remap_addr;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_cal_dprio_busy;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg alt_cal_dprio_busy_int;
+(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+reg [15:0] alt_cal_dprio_datain;
+
+function integer CLogB2;
+input integer Depth;
+integer i;
+begin
+i = Depth;
+for(CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1)
+i = i >> 1;
+end
+endfunction
+
+// Implement waitrequest to match previous implementation
+altera_wait_generate wait_gen(
+ .rst(reset),
+ .clk(reconfig_clk),
+ .launch_signal(offset_cancellation_read),
+ .wait_req(offset_cancellation_waitrequest)
+);
+
+// synopsys translate_off
+initial begin
+ state = 3'b000;
+ alt_cal_remap_addr = 12'h000;
+ req_and_use_mutex = 1'b0;
+ wait_phy_addr_ready = 1'b0;
+ // alt_cal_testbuses = 0;
+ alt_cal_dprio_datain = 16'h0000;
+ alt_cal_dprio_busy = 1'b0;
+ alt_cal_dprio_busy_int = 1'b0;
+
+ master_write = 1'b0;
+ master_read = 1'b0;
+ master_write_data = {32{1'b0}};
+ master_address = 3'h0;
+
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy = 1'b0; // 1 for assert busy, 0 for deassert busy
+
+ alt_cal_error_reg = 1'b0;
+ offset_cancellation_done = 1'b0;
+
+end
+// synopsys translate_on
+
+integer count;
+
+always @(posedge reconfig_clk or posedge reset)
+begin
+ if (reset)
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ master_write_data <= {32{1'b0}};
+ master_address <= 3'h0;
+ write_read_control = 1'b0; // 1 for write, 0 for read
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ offset_cancellation_readdata[31:0] <= {32{1'b0}};
+ alt_cal_error_reg <= 1'b0;
+ req_and_use_mutex <= 1'b0;
+ wait_phy_addr_ready <= 1'b0;
+ alt_cal_dprio_busy_int<= 1'b0;
+ offset_cancellation_done <= 1'b0;
+ end
+ else begin
+ if(offset_cancellation_read == 1'b1)
+ begin
+ if(offset_cancellation_address == 1'b0)
+ begin
+ offset_cancellation_readdata <= {{22{1'b0}}, alt_cal_error_reg, alt_cal_busy , {8{1'b0}}};
+ end
+ end
+
+ for(count=0; count < (number_of_reconfig_interfaces*4); count=count+1)
+ begin
+ alt_cal_error_reg = alt_cal_error[count] | alt_cal_error_reg;
+ end
+
+ if(alt_cal_busy == 1'b0)
+ req_and_use_mutex <= 1'b0;
+ else
+ req_and_use_mutex <= 1'b1;
+
+ case (state)
+ IDLE_STATE:
+ begin
+ offset_cancellation_done <= 1'b0; // reset write/read done flag
+ //reset the signal
+ set_busy <= 1'b0;
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ alt_cal_remap_addr <= 12'h000;
+
+ //al_cal will not assert wren and rden at the same time
+ if((alt_cal_dprio_wren == 1'b1) || (alt_cal_dprio_rden == 1'b1))
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(alt_cal_dprio_wren == 1'b1)
+ write_read_control <= 1'b1; // 1 for write
+ else
+ write_read_control <= 1'b0; // 0 for read
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ else
+ state <= IDLE_STATE;
+ end
+ else if(alt_cal_retain_addr == 1'b1)
+ begin
+ if(mutex_grant == 1'b1)
+ state <= WRITE_DATA_STATE;
+ else
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ state <= IDLE_STATE;
+ end
+ end
+ LOGICAL_ADDRESS_STATE: //sending channel and quad address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h1;
+ master_write_data <= {{21{1'b0}}, alt_cal_quad_addr, alt_cal_dprio_addr[13:12]};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= READ_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ state <= LOGICAL_ADDRESS_STATE;
+ end
+ end
+ READ_PHY_ADDR_STATE: //read phsical address
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h2;
+ master_read <= 1'b1;
+ master_write <= 1'b0;
+ if (wait_phy_addr_ready == 1'b1)
+ begin
+ wait_phy_addr_ready <= 1'b0;
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ else
+ begin
+ wait_phy_addr_ready <= 1'b1;
+ state <= READ_PHY_ADDR_STATE;
+ //state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_PHY_ADDR_STATE;
+ end
+ end
+ CHECK_PHY_ADDR_STATE: //check physical address correct or not
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ if (master_read_data[9:0] == ILLEGAL_PHYSICAL_CHNL)
+ begin
+ // synopsys translate_off
+ $display ("Illegal physical address: 10'h%h", master_read_data);
+ $display ("Time: %0t Instance: %m", $time);
+ // synopsys translate_on
+ alt_cal_remap_addr <= 12'hfff;
+ state <= IDLE_STATE;
+ end
+ else
+ begin
+ alt_cal_remap_addr <= master_read_data[11:0];
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ else
+ begin
+ state <= CHECK_PHY_ADDR_STATE;
+ end
+ end
+ ADDRESS_OFFSET_STATE: // send address offset to alt_dprio
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h4;
+ master_write_data <= {{17{1'b0}}, alt_cal_dprio_addr[14:0]};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(write_read_control == 1'b1)
+ state <= WRITE_DATA_STATE;
+ else
+ state <= CONTROL_STATE;
+ end
+ else
+ begin
+ state <= ADDRESS_OFFSET_STATE;
+ end
+ end
+ WRITE_DATA_STATE:
+ begin
+ master_address <= 3'h5;
+ master_write_data = {{16{1'b0}}, alt_cal_dprio_dataout};
+ master_write <= 1'b1; // send address to alt_dprio
+ master_read <= 1'b0;
+ state <= CONTROL_STATE;
+ end
+ CONTROL_STATE: // sending write/read command
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h3; // get ready to send control command to alt_dprio
+// master_write_data <= {{29{1'b0}}, (~write_read_control), write_read_control};
+ master_write_data <= {{27{1'b0}}, 1'b1, 1'b0, (~write_read_control), write_read_control}; // use absolute addressing
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ state <= BASE_BUSY_STATE;
+ end
+ else
+ begin
+ state <= CONTROL_STATE;
+ end
+ end
+ BASE_BUSY_STATE: // send busy to reconfig_togxb
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ master_address <= 3'h7; // set offset cancellation busy to reconfig_togxb
+ master_write_data <= {{30{1'b0}}, alt_cal_busy};
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ if(set_busy == 1'b0)
+ begin
+ set_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ else
+ begin
+ set_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= BASE_BUSY_STATE;
+ end
+ end
+ BUSY_STATE: // wait for write done
+ begin
+ if(offset_cancellation_irq_from_base == 1'b1)
+ begin
+ alt_cal_dprio_busy <= 1'b1;
+ if(write_read_control == 1'b0) //read
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+
+ master_write <= 1'b0;
+ master_read <= 1'b0;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_cal_dprio_busy <= 1'b1;
+ state <= BUSY_STATE;
+ end
+ end
+ WRITE_DONE_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(offset_cancellation_irq_from_base == 1'b1)
+ begin
+ if(alt_cal_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_cal_dprio_busy_int <= master_read_data[8];
+ alt_cal_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ else
+ begin
+ master_write <= 1'b1;
+ master_read <= 1'b0;
+ master_address <= 3'h3;
+ master_write_data <= {{16{1'b0}}, {16'h0000}}; //acknowledge write operation
+ alt_cal_dprio_busy <= 1'b1;
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ alt_cal_dprio_busy <= 1'b0;
+ offset_cancellation_done <= 1'b1; // write done
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= WRITE_DONE_STATE;
+ end
+ end
+ READ_DATA_STATE:
+ begin
+ if(mutex_grant == 1'b1)
+ begin
+ if(offset_cancellation_irq_from_base == 1'b1)
+ begin
+ if(alt_cal_dprio_busy_int == 1'b1) // wait for dprio_busy to go low
+ begin
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ master_address <= 3'h3;
+ alt_cal_dprio_busy_int <= master_read_data[8];
+ alt_cal_dprio_busy <= 1'b1;
+ end
+ else
+ begin
+ master_address <= 3'h5;
+ master_write <= 1'b0;
+ master_read <= 1'b1;
+ alt_cal_dprio_busy <= 1'b1;
+ end
+ state <= READ_DATA_STATE;
+ end
+ else
+ begin
+ master_read <= 1'b0;
+ master_write <= 1'b0;
+ offset_cancellation_done <= 1'b1; // read done
+ alt_cal_dprio_datain <= master_read_data[15:0];
+ alt_cal_dprio_busy <= 1'b0;
+ state <= IDLE_STATE;
+ end
+ end
+ else
+ begin
+ state <= READ_DATA_STATE;
+ end
+ end
+ default:
+ begin
+ state <= IDLE_STATE;
+ end
+ endcase
+ end
+end
+
+
+
+generate
+
+//Deepak Use alt_cal_mm for SIV and AIIGX
+if((device_family=="Stratix IV") || (device_family=="Arria II GX") || (device_family=="Arria II GZ") || (device_family=="HardCopy IV"))
+begin
+ alt_cal_mm #(
+ .number_of_channels (number_of_reconfig_interfaces*4),
+ .channel_address_width (CLogB2(number_of_reconfig_interfaces*4))
+ )alt_cal_inst
+ (
+ .clock(reconfig_clk),
+ .reset(reset),
+ .start(),
+ .busy(alt_cal_busy),
+ .dprio_addr(alt_cal_dprio_addr), // only extract the logical channel address
+ .quad_addr(alt_cal_quad_addr),
+ .dprio_dataout(alt_cal_dprio_dataout),
+ .dprio_datain(alt_cal_dprio_datain),
+ .dprio_wren(alt_cal_dprio_wren),
+ .dprio_rden(alt_cal_dprio_rden),
+ .dprio_busy(alt_cal_dprio_busy),
+ .retain_addr(alt_cal_retain_addr),
+ .remap_addr(alt_cal_remap_addr),
+ .testbuses(alt_cal_testbuses),
+ .cal_error(alt_cal_error)
+ );
+end
+//Deepak: Use alt_cal_c3gxb for Cyclone IV GX
+if(device_family=="Cyclone IV GX")
+begin
+ alt_cal_c3gxb alt_cal_inst
+ (
+ .clock(reconfig_clk),
+ .reset(reset),
+ .start(),
+ .busy(alt_cal_busy),
+ .dprio_addr(alt_cal_dprio_addr), // only extract the logical channel address
+ .quad_addr(alt_cal_quad_addr),
+ .dprio_dataout(alt_cal_dprio_dataout),
+ .dprio_datain(alt_cal_dprio_datain),
+ .dprio_wren(alt_cal_dprio_wren),
+ .dprio_rden(alt_cal_dprio_rden),
+ .dprio_busy(alt_cal_dprio_busy),
+ .retain_addr(alt_cal_retain_addr),
+ .remap_addr(alt_cal_remap_addr),
+ .testbuses(alt_cal_testbuses),
+ .cal_error(alt_cal_error)
+ );
+defparam
+ alt_cal_inst.number_of_channels = number_of_reconfig_interfaces*4,
+ alt_cal_inst.channel_address_width = CLogB2(number_of_reconfig_interfaces*4);
+end
+endgenerate
+
+alt_mutex_acq #(
+ .mutex_wait_time(102), ///Thia: pick a different mutex wait time to avoid collision. Say 102. (since analog is already using 101)
+ .addr_width(5),
+ .data_width(32)
+)
+mutex_inst (
+ .clk(reconfig_clk),
+ .reset(reset),
+// inputs to the base that should be routed through the mutex
+ .address(master_address_shifted),
+ .writedata(master_write_data),
+ .write(master_write),
+ .read(master_read),
+// output from the mutex which is processed form of output from base
+ .waitrequest(),
+ .readdata(master_read_data),
+
+// outputs from mutex to be routed to the base
+ .master_address(offset_cancellation_address_base),
+ .master_writedata(offset_cancellation_writedata_base),
+ .master_write(offset_cancellation_write_base),
+ .master_read(offset_cancellation_read_base),
+
+// these ports are from the base routed to the mutex
+ .master_waitrequest(offset_cancellation_waitrequest_from_base),
+ .master_readdata(offset_cancellation_readdata_base), // from MM
+
+//request signal to the mutex should be kept high as long as the mutex is being used
+ .mutex_req(req_and_use_mutex),
+// output from mutex indicates whether you have mutex or not
+ .mutex_grant(mutex_grant)
+);
+
+//wire assignment
+assign alt_cal_testbuses = testbus_data;
+assign master_address_shifted = {master_address, {2'b00}};
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_siv.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_siv.sv
new file mode 100644
index 0000000000000000000000000000000000000000..727be748a008f29b2f9649fef902f9787b9b1f47
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_reconfig_siv.sv
@@ -0,0 +1,441 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Transceiver Reconfiguration Module for Stratix IV architectures
+//
+// Includes many function-specific sub-modules, such as:
+// - analog reconfig (alt_xcvr_reconfig_analog)
+// - offset cancellation (alt_xcvr_reconfig_offset_cancellation)
+// - ...
+
+// $Header$
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_reconfig_siv #(
+ parameter number_of_reconfig_interfaces = 1
+) (
+ input wire mgmt_clk_clk, // mgmt_clk.clk
+ input wire mgmt_rst_reset, // mgmt_rst.reset
+
+ // user reconfiguration management interface
+ input wire [6:0] reconfig_mgmt_address, // reconfig_mgmt.address
+ output reg reconfig_mgmt_waitrequest = 0, // .waitrequest
+ input wire reconfig_mgmt_read, // .read
+ output reg [31:0] reconfig_mgmt_readdata = ~0, // .readdata
+ input wire reconfig_mgmt_write, // .write
+ input wire [31:0] reconfig_mgmt_writedata, // .writedata
+ output wire reconfig_done, // reconfig_done.export
+
+ output wire [3:0] reconfig_togxb, // reconfig_togxb_data.data
+ input wire [number_of_reconfig_interfaces*17 - 1 : 0] reconfig_fromgxb // dprioout, testbus from altgx : (17+4 bits/quad)
+);
+
+ // master interface to basic reconfiguration block that interfaces to the transceiver channel
+ wire [2:0] basic_address; // basic.address // master interface must include 2 lower addr bits
+ wire basic_waitrequest; // .waitrequest
+ wire basic_irq; // .irq
+ wire basic_read; // .read
+ wire [31:0] basic_readdata; // .readdata
+ wire basic_write; // .write
+ wire [31:0] basic_writedata; // .writedata
+
+ // native testbus input
+ wire [15:0] testbus_data;
+
+ localparam l_dev_family = "Stratix IV";
+ localparam width_awa = 3; // word address width of interface to analog reconfig block
+ localparam width_bwa = 3; // word address width of interface to basic reconfig block
+ localparam arb_count = 4; // count of the total number of sub-components that can act
+ // as slaves to the mgmt interface, and masters to the 'basic' block
+ localparam arb_offset = 0;
+ localparam arb_analog = 1;
+ localparam arb_eyemon = 2;
+ localparam arb_dfe = 3;
+
+ // Analog controls output ports, mgmt facing
+ wire [31:0] sc_analog_readdata;
+ wire sc_analog_waitrequest;
+
+ // Offset cancellation output ports, mgmt facing
+ wire [31:0] sc_offset_readdata;
+ wire sc_offset_waitrequest;
+
+ // Eyemon output ports, mgmt facing
+ wire [31:0] sc_eyemon_readdata;
+ wire sc_eyemon_waitrequest;
+
+ // DFE output ports, mgmt facing
+ wire [31:0] sc_dfe_readdata;
+ wire sc_dfe_waitrequest;
+
+ ///////////////////////////////////////////////////////////////////////
+ // Decoder for multiple slaves of reconfig_mgmt interface
+ ///////////////////////////////////////////////////////////////////////
+ wire [arb_count-1:0] r_decode;
+ assign r_decode =
+ (reconfig_mgmt_address[6:width_awa] == arb_offset) ? (({arb_count-arb_offset{1'b0}} | 1'b1) << arb_offset)
+ : (reconfig_mgmt_address[6:width_awa] == arb_analog) ? (({arb_count-arb_analog{1'b0}} | 1'b1) << arb_analog)
+ : (reconfig_mgmt_address[6:width_awa] == arb_eyemon) ? (({arb_count-arb_eyemon{1'b0}} | 1'b1) << arb_eyemon)
+ : (reconfig_mgmt_address[6:width_awa] == arb_dfe) ? (({arb_count-arb_dfe{1'b0}} | 1'b1) << arb_dfe)
+ : {arb_count{1'b0}};
+
+ // reconfig_mgmt output generation is muxing of decoded slave output
+ always @(*) begin
+ case (reconfig_mgmt_address[6:width_awa])
+ arb_offset: begin
+ reconfig_mgmt_readdata = sc_offset_readdata;
+ reconfig_mgmt_waitrequest = sc_offset_waitrequest;
+ end
+ arb_analog: begin
+ reconfig_mgmt_readdata = sc_analog_readdata;
+ reconfig_mgmt_waitrequest = sc_analog_waitrequest;
+ end
+ arb_eyemon: begin
+ reconfig_mgmt_readdata = sc_eyemon_readdata;
+ reconfig_mgmt_waitrequest = sc_eyemon_waitrequest;
+ end
+ arb_dfe: begin
+ reconfig_mgmt_readdata = sc_dfe_readdata;
+ reconfig_mgmt_waitrequest = sc_dfe_waitrequest;
+ end
+ default: begin
+ reconfig_mgmt_readdata = -1;
+ reconfig_mgmt_waitrequest = 1'b0;
+ end
+ endcase
+ end
+
+ ///////////////////////////////////////////////////////////////////////
+ // Arbiter for multiple masters accessing 'basic' reconfig slave port
+ ///////////////////////////////////////////////////////////////////////
+ wire [arb_count-1:0] req; // req[0] is highest priority when current grantee is done
+ wire [arb_count-1:0] grant;
+
+ alt_xcvr_arbiter #(
+ .width(arb_count) // count total number of sub-components that act as masters to 'basic'
+ ) arbiter (
+ .clock(mgmt_clk_clk),
+ .req(req),
+ .grant(grant)
+ );
+
+ ////////////////////////////////////
+ // Sub-component: analog controls
+ // word address offset: +0
+ ////////////////////////////////////
+
+ // Analog controls output ports, mgmt facing
+ wire analog_reconfig_done;
+ // Analog controls output ports, basic slave facing
+ wire [width_bwa+1:0] scs_analog_address;
+ wire [31:0] scs_analog_writedata;
+ wire scs_analog_write;
+ wire scs_analog_read;
+
+ // Analog controls master-to-slave access fabric outputs
+ tri0 m2s_analog_read;
+ tri0 m2s_analog_write;
+ tri0 [width_bwa-1:0] m2s_analog_address;
+ tri0 [31:0] m2s_analog_writedata;
+ wire [31:0] m2s_analog_readdata;
+ wire m2s_analog_waitrequest;
+
+ alt_xcvr_reconfig_analog_tgx sc_analog (
+ .reconfig_clk(mgmt_clk_clk),
+ .reset(mgmt_rst_reset),
+ // external mgmt interface facing
+ .analog_reconfig_address(reconfig_mgmt_address[width_awa-1:0]),
+ .analog_reconfig_writedata(reconfig_mgmt_writedata),
+ .analog_reconfig_write(reconfig_mgmt_write & r_decode[arb_analog]),
+ .analog_reconfig_read(reconfig_mgmt_read & r_decode[arb_analog]),
+ .analog_reconfig_readdata(sc_analog_readdata),
+ .analog_reconfig_waitrequest(sc_analog_waitrequest),
+ .analog_reconfig_done(analog_reconfig_done),
+ // master-to-slave fabric facing, to basic reconfig
+ .analog_reconfig_irq_from_base(basic_irq),
+ .analog_reconfig_waitrequest_from_base(m2s_analog_waitrequest),
+ .analog_reconfig_readdata_base(m2s_analog_readdata),
+ .analog_reconfig_address_base(scs_analog_address),
+ .analog_reconfig_writedata_base(scs_analog_writedata),
+ .analog_reconfig_write_base(scs_analog_write),
+ .analog_reconfig_read_base(scs_analog_read)
+ );
+
+ // master-to-slave access module
+ alt_xcvr_m2s #(
+ .width_addr(width_bwa),
+ .width_data(32)
+ ) m2s_analog (
+ .clock(mgmt_clk_clk),
+ .req(req[arb_analog]),
+ .grant(grant[arb_analog]),
+ // master ports, facing basic reconfig block
+ .m_read(scs_analog_read),
+ .m_write(scs_analog_write),
+ .m_address(scs_analog_address[2 +: width_bwa]), // drop 2 lower addr bits
+ .m_writedata(scs_analog_writedata),
+ .m_readdata(m2s_analog_readdata),
+ .m_waitrequest(m2s_analog_waitrequest),
+ // slave-side ports, from basic reconfig block
+ .s_readdata(basic_readdata),
+ .s_waitrequest(basic_waitrequest),
+ .s_read(m2s_analog_read),
+ .s_write(m2s_analog_write),
+ .s_address(m2s_analog_address),
+ .s_writedata(m2s_analog_writedata)
+ );
+
+ ///////////////////////////////////////////
+ // Sub-component: offset cancellation
+ // word address offset: +8 (0x20 in bytes)
+ ///////////////////////////////////////////
+
+ // Offset cancellation output ports:
+ wire offset_cancellation_done;
+ wire [width_bwa-1:0] scs_offset_address;
+ wire [31:0] scs_offset_writedata;
+ wire scs_offset_write;
+ wire scs_offset_read;
+
+ // Offset cancellation master-to-slave access fabric outputs
+ tri0 m2s_offset_read;
+ tri0 m2s_offset_write;
+ tri0 [width_bwa-1:0] m2s_offset_address;
+ tri0 [31:0] m2s_offset_writedata;
+ wire [31:0] m2s_offset_readdata;
+ wire m2s_offset_waitrequest;
+
+ alt_xcvr_reconfig_offset_cancellation #(
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces),
+ .device_family(l_dev_family)
+ ) sc_offset (
+ .reconfig_clk(mgmt_clk_clk),
+ .reset(mgmt_rst_reset),
+ // external mgmt interface facing
+ .offset_cancellation_address(reconfig_mgmt_address[0]), // slave uses a single address bit
+ .offset_cancellation_writedata(reconfig_mgmt_writedata),
+ .offset_cancellation_write(reconfig_mgmt_write & r_decode[arb_offset]),
+ .offset_cancellation_read(reconfig_mgmt_read & r_decode[arb_offset]),
+ .offset_cancellation_readdata(sc_offset_readdata),
+ .offset_cancellation_waitrequest(sc_offset_waitrequest),
+ // master-to-slave fabric facing, to basic reconfig
+ .offset_cancellation_irq_from_base(basic_irq),
+ .offset_cancellation_waitrequest_from_base(m2s_offset_waitrequest),
+ .offset_cancellation_readdata_base(m2s_offset_readdata),
+ .testbus_data(testbus_data),
+ .offset_cancellation_done(offset_cancellation_done),
+ .offset_cancellation_address_base(scs_offset_address),
+ .offset_cancellation_writedata_base(scs_offset_writedata),
+ .offset_cancellation_write_base(scs_offset_write),
+ .offset_cancellation_read_base(scs_offset_read)
+ );
+
+ // master-to-slave access module
+ alt_xcvr_m2s #(
+ .width_addr(width_bwa),
+ .width_data(32)
+ ) m2s_offset (
+ .clock(mgmt_clk_clk),
+ .req(req[arb_offset]),
+ .grant(grant[arb_offset]),
+ // master ports, facing basic reconfig block
+ .m_read(scs_offset_read),
+ .m_write(scs_offset_write),
+ .m_address(scs_offset_address), // drop 2 lower addr bits
+ .m_writedata(scs_offset_writedata),
+ .m_readdata(m2s_offset_readdata),
+ .m_waitrequest(m2s_offset_waitrequest),
+ // slave-side ports, from basic reconfig block
+ .s_readdata(basic_readdata),
+ .s_waitrequest(basic_waitrequest),
+ .s_read(m2s_offset_read),
+ .s_write(m2s_offset_write),
+ .s_address(m2s_offset_address),
+ .s_writedata(m2s_offset_writedata)
+ );
+
+ ///////////////////////////////////////////
+ // Sub-component: "EyeQ" eye monitor
+ // word address offset: +16 (0x40 in bytes)
+ ///////////////////////////////////////////
+
+ // Eyemon output ports:
+ wire eyemon_done;
+ wire [width_bwa+1:0] scs_eyemon_address;
+ wire [31:0] scs_eyemon_writedata;
+ wire scs_eyemon_write;
+ wire scs_eyemon_read;
+
+ // eyemon master-to-slave access fabric outputs
+ tri0 m2s_eyemon_read;
+ tri0 m2s_eyemon_write;
+ tri0 [width_bwa-1:0] m2s_eyemon_address;
+ tri0 [31:0] m2s_eyemon_writedata;
+ wire [31:0] m2s_eyemon_readdata;
+ wire m2s_eyemon_waitrequest;
+
+ alt_xcvr_reconfig_eyemon_tgx #(
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces),
+ .device_family(l_dev_family)
+ ) sc_eyemon (
+ .reconfig_clk(mgmt_clk_clk),
+ .reset(mgmt_rst_reset),
+ // external mgmt interface facing
+ .eyemon_address(reconfig_mgmt_address[width_awa-1:0]), // slave uses a 3-bit address
+ .eyemon_writedata(reconfig_mgmt_writedata),
+ .eyemon_write(reconfig_mgmt_write & r_decode[arb_eyemon]),
+ .eyemon_read(reconfig_mgmt_read & r_decode[arb_eyemon]),
+ .eyemon_readdata(sc_eyemon_readdata),
+ .eyemon_waitrequest(sc_eyemon_waitrequest),
+ // master-to-slave fabric facing, to basic reconfig
+ .eyemon_irq_from_base(basic_irq),
+ .eyemon_waitrequest_from_base(m2s_eyemon_waitrequest),
+ .eyemon_readdata_base(m2s_eyemon_readdata),
+ .eyemon_irq(eyemon_done),
+ .eyemon_address_base(scs_eyemon_address),
+ .eyemon_writedata_base(scs_eyemon_writedata),
+ .eyemon_write_base(scs_eyemon_write),
+ .eyemon_read_base(scs_eyemon_read)
+ );
+
+ // master-to-slave access module
+ alt_xcvr_m2s #(
+ .width_addr(width_bwa),
+ .width_data(32)
+ ) m2s_eyemon (
+ .clock(mgmt_clk_clk),
+ .req(req[arb_eyemon]),
+ .grant(grant[arb_eyemon]),
+ // master ports, facing basic reconfig block
+ .m_read(scs_eyemon_read),
+ .m_write(scs_eyemon_write),
+ .m_address(scs_eyemon_address[2 +: width_bwa]), // drop 2 lower addr bits
+ .m_writedata(scs_eyemon_writedata),
+ .m_readdata(m2s_eyemon_readdata),
+ .m_waitrequest(m2s_eyemon_waitrequest),
+ // slave-side ports, from basic reconfig block
+ .s_readdata(basic_readdata),
+ .s_waitrequest(basic_waitrequest),
+ .s_read(m2s_eyemon_read),
+ .s_write(m2s_eyemon_write),
+ .s_address(m2s_eyemon_address),
+ .s_writedata(m2s_eyemon_writedata)
+ );
+
+ ///////////////////////////////////////////
+ // Sub-component: DFE
+ // word address offset: +24 (0x60 in bytes)
+ ///////////////////////////////////////////
+
+ // DFE output ports:
+ wire dfe_done;
+ wire [width_bwa-1:0] scs_dfe_address;
+ wire [31:0] scs_dfe_writedata;
+ wire scs_dfe_write;
+ wire scs_dfe_read;
+
+ // dfe master-to-slave access fabric outputs
+ tri0 m2s_dfe_read;
+ tri0 m2s_dfe_write;
+ tri0 [width_bwa-1:0] m2s_dfe_address;
+ tri0 [31:0] m2s_dfe_writedata;
+ wire [31:0] m2s_dfe_readdata;
+ wire m2s_dfe_waitrequest;
+
+ alt_xcvr_reconfig_dfe_tgx #(
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces),
+ .device_family(l_dev_family)
+ ) sc_dfe (
+ .reconfig_clk(mgmt_clk_clk),
+ .reset(mgmt_rst_reset),
+ // external mgmt interface facing
+ .dfe_address(reconfig_mgmt_address[width_awa-1:0]), // slave uses a 3-bit address
+ .dfe_writedata(reconfig_mgmt_writedata),
+ .dfe_write(reconfig_mgmt_write & r_decode[arb_dfe]),
+ .dfe_read(reconfig_mgmt_read & r_decode[arb_dfe]),
+ .dfe_readdata(sc_dfe_readdata),
+ .dfe_waitrequest(sc_dfe_waitrequest),
+ // master-to-slave fabric facing, to basic reconfig
+ .dfe_irq_from_base(basic_irq),
+ .dfe_waitrequest_from_base(m2s_dfe_waitrequest),
+ .dfe_readdata_base(m2s_dfe_readdata),
+ .dfe_irq(dfe_done),
+ .dfe_address_base(scs_dfe_address),
+ .dfe_writedata_base(scs_dfe_writedata),
+ .dfe_write_base(scs_dfe_write),
+ .dfe_read_base(scs_dfe_read)
+ );
+
+ // master-to-slave access module
+ alt_xcvr_m2s #(
+ .width_addr(width_bwa),
+ .width_data(32)
+ ) m2s_dfe (
+ .clock(mgmt_clk_clk),
+ .req(req[arb_dfe]),
+ .grant(grant[arb_dfe]),
+ // master ports, facing basic reconfig block
+ .m_read(scs_dfe_read),
+ .m_write(scs_dfe_write),
+ .m_address(scs_dfe_address),
+ .m_writedata(scs_dfe_writedata),
+ .m_readdata(m2s_dfe_readdata),
+ .m_waitrequest(m2s_dfe_waitrequest),
+ // slave-side ports, from basic reconfig block
+ .s_readdata(basic_readdata),
+ .s_waitrequest(basic_waitrequest),
+ .s_read(m2s_dfe_read),
+ .s_write(m2s_dfe_write),
+ .s_address(m2s_dfe_address),
+ .s_writedata(m2s_dfe_writedata)
+ );
+
+
+ ///////////////////////////////////////////
+ // Outputs to basic block
+ ///////////////////////////////////////////
+ assign basic_address = m2s_analog_address | m2s_offset_address | m2s_eyemon_address | m2s_dfe_address;
+ assign basic_read = m2s_analog_read | m2s_offset_read | m2s_eyemon_read | m2s_dfe_read;
+ assign basic_write = m2s_analog_write | m2s_offset_write | m2s_eyemon_write | m2s_dfe_write;
+ assign basic_writedata = m2s_analog_writedata | m2s_offset_writedata | m2s_eyemon_writedata | m2s_dfe_writedata;
+
+ wire [number_of_reconfig_interfaces*8 - 1 : 0] aeq_fromgxb_data=0;
+ wire [number_of_reconfig_interfaces*24 - 1 : 0] aeq_togxb_data;
+
+ alt_xcvr_reconfig_basic_tgx #(
+ .number_of_reconfig_interfaces(number_of_reconfig_interfaces)
+ ) sc_basic (
+ .reconfig_clk(mgmt_clk_clk),
+ .reset(mgmt_rst_reset),
+ .basic_reconfig_write(basic_write),
+ .basic_reconfig_read(basic_read),
+ .basic_reconfig_writedata(basic_writedata),
+ .basic_reconfig_address(basic_address),
+ .basic_reconfig_fromgxb_data(reconfig_fromgxb),
+ .aeq_fromgxb_data(aeq_fromgxb_data),
+ .basic_reconfig_readdata(basic_readdata),
+ .basic_reconfig_waitrequest(basic_waitrequest),
+ .basic_reconfig_togxb_data(reconfig_togxb),
+ .aeq_togxb_data(aeq_togxb_data),
+ .testbus_data(testbus_data),
+ .basic_reconfig_irq(basic_irq)
+ );
+
+
+ ///////////////////////////////////////////
+ // Status to external mgmt interface
+ ///////////////////////////////////////////
+ assign reconfig_done = analog_reconfig_done | offset_cancellation_done | eyemon_done | dfe_done;
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_resync.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_resync.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5c723372b22da2640f7283962c5acdd598a91dfa
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/alt_xcvr_resync.sv
@@ -0,0 +1,98 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Module: alt_xcvr_resync
+//
+// Description:
+// A general purpose resynchronization module.
+//
+// Parameters:
+// SYNC_CHAIN_LENGTH
+// - Specifies the length of the synchronizer chain for metastability
+// retiming.
+// WIDTH
+// - Specifies the number of bits you want to synchronize. Controls the width of the
+// d and q ports.
+// SLOW_CLOCK - USE WITH CAUTION.
+// - Leaving this setting at its default will create a standard resynch circuit that
+// merely passes the input data through a chain of flip-flops. This setting assumes
+// that the input data has a pulse width longer than one clock cycle sufficient to
+// satisfy setup and hold requirements on at least one clock edge.
+// - By setting this to 1 (USE CAUTION) you are creating an asynchronous
+// circuit that will capture the input data regardless of the pulse width and
+// its relationship to the clock. However it is more difficult to apply static
+// timing constraints as it ties the data input to the clock input of the flop.
+// This implementation assumes the data rate is slow enough
+// INIT_VALUE
+// - Specifies the initial values of the synchronization registers.
+//
+// Apply embedded false path timing constraint
+(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers *alt_xcvr_resync*sync_r[0]]\"" *)
+
+`timescale 1ps/1ps
+
+module alt_xcvr_resync #(
+ parameter SYNC_CHAIN_LENGTH = 2, // Number of flip-flops for retiming
+ parameter WIDTH = 1, // Number of bits to resync
+ parameter SLOW_CLOCK = 0, // See description above
+ parameter INIT_VALUE = 0
+ ) (
+ input wire clk,
+ input wire reset,
+ input wire [WIDTH-1:0] d,
+ output wire [WIDTH-1:0] q
+ );
+
+localparam INT_LEN = (SYNC_CHAIN_LENGTH > 0) ? SYNC_CHAIN_LENGTH : 1;
+localparam [INT_LEN-1:0] L_INIT_VALUE = (INIT_VALUE == 1) ? {INT_LEN{1'b1}} : {INT_LEN{1'b0}};
+
+genvar ig;
+
+// Generate a synchronizer chain for each bit
+generate begin
+ for(ig=0;ig<WIDTH;ig=ig+1) begin : resync_chains
+ wire d_in; // Input to sychronization chain.
+ reg [INT_LEN-1:0] sync_r = L_INIT_VALUE;
+ wire [INT_LEN :0] next_r; // One larger than real chain
+
+ assign q[ig] = sync_r[INT_LEN-1]; // Output signal
+ assign next_r = {sync_r,d_in};
+
+ always @(posedge clk or posedge reset)
+ if(reset)
+ sync_r <= L_INIT_VALUE;
+ else
+ sync_r <= next_r[INT_LEN-1:0];
+
+ // Generate asynchronous capture circuit if specified.
+ if(SLOW_CLOCK == 0) begin
+ assign d_in = d[ig];
+ end else begin
+ wire d_clk;
+ reg d_r = L_INIT_VALUE[0];
+ wire clr_n;
+
+ assign d_clk = d[ig];
+ assign d_in = d_r;
+ assign clr_n = ~q[ig] | d_clk; // Clear when output is logic 1 and input is logic 0
+
+ // Asynchronously latch the input signal.
+ always @(posedge d_clk or negedge clr_n)
+ if(!clr_n) d_r <= 1'b0;
+ else if(d_clk) d_r <= 1'b1;
+ end // SLOW_CLOCK
+ end // for loop
+end // generate
+endgenerate
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/altera_wait_generate.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/altera_wait_generate.v
new file mode 100644
index 0000000000000000000000000000000000000000..d11ec7e154387185d9a1d14b39c0410608a6c6ed
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/altera_wait_generate.v
@@ -0,0 +1,38 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+module altera_wait_generate
+//#(
+//This code only works when wait_cycle =1, if need other case, you need to modify this code.
+//please set wait_cycle default value as 1 to keep old design works.
+// parameter wait_cycle =1
+// )
+(
+ input wire rst,
+ input wire clk,
+ input wire launch_signal,
+ output wire wait_req
+ );
+reg launch_reg = 0;
+reg wait_reg = 0;
+always @ (posedge clk, posedge rst) begin
+ if(rst) launch_reg <= 1'b0;
+ else launch_reg <= launch_signal;
+end
+always @ (posedge clk, posedge rst) begin
+ if(rst) wait_reg <= 1'b0;
+ else wait_reg <= launch_signal & launch_reg & (! wait_reg & !wait_req);
+end
+assign wait_req = (launch_signal & ~launch_reg) | (wait_reg & launch_signal ) ;
+endmodule
\ No newline at end of file
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/altera_xcvr_functions.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/altera_xcvr_functions.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5ef175a54cc3ce30e9dded8e494731600eb6ffda
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/altera_xcvr_functions.sv
@@ -0,0 +1,746 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common functions for transceiver PHY IP
+//
+// $Header$
+//
+// PACKAGE DECLARATION
+package altera_xcvr_functions;
+ localparam integer MAX_CHARS = 32;
+ localparam integer MAX_STRS = 16;
+ localparam integer MAX_XCVR_CHANNELS = 64;
+
+ // Reconfiguration bundle widths per family
+ localparam integer W_S5_RECONFIG_BUNDLE_TO_XCVR = 70;
+ localparam integer W_S5_RECONFIG_BUNDLE_FROM_XCVR = 46;
+ localparam integer W_A5_RECONFIG_BUNDLE_TO_XCVR = 70;
+ localparam integer W_A5_RECONFIG_BUNDLE_FROM_XCVR = 46;
+ localparam integer W_S4_RECONFIG_BUNDLE_TO_XCVR = 4;
+ localparam integer W_S4_RECONFIG_BUNDLE_FROM_XCVR = 17;
+ localparam integer W_C4_RECONFIG_BUNDLE_TO_XCVR = 4;
+ localparam integer W_C4_RECONFIG_BUNDLE_FROM_XCVR = 17;
+
+ // Reconfiguration bundle widths per family
+ localparam integer W_S5_RECONFIG_BUNDLE_TO_GXB = W_S5_RECONFIG_BUNDLE_TO_XCVR;
+ localparam integer W_S5_RECONFIG_BUNDLE_FROM_GXB = W_S5_RECONFIG_BUNDLE_FROM_XCVR;
+ localparam integer W_A5_RECONFIG_BUNDLE_TO_GXB = W_A5_RECONFIG_BUNDLE_TO_XCVR;
+ localparam integer W_A5_RECONFIG_BUNDLE_FROM_GXB = W_A5_RECONFIG_BUNDLE_FROM_XCVR;
+ localparam integer W_S4_RECONFIG_BUNDLE_TO_GXB = W_S4_RECONFIG_BUNDLE_TO_XCVR;
+ localparam integer W_S4_RECONFIG_BUNDLE_FROM_GXB = W_S4_RECONFIG_BUNDLE_FROM_XCVR;
+ localparam integer W_C4_RECONFIG_BUNDLE_TO_GXB = W_C4_RECONFIG_BUNDLE_TO_XCVR;
+ localparam integer W_C4_RECONFIG_BUNDLE_FROM_GXB = W_C4_RECONFIG_BUNDLE_FROM_XCVR;
+
+ // convert frequency string into integer Hz. Fractional Hz are truncated
+ // Must remain a constant function - can't use string.atoi().
+ function time str2hz (
+ input [8*MAX_CHARS:1] s
+ );
+
+ integer i;
+ integer c; // temp char storage for frequency conversion
+ integer unit_tens; // assume already Hz
+ integer is_numeric;
+ integer saw_dot;
+
+ reg [8:1] c_dot; // = ".";
+ reg [8:1] c_space; // = " ";
+ reg [8:1] c_a; // = 8'h61; //"a";
+ reg [8:1] c_z; // = 8'h7a; //"z";
+ reg [8*4:1] s_unit;
+ reg [8*MAX_CHARS:1] s_shift;
+
+ begin
+ // frequency ratio calculations
+ str2hz = 0;
+ unit_tens = 0; // assume already Hz
+ is_numeric = 1;
+ saw_dot = 0;
+ s_unit = "";
+
+ // Modelsim optimizer bug forces us to initialize these non-statically
+ c_dot = ".";
+ c_space = " ";
+ c_a = "a";
+ c_z = "z";
+ for (i=(MAX_CHARS-1); i>=0; i=i-1) begin
+ s_shift = (s >> (i*8));
+ c = s_shift[8:1] & 8'hff;
+ if (c > 0) begin
+ //$display("[%d] => '%1s',", i, c);
+ if (c >= 8'h30 && c <= 8'h39 && is_numeric) begin
+ str2hz = (str2hz * 10) + (c & 8'h0f);
+ if (saw_dot) unit_tens = unit_tens - 1; // count digits after decimal point
+ end else if (c == c_dot) saw_dot = 1;
+ else if (c != c_space) begin
+ is_numeric = 0; // stop accepting new numeric digits in value
+ // if it's a-z, convert to upper case A-Z
+ if (c >= c_a && c <= c_z) c = (c & 8'h5f); // convert a-z (lower) to A-Z (upper)
+ s_unit = (s_unit << 8) | c;
+ end
+ end
+ end
+ //$display("numeric = %d x 10**(%2d), unit = '%0s'", str2hz, unit_tens, s_unit);
+
+ // account for frequency unit
+ if (s_unit == "GHZ" || s_unit == "GBPS") unit_tens = unit_tens + 9; // 10**9
+ else if (s_unit == "MHZ" || s_unit == "MBPS") unit_tens = unit_tens + 6; // 10**6
+ else if (s_unit == "KHZ" || s_unit == "KBPS") unit_tens = unit_tens + 3; // 10**3
+ else if (s_unit != "HZ" && s_unit != "BPS") begin
+ $display("Invalid frequency unit '%0s', assuming %d x 10**(%2d) 'Hz'", s_unit, str2hz, unit_tens);
+ end
+ //$display("numeric in Hz = %d x 10**(%2d)", str2hz, unit_tens);
+
+ // align numeric to Hz
+ if (unit_tens < 0) begin
+ //str2hz = str2hz / (10**(-unit_tens));
+ for (i=0; i>unit_tens; i=i-1) begin
+ str2hz = str2hz / 10;
+ end
+ end else begin
+ //str2hz = str2hz * (10**unit_tens);
+ for (i=0; i<unit_tens; i=i+1) begin
+ str2hz = str2hz * 10;
+ end
+ end
+ //$display("%d Hz", str2hz);
+ end
+ endfunction
+
+ // convert integer Hz to a frequency string
+ // integer Hz as type time, and the frequency string will use MHz units
+ // Must remain a constant function - can't use $sformat or string.itoa().
+ function [MAX_CHARS*8-1:0] hz2str (
+ input time hz
+ );
+ integer pos;
+ integer f_unit; // 10**f_unit is offset from Hz for larger unit
+ time hz_mod_10;
+ begin
+ hz2str = "0.000000 MHz"; // minimum string value
+ f_unit = 6; // MHz offsets Hz value by 6 decimal digits
+
+ // convert time back to string with frequency units
+ // char positions 3 to 0 are used by " MHz", so start with digits at pos 4
+ for (pos = 4; pos < MAX_CHARS && hz > 0; pos = pos + 1) begin
+ if (f_unit == 0) begin
+ hz2str[pos*8 +: 8] = 8'h2e; // add "." character
+ pos = pos + 1;
+ end
+ f_unit = f_unit - 1;
+ hz_mod_10 = (hz % 10);
+ hz2str[pos*8 +: 8] = hz_mod_10[7:0] | 8'h30;
+ hz = hz / 10;
+ //$display("hz2str() => so far '%s', pos (%d), f_unit(%d) ", hz2str, pos, f_unit);
+ end
+ //$display("hz2str() returns '%s'", hz2str);
+ end
+ endfunction
+
+ // Convert a string to an integer
+ // Uses pre-existing str2hz function
+ function integer str2int(
+ input [MAX_CHARS*8-1:0] instring
+ );
+ time temp;
+ temp = str2hz({instring,"Hz"});
+ str2int = temp[31:0];
+ endfunction
+
+
+ // Convert an integer to a string
+ function [MAX_CHARS*8-1:0] int2str(
+ input integer in_int
+ );
+ integer i;
+ integer this_char;
+ i = 0;
+ int2str = "";
+ do
+ begin
+ this_char = (in_int % 10) + 48;
+ int2str[i*8+:8] = this_char[7:0];
+ i=i+1;
+ in_int = in_int / 10;
+ end
+ while(in_int > 0);
+ endfunction
+
+ // function to convert at most 40-bit long string to binary
+ function [39 : 0] m_str_to_bin;
+ input [40*8 : 1] s;
+ reg [40*8 : 1] reg_s;
+ reg [40:1] res;
+
+ integer m;
+ begin
+
+ reg_s = s;
+ for (m = 40; m > 0; m = m-1 )
+ begin
+ res[m] = reg_s[313];
+ reg_s = reg_s << 8;
+ end
+
+ m_str_to_bin = res;
+ end
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Verify that the string value is contained in the legal set.
+ //
+ // The 'set' can consist of a single string with no delimiters, e.g. "individual",
+ // or multiple values, separated by commas, and surrounded by parens, e.g. "(one,two,three,four,five)"
+ //
+ // Returns 1 if the value is in the set, and 0 otherwise
+ function integer is_in_legal_set(
+ input [MAX_CHARS*8-1:0] value,
+ input [MAX_STRS*MAX_CHARS*8-1:0] set
+ );
+ if (value == "<auto_any>")
+ is_in_legal_set = 1;
+ else if (value == "<auto_single>")
+ is_in_legal_set = (set[7:0] == 8'h29) ? 0 : 1; // 8'h29 is closing parenthesis char
+ else if (value == set)
+ is_in_legal_set = 1; // value matches single value in set
+ else begin
+ // check value against each in set
+ integer close_pos; // end of string marker can be comma or closing paren
+ integer open_pos; // open paren is start of set, if appropriate
+ reg [MAX_STRS*MAX_CHARS*8-1:0] legalstr;
+
+ is_in_legal_set = 0;
+ open_pos = MAX_STRS*MAX_CHARS-1;
+ // Remove closing parenthesis if exists
+ if(set[7:0] == 8'h29) begin
+ set = (set >> 8);
+ set[(MAX_STRS*MAX_CHARS*8-1)-:8] = 8'h00;
+ end
+ // look for first non-null and non open paren character
+ while (open_pos > 0 && (set[open_pos*8 +: 8] == 8'h00 || set[open_pos*8 +: 8] == 8'h28)) // look for first non-null
+ open_pos = open_pos - 1;
+
+ while (is_in_legal_set == 0 && open_pos >= 0) begin
+ close_pos = open_pos;
+ while (close_pos > 0
+ && set[close_pos*8 +: 8] != 8'h2c) // look for comma (8'h2c)
+ close_pos = close_pos - 1;
+ if (close_pos >= 0) begin
+ close_pos = close_pos == 0 ? 0 : close_pos + 1;
+ legalstr = ((set & ((1'b1 << open_pos*8+8)-1)) >> close_pos*8);
+ if (value == legalstr)
+ is_in_legal_set = 1;
+ end
+ open_pos = close_pos-2; // prepare to look for next legal string
+ end
+ end
+ //$display("is_in_legal_set(): returns %d", is_in_legal_set);
+ endfunction
+
+
+ // Accepts a string list of comma seperated numbers and returns a binary
+ // field where each bit indicates whether the index corresponding to that bit
+ // was found in the legal set.
+ //
+ // @param count - The number of integer indexes to check for in the set
+ // or the highest integer minus 1.
+ // @param set - The list containing the integer values to search for
+ // @return - A bitfield where each bit indicates whether the corresponding
+ // integer was found in the legal set.
+ function [MAX_XCVR_CHANNELS-1:0] map_numerical_is_in_legal_set(
+ input integer count,
+ input [MAX_STRS*MAX_CHARS*8-1:0] set
+ );
+ integer index;
+ reg [MAX_XCVR_CHANNELS-1:0] retval;
+
+ // Validate count parameter
+ if(count > MAX_XCVR_CHANNELS)
+ $display("Error: [map_numerical_is_in_legal_set]: Invalid value for count: %0d",count);
+
+ map_numerical_is_in_legal_set = {MAX_XCVR_CHANNELS{1'b0}};
+ retval = {MAX_XCVR_CHANNELS{1'b0}};
+ for(index = 0; index < count; index = index + 1) begin
+ if(is_in_legal_set(int2str(index),set))
+ retval = retval | (({MAX_XCVR_CHANNELS{1'b0}} | 1'b1) << index);
+ end
+ map_numerical_is_in_legal_set = retval;
+ endfunction
+
+
+ // Accepts a string list of comma seperated numbers and returns a binary
+ // field where each byte contains the corresponding number found in the
+ // list.
+ //
+ // @param count - The number of elements in the list.
+ // @param set - The list containing the integer values.
+ // @return - A bitfield where each byte contains the corresponding number found
+ // at that location in the list.
+ function [MAX_XCVR_CHANNELS*8-1:0] map_numerical_legal_set(
+ input integer count,
+ input [MAX_STRS*MAX_CHARS*8-1:0] set
+ );
+ integer index;
+ reg [MAX_XCVR_CHANNELS-1:0] retval;
+ reg [MAX_CHARS*8-1:0] str_val;
+ reg [7:0] int_val;
+
+ // Validate count parameter
+ if(count > MAX_XCVR_CHANNELS || count > 256)
+ $display("Error: [map_numerical_legal_set]: Invalid value for count: %0d",count);
+
+ map_numerical_legal_set = {MAX_XCVR_CHANNELS{8'd0}};
+ retval = {MAX_XCVR_CHANNELS{8'd0}};
+ for(index = 0; index < count; index = index + 1) begin
+ str_val = get_value_at_index(index,set);
+ if(str_val != "NA") begin
+ int_val = str2int(str_val);
+ if(int_val > 255)
+ $display("Error: [map_numerical_legal_set]: Invalid string contains non-numerical item or value:%0d",int_val);
+ else begin
+ retval = retval | ( ( {MAX_XCVR_CHANNELS{8'd0}} | int_val ) << (index * 8));
+ end
+ end
+ end
+ map_numerical_legal_set = retval;
+ endfunction
+
+
+ // Accepts a comma separated list of string values and returns the element
+ // found at the specified index. If the index is invalid, "NA" is returned
+ //
+ // @param index - The index of the value to return within "set"
+ // @param set - A comma separated list of string values. The entire list may
+ // be surrounded by parenthesis("(item0,item1,item2)")
+ function [MAX_CHARS*8-1:0] get_value_at_index(
+ input integer index,
+ input [MAX_STRS*MAX_CHARS*8-1:0] set
+ );
+ // check value against each in set
+ integer close_pos; // end of string marker can be comma or closing paren
+ integer open_pos; // open paren is start of set, if appropriate
+ reg [MAX_STRS*MAX_CHARS*8-1:0] legalstr;
+ integer cur_index = 0;
+
+ get_value_at_index = "";
+ legalstr = "NA";
+ cur_index = 0;
+ open_pos = MAX_STRS*MAX_CHARS-1;
+ // Remove closing parenthesis if exists
+ if(set[7:0] == 8'h29) begin
+ set = (set >> 8);
+ set[(MAX_STRS*MAX_CHARS*8-1)-:8] = 8'h00;
+ end
+ // Find the start of the string
+ while (open_pos >= 1 && (set[open_pos*8 +: 8] == 8'h00 || set[open_pos*8 +: 8] == 8'h28)) // look for first non-null
+ open_pos = open_pos - 1;
+
+ // Iterate through list until the string is found or we've reached the end of the list
+ while (legalstr == "NA" && open_pos >= 0 && cur_index <= index) begin
+ close_pos = open_pos;
+ // Move the close iterator to the end of the current value (or end of string)
+ while (close_pos > 0
+ && set[close_pos*8 +: 8] != 8'h2c) // look for comma (8'h2c)
+ close_pos = close_pos - 1;
+ if (close_pos >= 0) begin
+ close_pos = close_pos == 0 ? 0 : close_pos + 1;
+ if(index == cur_index) begin
+ legalstr = ((set & ((1'b1 << open_pos*8+8)-1)) >> close_pos*8);
+ end
+ open_pos = close_pos-2; // prepare to look for next legal string
+ end
+ cur_index = cur_index + 1;
+ end
+
+ cur_index = 0;
+ while(legalstr[cur_index*8+:8] != 0) begin
+ get_value_at_index[cur_index*8+:8] = legalstr[cur_index*8+:8];
+ cur_index = cur_index + 1;
+ end
+
+ //$display("is_in_legal_set(): returns %d", is_in_legal_set);
+ endfunction
+
+
+ ////////////////////////////////////////////////////////////////////////
+ // Calculate the minimum number of bits needed to hold an integer value
+ //
+ // Returns ceil_log2() value
+ localparam integer MAX_PRECISION = 32; // VCS requires this declaration outside the function
+ function integer ceil_log2;
+ input [MAX_PRECISION-1:0] input_num;
+ integer i;
+ reg [MAX_PRECISION-1:0] try_result;
+ begin
+ i = 0;
+ try_result = 1;
+ while ((try_result << i) < input_num && i < MAX_PRECISION)
+ i = i + 1;
+ ceil_log2 = i;
+ end
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Return current device family string for display purposes
+ `ifndef XCVR_DEV_FAM
+ `ifdef ALTERA_RESERVED_QIS_FAMILY
+ `define XCVR_DEV_FAM `ALTERA_RESERVED_QIS_FAMILY // synthesis: use QIS-defined value
+ `else
+ `define XCVR_DEV_FAM device_family // simulation: use passed-in value
+ `endif
+ `endif
+ function [MAX_CHARS*8-1:0] current_device_family (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ current_device_family = `XCVR_DEV_FAM;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Match device family against standard family name strings
+ //
+ // Returns 1 if the names feature is present in the given device family
+ function integer has_s4_style_hssi (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ has_s4_style_hssi = ( (`XCVR_DEV_FAM == "Stratix IV")
+ || (`XCVR_DEV_FAM == "Arria II")
+ || (`XCVR_DEV_FAM == "Cyclone IV GX") // not exact, but close enough
+ || (`XCVR_DEV_FAM == "Arria II GX")
+ || (`XCVR_DEV_FAM == "Arria II GZ")
+ || (`XCVR_DEV_FAM == "HardCopy IV")
+ ) ? 1 : 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Match device family against standard family name strings
+ //
+ // Returns 1 if the names feature is present in the given device family
+ function integer has_s5_style_hssi (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ has_s5_style_hssi = ( (`XCVR_DEV_FAM == "Stratix V")
+ ) ? 1 : 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Match device family against standard family name strings
+ //
+ // Returns 1 if the names feature is present in the given device family
+ function integer has_a5_style_hssi (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ has_a5_style_hssi = ( (`XCVR_DEV_FAM == "Arria V")
+ ) ? 1 : 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Match device family against standard family name strings
+ //
+ // Returns 1 if the names feature is present in the given device family
+ function integer has_c5_style_hssi (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ has_c5_style_hssi = ( (`XCVR_DEV_FAM == "Cyclone V")
+ ) ? 1 : 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Match device family against standard family name strings
+ //
+ // Returns 1 if the names feature is present in the given device family
+ function integer has_c4_style_hssi (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ has_c4_style_hssi = ( (`XCVR_DEV_FAM == "Cyclone IV GX")
+ ) ? 1 : 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_to_gxb bundle width for specified device family
+ //
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_to_gxb bundle for that family
+ function integer get_reconfig_to_gxb_width (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family))
+ get_reconfig_to_gxb_width = W_S5_RECONFIG_BUNDLE_TO_XCVR;
+ else if (has_s4_style_hssi(device_family))
+ get_reconfig_to_gxb_width = W_S4_RECONFIG_BUNDLE_TO_XCVR;
+ else if (has_c4_style_hssi(device_family))
+ get_reconfig_to_gxb_width = W_C4_RECONFIG_BUNDLE_TO_XCVR;
+ else
+ get_reconfig_to_gxb_width = 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_from_gxb bundle width for specified device family
+ //
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_gxb bundle for that family
+ function integer get_reconfig_from_gxb_width (
+ input [MAX_CHARS*8-1:0] device_family
+ );
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family))
+ get_reconfig_from_gxb_width = W_S5_RECONFIG_BUNDLE_FROM_XCVR;
+ else if (has_s4_style_hssi(device_family))
+ get_reconfig_from_gxb_width = W_S4_RECONFIG_BUNDLE_FROM_XCVR;
+ else if (has_c4_style_hssi(device_family))
+ get_reconfig_from_gxb_width = W_C4_RECONFIG_BUNDLE_FROM_XCVR;
+ else
+ get_reconfig_from_gxb_width = 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_to_xcvr total port width for specified device family
+ //
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_to_xcvr port for that family
+ function integer get_reconfig_to_width (
+ input [MAX_CHARS*8-1:0] device_family,
+ input integer reconfig_interfaces
+ );
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family))
+ get_reconfig_to_width = get_s5_reconfig_to_width(reconfig_interfaces);
+ else if (has_s4_style_hssi(device_family))
+ get_reconfig_to_width = W_S4_RECONFIG_BUNDLE_TO_XCVR;
+ else if (has_c4_style_hssi(device_family))
+ get_reconfig_to_width = W_C4_RECONFIG_BUNDLE_TO_XCVR;
+ else
+ get_reconfig_to_width = 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_to_xcvr total port width for Stratix V device family
+ //
+ function integer get_s5_reconfig_to_width (
+ input integer reconfig_interfaces
+ );
+ get_s5_reconfig_to_width = reconfig_interfaces * get_reconfig_to_gxb_width("Stratix V");
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_from_xcvr total port width for specified device family
+ //
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_reconfig_from_width (
+ input [MAX_CHARS*8-1:0] device_family,
+ input integer reconfig_interfaces
+ );
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family))
+ get_reconfig_from_width = reconfig_interfaces * get_reconfig_from_gxb_width(device_family);
+ else if (has_s4_style_hssi(device_family))
+ get_reconfig_from_width = reconfig_interfaces * get_reconfig_from_gxb_width(device_family);
+ else if (has_c4_style_hssi(device_family))
+ get_reconfig_from_width = reconfig_interfaces * get_reconfig_from_gxb_width(device_family);
+ else
+ get_reconfig_from_width = 0;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_from_xcvr total port width for Stratix V device family
+ //
+ function integer get_s5_reconfig_from_width (
+ input integer reconfig_interfaces
+ );
+ get_s5_reconfig_from_width = reconfig_interfaces * get_reconfig_from_gxb_width("Stratix V");
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get number of reconfig interfaces for Custom PHY
+ // NOTE - !!Has since been used by other PHY IP!!
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // @param lanes - Number of channels
+ // @param plls - Number of TX plls (per channel)
+ // @param bonded_group_size - Size of bonded group (1 or lanes)
+ // @param data_path_type - Abuse of function by overloading for ATT support
+ // - Carry on the abuse
+ //
+ // @return 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_custom_reconfig_interfaces(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer lanes,
+ input integer plls,
+ input integer bonded_group_size,
+ input [MAX_CHARS*8-1:0] data_path_type = "",
+ input [MAX_CHARS*8-1:0] bonded_mode = "xN"
+ );
+ integer reconfig_interfaces;
+ reconfig_interfaces = 0;
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family)) begin
+ // ATT specific calculations
+ if( data_path_type == "ATT" ) begin
+ if((operation_mode == "RX_ONLY") || (operation_mode == "rx_only") || (operation_mode == "Rx") || (operation_mode == "RX") || (operation_mode == "rx")) begin
+ reconfig_interfaces = lanes;
+ end else if((operation_mode == "TX_ONLY") || (operation_mode == "tx_only") || (operation_mode == "Tx") || (operation_mode == "TX") || (operation_mode == "tx")) begin
+ reconfig_interfaces = 2*lanes;
+ end else begin
+ reconfig_interfaces = 3*lanes;
+ end
+ end else begin
+ // Custom PHY calculations
+ if((operation_mode == "RX") || (operation_mode == "Rx") || (operation_mode == "rx_only"))
+ reconfig_interfaces = lanes;
+ else begin
+ bonded_group_size = (bonded_mode == "fb_compensation") ? 1 : bonded_group_size;
+ reconfig_interfaces = lanes+(plls*(lanes/bonded_group_size));
+ end
+ end
+ end
+ get_custom_reconfig_interfaces = reconfig_interfaces;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_to_xcvr total port width for Custom PHY
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // @param lanes - Number of transceiver channels
+ // @param plls - Number of plls per bonded group
+ // @param bonded_group_size - Size of bonded group (1 or lanes)
+ // @param data_path_type - Abuse of function to support ATT
+ //
+ // @return - 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_custom_reconfig_to_width(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer lanes,
+ input integer plls,
+ input integer bonded_group_size,
+ input [MAX_CHARS*8-1:0] data_path_type = "",
+ input [MAX_CHARS*8-1:0] bonded_mode = "xN"
+ );
+ integer reconfig_interfaces;
+ reconfig_interfaces = get_custom_reconfig_interfaces(device_family,operation_mode,lanes,plls,bonded_group_size, data_path_type, bonded_mode );
+ get_custom_reconfig_to_width = get_s5_reconfig_to_width(reconfig_interfaces);
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_from_xcvr total port width for Custom PHY
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // @param lanes - Number of transceiver channels
+ // @param plls - Number of plls per bonded group
+ // @param bonded_group_size - Size of bonded group (1 or lanes)
+ // @param data_path_type - Abuse of function to support ATT
+ //
+ // @return - 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_custom_reconfig_from_width(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer lanes,
+ input integer plls,
+ input integer bonded_group_size,
+ input [MAX_CHARS*8-1:0] data_path_type = "",
+ input [MAX_CHARS*8-1:0] bonded_mode = "xN"
+ );
+ integer reconfig_interfaces;
+ reconfig_interfaces = get_custom_reconfig_interfaces(device_family,operation_mode,lanes,plls,bonded_group_size, data_path_type, bonded_mode);
+ get_custom_reconfig_from_width = get_s5_reconfig_from_width(reconfig_interfaces);
+ endfunction
+
+
+ ////////////////////////////////////////////////////////////////////
+ // Start Interlaken Specific functions for calculating reconfig interfaces
+ // and reconfig_to_gxb, reconfig_from_gxb widths
+
+ ////////////////////////////////////////////////////////////////////
+ // Get number of reconfig interfaces for Interlaken PHY
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_interlaken_reconfig_interfaces(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer bonded_group_size,
+ input integer lanes
+ );
+ integer reconfig_interfaces;
+ integer xslices;
+ integer xremain;
+ integer totalplls;
+
+ reconfig_interfaces = 0;
+ if (has_s5_style_hssi(device_family) || has_a5_style_hssi(device_family) || has_c5_style_hssi(device_family)) begin
+ if((operation_mode == "RX") || (operation_mode == "Rx") || (operation_mode == "rx_only"))
+ reconfig_interfaces = lanes;
+ else begin
+ xslices = lanes/bonded_group_size;
+ xremain = lanes % bonded_group_size;
+
+ if (xremain >0)
+ totalplls = xslices +1;
+ else
+ totalplls = xslices;
+ reconfig_interfaces = lanes+totalplls;
+ end // else: !if((operation_mode == "RX") || (operation_mode == "Rx") || (operation_mode == "rx_only"))
+ end // if (has_s5_style_hssi(device_family))
+ get_interlaken_reconfig_interfaces = reconfig_interfaces;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_to_xcvr total port width for Interlaken PHY
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // @param lanes - Number of transceiver channels
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_interlaken_reconfig_to_width(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer bonded_group_size,
+ input integer lanes
+ );
+ integer reconfig_interfaces;
+ reconfig_interfaces = get_interlaken_reconfig_interfaces(device_family,operation_mode,bonded_group_size,lanes);
+ get_interlaken_reconfig_to_width = get_s5_reconfig_to_width(reconfig_interfaces);
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Get reconfig_from_xcvr total port width for Custom PHY
+ //
+ // @param device_family - Desired device family
+ // @param operation_mode - "Duplex","Rx","Tx" or "duplex", "rx_only", "tx_only" in 10gbaser
+ // Returns 0 if the device_family argument is invalid, otherwise
+ // it returns the width of the reconfig_from_xcvr port for that family
+ function integer get_interlaken_reconfig_from_width(
+ input [MAX_CHARS*8-1:0] device_family,
+ input [MAX_CHARS*8-1:0] operation_mode,
+ input integer bonded_group_size,
+ input integer lanes
+ );
+ integer reconfig_interfaces;
+ reconfig_interfaces = get_interlaken_reconfig_interfaces(device_family,operation_mode,bonded_group_size,lanes);
+ get_interlaken_reconfig_from_width = get_s5_reconfig_from_width(reconfig_interfaces);
+ endfunction
+
+ // End Interlaken specific functions
+ ////////////////////////////////////////////////////////////////////
+
+
+
+
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/altera_xcvr_xaui.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/altera_xcvr_xaui.sv
new file mode 100644
index 0000000000000000000000000000000000000000..f5731672ef25f5db829bfa5138a5ea5bee0aec5c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/altera_xcvr_xaui.sv
@@ -0,0 +1,510 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//-----------------------------------------------------------------------------
+//
+// Description: alt_xaui static verilog top level
+//
+// Authors: bauyeung 7-Sep-2010
+// Modified: ishimony 13-Dec-2010
+//
+// Copyright (c) Altera Corporation 1997 - 2010
+// All rights reserved.
+//
+//
+//-----------------------------------------------------------------------------
+
+// have separate generate statements for each component
+
+`timescale 1 ps / 1 ps
+import altera_xcvr_functions::*;
+(* altera_attribute = "-name IP_TOOL_NAME __ACDS_IP_CORE_NAME__; -name IP_TOOL_VERSION __ACDS_VERSION_SHORT__" *)
+module altera_xcvr_xaui #(
+ parameter device_family = "Stratix IV", // default Stratix IV
+ parameter starting_channel_number = 0, // only applies to SIV
+ parameter interface_type = "Hard XAUI",
+ parameter data_rate = "3125 Mbps",
+ parameter xaui_pll_type = "CMU",
+ parameter BASE_DATA_RATE = "3125 Mbps",
+ parameter use_control_and_status_ports = 0,
+ parameter external_pma_ctrl_reconf = 0,
+ parameter recovered_clk_out = 0,
+ parameter number_of_interfaces = 1,
+ parameter reconfig_interfaces = 1,
+ parameter use_rx_rate_match = 0,
+ parameter tx_termination = "OCT_150_OHMS",
+ parameter tx_vod_selection = 1,
+ parameter tx_preemp_pretap = 0,
+ parameter tx_preemp_pretap_inv = 0,
+ parameter tx_preemp_tap_1 = 5,
+ parameter tx_preemp_tap_2 = 0,
+ parameter tx_preemp_tap_2_inv = 0,
+ parameter rx_common_mode = "0.82v",
+ parameter rx_termination = "OCT_150_OHMS",
+ parameter rx_eq_dc_gain = 0,
+ parameter rx_eq_ctrl = 14,
+ parameter mgmt_clk_in_mhz = 50
+) (
+ input wire pll_ref_clk,
+ input wire xgmii_tx_clk,
+ output wire xgmii_rx_clk,
+ output wire tx_clk312_5, // dxaui: pma tx out clock, 312.5Mhz
+ input wire phy_mgmt_clk,
+ input wire phy_mgmt_clk_reset,
+ input wire [8:0] phy_mgmt_address,
+ output wire phy_mgmt_waitrequest,
+ input wire phy_mgmt_read,
+ output wire [31:0] phy_mgmt_readdata,
+ input wire phy_mgmt_write,
+ input wire [31:0] phy_mgmt_writedata,
+ input wire [71:0] xgmii_tx_dc,
+ output wire [71:0] xgmii_rx_dc,
+ output wire [3:0] xaui_tx_serial_data,
+ input wire [3:0] xaui_rx_serial_data,
+ output wire rx_ready,
+ output wire tx_ready,
+ output wire [3:0] rx_recovered_clk, // rx recovered clock from cdr
+
+// only used if use_control_and_status_ports is set
+ input tri0 rx_analogreset,
+ input tri0 rx_digitalreset,
+ input tri0 tx_digitalreset,
+ output tri0 rx_channelaligned,
+ input tri0 [3:0] rx_invpolarity,
+ input tri0 [3:0] rx_set_locktodata,
+ input tri0 [3:0] rx_set_locktoref,
+ input tri0 [3:0] rx_seriallpbken,
+ input tri0 [3:0] tx_invpolarity,
+ output tri1 [3:0] rx_is_lockedtodata,
+ output tri0 [3:0] rx_phase_comp_fifo_error,
+ output tri1 [3:0] rx_is_lockedtoref,
+ output tri0 [3:0] rx_rlv,
+ output tri0 [3:0] rx_rmfifoempty,
+ output tri0 [3:0] rx_rmfifofull,
+ output tri0 [3:0] tx_phase_comp_fifo_error,
+ output tri0 [7:0] rx_disperr,
+ output tri0 [7:0] rx_errdetect,
+ output tri0 [7:0] rx_patterndetect,
+ output tri0 [7:0] rx_rmfifodatadeleted,
+ output tri0 [7:0] rx_rmfifodatainserted,
+ output tri0 [7:0] rx_runningdisp,
+ output tri0 [7:0] rx_syncstatus,
+
+
+// only used if external_pma_ctrl_reconf is set
+ output tri0 [altera_xcvr_functions::get_reconfig_from_width(device_family,reconfig_interfaces)-1:0] reconfig_from_xcvr,
+ input tri0 [altera_xcvr_functions::get_reconfig_to_width(device_family,reconfig_interfaces) -1:0] reconfig_to_xcvr,
+ output tri0 pll_locked,
+ input tri0 cal_blk_powerdown,
+ input tri0 gxb_powerdown,
+ input tri0 pll_powerdown
+// need to add all possible port/param combinations
+// these should be set to tri0/1 where possible, so unused ports don't need to be terminated by the user
+);
+
+import altera_xcvr_functions::*;
+
+localparam reconfig_out_width = altera_xcvr_functions::get_reconfig_from_width(device_family,reconfig_interfaces);
+localparam reconfig_in_width = altera_xcvr_functions::get_reconfig_to_width(device_family,reconfig_interfaces);
+
+ wire [reconfig_out_width -1:0] l_reconfig_from_xcvr; // local reconfig_from_xcvr
+ wire [reconfig_in_width -1:0] l_reconfig_to_xcvr; // local reconfig_to_xcvr
+
+ wire [7:0] sc_phy_address; // mgmt.address
+ wire sc_phy_waitrequest; // .waitrequest
+ wire sc_phy_read; // .read
+ wire [31:0] sc_phy_readdata; // .readdata
+ wire sc_phy_write; // .write
+
+ wire [6:0] sc_reconf_address; // mgmt.address
+ wire sc_reconf_waitrequest; // .waitrequest
+ wire sc_reconf_read; // .read
+ wire [31:0] sc_reconf_readdata; // .readdata
+ wire sc_reconf_write; // .write
+
+///////////////////////////////////////////////////////////////////////
+// Custom decoder for multiple slaves of phy-reconfig interface
+///////////////////////////////////////////////////////////////////////
+// should be consistent across all device families
+ alt_xcvr_mgmt2dec_phyreconfig mgmtdec_phyreconfig (
+ .mgmt_clk_reset (phy_mgmt_clk_reset),
+ .mgmt_clk (phy_mgmt_clk),
+
+ .mgmt_address (phy_mgmt_address),
+ .mgmt_read (phy_mgmt_read),
+ .mgmt_write (phy_mgmt_write),
+ .mgmt_readdata (phy_mgmt_readdata),
+ .mgmt_waitrequest (phy_mgmt_waitrequest),
+
+ // internal interface to 'top' phy block
+ .sc_phy_readdata (sc_phy_readdata),
+ .sc_phy_waitrequest (sc_phy_waitrequest),
+ .sc_phy_address (sc_phy_address),
+ .sc_phy_read (sc_phy_read),
+ .sc_phy_write (sc_phy_write),
+
+ // internal interface to 'top' reconfig block
+ .sc_reconf_readdata (sc_reconf_readdata),
+ .sc_reconf_waitrequest (sc_reconf_waitrequest),
+ .sc_reconf_address (sc_reconf_address),
+ .sc_reconf_read (sc_reconf_read),
+ .sc_reconf_write (sc_reconf_write)
+ );
+
+
+///////////////////////////////////////////////////////////////////////
+// alt_xcvr_reconfig
+///////////////////////////////////////////////////////////////////////
+// add generate statement for this
+// need to account for external pma reconfig
+ generate
+ if (external_pma_ctrl_reconf == 1) begin
+ assign l_reconfig_to_xcvr = reconfig_to_xcvr;
+ assign reconfig_from_xcvr = l_reconfig_from_xcvr;
+ end else if ((interface_type == "Hard XAUI") && ((device_family == "Stratix IV") || (device_family == "HardCopy IV") || (device_family == "Arria II GX") || (device_family == "Arria II GX") || (device_family == "Arria II GZ"))) begin
+ alt_xcvr_reconfig_siv #(
+ .number_of_reconfig_interfaces (1)
+ ) alt_xcvr_reconfig_0 (
+ .mgmt_clk_clk (phy_mgmt_clk),
+ .mgmt_rst_reset (phy_mgmt_clk_reset),
+ .reconfig_mgmt_address (sc_reconf_address),
+ .reconfig_mgmt_waitrequest (sc_reconf_waitrequest),
+ .reconfig_mgmt_read (sc_reconf_read),
+ .reconfig_mgmt_readdata (sc_reconf_readdata),
+ .reconfig_mgmt_write (sc_reconf_write),
+ .reconfig_mgmt_writedata (phy_mgmt_writedata),
+ .reconfig_togxb (l_reconfig_to_xcvr),
+ .reconfig_fromgxb (l_reconfig_from_xcvr[16:0])
+ );
+ end else if ((interface_type == "Soft XAUI") && ((device_family == "Stratix IV") || (device_family == "HardCopy IV"))) begin // Arria II GX/GZ don't support soft xaui
+ alt_xcvr_reconfig_siv #(
+ .number_of_reconfig_interfaces (4)
+ ) alt_xcvr_reconfig_0 (
+ .mgmt_clk_clk (phy_mgmt_clk),
+ .mgmt_rst_reset (phy_mgmt_clk_reset),
+ .reconfig_mgmt_address (sc_reconf_address),
+ .reconfig_mgmt_waitrequest (sc_reconf_waitrequest),
+ .reconfig_mgmt_read (sc_reconf_read),
+ .reconfig_mgmt_readdata (sc_reconf_readdata),
+ .reconfig_mgmt_write (sc_reconf_write),
+ .reconfig_mgmt_writedata (phy_mgmt_writedata),
+ .reconfig_togxb (l_reconfig_to_xcvr),
+ .reconfig_fromgxb (l_reconfig_from_xcvr)
+ );
+ end else if ((interface_type == "DDR XAUI") && (device_family == "Stratix IV")) begin
+ // stub for now - nothing here
+ end else if (device_family == "Stratix V") begin
+ // stub for now - nothing here
+ assign l_reconfig_to_xcvr = reconfig_to_xcvr;
+ assign reconfig_from_xcvr = l_reconfig_from_xcvr;
+ end else if (device_family == "Cyclone IV GX") begin
+ alt_xcvr_reconfig_civ #(
+ .number_of_reconfig_interfaces (1)
+ ) alt_xcvr_reconfig_0 (
+ .reconfig_mgmt_clk_clk (phy_mgmt_clk),
+ .reconfig_mgmt_rst_reset (phy_mgmt_clk_reset),
+ .reconfig_mgmt_address (sc_reconf_address),
+ .reconfig_mgmt_waitrequest (sc_reconf_waitrequest),
+ .reconfig_mgmt_read (sc_reconf_read),
+ .reconfig_mgmt_readdata (sc_reconf_readdata),
+ .reconfig_mgmt_write (sc_reconf_write),
+ .reconfig_mgmt_writedata (phy_mgmt_writedata),
+ .reconfig_togxb (l_reconfig_to_xcvr),
+ .reconfig_fromgxb (l_reconfig_from_xcvr[16:0])
+ );
+ end
+ endgenerate
+
+///////////////////////////////////////////////////////////////////////
+// alt_xaui_phy - Integrates hxaui (i/f to hxaui_alt_c3gxb), csr, pma
+// controller and pma channel controller
+///////////////////////////////////////////////////////////////////////
+ generate
+ if (device_family == "Stratix V") begin
+ sv_xcvr_xaui #(
+ .device_family (device_family),
+ .starting_channel_number (starting_channel_number),
+ .interface_type (interface_type),
+ .reconfig_interfaces (reconfig_interfaces),
+ .sys_clk_in_mhz (mgmt_clk_in_mhz),
+ .data_rate (data_rate),
+ .xaui_pll_type (xaui_pll_type),
+ .BASE_DATA_RATE (BASE_DATA_RATE),
+ .use_control_and_status_ports (use_control_and_status_ports),
+ .tx_termination (tx_termination),
+ .rx_termination (rx_termination),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv (tx_preemp_pretap_inv),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv (tx_preemp_tap_2_inv),
+ .tx_vod_selection (tx_vod_selection),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .rx_common_mode (rx_common_mode),
+ .bonded_group_size (4), /// allowed values 1=> non-bonded 4=> bonded
+ .bonded_mode ("xN") /// allowed values "xN" and "fb_compensation"
+ ) alt_xaui_phy (
+ .pll_ref_clk (pll_ref_clk), // refclk.clk
+ .xgmii_tx_clk (xgmii_tx_clk), // xgmii_tx_clk.clk
+ .xgmii_rx_clk (xgmii_rx_clk), // xgmii_rx_clk.clk
+ .phy_mgmt_clk (phy_mgmt_clk), // mgmt_clk.clk
+ .phy_mgmt_clk_reset (phy_mgmt_clk_reset), // mgmt_clk_rst.reset_n
+ .phy_mgmt_address (sc_phy_address), // phy_mgmt.address
+ .phy_mgmt_waitrequest (sc_phy_waitrequest), // .waitrequest
+ .phy_mgmt_read (sc_phy_read), // .read
+ .phy_mgmt_readdata (sc_phy_readdata), // .readdata
+ .phy_mgmt_write (sc_phy_write), // .write
+ .phy_mgmt_writedata (phy_mgmt_writedata), // .writedata
+ .xgmii_tx_dc (xgmii_tx_dc), // xgmii_tx_dc.data
+ .xgmii_rx_dc (xgmii_rx_dc), // xgmii_rx_dc.data
+ .xaui_tx_serial_data (xaui_tx_serial_data), // xaui_tx_serial.export
+ .xaui_rx_serial_data (xaui_rx_serial_data), // xaui_rx_serial.export
+ .rx_digitalreset (rx_digitalreset), // rx_digitalreset.data
+ .tx_digitalreset (tx_digitalreset), // tx_digitalreset.data
+ .rx_channelaligned (rx_channelaligned), // rx_channelaligned.data
+ .rx_syncstatus (rx_syncstatus), // rx_syncstatus.data
+ .rx_disperr (rx_disperr), // rx_disperr.data
+ .rx_errdetect (rx_errdetect), // rx_errdetect.data
+ .rx_ready (rx_ready), // rx_pma_ready.data
+ .tx_ready (tx_ready), // tx_pma_ready.data
+ .reconfig_to_xcvr (l_reconfig_to_xcvr),
+ .reconfig_from_xcvr (l_reconfig_from_xcvr),
+ .rx_recovered_clk (rx_recovered_clk)
+ );
+ end else if ((interface_type == "DDR XAUI") && (device_family == "Stratix IV")) begin
+ dxaui_siv #(
+ .device_family (device_family),
+ .starting_channel_number (starting_channel_number),
+ .interface_type (interface_type),
+ .number_of_interfaces (1),
+ .reconfig_interfaces (reconfig_interfaces),
+ .sys_clk_in_mhz (mgmt_clk_in_mhz),
+ .xaui_pll_type (xaui_pll_type),
+ .use_control_and_status_ports (use_control_and_status_ports),
+ .external_pma_ctrl_reconf (external_pma_ctrl_reconf),
+ .tx_termination (tx_termination),
+ .tx_vod_selection (tx_vod_selection),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv (tx_preemp_pretap_inv),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv (tx_preemp_tap_2_inv),
+ .rx_common_mode (rx_common_mode),
+ .rx_termination (rx_termination),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .use_rx_rate_match (use_rx_rate_match)
+) dxaui_siv (
+ .pll_ref_clk (pll_ref_clk), // i
+ .xgmii_tx_clk (xgmii_tx_clk), // i
+ .xgmii_rx_clk (xgmii_rx_clk), // o
+ .tx_clk312_5 (tx_clk312_5), // o
+ .phy_mgmt_clk (phy_mgmt_clk), // i
+ .phy_mgmt_clk_reset (phy_mgmt_clk_reset), // i
+ .phy_mgmt_address (sc_phy_address), // i
+ .phy_mgmt_waitrequest (sc_phy_waitrequest), // o
+ .phy_mgmt_read (sc_phy_read), // i
+ .phy_mgmt_readdata (sc_phy_readdata), // o
+ .phy_mgmt_write (sc_phy_write), // i
+ .phy_mgmt_writedata (phy_mgmt_writedata), // i
+ .xgmii_tx_dc (xgmii_tx_dc), // i
+ .xgmii_rx_dc (xgmii_rx_dc), // o
+ .xaui_tx_serial_data (xaui_tx_serial_data), // o
+ .xaui_rx_serial_data (xaui_rx_serial_data), // i
+ .rx_ready (rx_ready), // o
+ .tx_ready (tx_ready), // o
+ .rx_recovered_clk (rx_recovered_clk), // o
+ .reconfig_from_xcvr (l_reconfig_from_xcvr), // o
+ .reconfig_to_xcvr (l_reconfig_to_xcvr), // i
+ .rx_analogreset (rx_analogreset), // i
+ .rx_digitalreset (rx_digitalreset), // i
+ .tx_digitalreset (tx_digitalreset), // i
+ .rx_channelaligned (rx_channelaligned), // o
+ .rx_invpolarity (rx_invpolarity), // i
+ .rx_set_locktodata (rx_set_locktodata), // i
+ .rx_set_locktoref (rx_set_locktoref), // i
+ .rx_seriallpbken (rx_seriallpbken), // i
+ .tx_invpolarity (tx_invpolarity), // i
+ .rx_is_lockedtodata (rx_is_lockedtodata), // o
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error), // o
+ .rx_is_lockedtoref (rx_is_lockedtoref), // o
+ .rx_rlv (rx_rlv), // o
+ .rx_rmfifoempty (rx_rmfifoempty), // o
+ .rx_rmfifofull (rx_rmfifofull), // o
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error), // o
+ .rx_disperr (rx_disperr), // o
+ .rx_errdetect (rx_errdetect), // o
+ .rx_patterndetect (rx_patterndetect), // o
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted), // o
+ .rx_rmfifodatainserted (rx_rmfifodatainserted), // o
+ .rx_runningdisp (rx_runningdisp), // o
+ .rx_syncstatus (rx_syncstatus), // o
+ .pll_locked (pll_locked), // o
+ .cal_blk_powerdown (cal_blk_powerdown), // i
+ .gxb_powerdown (gxb_powerdown), // i
+ .pll_powerdown (pll_powerdown) // i
+); // module dxaui_siv
+ end else if ((device_family == "Stratix IV") || (device_family == "HardCopy IV") ||(device_family == "Arria II GX") || (device_family == "Arria II GZ")) begin
+ siv_xcvr_xaui #(
+ .device_family (device_family),
+ .starting_channel_number (starting_channel_number),
+ .interface_type (interface_type),
+ .number_of_interfaces (1),
+ .reconfig_interfaces (reconfig_interfaces),
+ .sys_clk_in_mhz (mgmt_clk_in_mhz),
+ .xaui_pll_type (xaui_pll_type),
+ .use_control_and_status_ports (use_control_and_status_ports),
+ .external_pma_ctrl_reconf (external_pma_ctrl_reconf),
+ .tx_termination (tx_termination),
+ .rx_termination (rx_termination),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv (tx_preemp_pretap_inv),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv (tx_preemp_tap_2_inv),
+ .tx_vod_selection (tx_vod_selection),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .rx_common_mode (rx_common_mode)
+ ) xaui_phy (
+ .pll_ref_clk (pll_ref_clk),
+ .xgmii_rx_clk (xgmii_rx_clk),
+ .xgmii_tx_clk (xgmii_tx_clk),
+ .phy_mgmt_clk (phy_mgmt_clk),
+ .phy_mgmt_clk_reset (phy_mgmt_clk_reset),
+ .phy_mgmt_address (sc_phy_address),
+ .phy_mgmt_read (sc_phy_read),
+ .phy_mgmt_readdata (sc_phy_readdata),
+ .phy_mgmt_waitrequest (sc_phy_waitrequest),
+ .phy_mgmt_write (sc_phy_write),
+ .phy_mgmt_writedata (phy_mgmt_writedata),
+ .xaui_rx_serial_data (xaui_rx_serial_data),
+ .xaui_tx_serial_data (xaui_tx_serial_data),
+ .xgmii_rx_dc (xgmii_rx_dc),
+ .xgmii_tx_dc (xgmii_tx_dc),
+ .rx_ready (rx_ready),
+ .tx_ready (tx_ready),
+ .rx_recovered_clk (rx_recovered_clk), //o
+ .reconfig_from_xcvr (l_reconfig_from_xcvr),
+ .reconfig_to_xcvr (l_reconfig_to_xcvr),
+
+// optional control and status ports - will be terminated by tri0 if unconnected
+ .rx_analogreset (rx_analogreset), // input wire
+ .rx_digitalreset (rx_digitalreset), // input wire [3:0]
+ .tx_digitalreset (tx_digitalreset), // input wire [3:0]
+ .rx_channelaligned (rx_channelaligned), // output wire
+ .rx_invpolarity (rx_invpolarity), // input wire [3:0]
+ .rx_set_locktodata (rx_set_locktodata), // input wire [3:0]
+ .rx_set_locktoref (rx_set_locktoref), // input wire [3:0]
+ .rx_seriallpbken (rx_seriallpbken), // input wire [3:0]
+ .tx_invpolarity (tx_invpolarity), // input wire [3:0]
+ .rx_is_lockedtodata (rx_is_lockedtodata), // output wire [3:0]
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error), // output wire [3:0]
+ .rx_is_lockedtoref (rx_is_lockedtoref), // output wire [3:0]
+ .rx_rlv (rx_rlv), // output wire [3:0]
+ .rx_rmfifoempty (rx_rmfifoempty), // output wire [3:0]
+ .rx_rmfifofull (rx_rmfifofull), // output wire [3:0]
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error), // output wire [3:0]
+ .rx_disperr (rx_disperr), // output wire [7:0]
+ .rx_errdetect (rx_errdetect), // output wire [7:0]
+ .rx_patterndetect (rx_patterndetect), // output wire [7:0]
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted), // output wire [7:0]
+ .rx_rmfifodatainserted (rx_rmfifodatainserted), // output wire [7:0]
+ .rx_runningdisp (rx_runningdisp), // output wire [7:0]
+ .rx_syncstatus (rx_syncstatus), // output wire [7:0]
+
+// external_pma_ctrl_reconf
+ .pll_locked (pll_locked), // output wire
+ .cal_blk_powerdown (cal_blk_powerdown), // input wire
+ .gxb_powerdown (gxb_powerdown), // input wire
+ .pll_powerdown (pll_powerdown) // input wire
+ );
+ end else if (device_family == "Cyclone IV GX") begin
+// need to add the extra optional ports for c&s and ext_pma
+ civ_xcvr_xaui #(
+ .device_family (device_family),
+ .starting_channel_number (starting_channel_number),
+ .interface_type (interface_type),
+ .number_of_interfaces (1),
+ .sys_clk_in_mhz (mgmt_clk_in_mhz),
+ .xaui_pll_type (xaui_pll_type),
+ .use_control_and_status_ports (use_control_and_status_ports),
+ .tx_termination (tx_termination),
+ .rx_termination (rx_termination),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv (tx_preemp_pretap_inv),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv (tx_preemp_tap_2_inv),
+ .tx_vod_selection (tx_vod_selection),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .rx_common_mode (rx_common_mode)
+ ) xaui_phy (
+ .pll_ref_clk (pll_ref_clk),
+ .xgmii_rx_clk (xgmii_rx_clk),
+ .xgmii_tx_clk (xgmii_tx_clk),
+ .phy_mgmt_clk (phy_mgmt_clk),
+ .phy_mgmt_clk_reset (phy_mgmt_clk_reset),
+ .phy_mgmt_address (sc_phy_address),
+ .phy_mgmt_read (sc_phy_read),
+ .phy_mgmt_readdata (sc_phy_readdata),
+ .phy_mgmt_waitrequest (sc_phy_waitrequest),
+ .phy_mgmt_write (sc_phy_write),
+ .phy_mgmt_writedata (phy_mgmt_writedata),
+ .xaui_rx_serial_data (xaui_rx_serial_data),
+ .xaui_tx_serial_data (xaui_tx_serial_data),
+ .xgmii_rx_dc (xgmii_rx_dc),
+ .xgmii_tx_dc (xgmii_tx_dc),
+ .rx_ready (rx_ready),
+ .tx_ready (tx_ready),
+ .rx_recovered_clk (rx_recovered_clk), //o
+ .reconfig_from_xcvr (l_reconfig_from_xcvr[16:0]),
+ .reconfig_to_xcvr (l_reconfig_to_xcvr),
+
+// optional control and status ports - will be terminated by tri0 if unconnected
+ .rx_analogreset (rx_analogreset), // input wire
+ .rx_digitalreset (rx_digitalreset), // input wire [3:0]
+ .tx_digitalreset (tx_digitalreset), // input wire [3:0]
+ .rx_channelaligned (rx_channelaligned), // output wire
+ .rx_invpolarity (rx_invpolarity), // input wire [3:0]
+ .rx_set_locktodata (rx_set_locktodata), // input wire [3:0]
+ .rx_set_locktoref (rx_set_locktoref), // input wire [3:0]
+ .rx_seriallpbken (rx_seriallpbken), // input wire [3:0]
+ .tx_invpolarity (tx_invpolarity), // input wire [3:0]
+ .rx_is_lockedtodata (rx_is_lockedtodata), // output wire [3:0]
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error), // output wire [3:0]
+ .rx_is_lockedtoref (rx_is_lockedtoref), // output wire [3:0]
+ .rx_rlv (rx_rlv), // output wire [3:0]
+ .rx_rmfifoempty (rx_rmfifoempty), // output wire [3:0]
+ .rx_rmfifofull (rx_rmfifofull), // output wire [3:0]
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error), // output wire [3:0]
+ .rx_disperr (rx_disperr), // output wire [7:0]
+ .rx_errdetect (rx_errdetect), // output wire [7:0]
+ .rx_patterndetect (rx_patterndetect), // output wire [7:0]
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted), // output wire [7:0]
+ .rx_rmfifodatainserted (rx_rmfifodatainserted), // output wire [7:0]
+ .rx_runningdisp (rx_runningdisp), // output wire [7:0]
+ .rx_syncstatus (rx_syncstatus), // output wire [7:0]
+
+// external_pma_ctrl_reconf
+ .pll_locked (pll_locked), // output wire
+ .cal_blk_powerdown (cal_blk_powerdown), // input wire
+ .gxb_powerdown (gxb_powerdown), // input wire
+ .pll_powerdown (pll_powerdown) // input wire
+ );
+ end
+ endgenerate
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/cadence_files.txt b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/cadence_files.txt
new file mode 100644
index 0000000000000000000000000000000000000000..74a1494a6ca89260bfe8fcacc20a13a631512bbf
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/cadence_files.txt
@@ -0,0 +1,59 @@
+./altera_xcvr_functions.sv
+./alt_pma_functions.sv
+./altera_xcvr_xaui.sv
+./hxaui_csr_h.sv
+./hxaui_csr.sv
+./alt_xcvr_mgmt2dec_phyreconfig.sv
+./alt_xcvr_mgmt2dec_xaui.sv
+./alt_pma_ch_controller_tgx.v
+./alt_pma_controller_tgx.v
+./alt_reset_ctrl_lego.sv
+./alt_reset_ctrl_tgx_cdrauto.sv
+./alt_xcvr_resync.sv
+./alt_xcvr_csr_common_h.sv
+./alt_xcvr_csr_common.sv
+./alt_xcvr_csr_pcs8g_h.sv
+./alt_xcvr_csr_pcs8g.sv
+./alt_xcvr_csr_selector.sv
+./alt_xcvr_mgmt2dec.sv
+./altera_wait_generate.v
+./cadence/alt_soft_xaui_pcs.v
+./cadence/alt_soft_xaui_reset.v
+./cadence/alt_soft_xaui_rx.v
+./cadence/alt_soft_xaui_rx_8b10b_dec.v
+./cadence/alt_soft_xaui_rx_channel_synch.v
+./cadence/alt_soft_xaui_rx_deskew.v
+./cadence/alt_soft_xaui_rx_deskew_channel.v
+./cadence/alt_soft_xaui_rx_deskew_ram.v
+./cadence/alt_soft_xaui_rx_invalid_code_det.v
+./cadence/alt_soft_xaui_rx_parity.v
+./cadence/alt_soft_xaui_rx_parity_4b.v
+./cadence/alt_soft_xaui_rx_parity_6b.v
+./cadence/alt_soft_xaui_rx_rate_match.v
+./cadence/alt_soft_xaui_rx_rate_match_ram.v
+./cadence/alt_soft_xaui_rx_rl_chk_6g.v
+./cadence/alt_soft_xaui_rx_sm.v
+./cadence/alt_soft_xaui_tx.v
+./cadence/alt_soft_xaui_tx_8b10b_enc.v
+./cadence/alt_soft_xaui_tx_idle_conv.v
+./cadence/l_modules.v
+./cadence/serdes_4_unit_lc_siv.v
+./cadence/serdes_4_unit_siv.v
+./cadence/serdes_4unit.v
+./sxaui.v
+./siv_xcvr_low_latency_phy_nr.sv
+./siv_xcvr_xaui.sv
+./alt4gxb_vo.v
+./alt_xcvr_reconfig_h.sv
+./alt_xcvr_reconfig_siv.sv
+./alt_xcvr_reconfig_analog.sv
+./alt_xcvr_reconfig_analog_tgx.v
+./alt_xcvr_reconfig_offset_cancellation.sv
+./alt_xcvr_reconfig_offset_cancellation_tgx.v
+./alt_xcvr_reconfig_eyemon_tgx.sv
+./alt_xcvr_reconfig_dfe_tgx.sv
+./alt_xcvr_reconfig_basic_tgx.v
+./alt_mutex_acq.v
+./alt_dprio.v
+./alt_xcvr_arbiter.sv
+./alt_xcvr_m2s.sv
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/hxaui_csr.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/hxaui_csr.sv
new file mode 100644
index 0000000000000000000000000000000000000000..5ad633285f019d30350c678e518974f6621093e3
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/hxaui_csr.sv
@@ -0,0 +1,415 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// (C) 2001-2010 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+///////////////////////////////////////////////////////////////////////////////
+//
+//
+// Description: Hard xaui control and status registers
+//
+// Authors: ishimony 12-Jun-2009
+//
+// Copyright (c) Altera Corporation 1997 - 2009
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+//
+// TBD: unless synthesis is smart enough all synchronization flops will have
+// to be manually instantiated (altera_std_synchronizer)
+//
+
+`timescale 1 ps / 1 ps
+
+module hxaui_csr(
+ clk, reset, address, byteenable, read, readdata, write, writedata,
+ rx_patterndetect, rx_syncstatus, rx_runningdisp, rx_errdetect,
+ rx_disperr, rx_phase_comp_fifo_error, rx_rlv, rx_rmfifodatadeleted,
+ rx_rmfifodatainserted, rx_rmfifoempty, rx_rmfifofull,
+ tx_phase_comp_fifo_error, r_rx_invpolarity, r_tx_invpolarity,
+ r_rx_digitalreset, r_tx_digitalreset, simulation_flag
+); // module hxaui_csr
+import hxaui_csr_h::*;
+
+// ports -------------------------------------------------------------------
+
+// Avalon MM slave
+input clk;
+input reset;
+
+input [4:0] address;
+input [3:0] byteenable;
+
+input read;
+output [31:0] readdata;
+
+input write;
+input [31:0] writedata;
+
+// hard xaui control/status
+input [7:0] rx_patterndetect;
+input [7:0] rx_syncstatus;
+input [7:0] rx_runningdisp; // nc
+
+input [7:0] rx_errdetect;
+input [7:0] rx_disperr;
+
+input [3:0] rx_phase_comp_fifo_error;
+input [3:0] rx_rlv;
+
+input [7:0] rx_rmfifodatadeleted;
+input [7:0] rx_rmfifodatainserted;
+input [3:0] rx_rmfifoempty;
+input [3:0] rx_rmfifofull;
+
+input [3:0] tx_phase_comp_fifo_error;
+
+output [3:0] r_rx_invpolarity;
+output [3:0] r_tx_invpolarity;
+output r_rx_digitalreset;
+output r_tx_digitalreset;
+
+output simulation_flag; // '1' shortens reset and loss_timer length
+
+// ports -------------------------------------------------------------------
+wire clk;
+wire reset;
+wire [4:0] address;
+wire [6:0] addr;
+wire [3:0] byteenable;
+wire read;
+reg [31:0] readdata;
+wire write;
+wire [31:0] writedata;
+wire [3:0] rx_phase_comp_fifo_error;
+wire [3:0] rx_rlv;
+wire [3:0] rx_rmfifoempty;
+wire [3:0] rx_rmfifofull;
+wire [3:0] tx_phase_comp_fifo_error;
+wire [7:0] rx_disperr;
+wire [7:0] rx_errdetect;
+wire [7:0] rx_patterndetect;
+wire [7:0] rx_rmfifodatadeleted;
+wire [7:0] rx_rmfifodatainserted;
+wire [7:0] rx_runningdisp;
+wire [7:0] rx_syncstatus;
+wire [3:0] r_rx_invpolarity;
+wire [3:0] r_tx_invpolarity;
+wire r_rx_digitalreset;
+wire r_tx_digitalreset;
+wire simulation_flag;
+
+// locals ------------------------------------------------------------------
+reg [1:0] hxaui_csr_reset, hxaui_csr_reset0q;
+reg [3:0] hxaui_csr_rx_cntrl, hxaui_csr_rx_cntrl0q;
+reg [3:0] hxaui_csr_tx_cntrl, hxaui_csr_tx_cntrl0q;
+wire [31:0] hxaui_csr_rx_status_0;
+wire [31:0] hxaui_csr_rx_status_1;
+wire [31:0] hxaui_csr_rx_status_2;
+wire [31:0] hxaui_csr_rx_status_3;
+wire [31:0] hxaui_csr_rx_status_4;
+wire [31:0] hxaui_csr_tx_status_0;
+reg hxaui_csr_simulation_flag, hxaui_csr_simulation_flag0q;
+
+
+reg [7:0] rx_patterndetect_c; // rx_patterndetect synced to clk
+reg [7:0] rx_syncstatus_c; // rx_syncstatus synced to clk
+reg [7:0] rx_patterndetect_sr; // rx_patterndetect sr ff
+reg [7:0] rx_syncstatus_sr; // rx_syncstatus sr ff
+wire read_rx_status_0;
+
+reg [7:0] rx_errdetect_c; // rx_errdetect synced to clk
+reg [7:0] rx_disperr_c; // rx_disperr synced to clk
+reg [7:0] rx_errdetect_sr; // rx_errdetect sr ff
+reg [7:0] rx_disperr_sr; // rx_disperr sr ff
+wire read_rx_status_1;
+
+reg [3:0] rx_phase_comp_fifo_error_c; // rx_phase_comp_fifo_error synced
+reg [3:0] rx_rlv_c; // rx_rlv synced to clk
+reg [3:0] rx_phase_comp_fifo_error_sr; // rx_phase_comp_fifo_error sr ff
+reg [3:0] rx_rlv_sr; // rx_rlv sr ff
+wire read_rx_status_2;
+
+reg [7:0] rx_rmfifodatainserted_c; // rx_rmfifodatainserted synced to clk
+reg [7:0] rx_rmfifodatadeleted_c; // rx_rmfifodatadeleted synced to clk
+reg [7:0] rx_rmfifodatainserted_sr;// rx_rmfifodatainserted sr ff
+reg [7:0] rx_rmfifodatadeleted_sr; // rx_rmfifodatadeleted sr ff
+wire read_rx_status_3;
+
+reg [3:0] rx_rmfifofull_c; // rx_rmfifo_full synced
+reg [3:0] rx_rmfifoempty_c; // rx_rmfifoempty synced to clk
+reg [3:0] rx_rmfifofull_sr; // rx_rmfifo_full sr ff
+reg [3:0] rx_rmfifoempty_sr; // rx_rmfifoempty sr ff
+wire read_rx_status_4;
+
+wire read_rx_status_5;
+
+reg [3:0] tx_phase_comp_fifo_error_c; // tx_phase_comp_fifo_error synced
+reg [3:0] tx_phase_comp_fifo_error_sr; // tx_phase_comp_fifo_error sr ff
+wire read_tx_status_0;
+
+// body --------------------------------------------------------------------
+
+//--- readdata output latch ---
+// For easier address debug shift back 2 bits
+assign addr = {address[4:0], 2'b00};
+
+always @(*) begin
+ case (addr)
+ HXAUI_CSR_RESET_ADDR:
+ readdata <= hxaui_csr_reset0q;
+ HXAUI_CSR_RX_CNTRL_ADDR:
+ readdata <= hxaui_csr_rx_cntrl0q;
+ HXAUI_CSR_TX_CNTRL_ADDR:
+ readdata <= hxaui_csr_tx_cntrl0q;
+ HXAUI_CSR_RX_STATUS_0_ADDR:
+ readdata <= hxaui_csr_rx_status_0;
+ HXAUI_CSR_RX_STATUS_1_ADDR:
+ readdata <= hxaui_csr_rx_status_1;
+ HXAUI_CSR_RX_STATUS_2_ADDR:
+ readdata <= hxaui_csr_rx_status_2;
+ HXAUI_CSR_RX_STATUS_3_ADDR:
+ readdata <= hxaui_csr_rx_status_3;
+ HXAUI_CSR_RX_STATUS_4_ADDR:
+ readdata <= hxaui_csr_rx_status_4;
+ HXAUI_CSR_TX_STATUS_0_ADDR:
+ readdata <= hxaui_csr_tx_status_0;
+ HXAUI_CSR_SIMULATION_FLAG_ADDR:
+ readdata <= hxaui_csr_simulation_flag0q;
+ default:
+ readdata <= 32'h0;
+ endcase // case (addr)
+end
+
+always @ (posedge clk or posedge reset) begin
+ if (reset) begin
+ hxaui_csr_reset0q <= 2'b0;
+ hxaui_csr_rx_cntrl0q <= 4'b0;
+ hxaui_csr_tx_cntrl0q <= 4'b0;
+ hxaui_csr_simulation_flag0q <= 1'b0;
+ end else begin
+ hxaui_csr_reset0q <= hxaui_csr_reset;
+ hxaui_csr_rx_cntrl0q <= hxaui_csr_rx_cntrl;
+ hxaui_csr_tx_cntrl0q <= hxaui_csr_tx_cntrl;
+ hxaui_csr_simulation_flag0q <= hxaui_csr_simulation_flag;
+ end
+end
+
+
+always @ (*) begin
+ hxaui_csr_reset = hxaui_csr_reset0q;
+ hxaui_csr_rx_cntrl = hxaui_csr_rx_cntrl0q;
+ hxaui_csr_tx_cntrl = hxaui_csr_tx_cntrl0q;
+ hxaui_csr_simulation_flag = hxaui_csr_simulation_flag0q;
+ if (write) begin
+ case (addr)
+ HXAUI_CSR_RESET_ADDR:
+ hxaui_csr_reset = writedata[1:0];
+ HXAUI_CSR_RX_CNTRL_ADDR:
+ hxaui_csr_rx_cntrl = writedata[3:0];
+ HXAUI_CSR_TX_CNTRL_ADDR:
+ hxaui_csr_tx_cntrl = writedata[3:0];
+ HXAUI_CSR_SIMULATION_FLAG_ADDR:
+ hxaui_csr_simulation_flag = writedata[0];
+ default:;
+ endcase // case (addr)
+ end
+end
+
+assign {r_rx_digitalreset, r_tx_digitalreset} = hxaui_csr_reset0q[1:0];
+assign r_rx_invpolarity[3:0] = hxaui_csr_rx_cntrl0q[3:0];
+assign r_tx_invpolarity[3:0] = hxaui_csr_tx_cntrl0q[3:0];
+assign simulation_flag = hxaui_csr_simulation_flag0q;
+
+//--- rx_status_0 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ rx_patterndetect_c <= rx_patterndetect;
+ rx_syncstatus_c <= rx_syncstatus;
+end
+
+assign read_rx_status_0 = read && (addr == HXAUI_CSR_RX_STATUS_0_ADDR);
+
+// sticky bits implementation -
+// set: status signal
+// reset: read from register
+// Set has precedence over reset
+//
+// s r q nq
+// ------------
+// 0 0 x q
+// 0 1 x 0
+// 1 x x 1
+//
+// nq <= s + qr'
+//
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ rx_patterndetect_sr <= 8'h0;
+ rx_syncstatus_sr <= 8'h0;
+ end else begin
+ rx_patterndetect_sr <= rx_patterndetect_c |
+ (rx_patterndetect_sr & {8{read_rx_status_0}});
+ rx_syncstatus_sr <= rx_syncstatus_c |
+ (rx_syncstatus_sr & {8{read_rx_status_0}});
+ end
+end
+
+assign hxaui_csr_rx_status_0 = {rx_patterndetect_sr, rx_syncstatus_sr};
+
+//--- rx_status_1 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ rx_errdetect_c <= rx_errdetect;
+ rx_disperr_c <= rx_disperr;
+end
+
+assign read_rx_status_1 = read && (addr == HXAUI_CSR_RX_STATUS_1_ADDR);
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ rx_errdetect_sr <= 8'h0;
+ rx_disperr_sr <= 8'h0;
+ end else begin
+ rx_errdetect_sr <= rx_errdetect_c |
+ (rx_errdetect_sr & {8{read_rx_status_1}});
+ rx_disperr_sr <= rx_disperr_c |
+ (rx_disperr_sr & {8{read_rx_status_1}});
+ end
+end
+
+assign hxaui_csr_rx_status_1 = {rx_errdetect_sr, rx_disperr_sr};
+
+//--- rx_status_2 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ rx_phase_comp_fifo_error_c <= rx_phase_comp_fifo_error;
+ rx_rlv_c <= rx_rlv;
+end
+
+assign read_rx_status_2 = read && (addr == HXAUI_CSR_RX_STATUS_2_ADDR);
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ rx_phase_comp_fifo_error_sr <= 4'h0;
+ rx_rlv_sr <= 4'h0;
+ end else begin
+ rx_phase_comp_fifo_error_sr <= rx_phase_comp_fifo_error_c |
+ (rx_phase_comp_fifo_error_sr & {4{read_rx_status_2}});
+ rx_rlv_sr <= rx_rlv_c |
+ (rx_rlv_sr & {4{read_rx_status_2}});
+ end
+end
+
+assign hxaui_csr_rx_status_2 = {rx_phase_comp_fifo_error_sr, rx_rlv_sr};
+
+//--- rx_status_3 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ rx_rmfifodatainserted_c <= rx_rmfifodatainserted;
+ rx_rmfifodatadeleted_c <= rx_rmfifodatadeleted;
+end
+
+assign read_rx_status_3 = read && (addr == HXAUI_CSR_RX_STATUS_3_ADDR);
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ rx_rmfifodatainserted_sr <= 8'h0;
+ rx_rmfifodatadeleted_sr <= 8'h0;
+ end else begin
+ rx_rmfifodatainserted_sr <= rx_rmfifodatainserted_c |
+ (rx_rmfifodatainserted_sr & {8{read_rx_status_3}});
+ rx_rmfifodatadeleted_sr <= rx_rmfifodatadeleted_c |
+ (rx_rmfifodatadeleted_sr & {8{read_rx_status_3}});
+ end
+end
+
+assign hxaui_csr_rx_status_3 = {rx_rmfifodatainserted_sr,
+ rx_rmfifodatadeleted_sr};
+
+//--- rx_status_4 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ rx_rmfifoempty_c <= rx_rmfifoempty;
+ rx_rmfifofull_c <= rx_rmfifofull;
+end
+
+assign read_rx_status_4 = read && (addr == HXAUI_CSR_RX_STATUS_4_ADDR);
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ rx_rmfifoempty_sr <= 4'h0;
+ rx_rmfifofull_sr <= 4'h0;
+ end else begin
+ rx_rmfifoempty_sr <= rx_rmfifoempty_c |
+ (rx_rmfifoempty_sr & {4{read_rx_status_4}});
+ rx_rmfifofull_sr <= rx_rmfifofull_c |
+ (rx_rmfifofull_sr & {4{read_rx_status_4}});
+ end
+end
+
+assign hxaui_csr_rx_status_4 = {rx_rmfifoempty_sr, rx_rmfifofull_sr};
+
+//--- tx_status_0 register: sticky - set by status, clear by read ---
+// The events latched are asynchronous to the Avalon clk, hence the user should
+// not assume that all the bits are set at the same time.
+
+// synchronize status signal to 'clk'
+always @ (posedge clk) begin
+ tx_phase_comp_fifo_error_c <= tx_phase_comp_fifo_error;
+end
+
+assign read_tx_status_0 = read && (addr == HXAUI_CSR_TX_STATUS_0_ADDR);
+
+always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ tx_phase_comp_fifo_error_sr <= 4'h0;
+ end else begin
+ tx_phase_comp_fifo_error_sr <= tx_phase_comp_fifo_error_c |
+ (tx_phase_comp_fifo_error_sr & {4{read_tx_status_0}});
+ end
+end
+
+assign hxaui_csr_tx_status_0 = tx_phase_comp_fifo_error_sr;
+
+
+endmodule // hxaui_csr
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/hxaui_csr_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/hxaui_csr_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..b4856c0cf54dc1a394a545937fa14fa28b03a1ce
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/hxaui_csr_h.sv
@@ -0,0 +1,155 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// (C) 2001-2011 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+///////////////////////////////////////////////////////////////////////////////
+//
+//
+// Description: Hard xaui control and status registers header file
+//
+// Authors: ishimony 12-Jun-2009
+//
+// Copyright (c) Altera Corporation 1997 - 2009
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+`timescale 1 ps / 1 ps
+
+package hxaui_csr_h;
+
+
+// address map
+localparam [11:0]ALT_PMA_CONTROLLER_ADDR =12'h080;
+localparam [11:0]ALT_PMA_CH_CONTROLLER_ADDR =12'h180;
+//localparam ALT_PMA_ADDR 12'h080
+localparam [11:0]ALT_RECONFIG_ANALOG_ADDR =12'h400;
+localparam [11:0]ALT_RECONFIG_OC_ADDR =12'h408;
+localparam [11:0]HXAUI_CSR_ADDR =12'h200;
+
+
+// registers address -------------------------------------------------------
+// preserve 7'h00 for indirection register (future implementation)
+localparam [6:0]HXAUI_CSR_RESET_ADDR =7'h04;
+localparam [6:0]HXAUI_CSR_RX_CNTRL_ADDR =7'h08;
+localparam [6:0]HXAUI_CSR_TX_CNTRL_ADDR =7'h0C;
+localparam [6:0]HXAUI_CSR_RX_STATUS_0_ADDR =7'h10;
+localparam [6:0]HXAUI_CSR_RX_STATUS_1_ADDR =7'h14;
+localparam [6:0]HXAUI_CSR_RX_STATUS_2_ADDR =7'h18;
+localparam [6:0]HXAUI_CSR_RX_STATUS_3_ADDR =7'h1C;
+localparam [6:0]HXAUI_CSR_RX_STATUS_4_ADDR =7'h20;
+localparam [6:0]HXAUI_CSR_TX_STATUS_0_ADDR =7'h24;
+localparam [6:0]HXAUI_CSR_SIMULATION_FLAG_ADDR =7'h28;
+
+// register bitmap ---------------------------------------------------------
+localparam [32:0]HXAUI_CSR_RESET_RX_DIGITAL =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RESET_TX_DIGITAL =32'h0000_0002;
+
+localparam [32:0]HXAUI_CSR_RX_CNTRL_INVPOLARITY_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_CNTRL_INVPOLARITY_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_CNTRL_INVPOLARITY_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_CNTRL_INVPOLARITY_3 =32'h0000_0008;
+
+localparam [32:0]HXAUI_CSR_TX_CNTRL_INVPOLARITY_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_TX_CNTRL_INVPOLARITY_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_TX_CNTRL_INVPOLARITY_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_TX_CNTRL_INVPOLARITY_3 =32'h0000_0008;
+
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_3 =32'h0000_0008;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_4 =32'h0000_0010;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_5 =32'h0000_0020;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_6 =32'h0000_0040;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_PATTERNDETECT_7 =32'h0000_0080;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_0 =32'h0000_0100;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_1 =32'h0000_0200;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_2 =32'h0000_0400;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_3 =32'h0000_0800;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_4 =32'h0000_1000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_5 =32'h0000_2000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_6 =32'h0000_4000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_0_SYNCSTATUS_7 =32'h0000_8000;
+
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_3 =32'h0000_0008;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_4 =32'h0000_0010;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_5 =32'h0000_0020;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_6 =32'h0000_0040;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_ERRDETECT_7 =32'h0000_0080;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_0 =32'h0000_0100;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_1 =32'h0000_0200;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_2 =32'h0000_0400;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_3 =32'h0000_0800;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_4 =32'h0000_1000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_5 =32'h0000_2000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_6 =32'h0000_4000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_1_DISPERR_7 =32'h0000_8000;
+
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_RLV_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_RLV_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_RLV_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_RLV_3 =32'h0000_0008;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_PHASE_COMP_FIFO_ERROR_0 =32'h0000_0010;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_PHASE_COMP_FIFO_ERROR_1 =32'h0000_0020;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_PHASE_COMP_FIFO_ERROR_2 =32'h0000_0040;
+localparam [32:0]HXAUI_CSR_RX_STATUS_2_PHASE_COMP_FIFO_ERROR_3 =32'h0000_0080;
+
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_3 =32'h0000_0008;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_4 =32'h0000_0010;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_5 =32'h0000_0020;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_6 =32'h0000_0040;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATADELETED_7 =32'h0000_0080;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_0 =32'h0000_0100;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_1 =32'h0000_0200;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_2 =32'h0000_0400;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_3 =32'h0000_0800;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_4 =32'h0000_1000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_5 =32'h0000_2000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_6 =32'h0000_4000;
+localparam [32:0]HXAUI_CSR_RX_STATUS_3_RMFIFODATAINSERTED_7 =32'h0000_8000;
+
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOFULL_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOFULL_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOFULL_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOFULL_3 =32'h0000_0008;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOEMPTY_0 =32'h0000_0010;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOEMPTY_1 =32'h0000_0020;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOEMPTY_2 =32'h0000_0040;
+localparam [32:0]HXAUI_CSR_RX_STATUS_4_RMFIFOEMPTY_3 =32'h0000_0080;
+
+localparam [32:0]HXAUI_CSR_TX_STATUS_0_PHASE_COMP_FIFO_ERROR_0 =32'h0000_0001;
+localparam [32:0]HXAUI_CSR_TX_STATUS_0_PHASE_COMP_FIFO_ERROR_1 =32'h0000_0002;
+localparam [32:0]HXAUI_CSR_TX_STATUS_0_PHASE_COMP_FIFO_ERROR_2 =32'h0000_0004;
+localparam [32:0]HXAUI_CSR_TX_STATUS_0_PHASE_COMP_FIFO_ERROR_3 =32'h0000_0008;
+
+localparam [32:0]HXAUI_CSR_SIMULATION_FLAG =32'h0000_0001;
+
+endpackage
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt4gxb_vo.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt4gxb_vo.v
new file mode 100644
index 0000000000000000000000000000000000000000..8ef56685da972b92f14186ad3e9f4325cbb498c9
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt4gxb_vo.v
@@ -0,0 +1,44084 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 2114304)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_dprio.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_dprio.v
new file mode 100644
index 0000000000000000000000000000000000000000..72342c0350fe6cec94b878f3a747c230666430ee
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_dprio.v
@@ -0,0 +1,210 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+PYEcV5WLbwIGuLOAfhWrwkseEsD4sE3vQ1cRwBEt2w4=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 8352)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_mutex_acq.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_mutex_acq.v
new file mode 100644
index 0000000000000000000000000000000000000000..724b5ba53e2106feb9ab923b2df6e714d830fc91
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_mutex_acq.v
@@ -0,0 +1,193 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 7520)
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+IQgN6YkosNlQmTcoDe3AWjcUwL4Um7Q3+3VTlRCMR8w=
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_pma_ch_controller_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_pma_ch_controller_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..f22b03e4b0b361896c232091a7ab96b3b8920a72
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_pma_ch_controller_tgx.v
@@ -0,0 +1,184 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 7072)
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+w+ld+hrZn5KDlwOAfwc86w==
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_pma_controller_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_pma_controller_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..5760024984a14c31d24e078458bdc5aa1f898cbe
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_pma_controller_tgx.v
@@ -0,0 +1,151 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 5488)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_pma_functions.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_pma_functions.sv
new file mode 100644
index 0000000000000000000000000000000000000000..ff457975bda064fc5d6d257532fc76dc68631ff1
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_pma_functions.sv
@@ -0,0 +1,88 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 2496)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_reset_ctrl_lego.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_reset_ctrl_lego.sv
new file mode 100644
index 0000000000000000000000000000000000000000..65b81465e061b87494a14045dc11a9a8eea218f6
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_reset_ctrl_lego.sv
@@ -0,0 +1,249 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 10208)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_reset_ctrl_tgx_cdrauto.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_reset_ctrl_tgx_cdrauto.sv
new file mode 100644
index 0000000000000000000000000000000000000000..00a639830a0bb4222b123eef29eef247c1c99ebd
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_reset_ctrl_tgx_cdrauto.sv
@@ -0,0 +1,245 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+oLasYAdsq8f97ncTkxg3+egoq+ico3SEndm+6N0S/wI=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 10032)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_pcs.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_pcs.v
new file mode 100644
index 0000000000000000000000000000000000000000..ff358dde1d5b8a25d12fcfae2f7a700abd6c7bf2
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_pcs.v
@@ -0,0 +1,337 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 14432)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_reset.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_reset.v
new file mode 100644
index 0000000000000000000000000000000000000000..a748396778126391702d3a8a1105ed8bc05b25ba
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_reset.v
@@ -0,0 +1,228 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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++ub5MURnVmAgfaFF1ksNiieaDRfYDpd0NY0OGkbQAK4=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 9184)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx.v
new file mode 100644
index 0000000000000000000000000000000000000000..8eec46463db28db1dcec4de675577e4c88500ee0
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx.v
@@ -0,0 +1,511 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 22800)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_8b10b_dec.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_8b10b_dec.v
new file mode 100644
index 0000000000000000000000000000000000000000..0415afc1007b173ee95ca75959eed746e351cada
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_8b10b_dec.v
@@ -0,0 +1,327 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 13968)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_channel_synch.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_channel_synch.v
new file mode 100644
index 0000000000000000000000000000000000000000..c7bcc962598d136ee59da64204f9e783e96e6339
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_channel_synch.v
@@ -0,0 +1,458 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 20240)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_deskew.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_deskew.v
new file mode 100644
index 0000000000000000000000000000000000000000..a93c9bb8978664ae35f6e5a0f5213a9fe0690932
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_deskew.v
@@ -0,0 +1,409 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 17888)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_deskew_channel.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_deskew_channel.v
new file mode 100644
index 0000000000000000000000000000000000000000..8ab72c41061c1a8e39c8046e66637bd48af869f7
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_deskew_channel.v
@@ -0,0 +1,170 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+v76PKvGTVEdEpX0Pib/vUjtXleGRNx49A0kzHsCfBgI=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 6400)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_deskew_ram.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_deskew_ram.v
new file mode 100644
index 0000000000000000000000000000000000000000..a4e9fa1d0821754e8089ef993e11ab1c75fb5be9
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_deskew_ram.v
@@ -0,0 +1,257 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+99dBDcxMFgfe67UyMaPWm/MjjzT3xRXbcgYr/9hcz6I=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 10608)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_invalid_code_det.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_invalid_code_det.v
new file mode 100644
index 0000000000000000000000000000000000000000..56f809c3cf9f68a6c824ae8e4aec6c0892c6bfc7
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_invalid_code_det.v
@@ -0,0 +1,131 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+Y4C/8+ljuJKkn2OwCzCMrBGOXb63VXw0QHullQ92rxw=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 4544)
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+dwVlSPOKHm8AE3YpXpiTPdil6e7QZ+NrVC+wQYcBgQs=
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_parity.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_parity.v
new file mode 100644
index 0000000000000000000000000000000000000000..284ea956003488f2f279ebba8913f4d1c2745a6b
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_parity.v
@@ -0,0 +1,145 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+W95L46Xe2Yfj23OF/Ssxqe6XQRn08hjWNEbptkV7dFI=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 5200)
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+kDwR+LSiXUtUmiS7wgHXmw==
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_parity_4b.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_parity_4b.v
new file mode 100644
index 0000000000000000000000000000000000000000..e885d6f34b785090df6b220de5ab9b55f00d9b2f
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_parity_4b.v
@@ -0,0 +1,123 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+NZ7e0ieUI6mC0WQniwlFcy1zBYMLZ23q/ZErokNVi7ITcktA0MnbkXzUQebp6MFb
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+AexvDWgo0oytQURdKkl3C/4LWqVnv2oQEKdYLvZ6qWg=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 4144)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_parity_6b.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_parity_6b.v
new file mode 100644
index 0000000000000000000000000000000000000000..563d2afdadf3351bee4ea8ae03d77b6034548550
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_parity_6b.v
@@ -0,0 +1,129 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 4464)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_rate_match.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_rate_match.v
new file mode 100644
index 0000000000000000000000000000000000000000..9adbd094189249fd9da5f0565ea03128943e8645
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_rate_match.v
@@ -0,0 +1,511 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 22768)
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+3Dz8BDQLKsSmtGX+x3e1iQ==
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_rate_match_ram.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_rate_match_ram.v
new file mode 100644
index 0000000000000000000000000000000000000000..687271d51ae4f364be4a7331fbfdca217810f84d
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_rate_match_ram.v
@@ -0,0 +1,261 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 10800)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_rl_chk_6g.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_rl_chk_6g.v
new file mode 100644
index 0000000000000000000000000000000000000000..dd903812c31f671525c77feab56e191c4a59bc38
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_rl_chk_6g.v
@@ -0,0 +1,448 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+jADwgeNuxVYaRnPszw6KUth6E3wfuYDYS1wxc5krAWQ=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 19760)
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+yhqd229168VtbWGgyRRGfSESGhPZlxvPtf7OBHz6Adg=
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_sm.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_sm.v
new file mode 100644
index 0000000000000000000000000000000000000000..2f6d6471cac2fbba91c35be8283022f4872190b0
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_sm.v
@@ -0,0 +1,893 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 41120)
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+ldrUGYKhzJCeEQwvqJ73CrfaYXXZwS8xEQXZWXfDauU=
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_tx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_tx.v
new file mode 100644
index 0000000000000000000000000000000000000000..725cc141e3a74f7056cff370df9ac54192bc0c4e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_tx.v
@@ -0,0 +1,169 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 6368)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_tx_8b10b_enc.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_tx_8b10b_enc.v
new file mode 100644
index 0000000000000000000000000000000000000000..1258e0c5a9f39437f4eb906cd9cc49d0fdc843c2
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_tx_8b10b_enc.v
@@ -0,0 +1,228 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 9216)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_tx_idle_conv.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_tx_idle_conv.v
new file mode 100644
index 0000000000000000000000000000000000000000..4170115b121972d5988ba996b7bfc76a161423a4
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_soft_xaui_tx_idle_conv.v
@@ -0,0 +1,785 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 35952)
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+Oh/jr7i2fh7//BssgewWmvuxi83OnqQfVfVxSrK0yiwo1zlPa2eeI+9HXrvJcLvL
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_arbiter.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_arbiter.sv
new file mode 100644
index 0000000000000000000000000000000000000000..9201fe9392a1f83a96bded3635bdcecbf1c3cc31
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_arbiter.sv
@@ -0,0 +1,100 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+kzr+GHJF6c8r2Ktqgeo7jbHeqse+1y5i2fQWwEb1cSP+08nAoqAy6OVmlxJGDc1r
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+00Re0NHMdK06PlP+94zS3uLQr1Ofr0PoWzK8LhRxtCc=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 3056)
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+aL3Ui9weC4EsnZ1FC/9DG/Low/lsOsu2t4c+h9C9nEo=
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_common.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_common.sv
new file mode 100644
index 0000000000000000000000000000000000000000..05d47a63ff795a780953a7207b4cd30623e546a1
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_common.sv
@@ -0,0 +1,244 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+goXNjNIgAuOaUEswCAVhKgi/FLDKtO5SWHhudsQxwa0E9CiHm0eRs4dreCDCtIJ8
+V2IpE4BYoE1bOlmnsJwOxfJdbJhCBT63ZDpDpzcwSHgSOIWKU7nMck0Dv2AfX/V7
+QhXXDICUsIqys5tYQb4ggYhsHZVZUX4GWEDLbNdtR3Y=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 9984)
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+m0YBv/PupEy8/Xz/XHNXR+oJJodcIe3fkfZHfOs8KBY0UX3wM4izeyEK65lOOAyg
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_common_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_common_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..6c497c12da003abbeaacd57513e9aff063cbe2ea
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_common_h.sv
@@ -0,0 +1,108 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+TOWgEh7Q0ry2M5e2DMIblPJfQNlm8NM1EHMNgV/rtWM=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 3424)
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+W4DVx5ruiC47L9RN0oSqeQ==
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_pcs8g.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_pcs8g.sv
new file mode 100644
index 0000000000000000000000000000000000000000..de318f36893e8a7e31873670221476b68c5faed7
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_pcs8g.sv
@@ -0,0 +1,410 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+hKtkiaJ74+qkTf0+fDmyZIfPUgyFAJsboFHIVVUlqZZFnXRsSQL4NkzU5uPVVY1h
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+y3BTaUni+Hubn+8B3CLX7DKbNzrWIs4NXzOBv9RUmCY=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 17952)
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+G3ByFmuwBIzEN3lNvQFx2VutiTLZCCVPkqqLRTpacnEvsoJUC39S3YbgrjGYLpj5
+3FCxxDuuztJ/nJHeKy6A4VrLuLz5KIv9lR6Jgf6183nMib86qt2MT9bvtg+f9WPs
+YTTHCTMk9bqVc5f5bZsX4DsQ2PdoU1KMbI6VoVJXS2lGaahLHjY88OzqBz761loU
+rvhas1j58Plbo4FsRtnOoscvOk+xg5M3P9YbPQLEsUXFUiUbuR42jP45gmE7ELyh
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+j3nsHELJHf0vuDTMU6cneDO9anSxnrgJs4WkOYlGGWUDWuD+jtD0NKr3HQWuVVIe
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_pcs8g_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_pcs8g_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..d1ec34e1c710d34265ab9b98577b6f3f498c0cc5
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_pcs8g_h.sv
@@ -0,0 +1,76 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+kLZr13QLguIANDar9SulmA7hFf2aqzrtRVOIklmFZVPadAAhrxt4F23s/2iYEhJH
++o8fhXosOcAZiHnzyKq07f1YCEkRAItSnQrsYPF8j0hJhn1DM/alSlcavHIXmH2P
+FdI/HIJng41AFhkct+wjpUFz+wmpC/3EdHZZzPUP+nQ=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 1920)
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+GiZqz2Spxk9oi0TZXSKPEan+aOW6Cics2Wvjm12oVHFgcvH/elqkI3BmcnSEC7Ia
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_selector.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_selector.sv
new file mode 100644
index 0000000000000000000000000000000000000000..801b179409a7cbbdf6cad6c84fadcfaff3a6c41c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_csr_selector.sv
@@ -0,0 +1,131 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+IAPQvGS2WEQvamIfKh4zuSYeYfJ+NmmR23TMuspMGcjny+aZb4gLlECCuBo5Xd7j
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+8cWLA40AHzbLMzNX3PnyyyYLRZUJHUVPGGQDK288CtI=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 4544)
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+J+51f6EJRoOzVrxlrV7aHDXmGLwEzcys+ZVHZcMwkl+v4pCDurQjAcfpdLu7L/EW
+w4+T6S3/WJT0rkue0vwclU9pX0rKS7MzzCNvKlby51n1po2TEC4y2HSzvj7j4LQG
+rZN0bhbrY7uRG/C9CmFUNmNR9KhYLdFSVMNkOEac8QguOBr+Fpk77biFuCG1yVLf
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+HOZjIbPnkEBDWs9ZEZUKrEvQPKmTDZaaxFatmEK2+jc=
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_m2s.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_m2s.sv
new file mode 100644
index 0000000000000000000000000000000000000000..6fbcca4dbd02d0124af931a01c68765c9fe60ba9
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_m2s.sv
@@ -0,0 +1,90 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+HS+I8naY9DPGVQxPrII2Frh1VJghpPubC5j5F0w2tZKpYlOfA9o38NqMkGQvPRYb
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+Smz71GMpWXutaeBQTP3kCIKoCml/V7N7Z/k/VCdY0lg=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 2592)
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+iDgazn1HrvrsnvccMo9FRJm7jmQycvGFtXczDfOHUdwfsjo8NfHeKoAVtCpGnJEt
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec.sv
new file mode 100644
index 0000000000000000000000000000000000000000..708f65dd161bd7db8620762a6f22c0aa9e2a3ab1
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec.sv
@@ -0,0 +1,122 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+AX6zMckUnfpntazoc0TCuNuo1AHRijgpQG03o7u16pJdmMpU47d/qW2Nsw7ZBnII
+aFZgSRUXaGiOMhOVI0jI/kDrrYBt8uQkDRfB0q8WTaIkRxDIovL3s7yVLnhOohP2
+m3n1EU+tPJ6e1Bo0jc/upKK4zeA4L/m/zhi0BBbmE18=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 4112)
+ghDx/HYtD8BDaeFqUmn37HGAHk50x7bTi5Gr3rbUQu5qecG4d5c7T6rmEUqrFitj
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec_phyreconfig.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec_phyreconfig.sv
new file mode 100644
index 0000000000000000000000000000000000000000..d6e371c82c763fbe90f5485fd1aae9abf8d49b07
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec_phyreconfig.sv
@@ -0,0 +1,141 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 5024)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec_xaui.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec_xaui.sv
new file mode 100644
index 0000000000000000000000000000000000000000..4bcb992c45e33b9053483c24b99e6e61338c37c6
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec_xaui.sv
@@ -0,0 +1,167 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 6256)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_analog.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_analog.sv
new file mode 100644
index 0000000000000000000000000000000000000000..2309672b77ddf40b1462ae30705167bbd20aa885
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_analog.sv
@@ -0,0 +1,185 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 7136)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_analog_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_analog_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..e586ed1dd708be01feb654b2d017ce915dbaded8
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_analog_tgx.v
@@ -0,0 +1,795 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 36432)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_basic_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_basic_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..c8025cdc92b5ddad3fe624f477ad4a8466f90142
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_basic_tgx.v
@@ -0,0 +1,375 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 16240)
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+b7RxtNIMCTZt6Vg7HQ8p+g==
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_dfe_tgx.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_dfe_tgx.sv
new file mode 100644
index 0000000000000000000000000000000000000000..4931754e1edddd25d71e21e04fc484b42ab66de9
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_dfe_tgx.sv
@@ -0,0 +1,386 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 16800)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_eyemon_tgx.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_eyemon_tgx.sv
new file mode 100644
index 0000000000000000000000000000000000000000..694a5541e8a54d5afd1a0a675e127d8547df47c2
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_eyemon_tgx.sv
@@ -0,0 +1,395 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 17216)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..22240cbc9f16d013a29b1a9607b2afe16b218fe2
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_h.sv
@@ -0,0 +1,427 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 18768)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_offset_cancellation.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_offset_cancellation.sv
new file mode 100644
index 0000000000000000000000000000000000000000..0e1898bbb251fd03e589fde44d76c3ff4645985e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_offset_cancellation.sv
@@ -0,0 +1,214 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 8528)
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+tClSSjNKRkyGJGLwb0cdEKwZBXsKopwaWGcZhUXuwCE=
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_offset_cancellation_tgx.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_offset_cancellation_tgx.v
new file mode 100644
index 0000000000000000000000000000000000000000..fe29ab815570c89edf71a3e5a9616e4f34bcda21
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_offset_cancellation_tgx.v
@@ -0,0 +1,452 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 19968)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_siv.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_siv.sv
new file mode 100644
index 0000000000000000000000000000000000000000..b458a1f9ed061719de8ae09f3183d825ad0cbfd8
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_siv.sv
@@ -0,0 +1,388 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 16880)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_resync.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_resync.sv
new file mode 100644
index 0000000000000000000000000000000000000000..b1e6c11c30214d200e1e3e3c547f9f71b640545d
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/alt_xcvr_resync.sv
@@ -0,0 +1,125 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+NU7nEWuiODNrD7ptbammFGF4LSdELgrfDkeOhWmedaA=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 4240)
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+K7fcKFVqylEaw5PEizuX8A==
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/altera_wait_generate.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/altera_wait_generate.v
new file mode 100644
index 0000000000000000000000000000000000000000..ef008094f669832fc7edb6f42638490009bac90d
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/altera_wait_generate.v
@@ -0,0 +1,76 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+NTatKXD2vaAi56tZ5DimfYyEBW+JNwsK30ioUF5+LXwIzabb/re9ghIliAm41Kbj
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+Ebf5ievExkme2joWSqIoSRCeN2RIunNQaCIQ1jdUM7A=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 1888)
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++vCKN0rkhBcVPddr9EUQdw==
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/altera_xcvr_functions.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/altera_xcvr_functions.sv
new file mode 100644
index 0000000000000000000000000000000000000000..bb92d08605ea29f7d2b2458456ce2000eb9e6a44
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/altera_xcvr_functions.sv
@@ -0,0 +1,666 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+pRrIJQeGz7EPVbooxqUk8+gHN8vsYnsYQxfwYXc6oQ3OyWm0ShI/K9+U/IAxgVtE
+ja0fzV+9+qf1S8k1QWRuP/ccmMIIgIxN1JCLYUT2EWoRPwjYnPmqaSpa7iYJp37Z
+nZ1qLsgZjHQCmBZQO3ECvHA7fcd5oe6LXuKiYuNnCyY=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 30240)
+3U/nAmvn/4dun14Bm8hyJ2+5EOFAHvqCE96SC37PMi7FnzZf9e+6Ne6MjP4ZzgIv
+Id8ybIeiFEHMreleT3N9q9lGCyyP4yY+Ze97w+RllbhBV8PmINvA3NFPHFXV8dx3
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/altera_xcvr_xaui.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/altera_xcvr_xaui.sv
new file mode 100644
index 0000000000000000000000000000000000000000..199fefd6d98f060aac8d275e961846eb91c1ace9
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/altera_xcvr_xaui.sv
@@ -0,0 +1,643 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 29136)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/hxaui_csr.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/hxaui_csr.sv
new file mode 100644
index 0000000000000000000000000000000000000000..691fc06c19c7976aec73e754c81780de616faafe
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/hxaui_csr.sv
@@ -0,0 +1,353 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+BEoanZH/TfnD97QSMY2/A9VAmXxKgnRQfGOZjK/uhJF3A/G04zIXIPBpErpt+b3P
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+8nymk6WmKIb3qNlUoGaqdtbjMaHliFW+uo8WahUFRE8=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 15200)
+hesWwhJly8dKXNL852ywc9+S576nkfjyxvdWzhpXUSCYKHefJGueVndUmR9ejPtk
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/hxaui_csr_h.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/hxaui_csr_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..03d1dfb48ea29b6a691b63e7caa467a92364ef9e
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/hxaui_csr_h.sv
@@ -0,0 +1,238 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 9664)
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+kjrFiQ9LMdSCB8ov1KaFWw==
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/l_modules.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/l_modules.v
new file mode 100644
index 0000000000000000000000000000000000000000..06edd88cca369f548fd979ee1f65fe8a4fd730cf
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/l_modules.v
@@ -0,0 +1,98 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+RhZ6QTU6+yR1Ty9wbcjuC2Or7ypWbgdiK3nljlSyFBI=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 2960)
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+mbzW6pwG02AlSIXCMQ+YMe27q4Hz9JxpkEdYIY7S3t3qSvRKnZUf2QgaDUPOtbmF
+vb2BT41J99c3eYfvvz02gJeEy4B/F0EzL5eidO8RiIjd3DcqKCSXxNyFPGdtXYFz
+Ij3tHpL71pnQLkvftU/Yq4iNtUJe+xpcnwhiwSZQ7DcmXSIs3zwpOdJbiyX4VS50
+8LIBWeIb/ehNx6abzTGoOzpOo0zqBG718p4t6OYMeICTGfhnudBdDMHWAZB5BQG8
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+WzyouO72rAwJ7Avu5L1DrEASPiH9BVLtgkjVMYkLIU3uTLsNfmLUe/hn8KpfWOqL
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+TZLSTxJH7oFhTcYgOqYkR67qmI/nZfq7foaVjI1H/Ns=
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/serdes_4_unit_lc_siv.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/serdes_4_unit_lc_siv.v
new file mode 100644
index 0000000000000000000000000000000000000000..ad7d268d0f5359cc54ae7f2c1410ec2d7fe770bf
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/serdes_4_unit_lc_siv.v
@@ -0,0 +1,1855 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+QXeuB5YSgOHddsZLV6GdIqcXIRnWr3s8KotOVEbYL2OpkhvuSJ6ywoEtxxxJSqqf
+TKd6YVZh84S/Xe6MA6SAnk6LjURiVXUxNnVjEYgbnXvvl3QtfzIOYar8V29nkEDB
+PdNqSzZKZ3MCt8nNhT4WyYDOzs8ns3HPnE92BjziiOk=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 87280)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/serdes_4_unit_siv.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/serdes_4_unit_siv.v
new file mode 100644
index 0000000000000000000000000000000000000000..7163027911d8a18d8230d9792467c195c6c04697
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/serdes_4_unit_siv.v
@@ -0,0 +1,1876 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 88304)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/serdes_4unit.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/serdes_4unit.v
new file mode 100644
index 0000000000000000000000000000000000000000..141cc7a3dd505dc7f3e82c308104f63f8418b708
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/serdes_4unit.v
@@ -0,0 +1,488 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 21664)
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+D32GkjPWyFKiSWqBqzkQBA==
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/siv_xcvr_low_latency_phy_nr.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/siv_xcvr_low_latency_phy_nr.sv
new file mode 100644
index 0000000000000000000000000000000000000000..0a79ceb612c38b4b8aaf4495610e5d7016207aec
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/siv_xcvr_low_latency_phy_nr.sv
@@ -0,0 +1,436 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 19184)
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+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/siv_xcvr_xaui.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/siv_xcvr_xaui.sv
new file mode 100644
index 0000000000000000000000000000000000000000..283b5136ac768134fe20afe4e80f18be4a1785bc
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/siv_xcvr_xaui.sv
@@ -0,0 +1,706 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 32144)
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+W3uDWqXAAdWYk3igkpmZd6zw3qntZ48kvXPAMIObw7s=
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/sxaui.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/sxaui.v
new file mode 100644
index 0000000000000000000000000000000000000000..3da21bae3ee5bf175c5e28c87d8589fe96b8ea8d
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor/sxaui.v
@@ -0,0 +1,252 @@
+// Copyright (C) Altera Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Altera and is being provided
+// in accordance with and subject to the protections of the
+// applicable Altera Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Altera
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other
+// applicable license agreement, including, without limitation,
+// that your use is for the sole purpose of simulating designs
+// for use exclusively in logic devices manufactured by Altera and sold
+// by Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details. Altera products and
+// services are protected under numerous U.S. and foreign patents,
+// maskwork rights, copyrights and other intellectual property laws.
+// Altera assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 11.1sp2 linux32 Build 259 01/26/2012
+// encrypted_file_type : mentor_tagged
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6c"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
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+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 10352)
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+goeR40PJp2zUmGW91ae2NIaY0h5baiNsDNM427EC5Ns=
+`pragma protect end_protected
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor_files.txt b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor_files.txt
new file mode 100644
index 0000000000000000000000000000000000000000..39c052374ca76eb6ee2614d410f7eab733c163bd
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/mentor_files.txt
@@ -0,0 +1,59 @@
+./mentor/altera_xcvr_functions.sv
+./mentor/alt_pma_functions.sv
+./mentor/altera_xcvr_xaui.sv
+./mentor/hxaui_csr_h.sv
+./mentor/hxaui_csr.sv
+./mentor/alt_xcvr_mgmt2dec_phyreconfig.sv
+./mentor/alt_xcvr_mgmt2dec_xaui.sv
+./mentor/alt_pma_ch_controller_tgx.v
+./mentor/alt_pma_controller_tgx.v
+./mentor/alt_reset_ctrl_lego.sv
+./mentor/alt_reset_ctrl_tgx_cdrauto.sv
+./mentor/alt_xcvr_resync.sv
+./mentor/alt_xcvr_csr_common_h.sv
+./mentor/alt_xcvr_csr_common.sv
+./mentor/alt_xcvr_csr_pcs8g_h.sv
+./mentor/alt_xcvr_csr_pcs8g.sv
+./mentor/alt_xcvr_csr_selector.sv
+./mentor/alt_xcvr_mgmt2dec.sv
+./mentor/altera_wait_generate.v
+./mentor/alt_soft_xaui_pcs.v
+./mentor/alt_soft_xaui_reset.v
+./mentor/alt_soft_xaui_rx.v
+./mentor/alt_soft_xaui_rx_8b10b_dec.v
+./mentor/alt_soft_xaui_rx_channel_synch.v
+./mentor/alt_soft_xaui_rx_deskew.v
+./mentor/alt_soft_xaui_rx_deskew_channel.v
+./mentor/alt_soft_xaui_rx_deskew_ram.v
+./mentor/alt_soft_xaui_rx_invalid_code_det.v
+./mentor/alt_soft_xaui_rx_parity.v
+./mentor/alt_soft_xaui_rx_parity_4b.v
+./mentor/alt_soft_xaui_rx_parity_6b.v
+./mentor/alt_soft_xaui_rx_rate_match.v
+./mentor/alt_soft_xaui_rx_rate_match_ram.v
+./mentor/alt_soft_xaui_rx_rl_chk_6g.v
+./mentor/alt_soft_xaui_rx_sm.v
+./mentor/alt_soft_xaui_tx.v
+./mentor/alt_soft_xaui_tx_8b10b_enc.v
+./mentor/alt_soft_xaui_tx_idle_conv.v
+./mentor/l_modules.v
+./mentor/serdes_4_unit_lc_siv.v
+./mentor/serdes_4_unit_siv.v
+./mentor/serdes_4unit.v
+./mentor/sxaui.v
+./mentor/siv_xcvr_low_latency_phy_nr.sv
+./mentor/siv_xcvr_xaui.sv
+./mentor/alt4gxb_vo.v
+./mentor/alt_xcvr_reconfig_h.sv
+./mentor/alt_xcvr_reconfig_siv.sv
+./mentor/alt_xcvr_reconfig_analog.sv
+./mentor/alt_xcvr_reconfig_analog_tgx.v
+./mentor/alt_xcvr_reconfig_offset_cancellation.sv
+./mentor/alt_xcvr_reconfig_offset_cancellation_tgx.v
+./mentor/alt_xcvr_reconfig_eyemon_tgx.sv
+./mentor/alt_xcvr_reconfig_dfe_tgx.sv
+./mentor/alt_xcvr_reconfig_basic_tgx.v
+./mentor/alt_mutex_acq.v
+./mentor/alt_dprio.v
+./mentor/alt_xcvr_arbiter.sv
+./mentor/alt_xcvr_m2s.sv
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/modelsim_sim_script_example.tcl b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/modelsim_sim_script_example.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..64f09857ea3ab03830ff65cce67d58db4b3c3eed
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/modelsim_sim_script_example.tcl
@@ -0,0 +1,380 @@
+# (C) 2001-2012 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and other
+# software and tools, and its AMPP partner logic functions, and any output
+# files any of the foregoing (including device programming or simulation
+# files), and any associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License Subscription
+# Agreement, Altera MegaCore Function License Agreement, or other applicable
+# license agreement, including, without limitation, that your use is for the
+# sole purpose of programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+
+###########################################
+#
+# This is an example file for compilation/simulation of 10GBASER-R PHY instance in Modelsim
+#
+# You can modify this script and use it to compile/simulate your design depending on
+# the following Modelsim license options:
+# (1) Mixed language license
+# - Top-level PHY IP variant can be in Verilog or VHDL
+# - Underlying PHY IP files are in plaintext Verilog
+# - Testbench can be in Verilog or VHDL
+#
+# (2) Non-mixed language license
+# (a) Verilog Only:
+# - Top-level PHY IP variant should be in Verilog
+# - Underlying PHY IP files are in plaintext Verilog
+# - Testbench should be in Verilog
+#
+# (b) VHDL Only:
+# - Top-level PHY IP variant should be in VHDL
+# - Underlying PHY IP files are in encrypted Verilog
+# - Testbench should be in VHDL
+#
+# (3) Quartus encrypted some files for copyright. Those file will be encrypted for different simulator
+#
+# Please do the following changes in this script in order to use it:
+# - Set the language (verilog or vhdl) of the generated PHY IP variant
+# - Set your top-level PHY IP variant name
+# - Set your top-level testbench name
+# - Compile your other design files and your testbench. You would use vlog or vcom according
+# to the language of your design files/testbench and your Modelsim license.
+#
+# Note that the PHY IP files are correctly compiled in this script according to the the
+# "language" variable you set.
+#
+##############################################################################################
+
+set QUARTUS_ROOTDIR $env(QUARTUS_ROOTDIR)
+#################################################################################
+##
+## Set your language, simulator and top level design name here
+## e.g. vsim -c -do "do ./test_sim/modelsim_example_script.tcl verilog stratixiv modelsim test test_tst hard"
+##
+#################################################################################
+# language = verilog (verilog variant of the PHY IP) or vhdl (vhdl variant of the PHY IP)
+# defaulted to verilog
+set language $1
+if {$language != "verilog" && $language != "vhdl"} {
+ echo "invalid setting for language: $language. valid settings are verilog and vhdl"
+ exit
+}
+
+# family =
+# defaulted to stratixv
+set family $2
+if {$family != "stratixiv" && $family != "stratixv" && $family != "cycloneiv" && $family != "arriaiigx" && $family != "arriaiigz" && $family != "hardcopyiv"} {
+ echo "invalid setting for family: $family. valid settings are stratixiv,stratixv,cycloneiv,arriaiigx,arriaiigz,hardcopyiv"
+ exit
+}
+
+# simulator = modelsim or VCS
+# defaulted to modelsim
+# This file not support VCS yet, you can use this file as reference for VCS
+set simulator $3
+if {$simulator != "modelsim"} {
+ echo "invalid setting for simulator: $simulator. valid settings are modelsim"
+ exit
+}
+## Set your top level design name here
+##set dut_name <top level design name as generted in Quartus or Qsys>
+set dut_name $4
+if {$dut_name == ""} {
+ echo "Missing top level design name: $dut_name"
+}
+## Set your test bench name here
+##set tb_name <test bench>
+set tb_name $5
+if {$tb_name == ""} {
+ echo "Missing test bench name: $tb_name"
+}
+
+## Set your XAUI type
+##set xaui_type soft or hard
+set xaui_type $6
+if {$xaui_type == ""} {
+ echo "Missing test xaui_type: $xaui_type"
+}
+
+puts " simulator=$simulator"
+puts " language=$language"
+puts " family=$family"
+#################################################################################
+## Set directory path according to simulator
+## unenc_file_dir for Quartus unecrypted files
+## enc_file_dir is for Quartus ecrypted files
+## This file only support modelsim simulation. You can use the following path
+## as reference of other simulator
+#################################################################################
+## Modelsim Verilog/Modelsim VHDL with Mixed language license
+if { $simulator == "modelsim" } {
+ set enc_file_dir ./${dut_name}_sim/altera_xcvr_xaui/mentor
+ if {$language == "verilog"} {
+ set unenc_file_dir ./${dut_name}_sim/altera_xcvr_xaui
+ } else {
+ ## Modelsim-AE / Models
+ set unenc_file_dir ./${dut_name}_sim/altera_xcvr_xaui/mentor
+ }
+
+} elseif { $simulator == "VCS" } {
+ set unenc_file_dir ${dut_name}_sim
+ set enc_file_dir $dut_name_sim/synopsys
+
+} elseif { $simulator == "Aldec" } {
+ set unenc_file_dir ${dut_name}_sim
+ set enc_file_dir $dut_name_sim/Aldec
+
+} elseif { $simulator == "VCS" } {
+ set unenc_file_dir ./${dut_name}_sim
+ set enc_file_dir ./${dut_name}_sim/synopsys
+
+} elseif { $simulator == "NCSIM" } {
+ set unenc_file_dir ./${dut_name}_sim
+ set enc_file_dir ./${dut_name}_sim/cadence
+
+}
+
+exec rm -rf work
+vlib work
+puts " unenc_file_dir=$unenc_file_dir"
+puts " enc_file_dir=$enc_file_dir"
+
+###########################################
+# Library files
+###########################################
+if {$language == "verilog"} {
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/220model.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/altera_primitives.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/sgate.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/altera_mf.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/stratixiv_hssi_atoms.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/stratixii_atoms.v
+
+ if {$family == "stratixiv" || $family == "arriaiigx" || $family == "arriaiigz" || $family == "hardcopyiv"} {
+ ###########################################
+ # Stratix IV library files
+ ###########################################
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/stratixiv_hssi_atoms.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/stratixiv_atoms.v
+ vlog $QUARTUS_ROOTDIR/libraries/megafunctions/alt_cal_c3gxb.v
+ }
+ if {$family == "cycloneiv"} {
+ ###########################################
+ # Cyclone IV library files
+ ###########################################
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/cycloneiv_hssi_atoms.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/cycloneiv_atoms.v
+ vlog $QUARTUS_ROOTDIR/libraries/megafunctions/alt_cal_c3gxb.v
+ }
+ if {$family == "stratixv"} {
+ ###########################################
+ # Stratix V library files
+ ###########################################
+ vlog -sv $QUARTUS_ROOTDIR/eda/sim_lib/altera_lnsim.sv
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/mentor/stratixv_atoms_ncrypt.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/stratixv_atoms.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/mentor/stratixv_hssi_atoms_ncrypt.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/stratixv_hssi_atoms.v
+ }
+} else {
+ vmap altera work
+ vmap altera_mf work
+ vmap lpm work
+ vmap sgate work
+ vmap stratixiv_hssi work
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/220pack.vhd
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/220model.vhd
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/altera_primitives_components.vhd
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/altera_primitives.vhd
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/sgate_pack.vhd
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/sgate.vhd
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/altera_mf_components.vhd
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/altera_mf.vhd
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/stratixii_atoms.vhd
+
+ if {$family == "stratixiv" || $family == "arriaiigx" || $family == "arriaiigz"} {
+ ###########################################
+ # Stratix IV library files
+ ###########################################
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/stratixiv_hssi_components.vhd
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/stratixiv_hssi_atoms.vhd
+ vcom $QUARTUS_ROOTDIR/libraries/megafunctions/alt_cal_c3gxb.vhd
+ }
+ if {$family == "cycloneiv"} {
+ ###########################################
+ # Cyclone IV library files
+ ###########################################
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/cycloneiv_hssi_components.vhd
+ vcom $QUARTUS_ROOTDIR/eda/sim_lib/cycloneiv_hssi_atoms.vhd
+ vcom $QUARTUS_ROOTDIR/libraries/megafunctions/alt_cal_c3gxb.vhd
+ }
+ if {$family == "stratixv"} {
+ ###########################################
+ # Stratix V library files
+ ###########################################
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/mentor/stratixv_atoms_for_vhdl.v
+ vlog $QUARTUS_ROOTDIR/eda/sim_lib/mentor/stratixv_hssi_atoms_for_vhdl.v
+ }
+}
+
+if {$xaui_type == "hard" } {
+ vlog -sv $unenc_file_dir/alt_xcvr_csr_common_h.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_csr_common.sv
+ vlog $unenc_file_dir/alt_dprio.v
+ vlog $unenc_file_dir/alt_mutex_acq.v
+ vlog $unenc_file_dir/alt_pma_ch_controller_tgx.v
+ vlog $unenc_file_dir/alt_pma_controller_tgx.v
+ vlog -sv $unenc_file_dir/altera_xcvr_functions.sv
+ vlog -sv $unenc_file_dir/alt_reset_ctrl_lego.sv
+ vlog -sv $unenc_file_dir/alt_reset_ctrl_tgx_cdrauto.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_resync.sv
+ vlog -sv $unenc_file_dir/altera_xcvr_xaui.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_arbiter.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_m2s.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_mgmt2dec_phyreconfig.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_mgmt2dec_xaui.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_csr_pcs8g_h.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_csr_pcs8g.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_csr_selector.sv
+ vlog $unenc_file_dir/altera_wait_generate.v
+ vlog $unenc_file_dir/hxaui.v
+ vlog $unenc_file_dir/hxaui_csr_h.sv
+ vlog +incdir+$unenc_file_dir $unenc_file_dir/hxaui_csr.sv
+ if {$family == "stratixiv" || $family == "arriaiigx" || $family == "arriaiigz" || $family == "hardcopyiv"} {
+ ###########################################
+ # Use this section for Stratix IV/Arria II GX Hard XAUI
+ ###########################################
+ vlog -sv $unenc_file_dir/siv_xcvr_xaui.sv
+ vlog $unenc_file_dir/alt_dprio.v
+ vlog $unenc_file_dir/alt_xcvr_reconfig*.v
+ vlog -sv $unenc_file_dir/alt_xcvr_reconfig*.sv
+ vlog $unenc_file_dir/hxaui_alt4gxb.v
+ }
+ if {$family == "cycloneiv"} {
+ ###########################################
+ # Use this section for Cyclone IV GX Hard XAUI
+ ###########################################
+ vlog $unenc_file_dir/civ_xcvr_xaui.v
+ vlog $unenc_file_dir/alt_xcvr_reconfig*.v
+ vlog -sv $unenc_file_dir/alt_xcvr_reconfig*.sv
+ vlog $unenc_file_dir/hxaui_alt_c3gxb.v
+ }
+ } else {
+ vlog -sv $unenc_file_dir/alt_xcvr_csr_common_h.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_csr_common.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_csr_pcs8g_h.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_csr_pcs8g.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_csr_selector.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_m2s.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_mgmt2dec_phyreconfig.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_mgmt2dec_xaui.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_arbiter.sv
+ vlog -sv $unenc_file_dir/altera_xcvr_functions.sv
+ vlog $enc_file_dir/alt_soft_xaui_pcs.v
+ vlog $enc_file_dir/alt_soft_xaui_reset.v
+ vlog $enc_file_dir/alt_soft_xaui_rx.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_8b10b_dec.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_channel_synch.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_deskew.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_deskew_channel.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_deskew_ram.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_invalid_code_det.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_parity.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_parity_4b.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_parity_6b.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_rate_match.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_rate_match_ram.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_rl_chk_6g.v
+ vlog $enc_file_dir/alt_soft_xaui_rx_sm.v
+ vlog $enc_file_dir/alt_soft_xaui_tx.v
+ vlog $enc_file_dir/alt_soft_xaui_tx_8b10b_enc.v
+ vlog $enc_file_dir/alt_soft_xaui_tx_idle_conv.v
+ vlog $enc_file_dir/l_modules.v
+ vlog $unenc_file_dir/hxaui_csr_h.sv
+ vlog +incdir+$unenc_file_dir $unenc_file_dir/hxaui_csr.sv
+ vlog $unenc_file_dir/sxaui.v
+ vlog -sv $unenc_file_dir/alt_reset_ctrl_lego.sv
+ vlog $unenc_file_dir/altera_wait_generate.v
+ vlog -sv $unenc_file_dir/altera_xcvr_xaui.sv
+ vlog -sv $unenc_file_dir/alt_reset_ctrl_tgx_cdrauto.sv
+ vlog -sv $unenc_file_dir/alt_xcvr_resync.sv
+ if {$family == "stratixiv" } {
+ ###########################################
+ # Use this section for Stratix IV Soft XAUI
+ ###########################################
+ vlog -sv $unenc_file_dir/siv_xcvr_xaui.sv
+ vlog $unenc_file_dir/alt4gxb_vo.v
+ vlog $unenc_file_dir/alt_mutex_acq.v
+ vlog $unenc_file_dir/alt_pma_ch_controller_tgx.v
+ vlog $unenc_file_dir/alt_pma_controller_tgx.v
+ vlog -sv $unenc_file_dir/alt_pma_functions.sv
+ vlog -sv $unenc_file_dir/siv_xcvr_low_latency_phy_nr.sv
+ vlog $unenc_file_dir/alt_dprio.v
+ vlog $unenc_file_dir/alt_xcvr_reconfig*.v
+ vlog -sv $unenc_file_dir/alt_xcvr_reconfig*.sv
+ } else {
+
+ ###########################################
+ # Use this section for Stratix V Soft XAUI
+ ###########################################
+
+ vlog -sv $unenc_file_dir/sv_xcvr_h.sv
+ vlog -sv $unenc_file_dir/sv_xcvr_xaui.sv
+ vlog -sv $unenc_file_dir/sv_xcvr_plls.sv
+ vlog $unenc_file_dir/alt_pma_ch_controller_tgx.v
+ vlog $unenc_file_dir/alt_pma_controller_tgx.v
+ vlog -sv $unenc_file_dir/alt_pma_functions.sv
+ vlog -sv $unenc_file_dir/sv_xcvr_low_latency_phy_nr.sv
+ vlog -sv $unenc_file_dir/sv_xcvr_avmm.sv
+ vlog -sv $unenc_file_dir/sv_xcvr_avmm_csr.sv
+ vlog -sv $unenc_file_dir/sv_xcvr_avmm_dcd.sv
+ vlog -sv $unenc_file_dir/sv_xcvr_custom_native.sv
+ vlog -sv $unenc_file_dir/sv_xcvr_data_adapter.sv
+ vlog -sv $unenc_file_dir/sv_xcvr_native.sv
+ vlog -sv $unenc_file_dir/sv_reconfig_bundle_to_xcvr.sv
+ vlog -sv $unenc_file_dir/sv_reconfig_bundle_merger.sv
+ vlog -sv $unenc_file_dir/sv_reconfig_bundle_to_ip.sv
+ vlog -sv $unenc_file_dir/sv_pcs.sv
+ vlog -sv $unenc_file_dir/sv_pcs_ch.sv
+ vlog -sv $unenc_file_dir/sv_pma.sv
+ vlog -sv $unenc_file_dir/sv_rx_pma.sv
+ vlog -sv $unenc_file_dir/sv_tx_pma.sv
+ vlog -sv $unenc_file_dir/sv_tx_pma_ch.sv
+ vlog -sv $unenc_file_dir/sv_pcs_ch.sv
+ vlog -sv $unenc_file_dir/sv_pcs_ch.sv
+ vlog -sv $unenc_file_dir/stratixv_hssi_8g_rx_pcs_rbc.sv
+ vlog -sv $unenc_file_dir/stratixv_hssi_8g_tx_pcs_rbc.sv
+ vlog -sv $unenc_file_dir/stratixv_hssi_common_pcs_pma_interface_rbc.sv
+ vlog -sv $unenc_file_dir/stratixv_hssi_common_pld_pcs_interface_rbc.sv
+ vlog -sv $unenc_file_dir/stratixv_hssi_rx_pcs_pma_interface_rbc.sv
+ vlog -sv $unenc_file_dir/stratixv_hssi_rx_pld_pcs_interface_rbc.sv
+ vlog -sv $unenc_file_dir/stratixv_hssi_tx_pcs_pma_interface_rbc.sv
+ vlog -sv $unenc_file_dir/stratixv_hssi_tx_pld_pcs_interface_rbc.sv
+ }
+ }
+
+
+#################################################################
+# Add your custom library compilation here and testbench
+#################################################################
+set custom_compilation custom_lib.tcl
+if {[file exists $custom_compilation]} {
+ source $custom_compilation
+}
+
+###########################################
+# Add your test bench here
+###########################################
+vlog ${dut_name}.v
+vsim -c -t 1ps $tb_name -novopt
+
+
+###########################################
+# Run and Quit your simulator
+###########################################
+run -all
+quit -sim
+exit
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/plain_files.txt b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/plain_files.txt
new file mode 100644
index 0000000000000000000000000000000000000000..4c25ca083f6ec1f6f001faabdca100f7abb426e2
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/plain_files.txt
@@ -0,0 +1,59 @@
+./altera_xcvr_functions.sv
+./alt_pma_functions.sv
+./altera_xcvr_xaui.sv
+./hxaui_csr_h.sv
+./hxaui_csr.sv
+./alt_xcvr_mgmt2dec_phyreconfig.sv
+./alt_xcvr_mgmt2dec_xaui.sv
+./alt_pma_ch_controller_tgx.v
+./alt_pma_controller_tgx.v
+./alt_reset_ctrl_lego.sv
+./alt_reset_ctrl_tgx_cdrauto.sv
+./alt_xcvr_resync.sv
+./alt_xcvr_csr_common_h.sv
+./alt_xcvr_csr_common.sv
+./alt_xcvr_csr_pcs8g_h.sv
+./alt_xcvr_csr_pcs8g.sv
+./alt_xcvr_csr_selector.sv
+./alt_xcvr_mgmt2dec.sv
+./altera_wait_generate.v
+./aldec/alt_soft_xaui_pcs.v
+./aldec/alt_soft_xaui_reset.v
+./aldec/alt_soft_xaui_rx.v
+./aldec/alt_soft_xaui_rx_8b10b_dec.v
+./aldec/alt_soft_xaui_rx_channel_synch.v
+./aldec/alt_soft_xaui_rx_deskew.v
+./aldec/alt_soft_xaui_rx_deskew_channel.v
+./aldec/alt_soft_xaui_rx_deskew_ram.v
+./aldec/alt_soft_xaui_rx_invalid_code_det.v
+./aldec/alt_soft_xaui_rx_parity.v
+./aldec/alt_soft_xaui_rx_parity_4b.v
+./aldec/alt_soft_xaui_rx_parity_6b.v
+./aldec/alt_soft_xaui_rx_rate_match.v
+./aldec/alt_soft_xaui_rx_rate_match_ram.v
+./aldec/alt_soft_xaui_rx_rl_chk_6g.v
+./aldec/alt_soft_xaui_rx_sm.v
+./aldec/alt_soft_xaui_tx.v
+./aldec/alt_soft_xaui_tx_8b10b_enc.v
+./aldec/alt_soft_xaui_tx_idle_conv.v
+./aldec/l_modules.v
+./aldec/serdes_4_unit_lc_siv.v
+./aldec/serdes_4_unit_siv.v
+./aldec/serdes_4unit.v
+./sxaui.v
+./siv_xcvr_low_latency_phy_nr.sv
+./siv_xcvr_xaui.sv
+./alt4gxb_vo.v
+./alt_xcvr_reconfig_h.sv
+./alt_xcvr_reconfig_siv.sv
+./alt_xcvr_reconfig_analog.sv
+./alt_xcvr_reconfig_analog_tgx.v
+./alt_xcvr_reconfig_offset_cancellation.sv
+./alt_xcvr_reconfig_offset_cancellation_tgx.v
+./alt_xcvr_reconfig_eyemon_tgx.sv
+./alt_xcvr_reconfig_dfe_tgx.sv
+./alt_xcvr_reconfig_basic_tgx.v
+./alt_mutex_acq.v
+./alt_dprio.v
+./alt_xcvr_arbiter.sv
+./alt_xcvr_m2s.sv
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/sim_script_files.txt b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/sim_script_files.txt
new file mode 100644
index 0000000000000000000000000000000000000000..4c25ca083f6ec1f6f001faabdca100f7abb426e2
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/sim_script_files.txt
@@ -0,0 +1,59 @@
+./altera_xcvr_functions.sv
+./alt_pma_functions.sv
+./altera_xcvr_xaui.sv
+./hxaui_csr_h.sv
+./hxaui_csr.sv
+./alt_xcvr_mgmt2dec_phyreconfig.sv
+./alt_xcvr_mgmt2dec_xaui.sv
+./alt_pma_ch_controller_tgx.v
+./alt_pma_controller_tgx.v
+./alt_reset_ctrl_lego.sv
+./alt_reset_ctrl_tgx_cdrauto.sv
+./alt_xcvr_resync.sv
+./alt_xcvr_csr_common_h.sv
+./alt_xcvr_csr_common.sv
+./alt_xcvr_csr_pcs8g_h.sv
+./alt_xcvr_csr_pcs8g.sv
+./alt_xcvr_csr_selector.sv
+./alt_xcvr_mgmt2dec.sv
+./altera_wait_generate.v
+./aldec/alt_soft_xaui_pcs.v
+./aldec/alt_soft_xaui_reset.v
+./aldec/alt_soft_xaui_rx.v
+./aldec/alt_soft_xaui_rx_8b10b_dec.v
+./aldec/alt_soft_xaui_rx_channel_synch.v
+./aldec/alt_soft_xaui_rx_deskew.v
+./aldec/alt_soft_xaui_rx_deskew_channel.v
+./aldec/alt_soft_xaui_rx_deskew_ram.v
+./aldec/alt_soft_xaui_rx_invalid_code_det.v
+./aldec/alt_soft_xaui_rx_parity.v
+./aldec/alt_soft_xaui_rx_parity_4b.v
+./aldec/alt_soft_xaui_rx_parity_6b.v
+./aldec/alt_soft_xaui_rx_rate_match.v
+./aldec/alt_soft_xaui_rx_rate_match_ram.v
+./aldec/alt_soft_xaui_rx_rl_chk_6g.v
+./aldec/alt_soft_xaui_rx_sm.v
+./aldec/alt_soft_xaui_tx.v
+./aldec/alt_soft_xaui_tx_8b10b_enc.v
+./aldec/alt_soft_xaui_tx_idle_conv.v
+./aldec/l_modules.v
+./aldec/serdes_4_unit_lc_siv.v
+./aldec/serdes_4_unit_siv.v
+./aldec/serdes_4unit.v
+./sxaui.v
+./siv_xcvr_low_latency_phy_nr.sv
+./siv_xcvr_xaui.sv
+./alt4gxb_vo.v
+./alt_xcvr_reconfig_h.sv
+./alt_xcvr_reconfig_siv.sv
+./alt_xcvr_reconfig_analog.sv
+./alt_xcvr_reconfig_analog_tgx.v
+./alt_xcvr_reconfig_offset_cancellation.sv
+./alt_xcvr_reconfig_offset_cancellation_tgx.v
+./alt_xcvr_reconfig_eyemon_tgx.sv
+./alt_xcvr_reconfig_dfe_tgx.sv
+./alt_xcvr_reconfig_basic_tgx.v
+./alt_mutex_acq.v
+./alt_dprio.v
+./alt_xcvr_arbiter.sv
+./alt_xcvr_m2s.sv
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/siv_xcvr_low_latency_phy_nr.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/siv_xcvr_low_latency_phy_nr.sv
new file mode 100644
index 0000000000000000000000000000000000000000..de32c92263ec21c27299b5fa15160844b80dba64
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/siv_xcvr_low_latency_phy_nr.sv
@@ -0,0 +1,352 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// PMA-direct component for TGX-style transceiver architectures
+//
+// $Header$
+//
+`timescale 1 ps / 1 ps
+module siv_xcvr_low_latency_phy_nr
+#(
+
+ //reserved parameter, don't change them.
+ parameter device_family="Stratix IV",
+ intended_device_variant ="ANY",
+
+ //must have parameters
+ parameter number_of_channels = 1,
+ parameter number_of_reconfig_interface = 1,//it's number of quad for S4
+ parameter operation_mode = "DUPLEX", //TX, RX, DUPLEX
+ parameter phase_comp_fifo_mode = "NONE",//EMBEDDED, NONE
+ parameter serialization_factor = 16,//8,10,16,20,32,40
+ parameter data_rate = "3125 Mbps",
+ parameter pll_input_frequency = "156.25 MHz",
+
+ //additonal system parameters
+ parameter number_pll_inclks = 1,//reconfig may need more than one reference clock
+ parameter pll_inclk_select = 0,//0-number_of_ref_clks
+ parameter pll_type = "CMU",//ATX|CMU
+ parameter bonded_mode = "TRUE",
+ parameter starting_channel_number = 0,//0,4,8,12 ...
+ parameter support_reconfig = 1,
+ parameter rx_use_cruclk = "FALSE",
+
+ //analog parameters
+ parameter gx_analog_power = "AUTO",//AUTO|2.5v|3.0v|3.3v|3.9v
+
+ parameter pll_lock_speed = "AUTO",//AUTO|LOW|MEDIUM|HIGH
+ parameter tx_analog_power = "AUTO",//AUTO|1.4V|1.5V
+ parameter tx_slew_rate = "LOW",//AUTO,LOW,MEDIUM,HIGH
+ parameter tx_termination = "OCT_100_OHMS",//OCT_85_OHMS,OCT_100_OHMS,OCT_120_OHMS,OCT_150_OHMS
+ parameter tx_use_external_termination = "FALSE", //FALSE|TRUE
+ parameter tx_common_mode = "0.65V", //"0.65V"
+
+ parameter rx_pll_lock_speed = "AUTO",//AUTO|LOW|MEDIUM|HIGH
+ parameter rx_common_mode = "0.82v", //TRISTATE|0.82v|1.1v
+ parameter rx_signal_detect_threshold = 2,
+ parameter rx_ppmselect = 32,
+ parameter rx_termination = "OCT_100_OHMS", //OCT_85_OHMS,OCT_100_OHMS,OCT_120_OHMS,OCT_150_OHMS
+ parameter rx_use_external_termination = "FALSE", //FALSE|TRUE
+
+ parameter tx_preemp_pretap = 0,//0-7
+ parameter tx_preemp_pretap_inv = "FALSE",//TRUE” or FALSE”. Determine whether the pre-emphasis control signal for the pretap needed to be inverted or not.“true” – Invert the pre-emphasis control signal for the pre tap.“false” – Do not invert the pre-emphasis control signal for the pretap.
+ parameter tx_preemp_tap_1 = 5,//0-15
+ parameter tx_preemp_tap_2 = 0,//0-7
+ parameter tx_preemp_tap_2_inv = "FALSE",//TRUE” or FALSE”.
+ parameter tx_vod_selection = 1,//0-7
+
+ parameter rx_eq_dc_gain = 0, //0-4
+ parameter rx_eq_ctrl = 14,//0-16
+
+ parameter sys_clk_in_mhz = 150, // used to calculate reset controller delays as system clock cycle counts
+
+ parameter loopback_mode = "NONE"//NONE|SLB|PLB|PRECDR_RSLB|POSTCDR_RSLB|RPLB
+)
+(
+
+ // user data (avalon-MM slave interface) //for all the channel rst, powerdown, rx serilize loopback enable
+ input wire rst,
+ input wire clk,
+ input wire [5:0] ch_mgmt_address,
+ input wire ch_mgmt_read,
+ output wire [31:0] ch_mgmt_readdata,
+ input wire ch_mgmt_write,
+ input wire [31:0] ch_mgmt_writedata,
+ output wire ch_mgmt_waitrequest,
+
+ // avalon-ST interface with PMA controller
+ input wire cal_blk_clk,
+ input wire cal_blk_pdn,
+ input wire gx_pdn,//sync with clk
+ input wire tx_rst_digital, // digital reset
+ input wire rx_rst_digital, // digital reset
+ output wire tx_pma_ready, // pma tx pll_locked
+ output wire rx_pma_ready, // pma rx pll is locked to data
+
+ input wire pll_pdn, //sync with clk
+ output wire pll_locked, //conduit
+
+ // avalon-ST interface with reconfig controller
+ input wire reconfig_clk,
+ input wire [3:0] reconfig_to_gxb, //sync with reconfig_clk
+ output wire [17* number_of_reconfig_interface -1:0] reconfig_from_gxb, //sync with reconfig_clk. 17 bit per quad
+// input wire [24 * number_of_reconfig_interface -1 : 0] aeq_to_gxb, //sync with reconfig_clk
+// output wire [8*number_of_reconfig_interface -1:0] aeq_from_gxb, //sync with reconfig_clk.
+
+
+ //channel related avalon-clock interface
+ input wire [number_pll_inclks-1:0] pll_ref_clk,
+ input wire [number_of_channels-1:0] rx_cdr_ref_clk,
+
+ //channel related avalon-ST interface, tx
+ input wire [number_of_channels * serialization_factor -1:0] tx_parallel_data,// sync with tx_clkout_clk
+ output wire [number_of_channels-1:0] tx_serial_data, // canduit
+ output wire [number_of_channels-1:0] tx_out_clk,
+
+ //channel related AVALON-st INTERFACE, rx
+ input wire [number_of_channels-1:0] rx_serial_data,//canduit
+ output wire [number_of_channels * serialization_factor -1:0] rx_parallel_data,// sync with rx_clkout_clk
+ output wire [number_of_channels-1:0] rx_recovered_clk,
+
+ output wire [number_of_channels-1:0] rx_is_lockedtodata,//conduit
+ output wire [number_of_channels-1:0] rx_is_lockedtoref,//conduit
+
+ output wire [number_of_channels-1:0] tx_digital_rst, // output digital reset for soft PCS, this reset can be controlled in AVMM
+ output wire [number_of_channels-1:0] rx_digital_rst // output digital reset for soft PCS, this reset can be controlled in AVMM
+
+);
+
+// instantiate package with common functions
+import alt_pma_functions::*;
+
+//derived parameters
+localparam tx_inclk0_input_period_loc = freq2ps(pll_input_frequency) ;
+localparam use6g= (((mega2k(data_rate) > 1000000) && ((serialization_factor == 32) || (serialization_factor == 40))) || ((serialization_factor != 8) && (serialization_factor != 10)))? "TRUE" : "FALSE";
+localparam pma_serialization_factor = (phase_comp_fifo_mode != "EMBEDDED") ? serialization_factor :
+ ((serialization_factor>20)? (serialization_factor/2):
+ ((serialization_factor<16)? serialization_factor :
+ ((use6g == "TRUE")? serialization_factor : serialization_factor /2)));
+//localparam RX_INCLK_INPUT_PERIOD_LOC = ( RX_INCLK_INPUT_PERIOD == 0) ? freq2ps(RX_pll_input_frequency) : RX_INCLK_INPUT_PERIOD;
+//localparam rx_inclk_input_frequency_loc = ( operation_mode == "DUPLEX") ? ((RX_INCLK_INPUT_FREQUENCY == 0) ? INCLK_INPUT_FREQUENCY : RX_INCLK_INPUT_FREQUENCY) :0;
+localparam double_serialization_mode=(serialization_factor/pma_serialization_factor == 2) ? "TRUE":"FALSE";
+localparam rx_eqa_ctrl = (device_family=="Stratix IV") ? ((rx_eq_ctrl >10)? 7 :0) : ((rx_eq_ctrl >1)? 1:0);
+localparam rx_eqb_ctrl = (device_family=="Stratix IV") ? ((rx_eq_ctrl >6)? 7 :0) : ((rx_eq_ctrl >3)? 1:0);
+localparam rx_eqc_ctrl = (device_family=="Stratix IV") ? ((rx_eq_ctrl >3)? 7 :0) : 0;
+localparam rx_eqd_ctrl = (device_family=="Stratix IV") ? ((rx_eq_ctrl >0)? 7 :0) : 0;
+localparam rx_eqv_ctrl = (device_family=="Stratix IV") ?
+ ((rx_eq_ctrl==2 | rx_eq_ctrl==5 | rx_eq_ctrl==8 | rx_eq_ctrl==13)? 4 :
+ ((rx_eq_ctrl==3 | rx_eq_ctrl==6 | rx_eq_ctrl==10 | rx_eq_ctrl==15)? 7 :
+ ((rx_eq_ctrl==9 | rx_eq_ctrl==14 )? 5 :
+ (rx_eq_ctrl==12)? 3 : 0))) :
+ ((rx_eq_ctrl==0 | rx_eq_ctrl==2 | rx_eq_ctrl==4 )? 1 :0 );
+localparam number_of_ctrl_bus=(bonded_mode == "FALSE")? number_of_reconfig_interface : 1;
+
+localparam enable_lc_tx_pll_param = (pll_type == "CMU")? "FALSE" : "TRUE";
+localparam enable_pma_direct_param = (phase_comp_fifo_mode == "EMBEDDED")? "FALSE":"TRUE";
+localparam dwidth_factor = (use6g == "TRUE")? (double_serialization_mode == "TRUE" ? 4:2):(double_serialization_mode == "TRUE" ? 2:1);
+localparam reconfig_dprio_mode = (support_reconfig == 0)? 0 : 1;
+
+localparam control_signal_width = (bonded_mode == "TRUE") ? 1: number_of_channels;
+localparam pma_direct_xn = (phase_comp_fifo_mode == "NONE")? bonded_mode : "FALSE";
+localparam pma_bonding = (phase_comp_fifo_mode == "EMBEDDED")? bonded_mode : "FALSE";
+
+wire [control_signal_width-1:0] gxb_pdn_loc;
+generate
+genvar i;
+for (i=0; i<control_signal_width; i=i+1)
+begin: gxb_pdn_bus
+assign gxb_pdn_loc[i] = gx_pdn;
+end
+endgenerate
+
+wire [control_signal_width-1:0] pll_pdn_loc;
+generate
+genvar j;
+for (j=0; j<control_signal_width; j=j+1)
+begin: pll_pdn_bus
+assign pll_pdn_loc[j] = pll_pdn;
+end
+endgenerate
+
+wire [number_of_channels-1:0] rx_set_locktodata;
+wire [number_of_channels-1:0] rx_set_locktoref;
+
+wire [number_of_channels-1:0] rx_analog_rst;
+wire [number_of_channels-1:0] rx_seriallpbken;
+
+
+
+alt4gxb #(
+ .cbx_hdl_language ("Verilog"),
+ .enable_pma_xn_bonding (pma_direct_xn),
+ .cmu_pll_inclk_log_index (pll_inclk_select),
+ .cmu_pll_log_index (0),
+ .device_family (device_family),
+ .intended_device_variant (intended_device_variant),
+ .effective_data_rate (data_rate),
+ .enable_lc_tx_pll (enable_lc_tx_pll_param),
+ .enable_pma_direct (enable_pma_direct_param),
+ .enable_pll_inclk_drive_rx_cru((rx_use_cruclk == "FALSE")? "TRUE" : "FALSE"),
+ .equalizer_ctrl_a_setting (rx_eqa_ctrl),
+ .equalizer_ctrl_b_setting (rx_eqb_ctrl),
+ .equalizer_ctrl_c_setting (rx_eqc_ctrl),
+ .equalizer_ctrl_d_setting (rx_eqd_ctrl),
+ .equalizer_ctrl_v_setting (rx_eqv_ctrl),
+ .equalizer_dcgain_setting (rx_eq_dc_gain),
+ .gen_reconfig_pll ("FALSE"),
+ .gx_channel_type ("AUTO"),
+ .gxb_analog_power (gx_analog_power),
+ .gxb_powerdown_width (control_signal_width),
+ .input_clock_frequency (pll_input_frequency),
+ .loopback_mode (loopback_mode),
+ .number_of_channels (number_of_channels),
+ .number_of_quads (number_of_reconfig_interface),
+ .operation_mode (operation_mode),
+ .pll_control_width (number_of_ctrl_bus),
+ .protocol ("BASIC"),
+ .use_global_clk_divider (pma_bonding),
+ .receiver_termination (rx_termination),
+ .rx_use_external_termination (rx_use_external_termination),
+ .reconfig_calibration ("TRUE"),
+ .reconfig_dprio_mode (reconfig_dprio_mode),
+ .reconfig_fromgxb_port_width (17*number_of_reconfig_interface ),
+ .reconfig_pll_inclk_width ((support_reconfig == 0)? 1: number_pll_inclks),
+ .reconfig_protocol ("BASIC"),
+ .reconfig_togxb_port_width (4),
+ .rx_use_cruclk (rx_use_cruclk),
+ .rx_channel_width (serialization_factor),
+ .rx_common_mode (rx_common_mode),
+ .rx_cru_bandwidth_type (rx_pll_lock_speed),
+ .rx_digitalreset_port_width (number_of_channels),
+ .rx_enable_lock_to_data_sig ("true"),
+ .rx_enable_lock_to_refclk_sig ("true"),
+ .rx_ppmselect (rx_ppmselect),
+ .rx_reconfig_clk_scheme ("indv_clk_source"),
+ .rx_signal_detect_threshold (rx_signal_detect_threshold),
+ .rx_use_clkout ("TRUE"),
+ .rx_use_coreclk ("false"),
+ .rx_use_deserializer_double_data_mode(use6g),
+ .rx_use_double_data_mode (double_serialization_mode),
+ .starting_channel_number (starting_channel_number),
+ .transmitter_termination (tx_termination),
+ .tx_use_external_termination (tx_use_external_termination),
+ .tx_dwidth_factor (dwidth_factor),
+ .tx_analog_power (tx_analog_power),
+ .tx_channel_width (serialization_factor),
+ .tx_clkout_width (number_of_channels),
+ .tx_common_mode (tx_common_mode),
+ .tx_pll_bandwidth_type (pll_lock_speed),
+ .tx_pll_inclk0_period (tx_inclk0_input_period_loc),
+ .tx_pll_type (pll_type),
+ .tx_reconfig_clk_scheme ("tx_ch0_clk_source"),
+ .tx_slew_rate (tx_slew_rate),
+ .tx_transmit_protocol ("basic"),
+ .tx_use_coreclk ("false"),
+ .tx_use_double_data_mode (double_serialization_mode),
+ .tx_use_serializer_double_data_mode (use6g),
+ .preemphasis_ctrl_pretap_setting (tx_preemp_pretap),
+ .preemphasis_ctrl_pretap_inv_setting (tx_preemp_pretap_inv),
+ .preemphasis_ctrl_1stposttap_setting (tx_preemp_tap_1),
+ .preemphasis_ctrl_2ndposttap_setting (tx_preemp_tap_2),
+ .preemphasis_ctrl_2ndposttap_inv_setting (tx_preemp_tap_2_inv),
+ .use_calibration_block ("TRUE"),
+ .vod_ctrl_setting (tx_vod_selection),
+ .tx_digitalreset_port_width (number_of_channels),
+ .rx_use_align_state_machine ("true"),//must have
+ .tx_datapath_low_latency_mode ("true"),
+ .rx_use_deskew_fifo ("false"),
+ .rx_word_aligner_num_byte (2),
+ .rx_rate_match_fifo_mode ("none"),
+ .tx_enable_bit_reversal ("false"),
+ .tx_enable_self_test_mode ("false"),
+ .tx_flip_tx_in ("false"),
+ .rx_dwidth_factor (dwidth_factor),
+ .rx_8b_10b_mode ("none"),
+ .rx_allow_align_polarity_inversion ("false"),
+ .rx_allow_pipe_polarity_inversion ("false"),
+ .tx_bitslip_enable ("false"),
+ .rx_bitslip_enable ("true"),
+ .rx_byte_ordering_mode ("none"),
+ .rx_enable_self_test_mode ("false"),
+ .rx_flip_rx_out ("false"),
+ .rx_force_signal_detect ("true"),
+ .rx_phfiforegmode ("false"),
+ .rx_datapath_low_latency_mode ("true"),
+ .rx_datapath_protocol ("basic"),
+ .rx_enable_bit_reversal ("false"),
+ .rx_enable_deep_align_byte_swap("false")
+ ) pma_direct (
+ .cal_blk_clk (cal_blk_clk),
+ .cal_blk_powerdown (cal_blk_pdn),
+ .gxb_powerdown (gxb_pdn_loc),
+ .pll_inclk(pll_ref_clk),
+ //.pll_inclk_rx_cruclk((support_reconfig == 0)? 0 : pll_ref_clk),
+ .rx_cruclk ((rx_use_cruclk == "TRUE")? rx_cdr_ref_clk[number_of_channels - 1:0] : {number_of_channels{1'b0}}),
+ .pll_locked (pll_locked),
+ .pll_powerdown (pll_pdn_loc),
+ .reconfig_clk (reconfig_clk),
+ .reconfig_fromgxb (reconfig_from_gxb),
+ .reconfig_togxb (reconfig_to_gxb),
+ .rx_analogreset (rx_analog_rst[number_of_channels-1:0]),
+ .rx_seriallpbken ((loopback_mode == "SLB")? rx_seriallpbken[number_of_channels-1:0] : 0),
+ .tx_digitalreset ((phase_comp_fifo_mode == "EMBEDDED")? tx_digital_rst[number_of_channels-1:0] : {number_of_channels{1'b0}}),
+ .rx_digitalreset ((phase_comp_fifo_mode == "EMBEDDED")? rx_digital_rst[number_of_channels-1:0] : {number_of_channels{1'b0}}),
+ .rx_clkout (rx_recovered_clk[number_of_channels-1:0]),
+ .rx_datain (rx_serial_data[number_of_channels-1:0]),
+ .rx_dataout (rx_parallel_data[serialization_factor * number_of_channels-1:0]),
+ .rx_freqlocked (rx_is_lockedtodata[number_of_channels-1:0]),
+ .rx_locktodata (rx_set_locktodata[number_of_channels-1:0]),
+ .rx_locktorefclk (rx_set_locktoref[number_of_channels-1:0]),
+ .rx_pll_locked (rx_is_lockedtoref[number_of_channels-1:0]),
+ .tx_clkout (tx_out_clk[number_of_channels-1:0]),
+ .tx_datain (tx_parallel_data[serialization_factor * number_of_channels-1:0]),
+ .tx_dataout (tx_serial_data[number_of_channels-1:0])
+ );
+
+alt_pma_ch_controller_tgx #(
+ .number_of_channels (number_of_channels),
+ .sys_clk_in_mhz (sys_clk_in_mhz),
+ .sync_depth (2)
+) channel_ctrl (
+ .rst(rst),
+ .tx_rst_digital (tx_rst_digital), // tx_digitalreset
+ .rx_rst_digital (rx_rst_digital), // rx_digitalreset
+ .tx_pma_ready (tx_pma_ready), // pma tx pll_locked
+ .rx_pma_ready (rx_pma_ready), // pma rx pll is locked to data
+ .rx_cal_busy (reconfig_to_gxb[3]), // rx_ocilator busy
+ .tx_cal_busy (1'b0), // rx_ocilator busy
+ .pll_locked (pll_locked), // tx pll_is_locked
+
+ .ch_mgmt_address (ch_mgmt_address),
+ .ch_mgmt_read (ch_mgmt_read),
+ .ch_mgmt_readdata (ch_mgmt_readdata),
+ .ch_mgmt_write (ch_mgmt_write),
+ .ch_mgmt_writedata (ch_mgmt_writedata),
+ .clk (clk),
+ .ch_mgmt_waitrequest(ch_mgmt_waitrequest),
+
+ .rx_is_lockedtodata (rx_is_lockedtodata),
+ .rx_is_lockedtoref (rx_is_lockedtoref),
+
+ .rx_set_locktodata (rx_set_locktodata),
+ .rx_set_locktoref (rx_set_locktoref),
+
+ .rx_analog_rst (rx_analog_rst),
+ .rx_seriallpbken (rx_seriallpbken),
+ .tx_digital_rst (tx_digital_rst),
+ .rx_digital_rst (rx_digital_rst),
+ .pll_powerdown ()
+);
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/siv_xcvr_xaui.sv b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/siv_xcvr_xaui.sv
new file mode 100644
index 0000000000000000000000000000000000000000..16ad2c9b0c247529918db040a9c41da5f8639e0c
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/siv_xcvr_xaui.sv
@@ -0,0 +1,539 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//-----------------------------------------------------------------------------
+//
+// Description: hxaui static verilog for Stratix IV
+//
+// Authors: bauyeung 7-Sep-2010
+//
+// Copyright (c) Altera Corporation 1997 - 2010
+// All rights reserved.
+//
+//-----------------------------------------------------------------------------
+ /*ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"set_false_path -from [get_registers *hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component*] -to [get_registers *xaui_phy*hxaui_csr*tx_phase_comp_fifo_error_c[*]]\" " */
+
+module siv_xcvr_xaui #(
+ parameter device_family = "Stratix IV",
+ parameter starting_channel_number = 0,
+ parameter interface_type = "Hard XAUI",
+ parameter number_of_interfaces = 1,
+ parameter sys_clk_in_mhz = 50,
+ parameter xaui_pll_type = "CMU",
+ parameter reconfig_interfaces = 1,
+ parameter use_control_and_status_ports = 0,
+ parameter external_pma_ctrl_reconf = 0,
+ parameter tx_termination = "OCT_150_OHMS",
+ parameter tx_vod_selection = 1,
+ parameter tx_preemp_pretap = 0,
+ parameter tx_preemp_pretap_inv = 0,
+ parameter tx_preemp_tap_1 = 5,
+ parameter tx_preemp_tap_2 = 0,
+ parameter tx_preemp_tap_2_inv = 0,
+ parameter rx_common_mode = "0.82v",
+ parameter rx_termination = "OCT_150_OHMS",
+ parameter rx_eq_dc_gain = 0,
+ parameter rx_eq_ctrl = 14
+) (
+ input wire pll_ref_clk, // refclk.clk
+ input wire xgmii_tx_clk, // xgmii_tx_clk.clk
+ output wire xgmii_rx_clk, // xgmii_rx_clk.clk
+ input wire phy_mgmt_clk, // mgmt_clk.clk
+ input wire phy_mgmt_clk_reset, // mgmt_clk_rst.reset_n
+ input wire [7:0] phy_mgmt_address, // phy_mgmt.address
+ output wire phy_mgmt_waitrequest, // .waitrequest
+ input wire phy_mgmt_read, // .read
+ output wire [31:0] phy_mgmt_readdata, // .readdata
+ input wire phy_mgmt_write, // .write
+ input wire [31:0] phy_mgmt_writedata, // .writedata
+ input wire [71:0] xgmii_tx_dc, // xgmii_tx_dc.data
+ output wire [71:0] xgmii_rx_dc, // xgmii_rx_dc.data
+ output wire [3:0] xaui_tx_serial_data, // xaui_tx_serial.export
+ input wire [3:0] xaui_rx_serial_data, // xaui_rx_serial.export
+ output wire rx_ready, // rx_pma_ready.data
+ output wire tx_ready, // tx_pma_ready.data
+ output tri0 [altera_xcvr_functions::get_reconfig_from_width(device_family,reconfig_interfaces)-1:0] reconfig_from_xcvr,
+ input tri0 [altera_xcvr_functions::get_reconfig_to_width(device_family,reconfig_interfaces) -1:0] reconfig_to_xcvr,
+
+ output wire [3:0] rx_recovered_clk, // rx recovered clock from cdr
+// optional control and status ports
+ input wire rx_analogreset,
+ input wire rx_digitalreset,
+ input wire tx_digitalreset,
+ output wire rx_channelaligned,
+ input wire [3:0] rx_invpolarity,
+ input wire [3:0] rx_set_locktodata,
+ input wire [3:0] rx_set_locktoref,
+ input wire [3:0] rx_seriallpbken,
+ input wire [3:0] tx_invpolarity,
+ output wire [3:0] rx_is_lockedtodata,
+ output wire [3:0] rx_phase_comp_fifo_error,
+ output wire [3:0] rx_is_lockedtoref,
+ output wire [3:0] rx_rlv,
+ output wire [3:0] rx_rmfifoempty,
+ output wire [3:0] rx_rmfifofull,
+ output wire [3:0] tx_phase_comp_fifo_error,
+ output wire [7:0] rx_disperr,
+ output wire [7:0] rx_errdetect,
+ output wire [7:0] rx_patterndetect,
+ output wire [7:0] rx_rmfifodatadeleted,
+ output wire [7:0] rx_rmfifodatainserted,
+ output wire [7:0] rx_runningdisp,
+ output wire [7:0] rx_syncstatus,
+
+// external_pma_ctrl_reconf
+ output wire pll_locked,
+ input wire cal_blk_powerdown,
+ input wire gxb_powerdown,
+ input wire pll_powerdown
+);
+
+import altera_xcvr_functions::*;
+
+ wire alt_pma_controller_0_cal_blk_pdn_data;
+ wire alt_pma_controller_0_pll_pdn0_data;
+ wire alt_pma_controller_0_gx_pdn_data;
+ wire pll_locked_data;
+ wire [7:0] rx_disperr_data;
+ wire [7:0] rx_errdetect_data;
+ wire [7:0] rx_patterndetect_data;
+ wire [3:0] rx_phase_comp_fifo_error_data;
+ wire [3:0] rx_rlv_data;
+ wire [7:0] rx_rmfifodatadeleted_data;
+ wire [7:0] rx_rmfifodatainserted_data;
+ wire [3:0] rx_rmfifoempty_data;
+ wire [3:0] rx_rmfifofull_data;
+ wire [7:0] rx_runningdisp_data;
+ wire [7:0] rx_syncstatus_data;
+ wire [3:0] tx_phase_comp_fifo_error_data;
+ wire [3:0] alt_pma_ch_controller_0_rx_set_locktodata_data;
+ wire [3:0] alt_pma_ch_controller_0_rx_set_locktoref_data;
+ wire [3:0] alt_pma_ch_controller_0_rx_seriallpbken_data;
+ wire [3:0] alt_pma_ch_controller_0_rx_analog_rst_data;
+ wire [3:0] rx_is_lockedtodata_data;
+ wire [3:0] rx_is_lockedtoref_data;
+ wire [3:0] alt_pma_ch_controller_0_tx_digital_rst_data;
+ wire [3:0] alt_pma_ch_controller_0_rx_digital_rst_data;
+ wire hxaui_csr_r_rx_digitalreset_data;
+ wire [3:0] hxaui_csr_r_rx_invpolarity_data;
+ wire hxaui_csr_r_tx_digitalreset_data;
+ wire [3:0] hxaui_csr_r_tx_invpolarity_data;
+ wire hxaui_csr_simulation_flag_data;
+ wire alt_pma_controller_0_pll_pdn;
+ wire [3:0] alt_pma_0_tx_out_clk_clk;
+ wire [3:0] alt_pma_0_rx_recovered_clk_clk;
+ wire [79:0] sxaui_0_tx_parallel_data_data;
+ wire [79:0] alt_pma_0_rx_parallel_data_data;
+ wire [3:0] alt_pma_0_rx_is_lockedtodata_data;
+ wire rx_pma_ready;
+ wire sxaui_rst_done;
+
+
+ wire [5:0] sc_pma_ch_controller_address;
+ wire sc_pma_ch_controller_read;
+ wire [31:0] sc_pma_ch_controller_readdata;
+ wire sc_pma_ch_controller_waitrequest;
+ wire sc_pma_ch_controller_write;
+
+
+ wire [1:0] sc_pma_controller_address;
+ wire sc_pma_controller_read;
+ wire [31:0] sc_pma_controller_readdata;
+ wire sc_pma_controller_waitrequest;
+ wire sc_pma_controller_write;
+
+ wire [4:0] sc_csr_address;
+ wire sc_csr_read;
+ wire [31:0] sc_csr_readdata;
+ wire sc_csr_write;
+
+// assign output wires for status ports - whether or not they are used will be decided by the top level
+ assign rx_is_lockedtodata = rx_is_lockedtodata_data;
+ assign rx_phase_comp_fifo_error = rx_phase_comp_fifo_error_data;
+ assign rx_is_lockedtoref = rx_is_lockedtoref_data;
+ assign rx_rlv = rx_rlv_data;
+ assign rx_rmfifoempty = rx_rmfifoempty_data;
+ assign rx_rmfifofull = rx_rmfifofull_data;
+ assign tx_phase_comp_fifo_error = tx_phase_comp_fifo_error_data;
+ assign rx_disperr = rx_disperr_data;
+ assign rx_errdetect = rx_errdetect_data;
+ assign rx_patterndetect = rx_patterndetect_data;
+ assign rx_rmfifodatadeleted = rx_rmfifodatadeleted_data;
+ assign rx_rmfifodatainserted = rx_rmfifodatainserted_data;
+ assign rx_runningdisp = rx_runningdisp_data;
+ assign rx_syncstatus = rx_syncstatus_data;
+ assign rx_recovered_clk = alt_pma_0_rx_recovered_clk_clk;
+
+ // assign output wires for external pma_ctrl - whether or not they are used will be decided by the top level
+ assign pll_locked = pll_locked_data;
+ assign rx_ready = rx_pma_ready & sxaui_rst_done; // pma and PCS must be both ready
+
+ ///////////////////////////////////////////////////////////////////////
+ // Decoder for multiple slaves of pma_ch_control,pma_control,hxaui i/f
+ ///////////////////////////////////////////////////////////////////////
+ alt_xcvr_mgmt2dec_xaui mgmtdec_xaui (
+ .mgmt_clk_reset (phy_mgmt_clk_reset),
+ .mgmt_clk (phy_mgmt_clk),
+ .mgmt_address (phy_mgmt_address),
+ .mgmt_read (phy_mgmt_read),
+ .mgmt_write (phy_mgmt_write),
+ .mgmt_readdata (phy_mgmt_readdata),
+ .mgmt_waitrequest (phy_mgmt_waitrequest),
+
+ // internal interface to 'top' pma ch controller block
+ .sc_pma_ch_controller_readdata (sc_pma_ch_controller_readdata),
+ .sc_pma_ch_controller_waitrequest (sc_pma_ch_controller_waitrequest),
+ .sc_pma_ch_controller_address (sc_pma_ch_controller_address), //6 bit wide
+ .sc_pma_ch_controller_read (sc_pma_ch_controller_read),
+ .sc_pma_ch_controller_write (sc_pma_ch_controller_write),
+
+ // internal interface to 'top' pma controller block
+ .sc_pma_controller_readdata (sc_pma_controller_readdata),
+ .sc_pma_controller_waitrequest (sc_pma_controller_waitrequest),
+ .sc_pma_controller_address (sc_pma_controller_address), //2 bit wide
+ .sc_pma_controller_read (sc_pma_controller_read),
+ .sc_pma_controller_write (sc_pma_controller_write),
+
+ // internal interface to 'top' hxaui csr block
+ .sc_csr_readdata (sc_csr_readdata),
+ .sc_csr_waitrequest (1'b0), // PCS CSR is always ready
+ .sc_csr_address (sc_csr_address), //5 bit wide
+ .sc_csr_read (sc_csr_read),
+ .sc_csr_write (sc_csr_write)
+ );
+
+ ///////////////////////////////////////////////////////////////////////
+ // PMA Channel Controller - only for HXAUI
+ ///////////////////////////////////////////////////////////////////////
+// add generate for hxaui/sxaui - only use ch_controller for hxaui
+ generate
+ if (interface_type == "Hard XAUI") begin
+ alt_pma_ch_controller_tgx #(
+ .number_of_channels (4),
+ .sync_depth (2),
+ .sys_clk_in_mhz (sys_clk_in_mhz)
+ ) alt_pma_ch_controller_0 (
+ .clk (phy_mgmt_clk),
+ .rst (phy_mgmt_clk_reset),
+ .ch_mgmt_address (sc_pma_ch_controller_address),
+ .ch_mgmt_read (sc_pma_ch_controller_read),
+ .ch_mgmt_readdata (sc_pma_ch_controller_readdata),
+ .ch_mgmt_write (sc_pma_ch_controller_write),
+ .ch_mgmt_writedata (phy_mgmt_writedata),
+ .ch_mgmt_waitrequest (sc_pma_ch_controller_waitrequest),
+ .rx_pma_ready (rx_pma_ready),
+ .tx_pma_ready (tx_ready),
+ .rx_is_lockedtodata (rx_is_lockedtodata_data),
+ .rx_is_lockedtoref (rx_is_lockedtoref_data),
+ .rx_set_locktodata (alt_pma_ch_controller_0_rx_set_locktodata_data),
+ .rx_set_locktoref (alt_pma_ch_controller_0_rx_set_locktoref_data),
+ .rx_seriallpbken (alt_pma_ch_controller_0_rx_seriallpbken_data),
+ .rx_analog_rst (alt_pma_ch_controller_0_rx_analog_rst_data),
+ .tx_digital_rst (alt_pma_ch_controller_0_tx_digital_rst_data),
+ .rx_digital_rst (alt_pma_ch_controller_0_rx_digital_rst_data),
+ .rx_rst_digital (rx_digitalreset), // optional user triggered rx_digitalreset
+ .tx_rst_digital (tx_digitalreset), // optional user triggered tx_digitalreset
+ //reconfig_to_xcvr bit configuration
+ //Bit | Value
+ //-------------------------------------------
+ //3 | offset_cancellation_is_busy |
+ //2 | dprio_load |
+ //1 | dprio_disable |
+ //0 | dprio_in |
+ //-------------------------------------------
+ // .rx_oc_busy (reconfig_to_xcvr[3]), // rx_oc_busy.data
+ .rx_cal_busy (reconfig_to_xcvr[3]), // rx_oc_busy.data
+ .tx_cal_busy (1'b0), // rx_oc_busy.data
+ .pll_locked (pll_locked_data)
+ );
+ end else if (interface_type == "Soft XAUI") begin
+ siv_xcvr_low_latency_phy_nr #(
+ .device_family (device_family),
+ .intended_device_variant ("ANY"),
+ .number_of_channels (4),
+ .number_of_reconfig_interface (reconfig_interfaces),
+ .operation_mode ("DUPLEX"),
+ .phase_comp_fifo_mode ("NONE"),
+ .serialization_factor (20),
+ .data_rate ("3125 Mbps"),
+ .pll_input_frequency ("156.25 MHz"),
+ .number_pll_inclks (1),
+ .pll_inclk_select (0),
+ .pll_type (xaui_pll_type),
+ .starting_channel_number (starting_channel_number),
+ .bonded_mode ("TRUE"),
+ .sys_clk_in_mhz (sys_clk_in_mhz),
+ //.rx_bitslip_en (0),
+ //.tx_bitslip_en (0),
+ //.select_10g_pcs (0),
+ //.tx_use_coreclk (0),
+ //.rx_use_coreclk (0),
+ .gx_analog_power ("AUTO"),
+ .pll_lock_speed ("AUTO"),
+ .tx_analog_power ("AUTO"),
+ .tx_slew_rate ("OFF"),
+ .tx_termination (tx_termination),
+ .tx_common_mode ("0.65V"),
+ .rx_pll_lock_speed ("AUTO"),
+ .rx_common_mode (rx_common_mode),
+ .rx_signal_detect_threshold (2),
+ .rx_ppmselect (32),
+ .rx_termination (rx_termination),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv ((tx_preemp_pretap_inv==1)? "TRUE" : "FALSE"),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv ((tx_preemp_tap_2_inv==1)? "TRUE" : "FALSE"),
+ .tx_vod_selection (tx_vod_selection),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .rx_use_cruclk ("FALSE"),
+ .loopback_mode ("SLB")
+ ) alt_pma_0 (
+ .clk (phy_mgmt_clk),
+ .rst (phy_mgmt_clk_reset),
+ .gx_pdn (alt_pma_controller_0_gx_pdn_data),
+ .ch_mgmt_address (sc_pma_ch_controller_address),
+ .ch_mgmt_read (sc_pma_ch_controller_read),
+ .ch_mgmt_readdata (sc_pma_ch_controller_readdata),
+ .ch_mgmt_write (sc_pma_ch_controller_write),
+ .ch_mgmt_writedata (phy_mgmt_writedata),
+ .ch_mgmt_waitrequest (sc_pma_ch_controller_waitrequest),
+ .cal_blk_clk (phy_mgmt_clk),
+ .cal_blk_pdn (alt_pma_controller_0_cal_blk_pdn_data),
+ .pll_ref_clk (pll_ref_clk),
+ .tx_out_clk (alt_pma_0_tx_out_clk_clk),
+ .tx_parallel_data (sxaui_0_tx_parallel_data_data),
+ .tx_serial_data (xaui_tx_serial_data),
+ .tx_pma_ready (tx_ready),
+ .pll_pdn (alt_pma_controller_0_pll_pdn0_data),
+ .pll_locked (pll_locked_data),
+ .rx_is_lockedtodata (alt_pma_0_rx_is_lockedtodata_data),
+ .rx_is_lockedtoref (),
+ .rx_recovered_clk (alt_pma_0_rx_recovered_clk_clk),
+ .rx_serial_data (xaui_rx_serial_data),
+ .rx_parallel_data (alt_pma_0_rx_parallel_data_data),
+ .rx_cdr_ref_clk (),
+ .rx_pma_ready (rx_pma_ready),
+ .reconfig_clk (phy_mgmt_clk),
+ .reconfig_to_gxb (reconfig_to_xcvr),
+ .reconfig_from_gxb (reconfig_from_xcvr),
+ .rx_rst_digital (rx_digitalreset), //optional user triggered rx_digitalreset
+ .tx_rst_digital (tx_digitalreset), //optional user triggered tx_digitalreset
+ //.tx_bitslip (28'b0),
+ //.tx_coreclk (4'b0),
+ //.rx_offset_cancellation_done (1'b1),
+ //.rx_bitslip (4'b0),
+ //.rx_parallel_data_read (4'b0),
+ //.rx_coreclk (4'b0),
+ //.aeq_to_gxb (96'b0),
+ //.aeq_from_gxb (),
+ .tx_digital_rst (alt_pma_ch_controller_0_tx_digital_rst_data),
+ .rx_digital_rst (alt_pma_ch_controller_0_rx_digital_rst_data)
+ );
+ end
+ // don't instantiate anything if the interface type is invalid
+ endgenerate
+
+ ///////////////////////////////////////////////////////////////////////
+ // PMA Controller
+ ///////////////////////////////////////////////////////////////////////
+ generate
+ if (external_pma_ctrl_reconf == 0) begin
+ alt_pma_controller_tgx #(
+ .number_of_plls (1),
+ .sync_depth (2),
+ .tx_pll_reset_hold_time (20)
+ ) alt_pma_controller_0 (
+ .clk (phy_mgmt_clk),
+ .rst (phy_mgmt_clk_reset),
+ .pma_mgmt_address (sc_pma_controller_address),
+ .pma_mgmt_read (sc_pma_controller_read),
+ .pma_mgmt_readdata (sc_pma_controller_readdata),
+ .pma_mgmt_write (sc_pma_controller_write),
+ .pma_mgmt_writedata (phy_mgmt_writedata),
+ .pma_mgmt_waitrequest (sc_pma_controller_waitrequest),
+ .cal_blk_clk (phy_mgmt_clk),
+ .cal_blk_pdn (alt_pma_controller_0_cal_blk_pdn_data),
+ .tx_pll_ready (),
+ .gx_pdn (alt_pma_controller_0_gx_pdn_data),
+ .pll_pdn (alt_pma_controller_0_pll_pdn0_data),
+ .pll_locked (pll_locked_data)
+ );
+ end else begin
+ assign alt_pma_controller_0_cal_blk_pdn_data = cal_blk_powerdown;
+ assign alt_pma_controller_0_gx_pdn_data = gxb_powerdown;
+ assign alt_pma_controller_0_pll_pdn0_data = pll_powerdown;
+ end
+ endgenerate
+
+
+ ///////////////////////////////////////////////////////////////////////
+ // HXAUI CSR
+ ///////////////////////////////////////////////////////////////////////
+// should be consistent across all device families and interface types
+// -might need a generate statement for some of the connections that don't exist between hxaui/sxaui
+ hxaui_csr hxaui_csr (
+ .clk (phy_mgmt_clk),
+ .reset (phy_mgmt_clk_reset),
+ .address (sc_csr_address),
+ .byteenable (4'b1111), // .byteenable (Tie byteenable to all 1s)
+ .read (sc_csr_read),
+ .readdata (sc_csr_readdata),
+ .write (sc_csr_write),
+ .writedata (phy_mgmt_writedata),
+ .rx_patterndetect (rx_patterndetect_data),
+ .rx_syncstatus (rx_syncstatus_data),
+ .rx_runningdisp (rx_runningdisp_data),
+ .rx_errdetect (rx_errdetect_data),
+ .rx_disperr (rx_disperr_data),
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error_data),
+ .rx_rlv (rx_rlv_data),
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted_data),
+ .rx_rmfifodatainserted (rx_rmfifodatainserted_data),
+ .rx_rmfifoempty (rx_rmfifoempty_data),
+ .rx_rmfifofull (rx_rmfifofull_data),
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error_data),
+ .r_rx_invpolarity (hxaui_csr_r_rx_invpolarity_data),
+ .r_tx_invpolarity (hxaui_csr_r_tx_invpolarity_data),
+ .r_rx_digitalreset (hxaui_csr_r_rx_digitalreset_data),
+ .r_tx_digitalreset (hxaui_csr_r_tx_digitalreset_data),
+ .simulation_flag (hxaui_csr_simulation_flag_data) // only for soft_xaui
+ );
+
+
+ ///////////////////////////////////////////////////////////////////////
+ // HXAUI - Interface to alt4gxb megafunction block
+ ///////////////////////////////////////////////////////////////////////
+// need to add generate to pick between sxaui and hxaui
+ generate
+ if (interface_type == "Hard XAUI") begin
+ (* ALTERA_ATTRIBUTE = {"-name SDC_STATEMENT \"set_false_path -from [get_registers *hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component*fifo*flow] -to [get_registers *xaui_phy*hxaui_csr*tx_phase_comp_fifo_error_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers *hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component*] -to [get_registers *xaui_phy*hxaui_csr*rx*_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*siv_xcvr_xaui*hxaui_csr*hxaui_csr_reset0q[*]}] -to [get_registers {*xaui_phy*hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component|*digitalreset*}]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*siv_xcvr_xaui*alt_pma_ch_controller_0*rc*}] -to [get_registers {*xaui_phy*hxaui_0*hxaui_alt4gxb*hxaui_alt4gxb_alt4gxb_dksa_component|*digitalreset*}]\""} *)
+ hxaui #(
+ .device_family (device_family),
+ .starting_channel_number (starting_channel_number),
+ .xaui_pll_type (xaui_pll_type),
+ .use_control_and_status_ports (use_control_and_status_ports),
+ .external_pma_ctrl_reconf (external_pma_ctrl_reconf),
+ .tx_termination (tx_termination),
+ .rx_termination (rx_termination),
+ .tx_preemp_pretap (tx_preemp_pretap),
+ .tx_preemp_pretap_inv (tx_preemp_pretap_inv),
+ .tx_preemp_tap_1 (tx_preemp_tap_1),
+ .tx_preemp_tap_2 (tx_preemp_tap_2),
+ .tx_preemp_tap_2_inv (tx_preemp_tap_2_inv),
+ .tx_vod_selection (tx_vod_selection),
+ .rx_eq_dc_gain (rx_eq_dc_gain),
+ .rx_eq_ctrl (rx_eq_ctrl),
+ .rx_common_mode (rx_common_mode)
+ ) hxaui_0 (
+ .xgmii_tx_clk (xgmii_tx_clk),
+ .xgmii_tx_dc (xgmii_tx_dc),
+ .xgmii_rx_clk (xgmii_rx_clk),
+ .xgmii_rx_dc (xgmii_rx_dc),
+ .refclk (pll_ref_clk),
+ .xaui_tx_serial (xaui_tx_serial_data),
+ .xaui_rx_serial (xaui_rx_serial_data),
+ .rx_analogreset (rx_analogreset), // use_cs_ports, input
+ .rx_digitalreset (alt_pma_ch_controller_0_rx_digital_rst_data),
+ .tx_digitalreset (alt_pma_ch_controller_0_tx_digital_rst_data),
+ .rx_channelaligned (rx_channelaligned), // use_cs_ports, output
+ .rx_invpolarity (rx_invpolarity), // use_cs_ports, input
+ .rx_set_locktodata (rx_set_locktodata), // use_cs_ports, input
+ .rx_set_locktoref (rx_set_locktoref), // use_cs_ports, input
+ .rx_seriallpbken (rx_seriallpbken), // use_cs_ports, input
+ .tx_invpolarity (tx_invpolarity), // use_cs_ports, input
+ .rx_is_lockedtodata (rx_is_lockedtodata_data), // use_cs_ports, output
+ .rx_phase_comp_fifo_error (rx_phase_comp_fifo_error_data), // use_cs_ports, output
+ .rx_is_lockedtoref (rx_is_lockedtoref_data), // use_cs_ports, output
+ .rx_rlv (rx_rlv_data), // use_cs_ports, output
+ .rx_rmfifoempty (rx_rmfifoempty_data), // use_cs_ports, output
+ .rx_rmfifofull (rx_rmfifofull_data), // use_cs_ports, output
+ .tx_phase_comp_fifo_error (tx_phase_comp_fifo_error_data), // use_cs_ports, output
+ .rx_disperr (rx_disperr_data), // use_cs_ports, output
+ .rx_errdetect (rx_errdetect_data), // use_cs_ports, output
+ .rx_patterndetect (rx_patterndetect_data), // use_cs_ports, output
+ .rx_rmfifodatadeleted (rx_rmfifodatadeleted_data), // use_cs_ports, output
+ .rx_rmfifodatainserted (rx_rmfifodatainserted_data), // use_cs_ports, output
+ .rx_runningdisp (rx_runningdisp_data), // use_cs_ports, output
+ .rx_syncstatus (rx_syncstatus_data), // use_cs_ports, output
+ .reconfig_clk (phy_mgmt_clk),
+ .reconfig_togxb (reconfig_to_xcvr), // external_pma_ctrl_reconf
+ .reconfig_fromgxb (reconfig_from_xcvr[16:0]), // external_pma_ctrl_reconf
+ .rx_recovered_clk (alt_pma_0_rx_recovered_clk_clk),
+ .cal_blk_clk (phy_mgmt_clk),
+ .cal_blk_powerdown (1'b0), // not used, should remove
+ .gxb_powerdown (1'b0), // not used, should remove
+ .pll_powerdown (1'b0), // not used, should remove
+ .pll_locked (pll_locked_data),
+ .r_cal_blk_powerdown (alt_pma_controller_0_cal_blk_pdn_data),
+ .r_gxb_powerdown (alt_pma_controller_0_gx_pdn_data),
+ .r_pll_powerdown (alt_pma_controller_0_pll_pdn0_data),
+ .r_rx_set_locktodata (alt_pma_ch_controller_0_rx_set_locktodata_data),
+ .r_rx_set_locktoref (alt_pma_ch_controller_0_rx_set_locktoref_data),
+ .r_rx_seriallpbken (alt_pma_ch_controller_0_rx_seriallpbken_data),
+ .r_rx_analogreset (alt_pma_ch_controller_0_rx_analog_rst_data),
+ .r_rx_digitalreset (hxaui_csr_r_rx_digitalreset_data),
+ .r_tx_digitalreset (hxaui_csr_r_tx_digitalreset_data),
+ .r_rx_invpolarity (hxaui_csr_r_rx_invpolarity_data),
+ .r_tx_invpolarity (hxaui_csr_r_tx_invpolarity_data)
+ );
+ assign sxaui_rst_done = 1'b1; // if using hard xaui, assign this to 1 to always be ready
+ end else if (interface_type == "Soft XAUI") begin
+ (* ALTERA_ATTRIBUTE = {" -name SDC_STATEMENT \"set_false_path -from [get_registers {*sxaui_0*alt_soft_xaui_pcs*xaui_rx*disp_err_delay[*]}] -to [get_registers *xaui_phy*hxaui_csr*rx*_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*sxaui_0*alt_soft_xaui_pcs*xaui_rx*pcs_rx_syncstatus[*]}] -to [get_registers *xaui_phy*hxaui_csr*rx*_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*sxaui_0*alt_soft_xaui_pcs*xaui_rx*channel_align_synchclk[*]}] -to [get_registers *xaui_phy*hxaui_csr*rx*_c[*]]\" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*siv_xcvr_xaui*hxaui_csr*hxaui_csr_reset0q[1]}] -to [get_registers *sxaui_0*alt_soft_xaui_pcs*tx_reset*] \" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*siv_xcvr_xaui*hxaui_csr*hxaui_csr_reset0q[1]}] -to [get_registers *sxaui_0*alt_soft_xaui_pcs*rx_reset*] \" ;-name SDC_STATEMENT \"set_false_path -from [get_registers {*sxaui_0*alt_soft_xaui_pcs*xaui_rx*rd_ptr_latched_del[*]}] -to [get_registers *sxaui_0*alt_soft_xaui_pcs*xaui_rx*rd_ptr_wr[*]]\""} *)
+ sxaui #(
+ .starting_channel_number (starting_channel_number),
+ .xaui_pll_type (xaui_pll_type),
+ .use_control_and_status_ports (use_control_and_status_ports)
+ ) sxaui_0 (
+ .xgmii_tx_clk (xgmii_tx_clk), // xgmii_tx_clk.clk
+ .xgmii_tx_dc (xgmii_tx_dc), // xgmii_tx_dc.data
+ .xgmii_rx_clk (xgmii_rx_clk), // xgmii_rx_clk.clk
+ .xgmii_rx_dc (xgmii_rx_dc), // xgmii_rx_dc.data
+ .refclk (pll_ref_clk), // refclk.clk
+ .mgmt_clk (phy_mgmt_clk), // mgmt_clk.clk
+ .tx_out_clk (alt_pma_0_tx_out_clk_clk), // tx_out_clk.clk
+ .rx_recovered_clk (alt_pma_0_rx_recovered_clk_clk), // rx_recovered_clk.clk
+ .tx_parallel_data (sxaui_0_tx_parallel_data_data), // tx_parallel_data.data
+ .rx_parallel_data (alt_pma_0_rx_parallel_data_data), // rx_parallel_data.data
+ .rx_is_lockedtodata (alt_pma_0_rx_is_lockedtodata_data), // rx_is_lockedtodata.data
+ .rx_digitalreset (alt_pma_ch_controller_0_rx_digital_rst_data[0] ), // rx_digitalreset from cahnnel controller in alt_pma
+ .tx_digitalreset (alt_pma_ch_controller_0_tx_digital_rst_data[0] ), // tx_digitalreset from cahnnel controller in alt_pma
+ .pll_locked (pll_locked_data), // pll_locked.data
+ .rx_syncstatus (rx_syncstatus_data), // rx_syncstatus.data
+ .rx_channelaligned (rx_channelaligned), // rx_channelaligned.data
+ .rx_disperr (rx_disperr_data), // rx_disperr.data
+ .rx_errdetect (rx_errdetect_data), // rx_errdetect.data
+ .r_rx_digitalreset (hxaui_csr_r_rx_digitalreset_data), // r_rx_digitalreset.data
+ .r_tx_digitalreset (hxaui_csr_r_tx_digitalreset_data), // r_tx_digitalreset.data
+ .pma_stat_rst_done (sxaui_rst_done), // soft reset done
+ .simulation_flag (hxaui_csr_simulation_flag_data) // simulation_flag.data
+ );
+ assign rx_patterndetect_data = 8'b0; // not supported by soft PCS
+ assign rx_runningdisp_data = 8'b0; // not supported by soft PCS
+ assign rx_phase_comp_fifo_error_data = 4'b0; // not supported by soft PCS
+ assign rx_rlv_data = 4'b0; // not supported by soft PCS
+ assign rx_rmfifodatadeleted_data = 8'b0; // not supported by soft PCS
+ assign rx_rmfifodatainserted_data = 8'b0; // not supported by soft PCS
+ assign rx_rmfifoempty_data = 4'b0; // not supported by soft PCS
+ assign rx_rmfifofull_data = 4'b0; // not supported by soft PCS
+ assign tx_phase_comp_fifo_error_data = 4'b0; // not supported by soft PCS
+ assign hxaui_csr_r_rx_invpolarity_data = 4'b0; // not supported by soft PCS
+ assign hxaui_csr_r_tx_invpolarity_data = 4'b0; // not supported by soft PCS
+ assign rx_is_lockedtodata_data = 4'b0; // not supported by soft PCS
+ assign rx_is_lockedtoref_data = 4'b0; // not supported by soft PCS
+ end
+ // don't instantiate anything if the interface type is invalid
+ endgenerate
+
+endmodule
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/sxaui.v b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/sxaui.v
new file mode 100644
index 0000000000000000000000000000000000000000..d0832e15d12cf3ef8977dcce01ac2f75f7947cae
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/sxaui.v
@@ -0,0 +1,230 @@
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//-----------------------------------------------------------------------------
+//
+// Description: soft xaui pcs
+//
+// Authors: ishimony 14-Jan-2009
+//
+// Copyright (c) Altera Corporation 1997 - 2009
+// All rights reserved.
+//
+//
+//-----------------------------------------------------------------------------
+
+`timescale 1 ps / 1 ps
+
+module sxaui(
+ xgmii_tx_clk, xgmii_tx_dc, xgmii_rx_clk, xgmii_rx_dc, refclk, mgmt_clk, tx_out_clk,
+ rx_recovered_clk, tx_parallel_data, rx_parallel_data, rx_is_lockedtodata,
+ rx_digitalreset, tx_digitalreset, pll_locked,
+ rx_syncstatus, rx_channelaligned, rx_disperr, rx_errdetect,
+ r_rx_digitalreset, r_tx_digitalreset, pma_stat_rst_done, simulation_flag
+); // module sxaui
+
+// parameters --------------------------------------------------------------
+parameter starting_channel_number = 0;
+parameter xaui_pll_type = "CMU"; // values: CMU/LCTANK
+parameter use_control_and_status_ports = "true";
+
+// ports -------------------------------------------------------------------
+
+// xgmii
+input xgmii_tx_clk;
+input [71:0] xgmii_tx_dc;
+output xgmii_rx_clk;
+output [71:0] xgmii_rx_dc;
+
+// pma
+input refclk;
+input mgmt_clk;
+input [3:0] tx_out_clk;
+input [3:0] rx_recovered_clk;
+output [79:0] tx_parallel_data;
+input [79:0] rx_parallel_data;
+input [3:0] rx_is_lockedtodata;
+
+// ctrl_stat: control and status
+input rx_digitalreset;
+input tx_digitalreset; //nc in sxaui
+input pll_locked;
+output [7:0] rx_syncstatus;
+output rx_channelaligned;
+output [7:0] rx_disperr;
+output [7:0] rx_errdetect;
+
+// register file version
+input r_rx_digitalreset;
+input r_tx_digitalreset;
+output pma_stat_rst_done;
+
+input simulation_flag; // '1' shortens reset and loss_timer length
+
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+
+// ports -------------------------------------------------------------------
+wire xgmii_tx_clk;
+wire [71:0] xgmii_tx_dc;
+wire [71:0] xgmii_rx_dc;
+wire xgmii_rx_clk;
+wire [79:0] tx_parallel_data;
+wire [79:0] rx_parallel_data;
+wire [3:0] tx_out_clk;
+wire [3:0] rx_recovered_clk;
+wire [3:0] rx_is_lockedtodata;
+wire rx_digitalreset;
+wire tx_digitalreset;
+wire pll_locked;
+wire [7:0] rx_syncstatus;
+wire rx_channelaligned;
+wire [7:0] rx_disperr;
+wire [7:0] rx_errdetect;
+wire simulation_flag;
+
+// locals ------------------------------------------------------------------
+wire [7:0] xgmii_tx_c;
+wire [63:0] xgmii_tx_d;
+wire [7:0] xgmii_rx_c;
+wire [63:0] xgmii_rx_d;
+
+// local version
+wire l_rx_digitalreset;
+
+// register file version
+wire r_rx_digitalreset;
+wire r_tx_digitalreset;
+
+// soft xaui signals -------------------------------------------------------
+wire [63:0] xgmii_tx_datain; // input
+wire [7:0] xgmii_tx_ctrlin; // input
+wire [63:0] xgmii_rx_dataout; // output
+wire [7:0] xgmii_rx_ctrlout; // output
+wire reset_n; // input
+wire [3:0] pma_tx_dataout; // output
+//wire pma_gxb_powerdown; // input
+wire pma_pll_inclk; // input
+wire pma_reconfig_clk; // input
+wire [3:0] pma_reconfig_togxb; // input
+wire [16:0] pma_reconfig_fromgxb; // output
+wire pma_pll_locked; // output
+wire pma_stat_rst_done; // output
+wire [3:0] pma_rx_clkout; // output nc: ///
+wire [3:0] pma_tx_clkout; // output nc: ///
+wire pma_rx_analogreset;
+wire [79:0] pma_pcs_tx_data; //Data from TX soft PCS to PMA
+wire [79:0] pma_pcs_rx_data; //Data from PMA to RX soft PCS
+wire [3:0] pma_rx_is_lockedtodata;
+
+// output: this is high per lane if the synchronization has been met. As we
+// only have 4 lanes, we will double their value
+wire [7:0] pcs_rx_syncstatus;
+// output: this is high if the channel aligner (resynch) has aligned all
+// the lanes and the correct number of align characters have been received
+wire pcs_rx_channelaligned;
+// output: this is high if a disparity error has occured
+wire [7:0] pcs_rx_disperr;
+// output: this is high if an invalid character has been detected.
+wire [7:0] pcs_rx_errdetect;
+
+// body --------------------------------------------------------------------
+
+// Convert to/from Avalon Streaming Interface single bus to data + control
+genvar g;
+generate
+ for (g = 0; g < 8; g = g + 1) begin : st_to_dc_b
+ assign xgmii_tx_d [g*8 +: 8] = xgmii_tx_dc[g*9 +: 8];
+ assign xgmii_tx_c [g] = xgmii_tx_dc[g*9 + 8];
+ assign xgmii_rx_dc[g*9 +: 8] = xgmii_rx_d [g*8 +: 8];
+ assign xgmii_rx_dc[g*9 + 8] = xgmii_rx_c [g];
+ end
+endgenerate
+
+// Default values in case ports are not and without control/status registers
+generate
+ if (use_control_and_status_ports == "true") begin: use_cs_ports_true
+ assign l_rx_digitalreset = rx_digitalreset | r_rx_digitalreset;
+ end else begin: use_cs_ports_false
+ assign l_rx_digitalreset = r_rx_digitalreset;
+ end
+endgenerate
+
+// soft xaui ---------------------------------------------------------------
+
+ // translate signal names
+assign xgmii_tx_datain = xgmii_tx_d;
+assign xgmii_tx_ctrlin = xgmii_tx_c;
+assign xgmii_rx_d = xgmii_rx_dataout;
+assign xgmii_rx_c = xgmii_rx_ctrlout;
+assign pma_pll_inclk = refclk;
+
+assign tx_parallel_data = pma_pcs_tx_data;
+assign pma_pcs_rx_data = rx_parallel_data;
+assign pma_tx_clkout = tx_out_clk;
+assign pma_rx_clkout = rx_recovered_clk;
+assign pma_rx_is_lockedtodata = rx_is_lockedtodata;
+
+assign reset_n = ~l_rx_digitalreset;
+assign pma_pll_locked = pll_locked;
+
+assign rx_syncstatus = pcs_rx_syncstatus;
+assign rx_channelaligned = pcs_rx_channelaligned;
+assign rx_disperr = pcs_rx_disperr;
+assign rx_errdetect = pcs_rx_errdetect;
+
+//assign pma_gxb_powerdown = 1'b0;
+
+// soft pcs
+alt_soft_xaui_pcs alt_soft_xaui_pcs(
+ .xgmii_tx_datain (xgmii_tx_datain), // i
+ .xgmii_tx_ctrlin (xgmii_tx_ctrlin), // i
+ .xgmii_rx_dataout (xgmii_rx_dataout), // o
+ .xgmii_rx_ctrlout (xgmii_rx_ctrlout), // o
+ .xgmii_tx_clk (xgmii_tx_clk), // i - must be tied to xgmii_rx_clk at top level, only for interface consistency does this exist
+ .sysclk (xgmii_rx_clk), // o
+ .reset_n (reset_n), // i
+// .pma_rx_datain (pma_rx_datain), // i
+// .pma_tx_dataout (pma_tx_dataout), // o
+// .pma_cal_blk_clk (pma_cal_blk_clk), // i
+// .pma_gxb_powerdown (pma_gxb_powerdown), // i
+ .pma_pll_inclk (pma_pll_inclk), // i
+// .pma_reconfig_clk (pma_reconfig_clk), // i
+// .pma_reconfig_togxb (pma_reconfig_togxb), // i
+// .pma_reconfig_fromgxb (pma_reconfig_fromgxb), // o
+ .pma_pll_locked (pma_pll_locked), // i
+// .pma_rx_pll_locked (pma_rx_is_lockedtoref), // i
+ .pma_rx_freqlocked (pma_rx_is_lockedtodata), // i
+ .pma_stat_rst_done (pma_stat_rst_done), // o
+ .pma_rx_clkout (pma_rx_clkout), // i
+ .pma_tx_clkout (pma_tx_clkout), // i
+ .pcs_rx_syncstatus (pcs_rx_syncstatus), // o
+ .pcs_rx_channelaligned (pcs_rx_channelaligned), // o
+ .pcs_rx_disperr (pcs_rx_disperr), // o
+ .pcs_rx_errdetect (pcs_rx_errdetect), // o
+ .pma_rx_analogreset (pma_rx_analogreset), // o
+ .pma_pcs_tx_data (pma_pcs_tx_data), // o
+ .pma_pcs_rx_data (pma_pcs_rx_data), // i
+ .simulation_flag (simulation_flag) // i
+); // module alt_soft_xaui_pcs
+defparam
+ alt_soft_xaui_pcs.p_family_id = "df_stratixIV",
+ alt_soft_xaui_pcs.p_USE_GXB_RECONFIG = 0,
+ alt_soft_xaui_pcs.starting_channel_number= starting_channel_number,
+ alt_soft_xaui_pcs.reconfig_togxb_port_size = 4,
+ alt_soft_xaui_pcs.reconfig_fromgxb_port_size = 17,
+ alt_soft_xaui_pcs.p_SOFTXAUI_PLL = xaui_pll_type; // CMU/LCTANK
+
+endmodule
+
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/synopsys_files.txt b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/synopsys_files.txt
new file mode 100644
index 0000000000000000000000000000000000000000..4bd73c0085a4e1232356cb606fc036f1fe99b4e0
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/altera_xcvr_xaui/synopsys_files.txt
@@ -0,0 +1,59 @@
+./altera_xcvr_functions.sv
+./alt_pma_functions.sv
+./altera_xcvr_xaui.sv
+./hxaui_csr_h.sv
+./hxaui_csr.sv
+./alt_xcvr_mgmt2dec_phyreconfig.sv
+./alt_xcvr_mgmt2dec_xaui.sv
+./alt_pma_ch_controller_tgx.v
+./alt_pma_controller_tgx.v
+./alt_reset_ctrl_lego.sv
+./alt_reset_ctrl_tgx_cdrauto.sv
+./alt_xcvr_resync.sv
+./alt_xcvr_csr_common_h.sv
+./alt_xcvr_csr_common.sv
+./alt_xcvr_csr_pcs8g_h.sv
+./alt_xcvr_csr_pcs8g.sv
+./alt_xcvr_csr_selector.sv
+./alt_xcvr_mgmt2dec.sv
+./altera_wait_generate.v
+./synopsys/alt_soft_xaui_pcs.v
+./synopsys/alt_soft_xaui_reset.v
+./synopsys/alt_soft_xaui_rx.v
+./synopsys/alt_soft_xaui_rx_8b10b_dec.v
+./synopsys/alt_soft_xaui_rx_channel_synch.v
+./synopsys/alt_soft_xaui_rx_deskew.v
+./synopsys/alt_soft_xaui_rx_deskew_channel.v
+./synopsys/alt_soft_xaui_rx_deskew_ram.v
+./synopsys/alt_soft_xaui_rx_invalid_code_det.v
+./synopsys/alt_soft_xaui_rx_parity.v
+./synopsys/alt_soft_xaui_rx_parity_4b.v
+./synopsys/alt_soft_xaui_rx_parity_6b.v
+./synopsys/alt_soft_xaui_rx_rate_match.v
+./synopsys/alt_soft_xaui_rx_rate_match_ram.v
+./synopsys/alt_soft_xaui_rx_rl_chk_6g.v
+./synopsys/alt_soft_xaui_rx_sm.v
+./synopsys/alt_soft_xaui_tx.v
+./synopsys/alt_soft_xaui_tx_8b10b_enc.v
+./synopsys/alt_soft_xaui_tx_idle_conv.v
+./synopsys/l_modules.v
+./synopsys/serdes_4_unit_lc_siv.v
+./synopsys/serdes_4_unit_siv.v
+./synopsys/serdes_4unit.v
+./sxaui.v
+./siv_xcvr_low_latency_phy_nr.sv
+./siv_xcvr_xaui.sv
+./alt4gxb_vo.v
+./alt_xcvr_reconfig_h.sv
+./alt_xcvr_reconfig_siv.sv
+./alt_xcvr_reconfig_analog.sv
+./alt_xcvr_reconfig_analog_tgx.v
+./alt_xcvr_reconfig_offset_cancellation.sv
+./alt_xcvr_reconfig_offset_cancellation_tgx.v
+./alt_xcvr_reconfig_eyemon_tgx.sv
+./alt_xcvr_reconfig_dfe_tgx.sv
+./alt_xcvr_reconfig_basic_tgx.v
+./alt_mutex_acq.v
+./alt_dprio.v
+./alt_xcvr_arbiter.sv
+./alt_xcvr_m2s.sv
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/ip_stratixiv_phy_xaui_soft.vhd b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/ip_stratixiv_phy_xaui_soft.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2975d799b3b68a98ce7a88f1eb09c715928250ae
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/ip_stratixiv_phy_xaui_soft.vhd
@@ -0,0 +1,169 @@
+-- ip_stratixiv_phy_xaui_soft.vhd
+
+-- Generated using ACDS version 11.1sp2 259 at 2014.09.29.14:01:40
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ip_stratixiv_phy_xaui_soft is
+ port (
+ pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
+ xgmii_tx_clk : in std_logic := '0'; -- xgmii_tx_clk.clk
+ xgmii_rx_clk : out std_logic; -- xgmii_rx_clk.clk
+ xgmii_rx_dc : out std_logic_vector(71 downto 0); -- xgmii_rx_dc.data
+ xgmii_tx_dc : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_tx_dc.data
+ xaui_rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- xaui_rx_serial_data.export
+ xaui_tx_serial_data : out std_logic_vector(3 downto 0); -- xaui_tx_serial_data.export
+ rx_ready : out std_logic; -- rx_ready.export
+ tx_ready : out std_logic; -- tx_ready.export
+ phy_mgmt_clk : in std_logic := '0'; -- phy_mgmt_clk.clk
+ phy_mgmt_clk_reset : in std_logic := '0'; -- phy_mgmt_clk_reset.reset
+ phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => '0'); -- phy_mgmt.address
+ phy_mgmt_read : in std_logic := '0'; -- .read
+ phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ phy_mgmt_write : in std_logic := '0'; -- .write
+ phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ phy_mgmt_waitrequest : out std_logic; -- .waitrequest
+ rx_digitalreset : in std_logic := '0'; -- rx_digitalreset.data
+ tx_digitalreset : in std_logic := '0'; -- tx_digitalreset.data
+ rx_channelaligned : out std_logic; -- rx_channelaligned.data
+ rx_syncstatus : out std_logic_vector(7 downto 0); -- rx_syncstatus.data
+ rx_disperr : out std_logic_vector(7 downto 0); -- rx_disperr.data
+ rx_errdetect : out std_logic_vector(7 downto 0); -- rx_errdetect.data
+ cal_blk_powerdown : in std_logic := '0'; -- cal_blk_powerdown.data
+ pll_powerdown : in std_logic := '0'; -- pll_powerdown.data
+ gxb_powerdown : in std_logic := '0'; -- gxb_powerdown.data
+ pll_locked : out std_logic; -- pll_locked.data
+ reconfig_from_xcvr : out std_logic_vector(67 downto 0); -- reconfig_from_xcvr.data
+ reconfig_to_xcvr : in std_logic_vector(3 downto 0) := (others => '0') -- reconfig_to_xcvr.data
+ );
+end entity ip_stratixiv_phy_xaui_soft;
+
+architecture rtl of ip_stratixiv_phy_xaui_soft is
+ component altera_xcvr_xaui is
+ generic (
+ device_family : string := "Stratix IV";
+ starting_channel_number : integer := 0;
+ interface_type : string := "Hard XAUI";
+ data_rate : string := "3125 Mbps";
+ xaui_pll_type : string := "AUTO";
+ BASE_DATA_RATE : string := "";
+ use_control_and_status_ports : integer := 0;
+ external_pma_ctrl_reconf : integer := 0;
+ recovered_clk_out : integer := 0;
+ number_of_interfaces : integer := 1;
+ reconfig_interfaces : integer := 1;
+ use_rx_rate_match : integer := 0;
+ tx_termination : string := "OCT_100_OHMS";
+ tx_vod_selection : integer := 4;
+ tx_preemp_pretap : integer := 0;
+ tx_preemp_pretap_inv : integer := 0;
+ tx_preemp_tap_1 : integer := 0;
+ tx_preemp_tap_2 : integer := 0;
+ tx_preemp_tap_2_inv : integer := 0;
+ rx_common_mode : string := "0.82v";
+ rx_termination : string := "OCT_100_OHMS";
+ rx_eq_dc_gain : integer := 0;
+ rx_eq_ctrl : integer := 0;
+ mgmt_clk_in_mhz : integer := 150
+ );
+ port (
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ xgmii_tx_clk : in std_logic := 'X'; -- clk
+ xgmii_rx_clk : out std_logic; -- clk
+ xgmii_rx_dc : out std_logic_vector(71 downto 0); -- data
+ xgmii_tx_dc : in std_logic_vector(71 downto 0) := (others => 'X'); -- data
+ xaui_rx_serial_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ xaui_tx_serial_data : out std_logic_vector(3 downto 0); -- export
+ rx_ready : out std_logic; -- export
+ tx_ready : out std_logic; -- export
+ phy_mgmt_clk : in std_logic := 'X'; -- clk
+ phy_mgmt_clk_reset : in std_logic := 'X'; -- reset
+ phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
+ phy_mgmt_read : in std_logic := 'X'; -- read
+ phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- readdata
+ phy_mgmt_write : in std_logic := 'X'; -- write
+ phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ phy_mgmt_waitrequest : out std_logic; -- waitrequest
+ rx_digitalreset : in std_logic := 'X'; -- data
+ tx_digitalreset : in std_logic := 'X'; -- data
+ rx_channelaligned : out std_logic; -- data
+ rx_syncstatus : out std_logic_vector(7 downto 0); -- data
+ rx_disperr : out std_logic_vector(7 downto 0); -- data
+ rx_errdetect : out std_logic_vector(7 downto 0); -- data
+ cal_blk_powerdown : in std_logic := 'X'; -- data
+ pll_powerdown : in std_logic := 'X'; -- data
+ gxb_powerdown : in std_logic := 'X'; -- data
+ pll_locked : out std_logic; -- data
+ reconfig_from_xcvr : out std_logic_vector(67 downto 0); -- data
+ reconfig_to_xcvr : in std_logic_vector(3 downto 0) := (others => 'X'); -- data
+ rx_recovered_clk : out std_logic_vector(3 downto 0); -- export
+ tx_clk312_5 : out std_logic -- export
+ );
+ end component altera_xcvr_xaui;
+
+begin
+
+ ip_stratixiv_phy_xaui_soft_inst : component altera_xcvr_xaui
+ generic map (
+ device_family => "Stratix IV",
+ starting_channel_number => 12,
+ interface_type => "Soft XAUI",
+ data_rate => "3125 Mbps",
+ xaui_pll_type => "ATX",
+ BASE_DATA_RATE => "",
+ use_control_and_status_ports => 1,
+ external_pma_ctrl_reconf => 1,
+ recovered_clk_out => 0,
+ number_of_interfaces => 1,
+ reconfig_interfaces => 4,
+ use_rx_rate_match => 0,
+ tx_termination => "OCT_100_OHMS",
+ tx_vod_selection => 4,
+ tx_preemp_pretap => 0,
+ tx_preemp_pretap_inv => 0,
+ tx_preemp_tap_1 => 0,
+ tx_preemp_tap_2 => 0,
+ tx_preemp_tap_2_inv => 0,
+ rx_common_mode => "0.82v",
+ rx_termination => "OCT_100_OHMS",
+ rx_eq_dc_gain => 0,
+ rx_eq_ctrl => 0,
+ mgmt_clk_in_mhz => 150
+ )
+ port map (
+ pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk
+ xgmii_tx_clk => xgmii_tx_clk, -- xgmii_tx_clk.clk
+ xgmii_rx_clk => xgmii_rx_clk, -- xgmii_rx_clk.clk
+ xgmii_rx_dc => xgmii_rx_dc, -- xgmii_rx_dc.data
+ xgmii_tx_dc => xgmii_tx_dc, -- xgmii_tx_dc.data
+ xaui_rx_serial_data => xaui_rx_serial_data, -- xaui_rx_serial_data.export
+ xaui_tx_serial_data => xaui_tx_serial_data, -- xaui_tx_serial_data.export
+ rx_ready => rx_ready, -- rx_ready.export
+ tx_ready => tx_ready, -- tx_ready.export
+ phy_mgmt_clk => phy_mgmt_clk, -- phy_mgmt_clk.clk
+ phy_mgmt_clk_reset => phy_mgmt_clk_reset, -- phy_mgmt_clk_reset.reset
+ phy_mgmt_address => phy_mgmt_address, -- phy_mgmt.address
+ phy_mgmt_read => phy_mgmt_read, -- .read
+ phy_mgmt_readdata => phy_mgmt_readdata, -- .readdata
+ phy_mgmt_write => phy_mgmt_write, -- .write
+ phy_mgmt_writedata => phy_mgmt_writedata, -- .writedata
+ phy_mgmt_waitrequest => phy_mgmt_waitrequest, -- .waitrequest
+ rx_digitalreset => rx_digitalreset, -- rx_digitalreset.data
+ tx_digitalreset => tx_digitalreset, -- tx_digitalreset.data
+ rx_channelaligned => rx_channelaligned, -- rx_channelaligned.data
+ rx_syncstatus => rx_syncstatus, -- rx_syncstatus.data
+ rx_disperr => rx_disperr, -- rx_disperr.data
+ rx_errdetect => rx_errdetect, -- rx_errdetect.data
+ cal_blk_powerdown => cal_blk_powerdown, -- cal_blk_powerdown.data
+ pll_powerdown => pll_powerdown, -- pll_powerdown.data
+ gxb_powerdown => gxb_powerdown, -- gxb_powerdown.data
+ pll_locked => pll_locked, -- pll_locked.data
+ reconfig_from_xcvr => reconfig_from_xcvr, -- reconfig_from_xcvr.data
+ reconfig_to_xcvr => reconfig_to_xcvr, -- reconfig_to_xcvr.data
+ rx_recovered_clk => open, -- (terminated)
+ tx_clk312_5 => open -- (terminated)
+ );
+
+end architecture rtl; -- of ip_stratixiv_phy_xaui_soft
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/mentor/msim_setup.tcl b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/mentor/msim_setup.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4c03220d0d8ad10469ae5b21e348907a8558fdce
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/phy_xaui/generated/ip_stratixiv_phy_xaui_soft_sim/mentor/msim_setup.tcl
@@ -0,0 +1,279 @@
+
+# (C) 2001-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ----------------------------------------
+# Auto-generated simulation script
+
+# ----------------------------------------
+# Initialize the variable
+if ![info exists SYSTEM_INSTANCE_NAME] {
+ set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
+ set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] {
+ set TOP_LEVEL_NAME "ip_stratixiv_phy_xaui_soft"
+} elseif { ![ string match "" $TOP_LEVEL_NAME ] } {
+ set TOP_LEVEL_NAME "$TOP_LEVEL_NAME"
+}
+
+if ![info exists QSYS_SIMDIR] {
+ set QSYS_SIMDIR "./../"
+} elseif { ![ string match "" $QSYS_SIMDIR ] } {
+ set QSYS_SIMDIR "$QSYS_SIMDIR"
+}
+
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib ./libraries/
+ensure_lib ./libraries/work/
+vmap work ./libraries/work/
+if { ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] } {
+ ensure_lib ./libraries/altera_ver/
+ vmap altera_ver ./libraries/altera_ver/
+ ensure_lib ./libraries/lpm_ver/
+ vmap lpm_ver ./libraries/lpm_ver/
+ ensure_lib ./libraries/sgate_ver/
+ vmap sgate_ver ./libraries/sgate_ver/
+ ensure_lib ./libraries/altera_mf_ver/
+ vmap altera_mf_ver ./libraries/altera_mf_ver/
+ ensure_lib ./libraries/altera_lnsim_ver/
+ vmap altera_lnsim_ver ./libraries/altera_lnsim_ver/
+ ensure_lib ./libraries/stratixiv_hssi_ver/
+ vmap stratixiv_hssi_ver ./libraries/stratixiv_hssi_ver/
+ ensure_lib ./libraries/stratixiv_pcie_hip_ver/
+ vmap stratixiv_pcie_hip_ver ./libraries/stratixiv_pcie_hip_ver/
+ ensure_lib ./libraries/stratixiv_ver/
+ vmap stratixiv_ver ./libraries/stratixiv_ver/
+ ensure_lib ./libraries/altera/
+ vmap altera ./libraries/altera/
+ ensure_lib ./libraries/lpm/
+ vmap lpm ./libraries/lpm/
+ ensure_lib ./libraries/sgate/
+ vmap sgate ./libraries/sgate/
+ ensure_lib ./libraries/altera_mf/
+ vmap altera_mf ./libraries/altera_mf/
+ ensure_lib ./libraries/altera_lnsim/
+ vmap altera_lnsim ./libraries/altera_lnsim/
+ ensure_lib ./libraries/stratixiv_hssi/
+ vmap stratixiv_hssi ./libraries/stratixiv_hssi/
+ ensure_lib ./libraries/stratixiv_pcie_hip/
+ vmap stratixiv_pcie_hip ./libraries/stratixiv_pcie_hip/
+ ensure_lib ./libraries/stratixiv/
+ vmap stratixiv ./libraries/stratixiv/
+}
+ensure_lib ./libraries/ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft/
+vmap ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft ./libraries/ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft/
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+ echo "\[exec\] dev_com"
+ if { ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] } {
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_primitives.v" -work altera_ver
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/220model.v" -work lpm_ver
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/sgate.v" -work sgate_ver
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_mf.v" -work altera_mf_ver
+ vlog -sv "/home/software/Altera/11.1/quartus/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv" -work altera_lnsim_ver
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_hssi_atoms.v" -work stratixiv_hssi_ver
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_pcie_hip_atoms.v" -work stratixiv_pcie_hip_ver
+ vlog "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_atoms.v" -work stratixiv_ver
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_syn_attributes.vhd" -work altera
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_standard_functions.vhd" -work altera
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_primitives_components.vhd" -work altera
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_primitives.vhd" -work altera
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/220pack.vhd" -work lpm
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/220model.vhd" -work lpm
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/sgate_pack.vhd" -work sgate
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/sgate.vhd" -work sgate
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_mf.vhd" -work altera_mf
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_hssi_components.vhd" -work stratixiv_hssi
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_hssi_atoms.vhd" -work stratixiv_hssi
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_pcie_hip_components.vhd" -work stratixiv_pcie_hip
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_pcie_hip_atoms.vhd" -work stratixiv_pcie_hip
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_atoms.vhd" -work stratixiv
+ vcom "/home/software/Altera/11.1/quartus/eda/sim_lib/stratixiv_components.vhd" -work stratixiv
+ }
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+ echo "\[exec\] com"
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/altera_xcvr_functions.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/altera_xcvr_functions.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_pma_functions.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_pma_functions.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/altera_xcvr_xaui.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/hxaui_csr_h.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/hxaui_csr.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_mgmt2dec_phyreconfig.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_mgmt2dec_xaui.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/altera_xcvr_xaui.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/hxaui_csr_h.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/hxaui_csr.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec_phyreconfig.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec_xaui.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/alt_pma_ch_controller_tgx.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_pma_ch_controller_tgx.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/alt_pma_controller_tgx.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_pma_controller_tgx.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_reset_ctrl_lego.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_reset_ctrl_tgx_cdrauto.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_resync.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_csr_common_h.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_csr_common.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_csr_pcs8g_h.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_csr_pcs8g.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_csr_selector.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_mgmt2dec.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/altera_wait_generate.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_reset_ctrl_lego.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_reset_ctrl_tgx_cdrauto.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_resync.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_csr_common_h.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_csr_common.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_csr_pcs8g_h.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_csr_pcs8g.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_csr_selector.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_mgmt2dec.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/altera_wait_generate.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_soft_xaui_pcs.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_soft_xaui_reset.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_soft_xaui_rx.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_8b10b_dec.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_channel_synch.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_deskew.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_deskew_channel.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_deskew_ram.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_invalid_code_det.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_parity.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_parity_4b.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_parity_6b.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_rate_match.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_rate_match_ram.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_rl_chk_6g.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_soft_xaui_rx_sm.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_soft_xaui_tx.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_soft_xaui_tx_8b10b_enc.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_soft_xaui_tx_idle_conv.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/l_modules.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/serdes_4_unit_lc_siv.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/serdes_4_unit_siv.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/serdes_4unit.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/sxaui.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/sxaui.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/siv_xcvr_low_latency_phy_nr.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/siv_xcvr_low_latency_phy_nr.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/siv_xcvr_xaui.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/siv_xcvr_xaui.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/alt4gxb_vo.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt4gxb_vo.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_reconfig_h.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_h.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_reconfig_siv.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_siv.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_reconfig_analog.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_analog.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_reconfig_analog_tgx.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_analog_tgx.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_reconfig_offset_cancellation.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_offset_cancellation.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_reconfig_offset_cancellation_tgx.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_offset_cancellation_tgx.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_reconfig_eyemon_tgx.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_eyemon_tgx.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_reconfig_dfe_tgx.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_dfe_tgx.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_reconfig_basic_tgx.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/alt_mutex_acq.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/alt_dprio.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_reconfig_basic_tgx.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_mutex_acq.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_dprio.v" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_arbiter.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/alt_xcvr_m2s.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_arbiter.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vlog -sv "$QSYS_SIMDIR/altera_xcvr_xaui/mentor/alt_xcvr_m2s.sv" -work ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft
+ vcom "$QSYS_SIMDIR/ip_stratixiv_phy_xaui_soft.vhd"
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+ echo "\[exec\] elab"
+ vsim -t ps -L work -L ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixiv_hssi_ver -L stratixiv_pcie_hip_ver -L stratixiv_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L stratixiv_hssi -L stratixiv_pcie_hip -L stratixiv $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with novopt option
+alias elab_debug {
+ echo "\[exec\] elab_debug"
+ vsim -novopt -t ps -L work -L ip_stratixiv_phy_xaui_soft_ip_stratixiv_phy_xaui_soft -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixiv_hssi_ver -L stratixiv_pcie_hip_ver -L stratixiv_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L stratixiv_hssi -L stratixiv_pcie_hip -L stratixiv $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+ dev_com
+ com
+ elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -novopt
+alias ld_debug "
+ dev_com
+ com
+ elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+ echo "List Of Command Line Aliases"
+ echo
+ echo "dev_com -- Compile device library files"
+ echo
+ echo "com -- Compile the design files in correct order"
+ echo
+ echo "elab -- Elaborate top level design"
+ echo
+ echo "elab_debug -- Elaborate the top level design with novopt option"
+ echo
+ echo "ld -- Compile all the design files and elaborate the top level design"
+ echo
+ echo "ld_debug -- Compile all the design files and elaborate the top level design with -novopt"
+ echo
+ echo
+ echo
+ echo "List Of Variables"
+ echo
+ echo "TOP_LEVEL_NAME -- Top level module name."
+ echo
+ echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
+ echo
+ echo "QSYS_SIMDIR -- Qsys base simulation directory."
+}
+h
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg b/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
index f85419113d803c3c616cbb05ab124fabb3334304..846ee6b24c4ce1ebe56e87b9298745b7f697f081 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_stratixiv_xaui
-hdl_library_clause_name = ip_stratixiv_xaui_lib
+hdl_lib_name = ip_stratixiv_phy_xaui
+hdl_library_clause_name = ip_stratixiv_phy_xaui_lib
hdl_lib_uses =
hdl_lib_technology = ip_stratixiv
@@ -7,15 +7,23 @@ build_sim_dir = $HDL_BUILD_DIR
build_synth_dir = $HDL_BUILD_DIR
modelsim_compile_ip_files =
- $UNB/Firmware/modules/tr_xaui/build/sim/modelsim/compile_ip.tcl
- $UNB/Firmware/modules/tr_xaui/build/sim/modelsim/compile_ip_soft.tcl
+ $RADIOHDL/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
+ $RADIOHDL/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
synth_files =
+ ip_stratixiv_phy_xaui_0.vhd
+ ip_stratixiv_phy_xaui_1.vhd
+ ip_stratixiv_phy_xaui_2.vhd
+ ip_stratixiv_phy_xaui_soft.vhd
test_bench_files =
+synth_copy_files =
+
quartus_vhdl_files =
quartus_sdc_files =
quartus_qip_files =
+ generated/ip_stratixiv_phy_xaui_0.qip
+ ip_stratixiv_phy_xaui_soft.qip
\ No newline at end of file