From f4f808c1a87eaddcce740e9e384d202fa15c03b4 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Fri, 13 Jun 2014 10:04:05 +0000
Subject: [PATCH] Default eth_ram_mosi <= c_mem_mosi_rst to avoid sim warnings.
Adde tb_end to be able to use run -all.
---
libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd b/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd
index a4067eb15d..22252fea15 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd
@@ -33,7 +33,7 @@ USE dp_lib.dp_stream_pkg.ALL;
USE dp_lib.tb_dp_pkg.ALL;
USE tech_tse_lib.tech_tse_pkg.ALL;
USE tech_tse_lib.tb_tech_tse_pkg.ALL;
-USE WORK.eth_layers_pkg.ALL;
+USE common_lib.eth_layers_pkg.ALL;
USE WORK.eth_pkg.ALL;
ENTITY tb_eth_udp_offload IS
@@ -286,6 +286,7 @@ BEGIN
reg_hdr_mosi <= c_mem_mosi_rst;
ram_hdr_mosi <= c_mem_mosi_rst;
eth_reg_mosi <= c_mem_mosi_rst;
+ eth_ram_mosi <= c_mem_mosi_rst;
dut_eth_init <= '1';
@@ -349,12 +350,22 @@ BEGIN
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
print_str("[" & time_to_str(now) & "] 0x" & slv_to_hex(ram_hdr_miso.rddata(c_word_w-1 DOWNTO 0)));
END LOOP;
-
- proc_common_wait_some_cycles(st_clk, 10);
+
+ proc_common_wait_until_high(st_clk, out_gap);
+ proc_common_wait_some_cycles(st_clk, 1000);
tb_end <= '1';
WAIT;
END PROCESS;
+ -- Stop the simulation
+ p_tb_end : PROCESS
+ BEGIN
+ WAIT UNTIL tb_end='1';
+ WAIT FOR 10 us;
+ ASSERT FALSE REPORT "Simulation finished." SEVERITY FAILURE;
+ WAIT;
+ END PROCESS;
+
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
--
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