diff --git a/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd b/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd
index a4067eb15d17a857304b0ea4080fdfb340519cb4..22252fea1520bd53a3caa0e803374e880bfaadc6 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd
@@ -33,7 +33,7 @@ USE dp_lib.dp_stream_pkg.ALL;
 USE dp_lib.tb_dp_pkg.ALL;
 USE tech_tse_lib.tech_tse_pkg.ALL;
 USE tech_tse_lib.tb_tech_tse_pkg.ALL;
-USE WORK.eth_layers_pkg.ALL;
+USE common_lib.eth_layers_pkg.ALL;
 USE WORK.eth_pkg.ALL;
 
 ENTITY tb_eth_udp_offload IS
@@ -286,6 +286,7 @@ BEGIN
     reg_hdr_mosi <= c_mem_mosi_rst;    
     ram_hdr_mosi <= c_mem_mosi_rst;    
     eth_reg_mosi <= c_mem_mosi_rst;    
+    eth_ram_mosi <= c_mem_mosi_rst;    
 
     dut_eth_init <= '1';
 
@@ -349,12 +350,22 @@ BEGIN
       proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
       print_str("[" & time_to_str(now) & "] 0x" & slv_to_hex(ram_hdr_miso.rddata(c_word_w-1 DOWNTO 0)));
     END LOOP;
-
-    proc_common_wait_some_cycles(st_clk, 10);
+    
+    proc_common_wait_until_high(st_clk, out_gap);
+    proc_common_wait_some_cycles(st_clk, 1000);
     tb_end <= '1';
     WAIT;
   END PROCESS;
  
+  -- Stop the simulation
+  p_tb_end : PROCESS  
+  BEGIN
+    WAIT UNTIL tb_end='1';
+    WAIT FOR 10 us;
+    ASSERT FALSE REPORT "Simulation finished." SEVERITY FAILURE;
+    WAIT;
+  END PROCESS;
+  
   ------------------------------------------------------------------------------
   -- DATA VERIFICATION
   ------------------------------------------------------------------------------