diff --git a/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd b/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd
index bb797c033f5f2bc137e823b39737d0e960840b1f..c6279edcd22be6baea0d2718b416627027d5fae8 100644
--- a/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd
+++ b/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd
@@ -70,6 +70,7 @@ ARCHITECTURE str OF mms_ppsh IS
SIGNAL st_capture_edge : STD_LOGIC;
SIGNAL st_expected_cnt : STD_LOGIC_VECTOR(ceil_log2(g_st_clk_freq)-1 DOWNTO 0); -- expected number of clk clock cycles between subsequent pps_ext pulses
+ SIGNAL st_pps_delay : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
-- MM registers in mm_clk domaim for pin_pps support
SIGNAL mm_pps_toggle : STD_LOGIC;
@@ -98,7 +99,8 @@ BEGIN
capture_cnt => st_capture_cnt,
pps_stable_ack => st_pps_stable_ack,
capture_edge => st_capture_edge,
- expected_cnt => st_expected_cnt
+ expected_cnt => st_expected_cnt,
+ pps_delay => st_pps_delay
);
------------------------------------------------------------------------------
@@ -127,7 +129,8 @@ BEGIN
st_pps_stable_ack => st_pps_stable_ack,
st_capture_cnt => st_capture_cnt,
st_capture_edge => st_capture_edge,
- st_expected_cnt => st_expected_cnt
+ st_expected_cnt => st_expected_cnt,
+ st_pps_delay => st_pps_delay
);
------------------------------------------------------------------------------
diff --git a/libraries/io/ppsh/src/vhdl/ppsh.vhd b/libraries/io/ppsh/src/vhdl/ppsh.vhd
index 178511ce5b9c33d1455f48932fdc91f303877b6b..595d1c3846c30670ff38bfb8a06f68c60298106d 100644
--- a/libraries/io/ppsh/src/vhdl/ppsh.vhd
+++ b/libraries/io/ppsh/src/vhdl/ppsh.vhd
@@ -70,7 +70,8 @@ ENTITY ppsh IS
capture_cnt : OUT STD_LOGIC_VECTOR(ceil_log2(g_clk_freq)-1 DOWNTO 0); -- counts the number of clk clock cycles between subsequent pps_ext pulses
pps_stable_ack : IN STD_LOGIC := '0'; -- pps stable acknowledge in clk domain
capture_edge : IN STD_LOGIC := '0'; -- when '0' then clock pps_ext on rising edge of clk, else use falling edge of clk
- expected_cnt : IN STD_LOGIC_VECTOR(ceil_log2(g_clk_freq)-1 DOWNTO 0) := (OTHERS=> '1') -- expected number of clk clock cycles between subsequent pps_ext pulses
+ expected_cnt : IN STD_LOGIC_VECTOR(ceil_log2(g_clk_freq)-1 DOWNTO 0) := (OTHERS=> '1'); -- expected number of clk clock cycles between subsequent pps_ext pulses
+ pps_delay : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := (OTHERS=>'0') -- Number of clk cycles of delay applied to pps_sys
);
END ppsh;
@@ -89,6 +90,7 @@ ARCHITECTURE rtl OF ppsh IS
SIGNAL pps_ext_sync : STD_LOGIC;
SIGNAL pps_ext_revt : STD_LOGIC;
+ SIGNAL pps_ext_revt_dly : STD_LOGIC;
SIGNAL i_capture_cnt : STD_LOGIC_VECTOR(capture_cnt'RANGE) := (OTHERS=>'1');
@@ -159,6 +161,17 @@ BEGIN
in_sig => pps_ext_sync,
out_evt => pps_ext_revt
);
+
+ -- Apply a number of clk cycles of delay to pps_ext_revt
+ pps_ext_revt_dly <= pps_ext_revt;
+
+
+
+
+
+
+
+
u_capture_cnt : ENTITY common_lib.common_interval_monitor
GENERIC MAP (
@@ -169,7 +182,7 @@ BEGIN
clk => clk,
-- ST
in_val => '1',
- in_evt => pps_ext_revt,
+ in_evt => pps_ext_revt_dly,
-- MM
interval_cnt => i_capture_cnt
);
@@ -184,7 +197,7 @@ BEGIN
PORT MAP (
rst => rst,
clk => clk,
- in_dat => pps_ext_revt,
+ in_dat => pps_ext_revt_dly,
out_dat => pps_sys_buf
);
diff --git a/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd b/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd
index 726b3703edeb90b65b54e4dc0eaa0d268642baa2..d2a38e5b591358e6a35f6875b2244620953863d8 100644
--- a/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd
+++ b/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd
@@ -24,6 +24,7 @@
-- . Report PPS toggle, stable and period capture count
-- . Set dp_clk capture edge for PPS
-- Set expected period capture count for PPS stable
+-- Set pps_delay between incoming and outgoing PPS, in units of dp_clk cycles (5ns)
--
-- 31 24 23 16 15 8 7 0 wi
-- |-----------------|-----------------|-----------------|-----------------|
@@ -31,6 +32,8 @@
-- |-----------------------------------------------------------------------|
-- |edge[31], xxx expected_cnt = [n:0]| 1
-- |-----------------------------------------------------------------------|
+-- | pps_delay = [31:0]| 2
+-- |-----------------------------------------------------------------------|
--
LIBRARY IEEE, common_lib;
@@ -62,7 +65,8 @@ ENTITY ppsh_reg IS
st_pps_stable_ack : OUT STD_LOGIC;
st_capture_edge : OUT STD_LOGIC;
- st_expected_cnt : OUT STD_LOGIC_VECTOR(ceil_log2(g_st_clk_freq)-1 DOWNTO 0) -- expected number of clk clock cycles between subsequent pps_ext pulses
+ st_expected_cnt : OUT STD_LOGIC_VECTOR(ceil_log2(g_st_clk_freq)-1 DOWNTO 0); -- expected number of clk clock cycles between subsequent pps_ext pulses
+ st_pps_delay : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0)
);
END ppsh_reg;
@@ -86,6 +90,8 @@ ARCHITECTURE rtl OF ppsh_reg IS
SIGNAL mm_capture_cnt : STD_LOGIC_VECTOR(ceil_log2(g_st_clk_freq)-1 DOWNTO 0);
SIGNAL mm_expected_cnt : STD_LOGIC_VECTOR(ceil_log2(g_st_clk_freq)-1 DOWNTO 0);
+
+ SIGNAL mm_pps_delay : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
BEGIN
@@ -107,7 +113,8 @@ BEGIN
mm_pps_stable_ack <= '0';
mm_capture_edge <= '0'; -- default rising edge
mm_expected_cnt <= TO_UVEC(g_st_clk_freq, mm_expected_cnt'LENGTH);
-
+ mm_pps_delay <= (OTHERS=>'0');
+
ELSIF rising_edge(mm_clk) THEN
-- Read access defaults
sla_out.rdval <= '0';
@@ -122,6 +129,9 @@ BEGIN
-- Write PPSH control
mm_capture_edge <= sla_in.wrdata(31);
mm_expected_cnt <= sla_in.wrdata(mm_expected_cnt'RANGE);
+ WHEN 2 =>
+ -- Write pps_delay
+ mm_pps_delay <= sla_in.wrdata(c_word_w-1 DOWNTO 0);
WHEN OTHERS => NULL; -- not used MM addresses
END CASE;
@@ -140,6 +150,9 @@ BEGIN
-- Read back PPSH control
sla_out.rddata(31) <= mm_capture_edge;
sla_out.rddata(29 DOWNTO 0) <= RESIZE_UVEC(mm_expected_cnt, 30);
+ WHEN 2 =>
+ -- Read back pps_delay
+ sla_out.rddata(c_word_w DOWNTO 0) <= mm_pps_delay;
WHEN OTHERS => NULL; -- not used MM addresses
END CASE;
END IF;
@@ -172,6 +185,7 @@ BEGIN
st_capture_edge <= mm_capture_edge;
st_expected_cnt <= mm_expected_cnt;
+ st_pps_delay <= mm_pps_delay;
END GENERATE; -- no_cross
gen_cross : IF g_cross_clock_domain = TRUE GENERATE
@@ -244,6 +258,19 @@ BEGIN
out_dat => st_expected_cnt,
out_new => OPEN
);
+
+ u_pps_delay : ENTITY common_lib.common_reg_cross_domain
+ PORT MAP (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => mm_pps_delay,
+ in_done => OPEN,
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_pps_delay,
+ out_new => OPEN
+ );
+
END GENERATE; -- gen_cross
END rtl;