diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd index ca1aa3906de6a94d526d2b1b8c1ecc4330a2acb5..6bdaf12e935afa0b47dd0cb70c4a7b7bfb70434a 100644 --- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd +++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd @@ -42,6 +42,7 @@ -- > as 7 # default -- > as 12 # for detailed debugging -- > run -a +-- Takes about 40 m -- ------------------------------------------------------------------------------- LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib; @@ -77,7 +78,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one IS CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C - CONSTANT c_nof_block_per_sync : NATURAL := 32; + CONSTANT c_nof_block_per_sync : NATURAL := 24; CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft; CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync; CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync); @@ -132,7 +133,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one IS SIGNAL ext_clk : STD_LOGIC := '0'; SIGNAL pps : STD_LOGIC := '0'; SIGNAL ext_pps : STD_LOGIC := '0'; - SIGNAL pps_rst : STD_LOGIC := '0'; + SIGNAL pps_rst : STD_LOGIC := '1'; SIGNAL WDI : STD_LOGIC; SIGNAL INTA : STD_LOGIC; @@ -242,9 +243,6 @@ BEGIN BEGIN -- Wait for DUT power up after reset WAIT FOR 1 us; - - -- wait for pps - proc_common_wait_until_hi_lo(ext_clk, ext_pps); ---------------------------------------------------------------------------- -- Enable BSN @@ -253,7 +251,11 @@ BEGIN mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0 mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BSN at PPS - + + -- Release PPS pulser, to get first PPS now and to start BSN source + WAIT FOR 1 us; + pps_rst <= '0'; + ---------------------------------------------------------------------------- -- Crosslets Info ---------------------------------------------------------------------------- @@ -285,6 +287,7 @@ BEGIN ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR; mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1 + -- bsn_scheduler_xsub mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk); -- Interval size mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, c_bsn_start_wg, tb_clk); -- first write low then high part @@ -292,9 +295,8 @@ BEGIN mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk); -- enable -- Wait for enough WG data and start of sync interval - - mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low - "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition + mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low + "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition c_sdp_T_sub, tb_clk); --------------------------------------------------------------------------- @@ -313,8 +315,6 @@ BEGIN xsub_stats_arr(v_B)(63 DOWNTO 32) <= rd_data; END IF; END LOOP; - - proc_common_wait_some_cycles(tb_clk, 1); --------------------------------------------------------------------------- diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd index a7ec9c1b89ecb74b30c1773db145ac4eb7efba0e..46153425b4f8b6a7bad1f83ad2b1a8c4a7e11237 100644 --- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd +++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd @@ -34,7 +34,8 @@ -- Usage: -- > as 7 # default -- > as 12 # for detailed debugging --- > run -a +-- > run -a +-- Takes about 10 m -- ------------------------------------------------------------------------------- LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib, eth_lib; @@ -100,7 +101,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload IS SIGNAL ext_clk : STD_LOGIC := '0'; SIGNAL pps : STD_LOGIC := '0'; SIGNAL ext_pps : STD_LOGIC := '0'; - SIGNAL pps_rst : STD_LOGIC := '0'; + SIGNAL pps_rst : STD_LOGIC := '1'; SIGNAL WDI : STD_LOGIC; SIGNAL INTA : STD_LOGIC; @@ -216,6 +217,10 @@ BEGIN mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000001#, tb_clk); -- Enable BSN immediately + -- Release PPS pulser, to get first PPS now and to start BSN source + WAIT FOR 1 us; + pps_rst <= '0'; + ---------------------------------------------------------------------------- -- Enable xsub ---------------------------------------------------------------------------- @@ -223,6 +228,7 @@ BEGIN mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, c_nof_block_per_sync, tb_clk); -- first write bsn low then bsn high part mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk); -- bsn high, assume v_bsn < 2**31-1 mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk); -- enable + ---------------------------------------------------------------------------- -- Offload enable ---------------------------------------------------------------------------- diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd index 36cec4108b82e2f34098d2483b631d0d5c3e7495..3b8c5cb0fe2672726f3b078aaed54afd41b55d73 100644 --- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd +++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd @@ -42,6 +42,7 @@ -- > as 7 # default -- > as 12 # for detailed debugging -- > run -a +-- Takes about 40 m -- ------------------------------------------------------------------------------- LIBRARY IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2c_sdp_station_lib; @@ -77,11 +78,12 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_xsub_one IS CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C - CONSTANT c_nof_block_per_sync : NATURAL := 32; + CONSTANT c_nof_block_per_sync : NATURAL := 24; CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft; CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync; CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync); - + CONSTANT c_ctrl_interval_size : NATURAL := c_nof_clk_per_sync; + CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value CONSTANT c_lo_factor : REAL := 1.0 - c_percentage; -- lower boundary CONSTANT c_hi_factor : REAL := 1.0 + c_percentage; -- higher boundary @@ -106,13 +108,13 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_xsub_one IS TYPE t_real_arr IS ARRAY (INTEGER RANGE <>) OF REAL; -- MM - CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2"; - CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER"; - CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG"; - CONSTANT c_mm_file_ram_st_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST"; - CONSTANT c_mm_file_reg_crosslets_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_CROSSLETS_INFO"; - CONSTANT c_mm_file_reg_bsn_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER_XSUB"; - CONSTANT c_mm_file_ram_st_xsq : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_XSQ"; + CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2"; + CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER"; + CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG"; + CONSTANT c_mm_file_ram_st_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST"; + CONSTANT c_mm_file_reg_crosslets_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_CROSSLETS_INFO"; + CONSTANT c_mm_file_reg_bsn_sync_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SYNC_SCHEDULER_XSUB"; + CONSTANT c_mm_file_ram_st_xsq : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_XSQ"; -- Tb SIGNAL tb_end : STD_LOGIC := '0'; @@ -131,7 +133,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_xsub_one IS SIGNAL ext_clk : STD_LOGIC := '0'; SIGNAL pps : STD_LOGIC := '0'; SIGNAL ext_pps : STD_LOGIC := '0'; - SIGNAL pps_rst : STD_LOGIC := '0'; + SIGNAL pps_rst : STD_LOGIC := '1'; SIGNAL WDI : STD_LOGIC; SIGNAL INTA : STD_LOGIC; @@ -225,9 +227,6 @@ BEGIN -- Wait for DUT power up after reset WAIT FOR 1 us; - -- wait for pps - proc_common_wait_until_hi_lo(ext_clk, ext_pps); - ---------------------------------------------------------------------------- -- Enable BSN ---------------------------------------------------------------------------- @@ -236,6 +235,10 @@ BEGIN mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BSN at PPS + -- Release PPS pulser, to get first PPS now and to start BSN source + WAIT FOR 1 us; + pps_rst <= '0'; + ---------------------------------------------------------------------------- -- Crosslets Info ---------------------------------------------------------------------------- @@ -267,14 +270,16 @@ BEGIN ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR; mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1 + -- bsn_scheduler_xsub - mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 0, c_bsn_start_wg, tb_clk); -- first write low then high part - mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 1, 0, tb_clk); -- assume v_bsn < 2**31-1 + mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk); -- Interval size + mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, c_bsn_start_wg, tb_clk); -- first write low then high part + mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk); -- assume v_bsn < 2**31-1 + mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk); -- enable -- Wait for enough WG data and start of sync interval - - mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low - "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition + mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low + "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition c_sdp_T_sub, tb_clk); --------------------------------------------------------------------------- @@ -293,8 +298,6 @@ BEGIN xsub_stats_arr(v_B)(63 DOWNTO 32) <= rd_data; END IF; END LOOP; - - proc_common_wait_some_cycles(tb_clk, 1); --------------------------------------------------------------------------- diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd index 2693384e18a3cffec0a9b7a84bbeaa6eae6eaa82..8a84a6fada42be3d8eea93fb4f284e94807a978f 100644 --- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd +++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd @@ -35,6 +35,7 @@ -- > as 7 # default -- > as 12 # for detailed debugging -- > run -a +-- Takes about 10 m -- ------------------------------------------------------------------------------- LIBRARY IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2c_sdp_station_lib, eth_lib; @@ -58,9 +59,9 @@ END tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload; ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload IS CONSTANT c_sim : BOOLEAN := TRUE; - CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0 - CONSTANT c_node_nr : NATURAL := 0; - CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; + CONSTANT c_unb_nr : NATURAL := 2; + CONSTANT c_node_nr : NATURAL := 1; + CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr * 4 + c_node_nr, 8); -- c_unb2c_board_nof_node = 4, c_unb2c_board_aux.id_w = 8 CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; CONSTANT c_fw_version : t_unb2c_board_fw_version := (1, 0); @@ -74,11 +75,12 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload IS CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft; CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync; CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync); + CONSTANT c_ctrl_interval_size : NATURAL := c_nof_clk_per_sync; -- MM - CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2"; - CONSTANT c_mm_file_reg_stat_enable_xst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_XST"; - CONSTANT c_mm_file_reg_bsn_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER_XSUB"; + CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2"; + CONSTANT c_mm_file_reg_stat_enable_xst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_XST"; + CONSTANT c_mm_file_reg_bsn_sync_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SYNC_SCHEDULER_XSUB"; -- Tb SIGNAL tb_end : STD_LOGIC := '0'; @@ -99,7 +101,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload IS SIGNAL ext_clk : STD_LOGIC := '0'; SIGNAL pps : STD_LOGIC := '0'; SIGNAL ext_pps : STD_LOGIC := '0'; - SIGNAL pps_rst : STD_LOGIC := '0'; + SIGNAL pps_rst : STD_LOGIC := '1'; SIGNAL WDI : STD_LOGIC; SIGNAL INTA : STD_LOGIC; @@ -197,12 +199,18 @@ BEGIN mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000001#, tb_clk); -- Enable BSN immediately + -- Release PPS pulser, to get first PPS now and to start BSN source + WAIT FOR 1 us; + pps_rst <= '0'; + ---------------------------------------------------------------------------- -- Enable xsub ---------------------------------------------------------------------------- - mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 0, 1, tb_clk); -- first write low then high part - mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 1, 0, tb_clk); -- assume v_bsn < 2**31-1 - + mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk); -- Interval size + mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, c_nof_block_per_sync, tb_clk); -- first write bsn low then bsn high part + mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk); -- bsn high, assume v_bsn < 2**31-1 + mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk); -- enable + ---------------------------------------------------------------------------- -- Offload enable ---------------------------------------------------------------------------- diff --git a/doc/erko_howto_tools.txt b/doc/erko_howto_tools.txt index 27c70037dd01d049183ba7d95dbd91ae7f06203a..553c1862065ed84560c14ccc8a454ea584c972a0 100755 --- a/doc/erko_howto_tools.txt +++ b/doc/erko_howto_tools.txt @@ -471,6 +471,10 @@ Host dop421 User hiemstra ProxyCommand ssh -q -A astron netcat 10.87.0.221 +* Remote access to regression test machine dop349: +ssh -X kooistra@portal.astron.nl +ssh -X regtest@dop349 + ******************************************************************************* * License server ******************************************************************************* diff --git a/libraries/base/dp/tb/vhdl/dp_statistics.vhd b/libraries/base/dp/tb/vhdl/dp_statistics.vhd index 084885e730bd37efa0f986d5ff9b908a2bc4b184..f9616b725b37a7e688fb5d3a05183eb8fc075af4 100644 --- a/libraries/base/dp/tb/vhdl/dp_statistics.vhd +++ b/libraries/base/dp/tb/vhdl/dp_statistics.vhd @@ -23,6 +23,17 @@ -- . Daniel van der Schuur -- Purpose: -- . Provide a generic DP bus checking stage for simulation. +-- Remark: +-- . EK 17 dec 2021: +-- . removed g_disable_failures, to simplify the component, because default +-- ERROR level is used in practise +-- . removed g_check_data_rate_mbps, to simplify the component, because +-- measuring the average data rate exactly is difficult and requires +-- receiving at least 2 snk_in.sops, to be able to derive mpbs from +-- valid_count / cycle_count between 2 snk_in.sops. +-- . I changed dp_done to end at eop (instead of at next sop), so that an +-- extra next packet is not needed, which reduces the sim time. +-- LIBRARY IEEE, common_lib, work, technology_lib; USE IEEE.STD_LOGIC_1164.ALL; @@ -35,14 +46,10 @@ USE technology_lib.technology_select_pkg.ALL; ENTITY dp_statistics IS GENERIC ( - g_disable_failures : BOOLEAN := FALSE; --TRUE: report warnings instead of failures - does not stop sim. g_runtime_nof_packets : NATURAL; -- Run the test bench for nof_packets before asserting tb_end g_runtime_timeout : TIME; -- Report Failure if g_runtime_nof_packets is not reached before this time - g_check_nof_valid : BOOLEAN := FALSE; -- True enables valid count checking at tb_end. Reports Failure in case of mismatch. - g_check_nof_valid_ref : NATURAL := 0; -- . Specify reference valid count here - g_check_data_rate_mbps : BOOLEAN := FALSE; -- True enables checking of calculated data rate in Mbps - g_check_data_rate_mbps_ref : NATURAL := 0; -- . Specify reference data rate in Mbps here - g_dp_clk_freq_khz : NATURAL := 200000; -- Used to calculate data rate + g_check_nof_valid : BOOLEAN := FALSE; -- True enables valid count checking at dp_done. Reports Failure in case of mismatch. + g_check_nof_valid_ref : NATURAL := 0; -- Reference (= expected) valid count g_dp_word_w : NATURAL := 32 -- Used to calculate data rate ); PORT ( @@ -58,29 +65,28 @@ END dp_statistics; ARCHITECTURE str OF dp_statistics IS - CONSTANT c_severity_level : SEVERITY_LEVEL := sel_a_b(g_disable_failures, WARNING, ERROR); - SIGNAL packet_count : NATURAL := 0; - SIGNAL valid_count : NATURAL := 0; - SIGNAL cycle_count : NATURAL := 0; - SIGNAL i_tb_end : STD_LOGIC; - SIGNAL timeout : STD_LOGIC; - SIGNAL nxt_packet_count : NATURAL := 0; + + SIGNAL valid_count : NATURAL := 0; SIGNAL nxt_valid_count : NATURAL := 0; - SIGNAL nxt_cycle_count : NATURAL := 0; - SIGNAL nxt_tb_end : STD_LOGIC; - SIGNAL data_rate_mbps : NATURAL; + SIGNAL timeout : STD_LOGIC; + + SIGNAL dp_done : STD_LOGIC := '0'; + SIGNAL nxt_dp_done : STD_LOGIC; BEGIN + -- Make sure tb_end will not cause dp_clk to be stopped before dp_done has + -- been evaluated in p_dp_done_check + tb_end <= dp_done WHEN rising_edge(dp_clk); + ------------------------------------------------------------------------------ -- Counters ------------------------------------------------------------------------------ nxt_packet_count <= packet_count+1 WHEN snk_in.sop='1' ELSE packet_count; nxt_valid_count <= valid_count+1 WHEN snk_in.valid='1'ELSE valid_count; - nxt_cycle_count <= cycle_count+1 WHEN packet_count>0 OR (packet_count=0 AND snk_in.sop='1') ELSE cycle_count; ------------------------------------------------------------------------------ -- Assert timeout after user specified time @@ -88,50 +94,31 @@ BEGIN -- the runtime. This is okay as tb_end='1' makes sure no signals are -- changing anymore so this does not take extra sim time. ------------------------------------------------------------------------------ - timeout <= '0', '1' AFTER g_runtime_timeout; + timeout <= '0', '1' AFTER g_runtime_timeout; ------------------------------------------------------------------------------ - -- Assert tb_end if we've seen g_runtime_nof_packets packets + -- Assert dp_done if we've seen g_runtime_nof_packets packets ------------------------------------------------------------------------------ - nxt_tb_end <= '1' WHEN packet_count>g_runtime_nof_packets OR (packet_count=g_runtime_nof_packets AND snk_in.sop='1') ELSE '0'; - tb_end <= i_tb_end; + nxt_dp_done <= '1' WHEN packet_count = g_runtime_nof_packets AND snk_in.eop = '1' ELSE '0'; ------------------------------------------------------------------------------ - -- Derive some interesting statistics + -- On dp_done; do the checks defined in the generics ------------------------------------------------------------------------------ - p_tb_end_calc: PROCESS(nxt_tb_end, timeout) + p_dp_done_check: PROCESS(dp_clk) BEGIN - IF nxt_tb_end='1' AND timeout='0' THEN --Don't calc anything if a timeout occured - data_rate_mbps <= g_dp_clk_freq_khz * g_dp_word_w / 1000 * valid_count / cycle_count; - END IF; - END PROCESS; - - ------------------------------------------------------------------------------ - -- On tb_end; do the checks defined in the generics - ------------------------------------------------------------------------------ - p_tb_end_check: PROCESS(dp_clk) - BEGIN - IF timeout='1' AND nxt_tb_end='0' THEN - REPORT "[dp_statistics] Timeout occured!" SEVERITY c_severity_level; -- report ERROR to have Error in log + IF timeout = '1' AND dp_done = '0' THEN + REPORT "[dp_statistics] Timeout occured!" SEVERITY ERROR; -- report ERROR to have Error in log REPORT "[dp_statistics] Timeout occured!" SEVERITY FAILURE; -- report FAILURE to stop simulation - ELSIF nxt_tb_end='1' THEN - IF falling_edge(dp_clk) THEN + ELSIF dp_done = '1' THEN + IF rising_edge(dp_clk) THEN -- report valid count - IF g_check_nof_valid =TRUE THEN - IF valid_count /=g_check_nof_valid_ref THEN - REPORT "[dp_statistics] Valid count " & INTEGER'IMAGE(valid_count) & " does not match reference " & INTEGER'IMAGE(g_check_nof_valid_ref) SEVERITY c_severity_level; + IF g_check_nof_valid = TRUE THEN + IF valid_count /= g_check_nof_valid_ref THEN + REPORT "[dp_statistics] Valid count " & INTEGER'IMAGE(valid_count) & " does not match reference " & INTEGER'IMAGE(g_check_nof_valid_ref) SEVERITY ERROR; ELSE REPORT "[dp_statistics] Valid count " & INTEGER'IMAGE(valid_count) & " is OK" SEVERITY NOTE; -- Note to show that the check indeed did happen END IF; END IF; - -- report data rate - IF g_check_data_rate_mbps=TRUE THEN - IF data_rate_mbps/=g_check_data_rate_mbps_ref THEN - REPORT "[dp_statistics] data rate " & INTEGER'IMAGE(data_rate_mbps) & " does not match reference " & INTEGER'IMAGE(g_check_data_rate_mbps_ref) SEVERITY c_severity_level; - ELSE - REPORT "[dp_statistics] data rate " & INTEGER'IMAGE(data_rate_mbps) & " is OK" SEVERITY NOTE; -- Note to show that the check indeed did happen - END IF; - END IF; END IF; END IF; END PROCESS; @@ -141,16 +128,14 @@ BEGIN ------------------------------------------------------------------------------ p_dp_clk: PROCESS(dp_clk, dp_rst) BEGIN - IF dp_rst='1' THEN + IF dp_rst = '1' THEN packet_count <= 0; valid_count <= 0; - cycle_count <= 0; - i_tb_end <= '0'; + dp_done <= '0'; ELSIF(rising_edge(dp_clk)) THEN packet_count <= nxt_packet_count; valid_count <= nxt_valid_count; - cycle_count <= nxt_cycle_count; - i_tb_end <= nxt_tb_end; + dp_done <= nxt_dp_done; END IF; END PROCESS; diff --git a/libraries/io/eth/src/vhdl/eth_statistics.vhd b/libraries/io/eth/src/vhdl/eth_statistics.vhd index 9f3bd8c9bac21e811bebdcfd467b0653c5fb4f02..31f58dbcc0d4ba99571143812e1fdfd335b0032b 100644 --- a/libraries/io/eth/src/vhdl/eth_statistics.vhd +++ b/libraries/io/eth/src/vhdl/eth_statistics.vhd @@ -50,13 +50,10 @@ USE technology_lib.technology_select_pkg.ALL; ENTITY eth_statistics IS GENERIC ( - g_disable_failures : BOOLEAN := FALSE; --TRUE: report warnings instead of failures - does not stop sim. g_runtime_nof_packets : NATURAL; -- Run the test bench for nof_packets before asserting tb_end g_runtime_timeout : TIME; -- Report Failure if g_runtime_nof_packets is not reached before this time g_check_nof_valid : BOOLEAN := FALSE; -- True enables valid count checking at tb_end. Reports Failure in case of mismatch. - g_check_nof_valid_ref : NATURAL := 0; -- . Specify reference valid count here - g_check_data_rate_mbps : BOOLEAN := FALSE; -- True enables checking of calculated data rate in Mbps - g_check_data_rate_mbps_ref : NATURAL := 0 -- . Specify reference data rate in Mbps here + g_check_nof_valid_ref : NATURAL := 0 -- Reference (= expected) valid count ); PORT ( eth_serial_in : IN STD_LOGIC; @@ -68,7 +65,6 @@ END eth_statistics; ARCHITECTURE str OF eth_statistics IS - CONSTANT c_eth_clk_freq_khz : NATURAL := 125000; CONSTANT c_eth_word_w : NATURAL := 32; CONSTANT c_eth_clk_period : TIME := 8 ns; @@ -130,14 +126,10 @@ BEGIN ------------------------------------------------------------------------------ u_dp_statistics : ENTITY dp_lib.dp_statistics GENERIC MAP ( - g_disable_failures => g_disable_failures, g_runtime_nof_packets => g_runtime_nof_packets, g_runtime_timeout => g_runtime_timeout, g_check_nof_valid => g_check_nof_valid, g_check_nof_valid_ref => g_check_nof_valid_ref, - g_check_data_rate_mbps => g_check_data_rate_mbps, - g_check_data_rate_mbps_ref => g_check_data_rate_mbps_ref, - g_dp_clk_freq_khz => c_eth_clk_freq_khz, g_dp_word_w => c_eth_word_w ) PORT MAP ( diff --git a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_statistics.vhd b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_statistics.vhd index 77b857a1ac4256172a7fa16604e6bc9f2f06b077..ec8c1875469e857eca50cd486c49c161e64ea58e 100644 --- a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_statistics.vhd +++ b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_statistics.vhd @@ -38,14 +38,11 @@ USE tech_pll_lib.tech_pll_component_pkg.ALL; ENTITY tr_10GbE_statistics IS GENERIC ( g_technology : NATURAL := c_tech_select_default; - g_disable_failures : BOOLEAN := FALSE; --TRUE: report warnings instead of failures - does not stop sim. + g_dp_clk_freq_khz : NATURAL := 200000; -- default dp_clk 200 MHz, 5 ns period g_runtime_nof_packets : NATURAL; -- Run the test bench for nof_packets before asserting tb_end g_runtime_timeout : TIME; -- Report Failure if g_runtime_nof_packets is not reached before this time - g_dp_clk_freq_khz : NATURAL := 200000; -- default dp_clk 200 MHz, 5 ns period g_check_nof_valid : BOOLEAN := FALSE; -- True enables valid count checking at tb_end. Reports Failure in case of mismatch. - g_check_nof_valid_ref : NATURAL := 0; -- . Specify reference valid count here - g_check_data_rate_mbps : BOOLEAN := FALSE; -- True enables checking of calculated data rate in Mbps - g_check_data_rate_mbps_ref : NATURAL := 0 -- . Specify reference data rate in Mbps here + g_check_nof_valid_ref : NATURAL := 0 -- Reference (= expected) valid count ); PORT ( xaui_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others=>'0'); @@ -196,14 +193,10 @@ BEGIN ------------------------------------------------------------------------------ u_dp_statistics : ENTITY dp_lib.dp_statistics GENERIC MAP ( - g_disable_failures => g_disable_failures, g_runtime_nof_packets => g_runtime_nof_packets, g_runtime_timeout => g_runtime_timeout, g_check_nof_valid => g_check_nof_valid, g_check_nof_valid_ref => g_check_nof_valid_ref, - g_check_data_rate_mbps => g_check_data_rate_mbps, - g_check_data_rate_mbps_ref => g_check_data_rate_mbps_ref, - g_dp_clk_freq_khz => g_dp_clk_freq_khz, g_dp_word_w => c_dp_word_w ) PORT MAP (