diff --git a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd index aa29a3de6a21497dbe3b44e38b26cc434f6add8d..646802cbcbb6db2ba21c00c557bc0f484ae1eb04 100755 --- a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd +++ b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd @@ -50,7 +50,7 @@ ENTITY tb_dp_deinterleave_one_to_n_to_one IS GENERIC ( -- general g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control - g_flow_control_verify : t_dp_flow_control_enum := e_random; -- always e_active, e_random or e_pulse flow control + g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control -- specific g_use_fifo : BOOLEAN := TRUE; -- use TRUE to break flow control between 1 to N and N to 1 g_use_complex : BOOLEAN := FALSE; -- needed when g_use_fifo=TRUE @@ -87,6 +87,12 @@ ARCHITECTURE tb OF tb_dp_deinterleave_one_to_n_to_one IS CONSTANT c_verify_pulse_active : NATURAL := 1; CONSTANT c_verify_pulse_period : NATURAL := 5; + CONSTANT c_flow_control_latency_pls : NATURAL := g_nof_repeat * g_pkt_len * (c_verify_pulse_period*c_stimuli_pulse_period) / (c_stimuli_pulse_active*c_verify_pulse_active); + CONSTANT c_flow_control_latency_rnd : NATURAL := g_nof_repeat * g_pkt_len; + CONSTANT c_flow_control_latency : NATURAL := sel_a_b(g_flow_control_stimuli=e_pulse OR g_flow_control_verify=e_pulse, + c_flow_control_latency_pls, + c_flow_control_latency_rnd); -- worst case value + CONSTANT c_data_max : UNSIGNED(c_data_w-1 DOWNTO 0) := (OTHERS=>'1'); CONSTANT c_dsp_max : UNSIGNED(c_data_w-1 DOWNTO 0) := (OTHERS=>'1'); @@ -148,7 +154,8 @@ BEGIN g_in_dat_w => c_data_w, g_nof_repeat => g_nof_repeat, g_pkt_len => g_pkt_len, - g_pkt_gap => g_pkt_gap + g_pkt_gap => g_pkt_gap, + g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli ) PORT MAP ( rst => rst,