diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/hdllib.cfg
index bbb3f9c5f4137f687edb7319fea9c56c2cc63679..838e1ad84288d5232b536d59091fbcd9c6785b93 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/hdllib.cfg
@@ -70,6 +70,8 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_rom_system_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_timer_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_io_ddr.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_ddrctrl_ctrl_state.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/lofar2_unb2c_ddrctrl.fpga.yaml b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/lofar2_unb2c_ddrctrl.fpga.yaml
index 7a77382c61865dfc292b3bcd1dffde55115b0650..82e13d08bc61d01de129125f6cf923301e717625 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/lofar2_unb2c_ddrctrl.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/lofar2_unb2c_ddrctrl.fpga.yaml
@@ -97,3 +97,11 @@ peripherals:
mm_port_names:
- REG_STOP_IN
+ - peripheral_name: ddr/io_ddr
+ mm_port_names:
+ - REG_IO_DDR
+
+ - peripheral_name: ddrctrl/ddrctrl_ctrl_state
+ mm_port_names:
+ - REG_DDRCTRL_CTRL_STATE
+
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_nios2_gen2_0.ip b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_nios2_gen2_0.ip
index 1ad3a5d22891c3c87fa9e248a13dd359e110088b..32c599afb32ac50fa77d0529a5eaf377e74ef145 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_nios2_gen2_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_nios2_gen2_0.ip
@@ -2302,7 +2302,7 @@
<ipxact:parameter parameterId="dataSlaveMapParam" type="string">
<ipxact:name>dataSlaveMapParam</ipxact:name>
<ipxact:displayName>dataSlaveMapParam</ipxact:displayName>
- <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_wg_wideband_arr.mem' start='0x100' end='0x200' datawidth='32' /><slave name='timer_0.s1' start='0x200' end='0x220' datawidth='16' /><slave name='reg_bsn_source_v2.mem' start='0x220' end='0x240' datawidth='32' /><slave name='reg_epcs.mem' start='0x240' end='0x260' datawidth='32' /><slave name='reg_remu.mem' start='0x260' end='0x280' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x280' end='0x2A0' datawidth='32' /><slave name='pio_wdi.s1' start='0x2A0' end='0x2B0' datawidth='32' /><slave name='pio_pps.mem' start='0x2B0' end='0x2C0' datawidth='32' /><slave name='reg_stop_in.mem' start='0x2C0' end='0x2C8' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x2C8' end='0x2D0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x2D0' end='0x2D8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x2D8' end='0x2E0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x2E0' end='0x2E8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x2E8' end='0x2F0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x2F0' end='0x2F8' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x4000' end='0x4800' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bsn_buf.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_data_buf.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_wg_wideband_arr.mem' start='0x70000' end='0x80000' datawidth='32' /></address-map></ipxact:value>
+ <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_wg_wideband_arr.mem' start='0x100' end='0x200' datawidth='32' /><slave name='timer_0.s1' start='0x200' end='0x220' datawidth='16' /><slave name='reg_bsn_source_v2.mem' start='0x220' end='0x240' datawidth='32' /><slave name='reg_epcs.mem' start='0x240' end='0x260' datawidth='32' /><slave name='reg_remu.mem' start='0x260' end='0x280' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x280' end='0x2A0' datawidth='32' /><slave name='pio_wdi.s1' start='0x2A0' end='0x2B0' datawidth='32' /><slave name='reg_io_ddr.mem' start='0x2B0' end='0x2C0' datawidth='32' /><slave name='pio_pps.mem' start='0x2C0' end='0x2D0' datawidth='32' /><slave name='reg_ddrctrl_ctrl_state.mem' start='0x2D0' end='0x2D8' datawidth='32' /><slave name='reg_stop_in.mem' start='0x2D8' end='0x2E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x2E0' end='0x2E8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x2E8' end='0x2F0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x2F0' end='0x2F8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x2F8' end='0x300' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x300' end='0x308' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x308' end='0x310' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x4000' end='0x4800' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bsn_buf.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_data_buf.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_wg_wideband_arr.mem' start='0x70000' end='0x80000' datawidth='32' /></address-map></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="tightlyCoupledDataMaster0MapParam" type="string">
<ipxact:name>tightlyCoupledDataMaster0MapParam</ipxact:name>
@@ -3584,7 +3584,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_wg_wideband_arr.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x200' end='0x220' datawidth='16' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x220' end='0x240' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x240' end='0x260' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x260' end='0x280' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x280' end='0x2A0' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x2A0' end='0x2B0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x2B0' end='0x2C0' datawidth='32' /&gt;&lt;slave name='reg_stop_in.mem' start='0x2C0' end='0x2C8' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x2C8' end='0x2D0' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x2D0' end='0x2D8' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x2D8' end='0x2E0' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x2E0' end='0x2E8' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x2E8' end='0x2F0' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x2F0' end='0x2F8' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x4000' end='0x4800' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_bsn_buf.mem' start='0x40000' end='0x60000' datawidth='32' /&gt;&lt;slave name='ram_data_buf.mem' start='0x60000' end='0x70000' datawidth='32' /&gt;&lt;slave name='ram_wg_wideband_arr.mem' start='0x70000' end='0x80000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_wg_wideband_arr.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x200' end='0x220' datawidth='16' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x220' end='0x240' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x240' end='0x260' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x260' end='0x280' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x280' end='0x2A0' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x2A0' end='0x2B0' datawidth='32' /&gt;&lt;slave name='reg_io_ddr.mem' start='0x2B0' end='0x2C0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x2C0' end='0x2D0' datawidth='32' /&gt;&lt;slave name='reg_ddrctrl_ctrl_state.mem' start='0x2D0' end='0x2D8' datawidth='32' /&gt;&lt;slave name='reg_stop_in.mem' start='0x2D8' end='0x2E0' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x2E0' end='0x2E8' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x2E8' end='0x2F0' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x2F0' end='0x2F8' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x2F8' end='0x300' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x300' end='0x308' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x308' end='0x310' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x4000' end='0x4800' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_bsn_buf.mem' start='0x40000' end='0x60000' datawidth='32' /&gt;&lt;slave name='ram_data_buf.mem' start='0x60000' end='0x70000' datawidth='32' /&gt;&lt;slave name='ram_wg_wideband_arr.mem' start='0x70000' end='0x80000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/qsys_lofar2_unb2c_ddrctrl.qsys b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/qsys_lofar2_unb2c_ddrctrl.qsys
index be1fddeb9357ce588e77a31256bc4a1803583b0c..bc518d1c9485136c38127f329be09e547e7bc423 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/qsys_lofar2_unb2c_ddrctrl.qsys
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/qsys_lofar2_unb2c_ddrctrl.qsys
@@ -78,7 +78,7 @@
{
datum baseAddress
{
- value = "752";
+ value = "776";
type = "String";
}
}
@@ -115,7 +115,7 @@
{
datum baseAddress
{
- value = "688";
+ value = "704";
type = "String";
}
}
@@ -232,7 +232,7 @@
{
datum baseAddress
{
- value = "712";
+ value = "736";
type = "String";
}
}
@@ -252,6 +252,22 @@
type = "String";
}
}
+ element reg_ddrctrl_ctrl_state
+ {
+ datum _sortIndex
+ {
+ value = "28";
+ type = "int";
+ }
+ }
+ element reg_ddrctrl_ctrl_state.mem
+ {
+ datum baseAddress
+ {
+ value = "720";
+ type = "String";
+ }
+ }
element reg_dpmm_ctrl
{
datum _sortIndex
@@ -264,7 +280,7 @@
{
datum baseAddress
{
- value = "744";
+ value = "768";
type = "String";
}
}
@@ -280,7 +296,7 @@
{
datum baseAddress
{
- value = "736";
+ value = "760";
type = "String";
}
}
@@ -332,6 +348,22 @@
type = "String";
}
}
+ element reg_io_ddr
+ {
+ datum _sortIndex
+ {
+ value = "27";
+ type = "int";
+ }
+ }
+ element reg_io_ddr.mem
+ {
+ datum baseAddress
+ {
+ value = "688";
+ type = "String";
+ }
+ }
element reg_mmdp_ctrl
{
datum _sortIndex
@@ -344,7 +376,7 @@
{
datum baseAddress
{
- value = "728";
+ value = "752";
type = "String";
}
}
@@ -360,7 +392,7 @@
{
datum baseAddress
{
- value = "720";
+ value = "744";
type = "String";
}
}
@@ -392,7 +424,7 @@
{
datum baseAddress
{
- value = "704";
+ value = "728";
type = "String";
}
}
@@ -878,6 +910,41 @@
internal="reg_bsn_source_v2.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_ddrctrl_ctrl_state_address"
+ internal="reg_ddrctrl_ctrl_state.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ddrctrl_ctrl_state_clk"
+ internal="reg_ddrctrl_ctrl_state.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ddrctrl_ctrl_state_read"
+ internal="reg_ddrctrl_ctrl_state.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ddrctrl_ctrl_state_readdata"
+ internal="reg_ddrctrl_ctrl_state.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ddrctrl_ctrl_state_reset"
+ internal="reg_ddrctrl_ctrl_state.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ddrctrl_ctrl_state_write"
+ internal="reg_ddrctrl_ctrl_state.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ddrctrl_ctrl_state_writedata"
+ internal="reg_ddrctrl_ctrl_state.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_dpmm_ctrl_address"
internal="reg_dpmm_ctrl.address"
@@ -1049,6 +1116,41 @@
internal="reg_fpga_voltage_sens.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_io_ddr_address"
+ internal="reg_io_ddr.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_io_ddr_clk"
+ internal="reg_io_ddr.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_io_ddr_read"
+ internal="reg_io_ddr.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_io_ddr_readdata"
+ internal="reg_io_ddr.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_io_ddr_reset"
+ internal="reg_io_ddr.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_io_ddr_write"
+ internal="reg_io_ddr.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_io_ddr_writedata"
+ internal="reg_io_ddr.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_mmdp_ctrl_address"
internal="reg_mmdp_ctrl.address"
@@ -4464,36 +4566,39 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>clk_in</name>
+ <name>clk</name>
<type>clock</type>
- <isStart>false</isStart>
+ <isStart>true</isStart>
<ports>
<port>
- <name>in_clk</name>
+ <name>clk_out</name>
<role>clk</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
- <assignmentValueMap>
- <entry>
- <key>qsys.ui.export_name</key>
- <value>clk</value>
- </entry>
- </assignmentValueMap>
+ <assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
+ <entry>
+ <key>associatedDirectClock</key>
+ <value>clk_in</value>
+ </entry>
<entry>
<key>clockRate</key>
<value>125000000</value>
</entry>
+ <entry>
+ <key>clockRateKnown</key>
+ <value>true</value>
+ </entry>
<entry>
<key>externallyDriven</key>
- <value>false</value>
+ <value>true</value>
</entry>
<entry>
<key>ptfSchematicName</key>
@@ -4502,13 +4607,13 @@
</parameters>
</interface>
<interface>
- <name>clk_in_reset</name>
- <type>reset</type>
+ <name>clk_in</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>reset_n</name>
- <role>reset_n</role>
+ <name>in_clk</name>
+ <role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -4519,59 +4624,56 @@
<assignmentValueMap>
<entry>
<key>qsys.ui.export_name</key>
- <value>reset</value>
+ <value>clk</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>125000000</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>NONE</value>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>clock</type>
- <isStart>true</isStart>
+ <name>clk_in_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
<ports>
<port>
- <name>clk_out</name>
- <role>clk</role>
- <direction>Output</direction>
+ <name>reset_n</name>
+ <role>reset_n</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
- <assignmentValueMap/>
+ <assignmentValueMap>
+ <entry>
+ <key>qsys.ui.export_name</key>
+ <value>reset</value>
+ </entry>
+ </assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
- <key>associatedDirectClock</key>
- <value>clk_in</value>
- </entry>
- <entry>
- <key>clockRate</key>
- <value>125000000</value>
- </entry>
- <entry>
- <key>clockRateKnown</key>
- <value>true</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>true</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>synchronousEdges</key>
+ <value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
@@ -5834,7 +5936,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_wg_wideband_arr.mem' start='0x100' end='0x200' datawidth='32' /><slave name='timer_0.s1' start='0x200' end='0x220' datawidth='16' /><slave name='reg_bsn_source_v2.mem' start='0x220' end='0x240' datawidth='32' /><slave name='reg_epcs.mem' start='0x240' end='0x260' datawidth='32' /><slave name='reg_remu.mem' start='0x260' end='0x280' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x280' end='0x2A0' datawidth='32' /><slave name='pio_wdi.s1' start='0x2A0' end='0x2B0' datawidth='32' /><slave name='pio_pps.mem' start='0x2B0' end='0x2C0' datawidth='32' /><slave name='reg_stop_in.mem' start='0x2C0' end='0x2C8' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x2C8' end='0x2D0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x2D0' end='0x2D8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x2D8' end='0x2E0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x2E0' end='0x2E8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x2E8' end='0x2F0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x2F0' end='0x2F8' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x4000' end='0x4800' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bsn_buf.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_data_buf.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_wg_wideband_arr.mem' start='0x70000' end='0x80000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_wg_wideband_arr.mem' start='0x100' end='0x200' datawidth='32' /><slave name='timer_0.s1' start='0x200' end='0x220' datawidth='16' /><slave name='reg_bsn_source_v2.mem' start='0x220' end='0x240' datawidth='32' /><slave name='reg_epcs.mem' start='0x240' end='0x260' datawidth='32' /><slave name='reg_remu.mem' start='0x260' end='0x280' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x280' end='0x2A0' datawidth='32' /><slave name='pio_wdi.s1' start='0x2A0' end='0x2B0' datawidth='32' /><slave name='reg_io_ddr.mem' start='0x2B0' end='0x2C0' datawidth='32' /><slave name='pio_pps.mem' start='0x2C0' end='0x2D0' datawidth='32' /><slave name='reg_ddrctrl_ctrl_state.mem' start='0x2D0' end='0x2D8' datawidth='32' /><slave name='reg_stop_in.mem' start='0x2D8' end='0x2E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x2E0' end='0x2E8' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x2E8' end='0x2F0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x2F0' end='0x2F8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x2F8' end='0x300' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x300' end='0x308' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x308' end='0x310' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x4000' end='0x4800' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bsn_buf.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_data_buf.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_wg_wideband_arr.mem' start='0x70000' end='0x80000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -16372,17 +16474,21 @@
</ports>
<assignments>
<assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>false</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>false</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>false</value>
+ <value>0</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -16422,6 +16528,7 @@
</entry>
<entry>
<key>bridgedAddressOffset</key>
+ <value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
@@ -19092,7 +19199,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_ctrl"
+ name="reg_ddrctrl_ctrl_state"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -20203,37 +20310,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_ddrctrl_ctrl_state</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_ddrctrl_ctrl_state</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_ddrctrl_ctrl_state</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_ddrctrl_ctrl_state</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_ddrctrl_ctrl_state</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_ddrctrl_ctrl_state</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_ddrctrl_ctrl_state</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_ddrctrl_ctrl_state.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_data"
+ name="reg_dpmm_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -21344,37 +21451,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_epcs"
+ name="reg_dpmm_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -21453,7 +21560,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21522,7 +21629,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -21751,7 +21858,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21929,11 +22036,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -22033,7 +22140,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22102,7 +22209,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -22331,7 +22438,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22485,37 +22592,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_epcs</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_epcs.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_temp_sens"
+ name="reg_epcs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -23626,37 +23733,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_voltage_sens"
+ name="reg_fpga_temp_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -23735,7 +23842,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23804,7 +23911,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -24033,7 +24140,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24211,11 +24318,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -24315,7 +24422,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24384,7 +24491,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -24613,7 +24720,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24767,37 +24874,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_ctrl"
+ name="reg_fpga_voltage_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -24876,7 +24983,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24945,7 +25052,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -25174,7 +25281,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25352,11 +25459,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -25456,7 +25563,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25525,7 +25632,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -25754,7 +25861,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25908,37 +26015,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_data"
+ name="reg_io_ddr"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -26017,7 +26124,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26086,7 +26193,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -26315,7 +26422,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26493,11 +26600,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -26597,7 +26704,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26666,7 +26773,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -26895,7 +27002,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27049,37 +27156,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_io_ddr</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_io_ddr</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_io_ddr</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_io_ddr</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_io_ddr</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_io_ddr</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_io_ddr</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_io_ddr.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_remu"
+ name="reg_mmdp_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -27158,7 +27265,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27227,7 +27334,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -27456,7 +27563,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27634,11 +27741,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -27738,7 +27845,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27807,7 +27914,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -28036,7 +28143,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28190,37 +28297,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_remu</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_remu.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stop_in"
+ name="reg_mmdp_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -29331,37 +29438,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_stop_in</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_stop_in</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_stop_in</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_stop_in</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_stop_in</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_stop_in</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_stop_in</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_stop_in.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_wdi"
+ name="reg_remu"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -29440,7 +29547,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29509,7 +29616,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -29738,7 +29845,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29916,11 +30023,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -30020,7 +30127,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30089,7 +30196,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -30318,7 +30425,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30472,37 +30579,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_wdi</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_wdi.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_wg_wideband_arr"
+ name="reg_stop_in"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -30581,7 +30688,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30650,7 +30757,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -30879,7 +30986,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31057,11 +31164,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -31161,7 +31268,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31230,7 +31337,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -31459,7 +31566,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31613,37 +31720,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_stop_in</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_stop_in</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_stop_in</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_stop_in</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_stop_in</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_stop_in</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_stop_in</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr.ip</parameter>
+ <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_stop_in.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="rom_system_info"
+ name="reg_wdi"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -31722,7 +31829,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31791,7 +31898,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -32020,72 +32127,2354 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_wdi</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_wdi</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_wdi</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_wdi</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_wdi.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_wg_wideband_arr"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="rom_system_info"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>13</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32768</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>13</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
@@ -34093,7 +36482,7 @@
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x02f0" />
+ <parameter name="baseAddress" value="0x0308" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -34173,7 +36562,7 @@
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x02b0" />
+ <parameter name="baseAddress" value="0x02c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -34273,7 +36662,7 @@
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x02e8" />
+ <parameter name="baseAddress" value="0x0300" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -34293,7 +36682,7 @@
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x02e0" />
+ <parameter name="baseAddress" value="0x02f8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -34313,7 +36702,7 @@
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x02d8" />
+ <parameter name="baseAddress" value="0x02f0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -34333,7 +36722,7 @@
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x02d0" />
+ <parameter name="baseAddress" value="0x02e8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -34413,7 +36802,7 @@
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x02c8" />
+ <parameter name="baseAddress" value="0x02e0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -34473,7 +36862,7 @@
start="cpu_0.data_master"
end="reg_stop_in.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x02c0" />
+ <parameter name="baseAddress" value="0x02d8" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -34527,6 +36916,46 @@
<parameter name="qsys_mm.syncResets" value="FALSE" />
<parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_io_ddr.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x02b0" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_ddrctrl_ctrl_state.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x02d0" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
<connection
kind="avalon"
version="19.4"
@@ -34777,6 +37206,12 @@
version="19.4"
start="clk_0.clk"
end="ram_bsn_buf.system" />
+ <connection kind="clock" version="19.4" start="clk_0.clk" end="reg_io_ddr.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="reg_ddrctrl_ctrl_state.system" />
<connection
kind="interrupt"
version="19.4"
@@ -34920,6 +37355,16 @@
version="19.4"
start="clk_0.clk_reset"
end="ram_bsn_buf.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_io_ddr.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_ddrctrl_ctrl_state.system_reset" />
<connection
kind="reset"
version="19.4"
@@ -35050,4 +37495,14 @@
version="19.4"
start="cpu_0.debug_reset_request"
end="ram_bsn_buf.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="cpu_0.debug_reset_request"
+ end="reg_io_ddr.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="cpu_0.debug_reset_request"
+ end="reg_ddrctrl_ctrl_state.system_reset" />
</system>
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
index 9255122e9132bfb9045205fed6f814d0933d7ce5..09d36c27747a20acb4dbf526e1f788b095d921a7 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
@@ -217,6 +217,14 @@ ARCHITECTURE str OF lofar2_unb2c_ddrctrl IS
SIGNAL out_siso : t_dp_siso := c_dp_siso_rst;
SIGNAL out_sosi_arr_ddrctrl : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL in_sosi_arr_data_buf : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+
+ SIGNAL reg_ddrctrl_ctrl_state_mosi : t_mem_mosi;
+ SIGNAL reg_ddrctrl_ctrl_state_miso : t_mem_miso;
+ SIGNAL ddrctrl_ctrl_state : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
+
+ SIGNAL reg_io_ddr_mosi : t_mem_mosi;
+ SIGNAL reg_io_ddr_miso : t_mem_miso;
+
SIGNAL phy3_in : t_tech_ddr3_phy_in;
SIGNAL phy3_io : t_tech_ddr3_phy_io;
SIGNAL phy3_ou : t_tech_ddr3_phy_ou;
@@ -371,6 +379,24 @@ BEGIN
);
+ u_ddrctrl_ctrl_state_reg : ENTITY common_lib.mms_common_reg
+ PORT MAP (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_ddrctrl_ctrl_state_mosi,
+ reg_miso => reg_ddrctrl_ctrl_state_miso,
+
+ -- Streaming clock domain
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ in_reg => ddrctrl_ctrl_state,
+ out_reg => open
+ );
+
+
u_ddrctrl : ENTITY lofar2_ddrctrl_lib.ddrctrl
GENERIC MAP (
g_tech_ddr => c_tech_ddr,
@@ -392,6 +418,10 @@ BEGIN
stop_in => stop_in_arr(0),
out_sosi_arr => out_sosi_arr_ddrctrl,
out_siso => out_siso,
+ ddrctrl_ctrl_state=> ddrctrl_ctrl_state,
+
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
--PHY
phy3_in => phy3_in,
@@ -680,6 +710,14 @@ BEGIN
reg_stop_in_mosi => reg_stop_in_mosi,
reg_stop_in_miso => reg_stop_in_miso,
+ -- ddrctrl_ctrl_state
+ reg_ddrctrl_ctrl_state_mosi => reg_ddrctrl_ctrl_state_mosi,
+ reg_ddrctrl_ctrl_state_miso => reg_ddrctrl_ctrl_state_miso,
+
+ -- io_ddr
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
-- data_buffer
reg_data_buf_mosi => reg_data_buf_mosi,
reg_data_buf_miso => reg_data_buf_miso,
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
index 829d63c21f5178f70d323389dc821c6265bb42c3..b55d55d6d50e714fce88ee67bcc6d6e1425ad3be 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
@@ -116,6 +116,14 @@ ENTITY mmm_lofar2_unb2c_ddrctrl IS
reg_stop_in_mosi : OUT t_mem_mosi;
reg_stop_in_miso : IN t_mem_miso;
+ -- ddrctrl_ctrl_state
+ reg_ddrctrl_ctrl_state_mosi : OUT t_mem_mosi;
+ reg_ddrctrl_ctrl_state_miso : IN t_mem_miso;
+
+ -- io_ddr
+ reg_io_ddr_mosi : OUT t_mem_mosi;
+ reg_io_ddr_miso : IN t_mem_miso;
+
-- data_buffer
reg_data_buf_mosi : OUT t_mem_mosi;
reg_data_buf_miso : IN t_mem_miso;
@@ -190,6 +198,12 @@ BEGIN
u_mm_file_reg_stop_in : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STOP_IN")
PORT MAP(mm_rst, mm_clk, reg_stop_in_mosi, reg_stop_in_miso);
+ u_mm_file_reg_ddrctrl_state : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DDRCTRL_CTRL_STATE")
+ PORT MAP(mm_rst, mm_clk, reg_ddrctrl_ctrl_state_mosi, reg_ddrctrl_ctrl_state_miso);
+
+ u_mm_file_reg_io_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
+ PORT MAP(mm_rst, mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
+
u_mm_file_reg_data_buf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DATA_BUF")
PORT MAP(mm_rst, mm_clk, reg_data_buf_mosi, reg_data_buf_miso);
@@ -412,8 +426,23 @@ BEGIN
ram_bsn_buf_read_export => ram_bsn_buf_mosi.rd,
ram_bsn_buf_readdata_export => ram_bsn_buf_miso.rddata(c_word_w-1 DOWNTO 0),
ram_bsn_buf_write_export => ram_bsn_buf_mosi.wr,
- ram_bsn_buf_writedata_export => ram_bsn_buf_mosi.wrdata(c_word_w-1 DOWNTO 0)
-
+ ram_bsn_buf_writedata_export => ram_bsn_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ reg_io_ddr_reset_export => OPEN,
+ reg_io_ddr_clk_export => OPEN,
+ reg_io_ddr_address_export => reg_io_ddr_mosi.address(1 DOWNTO 0),
+ reg_io_ddr_read_export => reg_io_ddr_mosi.rd,
+ reg_io_ddr_readdata_export => reg_io_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_io_ddr_write_export => reg_io_ddr_mosi.wr,
+ reg_io_ddr_writedata_export => reg_io_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ reg_ddrctrl_ctrl_state_reset_export => OPEN,
+ reg_ddrctrl_ctrl_state_clk_export => OPEN,
+ reg_ddrctrl_ctrl_state_address_export => reg_ddrctrl_ctrl_state_mosi.address(0 DOWNTO 0),
+ reg_ddrctrl_ctrl_state_read_export => reg_ddrctrl_ctrl_state_mosi.rd,
+ reg_ddrctrl_ctrl_state_readdata_export => reg_ddrctrl_ctrl_state_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_ddrctrl_ctrl_state_write_export => reg_ddrctrl_ctrl_state_mosi.wr,
+ reg_ddrctrl_ctrl_state_writedata_export => reg_ddrctrl_ctrl_state_mosi.wrdata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
index 05238c8259843ae5abcc5b7f52db91d94edbdaa7..3c14bb5d076ae36cd1a7a4b88573f7c72568fd84 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
@@ -171,6 +171,13 @@ PACKAGE qsys_lofar2_unb2c_ddrctrl_pkg IS
reg_stop_in_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_stop_in_read_export : out std_logic; -- export
reg_stop_in_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_reset_export : out std_logic; -- export
+ reg_io_ddr_clk_export : out std_logic; -- export
+ reg_io_ddr_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_io_ddr_write_export : out std_logic; -- export
+ reg_io_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_read_export : out std_logic; -- export
+ reg_io_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_wdi_reset_export : out std_logic; -- export
reg_wdi_clk_export : out std_logic; -- export
reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
@@ -185,6 +192,13 @@ PACKAGE qsys_lofar2_unb2c_ddrctrl_pkg IS
reg_wg_wideband_arr_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_wg_wideband_arr_read_export : out std_logic; -- export
reg_wg_wideband_arr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ddrctrl_ctrl_state_reset_export : out std_logic; -- export
+ reg_ddrctrl_ctrl_state_clk_export : out std_logic; -- export
+ reg_ddrctrl_ctrl_state_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_ddrctrl_ctrl_state_write_export : out std_logic; -- export
+ reg_ddrctrl_ctrl_state_writedata_export: out std_logic_vector(31 downto 0); -- export
+ reg_ddrctrl_ctrl_state_read_export : out std_logic; -- export
+ reg_ddrctrl_ctrl_state_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
rom_system_info_reset_export : out std_logic; -- export
rom_system_info_clk_export : out std_logic; -- export
rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
index 069ab0f10d6dd2db40a465f8fdd5f9fc7ede1ce0..a0b631478170270ef273984a45003e2bb0fc17ea 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
@@ -335,7 +335,7 @@ BEGIN
-----------------------------------------------------------------------------------------------------------------------------
- WAIT FOR c_mm_clk_period*24000;
+ WAIT FOR c_mm_clk_period*240000;
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
WAIT FOR c_mm_clk_period*30;
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 0, tb_clk);
diff --git a/applications/lofar2/libraries/ddrctrl/ddrctrl.peripheral.yaml b/applications/lofar2/libraries/ddrctrl/ddrctrl.peripheral.yaml
index 2edfe240d396630bd33020c939d528befe7934da..1d1b2c8fa9efe5e9f7fef646c8988971dab83eef 100644
--- a/applications/lofar2/libraries/ddrctrl/ddrctrl.peripheral.yaml
+++ b/applications/lofar2/libraries/ddrctrl/ddrctrl.peripheral.yaml
@@ -21,3 +21,18 @@ peripherals:
"Stops writing on a falling edge from 1 to 0."
address_offset: 0 * MM_BUS_SIZE
mm_width: 1
+
+ - peripheral_name: ddrctrl_ctrl_state # pi_ddrctrl_stop_in.py
+ peripheral_description: "Reads the state of ddrctrl."
+ mm_ports:
+ # MM port for mms_diag_rx_seq.vhd
+ - mm_port_name: REG_DDRCTRL_CTRL_STATE
+ mm_port_type: REG
+ mm_port_span: 1 * MM_BUS_SIZE
+ mm_port_description: "Reads the state of ddrctrl."
+ fields:
+ - - field_name: stop_in
+ field_description: |
+ "Describes the state of ddrctrl."
+ address_offset: 0 * MM_BUS_SIZE
+ mm_width: 1
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index 69d2672f906d8c2acb44fd6b0f7e756a14ee972f..7dd206f9186d5010e0f2f3c0d6c16406a8432055 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -35,6 +35,7 @@
LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib, io_ddr_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
@@ -66,10 +67,15 @@ ENTITY ddrctrl IS
out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
out_siso : IN t_dp_siso := c_dp_siso_rst;
+ ddrctrl_ctrl_state: OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0);
term_ctrl_out : OUT t_tech_ddr3_phy_terminationcontrol;
term_ctrl_in : IN t_tech_ddr3_phy_terminationcontrol := c_tech_ddr3_phy_terminationcontrol_rst;
+ -- IO_DDR monitor data
+ reg_io_ddr_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_io_ddr_miso : OUT t_mem_miso;
+
-- DDR3 PHY external interface
phy3_in : IN t_tech_ddr3_phy_in := c_tech_ddr3_phy_in_x;
phy3_io : INOUT t_tech_ddr3_phy_io;
@@ -95,8 +101,8 @@ ARCHITECTURE str OF ddrctrl IS
CONSTANT c_burstsize : NATURAL := g_tech_ddr.maxburstsize;
CONSTANT c_adr_w : NATURAL := func_tech_ddr_ctlr_address_w(g_tech_ddr); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
CONSTANT c_max_adr : NATURAL := 2**(c_adr_w)-1; -- the maximal address that is possible within the vector length of the address
- CONSTANT c_bim : NATURAL := (c_max_adr*c_io_ddr_data_w)/(g_block_size*g_nof_streams*g_data_w); -- the amount of whole blocks that fit in memory.
CONSTANT c_adr_per_b : NATURAL := ((g_block_size*g_nof_streams*g_data_w)/c_io_ddr_data_w)+1; -- rounding error removes the amount of extra addresses.
+ CONSTANT c_bim : NATURAL := NATURAL(floor(REAL(c_max_adr)/REAL(c_adr_per_b)));
SIGNAL s_adr_per_b : NATURAL := c_adr_per_b;
@@ -195,8 +201,8 @@ BEGIN
mm_clk => mm_clk,
-- MM interface
- reg_io_ddr_mosi => open,
- reg_io_ddr_miso => open,
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
-- Driver clock domain
dvr_clk => clk,
@@ -302,7 +308,8 @@ BEGIN
-- ddrctrl_controller
stop_in => stop_in,
- stop_out => stop
+ stop_out => stop,
+ ddrctrl_ctrl_state => ddrctrl_ctrl_state
);
END str;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index 8ad8bc4bb1fb2d531a6255282c78bfa87ca9471e..c6ccdf9715f260b4ec2d2e3ac6949cd0a7e764b0 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -78,7 +78,8 @@ ENTITY ddrctrl_controller IS
-- ddrctrl_controller
stop_in : IN STD_LOGIC;
- stop_out : OUT STD_LOGIC
+ stop_out : OUT STD_LOGIC;
+ ddrctrl_ctrl_state : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0) := (OTHERS => '0')
);
END ddrctrl_controller;
@@ -86,7 +87,7 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
CONSTANT c_bitshift_w : NATURAL := ceil_log2(g_burstsize); -- bitshift to make sure there is only a burst start at a interval of c_burstsize.
CONSTANT c_adr_w : NATURAL := func_tech_ddr_ctlr_address_w( g_tech_ddr ); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
- CONSTANT c_pof_ma : NATURAL := (((g_max_adr*(100-g_stop_percentage))/100)/g_adr_per_b)*g_adr_per_b; --percentage of max address.
+ CONSTANT c_pof_ma : NATURAL := NATURAL((((REAL(g_max_adr)*(100.0-REAL(g_stop_percentage)))/100.0)/REAL(g_adr_per_b))*REAL(g_adr_per_b)); --percentage of max address.
CONSTANT c_zeros : STD_LOGIC_VECTOR(c_bitshift_w-1 DOWNTO 0) := (OTHERS => '0');
@@ -126,9 +127,10 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
-- output
dvr_mosi : t_mem_ctlr_mosi;
wr_sosi : t_dp_sosi;
+ ddrctrl_ctrl_state : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
END RECORD;
- CONSTANT c_t_reg_init : t_reg := (RESET, '0', '0', TO_UVEC(g_max_adr, c_adr_w), (OTHERS => '0'), 0, '1', '1', '0', 0, (OTHERS => '0'), 0, '1', c_mem_ctlr_mosi_rst, c_dp_sosi_init);
+ CONSTANT c_t_reg_init : t_reg := (RESET, '0', '0', TO_UVEC(g_max_adr, c_adr_w), (OTHERS => '0'), 0, '1', '1', '0', 0, (OTHERS => '0'), 0, '1', c_mem_ctlr_mosi_rst, c_dp_sosi_init, (OTHERS => '0'));
-- signals for readability
@@ -158,6 +160,7 @@ BEGIN
v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := (OTHERS => '0');
v.dvr_mosi.wr := '1';
v.wr_sosi.valid := '1';
+ v.ddrctrl_ctrl_state(32-1) := rst;
IF rst = '0' THEN
v.state := STOP_READING;
@@ -165,6 +168,7 @@ BEGIN
WHEN STOP_READING =>
+ v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(1, 32);
-- this is the last read burst, this make sure every data containing word in the memory has been read.
IF TO_UINT(rd_fifo_usedw) <= g_burstsize AND dvr_miso.done = '1' AND q_reg.rd_burst_en = '1' THEN
v.dvr_mosi.burstbegin := '1';
@@ -187,6 +191,7 @@ BEGIN
WHEN WAIT_FOR_SOP =>
+ v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(2, 32);
v.dvr_mosi.burstbegin := '0';
v.rst_ddrctrl_input_ac := '0';
IF q_reg.started = '0' AND inp_sosi.eop = '1' THEN
@@ -199,6 +204,7 @@ BEGIN
WHEN WRITING =>
+ v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(3, 32);
-- this state generates the rest of the write bursts, it also checks if there is a stop signal or if it needs to stop writing.
v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w-1 DOWNTO c_bitshift_w));
IF q_reg.wr_bursts_ready >= 1 AND dvr_miso.done = '1' AND q_reg.wr_burst_en = '1' AND q_reg.dvr_mosi.burstbegin = '0' THEN
@@ -236,6 +242,7 @@ BEGIN
WHEN SET_STOP =>
+ v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(4, 32);
-- this state sets a stop address dependend on the g_stop_percentage.
IF inp_adr-c_pof_ma >= 0 THEN
v.stop_adr(c_adr_w-1 DOWNTO 0) := TO_UVEC(inp_adr-c_pof_ma, c_adr_w);
@@ -243,7 +250,11 @@ BEGIN
v.stop_adr(c_adr_w-1 DOWNTO 0) := TO_UVEC(inp_adr+g_max_adr-c_pof_ma, c_adr_w);
END IF;
v.ready_for_set_stop := '0';
- v.last_adr_to_write_to(c_adr_w-1 DOWNTO c_bitshift_w) := v.stop_adr(c_adr_w-1 DOWNTO c_bitshift_w);
+ IF TO_UINT(v.stop_adr(c_adr_w-1 DOWNTO 0)) = 0 THEN
+ v.last_adr_to_write_to(c_adr_w-1 DOWNTO 0) := TO_UVEC(g_max_adr-g_last_burstsize, c_adr_w);
+ ELSE
+ v.last_adr_to_write_to(c_adr_w-1 DOWNTO c_bitshift_w) := v.stop_adr(c_adr_w-1 DOWNTO c_bitshift_w);
+ END IF;
v.last_adr_to_write_to(c_bitshift_w-1 DOWNTO 0) := (OTHERS => '0');
v.stop_burstsize := TO_UINT(v.stop_adr(c_adr_w-1 DOWNTO 0))-TO_UINT(v.last_adr_to_write_to)+1;
@@ -281,6 +292,7 @@ BEGIN
WHEN STOP_WRITING =>
+ v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(5, 32);
-- this state stops the writing by generating one last whole write burst which almost empties wr_fifo.
v.wr_sosi.valid := '0';
v.dvr_mosi.burstbegin := '0';
@@ -288,7 +300,7 @@ BEGIN
v.stop_adr := TO_UVEC(g_max_adr, c_adr_w);
-- still receiving write data.
- v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w-1 DOWNTO c_bitshift_w));
+ v.wr_bursts_ready := TO_UINT(TO_UVEC(TO_UINT(wr_fifo_usedw)+2, g_wr_fifo_uw_w)(g_wr_fifo_uw_w-1 DOWNTO c_bitshift_w));
IF NOT (q_reg.wr_bursts_ready = 0) AND q_reg.dvr_mosi.burstbegin = '0'THEN
v.wr_burst_en := '1';
ELSIF q_reg.wr_bursts_ready = 0 THEN
@@ -311,12 +323,13 @@ BEGIN
v.dvr_mosi.wr := '1';
v.dvr_mosi.rd := '0';
- IF dvr_miso.done = '1' AND q_reg.dvr_mosi.burstbegin = '0' AND q_reg.wr_burst_en = '0' AND q_reg.wr_bursts_ready = 0 THEN
+ IF dvr_miso.done = '1' AND q_reg.dvr_mosi.burstbegin = '0' AND q_reg.wr_burst_en = '0' AND q_reg.wr_bursts_ready = 0 AND inp_data_stopped = '1' AND TO_UINT(wr_fifo_usedw) <= q_reg.stop_burstsize THEN
v.state := LAST_WRITE_BURST;
END IF;
WHEN LAST_WRITE_BURST =>
+ v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(6, 32);
-- this state stops the writing by generatign one last write burst which empties wr_fifo.
v.wr_sosi.valid := '0';
IF dvr_miso.done = '1' THEN
@@ -338,9 +351,10 @@ BEGIN
WHEN START_READING =>
+ v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(7, 32);
-- this state generates the first read burst, the size of this burst is dependend on the size of the last write burst.
v.dvr_mosi.burstbegin := '0';
- v.outp_bsn := TO_UVEC(TO_UINT(inp_sosi.bsn)-g_bim, c_dp_stream_bsn_w);
+ v.outp_bsn := INCR_UVEC(inp_sosi.bsn,-1*g_bim);
v.wr_sosi.valid := '0';
IF dvr_miso.done = '1' AND v.rd_burst_en = '1' AND q_reg.dvr_mosi.burstbegin = '0' THEN
@@ -367,6 +381,7 @@ BEGIN
WHEN READING =>
+ v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(8, 32);
v.wr_sosi.valid := '0';
-- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo which results in your outputs sosi.valid not being constatly valid.
IF TO_UINT(rd_fifo_usedw) <= g_burstsize AND dvr_miso.done = '1' AND q_reg.rd_burst_en = '1' THEN
@@ -419,5 +434,7 @@ BEGIN
stop_out <= q_reg.stopped;
outp_bsn <= q_reg.outp_bsn;
rst_ddrctrl_input_ac <= q_reg.rst_ddrctrl_input_ac OR rst;
+ ddrctrl_ctrl_state <= q_reg.ddrctrl_ctrl_state;
+
END rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index 7e8c2433845482a67feeeddec109aaeac5e2105e..283163399842fdd4d0f7887e22aab808aad29f50 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -67,6 +67,7 @@ ARCHITECTURE tb OF tb_ddrctrl IS
CONSTANT c_clk_period : TIME := (10**6/c_clk_freq)*1 ps; -- clock priod, 5 ns
CONSTANT c_mm_clk_freq : NATURAL := 100; -- mm clock frequency in MHz
CONSTANT c_mm_clk_period : TIME := (10**6/c_mm_clk_freq)*1 ps; -- mm clock period, 10 ns
+ CONSTANT c_stop_value_for_j : NATURAL := 14180;
-- constant for checking output data
CONSTANT c_adr_w : NATURAL := func_tech_ddr_ctlr_address_w(c_tech_ddr); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
@@ -206,7 +207,7 @@ BEGIN
in_sosi_arr(I).valid <= '1';
END LOOP;
- IF (K = 0 OR K = 3) AND J = c_bim*g_block_size-1 THEN
+ IF (K = 1 OR K = 3) AND J = c_stop_value_for_J THEN
stop_in <= '1';
ELSE
stop_in <= '0';