diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index 55d56fe1992e4da559138d298c64ed381341b902..fbf9ce2279aa5af719e15361e456580e09cd5deb 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -393,6 +393,8 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL ait_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
SIGNAL pfb_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
SIGNAL fsub_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
+
+ SIGNAL dp_bsn_source_restart : STD_LOGIC;
SIGNAL bf_udp_sosi_arr : t_dp_sosi_arr(c_sdp_N_beamsets-1 DOWNTO 0);
SIGNAL bf_udp_siso_arr : t_dp_siso_arr(c_sdp_N_beamsets-1 DOWNTO 0);
@@ -792,7 +794,8 @@ BEGIN
jesd204b_sync_n => JESD204B_SYNC_N,
-- Streaming data output
- out_sosi_arr => ait_sosi_arr
+ out_sosi_arr => ait_sosi_arr,
+ dp_bsn_source_restart => dp_bsn_source_restart
);
-----------------------------------------------------------------------------
@@ -806,40 +809,41 @@ BEGIN
g_scope_selected_subband => g_scope_selected_subband
)
PORT MAP(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- pfb_sosi_arr => pfb_sosi_arr,
- fsub_sosi_arr => fsub_sosi_arr,
-
- sst_udp_sosi => udp_tx_sosi_arr(0),
- sst_udp_siso => udp_tx_siso_arr(0),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_gains_mosi => ram_equalizer_gains_mosi,
- ram_gains_miso => ram_equalizer_gains_miso,
- reg_selector_mosi => reg_dp_selector_mosi,
- reg_selector_miso => reg_dp_selector_miso,
-
- reg_enable_mosi => reg_stat_enable_sst_mosi,
- reg_enable_miso => reg_stat_enable_sst_miso,
- reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_mosi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_sst_miso,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ pfb_sosi_arr => pfb_sosi_arr,
+ fsub_sosi_arr => fsub_sosi_arr,
+ dp_bsn_source_restart => dp_bsn_source_restart,
+
+ sst_udp_sosi => udp_tx_sosi_arr(0),
+ sst_udp_siso => udp_tx_siso_arr(0),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ ram_gains_mosi => ram_equalizer_gains_mosi,
+ ram_gains_miso => ram_equalizer_gains_miso,
+ reg_selector_mosi => reg_dp_selector_mosi,
+ reg_selector_miso => reg_dp_selector_miso,
+
+ reg_enable_mosi => reg_stat_enable_sst_mosi,
+ reg_enable_miso => reg_stat_enable_sst_miso,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_mosi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_sst_miso,
- sdp_info => sdp_info,
- gn_id => gn_id,
- eth_src_mac => stat_eth_src_mac,
- ip_src_addr => stat_ip_src_addr,
- udp_src_port => sst_udp_src_port
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
);
END GENERATE;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index 11e331a80e0267d8ef97720e36756d7f188a7426..ab3d08b91f394964b07440c87d29a487bbe350b4 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -99,7 +99,8 @@ ENTITY node_sdp_adc_input_and_timing IS
jesd204b_sync_n : OUT STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0);
-- Streaming data output
- out_sosi_arr : OUT t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0)
+ out_sosi_arr : OUT t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
+ dp_bsn_source_restart : OUT STD_LOGIC
);
END node_sdp_adc_input_and_timing;
@@ -123,6 +124,9 @@ ARCHITECTURE str OF node_sdp_adc_input_and_timing IS
SIGNAL rx_rst : STD_LOGIC;
SIGNAL rx_sysref : STD_LOGIC;
+ SIGNAL arst : STD_LOGIC;
+ SIGNAL rx_bsn_source_restart : STD_LOGIC;
+
-- Sosis and sosi arrays
SIGNAL rx_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
SIGNAL dp_shiftram_snk_in_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
@@ -252,7 +256,9 @@ BEGIN
reg_miso => reg_bsn_source_v2_miso,
-- Streaming clock domain
- bs_sosi => bs_sosi
+ bs_sosi => bs_sosi,
+
+ bs_restart => rx_bsn_source_restart
);
u_bsn_trigger_wg : ENTITY dp_lib.mms_dp_bsn_scheduler
@@ -463,6 +469,24 @@ BEGIN
);
END GENERATE;
+ -- use common dc fifo for restart signal
+ u_common_fifo_dc_restart : ENTITY common_lib.common_fifo_dc
+ GENERIC MAP (
+ g_dat_w => 1,
+ g_nof_words => c_dp_fifo_dc_size
+ )
+ PORT MAP (
+ rst => arst,
+ wr_clk => rx_clk,
+ wr_dat(0) => rx_bsn_source_restart,
+ wr_req => bs_sosi.valid,
+ rd_clk => dp_clk,
+ rd_dat(0) => dp_bsn_source_restart,
+ rd_req => '1'
+ );
+
+ arst <= rx_rst OR dp_rst;
+
-----------------------------------------------------------------------------
-- JESD Control register
-----------------------------------------------------------------------------
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
index 51de3371d0576e1947962dd91cc07a744f23160a..69356104b26cf09270a30ac75a2be71193b51ce8 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
@@ -63,8 +63,10 @@ ENTITY node_sdp_filterbank IS
sst_udp_sosi : OUT t_dp_sosi;
sst_udp_siso : IN t_dp_siso := c_dp_siso_rst;
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
+ dp_bsn_source_restart : IN STD_LOGIC;
+
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
reg_si_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_si_miso : OUT t_mem_miso;
@@ -99,6 +101,8 @@ ARCHITECTURE str OF node_sdp_filterbank IS
CONSTANT c_nof_masters : POSITIVE := 2;
+ CONSTANT c_si_pipeline : NATURAL := 1;
+
SIGNAL ram_st_sst_mosi_arr : t_mem_mosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL ram_st_sst_miso_arr : t_mem_miso_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
@@ -119,8 +123,9 @@ ARCHITECTURE str OF node_sdp_filterbank IS
SIGNAL dp_selector_out_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL scope_sosi_arr : t_dp_sosi_integer_arr(c_sdp_S_pn-1 DOWNTO 0);
- SIGNAL selector_en : STD_LOGIC;
- SIGNAL subband_calibrated_flag : STD_LOGIC;
+ SIGNAL selector_en : STD_LOGIC;
+ SIGNAL subband_calibrated_flag : STD_LOGIC;
+ SIGNAL dp_bsn_source_restart_pipe : STD_LOGIC;
BEGIN
---------------------------------------------------------------
-- SPECTRAL INVERSION
@@ -128,7 +133,7 @@ BEGIN
u_si_arr : ENTITY si_lib.si_arr
GENERIC MAP (
g_nof_streams => c_sdp_S_pn,
- g_pipeline => 1,
+ g_pipeline => c_si_pipeline,
g_dat_w => c_sdp_W_adc
)
PORT MAP(
@@ -156,7 +161,19 @@ BEGIN
wpfb_unit_in_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(si_sosi_arr(2*I+1).data);
END LOOP;
END PROCESS;
-
+
+ -- pipeline bsn restart signal to keep dp_bsn_source_restart aligned with si_sosi_arr
+ u_common_pipeline_sl : ENTITY common_lib.common_pipeline_sl
+ GENERIC MAP (
+ g_pipeline => c_si_pipeline
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_dat => dp_bsn_source_restart,
+ out_dat => dp_bsn_source_restart_pipe
+ );
+
-- PFB
u_wpfb_unit_dev : ENTITY wpfb_lib.wpfb_unit_dev
GENERIC MAP (
@@ -177,7 +194,9 @@ BEGIN
in_sosi_arr => wpfb_unit_in_sosi_arr,
fil_sosi_arr => wpfb_unit_fil_sosi_arr,
- out_sosi_arr => wpfb_unit_out_sosi_arr
+ out_sosi_arr => wpfb_unit_out_sosi_arr,
+
+ dp_bsn_source_restart => dp_bsn_source_restart_pipe
);
-- Output PFB streams
diff --git a/libraries/base/dp/hdllib.cfg b/libraries/base/dp/hdllib.cfg
index 07fb20fc3763feb3845b327bf748ccf5e033f7d4..35eb45f99ba31ed7867ddb948437b64012e445f1 100644
--- a/libraries/base/dp/hdllib.cfg
+++ b/libraries/base/dp/hdllib.cfg
@@ -256,6 +256,7 @@ test_bench_files =
tb/vhdl/tb_dp_xonoff_reg_timeout.vhd
tb/vhdl/tb_dp_sync_insert.vhd
tb/vhdl/tb_dp_sync_insert_v2.vhd
+ tb/vhdl/tb_dp_sync_recover.vhd
tb/vhdl/tb_dp_folder.vhd
tb/vhdl/tb_dp_switch.vhd
tb/vhdl/tb_dp_counter_func.vhd
@@ -308,6 +309,7 @@ test_bench_files =
tb/vhdl/tb_tb_dp_sync_checker.vhd
tb/vhdl/tb_tb_dp_sync_insert.vhd
tb/vhdl/tb_tb_dp_sync_insert_v2.vhd
+ tb/vhdl/tb_tb_dp_sync_recover.vhd
tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd
tb/vhdl/tb_tb_mms_dp_force_data_serial_arr.vhd
tb/vhdl/tb_tb_mms_dp_gain_arr.vhd
@@ -370,6 +372,7 @@ regression_test_vhdl =
tb/vhdl/tb_mms_dp_sync_checker.vhd
tb/vhdl/tb_tb_dp_sync_insert.vhd
tb/vhdl/tb_tb_dp_sync_insert_v2.vhd
+ tb/vhdl/tb_tb_dp_sync_recover.vhd
tb/vhdl/tb_dp_counter_func.vhd
tb/vhdl/tb_tb_dp_counter.vhd
tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
index f73edbf022860bb34582210adf067f6f0e8fab46..66598b4d337c739710274cbe38b8ebebb8d85bf6 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
@@ -58,6 +58,7 @@ ENTITY dp_bsn_source_v2 IS
dp_on_pps : IN STD_LOGIC;
dp_on_status : OUT STD_LOGIC;
+ bs_restart : OUT STD_LOGIC;
nof_clk_per_sync : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := TO_UVEC(g_nof_clk_per_sync, c_word_w);
bsn_init : IN STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
@@ -102,6 +103,7 @@ ARCHITECTURE rtl OF dp_bsn_source_v2 IS
SIGNAL i_dp_on_status : STD_LOGIC;
SIGNAL nxt_dp_on_status : STD_LOGIC;
+ SIGNAL nxt_bs_restart : STD_LOGIC;
SIGNAL nxt_bsn_time_offset_cnt : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
SIGNAL bsn_time_offset_cnt : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
@@ -132,6 +134,7 @@ BEGIN
nxt_clk_cnt <= INCR_UVEC(clk_cnt, 1);
nxt_sync <= sync;
nxt_dp_on_status <= i_dp_on_status;
+ nxt_bs_restart <= '0';
nxt_bsn_time_offset_cnt <= bsn_time_offset_cnt;
nxt_current_bsn_time_offset <= bsn_time_offset;
@@ -187,6 +190,9 @@ BEGIN
nxt_src_out.sync <= '1';
nxt_sync <= '0';
END IF;
+ IF i_dp_on_status = '0' THEN -- transition from 0 to 1 is a (re)start
+ nxt_bs_restart <= '1'; -- bs_restart indicates a restart as a pulse on the sop (and sync if dp_on_pps is used).
+ END IF;
WHEN s_dp_on =>
nxt_src_out.valid <= '1';
@@ -221,6 +227,7 @@ BEGIN
sync <= '0';
block_size_cnt <= (OTHERS=>'0');
i_dp_on_status <= '0';
+ bs_restart <= '0';
bsn_time_offset_cnt <= (OTHERS=>'0');
ELSIF rising_edge(clk) THEN
prev_state <= state;
@@ -230,6 +237,7 @@ BEGIN
sync <= nxt_sync;
block_size_cnt <= nxt_block_size_cnt;
i_dp_on_status <= nxt_dp_on_status;
+ bs_restart <= nxt_bs_restart;
bsn_time_offset_cnt <= nxt_bsn_time_offset_cnt;
i_current_bsn_time_offset <= nxt_current_bsn_time_offset;
END IF;
diff --git a/libraries/base/dp/src/vhdl/dp_sync_recover.vhd b/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
index 5ad7ffb05520724abe162317f91bf9ea86793f2d..f4ff1b9746c7856b039b387c034a1403e8ff3a80 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
@@ -20,16 +20,21 @@
-------------------------------------------------------------------------------
-- Author : R vd Walle
--- Purpose : Recover DP control signals (sync, valid, sop, eop, bsn) from input with only valid and sync.
--- Description: dp_sync_recover generates the control signals based on in_sosi.sync, in_sosi.bsn and val.
--- . A data counter is used to count the valids from the input "val" and compare to g_nof_data_per_block to generate sop/eop.
+-- Purpose : Recover DP control signals (sync, valid, sop, eop, bsn) from input of a processing component and the out valid of that component.
+-- Description: dp_sync_recover generates the control signals based on in_sosi.sync, in_sosi.bsn and recover_val.
+-- dp_sync_recover is used in combination with a processing component that doesn't keep the control signals. By connecting the input of the
+-- processing component to in_sosi and the valid of the output of the processing component to recover_val, dp_sync_recover will generate the
+-- missing control signals at out_sosi.
+-- . A data counter is used to count the valids from the input "recover_val" and compare to g_nof_data_per_block to generate sop/eop.
-- . A block counter is used generate the BSN
-- . The BSN at sync of in_sosi is captured to determine when to generate the sync at the output.
--- . out_sosi.valid is directly connected to val.
+-- . IN recover_val is used to indicate when to start outputting the control signals. recover_val is also used for out_sosi.valid, these are connected as wires, so no latency.
+-- . IN restart is used to restart the counters. On the restart pulse the in_sosi.bsn is used as the initial value for the bsn counter.
-- Remarks:
--- . The val input signal should be connected to the desired valid of the output. It determines when
--- the first block will start.
--- . g_initial_bsn can be used to start with a non-zero bsn
+-- . The recover_val input signal should be connected to the valid of the output of the related processing component. It determines when
+-- the first block will start after a (re)start.
+-- . It is assumed that the restart pulse is synchronous with in_sosi.sop (if it would have a sop)
+-- . IN recover_val should have at least a latency of 1 compared to in_sosi.
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib;
@@ -41,19 +46,19 @@ USE work.dp_stream_pkg.ALL;
ENTITY dp_sync_recover IS
GENERIC (
- g_initial_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0) := (OTHERS => '0');
g_nof_data_per_block : POSITIVE := 1
);
PORT (
-- Clocks and reset
- dp_rst : IN STD_LOGIC;
- dp_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
- in_sosi : IN t_dp_sosi := c_dp_sosi_rst;
- val : IN STD_LOGIC; -- valid at the output
- -- Streaming source
- out_sosi : OUT t_dp_sosi
+ in_sosi : IN t_dp_sosi := c_dp_sosi_rst;
+ recover_val : IN STD_LOGIC; -- valid of the out_sosi that needs to be recoverd.
+ restart : IN STD_LOGIC := '0'; -- pulse to restart bsn counter
+
+ out_sosi : OUT t_dp_sosi
);
END dp_sync_recover;
@@ -61,13 +66,17 @@ END dp_sync_recover;
ARCHITECTURE rtl OF dp_sync_recover IS
TYPE t_reg IS RECORD -- local registers
- bsn_at_sync : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0);
- data_cnt : NATURAL RANGE 0 TO g_nof_data_per_block;
- out_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0);
- out_sosi : t_dp_sosi;
+ bsn_at_sync : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0); -- bsn to store at which to generate a sync pulse.
+ bsn_before_restart : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0); -- bsn to store at which to restart te bsn counter.
+ bsn_at_restart : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0); -- bsn to store inital bsn after (re)start.
+ restart : STD_LOGIC;
+ started : STD_LOGIC;
+ data_cnt : NATURAL RANGE 0 TO g_nof_data_per_block;
+ out_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w -1 DOWNTO 0);
+ out_sosi : t_dp_sosi;
END RECORD;
- CONSTANT c_reg_rst : t_reg := ( (OTHERS => '0'), 0, g_initial_bsn, c_dp_sosi_rst);
+ CONSTANT c_reg_rst : t_reg := ( (OTHERS => '0'), (OTHERS => '0'), (OTHERS => '0'), '0', '0', 0, (OTHERS => '0'), c_dp_sosi_rst);
-- Define the local registers in t_reg record
SIGNAL r : t_reg;
@@ -86,37 +95,55 @@ BEGIN
END IF;
END PROCESS;
- p_comb : PROCESS(r, in_sosi, val)
+ p_comb : PROCESS(r, in_sosi, recover_val)
VARIABLE v : t_reg;
BEGIN
v := r;
v.out_sosi := c_dp_sosi_rst;
- v.out_sosi.valid := val;
+ v.out_sosi.valid := recover_val;
v.out_sosi.bsn := r.out_sosi.bsn;
- IF in_sosi.sync = '1' THEN
- v.bsn_at_sync := in_sosi.bsn;
+ IF r.restart = '0' AND restart = '0' THEN -- keep track of last bsn before restart
+ v.bsn_before_restart := in_sosi.bsn;
+ END IF;
+
+ IF in_sosi.sync = '1' THEN -- capture bsn at sync
+ v.bsn_at_sync := in_sosi.bsn;
END IF;
- IF val = '1' THEN
+
+ IF recover_val = '1' THEN
v.data_cnt := r.data_cnt + 1;
- IF r.data_cnt = 0 THEN
+ IF r.data_cnt = 0 THEN -- generate sop + bsn
v.out_sosi.sop := '1';
- v.out_bsn := STD_LOGIC_VECTOR(UNSIGNED(r.out_bsn) + 1);
+ v.out_bsn := STD_LOGIC_VECTOR(UNSIGNED(r.out_bsn) + 1); -- increase block counter
v.out_sosi.bsn := r.out_bsn;
- IF r.out_bsn = r.bsn_at_sync THEN
- v.out_sosi.sync := '1';
+ IF r.out_bsn = r.bsn_at_sync THEN -- generate sync pulse
+ v.out_sosi.sync := '1';
END IF;
END IF;
- IF r.data_cnt = g_nof_data_per_block-1 THEN
+ IF r.data_cnt = g_nof_data_per_block-1 THEN --reset data counter and generate eop.
v.data_cnt := 0;
v.out_sosi.eop := '1';
END IF;
- ELSE
- v.out_sosi := c_reg_rst.out_sosi;
- v.out_bsn := c_reg_rst.out_bsn;
- v.data_cnt := c_reg_rst.data_cnt;
END IF;
-
+
+ -- overwrite v.out_bsn if a restart has occurd.
+ IF restart = '1' THEN -- Capture BSN at restart
+ v.bsn_at_restart := in_sosi.bsn; -- initial bsn value
+ v.restart := '1';
+ IF r.started = '0' OR r.out_sosi.bsn = r.bsn_before_restart THEN -- if restarted for the first time or if the restart should happen at the current bsn use the in_sosi.bsn immidiatly.
+ v.started := '1';
+ v.restart := '0';
+ v.out_bsn := in_sosi.bsn;
+ END IF;
+ END IF;
+
+ -- If the latency is larger than one block, it is needed wait with the restart until the last block has arrived.
+ IF r.restart = '1' AND r.out_sosi.bsn = r.bsn_before_restart THEN -- set bsn to initial value after restart
+ v.out_bsn := r.bsn_at_restart;
+ v.restart := '0';
+ END IF;
+
nxt_r <= v;
END PROCESS;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
index 9d096d2a96a0c3943ce7a037d5565206d7e823bf..bc82cda1f4970574aa8da25eee1ecfd57bec1d35 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
@@ -50,7 +50,9 @@ ENTITY mms_dp_bsn_source_v2 IS
reg_miso : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
-- Streaming clock domain
- bs_sosi : OUT t_dp_sosi
+ bs_sosi : OUT t_dp_sosi;
+
+ bs_restart : OUT STD_LOGIC -- pulse to indicate if the bsn_source has restarted
);
END mms_dp_bsn_source_v2;
@@ -115,6 +117,7 @@ BEGIN
dp_on => dp_on,
dp_on_pps => dp_on_pps,
dp_on_status => dp_on_status,
+ bs_restart => bs_restart,
bsn_init => bsn_init,
nof_clk_per_sync => nof_clk_per_sync,
bsn_time_offset => bsn_time_offset,
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7650451cd09ac897b307e35667f2ad58aa3fed3b
--- /dev/null
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
@@ -0,0 +1,235 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Purpose: Verify dp_sync_recover
+-- Description: The tb verifies:
+-- . data valid gaps between blocks
+-- . data valid gaps within blocks
+-- . output sop, eop, valid, bsn and sync
+-- . restarts of the dut using IN restart of the dut
+-- Usage:
+-- > as 8
+-- > run -all
+--
+-- * The tb is self stopping because tb_end will stop the simulation by
+-- stopping the clk and thus all toggling.
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_lfsr_sequences_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE dp_lib.tb_dp_pkg.ALL;
+
+
+ENTITY tb_dp_sync_recover IS
+ GENERIC (
+ g_nof_data_per_block : NATURAL := 16;
+ g_nof_blk_per_sync : NATURAL := 8;
+ g_gap_size_during_block : NATURAL := 0;
+ g_gap_size_between_block : NATURAL := 0;
+ g_init_bsn : NATURAL := 23;
+ g_bsn_at_restart : NATURAL := 40; -- the bsn index at which to restart the dut.
+ g_dut_latency : NATURAL := 25;
+ g_nof_repeat : NATURAL := 14
+ );
+END tb_dp_sync_recover;
+
+
+ARCHITECTURE tb OF tb_dp_sync_recover IS
+
+ CONSTANT c_dp_clk_period : TIME := 5 ns;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL dp_clk : STD_LOGIC := '1';
+ SIGNAL rst : STD_LOGIC := '1';
+
+ -- DUT
+ SIGNAL ref_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL out_sosi : t_dp_sosi;
+ SIGNAL restart : STD_LOGIC := '0';
+
+ -- Verification
+ SIGNAL dly_valid_arr : STD_LOGIC_VECTOR(0 TO g_dut_latency) := (OTHERS=>'0');
+ SIGNAL dly_ref_sosi_arr : t_dp_sosi_arr(0 TO g_dut_latency) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL exp_sync : STD_LOGIC := '0';
+ SIGNAL out_hold_sop : STD_LOGIC := '0';
+ SIGNAL exp_size : NATURAL := g_nof_data_per_block;
+ SIGNAL cnt_size : NATURAL;
+
+BEGIN
+
+ dp_clk <= (NOT dp_clk) OR tb_end AFTER c_dp_clk_period/2;
+ rst <= '1', '0' AFTER c_dp_clk_period*7;
+
+ ------------------------------------------------------------------------------
+ -- STIMULI
+ ------------------------------------------------------------------------------
+
+ p_stimuli : PROCESS
+ VARIABLE v_bsn : NATURAL;
+ BEGIN
+ proc_common_wait_until_low(dp_clk, rst);
+ proc_common_wait_some_cycles(dp_clk, 5);
+
+ FOR I IN 0 TO g_nof_repeat-1 LOOP
+ -- Generate first block with sync
+ ref_sosi.sync <= '1';
+ ref_sosi.sop <= '1';
+ ref_sosi.valid <= '1';
+ v_bsn := g_init_bsn + I * g_nof_blk_per_sync;
+ IF v_bsn = g_bsn_at_restart OR I = 0 THEN
+ v_bsn := g_init_bsn;
+ restart <= '1';
+ ELSIF v_bsn > g_bsn_at_restart THEN
+ v_bsn := 2*g_init_bsn + I * g_nof_blk_per_sync - g_bsn_at_restart;
+ END IF;
+ ref_sosi.bsn <= TO_DP_BSN(v_bsn);
+ proc_common_wait_some_cycles(dp_clk, 1);
+ ref_sosi.sync <= '0';
+ ref_sosi.sop <= '0';
+ restart <= '0';
+
+ -- Optionally apply valid='0' during block of data
+ ref_sosi.valid <= '0';
+ proc_common_wait_some_cycles(dp_clk, g_gap_size_during_block);
+ ref_sosi.valid <= '1';
+
+ proc_common_wait_some_cycles(dp_clk, g_nof_data_per_block-2);
+ ref_sosi.eop <= '1';
+ proc_common_wait_some_cycles(dp_clk, 1);
+ ref_sosi.eop <= '0';
+ ref_sosi.valid <= '0';
+
+ -- Optionally apply valid='0' between block of data
+ proc_common_wait_some_cycles(dp_clk, g_gap_size_between_block);
+
+ -- Generate next blocks after sync
+ FOR J IN 0 TO g_nof_blk_per_sync-2 LOOP
+ v_bsn := g_init_bsn + I * g_nof_blk_per_sync + J + 1;
+ ref_sosi.sop <= '1';
+ ref_sosi.valid <= '1';
+ IF v_bsn = g_bsn_at_restart THEN
+ v_bsn := 2*g_init_bsn + I * g_nof_blk_per_sync + J + 1 - g_bsn_at_restart;
+ restart <= '1';
+ ELSIF v_bsn > g_bsn_at_restart THEN
+ v_bsn := 2*g_init_bsn + I * g_nof_blk_per_sync + J + 1 - g_bsn_at_restart;
+ END IF;
+
+ ref_sosi.bsn <= TO_DP_BSN(v_bsn);
+ proc_common_wait_some_cycles(dp_clk, 1);
+ ref_sosi.sync <= '0';
+ ref_sosi.sop <= '0';
+ restart <= '0';
+
+ -- Optionally apply valid='0' during block of data
+ ref_sosi.valid <= '0';
+ proc_common_wait_some_cycles(dp_clk, g_gap_size_during_block);
+ ref_sosi.valid <= '1';
+
+ proc_common_wait_some_cycles(dp_clk, g_nof_data_per_block-2);
+ ref_sosi.eop <= '1';
+ proc_common_wait_some_cycles(dp_clk, 1);
+ ref_sosi.eop <= '0';
+ ref_sosi.valid <= '0';
+
+ -- Optionally apply valid='0' between block of data
+ proc_common_wait_some_cycles(dp_clk, g_gap_size_between_block);
+ END LOOP;
+ END LOOP;
+
+ -- End of stimuli
+ proc_common_wait_some_cycles(dp_clk, 100);
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+
+ ref_sosi.data <= INCR_UVEC(ref_sosi.data, 1) WHEN rising_edge(dp_clk);
+ ref_sosi.re <= INCR_UVEC(ref_sosi.re, 2) WHEN rising_edge(dp_clk);
+ ref_sosi.im <= INCR_UVEC(ref_sosi.im, 3) WHEN rising_edge(dp_clk);
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ u_dut: ENTITY work.dp_sync_recover
+ GENERIC MAP (
+ g_nof_data_per_block => g_nof_data_per_block
+ )
+ PORT MAP (
+ dp_rst => rst,
+ dp_clk => dp_clk,
+
+ -- Streaming sink
+ in_sosi => ref_sosi,
+ recover_val => dly_ref_sosi_arr(g_dut_latency).valid,
+ restart => restart,
+ -- Streaming source
+ out_sosi => out_sosi
+ );
+
+ ------------------------------------------------------------------------------
+ -- Verification
+ -- . use some DUT specific verification
+ -- . use some general Verification means from tb_dp_pkg.vhd, dp_stream_verify.vhd
+ ------------------------------------------------------------------------------
+ dly_ref_sosi_arr(0) <= ref_sosi;
+ dly_ref_sosi_arr(1 TO g_dut_latency) <= dly_ref_sosi_arr(0 TO g_dut_latency-1) WHEN rising_edge(dp_clk);
+
+ p_exp_sync : PROCESS(dp_clk)
+ VARIABLE blk_cnt : NATURAL := 0;
+ BEGIN
+ IF rising_edge(dp_clk) THEN
+ exp_sync <= '0';
+ IF dly_ref_sosi_arr(g_dut_latency-1).sop = '1' THEN
+ IF dly_ref_sosi_arr(g_dut_latency-1).sync = '1' OR blk_cnt >= g_nof_blk_per_sync-1 THEN
+ blk_cnt := 0;
+ exp_sync <= '1';
+ ELSE
+ blk_cnt := blk_cnt+1;
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ p_verify_out_sosi : PROCESS(dp_clk)
+ BEGIN
+ IF rising_edge(dp_clk) THEN
+ ASSERT out_sosi.valid = dly_ref_sosi_arr(g_dut_latency).valid REPORT "Wrong out_sosi.valid" SEVERITY ERROR;
+ ASSERT out_sosi.sop = dly_ref_sosi_arr(g_dut_latency).sop REPORT "Wrong out_sosi.sop" SEVERITY ERROR;
+ ASSERT out_sosi.eop = dly_ref_sosi_arr(g_dut_latency).eop REPORT "Wrong out_sosi.eop" SEVERITY ERROR;
+ ASSERT out_sosi.bsn = dly_ref_sosi_arr(g_dut_latency).bsn REPORT "Wrong out_sosi.bsn" SEVERITY ERROR;
+ ASSERT out_sosi.sync = dly_ref_sosi_arr(g_dut_latency).sync REPORT "Wrong out_sosi.sync" SEVERITY ERROR;
+ END IF;
+ END PROCESS;
+
+ -- Verify output packet ctrl
+ proc_dp_verify_sop_and_eop(dp_clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, out_hold_sop);
+ -- Verify output packet block size
+ proc_dp_verify_block_size(exp_size, dp_clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, cnt_size);
+
+
+
+END tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e91f0319413b94a924b926df1fcc815113dcb4a8
--- /dev/null
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd
@@ -0,0 +1,57 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Purpose: Verify multiple variations of tb_dp_sync_recover
+-- Description:
+-- Usage:
+-- > as 3
+-- > run -all
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY tb_tb_dp_sync_recover IS
+END tb_tb_dp_sync_recover;
+
+ARCHITECTURE tb OF tb_tb_dp_sync_recover IS
+ SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+BEGIN
+
+-- g_nof_data_per_block : NATURAL := 16;
+-- g_nof_blk_per_sync : NATURAL := 8;
+-- g_gap_size_during_block : NATURAL := 0;
+-- g_gap_size_between_block : NATURAL := 0;
+-- g_init_bsn : NATURAL := 23;
+-- g_bsn_at_restart : NATURAL := 40; -- the bsn index at which to restart the dut.
+-- g_dut_latency : NATURAL := 25;
+-- g_nof_repeat : NATURAL := 14
+
+ u_no_gaps : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 0, 0, 3, 50, 10, 14);
+ u_gap : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 1, 3, 3, 50, 10, 14);
+ u_restart_at_sync : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 1, 3, 3, 2*8+3, 10, 14);
+ u_restart_at_sync_hi : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 1, 3, 3, 2*8+3, 100, 14);
+ u_restart_at_sync_lo : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 1, 3, 3, 2*8+3, 1, 14);
+ u_high_latency : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 1, 3, 3, 50, 100, 14);
+ u_low_latency : ENTITY work.tb_dp_sync_recover GENERIC MAP(16, 8, 1, 3, 3, 50, 1, 14);
+
+END tb;
diff --git a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
index 071a6785a0266c3da24ea15d4c09cd7ffcf9f831..5188d93bd2cc1cc01f51cedbd5974a3e48a9eb5e 100644
--- a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
+++ b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
@@ -368,21 +368,22 @@ entity wpfb_unit_dev is
g_coefs_file_prefix : string := "data/coefs_wide" -- File prefix for the coefficients files.
);
port (
- dp_rst : in std_logic := '0';
- dp_clk : in std_logic;
- mm_rst : in std_logic;
- mm_clk : in std_logic;
- ram_fil_coefs_mosi : in t_mem_mosi := c_mem_mosi_rst;
- ram_fil_coefs_miso : out t_mem_miso;
- ram_st_sst_mosi : in t_mem_mosi := c_mem_mosi_rst; -- Subband statistics registers
- ram_st_sst_miso : out t_mem_miso;
- reg_bg_ctrl_mosi : in t_mem_mosi := c_mem_mosi_rst;
- reg_bg_ctrl_miso : out t_mem_miso;
- ram_bg_data_mosi : in t_mem_mosi := c_mem_mosi_rst;
- ram_bg_data_miso : out t_mem_miso;
- in_sosi_arr : in t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
- fil_sosi_arr : out t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
- out_sosi_arr : out t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0)
+ dp_rst : in std_logic := '0';
+ dp_clk : in std_logic;
+ mm_rst : in std_logic;
+ mm_clk : in std_logic;
+ ram_fil_coefs_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ ram_fil_coefs_miso : out t_mem_miso;
+ ram_st_sst_mosi : in t_mem_mosi := c_mem_mosi_rst; -- Subband statistics registers
+ ram_st_sst_miso : out t_mem_miso;
+ reg_bg_ctrl_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ reg_bg_ctrl_miso : out t_mem_miso;
+ ram_bg_data_mosi : in t_mem_mosi := c_mem_mosi_rst;
+ ram_bg_data_miso : out t_mem_miso;
+ in_sosi_arr : in t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
+ fil_sosi_arr : out t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
+ out_sosi_arr : out t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
+ dp_bsn_source_restart : in std_logic
);
end entity wpfb_unit_dev;
@@ -447,14 +448,12 @@ architecture str of wpfb_unit_dev is
signal fft_out_im_arr_pipe : t_fft_slv_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
signal fft_out_val_arr : std_logic_vector(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
- signal fft_out_sosi : t_dp_sosi;
- signal fft_out_sosi_arr : t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0) := (others => c_dp_sosi_rst);
-
signal pfb_out_sosi_arr : t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0) := (others => c_dp_sosi_rst);
signal ctrl_pfb_out_sosi : t_dp_sosi := c_dp_sosi_rst;
type reg_type is record
in_sosi_arr : t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
+ bsn_source_restart : STD_LOGIC;
end record;
signal r, rin : reg_type;
@@ -465,9 +464,10 @@ begin
comb : process(r, in_sosi_arr)
variable v : reg_type;
begin
- v := r;
- v.in_sosi_arr := in_sosi_arr;
- rin <= v;
+ v := r;
+ v.in_sosi_arr := in_sosi_arr;
+ v.bsn_source_restart := dp_bsn_source_restart;
+ rin <= v;
end process comb;
regs : process(dp_clk)
@@ -621,10 +621,6 @@ begin
-- Capture input BSN at input sync and pass the captured input BSN it on to PFB output sync.
-- The FFT output valid defines PFB output sync, sop, eop.
- fft_out_sosi.sync <= r.in_sosi_arr(0).sync;
- fft_out_sosi.bsn <= r.in_sosi_arr(0).bsn;
- fft_out_sosi.valid <= fft_out_val_arr(0);
-
u_dp_sync_recover : ENTITY dp_lib.dp_sync_recover
GENERIC MAP(
g_nof_data_per_block => c_nof_valid_per_block
@@ -633,10 +629,10 @@ begin
dp_rst => dp_rst,
dp_clk => dp_clk,
- in_sosi => fft_out_sosi,
- val => fft_out_sosi.valid,
-
- out_sosi => ctrl_pfb_out_sosi
+ in_sosi => r.in_sosi_arr(0),
+ recover_val => fft_out_val_arr(0),
+ restart => r.bsn_source_restart,
+ out_sosi => ctrl_pfb_out_sosi
);
wire_pfb_out_sosi_arr : for I in 0 to g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 generate
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_dev.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_dev.vhd
index f789359e1d3410443b43e3e84fa048ff4c21290c..61eb02d33154f9d5913df6b2ca23e7f768f61a5b 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_dev.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_dev.vhd
@@ -330,7 +330,8 @@ BEGIN
ram_bg_data_mosi => ram_diag_bg_pfb_mosi,
ram_bg_data_miso => ram_diag_bg_pfb_miso,
in_sosi_arr => bg_sosi_arr,
- out_sosi_arr => out_sosi_arr
+ out_sosi_arr => out_sosi_arr,
+ dp_bsn_source_restart => bg_sosi_arr(0).sync
);
time_map : process is
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
index cc5285d65f13cb922e06d09bbee6c2fecf80c9e8..bf8e6cb17e5dfd61f20376510f7a5174c379d400 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
@@ -486,7 +486,8 @@ begin
ram_bg_data_miso => open,
in_sosi_arr => in_sosi_arr,
fil_sosi_arr => fil_sosi_arr,
- out_sosi_arr => out_sosi_arr
+ out_sosi_arr => out_sosi_arr,
+ dp_bsn_source_restart => in_sosi_arr(0).sync
);
p_fil_sosi_arr : process(fil_sosi_arr)
@@ -804,4 +805,4 @@ begin
out_val => open
);
-end tb;
\ No newline at end of file
+end tb;