From f26c22689811f7aec5bb9724c51a1345ccc69703 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Wed, 4 May 2022 13:27:51 +0200
Subject: [PATCH] Renamed c_tech_arria10 into c_tech_arria10_proto to more
easily find it with e.g. grep.
---
libraries/technology/10gbase_r/tech_10gbase_r.vhd | 2 +-
libraries/technology/clkbuf/tech_clkbuf.vhd | 2 +-
libraries/technology/ddr/tech_ddr.vhd | 2 +-
libraries/technology/ddr/tech_ddr_pkg.vhd | 2 +-
libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd | 2 +-
libraries/technology/eth_10g/tech_eth_10g.vhd | 2 +-
libraries/technology/eth_10g/tech_eth_10g_clocks.vhd | 2 +-
libraries/technology/fifo/tech_fifo_dc.vhd | 2 +-
libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd | 2 +-
libraries/technology/fifo/tech_fifo_sc.vhd | 2 +-
libraries/technology/flash/tech_flash_asmi_parallel.vhd | 2 +-
libraries/technology/flash/tech_flash_component_pkg.vhd | 4 ++--
libraries/technology/flash/tech_flash_remote_update.vhd | 2 +-
libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd | 2 +-
.../technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd | 2 +-
.../fractional_pll/tech_fractional_pll_clk125.vhd | 2 +-
.../fractional_pll/tech_fractional_pll_clk200.vhd | 2 +-
libraries/technology/iobuf/tech_iobuf_ddio_in.vhd | 2 +-
libraries/technology/iobuf/tech_iobuf_ddio_out.vhd | 2 +-
libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd | 2 +-
libraries/technology/mac_10g/tech_mac_10g.vhd | 6 +++---
libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd | 6 +++---
libraries/technology/memory/tech_memory_ram_cr_cw.vhd | 2 +-
libraries/technology/memory/tech_memory_ram_crw_crw.vhd | 2 +-
libraries/technology/memory/tech_memory_ram_crwk_crw.vhd | 2 +-
libraries/technology/memory/tech_memory_ram_r_w.vhd | 2 +-
libraries/technology/memory/tech_memory_rom_r.vhd | 2 +-
libraries/technology/mult/tech_complex_mult.vhd | 6 +++---
libraries/technology/mult/tech_mult.vhd | 4 ++--
libraries/technology/pll/tech_pll_clk125.vhd | 2 +-
libraries/technology/pll/tech_pll_clk200.vhd | 2 +-
libraries/technology/pll/tech_pll_clk25.vhd | 2 +-
libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd | 2 +-
libraries/technology/technology_pkg.vhd | 2 +-
libraries/technology/tse/tb_tech_tse_pkg.vhd | 4 ++--
libraries/technology/tse/tech_tse.vhd | 2 +-
36 files changed, 45 insertions(+), 45 deletions(-)
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r.vhd b/libraries/technology/10gbase_r/tech_10gbase_r.vhd
index 8d8d53de97..dfa1ca0e17 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r.vhd
@@ -72,7 +72,7 @@ ARCHITECTURE str OF tech_10gbase_r IS
BEGIN
- gen_ip_arria10 : IF c_use_technology=TRUE AND g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF c_use_technology=TRUE AND g_technology=c_tech_arria10_proto GENERATE
u0 : ENTITY work.tech_10gbase_r_arria10
GENERIC MAP (g_sim, g_nof_channels)
PORT MAP (tr_ref_clk_644,
diff --git a/libraries/technology/clkbuf/tech_clkbuf.vhd b/libraries/technology/clkbuf/tech_clkbuf.vhd
index 817998a412..567a98e134 100644
--- a/libraries/technology/clkbuf/tech_clkbuf.vhd
+++ b/libraries/technology/clkbuf/tech_clkbuf.vhd
@@ -50,7 +50,7 @@ BEGIN
-- ip_arria10
-----------------------------------------------------------------------------
- gen_ip_arria10 : IF g_technology=c_tech_arria10 AND g_clock_net="GLOBAL" GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto AND g_clock_net="GLOBAL" GENERATE
u0 : ip_arria10_clkbuf_global
PORT MAP (
inclk => inclk, -- inclk
diff --git a/libraries/technology/ddr/tech_ddr.vhd b/libraries/technology/ddr/tech_ddr.vhd
index e27d82cdba..d323d663c3 100644
--- a/libraries/technology/ddr/tech_ddr.vhd
+++ b/libraries/technology/ddr/tech_ddr.vhd
@@ -86,7 +86,7 @@ BEGIN
phy3_in, phy3_io, phy3_ou);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ENTITY work.tech_ddr_arria10
GENERIC MAP (g_tech_ddr)
PORT MAP (ref_clk, ref_rst,
diff --git a/libraries/technology/ddr/tech_ddr_pkg.vhd b/libraries/technology/ddr/tech_ddr_pkg.vhd
index dd42a50691..0b0d8898b1 100644
--- a/libraries/technology/ddr/tech_ddr_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_pkg.vhd
@@ -199,7 +199,7 @@ PACKAGE BODY tech_ddr_pkg IS
BEGIN
CASE g_technology IS
WHEN c_tech_stratixiv => RETURN g_ddr3; -- unb1
- WHEN c_tech_arria10 => RETURN g_ddr4; -- unb2
+ WHEN c_tech_arria10_proto => RETURN g_ddr4; -- unb2
WHEN c_tech_arria10_e3sge3 => RETURN g_ddr4; -- unb2
WHEN c_tech_arria10_e1sg => RETURN g_ddr4; -- unb2b
WHEN c_tech_arria10_e2sg => RETURN g_ddr4; -- unb2c
diff --git a/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd b/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd
index c7042228db..8b9f646885 100644
--- a/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd
+++ b/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd
@@ -26,7 +26,7 @@
-- The tb is self checking based on that tb_tech_eth_10g is self checking
-- and both tb_tech_eth_10g instances send the same and expect the same.
-- Remarks:
--- . For c_tech_arria10 the test fails when g_nof_10ppm /= 0 (erko, 21 nov 2014)
+-- . For c_tech_arria10_proto the test fails when g_nof_10ppm /= 0 (erko, 21 nov 2014)
-- . For c_tech_stratixiv the test fails when g_nof_10ppm /= 0 (erko, 5 dec 2014)
-- Usage:
-- > as 16
diff --git a/libraries/technology/eth_10g/tech_eth_10g.vhd b/libraries/technology/eth_10g/tech_eth_10g.vhd
index 901ffac3b5..e783a5ea94 100644
--- a/libraries/technology/eth_10g/tech_eth_10g.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g.vhd
@@ -181,7 +181,7 @@ BEGIN
);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ENTITY work.tech_eth_10g_arria10
GENERIC MAP (
g_sim => g_sim,
diff --git a/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd b/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd
index 1e5cf5a870..239beeecb9 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd
@@ -85,7 +85,7 @@ BEGIN
eth_rx_rst_arr <= rx_rst_arr;
END GENERATE;
- gen_clocks_10gbase_r : IF g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg GENERATE
+ gen_clocks_10gbase_r : IF g_technology=c_tech_arria10_proto OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg GENERATE
eth_tx_clk_arr <= (OTHERS=>tr_ref_clk_156);
eth_tx_rst_arr <= (OTHERS=>tr_ref_rst_156);
diff --git a/libraries/technology/fifo/tech_fifo_dc.vhd b/libraries/technology/fifo/tech_fifo_dc.vhd
index 997612ba61..179aa1ff4c 100644
--- a/libraries/technology/fifo/tech_fifo_dc.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc.vhd
@@ -65,7 +65,7 @@ BEGIN
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_fifo_dc
GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
diff --git a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
index 5aba78979b..58352cd3a6 100644
--- a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
@@ -65,7 +65,7 @@ BEGIN
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_fifo_dc_mixed_widths
GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
diff --git a/libraries/technology/fifo/tech_fifo_sc.vhd b/libraries/technology/fifo/tech_fifo_sc.vhd
index 4e95260d01..2694bc2e8b 100644
--- a/libraries/technology/fifo/tech_fifo_sc.vhd
+++ b/libraries/technology/fifo/tech_fifo_sc.vhd
@@ -63,7 +63,7 @@ BEGIN
PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_fifo_sc
GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
diff --git a/libraries/technology/flash/tech_flash_asmi_parallel.vhd b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
index b6979cc495..b91e7ee92f 100644
--- a/libraries/technology/flash/tech_flash_asmi_parallel.vhd
+++ b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
@@ -75,7 +75,7 @@ BEGIN
-- Note 1: addr must be 32 bits
-- Note 2: need ports for reset, en4b_addr
-- Note 3: ug_altasmi_parallel.pdf not clear what sce(2 downto 0) is for
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_asmi_parallel
PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write, reset, sce, en4b_addr);
END GENERATE;
diff --git a/libraries/technology/flash/tech_flash_component_pkg.vhd b/libraries/technology/flash/tech_flash_component_pkg.vhd
index 5839bf349d..0ecf1453f0 100644
--- a/libraries/technology/flash/tech_flash_component_pkg.vhd
+++ b/libraries/technology/flash/tech_flash_component_pkg.vhd
@@ -248,7 +248,7 @@ package body tech_flash_component_pkg is
if technology = c_tech_stratixiv then
return 24;
end if;
- if technology = c_tech_arria10 then
+ if technology = c_tech_arria10_proto then
return 32;
end if;
if technology = c_tech_arria10_e3sge3 or technology = c_tech_arria10_e1sg or technology = c_tech_arria10_e2sg then
@@ -261,7 +261,7 @@ package body tech_flash_component_pkg is
if technology = c_tech_stratixiv then
return 24;
end if;
- if technology = c_tech_arria10 then
+ if technology = c_tech_arria10_proto then
return 32;
end if;
if technology = c_tech_arria10_e3sge3 or technology = c_tech_arria10_e1sg or technology = c_tech_arria10_e2sg then
diff --git a/libraries/technology/flash/tech_flash_remote_update.vhd b/libraries/technology/flash/tech_flash_remote_update.vhd
index 5d668f11b5..e30a5affdb 100644
--- a/libraries/technology/flash/tech_flash_remote_update.vhd
+++ b/libraries/technology/flash/tech_flash_remote_update.vhd
@@ -65,7 +65,7 @@ BEGIN
-- note 1: data_in and data_out must increase to 32 bits
-- note 2: EPCQ-L1024 not yet supported in IP editor
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_remote_update
PORT MAP (clock, data_in, param, read_param, reconfig, reset, reset_timer, write_param, busy, data_out);
END GENERATE;
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
index 4708a81596..446ece63fa 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
@@ -49,7 +49,7 @@ ARCHITECTURE str OF tech_fpga_temp_sens IS
BEGIN
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_temp_sense
PORT MAP (
corectl => corectl, -- corectl.corectl
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
index e67b45a399..670ac1064a 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
@@ -57,7 +57,7 @@ ARCHITECTURE str OF tech_fpga_voltage_sens IS
BEGIN
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_voltage_sense
PORT MAP (
clock_clk => clock_clk,
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
index 416cfaad64..5b38f8b5c9 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
@@ -50,7 +50,7 @@ ARCHITECTURE str OF tech_fractional_pll_clk125 IS
BEGIN
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_fractional_pll_clk125
PORT MAP (
outclk0 => c0, -- outclk0.clk
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
index 93a08d7957..aed39a9266 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
@@ -49,7 +49,7 @@ ARCHITECTURE str OF tech_fractional_pll_clk200 IS
BEGIN
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_fractional_pll_clk200
PORT MAP (
outclk0 => c0, -- outclk0.clk
diff --git a/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd b/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
index 75a3811459..4222dd7683 100644
--- a/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
@@ -58,7 +58,7 @@ BEGIN
PORT MAP (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_ddio_in
GENERIC MAP (g_width)
PORT MAP (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
diff --git a/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd b/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
index 1547d4bd2c..fbfe0ce3f3 100644
--- a/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
@@ -58,7 +58,7 @@ BEGIN
PORT MAP (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_ddio_out
GENERIC MAP (g_width)
PORT MAP (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd
index af2746fccf..154fc42ac5 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd
@@ -127,7 +127,7 @@ PACKAGE BODY tb_tech_mac_10g_pkg IS
BEGIN
CASE c_technology IS
WHEN c_tech_stratixiv => proc_tech_mac_10g_setup_stratixiv(src_mac, mm_offset, mm_clk, mm_miso, mm_mosi);
- WHEN c_tech_arria10 => proc_tech_mac_10g_setup_arria10( src_mac, mm_offset, mm_clk, mm_miso, mm_mosi);
+ WHEN c_tech_arria10_proto => proc_tech_mac_10g_setup_arria10( src_mac, mm_offset, mm_clk, mm_miso, mm_mosi);
WHEN OTHERS => proc_tech_mac_10g_setup_stratixiv(src_mac, mm_offset, mm_clk, mm_miso, mm_mosi); -- default to c_tech_stratixiv
END CASE;
END proc_tech_mac_10g_setup;
diff --git a/libraries/technology/mac_10g/tech_mac_10g.vhd b/libraries/technology/mac_10g/tech_mac_10g.vhd
index 8a5cf23b68..52591a737e 100644
--- a/libraries/technology/mac_10g/tech_mac_10g.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g.vhd
@@ -118,8 +118,8 @@ END tech_mac_10g;
ARCHITECTURE str OF tech_mac_10g IS
-- Adapt ST ready latency 1 to IP ready latency
- CONSTANT c_ip_tx_ready_latency : NATURAL := sel_a_b(g_technology=c_tech_stratixiv OR g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg, 0, 1);
- CONSTANT c_ip_rx_ready_latency : NATURAL := sel_a_b(g_technology=c_tech_stratixiv OR g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg, 0, 1);
+ CONSTANT c_ip_tx_ready_latency : NATURAL := sel_a_b(g_technology=c_tech_stratixiv OR g_technology=c_tech_arria10_proto OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg, 0, 1);
+ CONSTANT c_ip_rx_ready_latency : NATURAL := sel_a_b(g_technology=c_tech_stratixiv OR g_technology=c_tech_arria10_proto OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg, 0, 1);
SIGNAL tx_mac_snk_in_data : STD_LOGIC_VECTOR(c_tech_mac_10g_data_w-1 DOWNTO 0); -- 64 bit
SIGNAL tx_mac_snk_in : t_dp_sosi;
@@ -153,7 +153,7 @@ BEGIN
xgmii_link_status, xgmii_tx_data, xgmii_rx_data);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ENTITY work.tech_mac_10g_arria10
PORT MAP (mm_clk, mm_rst, csr_mosi, csr_miso,
tx_clk_312, tx_clk_156, tx_rst, tx_mac_snk_in, tx_mac_snk_out,
diff --git a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
index fe4e87ff6f..2455289038 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
@@ -300,13 +300,13 @@ PACKAGE BODY tech_mac_10g_component_pkg IS
BEGIN
CASE c_technology IS
WHEN c_tech_stratixiv => v_csr_addr_w := 13;
- WHEN c_tech_arria10 => v_csr_addr_w := 13; -- 13 with INSERT_CSR_ADAPTOR=1 in ip_arria10_mac_10g.qsys, 10 without
- WHEN c_tech_arria10_e3sge3 => v_csr_addr_w := 13; -- 13 with INSERT_CSR_ADAPTOR=1 in ip_arria10_e3sge3_mac_10g.qsys, 10 without
+ WHEN c_tech_arria10_proto => v_csr_addr_w := 13; -- 13 with INSERT_CSR_ADAPTOR=1 in ip_arria10_mac_10g.qsys, 10 without
+ WHEN c_tech_arria10_e3sge3 => v_csr_addr_w := 13; -- 13 with INSERT_CSR_ADAPTOR=1 in ip_arria10_e3sge3_mac_10g.qsys, 10 without
WHEN c_tech_arria10_e1sg => v_csr_addr_w := 13; -- 13 with INSERT_CSR_ADAPTOR=1 in ip_arria10_e1sg_mac_10g.qsys, 10 without
WHEN c_tech_arria10_e2sg => v_csr_addr_w := 13; -- 13 with INSERT_CSR_ADAPTOR=1 in ip_arria10_e1sg_mac_10g.qsys, 10 without
WHEN OTHERS => v_csr_addr_w := 13; -- default to c_tech_stratixiv
END CASE;
- RETURN v_csr_addr_w;
+ RETURN v_csr_addr_w;
END func_tech_mac_10g_csr_addr_w;
END tech_mac_10g_component_pkg;
diff --git a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
index 342a964b87..9e0131c566 100644
--- a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
@@ -64,7 +64,7 @@ BEGIN
PORT MAP (data, rdaddress, rdclock, rdclocken, wraddress, wrclock, wrclocken, wren, q);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_ram_cr_cw
GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
PORT MAP (data, rdaddress, rdclock, wraddress, wrclock, wren, q);
diff --git a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
index 6e43a2d128..7421d579f9 100644
--- a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
@@ -71,7 +71,7 @@ BEGIN
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, enable_a, enable_b, rden_a, rden_b, wren_a, wren_b, q_a, q_b);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_ram_crw_crw
GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
diff --git a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
index 802e6d8e85..9b88238eea 100644
--- a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
@@ -73,7 +73,7 @@ BEGIN
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, enable_a, enable_b, rden_a, rden_b, wren_a, wren_b, q_a, q_b);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_ram_crwk_crw
GENERIC MAP (g_adr_a_w, g_dat_a_w, g_adr_b_w, g_dat_b_w, g_nof_words_a, g_nof_words_b, g_rd_latency, g_init_file)
PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
diff --git a/libraries/technology/memory/tech_memory_ram_r_w.vhd b/libraries/technology/memory/tech_memory_ram_r_w.vhd
index 54203fc494..b367295b15 100644
--- a/libraries/technology/memory/tech_memory_ram_r_w.vhd
+++ b/libraries/technology/memory/tech_memory_ram_r_w.vhd
@@ -61,7 +61,7 @@ BEGIN
PORT MAP (clock, enable, data, rdaddress, wraddress, wren, q);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_ram_r_w
GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
PORT MAP (clock, data, rdaddress, wraddress, wren, q);
diff --git a/libraries/technology/memory/tech_memory_rom_r.vhd b/libraries/technology/memory/tech_memory_rom_r.vhd
index 2fadf62988..76ac8a9c70 100644
--- a/libraries/technology/memory/tech_memory_rom_r.vhd
+++ b/libraries/technology/memory/tech_memory_rom_r.vhd
@@ -57,7 +57,7 @@ BEGIN
PORT MAP (address, clock, clken, q);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
-- use ip_arria10_ram_r_w as ROM
u0 : ip_arria10_ram_r_w
GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, 1, g_init_file)
diff --git a/libraries/technology/mult/tech_complex_mult.vhd b/libraries/technology/mult/tech_complex_mult.vhd
index 81cf3f0459..1c36a57e13 100644
--- a/libraries/technology/mult/tech_complex_mult.vhd
+++ b/libraries/technology/mult/tech_complex_mult.vhd
@@ -140,7 +140,7 @@ BEGIN
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
END GENERATE;
- gen_ip_arria10_ip : IF g_variant="IP" AND g_technology=c_tech_arria10 AND c_dsp_dat_w <= c_dsp_mult_18_w GENERATE
+ gen_ip_arria10_ip : IF g_variant="IP" AND g_technology=c_tech_arria10_proto AND c_dsp_dat_w <= c_dsp_mult_18_w GENERATE
-- Adapt DSP input widths
ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w);
ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w);
@@ -299,7 +299,7 @@ BEGIN
END GENERATE;
-- RTL variant is the same for unb2, unb2a and unb2b
- gen_ip_arria10_rtl : IF g_variant="RTL" AND (g_technology=c_tech_arria10 OR
+ gen_ip_arria10_rtl : IF g_variant="RTL" AND (g_technology=c_tech_arria10_proto OR
g_technology=c_tech_arria10_e3sge3 OR
g_technology=c_tech_arria10_e1sg OR
g_technology=c_tech_arria10_e2sg) GENERATE
@@ -328,7 +328,7 @@ BEGIN
END GENERATE;
-- RTL variant is the same for unb2, unb2a and unb2b
- gen_ip_arria10_rtl_canonical : IF g_variant="RTL_C" AND (g_technology=c_tech_arria10 OR
+ gen_ip_arria10_rtl_canonical : IF g_variant="RTL_C" AND (g_technology=c_tech_arria10_proto OR
g_technology=c_tech_arria10_e3sge3 OR
g_technology=c_tech_arria10_e1sg OR
g_technology=c_tech_arria10_e2sg) GENERATE
diff --git a/libraries/technology/mult/tech_mult.vhd b/libraries/technology/mult/tech_mult.vhd
index 5144eab123..cb65990aab 100644
--- a/libraries/technology/mult/tech_mult.vhd
+++ b/libraries/technology/mult/tech_mult.vhd
@@ -107,7 +107,7 @@ begin
);
END GENERATE;
- gen_ip_arria10_ip : IF ((g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg ) AND g_variant="IP") GENERATE
+ gen_ip_arria10_ip : IF ((g_technology=c_tech_arria10_proto OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg ) AND g_variant="IP") GENERATE
u0 : ip_arria10_mult
GENERIC MAP(
g_in_a_w => g_in_a_w,
@@ -128,7 +128,7 @@ begin
);
END GENERATE;
- gen_ip_arria10_rtl : IF ((g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg ) AND g_variant="RTL") GENERATE
+ gen_ip_arria10_rtl : IF ((g_technology=c_tech_arria10_proto OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg ) AND g_variant="RTL") GENERATE
u0 : ip_arria10_mult_rtl
GENERIC MAP(
g_in_a_w => g_in_a_w,
diff --git a/libraries/technology/pll/tech_pll_clk125.vhd b/libraries/technology/pll/tech_pll_clk125.vhd
index afe5ff658d..be4cf0ece3 100644
--- a/libraries/technology/pll/tech_pll_clk125.vhd
+++ b/libraries/technology/pll/tech_pll_clk125.vhd
@@ -50,7 +50,7 @@ ARCHITECTURE str OF tech_pll_clk125 IS
BEGIN
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_pll_clk125
PORT MAP (
rst => areset,
diff --git a/libraries/technology/pll/tech_pll_clk200.vhd b/libraries/technology/pll/tech_pll_clk200.vhd
index ccff2fa603..f25c4f5052 100644
--- a/libraries/technology/pll/tech_pll_clk200.vhd
+++ b/libraries/technology/pll/tech_pll_clk200.vhd
@@ -59,7 +59,7 @@ BEGIN
PORT MAP (areset, inclk0, c0, c1, c2, locked);
END GENERATE;
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_pll_clk200
PORT MAP (
rst => areset,
diff --git a/libraries/technology/pll/tech_pll_clk25.vhd b/libraries/technology/pll/tech_pll_clk25.vhd
index 1e2251793d..d2f4a37419 100644
--- a/libraries/technology/pll/tech_pll_clk25.vhd
+++ b/libraries/technology/pll/tech_pll_clk25.vhd
@@ -52,7 +52,7 @@ ARCHITECTURE str OF tech_pll_clk25 IS
BEGIN
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_pll_clk25
PORT MAP (
rst => areset,
diff --git a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
index 9cee65f0b2..1f0bf6459d 100644
--- a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
+++ b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
@@ -70,7 +70,7 @@ ARCHITECTURE str OF tech_pll_xgmii_mac_clocks IS
BEGIN
- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF g_technology=c_tech_arria10_proto GENERATE
u0 : ip_arria10_pll_xgmii_mac_clocks
PORT MAP (
pll_refclk0 => refclk_644,
diff --git a/libraries/technology/technology_pkg.vhd b/libraries/technology/technology_pkg.vhd
index c91c630e2b..f913ccfbf0 100644
--- a/libraries/technology/technology_pkg.vhd
+++ b/libraries/technology/technology_pkg.vhd
@@ -45,7 +45,7 @@ PACKAGE technology_pkg IS
CONSTANT c_tech_stratixiv : INTEGER := 2; -- e.g. used on UniBoard1
CONSTANT c_tech_virtex6 : INTEGER := 3; -- e.g. used on Roach2 for Casper
CONSTANT c_tech_virtex7 : INTEGER := 4; -- e.g. used on Roach3 for Casper
- CONSTANT c_tech_arria10 : INTEGER := 5; -- e.g. used on UniBoard2 first proto (1 board version "00" may 2015)
+ CONSTANT c_tech_arria10_proto : INTEGER := 5; -- e.g. used on UniBoard2 first proto (1 board version "00" may 2015)
CONSTANT c_tech_arria10_e3sge3 : INTEGER := 6; -- e.g. used on UniBoard2 second run (7 boards version "01" dec 2015)
CONSTANT c_tech_arria10_e1sg : INTEGER := 7; -- e.g. used on UniBoard2b third run (5 ARTS boards version "01" feb 2017)
CONSTANT c_tech_arria10_e2sg : INTEGER := 8; -- e.g. used on UniBoard2c (2 LOFAR2.0 SDP boards version "11" f 2021)
diff --git a/libraries/technology/tse/tb_tech_tse_pkg.vhd b/libraries/technology/tse/tb_tech_tse_pkg.vhd
index 801e108246..43c6110b8d 100644
--- a/libraries/technology/tse/tb_tech_tse_pkg.vhd
+++ b/libraries/technology/tse/tb_tech_tse_pkg.vhd
@@ -143,11 +143,11 @@ PACKAGE BODY tb_tech_tse_pkg IS
BEGIN
CASE c_technology IS
WHEN c_tech_stratixiv => proc_tech_tse_setup_stratixiv(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi);
- WHEN c_tech_arria10 => proc_tech_tse_setup_arria10(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi);
+ WHEN c_tech_arria10_proto => proc_tech_tse_setup_arria10(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi);
WHEN c_tech_arria10_e3sge3 => proc_tech_tse_setup_arria10(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi);
WHEN c_tech_arria10_e1sg => proc_tech_tse_setup_arria10(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi);
WHEN c_tech_arria10_e2sg => proc_tech_tse_setup_arria10(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi);
- WHEN OTHERS => proc_tech_tse_setup_stratixiv(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi); -- default to c_tech_stratixiv
+ WHEN OTHERS => proc_tech_tse_setup_stratixiv(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi); -- default to c_tech_stratixiv
END CASE;
END proc_tech_tse_setup;
diff --git a/libraries/technology/tse/tech_tse.vhd b/libraries/technology/tse/tech_tse.vhd
index 86aa31094c..09cae2c3bc 100644
--- a/libraries/technology/tse/tech_tse.vhd
+++ b/libraries/technology/tse/tech_tse.vhd
@@ -138,7 +138,7 @@ BEGIN
tse_led);
END GENERATE;
- gen_ip_arria10 : IF c_use_technology=TRUE AND g_technology=c_tech_arria10 GENERATE
+ gen_ip_arria10 : IF c_use_technology=TRUE AND g_technology=c_tech_arria10_proto GENERATE
u0 : ENTITY work.tech_tse_arria10
GENERIC MAP (g_ETH_PHY)
PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk,
--
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