diff --git a/libraries/technology/mac_10g/tb_tb_tech_mac_10g.vhd b/libraries/technology/mac_10g/tb_tb_tech_mac_10g.vhd
index cc1c453bc81f1b3582bfb58f3d766b84a2635711..4221e288f5abe7afcec2bff5d13f3abd5dc31f8b 100644
--- a/libraries/technology/mac_10g/tb_tb_tech_mac_10g.vhd
+++ b/libraries/technology/mac_10g/tb_tb_tech_mac_10g.vhd
@@ -39,6 +39,7 @@ END tb_tb_tech_mac_10g;
 ARCHITECTURE tb OF tb_tb_tech_mac_10g IS
   CONSTANT c_tb_end_vec : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS=>'1');
   SIGNAL   tb_end_vec   : STD_LOGIC_VECTOR(7 DOWNTO 0) := c_tb_end_vec;  -- sufficiently long to fit all tb instances
+  SIGNAL   tb_end       : STD_LOGIC := '0';
 BEGIN
 
 --    g_technology : NATURAL := c_tech_select_default;
@@ -53,9 +54,12 @@ BEGIN
   u_tech_mac_10g_counter : ENTITY work.tb_tech_mac_10g GENERIC MAP (c_tech_select_default, FALSE, FALSE, c_tb_tech_mac_10g_data_type_counter) PORT MAP (tb_end_vec(2));
   u_tech_mac_10g_symbols : ENTITY work.tb_tech_mac_10g GENERIC MAP (c_tech_select_default, FALSE, FALSE, c_tb_tech_mac_10g_data_type_symbols) PORT MAP (tb_end_vec(3));
   
+  tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec ELSE '0';
+  
   p_tb_end : PROCESS
   BEGIN
-    WAIT UNTIL tb_end_vec=c_tb_end_vec;
+    WAIT UNTIL tb_end='1';
+    WAIT FOR 1 ns;
     REPORT "Multi tb simulation finished." SEVERITY FAILURE;
     WAIT;
   END PROCESS;