From f24c3861fddea77961ddf7cbff2cbbd0331441eb Mon Sep 17 00:00:00 2001
From: JobvanWee <wee@astron.nl>
Date: Fri, 4 Mar 2022 11:08:15 +0100
Subject: [PATCH] Ready for review.
---
.../ddrctrl/src/vhdl/ddrctrl_pack.vhd | 9 ++-
.../ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd | 56 ++++++++++---------
2 files changed, 34 insertions(+), 31 deletions(-)
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_pack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_pack.vhd
index 1a547881d6..1fde708fef 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_pack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_pack.vhd
@@ -34,15 +34,14 @@ USE dp_lib.dp_stream_pkg.ALL;
ENTITY ddrctrl_pack IS
GENERIC (
- g_nof_streams : POSITIVE := 12; -- number of input streams
- g_data_w : NATURAL := 14 -- data with of input data vectors
+ g_nof_streams : POSITIVE := 12; -- number of input streams
+ g_data_w : NATURAL := 14 -- data with of input data vectors
);
PORT (
- clk : IN STD_LOGIC; -- clock signal
- in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- input signal
- out_data : OUT STD_LOGIC_VECTOR((g_nof_streams*g_data_w)-1 DOWNTO 0) -- output signal
+ in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- input data
+ out_data : OUT STD_LOGIC_VECTOR((g_nof_streams*g_data_w)-1 DOWNTO 0) -- output data
);
END ddrctrl_pack;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd
index 5478ec55c5..6f81b6cb22 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_pack.vhd
@@ -35,20 +35,23 @@ USE common_lib.common_pkg.ALL;
ENTITY tb_ddrctrl_pack IS
GENERIC (
- g_nof_streams : POSITIVE := 12; -- number of input streams
- g_data_w : NATURAL := 14 -- data with of input data vectors
+ g_nof_streams : POSITIVE := 12; -- number of input streams
+ g_data_w : NATURAL := 14; -- data with of input data vectors
+ g_sim_length : NATURAL := 52 -- determens the lengt of the duration of the test
- );
+ );
END tb_ddrctrl_pack;
ARCHITECTURE tb OF tb_ddrctrl_pack IS
- CONSTANT c_clk_freq : NATURAL := 200; -- MHz
- CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps; -- clock priod, 5 ns
-
+ -- constants for running the testbench
+ CONSTANT c_clk_freq : NATURAL := 200; -- clock frequency in MHz
+ CONSTANT c_clk_period : TIME := (10**6/c_clk_freq)*1 ps; -- clock priod, 5 ns
- CONSTANT c_out_data_w : NATURAL := g_nof_streams * g_data_w; -- output data with, 168
+ -- constant for readability
+ CONSTANT c_out_data_w : NATURAL := g_nof_streams*g_data_w; -- output data with, 168
+ -- function for making test vector
FUNCTION c_testv_init RETURN STD_LOGIC_VECTOR IS
VARIABLE temp : STD_LOGIC_VECTOR(c_out_data_w-1 DOWNTO 0);
BEGIN
@@ -57,39 +60,44 @@ ARCHITECTURE tb OF tb_ddrctrl_pack IS
END LOOP;
RETURN temp;
END FUNCTION c_testv_init;
- CONSTANT c_testv : STD_LOGIC_VECTOR(c_out_data_w-1 DOWNTO 0) := c_testv_init; -- testvector which contains a number for each stream, so the data of stream 6 will look like ...00110
-
-
- SIGNAL tb_end : STD_LOGIC := '0'; -- signal to turn the testbench off
+ -- constants for running the test
+ CONSTANT c_testv : STD_LOGIC_VECTOR(c_out_data_w-1 DOWNTO 0) := c_testv_init; -- testvector which contains a number for each stream, so the data of stream 6 will look like ...00110
+ -- input signals for ddrctrl_pack.vhd
SIGNAL clk : STD_LOGIC := '1'; -- clock signal
SIGNAL in_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_init); -- input signal for ddrctrl_pack.vhd
+ -- output singal from ddrctrl_pack.vhd
SIGNAL out_data : STD_LOGIC_VECTOR(c_out_data_w-1 DOWNTO 0); -- output signal from ddrctrl_pack.vhd
+ -- testbench signal
+ SIGNAL tb_end : STD_LOGIC := '0'; -- signal to turn the testbench off
+
BEGIN
- clk <= NOT clk OR tb_end AFTER c_clk_period/2; -- generating clock signal
+ -- generating clock
+ clk <= NOT clk OR tb_end AFTER c_clk_period/2;
- p_mm : PROCESS
+ -- excecuting the test
+ p_test : PROCESS
BEGIN
- -- Start the testbench.
+ -- starting the test
tb_end <= '0';
- WAIT UNTIL rising_edge(clk); -- align to rising edge
+ WAIT UNTIL rising_edge(clk);
WAIT FOR c_clk_period*2;
- -- The input data vectors get filled with the corresponding number.
+ -- the input data vectors get filled with the corresponding number
fill_in_sosi_arr : FOR I IN 0 TO g_nof_streams-1 LOOP
in_sosi_arr(I).data(g_data_w - 1 DOWNTO 0) <= c_testv(g_data_w * (I + 1) - 1 DOWNTO g_data_w * I);
END LOOP;
- -- The numbers get cycled trough the input vectors.
- change_in_sosi_arr : FOR J IN 0 TO 4 LOOP
+ -- the numbers get cycled trough the input vectors
+ change_in_sosi_arr : FOR J IN 0 TO g_sim_length-1 LOOP
WAIT FOR c_clk_period*1;
in_sosi_arr(0).data(g_data_w - 1 DOWNTO 0) <= in_sosi_arr(g_nof_streams-1).data(g_data_w - 1 DOWNTO 0);
loop_switch_data : FOR I IN 1 TO g_nof_streams-1 LOOP
@@ -97,15 +105,13 @@ BEGIN
END LOOP;
END LOOP;
- -- Stop the testbench.
+ -- stopping the testbench
WAIT FOR c_clk_period*4;
tb_end <= '1';
-
-
- WAIT;
+ ASSERT FALSE REPORT "Test: OK" SEVERITY FAILURE;
END PROCESS;
- -- Verification by checking if the input vectors equel the corresponding index of the output vector.
+ -- verification by checking if the input vectors equel the corresponding index of the output vector
p_verify : PROCESS
BEGIN
WAIT UNTIL rising_edge(clk);
@@ -116,15 +122,13 @@ BEGIN
END IF;
END PROCESS;
-
-
+ -- DUT
u_ddrctrl_pack : ENTITY work.ddrctrl_pack
GENERIC MAP (
g_nof_streams => g_nof_streams,
g_data_w => g_data_w
)
PORT MAP (
- clk => clk,
in_sosi_arr => in_sosi_arr,
out_data => out_data
--
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