From f2438b044e55d7a037cd4fd0d21f5bde5197f7e6 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Fri, 10 Apr 2015 14:44:54 +0000
Subject: [PATCH] updated pinning constraints

---
 .../quartus/unb1_test_pins_constraints.tcl    | 960 +++++++++---------
 .../unb1_test_10GbE/unb1_test_10GbE.vhd       |  11 +-
 2 files changed, 483 insertions(+), 488 deletions(-)

diff --git a/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins_constraints.tcl b/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins_constraints.tcl
index a6cd681361..97d70ca65f 100644
--- a/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins_constraints.tcl
+++ b/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins_constraints.tcl
@@ -1,483 +1,483 @@
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO[0].dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO[0].dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO[0].dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU[0].ck[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU[0].ck[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU[0].ck[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU[0].ck[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU[0].ck_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU[0].ck_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU[0].ck_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU[0].ck_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].a[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].a[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].ba[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].ba[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].ba[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].ba[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].ba[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].ba[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].cs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].cs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].cs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].cs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].we_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].we_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].ras_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].ras_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].cas_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].cas_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].cke[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].cke[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].cke[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].cke[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].odt[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].odt[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].odt[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].odt[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD 1.5V -to MB_I_OU[0].reset_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU[0].reset_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU[0].dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU[0].dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_IO[0].dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_IO[0].dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_IO[0].dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_IO[0].dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_IO[0].dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_IO[0].dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_IO[0].dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_IO[0].dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[0] -to MB_I_OU[0].dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[1] -to MB_I_OU[0].dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[2] -to MB_I_OU[0].dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[3] -to MB_I_OU[0].dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[4] -to MB_I_OU[0].dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[5] -to MB_I_OU[0].dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[6] -to MB_I_OU[0].dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO[0].dqs[7] -to MB_I_OU[0].dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU[0].dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
-set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO[0].dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU.ck[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU.ck[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU.ck[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU.ck[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU.ck_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU.ck_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to MB_I_OU.ck_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to MB_I_OU.ck_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.a[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.a[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.ba[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.ba[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.ba[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.ba[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.ba[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.ba[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.we_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.we_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.ras_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.ras_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cas_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cas_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cke[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cke[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.cke[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.cke[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.odt[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.odt[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.odt[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.odt[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD 1.5V -to MB_I_OU.reset_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to MB_I_OU.reset_n -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to MB_I_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MB_I_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[0] -to MB_I_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[1] -to MB_I_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[2] -to MB_I_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[3] -to MB_I_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[4] -to MB_I_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[5] -to MB_I_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[6] -to MB_I_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name DQ_GROUP 9 -from MB_I_IO.dqs[7] -to MB_I_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[8] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[9] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[10] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[11] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[12] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[13] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[14] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[15] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[16] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[17] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[18] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[19] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[20] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[21] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[22] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[23] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[24] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[25] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[26] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[27] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[28] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[29] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[30] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[31] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[32] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[33] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[34] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[35] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[36] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[37] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[38] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[39] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[40] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[41] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[42] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[43] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[44] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[45] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[46] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[47] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[48] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[49] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[50] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[51] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[52] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[53] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[54] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[55] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[56] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[57] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[58] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[59] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[60] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[61] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[62] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dq[63] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_OU.dm[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[0] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[1] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[2] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[3] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[4] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[5] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[6] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
+set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to MB_I_IO.dqs_n[7] -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
 set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[1]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
 set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[2]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
 set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to "u_revision|\\gen_MB_I:u_mms_ddr3_i|u_tech_ddr|\\gen_ip_stratixiv:u0|\\gen_ip_stratixiv_ddr3_uphy_4g_800_master:u_ip_stratixiv_ddr3_uphy_4g_800_master|ip_stratixiv_ddr3_uphy_4g_800_master_inst|pll0|upll_memphy|auto_generated|clk[3]" -tag __ip_stratixiv_ddr3_uphy_4g_800_master_p0
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
index 910e0fea52..8b130ff568 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
@@ -92,14 +92,9 @@ ENTITY unb1_test_10GbE IS
     BN_BI_3_RX    : IN    STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
 
     -- SO-DIMM Memory Bank I
-    MB_I_IN       : IN    t_tech_ddr_phy_in_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0);
-    MB_I_IO       : INOUT t_tech_ddr_phy_io_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0);
-    MB_I_OU       : OUT   t_tech_ddr_phy_ou_arr(sel_a_b(g_sim, 1, g_use_MB_I) -1 DOWNTO 0)
-
-    -- SO-DIMM Memory Bank II                                                                    
-    --MB_II_IN      : IN    t_tech_ddr_phy_in_arr(sel_a_b(g_sim, 1, g_use_MB_II) -1 DOWNTO 0);
-    --MB_II_IO      : INOUT t_tech_ddr_phy_io_arr(sel_a_b(g_sim, 1, g_use_MB_II) -1 DOWNTO 0);
-    --MB_II_OU      : OUT   t_tech_ddr_phy_ou_arr(sel_a_b(g_sim, 1, g_use_MB_II) -1 DOWNTO 0)
+    MB_I_IN       : IN    t_tech_ddr3_phy_in;
+    MB_I_IO       : INOUT t_tech_ddr3_phy_io;
+    MB_I_OU       : OUT   t_tech_ddr3_phy_ou
   );
 END unb1_test_10GbE;
 
-- 
GitLab