diff --git a/applications/aartfaac/designs/aartfaac_fn_sdo/src/quartus/sopc_aartfaac_fn_sdo.sopc b/applications/aartfaac/designs/aartfaac_fn_sdo/src/quartus/sopc_aartfaac_fn_sdo.sopc
index 3cddc24548e323463d16322f69ceb8aa89338a36..3333ea375a935fc005cfdcb162a4825bc54190b4 100644
--- a/applications/aartfaac/designs/aartfaac_fn_sdo/src/quartus/sopc_aartfaac_fn_sdo.sopc
+++ b/applications/aartfaac/designs/aartfaac_fn_sdo/src/quartus/sopc_aartfaac_fn_sdo.sopc
@@ -22,7 +22,7 @@
{
datum _sortIndex
{
- value = "18";
+ value = "17";
type = "int";
}
}
@@ -100,48 +100,48 @@
type = "String";
}
}
- element pio_system_info.mem
+ element reg_unb_sens.mem
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "0";
+ value = "544";
type = "long";
}
}
- element reg_unb_sens.mem
+ element reg_mdio_1.mem
{
datum baseAddress
{
- value = "544";
+ value = "640";
type = "long";
}
}
- element reg_tr_xaui.mem
+ element reg_tr_nonbonded.mem
{
datum baseAddress
{
- value = "16384";
+ value = "128";
type = "long";
}
}
- element reg_diagnostics.mem
+ element pio_system_info.mem
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "256";
+ value = "0";
type = "long";
}
}
- element reg_tr_nonbonded.mem
+ element reg_tr_10GbE.mem
{
datum baseAddress
{
- value = "128";
+ value = "32768";
type = "long";
}
}
@@ -158,35 +158,35 @@
type = "long";
}
}
- element reg_diag_data_buffer.mem
+ element reg_mdio_0.mem
{
datum baseAddress
{
- value = "576";
+ value = "608";
type = "long";
}
}
- element ram_diag_data_buffer.mem
+ element reg_diagnostics.mem
{
datum baseAddress
{
- value = "262144";
+ value = "256";
type = "long";
}
}
- element reg_mdio_0.mem
+ element ram_diag_data_buffer.mem
{
datum baseAddress
{
- value = "608";
+ value = "262144";
type = "long";
}
}
- element reg_tr_10GbE.mem
+ element reg_tr_xaui.mem
{
datum baseAddress
{
- value = "32768";
+ value = "16384";
type = "long";
}
}
@@ -198,14 +198,6 @@
type = "long";
}
}
- element reg_mdio_1.mem
- {
- datum baseAddress
- {
- value = "640";
- type = "long";
- }
- }
element reg_wdi.mem
{
datum _lockedAddress
@@ -219,6 +211,14 @@
type = "long";
}
}
+ element reg_diag_data_buffer.mem
+ {
+ datum baseAddress
+ {
+ value = "576";
+ type = "long";
+ }
+ }
element avs_eth_0.mms_ram
{
datum baseAddress
@@ -264,14 +264,6 @@
type = "int";
}
}
- element pio_pps
- {
- datum _sortIndex
- {
- value = "14";
- type = "int";
- }
- }
element pio_system_info
{
datum _sortIndex
@@ -310,7 +302,7 @@
{
datum _sortIndex
{
- value = "16";
+ value = "15";
type = "int";
}
}
@@ -318,7 +310,7 @@
{
datum _sortIndex
{
- value = "15";
+ value = "14";
type = "int";
}
}
@@ -334,7 +326,7 @@
{
datum _sortIndex
{
- value = "20";
+ value = "19";
type = "int";
}
}
@@ -342,7 +334,7 @@
{
datum _sortIndex
{
- value = "21";
+ value = "20";
type = "int";
}
}
@@ -350,7 +342,7 @@
{
datum _sortIndex
{
- value = "22";
+ value = "21";
type = "int";
}
}
@@ -358,7 +350,7 @@
{
datum _sortIndex
{
- value = "17";
+ value = "16";
type = "int";
}
}
@@ -374,7 +366,7 @@
{
datum _sortIndex
{
- value = "19";
+ value = "18";
type = "int";
}
}
@@ -402,14 +394,6 @@
type = "int";
}
}
- element pio_wdi.s1
- {
- datum baseAddress
- {
- value = "736";
- type = "long";
- }
- }
element pio_debug_wave.s1
{
datum baseAddress
@@ -418,32 +402,32 @@
type = "long";
}
}
- element onchip_memory2_0.s1
+ element timer_0.s1
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "131072";
+ value = "512";
type = "long";
}
}
- element timer_0.s1
+ element pio_wdi.s1
{
datum baseAddress
{
- value = "512";
+ value = "736";
type = "long";
}
}
- element pio_pps.s1
+ element onchip_memory2_0.s1
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "752";
+ value = "131072";
type = "long";
}
}
@@ -470,10 +454,10 @@
<parameter name="globalResetBus" value="true" />
<parameter name="hdlLanguage" value="VHDL" />
<parameter name="maxAdditionalLatency" value="0" />
- <parameter name="projectName" value="" />
+ <parameter name="projectName" value="aartfaac_fn_sdo.qpf" />
<parameter name="sopcBorderPoints" value="true" />
- <parameter name="systemHash" value="-60671328635" />
- <parameter name="timeStamp" value="1441368791753" />
+ <parameter name="systemHash" value="-63089045873" />
+ <parameter name="timeStamp" value="1441369895633" />
<parameter name="useTestBenchNamingPattern" value="false" />
<module kind="clock_source" version="11.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="25000000" />
@@ -574,7 +558,7 @@
<parameter name="dcache_numTCDM" value="_0" />
<parameter name="dcache_lineSize" value="_32" />
<parameter name="dcache_bursts" value="false" />
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_tr_nonbonded.mem' start='0x80' end='0xC0' /><slave name='avs_eth_0.mms_reg' start='0xC0' end='0x100' /><slave name='reg_diagnostics.mem' start='0x100' end='0x200' /><slave name='timer_0.s1' start='0x200' end='0x220' /><slave name='reg_unb_sens.mem' start='0x220' end='0x240' /><slave name='reg_diag_data_buffer.mem' start='0x240' end='0x260' /><slave name='reg_mdio_0.mem' start='0x260' end='0x280' /><slave name='reg_mdio_1.mem' start='0x280' end='0x2A0' /><slave name='reg_mdio_2.mem' start='0x2A0' end='0x2C0' /><slave name='altpll_0.pll_slave' start='0x2C0' end='0x2D0' /><slave name='pio_debug_wave.s1' start='0x2D0' end='0x2E0' /><slave name='pio_wdi.s1' start='0x2E0' end='0x2F0' /><slave name='pio_pps.s1' start='0x2F0' end='0x300' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x300' end='0x308' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='reg_tr_10GbE.mem' start='0x8000' end='0x10000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_diag_data_buffer.mem' start='0x40000' end='0x60000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_tr_nonbonded.mem' start='0x80' end='0xC0' /><slave name='avs_eth_0.mms_reg' start='0xC0' end='0x100' /><slave name='reg_diagnostics.mem' start='0x100' end='0x200' /><slave name='timer_0.s1' start='0x200' end='0x220' /><slave name='reg_unb_sens.mem' start='0x220' end='0x240' /><slave name='reg_diag_data_buffer.mem' start='0x240' end='0x260' /><slave name='reg_mdio_0.mem' start='0x260' end='0x280' /><slave name='reg_mdio_1.mem' start='0x280' end='0x2A0' /><slave name='reg_mdio_2.mem' start='0x2A0' end='0x2C0' /><slave name='altpll_0.pll_slave' start='0x2C0' end='0x2D0' /><slave name='pio_debug_wave.s1' start='0x2D0' end='0x2E0' /><slave name='pio_wdi.s1' start='0x2E0' end='0x2F0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x300' end='0x308' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='reg_tr_10GbE.mem' start='0x8000' end='0x10000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_diag_data_buffer.mem' start='0x40000' end='0x60000' /></address-map>]]></parameter>
<parameter name="dataAddrWidth" value="19" />
<parameter name="customInstSlavesSystemInfo" value="<info/>" />
<parameter name="cpuReset" value="false" />
@@ -871,20 +855,6 @@ q]]></parameter>
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
- <module kind="altera_avalon_pio" version="11.1" enabled="1" name="pio_pps">
- <parameter name="bitClearingEdgeCapReg" value="false" />
- <parameter name="bitModifyingOutReg" value="false" />
- <parameter name="captureEdge" value="false" />
- <parameter name="clockRate" value="125000000" />
- <parameter name="direction" value="Input" />
- <parameter name="edgeType" value="RISING" />
- <parameter name="generateIRQ" value="false" />
- <parameter name="irqType" value="LEVEL" />
- <parameter name="resetValue" value="0" />
- <parameter name="simDoTestBenchWiring" value="false" />
- <parameter name="simDrivenValue" value="0" />
- <parameter name="width" value="32" />
- </module>
<module
kind="avs_common_mm"
version="1.0"
@@ -1114,15 +1084,6 @@ q]]></parameter>
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3000" />
</connection>
- <connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_pps.clk" />
- <connection
- kind="avalon"
- version="11.1"
- start="cpu_0.data_master"
- end="pio_pps.s1">
- <parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x02f0" />
- </connection>
<connection
kind="clock"
version="11.1"
diff --git a/applications/aartfaac/designs/aartfaac_fn_sdo/src/vhdl/aartfaac_fn_sdo.vhd b/applications/aartfaac/designs/aartfaac_fn_sdo/src/vhdl/aartfaac_fn_sdo.vhd
index 1538c1d32f485050b164dbf68535a07ac6bbce2d..8aedcf2d90bfdd32baa5d1760dbe91cda45fe777 100644
--- a/applications/aartfaac/designs/aartfaac_fn_sdo/src/vhdl/aartfaac_fn_sdo.vhd
+++ b/applications/aartfaac/designs/aartfaac_fn_sdo/src/vhdl/aartfaac_fn_sdo.vhd
@@ -154,6 +154,7 @@ ARCHITECTURE str OF aartfaac_fn_sdo IS
-- Transceiver clocks
SIGNAL tr_clk : STD_LOGIC;
SIGNAL cal_rec_clk : STD_LOGIC;
+ SIGNAL sa_rst : STD_LOGIC;
-- MM buses
SIGNAL reg_diagnostics_mosi : t_mem_mosi;
@@ -343,6 +344,17 @@ BEGIN
tr_10GbE_snk_in_arr(0) <= dp_mux_src_out;
dp_mux_src_in <= tr_10GbE_snk_out_arr(0);
+ u_areset_sa_rst : ENTITY common_lib.common_areset
+ GENERIC MAP(
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ PORT MAP(
+ clk => SA_CLK,
+ in_rst => '0',
+ out_rst => sa_rst
+ );
+
u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
GENERIC MAP(
g_sim => g_sim,
@@ -394,7 +406,7 @@ BEGIN
xaui_rx_arr(i) <= unb_xaui_rx_arr(i);
END GENERATE;
- u_front_io : ENTITY unb1_board_lib.unb_front_io
+ u_front_io : ENTITY unb1_board_lib.unb1_board_front_io
GENERIC MAP (
g_nof_xaui => c_nof_10GbE_offload_streams
)
@@ -453,7 +465,6 @@ BEGIN
-- PIOs
pout_wdi => pout_wdi,
- pin_pps => pin_pps,
-- eth1g
eth1g_tse_clk => eth1g_tse_clk,
@@ -522,7 +533,6 @@ BEGIN
mm_locked => mm_locked,
pout_wdi => pout_wdi,
- pin_pps => pin_pps,
reg_wdi_mosi => reg_wdi_mosi,
reg_wdi_miso => reg_wdi_miso,
diff --git a/applications/aartfaac/designs/aartfaac_fn_sdo/src/vhdl/mmm_aartfaac_fn_sdo.vhd b/applications/aartfaac/designs/aartfaac_fn_sdo/src/vhdl/mmm_aartfaac_fn_sdo.vhd
index 20a2797a64dbe1eb9ba07b11a935abd60ddf1637..18948079476ad7f1f74b56ec0c1ab008bd8dcefe 100644
--- a/applications/aartfaac/designs/aartfaac_fn_sdo/src/vhdl/mmm_aartfaac_fn_sdo.vhd
+++ b/applications/aartfaac/designs/aartfaac_fn_sdo/src/vhdl/mmm_aartfaac_fn_sdo.vhd
@@ -59,8 +59,6 @@ ENTITY mmm_aartfaac_fn_sdo IS
pout_wdi : OUT STD_LOGIC;
- pin_pps : IN STD_LOGIC_VECTOR;
-
reg_wdi_mosi : OUT t_mem_mosi;
reg_wdi_miso : IN t_mem_miso;
@@ -90,6 +88,10 @@ ENTITY mmm_aartfaac_fn_sdo IS
ram_diag_data_buf_miso : IN t_mem_miso := c_mem_miso_rst;
reg_diag_data_buf_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_diag_data_buf_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_mdio_mosi_arr : OUT t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
+ reg_mdio_miso_arr : IN t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
+ reg_tr_xaui_mosi : OUT t_mem_mosi;
+ reg_tr_xaui_miso : IN t_mem_miso := c_mem_miso_rst;
reg_tr_10GbE_mosi : OUT t_mem_mosi;
reg_tr_10GbE_miso : IN t_mem_miso
);
@@ -115,7 +117,10 @@ ARCHITECTURE str OF mmm_aartfaac_fn_sdo IS
CONSTANT c_multi_reg_diag_db_adr_w : NATURAL := ceil_log2(c_nof_mesh_xcvrs* pow2(c_reg_diag_db_adr_w));
CONSTANT c_reg_tr_10GbE_adr_w : NATURAL := 13;
-
+ CONSTANT c_xaui_mosi_addr_w : NATURAL := 9; --2^9 = range of 512 addresses
+ CONSTANT c_max_nof_xaui_inst : NATURAL := 4;
+ CONSTANT c_reg_tr_xaui_addr_w : NATURAL := ceil_log2(c_max_nof_xaui_inst* pow2(c_xaui_mosi_addr_w)); -- 4* 512 = 2048 addresses -> 11 address bits.
+
SIGNAL i_mm_clk : STD_LOGIC := '1';
SIGNAL i_tse_clk : STD_LOGIC := '1';
SIGNAL i_dp_clk : STD_LOGIC := '1';
@@ -309,9 +314,6 @@ BEGIN
-- the_pio_debug_wave
out_port_from_the_pio_debug_wave => OPEN,
- -- the_pio_pps
- in_port_to_the_pio_pps => pin_pps,
-
-- the_pio_system_info: actually a avs_common_mm instance
coe_clk_export_from_the_pio_system_info => OPEN,
coe_reset_export_from_the_pio_system_info => OPEN,
@@ -360,6 +362,43 @@ BEGIN
coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- the_reg_mdio_0
+ coe_clk_export_from_the_reg_mdio_0 => OPEN,
+ coe_reset_export_from_the_reg_mdio_0 => OPEN,
+ coe_address_export_from_the_reg_mdio_0 => reg_mdio_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_mdio_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_mdio_0 => reg_mdio_mosi_arr(0).rd,
+ coe_readdata_export_to_the_reg_mdio_0 => reg_mdio_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_mdio_0 => reg_mdio_mosi_arr(0).wr,
+ coe_writedata_export_from_the_reg_mdio_0 => reg_mdio_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_mdio_1
+ coe_clk_export_from_the_reg_mdio_1 => OPEN,
+ coe_reset_export_from_the_reg_mdio_1 => OPEN,
+ coe_address_export_from_the_reg_mdio_1 => reg_mdio_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_mdio_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_mdio_1 => reg_mdio_mosi_arr(1).rd,
+ coe_readdata_export_to_the_reg_mdio_1 => reg_mdio_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_mdio_1 => reg_mdio_mosi_arr(1).wr,
+ coe_writedata_export_from_the_reg_mdio_1 => reg_mdio_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_mdio_2
+ coe_clk_export_from_the_reg_mdio_2 => OPEN,
+ coe_reset_export_from_the_reg_mdio_2 => OPEN,
+ coe_address_export_from_the_reg_mdio_2 => reg_mdio_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.reg_mdio_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_mdio_2 => reg_mdio_mosi_arr(2).rd,
+ coe_readdata_export_to_the_reg_mdio_2 => reg_mdio_miso_arr(2).rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_mdio_2 => reg_mdio_mosi_arr(2).wr,
+ coe_writedata_export_from_the_reg_mdio_2 => reg_mdio_mosi_arr(2).wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_tr_xaui
+ coe_clk_export_from_the_reg_tr_xaui => OPEN,
+ coe_reset_export_from_the_reg_tr_xaui => OPEN,
+ coe_address_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.address(c_reg_tr_xaui_addr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.rd,
+ coe_readdata_export_to_the_reg_tr_xaui => reg_tr_xaui_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_waitrequest_export_to_the_reg_tr_xaui => reg_tr_xaui_miso.waitrequest,
+ coe_write_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.wr,
+ coe_writedata_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
-- the_reg_tr_10GbE
coe_clk_export_from_the_reg_tr_10GbE => OPEN,
coe_reset_export_from_the_reg_tr_10GbE => OPEN,