From f134307036bc3a419d16bd0c7130f438ea3a08cc Mon Sep 17 00:00:00 2001
From: David Brouwer <dbrouwer@astron.nl>
Date: Mon, 6 Nov 2023 17:39:35 +0100
Subject: [PATCH] Added component description for ip_agi027_xxxx_ram_crk_cw.
---
.../memory/tech_memory_component_pkg.vhd | 23 +++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/libraries/technology/memory/tech_memory_component_pkg.vhd b/libraries/technology/memory/tech_memory_component_pkg.vhd
index 66421ed3eb..e28370e31b 100644
--- a/libraries/technology/memory/tech_memory_component_pkg.vhd
+++ b/libraries/technology/memory/tech_memory_component_pkg.vhd
@@ -593,6 +593,29 @@ package tech_memory_component_pkg is
);
end component;
+ component ip_agi027_xxxx_ram_crk_cw is
+ generic (
+ g_wr_adr_w : natural := 5;
+ g_wr_dat_w : natural := 32;
+ g_wr_nof_words : natural := 2**5;
+ g_rd_adr_w : natural := 4;
+ g_rd_dat_w : natural := 64;
+ g_rd_nof_words : natural := 2**4;
+ g_rd_latency : natural := 1; -- choose 1 or 2
+ g_init_file : string := "UNUSED"
+ );
+ port
+ (
+ data : in std_logic_vector(g_wr_dat_w - 1 downto 0);
+ wraddress : in std_logic_vector(g_wr_adr_w - 1 downto 0);
+ wrclk : in std_logic := '1';
+ wren : in std_logic := '0';
+ rdaddress : in std_logic_vector(g_rd_adr_w - 1 downto 0);
+ rdclk : in std_logic;
+ q : out std_logic_vector(g_rd_dat_w - 1 downto 0)
+ );
+ end component;
+
component ip_agi027_xxxx_ram_rw_rw is
generic (
g_inferred : boolean := false;
--
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