From f0f3ffd49653b5ca5b5919b46193755d6959fe2c Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Mon, 2 Mar 2020 16:28:40 +0100
Subject: [PATCH] Removed unused signal and removed latch
---
.../base/dp/src/vhdl/dp_fifo_fill_eop.vhd | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
index b4b591c923..535e1c1055 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
@@ -119,21 +119,23 @@ ARCHITECTURE rtl OF dp_fifo_fill_eop IS
SIGNAL i_src_out : t_dp_sosi;
SIGNAL nxt_src_out : t_dp_sosi;
- -- Signals for g_fifo_rl=1
- SIGNAL hold_src_in : t_dp_siso;
- SIGNAL pend_src_out : t_dp_sosi;
-
+ -- EOP clock domain crossing signals
SIGNAL reg_wr_eop_cnt : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL reg_rd_eop_cnt : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL wr_eop_done : STD_LOGIC;
SIGNAL wr_eop_new : STD_LOGIC;
- SIGNAL prev_snk_in_eop : STD_LOGIC;
SIGNAL rd_eop_new : STD_LOGIC;
SIGNAL wr_eop_busy : STD_LOGIC;
SIGNAL wr_eop_cnt : NATURAL := 0;
SIGNAL rd_eop_cnt : NATURAL := 0;
+
SIGNAL eop_cnt : INTEGER := 0;
- SIGNAL nxt_eop_cnt : INTEGER := 0;
+ SIGNAL nxt_eop_cnt : INTEGER := 0;
+
+ -- Signals for g_fifo_rl=1
+ SIGNAL hold_src_in : t_dp_siso;
+ SIGNAL pend_src_out : t_dp_sosi;
+
BEGIN
-- Output monitor FIFO filling
@@ -324,7 +326,7 @@ BEGIN
nxt_src_out.sop <= '0';
nxt_src_out.eop <= '0';
nxt_src_out.sync <= '0';
-
+ nxt_eop_cnt <= eop_cnt;
IF rd_eop_new = '1' THEN
nxt_eop_cnt <= eop_cnt + rd_eop_cnt;
END IF;
@@ -413,7 +415,7 @@ BEGIN
nxt_src_out.sop <= '0';
nxt_src_out.eop <= '0';
nxt_src_out.sync <= '0';
-
+ nxt_eop_cnt <= eop_cnt;
IF rd_eop_new = '1' THEN
nxt_eop_cnt <= eop_cnt + rd_eop_cnt;
END IF;
--
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