diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/lofar2_unb2b_filterbank.sdc b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/lofar2_unb2b_filterbank.sdc index a041aae6d83c1972821b3e27f333568006a8c93e..46111751707cc59f2c76e125f70af2409c25abb2 100644 --- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/lofar2_unb2b_filterbank.sdc +++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/lofar2_unb2b_filterbank.sdc @@ -98,7 +98,8 @@ set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_nat #-group [get_clocks {inst2|xcvr_pll_inst|xcvr_fpll_a10_0|tx_bonding_clocks[0]}] # false paths added for the jesd test design -set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|link_clk}] -set_false_path -from [get_clocks {*core_pll|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}] -set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|frame_clk}] -set_false_path -from [get_clocks {*core_pll|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}] +set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|link_clk}] +set_false_path -from [get_clocks {*iopll_0|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}] + +set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*u_ip_arria10_e1sg_jesd204b_rx_corepll_200MHz|iopll_0|frame_clk}] +set_false_path -from [get_clocks {*u_ip_arria10_e1sg_jesd204b_rx_corepll_200MHz|iopll_0|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]